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Merge tag 'efi-urgent' of git://git.kernel.org/pub/scm/linux/kernel/git/efi/efi into...
[mirror_ubuntu-artful-kernel.git] / drivers / usb / gadget / udc / atmel_usba_udc.c
CommitLineData
914a3f3b
HS		 1/*
2 * Driver for the Atmel USBA high speed USB device controller
3 *
4 * Copyright (C) 2005-2007 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/clk.h>
3280e675 11#include <linux/clk/at91_pmc.h>
914a3f3b
HS		 12#include <linux/module.h>
13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/io.h>
5a0e3ad6 16#include <linux/slab.h>
914a3f3b
HS		 17#include <linux/device.h>
18#include <linux/dma-mapping.h>
19#include <linux/list.h>
4747639f 20#include <linux/mfd/syscon.h>
914a3f3b 21#include <linux/platform_device.h>
4747639f 22#include <linux/regmap.h>
741d2558 23#include <linux/ctype.h>
914a3f3b
HS		 24#include <linux/usb/ch9.h>
25#include <linux/usb/gadget.h>
8d855317 26#include <linux/usb/atmel_usba_udc.h>
914a3f3b 27#include <linux/delay.h>
4a3ae932
JCPV		 28#include <linux/of.h>
29#include <linux/of_gpio.h>
914a3f3b 30
914a3f3b
HS		 31#include "atmel_usba_udc.h"
32
914a3f3b
HS		 33#ifdef CONFIG_USB_GADGET_DEBUG_FS
34#include <linux/debugfs.h>
35#include <linux/uaccess.h>
36
37static int queue_dbg_open(struct inode *inode, struct file *file)
38{
39 struct usba_ep *ep = inode->i_private;
40 struct usba_request *req, *req_copy;
41 struct list_head *queue_data;
42
43 queue_data = kmalloc(sizeof(*queue_data), GFP_KERNEL);
44 if (!queue_data)
45 return -ENOMEM;
46 INIT_LIST_HEAD(queue_data);
47
48 spin_lock_irq(&ep->udc->lock);
49 list_for_each_entry(req, &ep->queue, queue) {
4b8e1233 50 req_copy = kmemdup(req, sizeof(*req_copy), GFP_ATOMIC);
914a3f3b
HS		 51 if (!req_copy)
52 goto fail;
914a3f3b
HS		 53 list_add_tail(&req_copy->queue, queue_data);
54 }
55 spin_unlock_irq(&ep->udc->lock);
56
57 file->private_data = queue_data;
58 return 0;
59
60fail:
61 spin_unlock_irq(&ep->udc->lock);
62 list_for_each_entry_safe(req, req_copy, queue_data, queue) {
63 list_del(&req->queue);
64 kfree(req);
65 }
66 kfree(queue_data);
67 return -ENOMEM;
68}
69
70/*
71 * bbbbbbbb llllllll IZS sssss nnnn FDL\n\0
72 *
73 * b: buffer address
74 * l: buffer length
75 * I/i: interrupt/no interrupt
76 * Z/z: zero/no zero
77 * S/s: short ok/short not ok
78 * s: status
79 * n: nr_packets
80 * F/f: submitted/not submitted to FIFO
81 * D/d: using/not using DMA
82 * L/l: last transaction/not last transaction
83 */
84static ssize_t queue_dbg_read(struct file *file, char __user *buf,
85 size_t nbytes, loff_t *ppos)
86{
87 struct list_head *queue = file->private_data;
88 struct usba_request *req, *tmp_req;
89 size_t len, remaining, actual = 0;
90 char tmpbuf[38];
91
92 if (!access_ok(VERIFY_WRITE, buf, nbytes))
93 return -EFAULT;
94
5955102c 95 inode_lock(file_inode(file));
914a3f3b
HS		 96 list_for_each_entry_safe(req, tmp_req, queue, queue) {
97 len = snprintf(tmpbuf, sizeof(tmpbuf),
98 "%8p %08x %c%c%c %5d %c%c%c\n",
99 req->req.buf, req->req.length,
100 req->req.no_interrupt ? 'i' : 'I',
101 req->req.zero ? 'Z' : 'z',
102 req->req.short_not_ok ? 's' : 'S',
103 req->req.status,
104 req->submitted ? 'F' : 'f',
105 req->using_dma ? 'D' : 'd',
106 req->last_transaction ? 'L' : 'l');
107 len = min(len, sizeof(tmpbuf));
108 if (len > nbytes)
109 break;
110
111 list_del(&req->queue);
112 kfree(req);
113
114 remaining = __copy_to_user(buf, tmpbuf, len);
115 actual += len - remaining;
116 if (remaining)
117 break;
118
119 nbytes -= len;
120 buf += len;
121 }
5955102c 122 inode_unlock(file_inode(file));
914a3f3b
HS		 123
124 return actual;
125}
126
127static int queue_dbg_release(struct inode *inode, struct file *file)
128{
129 struct list_head *queue_data = file->private_data;
130 struct usba_request *req, *tmp_req;
131
132 list_for_each_entry_safe(req, tmp_req, queue_data, queue) {
133 list_del(&req->queue);
134 kfree(req);
135 }
136 kfree(queue_data);
137 return 0;
138}
139
140static int regs_dbg_open(struct inode *inode, struct file *file)
141{
142 struct usba_udc *udc;
143 unsigned int i;
144 u32 *data;
145 int ret = -ENOMEM;
146
5955102c 147 inode_lock(inode);
914a3f3b
HS		 148 udc = inode->i_private;
149 data = kmalloc(inode->i_size, GFP_KERNEL);
150 if (!data)
151 goto out;
152
153 spin_lock_irq(&udc->lock);
154 for (i = 0; i < inode->i_size / 4; i++)
a3dd3bef 155 data[i] = usba_io_readl(udc->regs + i * 4);
914a3f3b
HS		 156 spin_unlock_irq(&udc->lock);
157
158 file->private_data = data;
159 ret = 0;
160
161out:
5955102c 162 inode_unlock(inode);
914a3f3b
HS		 163
164 return ret;
165}
166
167static ssize_t regs_dbg_read(struct file *file, char __user *buf,
168 size_t nbytes, loff_t *ppos)
169{
496ad9aa 170 struct inode *inode = file_inode(file);
914a3f3b
HS		 171 int ret;
172
5955102c 173 inode_lock(inode);
914a3f3b
HS		 174 ret = simple_read_from_buffer(buf, nbytes, ppos,
175 file->private_data,
496ad9aa 176 file_inode(file)->i_size);
5955102c 177 inode_unlock(inode);
914a3f3b
HS		 178
179 return ret;
180}
181
182static int regs_dbg_release(struct inode *inode, struct file *file)
183{
184 kfree(file->private_data);
185 return 0;
186}
187
188const struct file_operations queue_dbg_fops = {
189 .owner = THIS_MODULE,
190 .open = queue_dbg_open,
191 .llseek = no_llseek,
192 .read = queue_dbg_read,
193 .release = queue_dbg_release,
194};
195
196const struct file_operations regs_dbg_fops = {
197 .owner = THIS_MODULE,
198 .open = regs_dbg_open,
199 .llseek = generic_file_llseek,
200 .read = regs_dbg_read,
201 .release = regs_dbg_release,
202};
203
204static void usba_ep_init_debugfs(struct usba_udc *udc,
205 struct usba_ep *ep)
206{
207 struct dentry *ep_root;
208
209 ep_root = debugfs_create_dir(ep->ep.name, udc->debugfs_root);
210 if (!ep_root)
211 goto err_root;
212 ep->debugfs_dir = ep_root;
213
214 ep->debugfs_queue = debugfs_create_file("queue", 0400, ep_root,
215 ep, &queue_dbg_fops);
216 if (!ep->debugfs_queue)
217 goto err_queue;
218
219 if (ep->can_dma) {
220 ep->debugfs_dma_status
221 = debugfs_create_u32("dma_status", 0400, ep_root,
222 &ep->last_dma_status);
223 if (!ep->debugfs_dma_status)
224 goto err_dma_status;
225 }
226 if (ep_is_control(ep)) {
227 ep->debugfs_state
228 = debugfs_create_u32("state", 0400, ep_root,
229 &ep->state);
230 if (!ep->debugfs_state)
231 goto err_state;
232 }
233
234 return;
235
236err_state:
237 if (ep->can_dma)
238 debugfs_remove(ep->debugfs_dma_status);
239err_dma_status:
240 debugfs_remove(ep->debugfs_queue);
241err_queue:
242 debugfs_remove(ep_root);
243err_root:
244 dev_err(&ep->udc->pdev->dev,
245 "failed to create debugfs directory for %s\n", ep->ep.name);
246}
247
248static void usba_ep_cleanup_debugfs(struct usba_ep *ep)
249{
250 debugfs_remove(ep->debugfs_queue);
251 debugfs_remove(ep->debugfs_dma_status);
252 debugfs_remove(ep->debugfs_state);
253 debugfs_remove(ep->debugfs_dir);
254 ep->debugfs_dma_status = NULL;
255 ep->debugfs_dir = NULL;
256}
257
258static void usba_init_debugfs(struct usba_udc *udc)
259{
260 struct dentry *root, *regs;
261 struct resource *regs_resource;
262
263 root = debugfs_create_dir(udc->gadget.name, NULL);
264 if (IS_ERR(root) || !root)
265 goto err_root;
266 udc->debugfs_root = root;
267
914a3f3b
HS		 268 regs_resource = platform_get_resource(udc->pdev, IORESOURCE_MEM,
269 CTRL_IOMEM_ID);
e59b4e91
DH		 270
271 if (regs_resource) {
272 regs = debugfs_create_file_size("regs", 0400, root, udc,
273 &regs_dbg_fops,
274 resource_size(regs_resource));
275 if (!regs)
276 goto err_regs;
277 udc->debugfs_regs = regs;
278 }
914a3f3b
HS		 279
280 usba_ep_init_debugfs(udc, to_usba_ep(udc->gadget.ep0));
281
282 return;
283
284err_regs:
285 debugfs_remove(root);
286err_root:
287 udc->debugfs_root = NULL;
288 dev_err(&udc->pdev->dev, "debugfs is not available\n");
289}
290
291static void usba_cleanup_debugfs(struct usba_udc *udc)
292{
293 usba_ep_cleanup_debugfs(to_usba_ep(udc->gadget.ep0));
294 debugfs_remove(udc->debugfs_regs);
295 debugfs_remove(udc->debugfs_root);
296 udc->debugfs_regs = NULL;
297 udc->debugfs_root = NULL;
298}
299#else
300static inline void usba_ep_init_debugfs(struct usba_udc *udc,
301 struct usba_ep *ep)
302{
303
304}
305
306static inline void usba_ep_cleanup_debugfs(struct usba_ep *ep)
307{
308
309}
310
311static inline void usba_init_debugfs(struct usba_udc *udc)
312{
313
314}
315
316static inline void usba_cleanup_debugfs(struct usba_udc *udc)
317{
318
319}
320#endif
321
741d2558
CB		 322static ushort fifo_mode;
323
324/* "modprobe ... fifo_mode=1" etc */
325module_param(fifo_mode, ushort, 0x0);
326MODULE_PARM_DESC(fifo_mode, "Endpoint configuration mode");
327
328/* mode 0 - uses autoconfig */
329
330/* mode 1 - fits in 8KB, generic max fifo configuration */
331static struct usba_fifo_cfg mode_1_cfg[] = {
332{ .hw_ep_num = 0, .fifo_size = 64, .nr_banks = 1, },
333{ .hw_ep_num = 1, .fifo_size = 1024, .nr_banks = 2, },
334{ .hw_ep_num = 2, .fifo_size = 1024, .nr_banks = 1, },
335{ .hw_ep_num = 3, .fifo_size = 1024, .nr_banks = 1, },
336{ .hw_ep_num = 4, .fifo_size = 1024, .nr_banks = 1, },
337{ .hw_ep_num = 5, .fifo_size = 1024, .nr_banks = 1, },
338{ .hw_ep_num = 6, .fifo_size = 1024, .nr_banks = 1, },
339};
340
341/* mode 2 - fits in 8KB, performance max fifo configuration */
342static struct usba_fifo_cfg mode_2_cfg[] = {
343{ .hw_ep_num = 0, .fifo_size = 64, .nr_banks = 1, },
344{ .hw_ep_num = 1, .fifo_size = 1024, .nr_banks = 3, },
345{ .hw_ep_num = 2, .fifo_size = 1024, .nr_banks = 2, },
346{ .hw_ep_num = 3, .fifo_size = 1024, .nr_banks = 2, },
347};
348
349/* mode 3 - fits in 8KB, mixed fifo configuration */
350static struct usba_fifo_cfg mode_3_cfg[] = {
351{ .hw_ep_num = 0, .fifo_size = 64, .nr_banks = 1, },
352{ .hw_ep_num = 1, .fifo_size = 1024, .nr_banks = 2, },
353{ .hw_ep_num = 2, .fifo_size = 512, .nr_banks = 2, },
354{ .hw_ep_num = 3, .fifo_size = 512, .nr_banks = 2, },
355{ .hw_ep_num = 4, .fifo_size = 512, .nr_banks = 2, },
356{ .hw_ep_num = 5, .fifo_size = 512, .nr_banks = 2, },
357{ .hw_ep_num = 6, .fifo_size = 512, .nr_banks = 2, },
358};
359
360/* mode 4 - fits in 8KB, custom fifo configuration */
361static struct usba_fifo_cfg mode_4_cfg[] = {
362{ .hw_ep_num = 0, .fifo_size = 64, .nr_banks = 1, },
363{ .hw_ep_num = 1, .fifo_size = 512, .nr_banks = 2, },
364{ .hw_ep_num = 2, .fifo_size = 512, .nr_banks = 2, },
365{ .hw_ep_num = 3, .fifo_size = 8, .nr_banks = 2, },
366{ .hw_ep_num = 4, .fifo_size = 512, .nr_banks = 2, },
367{ .hw_ep_num = 5, .fifo_size = 512, .nr_banks = 2, },
368{ .hw_ep_num = 6, .fifo_size = 16, .nr_banks = 2, },
369{ .hw_ep_num = 7, .fifo_size = 8, .nr_banks = 2, },
370{ .hw_ep_num = 8, .fifo_size = 8, .nr_banks = 2, },
371};
372/* Add additional configurations here */
373
374int usba_config_fifo_table(struct usba_udc *udc)
375{
376 int n;
377
378 switch (fifo_mode) {
379 default:
380 fifo_mode = 0;
381 case 0:
382 udc->fifo_cfg = NULL;
383 n = 0;
384 break;
385 case 1:
386 udc->fifo_cfg = mode_1_cfg;
387 n = ARRAY_SIZE(mode_1_cfg);
388 break;
389 case 2:
390 udc->fifo_cfg = mode_2_cfg;
391 n = ARRAY_SIZE(mode_2_cfg);
392 break;
393 case 3:
394 udc->fifo_cfg = mode_3_cfg;
395 n = ARRAY_SIZE(mode_3_cfg);
396 break;
397 case 4:
398 udc->fifo_cfg = mode_4_cfg;
399 n = ARRAY_SIZE(mode_4_cfg);
400 break;
401 }
402 DBG(DBG_HW, "Setup fifo_mode %d\n", fifo_mode);
403
404 return n;
405}
406
e3a912a1
BB		 407static inline u32 usba_int_enb_get(struct usba_udc *udc)
408{
409 return udc->int_enb_cache;
410}
411
412static inline void usba_int_enb_set(struct usba_udc *udc, u32 val)
413{
414 usba_writel(udc, INT_ENB, val);
415 udc->int_enb_cache = val;
416}
417
914a3f3b
HS		 418static int vbus_is_present(struct usba_udc *udc)
419{
472a6786 420 if (gpio_is_valid(udc->vbus_pin))
640e95ab 421 return gpio_get_value(udc->vbus_pin) ^ udc->vbus_pin_inverted;
914a3f3b
HS		 422
423 /* No Vbus detection: Assume always present */
424 return 1;
425}
426
3280e675 427static void toggle_bias(struct usba_udc *udc, int is_on)
e60c65d3 428{
3280e675
BB		 429 if (udc->errata && udc->errata->toggle_bias)
430 udc->errata->toggle_bias(udc, is_on);
e60c65d3
NF		 431}
432
258e2ddd
BB		 433static void generate_bias_pulse(struct usba_udc *udc)
434{
435 if (!udc->bias_pulse_needed)
436 return;
437
438 if (udc->errata && udc->errata->pulse_bias)
439 udc->errata->pulse_bias(udc);
440
441 udc->bias_pulse_needed = false;
442}
443
914a3f3b
HS		 444static void next_fifo_transaction(struct usba_ep *ep, struct usba_request *req)
445{
446 unsigned int transaction_len;
447
448 transaction_len = req->req.length - req->req.actual;
449 req->last_transaction = 1;
450 if (transaction_len > ep->ep.maxpacket) {
451 transaction_len = ep->ep.maxpacket;
452 req->last_transaction = 0;
453 } else if (transaction_len == ep->ep.maxpacket && req->req.zero)
454 req->last_transaction = 0;
455
456 DBG(DBG_QUEUE, "%s: submit_transaction, req %p (length %d)%s\n",
457 ep->ep.name, req, transaction_len,
458 req->last_transaction ? ", done" : "");
459
5d4c2707 460 memcpy_toio(ep->fifo, req->req.buf + req->req.actual, transaction_len);
914a3f3b
HS		 461 usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
462 req->req.actual += transaction_len;
463}
464
465static void submit_request(struct usba_ep *ep, struct usba_request *req)
466{
467 DBG(DBG_QUEUE, "%s: submit_request: req %p (length %d)\n",
468 ep->ep.name, req, req->req.length);
469
470 req->req.actual = 0;
471 req->submitted = 1;
472
473 if (req->using_dma) {
474 if (req->req.length == 0) {
475 usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY);
476 return;
477 }
478
479 if (req->req.zero)
480 usba_ep_writel(ep, CTL_ENB, USBA_SHORT_PACKET);
481 else
482 usba_ep_writel(ep, CTL_DIS, USBA_SHORT_PACKET);
483
484 usba_dma_writel(ep, ADDRESS, req->req.dma);
485 usba_dma_writel(ep, CONTROL, req->ctrl);
486 } else {
487 next_fifo_transaction(ep, req);
488 if (req->last_transaction) {
489 usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY);
490 usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE);
491 } else {
492 usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
493 usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY);
494 }
495 }
496}
497
498static void submit_next_request(struct usba_ep *ep)
499{
500 struct usba_request *req;
501
502 if (list_empty(&ep->queue)) {
503 usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY | USBA_RX_BK_RDY);
504 return;
505 }
506
507 req = list_entry(ep->queue.next, struct usba_request, queue);
508 if (!req->submitted)
509 submit_request(ep, req);
510}
511
512static void send_status(struct usba_udc *udc, struct usba_ep *ep)
513{
514 ep->state = STATUS_STAGE_IN;
515 usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
516 usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE);
517}
518
519static void receive_data(struct usba_ep *ep)
520{
521 struct usba_udc *udc = ep->udc;
522 struct usba_request *req;
523 unsigned long status;
524 unsigned int bytecount, nr_busy;
525 int is_complete = 0;
526
527 status = usba_ep_readl(ep, STA);
528 nr_busy = USBA_BFEXT(BUSY_BANKS, status);
529
530 DBG(DBG_QUEUE, "receive data: nr_busy=%u\n", nr_busy);
531
532 while (nr_busy > 0) {
533 if (list_empty(&ep->queue)) {
534 usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
535 break;
536 }
537 req = list_entry(ep->queue.next,
538 struct usba_request, queue);
539
540 bytecount = USBA_BFEXT(BYTE_COUNT, status);
541
542 if (status & (1 << 31))
543 is_complete = 1;
544 if (req->req.actual + bytecount >= req->req.length) {
545 is_complete = 1;
546 bytecount = req->req.length - req->req.actual;
547 }
548
5d4c2707 549 memcpy_fromio(req->req.buf + req->req.actual,
914a3f3b
HS		 550 ep->fifo, bytecount);
551 req->req.actual += bytecount;
552
553 usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
554
555 if (is_complete) {
556 DBG(DBG_QUEUE, "%s: request done\n", ep->ep.name);
557 req->req.status = 0;
558 list_del_init(&req->queue);
559 usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
560 spin_unlock(&udc->lock);
304f7e5e 561 usb_gadget_giveback_request(&ep->ep, &req->req);
914a3f3b
HS		 562 spin_lock(&udc->lock);
563 }
564
565 status = usba_ep_readl(ep, STA);
566 nr_busy = USBA_BFEXT(BUSY_BANKS, status);
567
568 if (is_complete && ep_is_control(ep)) {
569 send_status(udc, ep);
570 break;
571 }
572 }
573}
574
575static void
576request_complete(struct usba_ep *ep, struct usba_request *req, int status)
577{
578 struct usba_udc *udc = ep->udc;
579
580 WARN_ON(!list_empty(&req->queue));
581
582 if (req->req.status == -EINPROGRESS)
583 req->req.status = status;
584
1bda9df8
FB		 585 if (req->using_dma)
586 usb_gadget_unmap_request(&udc->gadget, &req->req, ep->is_in);
914a3f3b
HS		 587
588 DBG(DBG_GADGET | DBG_REQ,
589 "%s: req %p complete: status %d, actual %u\n",
590 ep->ep.name, req, req->req.status, req->req.actual);
591
592 spin_unlock(&udc->lock);
304f7e5e 593 usb_gadget_giveback_request(&ep->ep, &req->req);
914a3f3b
HS		 594 spin_lock(&udc->lock);
595}
596
597static void
598request_complete_list(struct usba_ep *ep, struct list_head *list, int status)
599{
600 struct usba_request *req, *tmp_req;
601
602 list_for_each_entry_safe(req, tmp_req, list, queue) {
603 list_del_init(&req->queue);
604 request_complete(ep, req, status);
605 }
606}
607
608static int
609usba_ep_enable(struct usb_ep *_ep, const struct usb_endpoint_descriptor *desc)
610{
611 struct usba_ep *ep = to_usba_ep(_ep);
612 struct usba_udc *udc = ep->udc;
42428202 613 unsigned long flags, maxpacket;
914a3f3b
HS		 614 unsigned int nr_trans;
615
616 DBG(DBG_GADGET, "%s: ep_enable: desc=%p\n", ep->ep.name, desc);
617
44fbbf1f 618 maxpacket = usb_endpoint_maxp(desc);
914a3f3b
HS		 619
620 if (((desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK) != ep->index)
621 || ep->index == 0
622 || desc->bDescriptorType != USB_DT_ENDPOINT
623 || maxpacket == 0
624 || maxpacket > ep->fifo_size) {
625 DBG(DBG_ERR, "ep_enable: Invalid argument");
626 return -EINVAL;
627 }
628
629 ep->is_isoc = 0;
630 ep->is_in = 0;
631
741d2558 632 DBG(DBG_ERR, "%s: EPT_CFG = 0x%lx (maxpacket = %lu)\n",
42428202 633 ep->ep.name, ep->ept_cfg, maxpacket);
914a3f3b 634
71de6b63 635 if (usb_endpoint_dir_in(desc)) {
914a3f3b 636 ep->is_in = 1;
741d2558 637 ep->ept_cfg |= USBA_EPT_DIR_IN;
914a3f3b
HS		 638 }
639
71de6b63 640 switch (usb_endpoint_type(desc)) {
914a3f3b 641 case USB_ENDPOINT_XFER_CONTROL:
741d2558 642 ep->ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_CONTROL);
914a3f3b
HS		 643 break;
644 case USB_ENDPOINT_XFER_ISOC:
645 if (!ep->can_isoc) {
646 DBG(DBG_ERR, "ep_enable: %s is not isoc capable\n",
647 ep->ep.name);
648 return -EINVAL;
649 }
650
651 /*
652 * Bits 11:12 specify number of _additional_
653 * transactions per microframe.
654 */
f0419d9f 655 nr_trans = usb_endpoint_maxp_mult(desc);
914a3f3b
HS		 656 if (nr_trans > 3)
657 return -EINVAL;
658
659 ep->is_isoc = 1;
741d2558
CB		 660 ep->ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_ISO);
661 ep->ept_cfg |= USBA_BF(NB_TRANS, nr_trans);
914a3f3b 662
914a3f3b
HS		 663 break;
664 case USB_ENDPOINT_XFER_BULK:
741d2558 665 ep->ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK);
914a3f3b
HS		 666 break;
667 case USB_ENDPOINT_XFER_INT:
741d2558 668 ep->ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_INT);
914a3f3b
HS		 669 break;
670 }
671
672 spin_lock_irqsave(&ep->udc->lock, flags);
673
978def1c 674 ep->ep.desc = desc;
914a3f3b
HS		 675 ep->ep.maxpacket = maxpacket;
676
741d2558 677 usba_ep_writel(ep, CFG, ep->ept_cfg);
914a3f3b
HS		 678 usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE);
679
680 if (ep->can_dma) {
681 u32 ctrl;
682
e3a912a1
BB		 683 usba_int_enb_set(udc, usba_int_enb_get(udc) |
684 USBA_BF(EPT_INT, 1 << ep->index) |
685 USBA_BF(DMA_INT, 1 << ep->index));
914a3f3b
HS		 686 ctrl = USBA_AUTO_VALID | USBA_INTDIS_DMA;
687 usba_ep_writel(ep, CTL_ENB, ctrl);
688 } else {
e3a912a1
BB		 689 usba_int_enb_set(udc, usba_int_enb_get(udc) |
690 USBA_BF(EPT_INT, 1 << ep->index));
914a3f3b
HS		 691 }
692
693 spin_unlock_irqrestore(&udc->lock, flags);
694
695 DBG(DBG_HW, "EPT_CFG%d after init: %#08lx\n", ep->index,
696 (unsigned long)usba_ep_readl(ep, CFG));
697 DBG(DBG_HW, "INT_ENB after init: %#08lx\n",
e3a912a1 698 (unsigned long)usba_int_enb_get(udc));
914a3f3b
HS		 699
700 return 0;
701}
702
703static int usba_ep_disable(struct usb_ep *_ep)
704{
705 struct usba_ep *ep = to_usba_ep(_ep);
706 struct usba_udc *udc = ep->udc;
707 LIST_HEAD(req_list);
708 unsigned long flags;
709
710 DBG(DBG_GADGET, "ep_disable: %s\n", ep->ep.name);
711
712 spin_lock_irqsave(&udc->lock, flags);
713
978def1c 714 if (!ep->ep.desc) {
914a3f3b 715 spin_unlock_irqrestore(&udc->lock, flags);
40517707
DB		 716 /* REVISIT because this driver disables endpoints in
717 * reset_all_endpoints() before calling disconnect(),
718 * most gadget drivers would trigger this non-error ...
719 */
720 if (udc->gadget.speed != USB_SPEED_UNKNOWN)
721 DBG(DBG_ERR, "ep_disable: %s not enabled\n",
722 ep->ep.name);
914a3f3b
HS		 723 return -EINVAL;
724 }
f9c56cdd 725 ep->ep.desc = NULL;
914a3f3b
HS		 726
727 list_splice_init(&ep->queue, &req_list);
728 if (ep->can_dma) {
729 usba_dma_writel(ep, CONTROL, 0);
730 usba_dma_writel(ep, ADDRESS, 0);
731 usba_dma_readl(ep, STATUS);
732 }
733 usba_ep_writel(ep, CTL_DIS, USBA_EPT_ENABLE);
e3a912a1
BB		 734 usba_int_enb_set(udc, usba_int_enb_get(udc) &
735 ~USBA_BF(EPT_INT, 1 << ep->index));
914a3f3b
HS		 736
737 request_complete_list(ep, &req_list, -ESHUTDOWN);
738
739 spin_unlock_irqrestore(&udc->lock, flags);
740
741 return 0;
742}
743
744static struct usb_request *
745usba_ep_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
746{
747 struct usba_request *req;
748
749 DBG(DBG_GADGET, "ep_alloc_request: %p, 0x%x\n", _ep, gfp_flags);
750
751 req = kzalloc(sizeof(*req), gfp_flags);
752 if (!req)
753 return NULL;
754
755 INIT_LIST_HEAD(&req->queue);
914a3f3b
HS		 756
757 return &req->req;
758}
759
760static void
761usba_ep_free_request(struct usb_ep *_ep, struct usb_request *_req)
762{
763 struct usba_request *req = to_usba_req(_req);
764
765 DBG(DBG_GADGET, "ep_free_request: %p, %p\n", _ep, _req);
766
767 kfree(req);
768}
769
770static int queue_dma(struct usba_udc *udc, struct usba_ep *ep,
771 struct usba_request *req, gfp_t gfp_flags)
772{
773 unsigned long flags;
774 int ret;
775
7a64c728
FB		 776 DBG(DBG_DMA, "%s: req l/%u d/%pad %c%c%c\n",
777 ep->ep.name, req->req.length, &req->req.dma,
914a3f3b
HS		 778 req->req.zero ? 'Z' : 'z',
779 req->req.short_not_ok ? 'S' : 's',
780 req->req.no_interrupt ? 'I' : 'i');
781
782 if (req->req.length > 0x10000) {
783 /* Lengths from 0 to 65536 (inclusive) are supported */
784 DBG(DBG_ERR, "invalid request length %u\n", req->req.length);
785 return -EINVAL;
786 }
787
1bda9df8
FB		 788 ret = usb_gadget_map_request(&udc->gadget, &req->req, ep->is_in);
789 if (ret)
790 return ret;
914a3f3b 791
1bda9df8 792 req->using_dma = 1;
914a3f3b
HS		 793 req->ctrl = USBA_BF(DMA_BUF_LEN, req->req.length)
794 | USBA_DMA_CH_EN | USBA_DMA_END_BUF_IE
f40afddd 795 | USBA_DMA_END_BUF_EN;
914a3f3b 796
f40afddd
BS		 797 if (!ep->is_in)
798 req->ctrl |= USBA_DMA_END_TR_EN | USBA_DMA_END_TR_IE;
914a3f3b
HS		 799
800 /*
801 * Add this request to the queue and submit for DMA if
802 * possible. Check if we're still alive first -- we may have
803 * received a reset since last time we checked.
804 */
805 ret = -ESHUTDOWN;
806 spin_lock_irqsave(&udc->lock, flags);
978def1c 807 if (ep->ep.desc) {
914a3f3b
HS		 808 if (list_empty(&ep->queue))
809 submit_request(ep, req);
810
811 list_add_tail(&req->queue, &ep->queue);
812 ret = 0;
813 }
814 spin_unlock_irqrestore(&udc->lock, flags);
815
816 return ret;
817}
818
819static int
820usba_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
821{
822 struct usba_request *req = to_usba_req(_req);
823 struct usba_ep *ep = to_usba_ep(_ep);
824 struct usba_udc *udc = ep->udc;
825 unsigned long flags;
826 int ret;
827
828 DBG(DBG_GADGET | DBG_QUEUE | DBG_REQ, "%s: queue req %p, len %u\n",
829 ep->ep.name, req, _req->length);
830
978def1c
IS		 831 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN ||
832 !ep->ep.desc)
914a3f3b
HS		 833 return -ESHUTDOWN;
834
835 req->submitted = 0;
836 req->using_dma = 0;
837 req->last_transaction = 0;
838
839 _req->status = -EINPROGRESS;
840 _req->actual = 0;
841
842 if (ep->can_dma)
843 return queue_dma(udc, ep, req, gfp_flags);
844
845 /* May have received a reset since last time we checked */
846 ret = -ESHUTDOWN;
847 spin_lock_irqsave(&udc->lock, flags);
978def1c 848 if (ep->ep.desc) {
914a3f3b
HS		 849 list_add_tail(&req->queue, &ep->queue);
850
f42706c9
MF		 851 if ((!ep_is_control(ep) && ep->is_in) ||
852 (ep_is_control(ep)
914a3f3b
HS		 853 && (ep->state == DATA_STAGE_IN
854 || ep->state == STATUS_STAGE_IN)))
855 usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY);
856 else
857 usba_ep_writel(ep, CTL_ENB, USBA_RX_BK_RDY);
858 ret = 0;
859 }
860 spin_unlock_irqrestore(&udc->lock, flags);
861
862 return ret;
863}
864
865static void
866usba_update_req(struct usba_ep *ep, struct usba_request *req, u32 status)
867{
868 req->req.actual = req->req.length - USBA_BFEXT(DMA_BUF_LEN, status);
869}
870
871static int stop_dma(struct usba_ep *ep, u32 *pstatus)
872{
873 unsigned int timeout;
874 u32 status;
875
876 /*
877 * Stop the DMA controller. When writing both CH_EN
878 * and LINK to 0, the other bits are not affected.
879 */
880 usba_dma_writel(ep, CONTROL, 0);
881
882 /* Wait for the FIFO to empty */
883 for (timeout = 40; timeout; --timeout) {
884 status = usba_dma_readl(ep, STATUS);
885 if (!(status & USBA_DMA_CH_EN))
886 break;
887 udelay(1);
888 }
889
890 if (pstatus)
891 *pstatus = status;
892
893 if (timeout == 0) {
894 dev_err(&ep->udc->pdev->dev,
895 "%s: timed out waiting for DMA FIFO to empty\n",
896 ep->ep.name);
897 return -ETIMEDOUT;
898 }
899
900 return 0;
901}
902
903static int usba_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
904{
905 struct usba_ep *ep = to_usba_ep(_ep);
906 struct usba_udc *udc = ep->udc;
5fb694f9 907 struct usba_request *req;
914a3f3b
HS		 908 unsigned long flags;
909 u32 status;
910
911 DBG(DBG_GADGET | DBG_QUEUE, "ep_dequeue: %s, req %p\n",
912 ep->ep.name, req);
913
914 spin_lock_irqsave(&udc->lock, flags);
915
5fb694f9
SW		 916 list_for_each_entry(req, &ep->queue, queue) {
917 if (&req->req == _req)
918 break;
919 }
920
921 if (&req->req != _req) {
922 spin_unlock_irqrestore(&udc->lock, flags);
923 return -EINVAL;
924 }
925
914a3f3b
HS		 926 if (req->using_dma) {
927 /*
928 * If this request is currently being transferred,
929 * stop the DMA controller and reset the FIFO.
930 */
931 if (ep->queue.next == &req->queue) {
932 status = usba_dma_readl(ep, STATUS);
933 if (status & USBA_DMA_CH_EN)
934 stop_dma(ep, &status);
935
936#ifdef CONFIG_USB_GADGET_DEBUG_FS
937 ep->last_dma_status = status;
938#endif
939
940 usba_writel(udc, EPT_RST, 1 << ep->index);
941
942 usba_update_req(ep, req, status);
943 }
944 }
945
946 /*
947 * Errors should stop the queue from advancing until the
948 * completion function returns.
949 */
950 list_del_init(&req->queue);
951
952 request_complete(ep, req, -ECONNRESET);
953
954 /* Process the next request if any */
955 submit_next_request(ep);
956 spin_unlock_irqrestore(&udc->lock, flags);
957
958 return 0;
959}
960
961static int usba_ep_set_halt(struct usb_ep *_ep, int value)
962{
963 struct usba_ep *ep = to_usba_ep(_ep);
964 struct usba_udc *udc = ep->udc;
965 unsigned long flags;
966 int ret = 0;
967
968 DBG(DBG_GADGET, "endpoint %s: %s HALT\n", ep->ep.name,
969 value ? "set" : "clear");
970
978def1c 971 if (!ep->ep.desc) {
914a3f3b
HS		 972 DBG(DBG_ERR, "Attempted to halt uninitialized ep %s\n",
973 ep->ep.name);
974 return -ENODEV;
975 }
976 if (ep->is_isoc) {
977 DBG(DBG_ERR, "Attempted to halt isochronous ep %s\n",
978 ep->ep.name);
979 return -ENOTTY;
980 }
981
982 spin_lock_irqsave(&udc->lock, flags);
983
984 /*
985 * We can't halt IN endpoints while there are still data to be
986 * transferred
987 */
988 if (!list_empty(&ep->queue)
989 || ((value && ep->is_in && (usba_ep_readl(ep, STA)
990 & USBA_BF(BUSY_BANKS, -1L))))) {
991 ret = -EAGAIN;
992 } else {
993 if (value)
994 usba_ep_writel(ep, SET_STA, USBA_FORCE_STALL);
995 else
996 usba_ep_writel(ep, CLR_STA,
997 USBA_FORCE_STALL | USBA_TOGGLE_CLR);
998 usba_ep_readl(ep, STA);
999 }
1000
1001 spin_unlock_irqrestore(&udc->lock, flags);
1002
1003 return ret;
1004}
1005
1006static int usba_ep_fifo_status(struct usb_ep *_ep)
1007{
1008 struct usba_ep *ep = to_usba_ep(_ep);
1009
1010 return USBA_BFEXT(BYTE_COUNT, usba_ep_readl(ep, STA));
1011}
1012
1013static void usba_ep_fifo_flush(struct usb_ep *_ep)
1014{
1015 struct usba_ep *ep = to_usba_ep(_ep);
1016 struct usba_udc *udc = ep->udc;
1017
1018 usba_writel(udc, EPT_RST, 1 << ep->index);
1019}
1020
1021static const struct usb_ep_ops usba_ep_ops = {
1022 .enable = usba_ep_enable,
1023 .disable = usba_ep_disable,
1024 .alloc_request = usba_ep_alloc_request,
1025 .free_request = usba_ep_free_request,
1026 .queue = usba_ep_queue,
1027 .dequeue = usba_ep_dequeue,
1028 .set_halt = usba_ep_set_halt,
1029 .fifo_status = usba_ep_fifo_status,
1030 .fifo_flush = usba_ep_fifo_flush,
1031};
1032
1033static int usba_udc_get_frame(struct usb_gadget *gadget)
1034{
1035 struct usba_udc *udc = to_usba_udc(gadget);
1036
1037 return USBA_BFEXT(FRAME_NUMBER, usba_readl(udc, FNUM));
1038}
1039
58ed7b94
HS		 1040static int usba_udc_wakeup(struct usb_gadget *gadget)
1041{
1042 struct usba_udc *udc = to_usba_udc(gadget);
1043 unsigned long flags;
1044 u32 ctrl;
1045 int ret = -EINVAL;
1046
1047 spin_lock_irqsave(&udc->lock, flags);
1048 if (udc->devstatus & (1 << USB_DEVICE_REMOTE_WAKEUP)) {
1049 ctrl = usba_readl(udc, CTRL);
1050 usba_writel(udc, CTRL, ctrl | USBA_REMOTE_WAKE_UP);
1051 ret = 0;
1052 }
1053 spin_unlock_irqrestore(&udc->lock, flags);
1054
1055 return ret;
1056}
1057
1058static int
1059usba_udc_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered)
1060{
1061 struct usba_udc *udc = to_usba_udc(gadget);
1062 unsigned long flags;
1063
d618c368 1064 gadget->is_selfpowered = (is_selfpowered != 0);
58ed7b94
HS		 1065 spin_lock_irqsave(&udc->lock, flags);
1066 if (is_selfpowered)
1067 udc->devstatus |= 1 << USB_DEVICE_SELF_POWERED;
1068 else
1069 udc->devstatus &= ~(1 << USB_DEVICE_SELF_POWERED);
1070 spin_unlock_irqrestore(&udc->lock, flags);
1071
1072 return 0;
1073}
1074
d809f78f
SAS		 1075static int atmel_usba_start(struct usb_gadget *gadget,
1076 struct usb_gadget_driver *driver);
22835b80
FB		 1077static int atmel_usba_stop(struct usb_gadget *gadget);
1078
741d2558
CB		 1079static struct usb_ep *atmel_usba_match_ep(
1080 struct usb_gadget *gadget,
1081 struct usb_endpoint_descriptor *desc,
1082 struct usb_ss_ep_comp_descriptor *ep_comp
1083)
1084{
1085 struct usb_ep *_ep;
1086 struct usba_ep *ep;
1087
1088 /* Look at endpoints until an unclaimed one looks usable */
1089 list_for_each_entry(_ep, &gadget->ep_list, ep_list) {
1090 if (usb_gadget_ep_match_desc(gadget, _ep, desc, ep_comp))
1091 goto found_ep;
1092 }
1093 /* Fail */
1094 return NULL;
1095
1096found_ep:
1097
1098 if (fifo_mode == 0) {
1099 /* Optimize hw fifo size based on ep type and other info */
1100 ep = to_usba_ep(_ep);
1101
1102 switch (usb_endpoint_type(desc)) {
1103
1104 case USB_ENDPOINT_XFER_CONTROL:
1105 break;
1106
1107 case USB_ENDPOINT_XFER_ISOC:
1108 ep->fifo_size = 1024;
1109 ep->nr_banks = 2;
1110 break;
1111
1112 case USB_ENDPOINT_XFER_BULK:
1113 ep->fifo_size = 512;
1114 ep->nr_banks = 1;
1115 break;
1116
1117 case USB_ENDPOINT_XFER_INT:
1118 if (desc->wMaxPacketSize == 0)
1119 ep->fifo_size =
1120 roundup_pow_of_two(_ep->maxpacket_limit);
1121 else
1122 ep->fifo_size =
1123 roundup_pow_of_two(le16_to_cpu(desc->wMaxPacketSize));
1124 ep->nr_banks = 1;
1125 break;
1126 }
1127
1128 /* It might be a little bit late to set this */
1129 usb_ep_set_maxpacket_limit(&ep->ep, ep->fifo_size);
1130
1131 /* Generate ept_cfg basd on FIFO size and number of banks */
1132 if (ep->fifo_size <= 8)
1133 ep->ept_cfg = USBA_BF(EPT_SIZE, USBA_EPT_SIZE_8);
1134 else
1135 /* LSB is bit 1, not 0 */
1136 ep->ept_cfg =
1137 USBA_BF(EPT_SIZE, fls(ep->fifo_size - 1) - 3);
1138
1139 ep->ept_cfg |= USBA_BF(BK_NUMBER, ep->nr_banks);
1140
1141 ep->udc->configured_ep++;
1142 }
1143
1144return _ep;
1145}
1146
914a3f3b 1147static const struct usb_gadget_ops usba_udc_ops = {
58ed7b94
HS		 1148 .get_frame = usba_udc_get_frame,
1149 .wakeup = usba_udc_wakeup,
1150 .set_selfpowered = usba_udc_set_selfpowered,
d809f78f
SAS		 1151 .udc_start = atmel_usba_start,
1152 .udc_stop = atmel_usba_stop,
741d2558 1153 .match_ep = atmel_usba_match_ep,
914a3f3b
HS		 1154};
1155
914a3f3b
HS		 1156static struct usb_endpoint_descriptor usba_ep0_desc = {
1157 .bLength = USB_DT_ENDPOINT_SIZE,
1158 .bDescriptorType = USB_DT_ENDPOINT,
1159 .bEndpointAddress = 0,
1160 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
551509d2 1161 .wMaxPacketSize = cpu_to_le16(64),
914a3f3b
HS		 1162 /* FIXME: I have no idea what to put here */
1163 .bInterval = 1,
1164};
1165
5056ee83 1166static struct usb_gadget usba_gadget_template = {
e8f2ea39
JCPV		 1167 .ops = &usba_udc_ops,
1168 .max_speed = USB_SPEED_HIGH,
1169 .name = "atmel_usba_udc",
914a3f3b
HS		 1170};
1171
1172/*
1173 * Called with interrupts disabled and udc->lock held.
1174 */
1175static void reset_all_endpoints(struct usba_udc *udc)
1176{
1177 struct usba_ep *ep;
1178 struct usba_request *req, *tmp_req;
1179
1180 usba_writel(udc, EPT_RST, ~0UL);
1181
1182 ep = to_usba_ep(udc->gadget.ep0);
1183 list_for_each_entry_safe(req, tmp_req, &ep->queue, queue) {
1184 list_del_init(&req->queue);
1185 request_complete(ep, req, -ECONNRESET);
1186 }
914a3f3b
HS		 1187}
1188
1189static struct usba_ep *get_ep_by_addr(struct usba_udc *udc, u16 wIndex)
1190{
1191 struct usba_ep *ep;
1192
1193 if ((wIndex & USB_ENDPOINT_NUMBER_MASK) == 0)
1194 return to_usba_ep(udc->gadget.ep0);
1195
1196 list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list) {
1197 u8 bEndpointAddress;
1198
978def1c 1199 if (!ep->ep.desc)
914a3f3b 1200 continue;
978def1c 1201 bEndpointAddress = ep->ep.desc->bEndpointAddress;
914a3f3b
HS		 1202 if ((wIndex ^ bEndpointAddress) & USB_DIR_IN)
1203 continue;
1204 if ((bEndpointAddress & USB_ENDPOINT_NUMBER_MASK)
1205 == (wIndex & USB_ENDPOINT_NUMBER_MASK))
1206 return ep;
1207 }
1208
1209 return NULL;
1210}
1211
1212/* Called with interrupts disabled and udc->lock held */
1213static inline void set_protocol_stall(struct usba_udc *udc, struct usba_ep *ep)
1214{
1215 usba_ep_writel(ep, SET_STA, USBA_FORCE_STALL);
1216 ep->state = WAIT_FOR_SETUP;
1217}
1218
1219static inline int is_stalled(struct usba_udc *udc, struct usba_ep *ep)
1220{
1221 if (usba_ep_readl(ep, STA) & USBA_FORCE_STALL)
1222 return 1;
1223 return 0;
1224}
1225
1226static inline void set_address(struct usba_udc *udc, unsigned int addr)
1227{
1228 u32 regval;
1229
1230 DBG(DBG_BUS, "setting address %u...\n", addr);
1231 regval = usba_readl(udc, CTRL);
1232 regval = USBA_BFINS(DEV_ADDR, addr, regval);
1233 usba_writel(udc, CTRL, regval);
1234}
1235
1236static int do_test_mode(struct usba_udc *udc)
1237{
1238 static const char test_packet_buffer[] = {
1239 /* JKJKJKJK * 9 */
1240 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1241 /* JJKKJJKK * 8 */
1242 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA,
1243 /* JJKKJJKK * 8 */
1244 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE,
1245 /* JJJJJJJKKKKKKK * 8 */
1246 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
1247 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
1248 /* JJJJJJJK * 8 */
1249 0x7F, 0xBF, 0xDF, 0xEF, 0xF7, 0xFB, 0xFD,
1250 /* {JKKKKKKK * 10}, JK */
1251 0xFC, 0x7E, 0xBF, 0xDF, 0xEF, 0xF7, 0xFB, 0xFD, 0x7E
1252 };
1253 struct usba_ep *ep;
1254 struct device *dev = &udc->pdev->dev;
1255 int test_mode;
1256
1257 test_mode = udc->test_mode;
1258
1259 /* Start from a clean slate */
1260 reset_all_endpoints(udc);
1261
1262 switch (test_mode) {
1263 case 0x0100:
1264 /* Test_J */
1265 usba_writel(udc, TST, USBA_TST_J_MODE);
1266 dev_info(dev, "Entering Test_J mode...\n");
1267 break;
1268 case 0x0200:
1269 /* Test_K */
1270 usba_writel(udc, TST, USBA_TST_K_MODE);
1271 dev_info(dev, "Entering Test_K mode...\n");
1272 break;
1273 case 0x0300:
1274 /*
1275 * Test_SE0_NAK: Force high-speed mode and set up ep0
1276 * for Bulk IN transfers
1277 */
68522de7 1278 ep = &udc->usba_ep[0];
914a3f3b
HS		 1279 usba_writel(udc, TST,
1280 USBA_BF(SPEED_CFG, USBA_SPEED_CFG_FORCE_HIGH));
1281 usba_ep_writel(ep, CFG,
1282 USBA_BF(EPT_SIZE, USBA_EPT_SIZE_64)
1283 | USBA_EPT_DIR_IN
1284 | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK)
1285 | USBA_BF(BK_NUMBER, 1));
1286 if (!(usba_ep_readl(ep, CFG) & USBA_EPT_MAPPED)) {
1287 set_protocol_stall(udc, ep);
1288 dev_err(dev, "Test_SE0_NAK: ep0 not mapped\n");
1289 } else {
1290 usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE);
1291 dev_info(dev, "Entering Test_SE0_NAK mode...\n");
1292 }
1293 break;
1294 case 0x0400:
1295 /* Test_Packet */
68522de7 1296 ep = &udc->usba_ep[0];
914a3f3b
HS		 1297 usba_ep_writel(ep, CFG,
1298 USBA_BF(EPT_SIZE, USBA_EPT_SIZE_64)
1299 | USBA_EPT_DIR_IN
1300 | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK)
1301 | USBA_BF(BK_NUMBER, 1));
1302 if (!(usba_ep_readl(ep, CFG) & USBA_EPT_MAPPED)) {
1303 set_protocol_stall(udc, ep);
1304 dev_err(dev, "Test_Packet: ep0 not mapped\n");
1305 } else {
1306 usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE);
1307 usba_writel(udc, TST, USBA_TST_PKT_MODE);
5d4c2707 1308 memcpy_toio(ep->fifo, test_packet_buffer,
914a3f3b
HS		 1309 sizeof(test_packet_buffer));
1310 usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
1311 dev_info(dev, "Entering Test_Packet mode...\n");
1312 }
1313 break;
1314 default:
1315 dev_err(dev, "Invalid test mode: 0x%04x\n", test_mode);
1316 return -EINVAL;
1317 }
1318
1319 return 0;
1320}
1321
1322/* Avoid overly long expressions */
1323static inline bool feature_is_dev_remote_wakeup(struct usb_ctrlrequest *crq)
1324{
551509d2 1325 if (crq->wValue == cpu_to_le16(USB_DEVICE_REMOTE_WAKEUP))
914a3f3b
HS		 1326 return true;
1327 return false;
1328}
1329
1330static inline bool feature_is_dev_test_mode(struct usb_ctrlrequest *crq)
1331{
551509d2 1332 if (crq->wValue == cpu_to_le16(USB_DEVICE_TEST_MODE))
914a3f3b
HS		 1333 return true;
1334 return false;
1335}
1336
1337static inline bool feature_is_ep_halt(struct usb_ctrlrequest *crq)
1338{
551509d2 1339 if (crq->wValue == cpu_to_le16(USB_ENDPOINT_HALT))
914a3f3b
HS		 1340 return true;
1341 return false;
1342}
1343
1344static int handle_ep0_setup(struct usba_udc *udc, struct usba_ep *ep,
1345 struct usb_ctrlrequest *crq)
1346{
40517707 1347 int retval = 0;
914a3f3b
HS		 1348
1349 switch (crq->bRequest) {
1350 case USB_REQ_GET_STATUS: {
1351 u16 status;
1352
1353 if (crq->bRequestType == (USB_DIR_IN | USB_RECIP_DEVICE)) {
58ed7b94 1354 status = cpu_to_le16(udc->devstatus);
914a3f3b
HS		 1355 } else if (crq->bRequestType
1356 == (USB_DIR_IN | USB_RECIP_INTERFACE)) {
551509d2 1357 status = cpu_to_le16(0);
914a3f3b
HS		 1358 } else if (crq->bRequestType
1359 == (USB_DIR_IN | USB_RECIP_ENDPOINT)) {
1360 struct usba_ep *target;
1361
1362 target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
1363 if (!target)
1364 goto stall;
1365
1366 status = 0;
1367 if (is_stalled(udc, target))
551509d2 1368 status |= cpu_to_le16(1);
914a3f3b
HS		 1369 } else
1370 goto delegate;
1371
1372 /* Write directly to the FIFO. No queueing is done. */
551509d2 1373 if (crq->wLength != cpu_to_le16(sizeof(status)))
914a3f3b
HS		 1374 goto stall;
1375 ep->state = DATA_STAGE_IN;
a3dd3bef 1376 usba_io_writew(status, ep->fifo);
914a3f3b
HS		 1377 usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
1378 break;
1379 }
1380
1381 case USB_REQ_CLEAR_FEATURE: {
1382 if (crq->bRequestType == USB_RECIP_DEVICE) {
58ed7b94
HS		 1383 if (feature_is_dev_remote_wakeup(crq))
1384 udc->devstatus
1385 &= ~(1 << USB_DEVICE_REMOTE_WAKEUP);
1386 else
914a3f3b
HS		 1387 /* Can't CLEAR_FEATURE TEST_MODE */
1388 goto stall;
914a3f3b
HS		 1389 } else if (crq->bRequestType == USB_RECIP_ENDPOINT) {
1390 struct usba_ep *target;
1391
551509d2 1392 if (crq->wLength != cpu_to_le16(0)
914a3f3b
HS		 1393 || !feature_is_ep_halt(crq))
1394 goto stall;
1395 target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
1396 if (!target)
1397 goto stall;
1398
1399 usba_ep_writel(target, CLR_STA, USBA_FORCE_STALL);
1400 if (target->index != 0)
1401 usba_ep_writel(target, CLR_STA,
1402 USBA_TOGGLE_CLR);
1403 } else {
1404 goto delegate;
1405 }
1406
1407 send_status(udc, ep);
1408 break;
1409 }
1410
1411 case USB_REQ_SET_FEATURE: {
1412 if (crq->bRequestType == USB_RECIP_DEVICE) {
1413 if (feature_is_dev_test_mode(crq)) {
1414 send_status(udc, ep);
1415 ep->state = STATUS_STAGE_TEST;
1416 udc->test_mode = le16_to_cpu(crq->wIndex);
1417 return 0;
1418 } else if (feature_is_dev_remote_wakeup(crq)) {
58ed7b94 1419 udc->devstatus |= 1 << USB_DEVICE_REMOTE_WAKEUP;
914a3f3b
HS		 1420 } else {
1421 goto stall;
1422 }
1423 } else if (crq->bRequestType == USB_RECIP_ENDPOINT) {
1424 struct usba_ep *target;
1425
551509d2 1426 if (crq->wLength != cpu_to_le16(0)
914a3f3b
HS		 1427 || !feature_is_ep_halt(crq))
1428 goto stall;
1429
1430 target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
1431 if (!target)
1432 goto stall;
1433
1434 usba_ep_writel(target, SET_STA, USBA_FORCE_STALL);
1435 } else
1436 goto delegate;
1437
1438 send_status(udc, ep);
1439 break;
1440 }
1441
1442 case USB_REQ_SET_ADDRESS:
1443 if (crq->bRequestType != (USB_DIR_OUT | USB_RECIP_DEVICE))
1444 goto delegate;
1445
1446 set_address(udc, le16_to_cpu(crq->wValue));
1447 send_status(udc, ep);
1448 ep->state = STATUS_STAGE_ADDR;
1449 break;
1450
1451 default:
1452delegate:
1453 spin_unlock(&udc->lock);
1454 retval = udc->driver->setup(&udc->gadget, crq);
1455 spin_lock(&udc->lock);
1456 }
1457
1458 return retval;
1459
1460stall:
00274921 1461 pr_err("udc: %s: Invalid setup request: %02x.%02x v%04x i%04x l%d, "
914a3f3b
HS		 1462 "halting endpoint...\n",
1463 ep->ep.name, crq->bRequestType, crq->bRequest,
1464 le16_to_cpu(crq->wValue), le16_to_cpu(crq->wIndex),
1465 le16_to_cpu(crq->wLength));
1466 set_protocol_stall(udc, ep);
1467 return -1;
1468}
1469
1470static void usba_control_irq(struct usba_udc *udc, struct usba_ep *ep)
1471{
1472 struct usba_request *req;
1473 u32 epstatus;
1474 u32 epctrl;
1475
1476restart:
1477 epstatus = usba_ep_readl(ep, STA);
1478 epctrl = usba_ep_readl(ep, CTL);
1479
1480 DBG(DBG_INT, "%s [%d]: s/%08x c/%08x\n",
1481 ep->ep.name, ep->state, epstatus, epctrl);
1482
1483 req = NULL;
1484 if (!list_empty(&ep->queue))
1485 req = list_entry(ep->queue.next,
1486 struct usba_request, queue);
1487
1488 if ((epctrl & USBA_TX_PK_RDY) && !(epstatus & USBA_TX_PK_RDY)) {
1489 if (req->submitted)
1490 next_fifo_transaction(ep, req);
1491 else
1492 submit_request(ep, req);
1493
1494 if (req->last_transaction) {
1495 usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY);
1496 usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE);
1497 }
1498 goto restart;
1499 }
1500 if ((epstatus & epctrl) & USBA_TX_COMPLETE) {
1501 usba_ep_writel(ep, CLR_STA, USBA_TX_COMPLETE);
1502
1503 switch (ep->state) {
1504 case DATA_STAGE_IN:
1505 usba_ep_writel(ep, CTL_ENB, USBA_RX_BK_RDY);
1506 usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
1507 ep->state = STATUS_STAGE_OUT;
1508 break;
1509 case STATUS_STAGE_ADDR:
1510 /* Activate our new address */
1511 usba_writel(udc, CTRL, (usba_readl(udc, CTRL)
1512 | USBA_FADDR_EN));
1513 usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
1514 ep->state = WAIT_FOR_SETUP;
1515 break;
1516 case STATUS_STAGE_IN:
1517 if (req) {
1518 list_del_init(&req->queue);
1519 request_complete(ep, req, 0);
1520 submit_next_request(ep);
1521 }
1522 usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
1523 ep->state = WAIT_FOR_SETUP;
1524 break;
1525 case STATUS_STAGE_TEST:
1526 usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
1527 ep->state = WAIT_FOR_SETUP;
1528 if (do_test_mode(udc))
1529 set_protocol_stall(udc, ep);
1530 break;
1531 default:
00274921 1532 pr_err("udc: %s: TXCOMP: Invalid endpoint state %d, "
914a3f3b
HS		 1533 "halting endpoint...\n",
1534 ep->ep.name, ep->state);
1535 set_protocol_stall(udc, ep);
1536 break;
1537 }
1538
1539 goto restart;
1540 }
1541 if ((epstatus & epctrl) & USBA_RX_BK_RDY) {
1542 switch (ep->state) {
1543 case STATUS_STAGE_OUT:
1544 usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
1545 usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
1546
1547 if (req) {
1548 list_del_init(&req->queue);
1549 request_complete(ep, req, 0);
1550 }
1551 ep->state = WAIT_FOR_SETUP;
1552 break;
1553
1554 case DATA_STAGE_OUT:
1555 receive_data(ep);
1556 break;
1557
1558 default:
1559 usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
1560 usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
00274921 1561 pr_err("udc: %s: RXRDY: Invalid endpoint state %d, "
914a3f3b
HS		 1562 "halting endpoint...\n",
1563 ep->ep.name, ep->state);
1564 set_protocol_stall(udc, ep);
1565 break;
1566 }
1567
1568 goto restart;
1569 }
1570 if (epstatus & USBA_RX_SETUP) {
1571 union {
1572 struct usb_ctrlrequest crq;
1573 unsigned long data[2];
1574 } crq;
1575 unsigned int pkt_len;
1576 int ret;
1577
1578 if (ep->state != WAIT_FOR_SETUP) {
1579 /*
1580 * Didn't expect a SETUP packet at this
1581 * point. Clean up any pending requests (which
1582 * may be successful).
1583 */
1584 int status = -EPROTO;
1585
1586 /*
1587 * RXRDY and TXCOMP are dropped when SETUP
1588 * packets arrive. Just pretend we received
1589 * the status packet.
1590 */
1591 if (ep->state == STATUS_STAGE_OUT
1592 || ep->state == STATUS_STAGE_IN) {
1593 usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
1594 status = 0;
1595 }
1596
1597 if (req) {
1598 list_del_init(&req->queue);
1599 request_complete(ep, req, status);
1600 }
1601 }
1602
1603 pkt_len = USBA_BFEXT(BYTE_COUNT, usba_ep_readl(ep, STA));
1604 DBG(DBG_HW, "Packet length: %u\n", pkt_len);
1605 if (pkt_len != sizeof(crq)) {
3f5ad864
JP		 1606 pr_warn("udc: Invalid packet length %u (expected %zu)\n",
1607 pkt_len, sizeof(crq));
914a3f3b
HS		 1608 set_protocol_stall(udc, ep);
1609 return;
1610 }
1611
1612 DBG(DBG_FIFO, "Copying ctrl request from 0x%p:\n", ep->fifo);
5d4c2707 1613 memcpy_fromio(crq.data, ep->fifo, sizeof(crq));
914a3f3b
HS		 1614
1615 /* Free up one bank in the FIFO so that we can
1616 * generate or receive a reply right away. */
1617 usba_ep_writel(ep, CLR_STA, USBA_RX_SETUP);
1618
1619 /* printk(KERN_DEBUG "setup: %d: %02x.%02x\n",
1620 ep->state, crq.crq.bRequestType,
1621 crq.crq.bRequest); */
1622
1623 if (crq.crq.bRequestType & USB_DIR_IN) {
1624 /*
1625 * The USB 2.0 spec states that "if wLength is
1626 * zero, there is no data transfer phase."
1627 * However, testusb #14 seems to actually
1628 * expect a data phase even if wLength = 0...
1629 */
1630 ep->state = DATA_STAGE_IN;
1631 } else {
551509d2 1632 if (crq.crq.wLength != cpu_to_le16(0))
914a3f3b
HS		 1633 ep->state = DATA_STAGE_OUT;
1634 else
1635 ep->state = STATUS_STAGE_IN;
1636 }
1637
1638 ret = -1;
1639 if (ep->index == 0)
1640 ret = handle_ep0_setup(udc, ep, &crq.crq);
1641 else {
1642 spin_unlock(&udc->lock);
1643 ret = udc->driver->setup(&udc->gadget, &crq.crq);
1644 spin_lock(&udc->lock);
1645 }
1646
1647 DBG(DBG_BUS, "req %02x.%02x, length %d, state %d, ret %d\n",
1648 crq.crq.bRequestType, crq.crq.bRequest,
1649 le16_to_cpu(crq.crq.wLength), ep->state, ret);
1650
1651 if (ret < 0) {
1652 /* Let the host know that we failed */
1653 set_protocol_stall(udc, ep);
1654 }
1655 }
1656}
1657
1658static void usba_ep_irq(struct usba_udc *udc, struct usba_ep *ep)
1659{
1660 struct usba_request *req;
1661 u32 epstatus;
1662 u32 epctrl;
1663
1664 epstatus = usba_ep_readl(ep, STA);
1665 epctrl = usba_ep_readl(ep, CTL);
1666
1667 DBG(DBG_INT, "%s: interrupt, status: 0x%08x\n", ep->ep.name, epstatus);
1668
1669 while ((epctrl & USBA_TX_PK_RDY) && !(epstatus & USBA_TX_PK_RDY)) {
1670 DBG(DBG_BUS, "%s: TX PK ready\n", ep->ep.name);
1671
1672 if (list_empty(&ep->queue)) {
1673 dev_warn(&udc->pdev->dev, "ep_irq: queue empty\n");
1674 usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY);
1675 return;
1676 }
1677
1678 req = list_entry(ep->queue.next, struct usba_request, queue);
1679
1680 if (req->using_dma) {
1681 /* Send a zero-length packet */
1682 usba_ep_writel(ep, SET_STA,
1683 USBA_TX_PK_RDY);
1684 usba_ep_writel(ep, CTL_DIS,
1685 USBA_TX_PK_RDY);
1686 list_del_init(&req->queue);
1687 submit_next_request(ep);
1688 request_complete(ep, req, 0);
1689 } else {
1690 if (req->submitted)
1691 next_fifo_transaction(ep, req);
1692 else
1693 submit_request(ep, req);
1694
1695 if (req->last_transaction) {
1696 list_del_init(&req->queue);
1697 submit_next_request(ep);
1698 request_complete(ep, req, 0);
1699 }
1700 }
1701
1702 epstatus = usba_ep_readl(ep, STA);
1703 epctrl = usba_ep_readl(ep, CTL);
1704 }
1705 if ((epstatus & epctrl) & USBA_RX_BK_RDY) {
1706 DBG(DBG_BUS, "%s: RX data ready\n", ep->ep.name);
1707 receive_data(ep);
914a3f3b
HS		 1708 }
1709}
1710
1711static void usba_dma_irq(struct usba_udc *udc, struct usba_ep *ep)
1712{
1713 struct usba_request *req;
1714 u32 status, control, pending;
1715
1716 status = usba_dma_readl(ep, STATUS);
1717 control = usba_dma_readl(ep, CONTROL);
1718#ifdef CONFIG_USB_GADGET_DEBUG_FS
1719 ep->last_dma_status = status;
1720#endif
1721 pending = status & control;
1722 DBG(DBG_INT | DBG_DMA, "dma irq, s/%#08x, c/%#08x\n", status, control);
1723
1724 if (status & USBA_DMA_CH_EN) {
1725 dev_err(&udc->pdev->dev,
1726 "DMA_CH_EN is set after transfer is finished!\n");
1727 dev_err(&udc->pdev->dev,
1728 "status=%#08x, pending=%#08x, control=%#08x\n",
1729 status, pending, control);
1730
1731 /*
1732 * try to pretend nothing happened. We might have to
1733 * do something here...
1734 */
1735 }
1736
1737 if (list_empty(&ep->queue))
1738 /* Might happen if a reset comes along at the right moment */
1739 return;
1740
1741 if (pending & (USBA_DMA_END_TR_ST | USBA_DMA_END_BUF_ST)) {
1742 req = list_entry(ep->queue.next, struct usba_request, queue);
1743 usba_update_req(ep, req, status);
1744
1745 list_del_init(&req->queue);
1746 submit_next_request(ep);
1747 request_complete(ep, req, 0);
1748 }
1749}
1750
1751static irqreturn_t usba_udc_irq(int irq, void *devid)
1752{
1753 struct usba_udc *udc = devid;
e3a912a1 1754 u32 status, int_enb;
914a3f3b
HS		 1755 u32 dma_status;
1756 u32 ep_status;
1757
1758 spin_lock(&udc->lock);
1759
e3a912a1 1760 int_enb = usba_int_enb_get(udc);
d134c48d 1761 status = usba_readl(udc, INT_STA) & (int_enb | USBA_HIGH_SPEED);
914a3f3b
HS		 1762 DBG(DBG_INT, "irq, status=%#08x\n", status);
1763
1764 if (status & USBA_DET_SUSPEND) {
3280e675 1765 toggle_bias(udc, 0);
914a3f3b 1766 usba_writel(udc, INT_CLR, USBA_DET_SUSPEND);
e3a912a1 1767 usba_int_enb_set(udc, int_enb | USBA_WAKE_UP);
258e2ddd 1768 udc->bias_pulse_needed = true;
914a3f3b
HS		 1769 DBG(DBG_BUS, "Suspend detected\n");
1770 if (udc->gadget.speed != USB_SPEED_UNKNOWN
1771 && udc->driver && udc->driver->suspend) {
1772 spin_unlock(&udc->lock);
1773 udc->driver->suspend(&udc->gadget);
1774 spin_lock(&udc->lock);
1775 }
1776 }
1777
1778 if (status & USBA_WAKE_UP) {
3280e675 1779 toggle_bias(udc, 1);
914a3f3b 1780 usba_writel(udc, INT_CLR, USBA_WAKE_UP);
e3a912a1 1781 usba_int_enb_set(udc, int_enb & ~USBA_WAKE_UP);
914a3f3b
HS		 1782 DBG(DBG_BUS, "Wake Up CPU detected\n");
1783 }
1784
1785 if (status & USBA_END_OF_RESUME) {
1786 usba_writel(udc, INT_CLR, USBA_END_OF_RESUME);
258e2ddd 1787 generate_bias_pulse(udc);
914a3f3b
HS		 1788 DBG(DBG_BUS, "Resume detected\n");
1789 if (udc->gadget.speed != USB_SPEED_UNKNOWN
1790 && udc->driver && udc->driver->resume) {
1791 spin_unlock(&udc->lock);
1792 udc->driver->resume(&udc->gadget);
1793 spin_lock(&udc->lock);
1794 }
1795 }
1796
1797 dma_status = USBA_BFEXT(DMA_INT, status);
1798 if (dma_status) {
1799 int i;
1800
bcabdc24 1801 for (i = 1; i <= USBA_NR_DMAS; i++)
914a3f3b 1802 if (dma_status & (1 << i))
68522de7 1803 usba_dma_irq(udc, &udc->usba_ep[i]);
914a3f3b
HS		 1804 }
1805
1806 ep_status = USBA_BFEXT(EPT_INT, status);
1807 if (ep_status) {
1808 int i;
1809
aa7be0f8 1810 for (i = 0; i < udc->num_ep; i++)
914a3f3b 1811 if (ep_status & (1 << i)) {
68522de7
JCPV		 1812 if (ep_is_control(&udc->usba_ep[i]))
1813 usba_control_irq(udc, &udc->usba_ep[i]);
914a3f3b 1814 else
68522de7 1815 usba_ep_irq(udc, &udc->usba_ep[i]);
914a3f3b
HS		 1816 }
1817 }
1818
1819 if (status & USBA_END_OF_RESET) {
741d2558
CB		 1820 struct usba_ep *ep0, *ep;
1821 int i, n;
914a3f3b
HS		 1822
1823 usba_writel(udc, INT_CLR, USBA_END_OF_RESET);
258e2ddd 1824 generate_bias_pulse(udc);
914a3f3b
HS		 1825 reset_all_endpoints(udc);
1826
39dd96d6 1827 if (udc->gadget.speed != USB_SPEED_UNKNOWN && udc->driver) {
40517707
DB		 1828 udc->gadget.speed = USB_SPEED_UNKNOWN;
1829 spin_unlock(&udc->lock);
39dd96d6 1830 usb_gadget_udc_reset(&udc->gadget, udc->driver);
40517707
DB		 1831 spin_lock(&udc->lock);
1832 }
1833
e538dfda 1834 if (status & USBA_HIGH_SPEED)
914a3f3b 1835 udc->gadget.speed = USB_SPEED_HIGH;
e538dfda 1836 else
914a3f3b 1837 udc->gadget.speed = USB_SPEED_FULL;
e538dfda
MN		 1838 DBG(DBG_BUS, "%s bus reset detected\n",
1839 usb_speed_string(udc->gadget.speed));
914a3f3b 1840
68522de7 1841 ep0 = &udc->usba_ep[0];
978def1c 1842 ep0->ep.desc = &usba_ep0_desc;
914a3f3b
HS		 1843 ep0->state = WAIT_FOR_SETUP;
1844 usba_ep_writel(ep0, CFG,
1845 (USBA_BF(EPT_SIZE, EP0_EPT_SIZE)
1846 | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_CONTROL)
1847 | USBA_BF(BK_NUMBER, USBA_BK_NUMBER_ONE)));
1848 usba_ep_writel(ep0, CTL_ENB,
1849 USBA_EPT_ENABLE | USBA_RX_SETUP);
e3a912a1
BB		 1850 usba_int_enb_set(udc, int_enb | USBA_BF(EPT_INT, 1) |
1851 USBA_DET_SUSPEND | USBA_END_OF_RESUME);
914a3f3b 1852
40517707
DB		 1853 /*
1854 * Unclear why we hit this irregularly, e.g. in usbtest,
1855 * but it's clearly harmless...
1856 */
914a3f3b 1857 if (!(usba_ep_readl(ep0, CFG) & USBA_EPT_MAPPED))
40517707
DB		 1858 dev_dbg(&udc->pdev->dev,
1859 "ODD: EP0 configuration is invalid!\n");
741d2558
CB		 1860
1861 /* Preallocate other endpoints */
1862 n = fifo_mode ? udc->num_ep : udc->configured_ep;
1863 for (i = 1; i < n; i++) {
1864 ep = &udc->usba_ep[i];
1865 usba_ep_writel(ep, CFG, ep->ept_cfg);
1866 if (!(usba_ep_readl(ep, CFG) & USBA_EPT_MAPPED))
1867 dev_dbg(&udc->pdev->dev,
1868 "ODD: EP%d configuration is invalid!\n", i);
1869 }
914a3f3b
HS		 1870 }
1871
1872 spin_unlock(&udc->lock);
1873
1874 return IRQ_HANDLED;
1875}
1876
a64ef71d
SR		 1877static int start_clock(struct usba_udc *udc)
1878{
1879 int ret;
1880
1881 if (udc->clocked)
1882 return 0;
1883
1884 ret = clk_prepare_enable(udc->pclk);
1885 if (ret)
1886 return ret;
1887 ret = clk_prepare_enable(udc->hclk);
1888 if (ret) {
1889 clk_disable_unprepare(udc->pclk);
1890 return ret;
1891 }
1892
1893 udc->clocked = true;
1894 return 0;
1895}
1896
1897static void stop_clock(struct usba_udc *udc)
1898{
1899 if (!udc->clocked)
1900 return;
1901
1902 clk_disable_unprepare(udc->hclk);
1903 clk_disable_unprepare(udc->pclk);
1904
1905 udc->clocked = false;
1906}
1907
1908static int usba_start(struct usba_udc *udc)
1909{
1910 unsigned long flags;
1911 int ret;
1912
1913 ret = start_clock(udc);
1914 if (ret)
1915 return ret;
1916
1917 spin_lock_irqsave(&udc->lock, flags);
1918 toggle_bias(udc, 1);
1919 usba_writel(udc, CTRL, USBA_ENABLE_MASK);
1920 usba_int_enb_set(udc, USBA_END_OF_RESET);
1921 spin_unlock_irqrestore(&udc->lock, flags);
1922
1923 return 0;
1924}
1925
1926static void usba_stop(struct usba_udc *udc)
1927{
1928 unsigned long flags;
1929
1930 spin_lock_irqsave(&udc->lock, flags);
1931 udc->gadget.speed = USB_SPEED_UNKNOWN;
1932 reset_all_endpoints(udc);
1933
1934 /* This will also disable the DP pullup */
1935 toggle_bias(udc, 0);
1936 usba_writel(udc, CTRL, USBA_DISABLE_MASK);
1937 spin_unlock_irqrestore(&udc->lock, flags);
1938
1939 stop_clock(udc);
1940}
1941
1942static irqreturn_t usba_vbus_irq_thread(int irq, void *devid)
914a3f3b
HS		 1943{
1944 struct usba_udc *udc = devid;
1945 int vbus;
1946
1947 /* debounce */
1948 udelay(10);
1949
a64ef71d 1950 mutex_lock(&udc->vbus_mutex);
914a3f3b 1951
640e95ab 1952 vbus = vbus_is_present(udc);
914a3f3b
HS		 1953 if (vbus != udc->vbus_prev) {
1954 if (vbus) {
a64ef71d 1955 usba_start(udc);
914a3f3b 1956 } else {
a64ef71d
SR		 1957 usba_stop(udc);
1958
1959 if (udc->driver->disconnect)
40517707 1960 udc->driver->disconnect(&udc->gadget);
914a3f3b
HS		 1961 }
1962 udc->vbus_prev = vbus;
1963 }
1964
a64ef71d 1965 mutex_unlock(&udc->vbus_mutex);
914a3f3b
HS		 1966 return IRQ_HANDLED;
1967}
1968
d809f78f
SAS		 1969static int atmel_usba_start(struct usb_gadget *gadget,
1970 struct usb_gadget_driver *driver)
914a3f3b 1971{
ffb62a14 1972 int ret;
d809f78f 1973 struct usba_udc *udc = container_of(gadget, struct usba_udc, gadget);
914a3f3b 1974 unsigned long flags;
914a3f3b
HS		 1975
1976 spin_lock_irqsave(&udc->lock, flags);
58ed7b94 1977 udc->devstatus = 1 << USB_DEVICE_SELF_POWERED;
914a3f3b 1978 udc->driver = driver;
914a3f3b
HS		 1979 spin_unlock_irqrestore(&udc->lock, flags);
1980
a64ef71d 1981 mutex_lock(&udc->vbus_mutex);
914a3f3b 1982
472a6786 1983 if (gpio_is_valid(udc->vbus_pin))
914a3f3b
HS		 1984 enable_irq(gpio_to_irq(udc->vbus_pin));
1985
1986 /* If Vbus is present, enable the controller and wait for reset */
a64ef71d
SR		 1987 udc->vbus_prev = vbus_is_present(udc);
1988 if (udc->vbus_prev) {
1989 ret = usba_start(udc);
1990 if (ret)
1991 goto err;
914a3f3b 1992 }
914a3f3b 1993
a64ef71d 1994 mutex_unlock(&udc->vbus_mutex);
ffb62a14 1995 return 0;
a64ef71d
SR		 1996
1997err:
1998 if (gpio_is_valid(udc->vbus_pin))
1999 disable_irq(gpio_to_irq(udc->vbus_pin));
2000
2001 mutex_unlock(&udc->vbus_mutex);
2002
2003 spin_lock_irqsave(&udc->lock, flags);
2004 udc->devstatus &= ~(1 << USB_DEVICE_SELF_POWERED);
2005 udc->driver = NULL;
2006 spin_unlock_irqrestore(&udc->lock, flags);
2007 return ret;
914a3f3b 2008}
914a3f3b 2009
22835b80 2010static int atmel_usba_stop(struct usb_gadget *gadget)
914a3f3b 2011{
d809f78f 2012 struct usba_udc *udc = container_of(gadget, struct usba_udc, gadget);
914a3f3b 2013
472a6786 2014 if (gpio_is_valid(udc->vbus_pin))
914a3f3b
HS		 2015 disable_irq(gpio_to_irq(udc->vbus_pin));
2016
741d2558
CB		 2017 if (fifo_mode == 0)
2018 udc->configured_ep = 1;
2019
a64ef71d 2020 usba_stop(udc);
914a3f3b 2021
d8eb6c65 2022 udc->driver = NULL;
914a3f3b
HS		 2023
2024 return 0;
2025}
914a3f3b 2026
4a3ae932 2027#ifdef CONFIG_OF
3280e675
BB		 2028static void at91sam9rl_toggle_bias(struct usba_udc *udc, int is_on)
2029{
4747639f
AB		 2030 regmap_update_bits(udc->pmc, AT91_CKGR_UCKR, AT91_PMC_BIASEN,
2031 is_on ? AT91_PMC_BIASEN : 0);
3280e675
BB		 2032}
2033
258e2ddd
BB		 2034static void at91sam9g45_pulse_bias(struct usba_udc *udc)
2035{
4747639f
AB		 2036 regmap_update_bits(udc->pmc, AT91_CKGR_UCKR, AT91_PMC_BIASEN, 0);
2037 regmap_update_bits(udc->pmc, AT91_CKGR_UCKR, AT91_PMC_BIASEN,
2038 AT91_PMC_BIASEN);
258e2ddd
BB		 2039}
2040
3280e675
BB		 2041static const struct usba_udc_errata at91sam9rl_errata = {
2042 .toggle_bias = at91sam9rl_toggle_bias,
2043};
2044
258e2ddd
BB		 2045static const struct usba_udc_errata at91sam9g45_errata = {
2046 .pulse_bias = at91sam9g45_pulse_bias,
2047};
2048
3280e675
BB		 2049static const struct of_device_id atmel_udc_dt_ids[] = {
2050 { .compatible = "atmel,at91sam9rl-udc", .data = &at91sam9rl_errata },
258e2ddd 2051 { .compatible = "atmel,at91sam9g45-udc", .data = &at91sam9g45_errata },
3280e675
BB		 2052 { .compatible = "atmel,sama5d3-udc" },
2053 { /* sentinel */ }
2054};
2055
2056MODULE_DEVICE_TABLE(of, atmel_udc_dt_ids);
2057
4a3ae932
JCPV		 2058static struct usba_ep * atmel_udc_of_init(struct platform_device *pdev,
2059 struct usba_udc *udc)
2060{
2061 u32 val;
2062 const char *name;
2063 enum of_gpio_flags flags;
2064 struct device_node *np = pdev->dev.of_node;
3280e675 2065 const struct of_device_id *match;
4a3ae932
JCPV		 2066 struct device_node *pp;
2067 int i, ret;
2068 struct usba_ep *eps, *ep;
2069
3280e675
BB		 2070 match = of_match_node(atmel_udc_dt_ids, np);
2071 if (!match)
2072 return ERR_PTR(-EINVAL);
2073
2074 udc->errata = match->data;
4747639f 2075 udc->pmc = syscon_regmap_lookup_by_compatible("atmel,at91sam9g45-pmc");
882bd9fc
AB		 2076 if (IS_ERR(udc->pmc))
2077 udc->pmc = syscon_regmap_lookup_by_compatible("atmel,at91sam9x5-pmc");
4747639f
AB		 2078 if (udc->errata && IS_ERR(udc->pmc))
2079 return ERR_CAST(udc->pmc);
3280e675 2080
4a3ae932
JCPV		 2081 udc->num_ep = 0;
2082
2083 udc->vbus_pin = of_get_named_gpio_flags(np, "atmel,vbus-gpio", 0,
2084 &flags);
2085 udc->vbus_pin_inverted = (flags & OF_GPIO_ACTIVE_LOW) ? 1 : 0;
2086
741d2558
CB		 2087 if (fifo_mode == 0) {
2088 pp = NULL;
2089 while ((pp = of_get_next_child(np, pp)))
2090 udc->num_ep++;
2091 udc->configured_ep = 1;
2092 } else
2093 udc->num_ep = usba_config_fifo_table(udc);
4a3ae932
JCPV		 2094
2095 eps = devm_kzalloc(&pdev->dev, sizeof(struct usba_ep) * udc->num_ep,
2096 GFP_KERNEL);
2097 if (!eps)
2098 return ERR_PTR(-ENOMEM);
2099
2100 udc->gadget.ep0 = &eps[0].ep;
2101
2102 INIT_LIST_HEAD(&eps[0].ep.ep_list);
2103
2104 pp = NULL;
2105 i = 0;
741d2558 2106 while ((pp = of_get_next_child(np, pp)) && i < udc->num_ep) {
4a3ae932
JCPV		 2107 ep = &eps[i];
2108
2109 ret = of_property_read_u32(pp, "reg", &val);
2110 if (ret) {
2111 dev_err(&pdev->dev, "of_probe: reg error(%d)\n", ret);
2112 goto err;
2113 }
741d2558 2114 ep->index = fifo_mode ? udc->fifo_cfg[i].hw_ep_num : val;
4a3ae932
JCPV		 2115
2116 ret = of_property_read_u32(pp, "atmel,fifo-size", &val);
2117 if (ret) {
2118 dev_err(&pdev->dev, "of_probe: fifo-size error(%d)\n", ret);
2119 goto err;
2120 }
741d2558 2121 ep->fifo_size = fifo_mode ? udc->fifo_cfg[i].fifo_size : val;
4a3ae932
JCPV		 2122
2123 ret = of_property_read_u32(pp, "atmel,nb-banks", &val);
2124 if (ret) {
2125 dev_err(&pdev->dev, "of_probe: nb-banks error(%d)\n", ret);
2126 goto err;
2127 }
741d2558 2128 ep->nr_banks = fifo_mode ? udc->fifo_cfg[i].nr_banks : val;
4a3ae932
JCPV		 2129
2130 ep->can_dma = of_property_read_bool(pp, "atmel,can-dma");
2131 ep->can_isoc = of_property_read_bool(pp, "atmel,can-isoc");
2132
2133 ret = of_property_read_string(pp, "name", &name);
7674cba5
RB		 2134 if (ret) {
2135 dev_err(&pdev->dev, "of_probe: name error(%d)\n", ret);
2136 goto err;
2137 }
32856eea
AB		 2138 sprintf(ep->name, "ep%d", ep->index);
2139 ep->ep.name = ep->name;
4a3ae932
JCPV		 2140
2141 ep->ep_regs = udc->regs + USBA_EPT_BASE(i);
2142 ep->dma_regs = udc->regs + USBA_DMA_BASE(i);
2143 ep->fifo = udc->fifo + USBA_FIFO_BASE(i);
2144 ep->ep.ops = &usba_ep_ops;
e117e742 2145 usb_ep_set_maxpacket_limit(&ep->ep, ep->fifo_size);
4a3ae932
JCPV		 2146 ep->udc = udc;
2147 INIT_LIST_HEAD(&ep->queue);
2148
cf261fd1
SR		 2149 if (ep->index == 0) {
2150 ep->ep.caps.type_control = true;
2151 } else {
2152 ep->ep.caps.type_iso = ep->can_isoc;
2153 ep->ep.caps.type_bulk = true;
2154 ep->ep.caps.type_int = true;
2155 }
2156
2157 ep->ep.caps.dir_in = true;
2158 ep->ep.caps.dir_out = true;
2159
741d2558
CB		 2160 if (fifo_mode != 0) {
2161 /*
2162 * Generate ept_cfg based on FIFO size and
2163 * banks number
2164 */
2165 if (ep->fifo_size <= 8)
2166 ep->ept_cfg = USBA_BF(EPT_SIZE, USBA_EPT_SIZE_8);
2167 else
2168 /* LSB is bit 1, not 0 */
2169 ep->ept_cfg =
2170 USBA_BF(EPT_SIZE, fls(ep->fifo_size - 1) - 3);
2171
2172 ep->ept_cfg |= USBA_BF(BK_NUMBER, ep->nr_banks);
2173 }
2174
4a3ae932
JCPV		 2175 if (i)
2176 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
2177
2178 i++;
2179 }
2180
fb0e139d
AB		 2181 if (i == 0) {
2182 dev_err(&pdev->dev, "of_probe: no endpoint specified\n");
2183 ret = -EINVAL;
2184 goto err;
2185 }
2186
4a3ae932
JCPV		 2187 return eps;
2188err:
2189 return ERR_PTR(ret);
2190}
2191#else
2192static struct usba_ep * atmel_udc_of_init(struct platform_device *pdev,
2193 struct usba_udc *udc)
2194{
2195 return ERR_PTR(-ENOSYS);
2196}
2197#endif
2198
2199static struct usba_ep * usba_udc_pdata(struct platform_device *pdev,
2200 struct usba_udc *udc)
914a3f3b 2201{
e01ee9f5 2202 struct usba_platform_data *pdata = dev_get_platdata(&pdev->dev);
4a3ae932
JCPV		 2203 struct usba_ep *eps;
2204 int i;
2205
2206 if (!pdata)
2207 return ERR_PTR(-ENXIO);
2208
2209 eps = devm_kzalloc(&pdev->dev, sizeof(struct usba_ep) * pdata->num_ep,
2210 GFP_KERNEL);
2211 if (!eps)
2212 return ERR_PTR(-ENOMEM);
2213
2214 udc->gadget.ep0 = &eps[0].ep;
2215
2216 udc->vbus_pin = pdata->vbus_pin;
2217 udc->vbus_pin_inverted = pdata->vbus_pin_inverted;
2218 udc->num_ep = pdata->num_ep;
2219
2220 INIT_LIST_HEAD(&eps[0].ep.ep_list);
2221
2222 for (i = 0; i < pdata->num_ep; i++) {
2223 struct usba_ep *ep = &eps[i];
2224
2225 ep->ep_regs = udc->regs + USBA_EPT_BASE(i);
2226 ep->dma_regs = udc->regs + USBA_DMA_BASE(i);
2227 ep->fifo = udc->fifo + USBA_FIFO_BASE(i);
2228 ep->ep.ops = &usba_ep_ops;
2229 ep->ep.name = pdata->ep[i].name;
e117e742
RB		 2230 ep->fifo_size = pdata->ep[i].fifo_size;
2231 usb_ep_set_maxpacket_limit(&ep->ep, ep->fifo_size);
4a3ae932
JCPV		 2232 ep->udc = udc;
2233 INIT_LIST_HEAD(&ep->queue);
2234 ep->nr_banks = pdata->ep[i].nr_banks;
2235 ep->index = pdata->ep[i].index;
2236 ep->can_dma = pdata->ep[i].can_dma;
2237 ep->can_isoc = pdata->ep[i].can_isoc;
2238
47bef386
RB		 2239 if (i == 0) {
2240 ep->ep.caps.type_control = true;
2241 } else {
2242 ep->ep.caps.type_iso = ep->can_isoc;
2243 ep->ep.caps.type_bulk = true;
2244 ep->ep.caps.type_int = true;
2245 }
2246
2247 ep->ep.caps.dir_in = true;
2248 ep->ep.caps.dir_out = true;
2249
4a3ae932
JCPV		 2250 if (i)
2251 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
2252 }
2253
2254 return eps;
2255}
2256
03d6a9c9 2257static int usba_udc_probe(struct platform_device *pdev)
4a3ae932 2258{
914a3f3b
HS		 2259 struct resource *regs, *fifo;
2260 struct clk *pclk, *hclk;
e8f2ea39 2261 struct usba_udc *udc;
914a3f3b
HS		 2262 int irq, ret, i;
2263
e8f2ea39
JCPV		 2264 udc = devm_kzalloc(&pdev->dev, sizeof(*udc), GFP_KERNEL);
2265 if (!udc)
2266 return -ENOMEM;
2267
2268 udc->gadget = usba_gadget_template;
2269 INIT_LIST_HEAD(&udc->gadget.ep_list);
2270
914a3f3b
HS		 2271 regs = platform_get_resource(pdev, IORESOURCE_MEM, CTRL_IOMEM_ID);
2272 fifo = platform_get_resource(pdev, IORESOURCE_MEM, FIFO_IOMEM_ID);
4a3ae932 2273 if (!regs || !fifo)
914a3f3b
HS		 2274 return -ENXIO;
2275
2276 irq = platform_get_irq(pdev, 0);
2277 if (irq < 0)
2278 return irq;
2279
40a8fb2a 2280 pclk = devm_clk_get(&pdev->dev, "pclk");
914a3f3b
HS		 2281 if (IS_ERR(pclk))
2282 return PTR_ERR(pclk);
40a8fb2a
JH		 2283 hclk = devm_clk_get(&pdev->dev, "hclk");
2284 if (IS_ERR(hclk))
2285 return PTR_ERR(hclk);
914a3f3b 2286
40517707 2287 spin_lock_init(&udc->lock);
a64ef71d 2288 mutex_init(&udc->vbus_mutex);
914a3f3b
HS		 2289 udc->pdev = pdev;
2290 udc->pclk = pclk;
2291 udc->hclk = hclk;
472a6786 2292 udc->vbus_pin = -ENODEV;
914a3f3b
HS		 2293
2294 ret = -ENOMEM;
40a8fb2a 2295 udc->regs = devm_ioremap(&pdev->dev, regs->start, resource_size(regs));
914a3f3b
HS		 2296 if (!udc->regs) {
2297 dev_err(&pdev->dev, "Unable to map I/O memory, aborting.\n");
40a8fb2a 2298 return ret;
914a3f3b
HS		 2299 }
2300 dev_info(&pdev->dev, "MMIO registers at 0x%08lx mapped at %p\n",
2301 (unsigned long)regs->start, udc->regs);
40a8fb2a 2302 udc->fifo = devm_ioremap(&pdev->dev, fifo->start, resource_size(fifo));
914a3f3b
HS		 2303 if (!udc->fifo) {
2304 dev_err(&pdev->dev, "Unable to map FIFO, aborting.\n");
40a8fb2a 2305 return ret;
914a3f3b
HS		 2306 }
2307 dev_info(&pdev->dev, "FIFO at 0x%08lx mapped at %p\n",
2308 (unsigned long)fifo->start, udc->fifo);
2309
914a3f3b
HS		 2310 platform_set_drvdata(pdev, udc);
2311
2312 /* Make sure we start from a clean slate */
0d98b9d6
BB		 2313 ret = clk_prepare_enable(pclk);
2314 if (ret) {
2315 dev_err(&pdev->dev, "Unable to enable pclk, aborting.\n");
40a8fb2a 2316 return ret;
0d98b9d6 2317 }
3280e675 2318
16a45bc8 2319 usba_writel(udc, CTRL, USBA_DISABLE_MASK);
0d98b9d6 2320 clk_disable_unprepare(pclk);
914a3f3b 2321
4a3ae932
JCPV		 2322 if (pdev->dev.of_node)
2323 udc->usba_ep = atmel_udc_of_init(pdev, udc);
2324 else
2325 udc->usba_ep = usba_udc_pdata(pdev, udc);
914a3f3b 2326
3280e675
BB		 2327 toggle_bias(udc, 0);
2328
40a8fb2a
JH		 2329 if (IS_ERR(udc->usba_ep))
2330 return PTR_ERR(udc->usba_ep);
914a3f3b 2331
40a8fb2a
JH		 2332 ret = devm_request_irq(&pdev->dev, irq, usba_udc_irq, 0,
2333 "atmel_usba_udc", udc);
914a3f3b
HS		 2334 if (ret) {
2335 dev_err(&pdev->dev, "Cannot request irq %d (error %d)\n",
2336 irq, ret);
40a8fb2a 2337 return ret;
914a3f3b
HS		 2338 }
2339 udc->irq = irq;
2340
4a3ae932
JCPV		 2341 if (gpio_is_valid(udc->vbus_pin)) {
2342 if (!devm_gpio_request(&pdev->dev, udc->vbus_pin, "atmel_usba_udc")) {
bb0a203c
SR		 2343 irq_set_status_flags(gpio_to_irq(udc->vbus_pin),
2344 IRQ_NOAUTOEN);
a64ef71d
SR		 2345 ret = devm_request_threaded_irq(&pdev->dev,
2346 gpio_to_irq(udc->vbus_pin), NULL,
2347 usba_vbus_irq_thread, IRQF_ONESHOT,
914a3f3b
HS		 2348 "atmel_usba_udc", udc);
2349 if (ret) {
472a6786 2350 udc->vbus_pin = -ENODEV;
914a3f3b
HS		 2351 dev_warn(&udc->pdev->dev,
2352 "failed to request vbus irq; "
2353 "assuming always on\n");
914a3f3b 2354 }
969affff
JCPV		 2355 } else {
2356 /* gpio_request fail so use -EINVAL for gpio_is_valid */
b4880951 2357 udc->vbus_pin = -EINVAL;
914a3f3b
HS		 2358 }
2359 }
2360
0f91349b
SAS		 2361 ret = usb_add_gadget_udc(&pdev->dev, &udc->gadget);
2362 if (ret)
40a8fb2a 2363 return ret;
112bf244 2364 device_init_wakeup(&pdev->dev, 1);
0f91349b 2365
914a3f3b 2366 usba_init_debugfs(udc);
4a3ae932
JCPV		 2367 for (i = 1; i < udc->num_ep; i++)
2368 usba_ep_init_debugfs(udc, &udc->usba_ep[i]);
914a3f3b
HS		 2369
2370 return 0;
914a3f3b
HS		 2371}
2372
c94e289f 2373static int usba_udc_remove(struct platform_device *pdev)
914a3f3b
HS		 2374{
2375 struct usba_udc *udc;
2376 int i;
2377
2378 udc = platform_get_drvdata(pdev);
2379
112bf244 2380 device_init_wakeup(&pdev->dev, 0);
0f91349b
SAS		 2381 usb_del_gadget_udc(&udc->gadget);
2382
4a3ae932 2383 for (i = 1; i < udc->num_ep; i++)
68522de7 2384 usba_ep_cleanup_debugfs(&udc->usba_ep[i]);
914a3f3b
HS		 2385 usba_cleanup_debugfs(udc);
2386
914a3f3b
HS		 2387 return 0;
2388}
2389
94a715ed 2390#ifdef CONFIG_PM_SLEEP
112bf244
SR		 2391static int usba_udc_suspend(struct device *dev)
2392{
2393 struct usba_udc *udc = dev_get_drvdata(dev);
2394
2395 /* Not started */
2396 if (!udc->driver)
2397 return 0;
2398
2399 mutex_lock(&udc->vbus_mutex);
2400
2401 if (!device_may_wakeup(dev)) {
2402 usba_stop(udc);
2403 goto out;
2404 }
2405
2406 /*
2407 * Device may wake up. We stay clocked if we failed
2408 * to request vbus irq, assuming always on.
2409 */
2410 if (gpio_is_valid(udc->vbus_pin)) {
2411 usba_stop(udc);
2412 enable_irq_wake(gpio_to_irq(udc->vbus_pin));
2413 }
2414
2415out:
2416 mutex_unlock(&udc->vbus_mutex);
2417 return 0;
2418}
2419
2420static int usba_udc_resume(struct device *dev)
2421{
2422 struct usba_udc *udc = dev_get_drvdata(dev);
2423
2424 /* Not started */
2425 if (!udc->driver)
2426 return 0;
2427
2428 if (device_may_wakeup(dev) && gpio_is_valid(udc->vbus_pin))
2429 disable_irq_wake(gpio_to_irq(udc->vbus_pin));
2430
2431 /* If Vbus is present, enable the controller and wait for reset */
2432 mutex_lock(&udc->vbus_mutex);
2433 udc->vbus_prev = vbus_is_present(udc);
2434 if (udc->vbus_prev)
2435 usba_start(udc);
2436 mutex_unlock(&udc->vbus_mutex);
2437
2438 return 0;
2439}
2440#endif
2441
2442static SIMPLE_DEV_PM_OPS(usba_udc_pm_ops, usba_udc_suspend, usba_udc_resume);
2443
914a3f3b 2444static struct platform_driver udc_driver = {
c94e289f 2445 .remove = usba_udc_remove,
914a3f3b
HS		 2446 .driver = {
2447 .name = "atmel_usba_udc",
112bf244 2448 .pm = &usba_udc_pm_ops,
4a3ae932 2449 .of_match_table = of_match_ptr(atmel_udc_dt_ids),
914a3f3b
HS		 2450 },
2451};
2452
52f7a82b 2453module_platform_driver_probe(udc_driver, usba_udc_probe);
914a3f3b
HS		 2454
2455MODULE_DESCRIPTION("Atmel USBA UDC driver");
e05503ef 2456MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
914a3f3b 2457MODULE_LICENSE("GPL");
f34c32f1 2458MODULE_ALIAS("platform:atmel_usba_udc");
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