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[mirror_ubuntu-eoan-kernel.git] / drivers / usb / gadget / udc / lpc32xx_udc.c
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5fd54ace 1// SPDX-License-Identifier: GPL-2.0+
24a28e42
RS		 2/*
3 * USB Gadget driver for LPC32xx
4 *
5 * Authors:
6 * Kevin Wells <kevin.wells@nxp.com>
7 * Mike James
8 * Roland Stigge <stigge@antcom.de>
9 *
10 * Copyright (C) 2006 Philips Semiconductors
11 * Copyright (C) 2009 NXP Semiconductors
12 * Copyright (C) 2012 Roland Stigge
13 *
14 * Note: This driver is based on original work done by Mike James for
15 * the LPC3180.
24a28e42
RS		 16 */
17
2de59c09 18#include <linux/clk.h>
24a28e42 19#include <linux/delay.h>
2de59c09
VZ		 20#include <linux/dma-mapping.h>
21#include <linux/dmapool.h>
22#include <linux/i2c.h>
24a28e42 23#include <linux/interrupt.h>
2de59c09
VZ		 24#include <linux/module.h>
25#include <linux/of.h>
26#include <linux/platform_device.h>
24a28e42 27#include <linux/proc_fs.h>
2de59c09 28#include <linux/slab.h>
24a28e42
RS		 29#include <linux/usb/ch9.h>
30#include <linux/usb/gadget.h>
24a28e42
RS		 31#include <linux/usb/isp1301.h>
32
24a28e42 33#ifdef CONFIG_USB_GADGET_DEBUG_FILES
d7dbdb5e 34#include <linux/debugfs.h>
24a28e42
RS		 35#include <linux/seq_file.h>
36#endif
37
2de59c09 38#include <mach/hardware.h>
2de59c09 39
24a28e42
RS		 40/*
41 * USB device configuration structure
42 */
43typedef void (*usc_chg_event)(int);
44struct lpc32xx_usbd_cfg {
45 int vbus_drv_pol; /* 0=active low drive for VBUS via ISP1301 */
46 usc_chg_event conn_chgb; /* Connection change event (optional) */
47 usc_chg_event susp_chgb; /* Suspend/resume event (optional) */
48 usc_chg_event rmwk_chgb; /* Enable/disable remote wakeup */
49};
50
51/*
52 * controller driver data structures
53 */
54
55/* 16 endpoints (not to be confused with 32 hardware endpoints) */
56#define NUM_ENDPOINTS 16
57
58/*
59 * IRQ indices make reading the code a little easier
60 */
61#define IRQ_USB_LP 0
62#define IRQ_USB_HP 1
63#define IRQ_USB_DEVDMA 2
64#define IRQ_USB_ATX 3
65
66#define EP_OUT 0 /* RX (from host) */
67#define EP_IN 1 /* TX (to host) */
68
69/* Returns the interrupt mask for the selected hardware endpoint */
70#define EP_MASK_SEL(ep, dir) (1 << (((ep) * 2) + dir))
71
72#define EP_INT_TYPE 0
73#define EP_ISO_TYPE 1
74#define EP_BLK_TYPE 2
75#define EP_CTL_TYPE 3
76
77/* EP0 states */
78#define WAIT_FOR_SETUP 0 /* Wait for setup packet */
79#define DATA_IN 1 /* Expect dev->host transfer */
80#define DATA_OUT 2 /* Expect host->dev transfer */
81
82/* DD (DMA Descriptor) structure, requires word alignment, this is already
83 * defined in the LPC32XX USB device header file, but this version is slightly
84 * modified to tag some work data with each DMA descriptor. */
85struct lpc32xx_usbd_dd_gad {
86 u32 dd_next_phy;
87 u32 dd_setup;
88 u32 dd_buffer_addr;
89 u32 dd_status;
90 u32 dd_iso_ps_mem_addr;
91 u32 this_dma;
92 u32 iso_status[6]; /* 5 spare */
93 u32 dd_next_v;
94};
95
96/*
97 * Logical endpoint structure
98 */
99struct lpc32xx_ep {
100 struct usb_ep ep;
101 struct list_head queue;
102 struct lpc32xx_udc *udc;
103
104 u32 hwep_num_base; /* Physical hardware EP */
105 u32 hwep_num; /* Maps to hardware endpoint */
106 u32 maxpacket;
107 u32 lep;
108
109 bool is_in;
110 bool req_pending;
111 u32 eptype;
112
113 u32 totalints;
114
115 bool wedge;
24a28e42
RS		 116};
117
2a60f5ea
AB		 118enum atx_type {
119 ISP1301,
120 STOTG04,
121};
122
24a28e42
RS		 123/*
124 * Common UDC structure
125 */
126struct lpc32xx_udc {
127 struct usb_gadget gadget;
128 struct usb_gadget_driver *driver;
129 struct platform_device *pdev;
130 struct device *dev;
131 struct dentry *pde;
132 spinlock_t lock;
133 struct i2c_client *isp1301_i2c_client;
134
135 /* Board and device specific */
136 struct lpc32xx_usbd_cfg *board;
24a28e42
RS		 137 void __iomem *udp_baseaddr;
138 int udp_irq[4];
24a28e42
RS		 139 struct clk *usb_slv_clk;
140
141 /* DMA support */
142 u32 *udca_v_base;
143 u32 udca_p_base;
144 struct dma_pool *dd_cache;
145
146 /* Common EP and control data */
147 u32 enabled_devints;
148 u32 enabled_hwepints;
149 u32 dev_status;
150 u32 realized_eps;
151
152 /* VBUS detection, pullup, and power flags */
153 u8 vbus;
154 u8 last_vbus;
155 int pullup;
156 int poweron;
2a60f5ea 157 enum atx_type atx;
24a28e42
RS		 158
159 /* Work queues related to I2C support */
160 struct work_struct pullup_job;
24a28e42
RS		 161 struct work_struct power_job;
162
163 /* USB device peripheral - various */
164 struct lpc32xx_ep ep[NUM_ENDPOINTS];
165 bool enabled;
166 bool clocked;
167 bool suspended;
24a28e42
RS		 168 int ep0state;
169 atomic_t enabled_ep_cnt;
170 wait_queue_head_t ep_disable_wait_queue;
171};
172
173/*
174 * Endpoint request
175 */
176struct lpc32xx_request {
177 struct usb_request req;
178 struct list_head queue;
179 struct lpc32xx_usbd_dd_gad *dd_desc_ptr;
180 bool mapped;
181 bool send_zlp;
182};
183
184static inline struct lpc32xx_udc *to_udc(struct usb_gadget *g)
185{
186 return container_of(g, struct lpc32xx_udc, gadget);
187}
188
189#define ep_dbg(epp, fmt, arg...) \
190 dev_dbg(epp->udc->dev, "%s: " fmt, __func__, ## arg)
191#define ep_err(epp, fmt, arg...) \
192 dev_err(epp->udc->dev, "%s: " fmt, __func__, ## arg)
193#define ep_info(epp, fmt, arg...) \
194 dev_info(epp->udc->dev, "%s: " fmt, __func__, ## arg)
195#define ep_warn(epp, fmt, arg...) \
196 dev_warn(epp->udc->dev, "%s:" fmt, __func__, ## arg)
197
198#define UDCA_BUFF_SIZE (128)
199
24a28e42
RS		 200/**********************************************************************
201 * USB device controller register offsets
202 **********************************************************************/
203
204#define USBD_DEVINTST(x) ((x) + 0x200)
205#define USBD_DEVINTEN(x) ((x) + 0x204)
206#define USBD_DEVINTCLR(x) ((x) + 0x208)
207#define USBD_DEVINTSET(x) ((x) + 0x20C)
208#define USBD_CMDCODE(x) ((x) + 0x210)
209#define USBD_CMDDATA(x) ((x) + 0x214)
210#define USBD_RXDATA(x) ((x) + 0x218)
211#define USBD_TXDATA(x) ((x) + 0x21C)
212#define USBD_RXPLEN(x) ((x) + 0x220)
213#define USBD_TXPLEN(x) ((x) + 0x224)
214#define USBD_CTRL(x) ((x) + 0x228)
215#define USBD_DEVINTPRI(x) ((x) + 0x22C)
216#define USBD_EPINTST(x) ((x) + 0x230)
217#define USBD_EPINTEN(x) ((x) + 0x234)
218#define USBD_EPINTCLR(x) ((x) + 0x238)
219#define USBD_EPINTSET(x) ((x) + 0x23C)
220#define USBD_EPINTPRI(x) ((x) + 0x240)
221#define USBD_REEP(x) ((x) + 0x244)
222#define USBD_EPIND(x) ((x) + 0x248)
223#define USBD_EPMAXPSIZE(x) ((x) + 0x24C)
224/* DMA support registers only below */
225/* Set, clear, or get enabled state of the DMA request status. If
226 * enabled, an IN or OUT token will start a DMA transfer for the EP */
227#define USBD_DMARST(x) ((x) + 0x250)
228#define USBD_DMARCLR(x) ((x) + 0x254)
229#define USBD_DMARSET(x) ((x) + 0x258)
230/* DMA UDCA head pointer */
231#define USBD_UDCAH(x) ((x) + 0x280)
232/* EP DMA status, enable, and disable. This is used to specifically
233 * enabled or disable DMA for a specific EP */
234#define USBD_EPDMAST(x) ((x) + 0x284)
235#define USBD_EPDMAEN(x) ((x) + 0x288)
236#define USBD_EPDMADIS(x) ((x) + 0x28C)
237/* DMA master interrupts enable and pending interrupts */
238#define USBD_DMAINTST(x) ((x) + 0x290)
239#define USBD_DMAINTEN(x) ((x) + 0x294)
240/* DMA end of transfer interrupt enable, disable, status */
241#define USBD_EOTINTST(x) ((x) + 0x2A0)
242#define USBD_EOTINTCLR(x) ((x) + 0x2A4)
243#define USBD_EOTINTSET(x) ((x) + 0x2A8)
244/* New DD request interrupt enable, disable, status */
245#define USBD_NDDRTINTST(x) ((x) + 0x2AC)
246#define USBD_NDDRTINTCLR(x) ((x) + 0x2B0)
247#define USBD_NDDRTINTSET(x) ((x) + 0x2B4)
248/* DMA error interrupt enable, disable, status */
249#define USBD_SYSERRTINTST(x) ((x) + 0x2B8)
250#define USBD_SYSERRTINTCLR(x) ((x) + 0x2BC)
251#define USBD_SYSERRTINTSET(x) ((x) + 0x2C0)
252
253/**********************************************************************
254 * USBD_DEVINTST/USBD_DEVINTEN/USBD_DEVINTCLR/USBD_DEVINTSET/
255 * USBD_DEVINTPRI register definitions
256 **********************************************************************/
257#define USBD_ERR_INT (1 << 9)
258#define USBD_EP_RLZED (1 << 8)
259#define USBD_TXENDPKT (1 << 7)
260#define USBD_RXENDPKT (1 << 6)
261#define USBD_CDFULL (1 << 5)
262#define USBD_CCEMPTY (1 << 4)
263#define USBD_DEV_STAT (1 << 3)
264#define USBD_EP_SLOW (1 << 2)
265#define USBD_EP_FAST (1 << 1)
266#define USBD_FRAME (1 << 0)
267
268/**********************************************************************
269 * USBD_EPINTST/USBD_EPINTEN/USBD_EPINTCLR/USBD_EPINTSET/
270 * USBD_EPINTPRI register definitions
271 **********************************************************************/
272/* End point selection macro (RX) */
273#define USBD_RX_EP_SEL(e) (1 << ((e) << 1))
274
275/* End point selection macro (TX) */
276#define USBD_TX_EP_SEL(e) (1 << (((e) << 1) + 1))
277
278/**********************************************************************
279 * USBD_REEP/USBD_DMARST/USBD_DMARCLR/USBD_DMARSET/USBD_EPDMAST/
280 * USBD_EPDMAEN/USBD_EPDMADIS/
281 * USBD_NDDRTINTST/USBD_NDDRTINTCLR/USBD_NDDRTINTSET/
282 * USBD_EOTINTST/USBD_EOTINTCLR/USBD_EOTINTSET/
283 * USBD_SYSERRTINTST/USBD_SYSERRTINTCLR/USBD_SYSERRTINTSET
284 * register definitions
285 **********************************************************************/
286/* Endpoint selection macro */
287#define USBD_EP_SEL(e) (1 << (e))
288
289/**********************************************************************
290 * SBD_DMAINTST/USBD_DMAINTEN
291 **********************************************************************/
292#define USBD_SYS_ERR_INT (1 << 2)
293#define USBD_NEW_DD_INT (1 << 1)
294#define USBD_EOT_INT (1 << 0)
295
296/**********************************************************************
297 * USBD_RXPLEN register definitions
298 **********************************************************************/
299#define USBD_PKT_RDY (1 << 11)
300#define USBD_DV (1 << 10)
301#define USBD_PK_LEN_MASK 0x3FF
302
303/**********************************************************************
304 * USBD_CTRL register definitions
305 **********************************************************************/
306#define USBD_LOG_ENDPOINT(e) ((e) << 2)
307#define USBD_WR_EN (1 << 1)
308#define USBD_RD_EN (1 << 0)
309
310/**********************************************************************
311 * USBD_CMDCODE register definitions
312 **********************************************************************/
313#define USBD_CMD_CODE(c) ((c) << 16)
314#define USBD_CMD_PHASE(p) ((p) << 8)
315
316/**********************************************************************
317 * USBD_DMARST/USBD_DMARCLR/USBD_DMARSET register definitions
318 **********************************************************************/
319#define USBD_DMAEP(e) (1 << (e))
320
321/* DD (DMA Descriptor) structure, requires word alignment */
322struct lpc32xx_usbd_dd {
323 u32 *dd_next;
324 u32 dd_setup;
325 u32 dd_buffer_addr;
326 u32 dd_status;
327 u32 dd_iso_ps_mem_addr;
328};
329
330/* dd_setup bit defines */
331#define DD_SETUP_ATLE_DMA_MODE 0x01
332#define DD_SETUP_NEXT_DD_VALID 0x04
333#define DD_SETUP_ISO_EP 0x10
334#define DD_SETUP_PACKETLEN(n) (((n) & 0x7FF) << 5)
335#define DD_SETUP_DMALENBYTES(n) (((n) & 0xFFFF) << 16)
336
337/* dd_status bit defines */
338#define DD_STATUS_DD_RETIRED 0x01
339#define DD_STATUS_STS_MASK 0x1E
340#define DD_STATUS_STS_NS 0x00 /* Not serviced */
341#define DD_STATUS_STS_BS 0x02 /* Being serviced */
342#define DD_STATUS_STS_NC 0x04 /* Normal completion */
343#define DD_STATUS_STS_DUR 0x06 /* Data underrun (short packet) */
344#define DD_STATUS_STS_DOR 0x08 /* Data overrun */
345#define DD_STATUS_STS_SE 0x12 /* System error */
346#define DD_STATUS_PKT_VAL 0x20 /* Packet valid */
347#define DD_STATUS_LSB_EX 0x40 /* LS byte extracted (ATLE) */
348#define DD_STATUS_MSB_EX 0x80 /* MS byte extracted (ATLE) */
349#define DD_STATUS_MLEN(n) (((n) >> 8) & 0x3F)
350#define DD_STATUS_CURDMACNT(n) (((n) >> 16) & 0xFFFF)
351
352/*
353 *
354 * Protocol engine bits below
355 *
356 */
357/* Device Interrupt Bit Definitions */
358#define FRAME_INT 0x00000001
359#define EP_FAST_INT 0x00000002
360#define EP_SLOW_INT 0x00000004
361#define DEV_STAT_INT 0x00000008
362#define CCEMTY_INT 0x00000010
363#define CDFULL_INT 0x00000020
364#define RxENDPKT_INT 0x00000040
365#define TxENDPKT_INT 0x00000080
366#define EP_RLZED_INT 0x00000100
367#define ERR_INT 0x00000200
368
369/* Rx & Tx Packet Length Definitions */
370#define PKT_LNGTH_MASK 0x000003FF
371#define PKT_DV 0x00000400
372#define PKT_RDY 0x00000800
373
374/* USB Control Definitions */
375#define CTRL_RD_EN 0x00000001
376#define CTRL_WR_EN 0x00000002
377
378/* Command Codes */
379#define CMD_SET_ADDR 0x00D00500
380#define CMD_CFG_DEV 0x00D80500
381#define CMD_SET_MODE 0x00F30500
382#define CMD_RD_FRAME 0x00F50500
383#define DAT_RD_FRAME 0x00F50200
384#define CMD_RD_TEST 0x00FD0500
385#define DAT_RD_TEST 0x00FD0200
386#define CMD_SET_DEV_STAT 0x00FE0500
387#define CMD_GET_DEV_STAT 0x00FE0500
388#define DAT_GET_DEV_STAT 0x00FE0200
389#define CMD_GET_ERR_CODE 0x00FF0500
390#define DAT_GET_ERR_CODE 0x00FF0200
391#define CMD_RD_ERR_STAT 0x00FB0500
392#define DAT_RD_ERR_STAT 0x00FB0200
393#define DAT_WR_BYTE(x) (0x00000100 | ((x) << 16))
394#define CMD_SEL_EP(x) (0x00000500 | ((x) << 16))
395#define DAT_SEL_EP(x) (0x00000200 | ((x) << 16))
396#define CMD_SEL_EP_CLRI(x) (0x00400500 | ((x) << 16))
397#define DAT_SEL_EP_CLRI(x) (0x00400200 | ((x) << 16))
398#define CMD_SET_EP_STAT(x) (0x00400500 | ((x) << 16))
399#define CMD_CLR_BUF 0x00F20500
400#define DAT_CLR_BUF 0x00F20200
401#define CMD_VALID_BUF 0x00FA0500
402
403/* Device Address Register Definitions */
404#define DEV_ADDR_MASK 0x7F
405#define DEV_EN 0x80
406
407/* Device Configure Register Definitions */
408#define CONF_DVICE 0x01
409
410/* Device Mode Register Definitions */
411#define AP_CLK 0x01
412#define INAK_CI 0x02
413#define INAK_CO 0x04
414#define INAK_II 0x08
415#define INAK_IO 0x10
416#define INAK_BI 0x20
417#define INAK_BO 0x40
418
419/* Device Status Register Definitions */
420#define DEV_CON 0x01
421#define DEV_CON_CH 0x02
422#define DEV_SUS 0x04
423#define DEV_SUS_CH 0x08
424#define DEV_RST 0x10
425
426/* Error Code Register Definitions */
427#define ERR_EC_MASK 0x0F
428#define ERR_EA 0x10
429
430/* Error Status Register Definitions */
431#define ERR_PID 0x01
432#define ERR_UEPKT 0x02
433#define ERR_DCRC 0x04
434#define ERR_TIMOUT 0x08
435#define ERR_EOP 0x10
436#define ERR_B_OVRN 0x20
437#define ERR_BTSTF 0x40
438#define ERR_TGL 0x80
439
440/* Endpoint Select Register Definitions */
441#define EP_SEL_F 0x01
442#define EP_SEL_ST 0x02
443#define EP_SEL_STP 0x04
444#define EP_SEL_PO 0x08
445#define EP_SEL_EPN 0x10
446#define EP_SEL_B_1_FULL 0x20
447#define EP_SEL_B_2_FULL 0x40
448
449/* Endpoint Status Register Definitions */
450#define EP_STAT_ST 0x01
451#define EP_STAT_DA 0x20
452#define EP_STAT_RF_MO 0x40
453#define EP_STAT_CND_ST 0x80
454
455/* Clear Buffer Register Definitions */
456#define CLR_BUF_PO 0x01
457
458/* DMA Interrupt Bit Definitions */
459#define EOT_INT 0x01
460#define NDD_REQ_INT 0x02
461#define SYS_ERR_INT 0x04
462
463#define DRIVER_VERSION "1.03"
464static const char driver_name[] = "lpc32xx_udc";
465
466/*
467 *
468 * proc interface support
469 *
470 */
471#ifdef CONFIG_USB_GADGET_DEBUG_FILES
472static char *epnames[] = {"INT", "ISO", "BULK", "CTRL"};
473static const char debug_filename[] = "driver/udc";
474
475static void proc_ep_show(struct seq_file *s, struct lpc32xx_ep *ep)
476{
477 struct lpc32xx_request *req;
478
479 seq_printf(s, "\n");
480 seq_printf(s, "%12s, maxpacket %4d %3s",
481 ep->ep.name, ep->ep.maxpacket,
482 ep->is_in ? "in" : "out");
483 seq_printf(s, " type %4s", epnames[ep->eptype]);
484 seq_printf(s, " ints: %12d", ep->totalints);
485
486 if (list_empty(&ep->queue))
487 seq_printf(s, "\t(queue empty)\n");
488 else {
489 list_for_each_entry(req, &ep->queue, queue) {
490 u32 length = req->req.actual;
491
492 seq_printf(s, "\treq %p len %d/%d buf %p\n",
493 &req->req, length,
494 req->req.length, req->req.buf);
495 }
496 }
497}
498
499static int proc_udc_show(struct seq_file *s, void *unused)
500{
501 struct lpc32xx_udc *udc = s->private;
502 struct lpc32xx_ep *ep;
503 unsigned long flags;
504
505 seq_printf(s, "%s: version %s\n", driver_name, DRIVER_VERSION);
506
507 spin_lock_irqsave(&udc->lock, flags);
508
509 seq_printf(s, "vbus %s, pullup %s, %s powered%s, gadget %s\n\n",
510 udc->vbus ? "present" : "off",
511 udc->enabled ? (udc->vbus ? "active" : "enabled") :
512 "disabled",
d60d9392 513 udc->gadget.is_selfpowered ? "self" : "VBUS",
24a28e42
RS		 514 udc->suspended ? ", suspended" : "",
515 udc->driver ? udc->driver->driver.name : "(none)");
516
517 if (udc->enabled && udc->vbus) {
518 proc_ep_show(s, &udc->ep[0]);
78ca9139
RS		 519 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list)
520 proc_ep_show(s, ep);
24a28e42
RS		 521 }
522
523 spin_unlock_irqrestore(&udc->lock, flags);
524
525 return 0;
526}
527
528static int proc_udc_open(struct inode *inode, struct file *file)
529{
d9dda78b 530 return single_open(file, proc_udc_show, PDE_DATA(inode));
24a28e42
RS		 531}
532
533static const struct file_operations proc_ops = {
534 .owner = THIS_MODULE,
535 .open = proc_udc_open,
536 .read = seq_read,
537 .llseek = seq_lseek,
538 .release = single_release,
539};
540
541static void create_debug_file(struct lpc32xx_udc *udc)
542{
543 udc->pde = debugfs_create_file(debug_filename, 0, NULL, udc, &proc_ops);
544}
545
546static void remove_debug_file(struct lpc32xx_udc *udc)
547{
23fba80a 548 debugfs_remove(udc->pde);
24a28e42
RS		 549}
550
551#else
552static inline void create_debug_file(struct lpc32xx_udc *udc) {}
553static inline void remove_debug_file(struct lpc32xx_udc *udc) {}
554#endif
555
556/* Primary initialization sequence for the ISP1301 transceiver */
557static void isp1301_udc_configure(struct lpc32xx_udc *udc)
558{
2a60f5ea
AB		 559 u8 value;
560 s32 vendor, product;
561
562 vendor = i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x00);
563 product = i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x02);
564
565 if (vendor == 0x0483 && product == 0xa0c4)
566 udc->atx = STOTG04;
567
24a28e42
RS		 568 /* LPC32XX only supports DAT_SE0 USB mode */
569 /* This sequence is important */
570
571 /* Disable transparent UART mode first */
572 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
573 (ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR),
574 MC1_UART_EN);
575
576 /* Set full speed and SE0 mode */
577 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
578 (ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), ~0);
579 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
580 ISP1301_I2C_MODE_CONTROL_1, (MC1_SPEED_REG | MC1_DAT_SE0));
581
582 /*
583 * The PSW_OE enable bit state is reversed in the ISP1301 User's Guide
584 */
585 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
586 (ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR), ~0);
2a60f5ea
AB		 587
588 value = MC2_BI_DI;
589 if (udc->atx != STOTG04)
590 value |= MC2_SPD_SUSP_CTRL;
24a28e42 591 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2a60f5ea 592 ISP1301_I2C_MODE_CONTROL_2, value);
24a28e42
RS		 593
594 /* Driver VBUS_DRV high or low depending on board setup */
595 if (udc->board->vbus_drv_pol != 0)
596 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
597 ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DRV);
598 else
599 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
600 ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
601 OTG1_VBUS_DRV);
602
603 /* Bi-directional mode with suspend control
604 * Enable both pulldowns for now - the pullup will be enable when VBUS
605 * is detected */
606 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
607 (ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), ~0);
608 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
609 ISP1301_I2C_OTG_CONTROL_1,
610 (0 | OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN));
611
612 /* Discharge VBUS (just in case) */
613 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
614 ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DISCHRG);
615 msleep(1);
616 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
617 (ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR),
618 OTG1_VBUS_DISCHRG);
619
24a28e42
RS		 620 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
621 ISP1301_I2C_INTERRUPT_LATCH | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
c67d4262 622
24a28e42
RS		 623 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
624 ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
24a28e42
RS		 625 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
626 ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
24a28e42 627
2a60f5ea
AB		 628 dev_info(udc->dev, "ISP1301 Vendor ID : 0x%04x\n", vendor);
629 dev_info(udc->dev, "ISP1301 Product ID : 0x%04x\n", product);
24a28e42
RS		 630 dev_info(udc->dev, "ISP1301 Version ID : 0x%04x\n",
631 i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x14));
2a60f5ea 632
24a28e42
RS		 633}
634
635/* Enables or disables the USB device pullup via the ISP1301 transceiver */
636static void isp1301_pullup_set(struct lpc32xx_udc *udc)
637{
638 if (udc->pullup)
639 /* Enable pullup for bus signalling */
640 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
641 ISP1301_I2C_OTG_CONTROL_1, OTG1_DP_PULLUP);
642 else
643 /* Enable pullup for bus signalling */
644 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
645 ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
646 OTG1_DP_PULLUP);
647}
648
649static void pullup_work(struct work_struct *work)
650{
651 struct lpc32xx_udc *udc =
652 container_of(work, struct lpc32xx_udc, pullup_job);
653
654 isp1301_pullup_set(udc);
655}
656
657static void isp1301_pullup_enable(struct lpc32xx_udc *udc, int en_pullup,
658 int block)
659{
660 if (en_pullup == udc->pullup)
661 return;
662
663 udc->pullup = en_pullup;
664 if (block)
665 isp1301_pullup_set(udc);
666 else
667 /* defer slow i2c pull up setting */
668 schedule_work(&udc->pullup_job);
669}
670
671#ifdef CONFIG_PM
672/* Powers up or down the ISP1301 transceiver */
673static void isp1301_set_powerstate(struct lpc32xx_udc *udc, int enable)
674{
2a60f5ea
AB		 675 /* There is no "global power down" register for stotg04 */
676 if (udc->atx == STOTG04)
677 return;
678
24a28e42
RS		 679 if (enable != 0)
680 /* Power up ISP1301 - this ISP1301 will automatically wakeup
681 when VBUS is detected */
682 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
683 ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR,
684 MC2_GLOBAL_PWR_DN);
685 else
686 /* Power down ISP1301 */
687 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
688 ISP1301_I2C_MODE_CONTROL_2, MC2_GLOBAL_PWR_DN);
689}
690
691static void power_work(struct work_struct *work)
692{
693 struct lpc32xx_udc *udc =
694 container_of(work, struct lpc32xx_udc, power_job);
695
696 isp1301_set_powerstate(udc, udc->poweron);
697}
698#endif
699
700/*
701 *
702 * USB protocol engine command/data read/write helper functions
703 *
704 */
705/* Issues a single command to the USB device state machine */
706static void udc_protocol_cmd_w(struct lpc32xx_udc *udc, u32 cmd)
707{
708 u32 pass = 0;
709 int to;
710
711 /* EP may lock on CLRI if this read isn't done */
712 u32 tmp = readl(USBD_DEVINTST(udc->udp_baseaddr));
713 (void) tmp;
714
715 while (pass == 0) {
716 writel(USBD_CCEMPTY, USBD_DEVINTCLR(udc->udp_baseaddr));
717
718 /* Write command code */
719 writel(cmd, USBD_CMDCODE(udc->udp_baseaddr));
720 to = 10000;
721 while (((readl(USBD_DEVINTST(udc->udp_baseaddr)) &
722 USBD_CCEMPTY) == 0) && (to > 0)) {
723 to--;
724 }
725
726 if (to > 0)
727 pass = 1;
728
729 cpu_relax();
730 }
731}
732
733/* Issues 2 commands (or command and data) to the USB device state machine */
734static inline void udc_protocol_cmd_data_w(struct lpc32xx_udc *udc, u32 cmd,
735 u32 data)
736{
737 udc_protocol_cmd_w(udc, cmd);
738 udc_protocol_cmd_w(udc, data);
739}
740
741/* Issues a single command to the USB device state machine and reads
742 * response data */
743static u32 udc_protocol_cmd_r(struct lpc32xx_udc *udc, u32 cmd)
744{
745 u32 tmp;
746 int to = 1000;
747
748 /* Write a command and read data from the protocol engine */
749 writel((USBD_CDFULL | USBD_CCEMPTY),
750 USBD_DEVINTCLR(udc->udp_baseaddr));
751
752 /* Write command code */
753 udc_protocol_cmd_w(udc, cmd);
754
755 tmp = readl(USBD_DEVINTST(udc->udp_baseaddr));
756 while ((!(readl(USBD_DEVINTST(udc->udp_baseaddr)) & USBD_CDFULL))
757 && (to > 0))
758 to--;
759 if (!to)
760 dev_dbg(udc->dev,
761 "Protocol engine didn't receive response (CDFULL)\n");
762
763 return readl(USBD_CMDDATA(udc->udp_baseaddr));
764}
765
766/*
767 *
768 * USB device interrupt mask support functions
769 *
770 */
771/* Enable one or more USB device interrupts */
772static inline void uda_enable_devint(struct lpc32xx_udc *udc, u32 devmask)
773{
774 udc->enabled_devints |= devmask;
775 writel(udc->enabled_devints, USBD_DEVINTEN(udc->udp_baseaddr));
776}
777
778/* Disable one or more USB device interrupts */
779static inline void uda_disable_devint(struct lpc32xx_udc *udc, u32 mask)
780{
781 udc->enabled_devints &= ~mask;
782 writel(udc->enabled_devints, USBD_DEVINTEN(udc->udp_baseaddr));
783}
784
785/* Clear one or more USB device interrupts */
786static inline void uda_clear_devint(struct lpc32xx_udc *udc, u32 mask)
787{
788 writel(mask, USBD_DEVINTCLR(udc->udp_baseaddr));
789}
790
791/*
792 *
793 * Endpoint interrupt disable/enable functions
794 *
795 */
796/* Enable one or more USB endpoint interrupts */
797static void uda_enable_hwepint(struct lpc32xx_udc *udc, u32 hwep)
798{
799 udc->enabled_hwepints |= (1 << hwep);
800 writel(udc->enabled_hwepints, USBD_EPINTEN(udc->udp_baseaddr));
801}
802
803/* Disable one or more USB endpoint interrupts */
804static void uda_disable_hwepint(struct lpc32xx_udc *udc, u32 hwep)
805{
806 udc->enabled_hwepints &= ~(1 << hwep);
807 writel(udc->enabled_hwepints, USBD_EPINTEN(udc->udp_baseaddr));
808}
809
810/* Clear one or more USB endpoint interrupts */
811static inline void uda_clear_hwepint(struct lpc32xx_udc *udc, u32 hwep)
812{
813 writel((1 << hwep), USBD_EPINTCLR(udc->udp_baseaddr));
814}
815
816/* Enable DMA for the HW channel */
817static inline void udc_ep_dma_enable(struct lpc32xx_udc *udc, u32 hwep)
818{
819 writel((1 << hwep), USBD_EPDMAEN(udc->udp_baseaddr));
820}
821
822/* Disable DMA for the HW channel */
823static inline void udc_ep_dma_disable(struct lpc32xx_udc *udc, u32 hwep)
824{
825 writel((1 << hwep), USBD_EPDMADIS(udc->udp_baseaddr));
826}
827
828/*
829 *
830 * Endpoint realize/unrealize functions
831 *
832 */
833/* Before an endpoint can be used, it needs to be realized
834 * in the USB protocol engine - this realizes the endpoint.
835 * The interrupt (FIFO or DMA) is not enabled with this function */
836static void udc_realize_hwep(struct lpc32xx_udc *udc, u32 hwep,
837 u32 maxpacket)
838{
839 int to = 1000;
840
841 writel(USBD_EP_RLZED, USBD_DEVINTCLR(udc->udp_baseaddr));
842 writel(hwep, USBD_EPIND(udc->udp_baseaddr));
843 udc->realized_eps |= (1 << hwep);
844 writel(udc->realized_eps, USBD_REEP(udc->udp_baseaddr));
845 writel(maxpacket, USBD_EPMAXPSIZE(udc->udp_baseaddr));
846
847 /* Wait until endpoint is realized in hardware */
848 while ((!(readl(USBD_DEVINTST(udc->udp_baseaddr)) &
849 USBD_EP_RLZED)) && (to > 0))
850 to--;
851 if (!to)
852 dev_dbg(udc->dev, "EP not correctly realized in hardware\n");
853
854 writel(USBD_EP_RLZED, USBD_DEVINTCLR(udc->udp_baseaddr));
855}
856
857/* Unrealize an EP */
858static void udc_unrealize_hwep(struct lpc32xx_udc *udc, u32 hwep)
859{
860 udc->realized_eps &= ~(1 << hwep);
861 writel(udc->realized_eps, USBD_REEP(udc->udp_baseaddr));
862}
863
864/*
865 *
866 * Endpoint support functions
867 *
868 */
869/* Select and clear endpoint interrupt */
870static u32 udc_selep_clrint(struct lpc32xx_udc *udc, u32 hwep)
871{
872 udc_protocol_cmd_w(udc, CMD_SEL_EP_CLRI(hwep));
873 return udc_protocol_cmd_r(udc, DAT_SEL_EP_CLRI(hwep));
874}
875
876/* Disables the endpoint in the USB protocol engine */
877static void udc_disable_hwep(struct lpc32xx_udc *udc, u32 hwep)
878{
879 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep),
880 DAT_WR_BYTE(EP_STAT_DA));
881}
882
883/* Stalls the endpoint - endpoint will return STALL */
884static void udc_stall_hwep(struct lpc32xx_udc *udc, u32 hwep)
885{
886 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep),
887 DAT_WR_BYTE(EP_STAT_ST));
888}
889
890/* Clear stall or reset endpoint */
891static void udc_clrstall_hwep(struct lpc32xx_udc *udc, u32 hwep)
892{
893 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep),
894 DAT_WR_BYTE(0));
895}
896
897/* Select an endpoint for endpoint status, clear, validate */
898static void udc_select_hwep(struct lpc32xx_udc *udc, u32 hwep)
899{
900 udc_protocol_cmd_w(udc, CMD_SEL_EP(hwep));
901}
902
903/*
904 *
905 * Endpoint buffer management functions
906 *
907 */
908/* Clear the current endpoint's buffer */
909static void udc_clr_buffer_hwep(struct lpc32xx_udc *udc, u32 hwep)
910{
911 udc_select_hwep(udc, hwep);
912 udc_protocol_cmd_w(udc, CMD_CLR_BUF);
913}
914
915/* Validate the current endpoint's buffer */
916static void udc_val_buffer_hwep(struct lpc32xx_udc *udc, u32 hwep)
917{
918 udc_select_hwep(udc, hwep);
919 udc_protocol_cmd_w(udc, CMD_VALID_BUF);
920}
921
922static inline u32 udc_clearep_getsts(struct lpc32xx_udc *udc, u32 hwep)
923{
924 /* Clear EP interrupt */
925 uda_clear_hwepint(udc, hwep);
926 return udc_selep_clrint(udc, hwep);
927}
928
929/*
930 *
931 * USB EP DMA support
932 *
933 */
934/* Allocate a DMA Descriptor */
935static struct lpc32xx_usbd_dd_gad *udc_dd_alloc(struct lpc32xx_udc *udc)
936{
937 dma_addr_t dma;
938 struct lpc32xx_usbd_dd_gad *dd;
939
fbc318af 940 dd = dma_pool_alloc(udc->dd_cache, GFP_ATOMIC | GFP_DMA, &dma);
24a28e42
RS		 941 if (dd)
942 dd->this_dma = dma;
943
944 return dd;
945}
946
947/* Free a DMA Descriptor */
948static void udc_dd_free(struct lpc32xx_udc *udc, struct lpc32xx_usbd_dd_gad *dd)
949{
950 dma_pool_free(udc->dd_cache, dd, dd->this_dma);
951}
952
953/*
954 *
955 * USB setup and shutdown functions
956 *
957 */
958/* Enables or disables most of the USB system clocks when low power mode is
959 * needed. Clocks are typically started on a connection event, and disabled
960 * when a cable is disconnected */
24a28e42
RS		 961static void udc_clk_set(struct lpc32xx_udc *udc, int enable)
962{
24a28e42
RS		 963 if (enable != 0) {
964 if (udc->clocked)
965 return;
966
967 udc->clocked = 1;
59e05272 968 clk_prepare_enable(udc->usb_slv_clk);
24a28e42
RS		 969 } else {
970 if (!udc->clocked)
971 return;
972
973 udc->clocked = 0;
59e05272 974 clk_disable_unprepare(udc->usb_slv_clk);
24a28e42
RS		 975 }
976}
977
978/* Set/reset USB device address */
979static void udc_set_address(struct lpc32xx_udc *udc, u32 addr)
980{
981 /* Address will be latched at the end of the status phase, or
982 latched immediately if function is called twice */
983 udc_protocol_cmd_data_w(udc, CMD_SET_ADDR,
984 DAT_WR_BYTE(DEV_EN | addr));
985}
986
987/* Setup up a IN request for DMA transfer - this consists of determining the
988 * list of DMA addresses for the transfer, allocating DMA Descriptors,
989 * installing the DD into the UDCA, and then enabling the DMA for that EP */
990static int udc_ep_in_req_dma(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
991{
992 struct lpc32xx_request *req;
993 u32 hwep = ep->hwep_num;
994
995 ep->req_pending = 1;
996
997 /* There will always be a request waiting here */
998 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
999
1000 /* Place the DD Descriptor into the UDCA */
1001 udc->udca_v_base[hwep] = req->dd_desc_ptr->this_dma;
1002
1003 /* Enable DMA and interrupt for the HW EP */
1004 udc_ep_dma_enable(udc, hwep);
1005
1006 /* Clear ZLP if last packet is not of MAXP size */
1007 if (req->req.length % ep->ep.maxpacket)
1008 req->send_zlp = 0;
1009
1010 return 0;
1011}
1012
1013/* Setup up a OUT request for DMA transfer - this consists of determining the
1014 * list of DMA addresses for the transfer, allocating DMA Descriptors,
1015 * installing the DD into the UDCA, and then enabling the DMA for that EP */
1016static int udc_ep_out_req_dma(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
1017{
1018 struct lpc32xx_request *req;
1019 u32 hwep = ep->hwep_num;
1020
1021 ep->req_pending = 1;
1022
1023 /* There will always be a request waiting here */
1024 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
1025
1026 /* Place the DD Descriptor into the UDCA */
1027 udc->udca_v_base[hwep] = req->dd_desc_ptr->this_dma;
1028
1029 /* Enable DMA and interrupt for the HW EP */
1030 udc_ep_dma_enable(udc, hwep);
1031 return 0;
1032}
1033
1034static void udc_disable(struct lpc32xx_udc *udc)
1035{
1036 u32 i;
1037
1038 /* Disable device */
1039 udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(0));
1040 udc_protocol_cmd_data_w(udc, CMD_SET_DEV_STAT, DAT_WR_BYTE(0));
1041
1042 /* Disable all device interrupts (including EP0) */
1043 uda_disable_devint(udc, 0x3FF);
1044
1045 /* Disable and reset all endpoint interrupts */
1046 for (i = 0; i < 32; i++) {
1047 uda_disable_hwepint(udc, i);
1048 uda_clear_hwepint(udc, i);
1049 udc_disable_hwep(udc, i);
1050 udc_unrealize_hwep(udc, i);
1051 udc->udca_v_base[i] = 0;
1052
1053 /* Disable and clear all interrupts and DMA */
1054 udc_ep_dma_disable(udc, i);
1055 writel((1 << i), USBD_EOTINTCLR(udc->udp_baseaddr));
1056 writel((1 << i), USBD_NDDRTINTCLR(udc->udp_baseaddr));
1057 writel((1 << i), USBD_SYSERRTINTCLR(udc->udp_baseaddr));
1058 writel((1 << i), USBD_DMARCLR(udc->udp_baseaddr));
1059 }
1060
1061 /* Disable DMA interrupts */
1062 writel(0, USBD_DMAINTEN(udc->udp_baseaddr));
1063
1064 writel(0, USBD_UDCAH(udc->udp_baseaddr));
1065}
1066
1067static void udc_enable(struct lpc32xx_udc *udc)
1068{
1069 u32 i;
1070 struct lpc32xx_ep *ep = &udc->ep[0];
1071
1072 /* Start with known state */
1073 udc_disable(udc);
1074
1075 /* Enable device */
1076 udc_protocol_cmd_data_w(udc, CMD_SET_DEV_STAT, DAT_WR_BYTE(DEV_CON));
1077
1078 /* EP interrupts on high priority, FRAME interrupt on low priority */
1079 writel(USBD_EP_FAST, USBD_DEVINTPRI(udc->udp_baseaddr));
1080 writel(0xFFFF, USBD_EPINTPRI(udc->udp_baseaddr));
1081
1082 /* Clear any pending device interrupts */
1083 writel(0x3FF, USBD_DEVINTCLR(udc->udp_baseaddr));
1084
1085 /* Setup UDCA - not yet used (DMA) */
1086 writel(udc->udca_p_base, USBD_UDCAH(udc->udp_baseaddr));
1087
1088 /* Only enable EP0 in and out for now, EP0 only works in FIFO mode */
1089 for (i = 0; i <= 1; i++) {
1090 udc_realize_hwep(udc, i, ep->ep.maxpacket);
1091 uda_enable_hwepint(udc, i);
1092 udc_select_hwep(udc, i);
1093 udc_clrstall_hwep(udc, i);
1094 udc_clr_buffer_hwep(udc, i);
1095 }
1096
1097 /* Device interrupt setup */
1098 uda_clear_devint(udc, (USBD_ERR_INT | USBD_DEV_STAT | USBD_EP_SLOW |
1099 USBD_EP_FAST));
1100 uda_enable_devint(udc, (USBD_ERR_INT | USBD_DEV_STAT | USBD_EP_SLOW |
1101 USBD_EP_FAST));
1102
1103 /* Set device address to 0 - called twice to force a latch in the USB
1104 engine without the need of a setup packet status closure */
1105 udc_set_address(udc, 0);
1106 udc_set_address(udc, 0);
1107
1108 /* Enable master DMA interrupts */
1109 writel((USBD_SYS_ERR_INT | USBD_EOT_INT),
1110 USBD_DMAINTEN(udc->udp_baseaddr));
1111
1112 udc->dev_status = 0;
1113}
1114
1115/*
1116 *
1117 * USB device board specific events handled via callbacks
1118 *
1119 */
1120/* Connection change event - notify board function of change */
1121static void uda_power_event(struct lpc32xx_udc *udc, u32 conn)
1122{
1123 /* Just notify of a connection change event (optional) */
1124 if (udc->board->conn_chgb != NULL)
1125 udc->board->conn_chgb(conn);
1126}
1127
1128/* Suspend/resume event - notify board function of change */
1129static void uda_resm_susp_event(struct lpc32xx_udc *udc, u32 conn)
1130{
1131 /* Just notify of a Suspend/resume change event (optional) */
1132 if (udc->board->susp_chgb != NULL)
1133 udc->board->susp_chgb(conn);
1134
1135 if (conn)
1136 udc->suspended = 0;
1137 else
1138 udc->suspended = 1;
1139}
1140
1141/* Remote wakeup enable/disable - notify board function of change */
1142static void uda_remwkp_cgh(struct lpc32xx_udc *udc)
1143{
1144 if (udc->board->rmwk_chgb != NULL)
1145 udc->board->rmwk_chgb(udc->dev_status &
1146 (1 << USB_DEVICE_REMOTE_WAKEUP));
1147}
1148
1149/* Reads data from FIFO, adjusts for alignment and data size */
1150static void udc_pop_fifo(struct lpc32xx_udc *udc, u8 *data, u32 bytes)
1151{
1152 int n, i, bl;
1153 u16 *p16;
1154 u32 *p32, tmp, cbytes;
1155
1156 /* Use optimal data transfer method based on source address and size */
1157 switch (((u32) data) & 0x3) {
1158 case 0: /* 32-bit aligned */
1159 p32 = (u32 *) data;
1160 cbytes = (bytes & ~0x3);
1161
1162 /* Copy 32-bit aligned data first */
1163 for (n = 0; n < cbytes; n += 4)
1164 *p32++ = readl(USBD_RXDATA(udc->udp_baseaddr));
1165
1166 /* Handle any remaining bytes */
1167 bl = bytes - cbytes;
1168 if (bl) {
1169 tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
1170 for (n = 0; n < bl; n++)
1171 data[cbytes + n] = ((tmp >> (n * 8)) & 0xFF);
1172
1173 }
1174 break;
1175
1176 case 1: /* 8-bit aligned */
1177 case 3:
1178 /* Each byte has to be handled independently */
1179 for (n = 0; n < bytes; n += 4) {
1180 tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
1181
1182 bl = bytes - n;
2aeb20ba
GS		 1183 if (bl > 4)
1184 bl = 4;
24a28e42
RS		 1185
1186 for (i = 0; i < bl; i++)
2aeb20ba 1187 data[n + i] = (u8) ((tmp >> (i * 8)) & 0xFF);
24a28e42
RS		 1188 }
1189 break;
1190
1191 case 2: /* 16-bit aligned */
1192 p16 = (u16 *) data;
1193 cbytes = (bytes & ~0x3);
1194
1195 /* Copy 32-bit sized objects first with 16-bit alignment */
1196 for (n = 0; n < cbytes; n += 4) {
1197 tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
1198 *p16++ = (u16)(tmp & 0xFFFF);
1199 *p16++ = (u16)((tmp >> 16) & 0xFFFF);
1200 }
1201
1202 /* Handle any remaining bytes */
1203 bl = bytes - cbytes;
1204 if (bl) {
1205 tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
1206 for (n = 0; n < bl; n++)
1207 data[cbytes + n] = ((tmp >> (n * 8)) & 0xFF);
1208 }
1209 break;
1210 }
1211}
1212
1213/* Read data from the FIFO for an endpoint. This function is for endpoints (such
1214 * as EP0) that don't use DMA. This function should only be called if a packet
1215 * is known to be ready to read for the endpoint. Note that the endpoint must
1216 * be selected in the protocol engine prior to this call. */
1217static u32 udc_read_hwep(struct lpc32xx_udc *udc, u32 hwep, u32 *data,
1218 u32 bytes)
1219{
1220 u32 tmpv;
1221 int to = 1000;
1222 u32 tmp, hwrep = ((hwep & 0x1E) << 1) | CTRL_RD_EN;
1223
1224 /* Setup read of endpoint */
1225 writel(hwrep, USBD_CTRL(udc->udp_baseaddr));
1226
1227 /* Wait until packet is ready */
1228 while ((((tmpv = readl(USBD_RXPLEN(udc->udp_baseaddr))) &
1229 PKT_RDY) == 0) && (to > 0))
1230 to--;
1231 if (!to)
1232 dev_dbg(udc->dev, "No packet ready on FIFO EP read\n");
1233
1234 /* Mask out count */
1235 tmp = tmpv & PKT_LNGTH_MASK;
1236 if (bytes < tmp)
1237 tmp = bytes;
1238
1239 if ((tmp > 0) && (data != NULL))
1240 udc_pop_fifo(udc, (u8 *) data, tmp);
1241
1242 writel(((hwep & 0x1E) << 1), USBD_CTRL(udc->udp_baseaddr));
1243
1244 /* Clear the buffer */
1245 udc_clr_buffer_hwep(udc, hwep);
1246
1247 return tmp;
1248}
1249
1250/* Stuffs data into the FIFO, adjusts for alignment and data size */
1251static void udc_stuff_fifo(struct lpc32xx_udc *udc, u8 *data, u32 bytes)
1252{
1253 int n, i, bl;
1254 u16 *p16;
1255 u32 *p32, tmp, cbytes;
1256
1257 /* Use optimal data transfer method based on source address and size */
1258 switch (((u32) data) & 0x3) {
1259 case 0: /* 32-bit aligned */
1260 p32 = (u32 *) data;
1261 cbytes = (bytes & ~0x3);
1262
1263 /* Copy 32-bit aligned data first */
1264 for (n = 0; n < cbytes; n += 4)
1265 writel(*p32++, USBD_TXDATA(udc->udp_baseaddr));
1266
1267 /* Handle any remaining bytes */
1268 bl = bytes - cbytes;
1269 if (bl) {
1270 tmp = 0;
1271 for (n = 0; n < bl; n++)
1272 tmp |= data[cbytes + n] << (n * 8);
1273
1274 writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
1275 }
1276 break;
1277
1278 case 1: /* 8-bit aligned */
1279 case 3:
1280 /* Each byte has to be handled independently */
1281 for (n = 0; n < bytes; n += 4) {
1282 bl = bytes - n;
1283 if (bl > 4)
1284 bl = 4;
1285
1286 tmp = 0;
1287 for (i = 0; i < bl; i++)
1288 tmp |= data[n + i] << (i * 8);
1289
1290 writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
1291 }
1292 break;
1293
1294 case 2: /* 16-bit aligned */
1295 p16 = (u16 *) data;
1296 cbytes = (bytes & ~0x3);
1297
1298 /* Copy 32-bit aligned data first */
1299 for (n = 0; n < cbytes; n += 4) {
1300 tmp = *p16++ & 0xFFFF;
1301 tmp |= (*p16++ & 0xFFFF) << 16;
1302 writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
1303 }
1304
1305 /* Handle any remaining bytes */
1306 bl = bytes - cbytes;
1307 if (bl) {
1308 tmp = 0;
1309 for (n = 0; n < bl; n++)
1310 tmp |= data[cbytes + n] << (n * 8);
1311
1312 writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
1313 }
1314 break;
1315 }
1316}
1317
1318/* Write data to the FIFO for an endpoint. This function is for endpoints (such
1319 * as EP0) that don't use DMA. Note that the endpoint must be selected in the
1320 * protocol engine prior to this call. */
1321static void udc_write_hwep(struct lpc32xx_udc *udc, u32 hwep, u32 *data,
1322 u32 bytes)
1323{
1324 u32 hwwep = ((hwep & 0x1E) << 1) | CTRL_WR_EN;
1325
1326 if ((bytes > 0) && (data == NULL))
1327 return;
1328
1329 /* Setup write of endpoint */
1330 writel(hwwep, USBD_CTRL(udc->udp_baseaddr));
1331
1332 writel(bytes, USBD_TXPLEN(udc->udp_baseaddr));
1333
1334 /* Need at least 1 byte to trigger TX */
1335 if (bytes == 0)
1336 writel(0, USBD_TXDATA(udc->udp_baseaddr));
1337 else
1338 udc_stuff_fifo(udc, (u8 *) data, bytes);
1339
1340 writel(((hwep & 0x1E) << 1), USBD_CTRL(udc->udp_baseaddr));
1341
1342 udc_val_buffer_hwep(udc, hwep);
1343}
1344
1345/* USB device reset - resets USB to a default state with just EP0
1346 enabled */
1347static void uda_usb_reset(struct lpc32xx_udc *udc)
1348{
1349 u32 i = 0;
1350 /* Re-init device controller and EP0 */
1351 udc_enable(udc);
1352 udc->gadget.speed = USB_SPEED_FULL;
1353
1354 for (i = 1; i < NUM_ENDPOINTS; i++) {
1355 struct lpc32xx_ep *ep = &udc->ep[i];
1356 ep->req_pending = 0;
1357 }
1358}
1359
1360/* Send a ZLP on EP0 */
1361static void udc_ep0_send_zlp(struct lpc32xx_udc *udc)
1362{
1363 udc_write_hwep(udc, EP_IN, NULL, 0);
1364}
1365
1366/* Get current frame number */
1367static u16 udc_get_current_frame(struct lpc32xx_udc *udc)
1368{
1369 u16 flo, fhi;
1370
1371 udc_protocol_cmd_w(udc, CMD_RD_FRAME);
1372 flo = (u16) udc_protocol_cmd_r(udc, DAT_RD_FRAME);
1373 fhi = (u16) udc_protocol_cmd_r(udc, DAT_RD_FRAME);
1374
1375 return (fhi << 8) | flo;
1376}
1377
1378/* Set the device as configured - enables all endpoints */
1379static inline void udc_set_device_configured(struct lpc32xx_udc *udc)
1380{
1381 udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(CONF_DVICE));
1382}
1383
1384/* Set the device as unconfigured - disables all endpoints */
1385static inline void udc_set_device_unconfigured(struct lpc32xx_udc *udc)
1386{
1387 udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(0));
1388}
1389
1390/* reinit == restore initial software state */
1391static void udc_reinit(struct lpc32xx_udc *udc)
1392{
1393 u32 i;
1394
1395 INIT_LIST_HEAD(&udc->gadget.ep_list);
1396 INIT_LIST_HEAD(&udc->gadget.ep0->ep_list);
1397
1398 for (i = 0; i < NUM_ENDPOINTS; i++) {
1399 struct lpc32xx_ep *ep = &udc->ep[i];
1400
1401 if (i != 0)
1402 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
e117e742 1403 usb_ep_set_maxpacket_limit(&ep->ep, ep->maxpacket);
24a28e42
RS		 1404 INIT_LIST_HEAD(&ep->queue);
1405 ep->req_pending = 0;
1406 }
1407
1408 udc->ep0state = WAIT_FOR_SETUP;
1409}
1410
1411/* Must be called with lock */
1412static void done(struct lpc32xx_ep *ep, struct lpc32xx_request *req, int status)
1413{
1414 struct lpc32xx_udc *udc = ep->udc;
1415
1416 list_del_init(&req->queue);
1417 if (req->req.status == -EINPROGRESS)
1418 req->req.status = status;
1419 else
1420 status = req->req.status;
1421
1422 if (ep->lep) {
369ac9cb 1423 usb_gadget_unmap_request(&udc->gadget, &req->req, ep->is_in);
24a28e42
RS		 1424
1425 /* Free DDs */
1426 udc_dd_free(udc, req->dd_desc_ptr);
1427 }
1428
1429 if (status && status != -ESHUTDOWN)
1430 ep_dbg(ep, "%s done %p, status %d\n", ep->ep.name, req, status);
1431
1432 ep->req_pending = 0;
1433 spin_unlock(&udc->lock);
304f7e5e 1434 usb_gadget_giveback_request(&ep->ep, &req->req);
24a28e42
RS		 1435 spin_lock(&udc->lock);
1436}
1437
1438/* Must be called with lock */
1439static void nuke(struct lpc32xx_ep *ep, int status)
1440{
1441 struct lpc32xx_request *req;
1442
1443 while (!list_empty(&ep->queue)) {
1444 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
1445 done(ep, req, status);
1446 }
1447
78ca9139 1448 if (status == -ESHUTDOWN) {
24a28e42
RS		 1449 uda_disable_hwepint(ep->udc, ep->hwep_num);
1450 udc_disable_hwep(ep->udc, ep->hwep_num);
1451 }
1452}
1453
1454/* IN endpoint 0 transfer */
1455static int udc_ep0_in_req(struct lpc32xx_udc *udc)
1456{
1457 struct lpc32xx_request *req;
1458 struct lpc32xx_ep *ep0 = &udc->ep[0];
1459 u32 tsend, ts = 0;
1460
1461 if (list_empty(&ep0->queue))
1462 /* Nothing to send */
1463 return 0;
1464 else
1465 req = list_entry(ep0->queue.next, struct lpc32xx_request,
1466 queue);
1467
1468 tsend = ts = req->req.length - req->req.actual;
1469 if (ts == 0) {
1470 /* Send a ZLP */
1471 udc_ep0_send_zlp(udc);
1472 done(ep0, req, 0);
1473 return 1;
1474 } else if (ts > ep0->ep.maxpacket)
1475 ts = ep0->ep.maxpacket; /* Just send what we can */
1476
1477 /* Write data to the EP0 FIFO and start transfer */
1478 udc_write_hwep(udc, EP_IN, (req->req.buf + req->req.actual), ts);
1479
1480 /* Increment data pointer */
1481 req->req.actual += ts;
1482
1483 if (tsend >= ep0->ep.maxpacket)
1484 return 0; /* Stay in data transfer state */
1485
1486 /* Transfer request is complete */
1487 udc->ep0state = WAIT_FOR_SETUP;
1488 done(ep0, req, 0);
1489 return 1;
1490}
1491
1492/* OUT endpoint 0 transfer */
1493static int udc_ep0_out_req(struct lpc32xx_udc *udc)
1494{
1495 struct lpc32xx_request *req;
1496 struct lpc32xx_ep *ep0 = &udc->ep[0];
1497 u32 tr, bufferspace;
1498
1499 if (list_empty(&ep0->queue))
1500 return 0;
1501 else
1502 req = list_entry(ep0->queue.next, struct lpc32xx_request,
1503 queue);
1504
1505 if (req) {
1506 if (req->req.length == 0) {
1507 /* Just dequeue request */
1508 done(ep0, req, 0);
1509 udc->ep0state = WAIT_FOR_SETUP;
1510 return 1;
1511 }
1512
1513 /* Get data from FIFO */
1514 bufferspace = req->req.length - req->req.actual;
1515 if (bufferspace > ep0->ep.maxpacket)
1516 bufferspace = ep0->ep.maxpacket;
1517
1518 /* Copy data to buffer */
1519 prefetchw(req->req.buf + req->req.actual);
1520 tr = udc_read_hwep(udc, EP_OUT, req->req.buf + req->req.actual,
1521 bufferspace);
1522 req->req.actual += bufferspace;
1523
1524 if (tr < ep0->ep.maxpacket) {
1525 /* This is the last packet */
1526 done(ep0, req, 0);
1527 udc->ep0state = WAIT_FOR_SETUP;
1528 return 1;
1529 }
1530 }
1531
1532 return 0;
1533}
1534
1535/* Must be called with lock */
1536static void stop_activity(struct lpc32xx_udc *udc)
1537{
1538 struct usb_gadget_driver *driver = udc->driver;
1539 int i;
1540
1541 if (udc->gadget.speed == USB_SPEED_UNKNOWN)
1542 driver = NULL;
1543
1544 udc->gadget.speed = USB_SPEED_UNKNOWN;
1545 udc->suspended = 0;
1546
1547 for (i = 0; i < NUM_ENDPOINTS; i++) {
1548 struct lpc32xx_ep *ep = &udc->ep[i];
1549 nuke(ep, -ESHUTDOWN);
1550 }
1551 if (driver) {
1552 spin_unlock(&udc->lock);
1553 driver->disconnect(&udc->gadget);
1554 spin_lock(&udc->lock);
1555 }
1556
1557 isp1301_pullup_enable(udc, 0, 0);
1558 udc_disable(udc);
1559 udc_reinit(udc);
1560}
1561
1562/*
1563 * Activate or kill host pullup
1564 * Can be called with or without lock
1565 */
1566static void pullup(struct lpc32xx_udc *udc, int is_on)
1567{
1568 if (!udc->clocked)
1569 return;
1570
1571 if (!udc->enabled || !udc->vbus)
1572 is_on = 0;
1573
1574 if (is_on != udc->pullup)
1575 isp1301_pullup_enable(udc, is_on, 0);
1576}
1577
1578/* Must be called without lock */
1579static int lpc32xx_ep_disable(struct usb_ep *_ep)
1580{
1581 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
1582 struct lpc32xx_udc *udc = ep->udc;
1583 unsigned long flags;
1584
1585 if ((ep->hwep_num_base == 0) || (ep->hwep_num == 0))
1586 return -EINVAL;
1587 spin_lock_irqsave(&udc->lock, flags);
1588
1589 nuke(ep, -ESHUTDOWN);
1590
24a28e42
RS		 1591 /* Clear all DMA statuses for this EP */
1592 udc_ep_dma_disable(udc, ep->hwep_num);
1593 writel(1 << ep->hwep_num, USBD_EOTINTCLR(udc->udp_baseaddr));
1594 writel(1 << ep->hwep_num, USBD_NDDRTINTCLR(udc->udp_baseaddr));
1595 writel(1 << ep->hwep_num, USBD_SYSERRTINTCLR(udc->udp_baseaddr));
1596 writel(1 << ep->hwep_num, USBD_DMARCLR(udc->udp_baseaddr));
1597
1598 /* Remove the DD pointer in the UDCA */
1599 udc->udca_v_base[ep->hwep_num] = 0;
1600
1601 /* Disable and reset endpoint and interrupt */
1602 uda_clear_hwepint(udc, ep->hwep_num);
1603 udc_unrealize_hwep(udc, ep->hwep_num);
1604
1605 ep->hwep_num = 0;
1606
1607 spin_unlock_irqrestore(&udc->lock, flags);
1608
1609 atomic_dec(&udc->enabled_ep_cnt);
1610 wake_up(&udc->ep_disable_wait_queue);
1611
1612 return 0;
1613}
1614
1615/* Must be called without lock */
1616static int lpc32xx_ep_enable(struct usb_ep *_ep,
1617 const struct usb_endpoint_descriptor *desc)
1618{
1619 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
1620 struct lpc32xx_udc *udc = ep->udc;
1621 u16 maxpacket;
1622 u32 tmp;
1623 unsigned long flags;
1624
1625 /* Verify EP data */
78ca9139 1626 if ((!_ep) || (!ep) || (!desc) ||
24a28e42
RS		 1627 (desc->bDescriptorType != USB_DT_ENDPOINT)) {
1628 dev_dbg(udc->dev, "bad ep or descriptor\n");
1629 return -EINVAL;
1630 }
1631 maxpacket = usb_endpoint_maxp(desc);
1632 if ((maxpacket == 0) || (maxpacket > ep->maxpacket)) {
1633 dev_dbg(udc->dev, "bad ep descriptor's packet size\n");
1634 return -EINVAL;
1635 }
1636
1637 /* Don't touch EP0 */
1638 if (ep->hwep_num_base == 0) {
1639 dev_dbg(udc->dev, "Can't re-enable EP0!!!\n");
1640 return -EINVAL;
1641 }
1642
1643 /* Is driver ready? */
1644 if ((!udc->driver) || (udc->gadget.speed == USB_SPEED_UNKNOWN)) {
1645 dev_dbg(udc->dev, "bogus device state\n");
1646 return -ESHUTDOWN;
1647 }
1648
1649 tmp = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
1650 switch (tmp) {
1651 case USB_ENDPOINT_XFER_CONTROL:
1652 return -EINVAL;
1653
1654 case USB_ENDPOINT_XFER_INT:
1655 if (maxpacket > ep->maxpacket) {
1656 dev_dbg(udc->dev,
1657 "Bad INT endpoint maxpacket %d\n", maxpacket);
1658 return -EINVAL;
1659 }
1660 break;
1661
1662 case USB_ENDPOINT_XFER_BULK:
1663 switch (maxpacket) {
1664 case 8:
1665 case 16:
1666 case 32:
1667 case 64:
1668 break;
1669
1670 default:
1671 dev_dbg(udc->dev,
1672 "Bad BULK endpoint maxpacket %d\n", maxpacket);
1673 return -EINVAL;
1674 }
1675 break;
1676
1677 case USB_ENDPOINT_XFER_ISOC:
1678 break;
1679 }
1680 spin_lock_irqsave(&udc->lock, flags);
1681
1682 /* Initialize endpoint to match the selected descriptor */
1683 ep->is_in = (desc->bEndpointAddress & USB_DIR_IN) != 0;
24a28e42
RS		 1684 ep->ep.maxpacket = maxpacket;
1685
1686 /* Map hardware endpoint from base and direction */
1687 if (ep->is_in)
1688 /* IN endpoints are offset 1 from the OUT endpoint */
1689 ep->hwep_num = ep->hwep_num_base + EP_IN;
1690 else
1691 ep->hwep_num = ep->hwep_num_base;
1692
1693 ep_dbg(ep, "EP enabled: %s, HW:%d, MP:%d IN:%d\n", ep->ep.name,
1694 ep->hwep_num, maxpacket, (ep->is_in == 1));
1695
1696 /* Realize the endpoint, interrupt is enabled later when
1697 * buffers are queued, IN EPs will NAK until buffers are ready */
1698 udc_realize_hwep(udc, ep->hwep_num, ep->ep.maxpacket);
1699 udc_clr_buffer_hwep(udc, ep->hwep_num);
1700 uda_disable_hwepint(udc, ep->hwep_num);
1701 udc_clrstall_hwep(udc, ep->hwep_num);
1702
1703 /* Clear all DMA statuses for this EP */
1704 udc_ep_dma_disable(udc, ep->hwep_num);
1705 writel(1 << ep->hwep_num, USBD_EOTINTCLR(udc->udp_baseaddr));
1706 writel(1 << ep->hwep_num, USBD_NDDRTINTCLR(udc->udp_baseaddr));
1707 writel(1 << ep->hwep_num, USBD_SYSERRTINTCLR(udc->udp_baseaddr));
1708 writel(1 << ep->hwep_num, USBD_DMARCLR(udc->udp_baseaddr));
1709
1710 spin_unlock_irqrestore(&udc->lock, flags);
1711
1712 atomic_inc(&udc->enabled_ep_cnt);
1713 return 0;
1714}
1715
1716/*
1717 * Allocate a USB request list
1718 * Can be called with or without lock
1719 */
1720static struct usb_request *lpc32xx_ep_alloc_request(struct usb_ep *_ep,
1721 gfp_t gfp_flags)
1722{
1723 struct lpc32xx_request *req;
1724
1725 req = kzalloc(sizeof(struct lpc32xx_request), gfp_flags);
1726 if (!req)
1727 return NULL;
1728
1729 INIT_LIST_HEAD(&req->queue);
1730 return &req->req;
1731}
1732
1733/*
1734 * De-allocate a USB request list
1735 * Can be called with or without lock
1736 */
1737static void lpc32xx_ep_free_request(struct usb_ep *_ep,
1738 struct usb_request *_req)
1739{
1740 struct lpc32xx_request *req;
1741
1742 req = container_of(_req, struct lpc32xx_request, req);
1743 BUG_ON(!list_empty(&req->queue));
1744 kfree(req);
1745}
1746
1747/* Must be called without lock */
1748static int lpc32xx_ep_queue(struct usb_ep *_ep,
1749 struct usb_request *_req, gfp_t gfp_flags)
1750{
1751 struct lpc32xx_request *req;
1752 struct lpc32xx_ep *ep;
1753 struct lpc32xx_udc *udc;
1754 unsigned long flags;
1755 int status = 0;
1756
1757 req = container_of(_req, struct lpc32xx_request, req);
1758 ep = container_of(_ep, struct lpc32xx_ep, ep);
1759
005a6430 1760 if (!_ep || !_req || !_req->complete || !_req->buf ||
24a28e42
RS		 1761 !list_empty(&req->queue))
1762 return -EINVAL;
1763
1764 udc = ep->udc;
1765
005a6430
PC		 1766 if (udc->gadget.speed == USB_SPEED_UNKNOWN)
1767 return -EPIPE;
24a28e42
RS		 1768
1769 if (ep->lep) {
24a28e42
RS		 1770 struct lpc32xx_usbd_dd_gad *dd;
1771
369ac9cb
FB		 1772 status = usb_gadget_map_request(&udc->gadget, _req, ep->is_in);
1773 if (status)
1774 return status;
24a28e42
RS		 1775
1776 /* For the request, build a list of DDs */
1777 dd = udc_dd_alloc(udc);
1778 if (!dd) {
1779 /* Error allocating DD */
1780 return -ENOMEM;
1781 }
1782 req->dd_desc_ptr = dd;
1783
1784 /* Setup the DMA descriptor */
1785 dd->dd_next_phy = dd->dd_next_v = 0;
1786 dd->dd_buffer_addr = req->req.dma;
1787 dd->dd_status = 0;
1788
1789 /* Special handling for ISO EPs */
1790 if (ep->eptype == EP_ISO_TYPE) {
1791 dd->dd_setup = DD_SETUP_ISO_EP |
1792 DD_SETUP_PACKETLEN(0) |
1793 DD_SETUP_DMALENBYTES(1);
1794 dd->dd_iso_ps_mem_addr = dd->this_dma + 24;
1795 if (ep->is_in)
1796 dd->iso_status[0] = req->req.length;
1797 else
1798 dd->iso_status[0] = 0;
1799 } else
1800 dd->dd_setup = DD_SETUP_PACKETLEN(ep->ep.maxpacket) |
1801 DD_SETUP_DMALENBYTES(req->req.length);
1802 }
1803
1804 ep_dbg(ep, "%s queue req %p len %d buf %p (in=%d) z=%d\n", _ep->name,
1805 _req, _req->length, _req->buf, ep->is_in, _req->zero);
1806
1807 spin_lock_irqsave(&udc->lock, flags);
1808
1809 _req->status = -EINPROGRESS;
1810 _req->actual = 0;
1811 req->send_zlp = _req->zero;
1812
1813 /* Kickstart empty queues */
1814 if (list_empty(&ep->queue)) {
1815 list_add_tail(&req->queue, &ep->queue);
1816
1817 if (ep->hwep_num_base == 0) {
1818 /* Handle expected data direction */
1819 if (ep->is_in) {
1820 /* IN packet to host */
1821 udc->ep0state = DATA_IN;
1822 status = udc_ep0_in_req(udc);
1823 } else {
1824 /* OUT packet from host */
1825 udc->ep0state = DATA_OUT;
1826 status = udc_ep0_out_req(udc);
1827 }
1828 } else if (ep->is_in) {
1829 /* IN packet to host and kick off transfer */
1830 if (!ep->req_pending)
1831 udc_ep_in_req_dma(udc, ep);
1832 } else
1833 /* OUT packet from host and kick off list */
1834 if (!ep->req_pending)
1835 udc_ep_out_req_dma(udc, ep);
1836 } else
1837 list_add_tail(&req->queue, &ep->queue);
1838
1839 spin_unlock_irqrestore(&udc->lock, flags);
1840
1841 return (status < 0) ? status : 0;
1842}
1843
1844/* Must be called without lock */
1845static int lpc32xx_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1846{
1847 struct lpc32xx_ep *ep;
1848 struct lpc32xx_request *req;
1849 unsigned long flags;
1850
1851 ep = container_of(_ep, struct lpc32xx_ep, ep);
1852 if (!_ep || ep->hwep_num_base == 0)
1853 return -EINVAL;
1854
1855 spin_lock_irqsave(&ep->udc->lock, flags);
1856
1857 /* make sure it's actually queued on this endpoint */
1858 list_for_each_entry(req, &ep->queue, queue) {
1859 if (&req->req == _req)
1860 break;
1861 }
1862 if (&req->req != _req) {
1863 spin_unlock_irqrestore(&ep->udc->lock, flags);
1864 return -EINVAL;
1865 }
1866
1867 done(ep, req, -ECONNRESET);
1868
1869 spin_unlock_irqrestore(&ep->udc->lock, flags);
1870
1871 return 0;
1872}
1873
1874/* Must be called without lock */
1875static int lpc32xx_ep_set_halt(struct usb_ep *_ep, int value)
1876{
1877 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
1878 struct lpc32xx_udc *udc = ep->udc;
1879 unsigned long flags;
1880
78ca9139 1881 if ((!ep) || (ep->hwep_num <= 1))
24a28e42
RS		 1882 return -EINVAL;
1883
1884 /* Don't halt an IN EP */
1885 if (ep->is_in)
1886 return -EAGAIN;
1887
1888 spin_lock_irqsave(&udc->lock, flags);
1889
1890 if (value == 1) {
1891 /* stall */
1892 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(ep->hwep_num),
1893 DAT_WR_BYTE(EP_STAT_ST));
1894 } else {
1895 /* End stall */
1896 ep->wedge = 0;
1897 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(ep->hwep_num),
1898 DAT_WR_BYTE(0));
1899 }
1900
1901 spin_unlock_irqrestore(&udc->lock, flags);
1902
1903 return 0;
1904}
1905
1906/* set the halt feature and ignores clear requests */
1907static int lpc32xx_ep_set_wedge(struct usb_ep *_ep)
1908{
1909 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
1910
1911 if (!_ep || !ep->udc)
1912 return -EINVAL;
1913
1914 ep->wedge = 1;
1915
1916 return usb_ep_set_halt(_ep);
1917}
1918
1919static const struct usb_ep_ops lpc32xx_ep_ops = {
1920 .enable = lpc32xx_ep_enable,
1921 .disable = lpc32xx_ep_disable,
1922 .alloc_request = lpc32xx_ep_alloc_request,
1923 .free_request = lpc32xx_ep_free_request,
1924 .queue = lpc32xx_ep_queue,
1925 .dequeue = lpc32xx_ep_dequeue,
1926 .set_halt = lpc32xx_ep_set_halt,
1927 .set_wedge = lpc32xx_ep_set_wedge,
1928};
1929
1930/* Send a ZLP on a non-0 IN EP */
1931void udc_send_in_zlp(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
1932{
1933 /* Clear EP status */
1934 udc_clearep_getsts(udc, ep->hwep_num);
1935
1936 /* Send ZLP via FIFO mechanism */
1937 udc_write_hwep(udc, ep->hwep_num, NULL, 0);
1938}
1939
1940/*
1941 * Handle EP completion for ZLP
1942 * This function will only be called when a delayed ZLP needs to be sent out
1943 * after a DMA transfer has filled both buffers.
1944 */
1945void udc_handle_eps(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
1946{
1947 u32 epstatus;
1948 struct lpc32xx_request *req;
1949
1950 if (ep->hwep_num <= 0)
1951 return;
1952
1953 uda_clear_hwepint(udc, ep->hwep_num);
1954
1955 /* If this interrupt isn't enabled, return now */
1956 if (!(udc->enabled_hwepints & (1 << ep->hwep_num)))
1957 return;
1958
1959 /* Get endpoint status */
1960 epstatus = udc_clearep_getsts(udc, ep->hwep_num);
1961
1962 /*
1963 * This should never happen, but protect against writing to the
1964 * buffer when full.
1965 */
1966 if (epstatus & EP_SEL_F)
1967 return;
1968
1969 if (ep->is_in) {
1970 udc_send_in_zlp(udc, ep);
1971 uda_disable_hwepint(udc, ep->hwep_num);
1972 } else
1973 return;
1974
1975 /* If there isn't a request waiting, something went wrong */
1976 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
1977 if (req) {
1978 done(ep, req, 0);
1979
1980 /* Start another request if ready */
1981 if (!list_empty(&ep->queue)) {
1982 if (ep->is_in)
1983 udc_ep_in_req_dma(udc, ep);
1984 else
1985 udc_ep_out_req_dma(udc, ep);
1986 } else
1987 ep->req_pending = 0;
1988 }
1989}
1990
1991
1992/* DMA end of transfer completion */
1993static void udc_handle_dma_ep(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
1994{
1995 u32 status, epstatus;
1996 struct lpc32xx_request *req;
1997 struct lpc32xx_usbd_dd_gad *dd;
1998
1999#ifdef CONFIG_USB_GADGET_DEBUG_FILES
2000 ep->totalints++;
2001#endif
2002
2003 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
2004 if (!req) {
2005 ep_err(ep, "DMA interrupt on no req!\n");
2006 return;
2007 }
2008 dd = req->dd_desc_ptr;
2009
2010 /* DMA descriptor should always be retired for this call */
2011 if (!(dd->dd_status & DD_STATUS_DD_RETIRED))
2012 ep_warn(ep, "DMA descriptor did not retire\n");
2013
2014 /* Disable DMA */
2015 udc_ep_dma_disable(udc, ep->hwep_num);
2016 writel((1 << ep->hwep_num), USBD_EOTINTCLR(udc->udp_baseaddr));
2017 writel((1 << ep->hwep_num), USBD_NDDRTINTCLR(udc->udp_baseaddr));
2018
2019 /* System error? */
2020 if (readl(USBD_SYSERRTINTST(udc->udp_baseaddr)) &
2021 (1 << ep->hwep_num)) {
2022 writel((1 << ep->hwep_num),
2023 USBD_SYSERRTINTCLR(udc->udp_baseaddr));
2024 ep_err(ep, "AHB critical error!\n");
2025 ep->req_pending = 0;
2026
2027 /* The error could have occurred on a packet of a multipacket
2028 * transfer, so recovering the transfer is not possible. Close
2029 * the request with an error */
2030 done(ep, req, -ECONNABORTED);
2031 return;
2032 }
2033
2034 /* Handle the current DD's status */
2035 status = dd->dd_status;
2036 switch (status & DD_STATUS_STS_MASK) {
2037 case DD_STATUS_STS_NS:
2038 /* DD not serviced? This shouldn't happen! */
2039 ep->req_pending = 0;
2040 ep_err(ep, "DMA critical EP error: DD not serviced (0x%x)!\n",
2041 status);
2042
2043 done(ep, req, -ECONNABORTED);
2044 return;
2045
2046 case DD_STATUS_STS_BS:
2047 /* Interrupt only fires on EOT - This shouldn't happen! */
2048 ep->req_pending = 0;
2049 ep_err(ep, "DMA critical EP error: EOT prior to service completion (0x%x)!\n",
2050 status);
2051 done(ep, req, -ECONNABORTED);
2052 return;
2053
2054 case DD_STATUS_STS_NC:
2055 case DD_STATUS_STS_DUR:
2056 /* Really just a short packet, not an underrun */
2057 /* This is a good status and what we expect */
2058 break;
2059
2060 default:
2061 /* Data overrun, system error, or unknown */
2062 ep->req_pending = 0;
2063 ep_err(ep, "DMA critical EP error: System error (0x%x)!\n",
2064 status);
2065 done(ep, req, -ECONNABORTED);
2066 return;
2067 }
2068
2069 /* ISO endpoints are handled differently */
2070 if (ep->eptype == EP_ISO_TYPE) {
2071 if (ep->is_in)
2072 req->req.actual = req->req.length;
2073 else
2074 req->req.actual = dd->iso_status[0] & 0xFFFF;
2075 } else
2076 req->req.actual += DD_STATUS_CURDMACNT(status);
2077
2078 /* Send a ZLP if necessary. This will be done for non-int
2079 * packets which have a size that is a divisor of MAXP */
2080 if (req->send_zlp) {
2081 /*
2082 * If at least 1 buffer is available, send the ZLP now.
2083 * Otherwise, the ZLP send needs to be deferred until a
2084 * buffer is available.
2085 */
2086 if (udc_clearep_getsts(udc, ep->hwep_num) & EP_SEL_F) {
2087 udc_clearep_getsts(udc, ep->hwep_num);
2088 uda_enable_hwepint(udc, ep->hwep_num);
2089 epstatus = udc_clearep_getsts(udc, ep->hwep_num);
2090
2091 /* Let the EP interrupt handle the ZLP */
2092 return;
2093 } else
2094 udc_send_in_zlp(udc, ep);
2095 }
2096
2097 /* Transfer request is complete */
2098 done(ep, req, 0);
2099
2100 /* Start another request if ready */
2101 udc_clearep_getsts(udc, ep->hwep_num);
2102 if (!list_empty((&ep->queue))) {
2103 if (ep->is_in)
2104 udc_ep_in_req_dma(udc, ep);
2105 else
2106 udc_ep_out_req_dma(udc, ep);
2107 } else
2108 ep->req_pending = 0;
2109
2110}
2111
2112/*
2113 *
2114 * Endpoint 0 functions
2115 *
2116 */
2117static void udc_handle_dev(struct lpc32xx_udc *udc)
2118{
2119 u32 tmp;
2120
2121 udc_protocol_cmd_w(udc, CMD_GET_DEV_STAT);
2122 tmp = udc_protocol_cmd_r(udc, DAT_GET_DEV_STAT);
2123
2124 if (tmp & DEV_RST)
2125 uda_usb_reset(udc);
2126 else if (tmp & DEV_CON_CH)
2127 uda_power_event(udc, (tmp & DEV_CON));
2128 else if (tmp & DEV_SUS_CH) {
2129 if (tmp & DEV_SUS) {
2130 if (udc->vbus == 0)
2131 stop_activity(udc);
2132 else if ((udc->gadget.speed != USB_SPEED_UNKNOWN) &&
2133 udc->driver) {
2134 /* Power down transceiver */
2135 udc->poweron = 0;
2136 schedule_work(&udc->pullup_job);
2137 uda_resm_susp_event(udc, 1);
2138 }
2139 } else if ((udc->gadget.speed != USB_SPEED_UNKNOWN) &&
2140 udc->driver && udc->vbus) {
2141 uda_resm_susp_event(udc, 0);
2142 /* Power up transceiver */
2143 udc->poweron = 1;
2144 schedule_work(&udc->pullup_job);
2145 }
2146 }
2147}
2148
2149static int udc_get_status(struct lpc32xx_udc *udc, u16 reqtype, u16 wIndex)
2150{
2151 struct lpc32xx_ep *ep;
2152 u32 ep0buff = 0, tmp;
2153
2154 switch (reqtype & USB_RECIP_MASK) {
2155 case USB_RECIP_INTERFACE:
2156 break; /* Not supported */
2157
2158 case USB_RECIP_DEVICE:
d60d9392 2159 ep0buff = udc->gadget.is_selfpowered;
24a28e42
RS		 2160 if (udc->dev_status & (1 << USB_DEVICE_REMOTE_WAKEUP))
2161 ep0buff |= (1 << USB_DEVICE_REMOTE_WAKEUP);
2162 break;
2163
2164 case USB_RECIP_ENDPOINT:
2165 tmp = wIndex & USB_ENDPOINT_NUMBER_MASK;
2166 ep = &udc->ep[tmp];
78ca9139 2167 if ((tmp == 0) || (tmp >= NUM_ENDPOINTS))
24a28e42
RS		 2168 return -EOPNOTSUPP;
2169
2170 if (wIndex & USB_DIR_IN) {
2171 if (!ep->is_in)
2172 return -EOPNOTSUPP; /* Something's wrong */
2173 } else if (ep->is_in)
2174 return -EOPNOTSUPP; /* Not an IN endpoint */
2175
2176 /* Get status of the endpoint */
2177 udc_protocol_cmd_w(udc, CMD_SEL_EP(ep->hwep_num));
2178 tmp = udc_protocol_cmd_r(udc, DAT_SEL_EP(ep->hwep_num));
2179
2180 if (tmp & EP_SEL_ST)
2181 ep0buff = (1 << USB_ENDPOINT_HALT);
2182 else
2183 ep0buff = 0;
2184 break;
2185
2186 default:
2187 break;
2188 }
2189
2190 /* Return data */
2191 udc_write_hwep(udc, EP_IN, &ep0buff, 2);
2192
2193 return 0;
2194}
2195
2196static void udc_handle_ep0_setup(struct lpc32xx_udc *udc)
2197{
2198 struct lpc32xx_ep *ep, *ep0 = &udc->ep[0];
2199 struct usb_ctrlrequest ctrlpkt;
2200 int i, bytes;
2201 u16 wIndex, wValue, wLength, reqtype, req, tmp;
2202
2203 /* Nuke previous transfers */
2204 nuke(ep0, -EPROTO);
2205
2206 /* Get setup packet */
2207 bytes = udc_read_hwep(udc, EP_OUT, (u32 *) &ctrlpkt, 8);
2208 if (bytes != 8) {
2209 ep_warn(ep0, "Incorrectly sized setup packet (s/b 8, is %d)!\n",
2210 bytes);
2211 return;
2212 }
2213
2214 /* Native endianness */
2215 wIndex = le16_to_cpu(ctrlpkt.wIndex);
2216 wValue = le16_to_cpu(ctrlpkt.wValue);
2217 wLength = le16_to_cpu(ctrlpkt.wLength);
2218 reqtype = le16_to_cpu(ctrlpkt.bRequestType);
2219
2220 /* Set direction of EP0 */
2221 if (likely(reqtype & USB_DIR_IN))
2222 ep0->is_in = 1;
2223 else
2224 ep0->is_in = 0;
2225
2226 /* Handle SETUP packet */
2227 req = le16_to_cpu(ctrlpkt.bRequest);
2228 switch (req) {
2229 case USB_REQ_CLEAR_FEATURE:
2230 case USB_REQ_SET_FEATURE:
2231 switch (reqtype) {
2232 case (USB_TYPE_STANDARD | USB_RECIP_DEVICE):
2233 if (wValue != USB_DEVICE_REMOTE_WAKEUP)
2234 goto stall; /* Nothing else handled */
2235
2236 /* Tell board about event */
2237 if (req == USB_REQ_CLEAR_FEATURE)
2238 udc->dev_status &=
2239 ~(1 << USB_DEVICE_REMOTE_WAKEUP);
2240 else
2241 udc->dev_status |=
2242 (1 << USB_DEVICE_REMOTE_WAKEUP);
2243 uda_remwkp_cgh(udc);
2244 goto zlp_send;
2245
2246 case (USB_TYPE_STANDARD | USB_RECIP_ENDPOINT):
2247 tmp = wIndex & USB_ENDPOINT_NUMBER_MASK;
2248 if ((wValue != USB_ENDPOINT_HALT) ||
2249 (tmp >= NUM_ENDPOINTS))
2250 break;
2251
2252 /* Find hardware endpoint from logical endpoint */
2253 ep = &udc->ep[tmp];
2254 tmp = ep->hwep_num;
2255 if (tmp == 0)
2256 break;
2257
2258 if (req == USB_REQ_SET_FEATURE)
2259 udc_stall_hwep(udc, tmp);
2260 else if (!ep->wedge)
2261 udc_clrstall_hwep(udc, tmp);
2262
2263 goto zlp_send;
2264
2265 default:
2266 break;
2267 }
3afa758c 2268 break;
24a28e42
RS		 2269
2270 case USB_REQ_SET_ADDRESS:
2271 if (reqtype == (USB_TYPE_STANDARD | USB_RECIP_DEVICE)) {
2272 udc_set_address(udc, wValue);
2273 goto zlp_send;
2274 }
2275 break;
2276
2277 case USB_REQ_GET_STATUS:
2278 udc_get_status(udc, reqtype, wIndex);
2279 return;
2280
2281 default:
2282 break; /* Let GadgetFS handle the descriptor instead */
2283 }
2284
2285 if (likely(udc->driver)) {
2286 /* device-2-host (IN) or no data setup command, process
2287 * immediately */
2288 spin_unlock(&udc->lock);
2289 i = udc->driver->setup(&udc->gadget, &ctrlpkt);
2290
2291 spin_lock(&udc->lock);
2292 if (req == USB_REQ_SET_CONFIGURATION) {
2293 /* Configuration is set after endpoints are realized */
2294 if (wValue) {
2295 /* Set configuration */
2296 udc_set_device_configured(udc);
2297
2298 udc_protocol_cmd_data_w(udc, CMD_SET_MODE,
2299 DAT_WR_BYTE(AP_CLK |
2300 INAK_BI | INAK_II));
2301 } else {
2302 /* Clear configuration */
2303 udc_set_device_unconfigured(udc);
2304
2305 /* Disable NAK interrupts */
2306 udc_protocol_cmd_data_w(udc, CMD_SET_MODE,
2307 DAT_WR_BYTE(AP_CLK));
2308 }
2309 }
2310
2311 if (i < 0) {
2312 /* setup processing failed, force stall */
0696f929 2313 dev_dbg(udc->dev,
24a28e42
RS		 2314 "req %02x.%02x protocol STALL; stat %d\n",
2315 reqtype, req, i);
2316 udc->ep0state = WAIT_FOR_SETUP;
2317 goto stall;
2318 }
2319 }
2320
2321 if (!ep0->is_in)
2322 udc_ep0_send_zlp(udc); /* ZLP IN packet on data phase */
2323
2324 return;
2325
2326stall:
2327 udc_stall_hwep(udc, EP_IN);
2328 return;
2329
2330zlp_send:
2331 udc_ep0_send_zlp(udc);
2332 return;
2333}
2334
2335/* IN endpoint 0 transfer */
2336static void udc_handle_ep0_in(struct lpc32xx_udc *udc)
2337{
2338 struct lpc32xx_ep *ep0 = &udc->ep[0];
2339 u32 epstatus;
2340
2341 /* Clear EP interrupt */
2342 epstatus = udc_clearep_getsts(udc, EP_IN);
2343
2344#ifdef CONFIG_USB_GADGET_DEBUG_FILES
2345 ep0->totalints++;
2346#endif
2347
2348 /* Stalled? Clear stall and reset buffers */
2349 if (epstatus & EP_SEL_ST) {
2350 udc_clrstall_hwep(udc, EP_IN);
2351 nuke(ep0, -ECONNABORTED);
2352 udc->ep0state = WAIT_FOR_SETUP;
2353 return;
2354 }
2355
2356 /* Is a buffer available? */
2357 if (!(epstatus & EP_SEL_F)) {
2358 /* Handle based on current state */
2359 if (udc->ep0state == DATA_IN)
2360 udc_ep0_in_req(udc);
2361 else {
2362 /* Unknown state for EP0 oe end of DATA IN phase */
2363 nuke(ep0, -ECONNABORTED);
2364 udc->ep0state = WAIT_FOR_SETUP;
2365 }
2366 }
2367}
2368
2369/* OUT endpoint 0 transfer */
2370static void udc_handle_ep0_out(struct lpc32xx_udc *udc)
2371{
2372 struct lpc32xx_ep *ep0 = &udc->ep[0];
2373 u32 epstatus;
2374
2375 /* Clear EP interrupt */
2376 epstatus = udc_clearep_getsts(udc, EP_OUT);
2377
2378
2379#ifdef CONFIG_USB_GADGET_DEBUG_FILES
2380 ep0->totalints++;
2381#endif
2382
2383 /* Stalled? */
2384 if (epstatus & EP_SEL_ST) {
2385 udc_clrstall_hwep(udc, EP_OUT);
2386 nuke(ep0, -ECONNABORTED);
2387 udc->ep0state = WAIT_FOR_SETUP;
2388 return;
2389 }
2390
2391 /* A NAK may occur if a packet couldn't be received yet */
2392 if (epstatus & EP_SEL_EPN)
2393 return;
2394 /* Setup packet incoming? */
2395 if (epstatus & EP_SEL_STP) {
2396 nuke(ep0, 0);
2397 udc->ep0state = WAIT_FOR_SETUP;
2398 }
2399
2400 /* Data available? */
2401 if (epstatus & EP_SEL_F)
2402 /* Handle based on current state */
2403 switch (udc->ep0state) {
2404 case WAIT_FOR_SETUP:
2405 udc_handle_ep0_setup(udc);
2406 break;
2407
2408 case DATA_OUT:
2409 udc_ep0_out_req(udc);
2410 break;
2411
2412 default:
2413 /* Unknown state for EP0 */
2414 nuke(ep0, -ECONNABORTED);
2415 udc->ep0state = WAIT_FOR_SETUP;
2416 }
2417}
2418
2419/* Must be called without lock */
2420static int lpc32xx_get_frame(struct usb_gadget *gadget)
2421{
2422 int frame;
2423 unsigned long flags;
2424 struct lpc32xx_udc *udc = to_udc(gadget);
2425
2426 if (!udc->clocked)
2427 return -EINVAL;
2428
2429 spin_lock_irqsave(&udc->lock, flags);
2430
2431 frame = (int) udc_get_current_frame(udc);
2432
2433 spin_unlock_irqrestore(&udc->lock, flags);
2434
2435 return frame;
2436}
2437
2438static int lpc32xx_wakeup(struct usb_gadget *gadget)
2439{
2440 return -ENOTSUPP;
2441}
2442
2443static int lpc32xx_set_selfpowered(struct usb_gadget *gadget, int is_on)
2444{
d60d9392 2445 gadget->is_selfpowered = (is_on != 0);
24a28e42
RS		 2446
2447 return 0;
2448}
2449
2450/*
2451 * vbus is here! turn everything on that's ready
2452 * Must be called without lock
2453 */
2454static int lpc32xx_vbus_session(struct usb_gadget *gadget, int is_active)
2455{
2456 unsigned long flags;
2457 struct lpc32xx_udc *udc = to_udc(gadget);
2458
2459 spin_lock_irqsave(&udc->lock, flags);
2460
2461 /* Doesn't need lock */
2462 if (udc->driver) {
2463 udc_clk_set(udc, 1);
2464 udc_enable(udc);
2465 pullup(udc, is_active);
2466 } else {
2467 stop_activity(udc);
2468 pullup(udc, 0);
2469
2470 spin_unlock_irqrestore(&udc->lock, flags);
2471 /*
2472 * Wait for all the endpoints to disable,
2473 * before disabling clocks. Don't wait if
2474 * endpoints are not enabled.
2475 */
2476 if (atomic_read(&udc->enabled_ep_cnt))
2477 wait_event_interruptible(udc->ep_disable_wait_queue,
2478 (atomic_read(&udc->enabled_ep_cnt) == 0));
2479
2480 spin_lock_irqsave(&udc->lock, flags);
2481
2482 udc_clk_set(udc, 0);
2483 }
2484
2485 spin_unlock_irqrestore(&udc->lock, flags);
2486
2487 return 0;
2488}
2489
2490/* Can be called with or without lock */
2491static int lpc32xx_pullup(struct usb_gadget *gadget, int is_on)
2492{
2493 struct lpc32xx_udc *udc = to_udc(gadget);
2494
2495 /* Doesn't need lock */
2496 pullup(udc, is_on);
2497
2498 return 0;
2499}
2500
252d8cec 2501static int lpc32xx_start(struct usb_gadget *, struct usb_gadget_driver *);
22835b80 2502static int lpc32xx_stop(struct usb_gadget *);
24a28e42
RS		 2503
2504static const struct usb_gadget_ops lpc32xx_udc_ops = {
2505 .get_frame = lpc32xx_get_frame,
2506 .wakeup = lpc32xx_wakeup,
2507 .set_selfpowered = lpc32xx_set_selfpowered,
2508 .vbus_session = lpc32xx_vbus_session,
2509 .pullup = lpc32xx_pullup,
252d8cec
RS		 2510 .udc_start = lpc32xx_start,
2511 .udc_stop = lpc32xx_stop,
24a28e42
RS		 2512};
2513
2514static void nop_release(struct device *dev)
2515{
2516 /* nothing to free */
2517}
2518
c4846a18 2519static const struct lpc32xx_udc controller_template = {
24a28e42
RS		 2520 .gadget = {
2521 .ops = &lpc32xx_udc_ops,
24a28e42
RS		 2522 .name = driver_name,
2523 .dev = {
2524 .init_name = "gadget",
2525 .release = nop_release,
2526 }
2527 },
2528 .ep[0] = {
2529 .ep = {
2530 .name = "ep0",
2531 .ops = &lpc32xx_ep_ops,
4d75c8bd
RB		 2532 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_CONTROL,
2533 USB_EP_CAPS_DIR_ALL),
24a28e42 2534 },
24a28e42
RS		 2535 .maxpacket = 64,
2536 .hwep_num_base = 0,
2537 .hwep_num = 0, /* Can be 0 or 1, has special handling */
2538 .lep = 0,
2539 .eptype = EP_CTL_TYPE,
2540 },
2541 .ep[1] = {
2542 .ep = {
2543 .name = "ep1-int",
2544 .ops = &lpc32xx_ep_ops,
4d75c8bd
RB		 2545 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT,
2546 USB_EP_CAPS_DIR_ALL),
24a28e42 2547 },
24a28e42
RS		 2548 .maxpacket = 64,
2549 .hwep_num_base = 2,
2550 .hwep_num = 0, /* 2 or 3, will be set later */
2551 .lep = 1,
2552 .eptype = EP_INT_TYPE,
2553 },
2554 .ep[2] = {
2555 .ep = {
2556 .name = "ep2-bulk",
2557 .ops = &lpc32xx_ep_ops,
4d75c8bd
RB		 2558 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2559 USB_EP_CAPS_DIR_ALL),
24a28e42 2560 },
24a28e42
RS		 2561 .maxpacket = 64,
2562 .hwep_num_base = 4,
2563 .hwep_num = 0, /* 4 or 5, will be set later */
2564 .lep = 2,
2565 .eptype = EP_BLK_TYPE,
2566 },
2567 .ep[3] = {
2568 .ep = {
2569 .name = "ep3-iso",
2570 .ops = &lpc32xx_ep_ops,
4d75c8bd
RB		 2571 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
2572 USB_EP_CAPS_DIR_ALL),
24a28e42 2573 },
24a28e42
RS		 2574 .maxpacket = 1023,
2575 .hwep_num_base = 6,
2576 .hwep_num = 0, /* 6 or 7, will be set later */
2577 .lep = 3,
2578 .eptype = EP_ISO_TYPE,
2579 },
2580 .ep[4] = {
2581 .ep = {
2582 .name = "ep4-int",
2583 .ops = &lpc32xx_ep_ops,
4d75c8bd
RB		 2584 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT,
2585 USB_EP_CAPS_DIR_ALL),
24a28e42 2586 },
24a28e42
RS		 2587 .maxpacket = 64,
2588 .hwep_num_base = 8,
2589 .hwep_num = 0, /* 8 or 9, will be set later */
2590 .lep = 4,
2591 .eptype = EP_INT_TYPE,
2592 },
2593 .ep[5] = {
2594 .ep = {
2595 .name = "ep5-bulk",
2596 .ops = &lpc32xx_ep_ops,
4d75c8bd
RB		 2597 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2598 USB_EP_CAPS_DIR_ALL),
24a28e42 2599 },
24a28e42
RS		 2600 .maxpacket = 64,
2601 .hwep_num_base = 10,
2602 .hwep_num = 0, /* 10 or 11, will be set later */
2603 .lep = 5,
2604 .eptype = EP_BLK_TYPE,
2605 },
2606 .ep[6] = {
2607 .ep = {
2608 .name = "ep6-iso",
2609 .ops = &lpc32xx_ep_ops,
4d75c8bd
RB		 2610 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
2611 USB_EP_CAPS_DIR_ALL),
24a28e42 2612 },
24a28e42
RS		 2613 .maxpacket = 1023,
2614 .hwep_num_base = 12,
2615 .hwep_num = 0, /* 12 or 13, will be set later */
2616 .lep = 6,
2617 .eptype = EP_ISO_TYPE,
2618 },
2619 .ep[7] = {
2620 .ep = {
2621 .name = "ep7-int",
2622 .ops = &lpc32xx_ep_ops,
4d75c8bd
RB		 2623 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT,
2624 USB_EP_CAPS_DIR_ALL),
24a28e42 2625 },
24a28e42
RS		 2626 .maxpacket = 64,
2627 .hwep_num_base = 14,
2628 .hwep_num = 0,
2629 .lep = 7,
2630 .eptype = EP_INT_TYPE,
2631 },
2632 .ep[8] = {
2633 .ep = {
2634 .name = "ep8-bulk",
2635 .ops = &lpc32xx_ep_ops,
4d75c8bd
RB		 2636 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2637 USB_EP_CAPS_DIR_ALL),
24a28e42 2638 },
24a28e42
RS		 2639 .maxpacket = 64,
2640 .hwep_num_base = 16,
2641 .hwep_num = 0,
2642 .lep = 8,
2643 .eptype = EP_BLK_TYPE,
2644 },
2645 .ep[9] = {
2646 .ep = {
2647 .name = "ep9-iso",
2648 .ops = &lpc32xx_ep_ops,
4d75c8bd
RB		 2649 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
2650 USB_EP_CAPS_DIR_ALL),
24a28e42 2651 },
24a28e42
RS		 2652 .maxpacket = 1023,
2653 .hwep_num_base = 18,
2654 .hwep_num = 0,
2655 .lep = 9,
2656 .eptype = EP_ISO_TYPE,
2657 },
2658 .ep[10] = {
2659 .ep = {
2660 .name = "ep10-int",
2661 .ops = &lpc32xx_ep_ops,
4d75c8bd
RB		 2662 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT,
2663 USB_EP_CAPS_DIR_ALL),
24a28e42 2664 },
24a28e42
RS		 2665 .maxpacket = 64,
2666 .hwep_num_base = 20,
2667 .hwep_num = 0,
2668 .lep = 10,
2669 .eptype = EP_INT_TYPE,
2670 },
2671 .ep[11] = {
2672 .ep = {
2673 .name = "ep11-bulk",
2674 .ops = &lpc32xx_ep_ops,
4d75c8bd
RB		 2675 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2676 USB_EP_CAPS_DIR_ALL),
24a28e42 2677 },
24a28e42
RS		 2678 .maxpacket = 64,
2679 .hwep_num_base = 22,
2680 .hwep_num = 0,
2681 .lep = 11,
2682 .eptype = EP_BLK_TYPE,
2683 },
2684 .ep[12] = {
2685 .ep = {
2686 .name = "ep12-iso",
2687 .ops = &lpc32xx_ep_ops,
4d75c8bd
RB		 2688 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
2689 USB_EP_CAPS_DIR_ALL),
24a28e42 2690 },
24a28e42
RS		 2691 .maxpacket = 1023,
2692 .hwep_num_base = 24,
2693 .hwep_num = 0,
2694 .lep = 12,
2695 .eptype = EP_ISO_TYPE,
2696 },
2697 .ep[13] = {
2698 .ep = {
2699 .name = "ep13-int",
2700 .ops = &lpc32xx_ep_ops,
4d75c8bd
RB		 2701 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT,
2702 USB_EP_CAPS_DIR_ALL),
24a28e42 2703 },
24a28e42
RS		 2704 .maxpacket = 64,
2705 .hwep_num_base = 26,
2706 .hwep_num = 0,
2707 .lep = 13,
2708 .eptype = EP_INT_TYPE,
2709 },
2710 .ep[14] = {
2711 .ep = {
2712 .name = "ep14-bulk",
2713 .ops = &lpc32xx_ep_ops,
4d75c8bd
RB		 2714 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2715 USB_EP_CAPS_DIR_ALL),
24a28e42 2716 },
24a28e42
RS		 2717 .maxpacket = 64,
2718 .hwep_num_base = 28,
2719 .hwep_num = 0,
2720 .lep = 14,
2721 .eptype = EP_BLK_TYPE,
2722 },
2723 .ep[15] = {
2724 .ep = {
2725 .name = "ep15-bulk",
2726 .ops = &lpc32xx_ep_ops,
4d75c8bd
RB		 2727 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2728 USB_EP_CAPS_DIR_ALL),
24a28e42 2729 },
24a28e42
RS		 2730 .maxpacket = 1023,
2731 .hwep_num_base = 30,
2732 .hwep_num = 0,
2733 .lep = 15,
2734 .eptype = EP_BLK_TYPE,
2735 },
2736};
2737
2738/* ISO and status interrupts */
2739static irqreturn_t lpc32xx_usb_lp_irq(int irq, void *_udc)
2740{
2741 u32 tmp, devstat;
2742 struct lpc32xx_udc *udc = _udc;
2743
2744 spin_lock(&udc->lock);
2745
2746 /* Read the device status register */
2747 devstat = readl(USBD_DEVINTST(udc->udp_baseaddr));
2748
2749 devstat &= ~USBD_EP_FAST;
2750 writel(devstat, USBD_DEVINTCLR(udc->udp_baseaddr));
2751 devstat = devstat & udc->enabled_devints;
2752
2753 /* Device specific handling needed? */
2754 if (devstat & USBD_DEV_STAT)
2755 udc_handle_dev(udc);
2756
2757 /* Start of frame? (devstat & FRAME_INT):
2758 * The frame interrupt isn't really needed for ISO support,
2759 * as the driver will queue the necessary packets */
2760
2761 /* Error? */
2762 if (devstat & ERR_INT) {
2763 /* All types of errors, from cable removal during transfer to
2764 * misc protocol and bit errors. These are mostly for just info,
2765 * as the USB hardware will work around these. If these errors
2766 * happen alot, something is wrong. */
2767 udc_protocol_cmd_w(udc, CMD_RD_ERR_STAT);
2768 tmp = udc_protocol_cmd_r(udc, DAT_RD_ERR_STAT);
2769 dev_dbg(udc->dev, "Device error (0x%x)!\n", tmp);
2770 }
2771
2772 spin_unlock(&udc->lock);
2773
2774 return IRQ_HANDLED;
2775}
2776
2777/* EP interrupts */
2778static irqreturn_t lpc32xx_usb_hp_irq(int irq, void *_udc)
2779{
2780 u32 tmp;
2781 struct lpc32xx_udc *udc = _udc;
2782
2783 spin_lock(&udc->lock);
2784
2785 /* Read the device status register */
2786 writel(USBD_EP_FAST, USBD_DEVINTCLR(udc->udp_baseaddr));
2787
2788 /* Endpoints */
2789 tmp = readl(USBD_EPINTST(udc->udp_baseaddr));
2790
2791 /* Special handling for EP0 */
2792 if (tmp & (EP_MASK_SEL(0, EP_OUT) | EP_MASK_SEL(0, EP_IN))) {
2793 /* Handle EP0 IN */
2794 if (tmp & (EP_MASK_SEL(0, EP_IN)))
2795 udc_handle_ep0_in(udc);
2796
2797 /* Handle EP0 OUT */
2798 if (tmp & (EP_MASK_SEL(0, EP_OUT)))
2799 udc_handle_ep0_out(udc);
2800 }
2801
2802 /* All other EPs */
2803 if (tmp & ~(EP_MASK_SEL(0, EP_OUT) | EP_MASK_SEL(0, EP_IN))) {
2804 int i;
2805
2806 /* Handle other EP interrupts */
2807 for (i = 1; i < NUM_ENDPOINTS; i++) {
2808 if (tmp & (1 << udc->ep[i].hwep_num))
2809 udc_handle_eps(udc, &udc->ep[i]);
2810 }
2811 }
2812
2813 spin_unlock(&udc->lock);
2814
2815 return IRQ_HANDLED;
2816}
2817
2818static irqreturn_t lpc32xx_usb_devdma_irq(int irq, void *_udc)
2819{
2820 struct lpc32xx_udc *udc = _udc;
2821
2822 int i;
2823 u32 tmp;
2824
2825 spin_lock(&udc->lock);
2826
2827 /* Handle EP DMA EOT interrupts */
2828 tmp = readl(USBD_EOTINTST(udc->udp_baseaddr)) |
2829 (readl(USBD_EPDMAST(udc->udp_baseaddr)) &
2830 readl(USBD_NDDRTINTST(udc->udp_baseaddr))) |
2831 readl(USBD_SYSERRTINTST(udc->udp_baseaddr));
2832 for (i = 1; i < NUM_ENDPOINTS; i++) {
2833 if (tmp & (1 << udc->ep[i].hwep_num))
2834 udc_handle_dma_ep(udc, &udc->ep[i]);
2835 }
2836
2837 spin_unlock(&udc->lock);
2838
2839 return IRQ_HANDLED;
2840}
2841
2842/*
2843 *
2844 * VBUS detection, pullup handler, and Gadget cable state notification
2845 *
2846 */
59a9901e 2847static void vbus_work(struct lpc32xx_udc *udc)
24a28e42
RS		 2848{
2849 u8 value;
24a28e42
RS		 2850
2851 if (udc->enabled != 0) {
2852 /* Discharge VBUS real quick */
2853 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2854 ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DISCHRG);
2855
2856 /* Give VBUS some time (100mS) to discharge */
2857 msleep(100);
2858
2859 /* Disable VBUS discharge resistor */
2860 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2861 ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
2862 OTG1_VBUS_DISCHRG);
2863
2864 /* Clear interrupt */
2865 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2866 ISP1301_I2C_INTERRUPT_LATCH |
2867 ISP1301_I2C_REG_CLEAR_ADDR, ~0);
2868
2869 /* Get the VBUS status from the transceiver */
2870 value = i2c_smbus_read_byte_data(udc->isp1301_i2c_client,
69da85ed 2871 ISP1301_I2C_INTERRUPT_SOURCE);
24a28e42
RS		 2872
2873 /* VBUS on or off? */
69da85ed 2874 if (value & INT_SESS_VLD)
24a28e42
RS		 2875 udc->vbus = 1;
2876 else
2877 udc->vbus = 0;
2878
2879 /* VBUS changed? */
2880 if (udc->last_vbus != udc->vbus) {
2881 udc->last_vbus = udc->vbus;
2882 lpc32xx_vbus_session(&udc->gadget, udc->vbus);
2883 }
2884 }
24a28e42
RS		 2885}
2886
2887static irqreturn_t lpc32xx_usb_vbus_irq(int irq, void *_udc)
2888{
2889 struct lpc32xx_udc *udc = _udc;
2890
59a9901e 2891 vbus_work(udc);
24a28e42
RS		 2892
2893 return IRQ_HANDLED;
2894}
2895
252d8cec
RS		 2896static int lpc32xx_start(struct usb_gadget *gadget,
2897 struct usb_gadget_driver *driver)
24a28e42 2898{
252d8cec 2899 struct lpc32xx_udc *udc = to_udc(gadget);
24a28e42 2900
252d8cec 2901 if (!driver || driver->max_speed < USB_SPEED_FULL || !driver->setup) {
24a28e42
RS		 2902 dev_err(udc->dev, "bad parameter.\n");
2903 return -EINVAL;
2904 }
2905
2906 if (udc->driver) {
2907 dev_err(udc->dev, "UDC already has a gadget driver\n");
2908 return -EBUSY;
2909 }
2910
2911 udc->driver = driver;
eebc0d36 2912 udc->gadget.dev.of_node = udc->dev->of_node;
24a28e42 2913 udc->enabled = 1;
d60d9392 2914 udc->gadget.is_selfpowered = 1;
24a28e42
RS		 2915 udc->vbus = 0;
2916
24a28e42
RS		 2917 /* Force VBUS process once to check for cable insertion */
2918 udc->last_vbus = udc->vbus = 0;
59a9901e 2919 vbus_work(udc);
24a28e42 2920
c67d4262
AB		 2921 /* enable interrupts */
2922 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2923 ISP1301_I2C_INTERRUPT_FALLING, INT_SESS_VLD | INT_VBUS_VLD);
2924 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2925 ISP1301_I2C_INTERRUPT_RISING, INT_SESS_VLD | INT_VBUS_VLD);
24a28e42
RS		 2926
2927 return 0;
2928}
2929
22835b80 2930static int lpc32xx_stop(struct usb_gadget *gadget)
24a28e42 2931{
252d8cec 2932 struct lpc32xx_udc *udc = to_udc(gadget);
24a28e42 2933
c67d4262
AB		 2934 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2935 ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
2936 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2937 ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
24a28e42
RS		 2938
2939 if (udc->clocked) {
24a28e42
RS		 2940 spin_lock(&udc->lock);
2941 stop_activity(udc);
2942 spin_unlock(&udc->lock);
2943
2944 /*
2945 * Wait for all the endpoints to disable,
2946 * before disabling clocks. Don't wait if
2947 * endpoints are not enabled.
2948 */
2949 if (atomic_read(&udc->enabled_ep_cnt))
2950 wait_event_interruptible(udc->ep_disable_wait_queue,
2951 (atomic_read(&udc->enabled_ep_cnt) == 0));
2952
2953 spin_lock(&udc->lock);
2954 udc_clk_set(udc, 0);
2955 spin_unlock(&udc->lock);
2956 }
2957
2958 udc->enabled = 0;
24a28e42
RS		 2959 udc->driver = NULL;
2960
24a28e42
RS		 2961 return 0;
2962}
2963
2964static void lpc32xx_udc_shutdown(struct platform_device *dev)
2965{
2966 /* Force disconnect on reboot */
252d8cec 2967 struct lpc32xx_udc *udc = platform_get_drvdata(dev);
24a28e42
RS		 2968
2969 pullup(udc, 0);
2970}
2971
2972/*
2973 * Callbacks to be overridden by options passed via OF (TODO)
2974 */
2975
2976static void lpc32xx_usbd_conn_chg(int conn)
2977{
2978 /* Do nothing, it might be nice to enable an LED
2979 * based on conn state being !0 */
2980}
2981
2982static void lpc32xx_usbd_susp_chg(int susp)
2983{
2984 /* Device suspend if susp != 0 */
2985}
2986
2987static void lpc32xx_rmwkup_chg(int remote_wakup_enable)
2988{
2989 /* Enable or disable USB remote wakeup */
2990}
2991
2992struct lpc32xx_usbd_cfg lpc32xx_usbddata = {
2993 .vbus_drv_pol = 0,
2994 .conn_chgb = &lpc32xx_usbd_conn_chg,
2995 .susp_chgb = &lpc32xx_usbd_susp_chg,
2996 .rmwk_chgb = &lpc32xx_rmwkup_chg,
2997};
2998
2999
3000static u64 lpc32xx_usbd_dmamask = ~(u32) 0x7F;
3001
b1a7c4f2 3002static int lpc32xx_udc_probe(struct platform_device *pdev)
24a28e42
RS		 3003{
3004 struct device *dev = &pdev->dev;
c4846a18 3005 struct lpc32xx_udc *udc;
24a28e42
RS		 3006 int retval, i;
3007 struct resource *res;
3008 dma_addr_t dma_handle;
3009 struct device_node *isp1301_node;
3010
408b56ca 3011 udc = devm_kmemdup(dev, &controller_template, sizeof(*udc), GFP_KERNEL);
c4846a18
RS		 3012 if (!udc)
3013 return -ENOMEM;
3014
c4846a18
RS		 3015 for (i = 0; i <= 15; i++)
3016 udc->ep[i].udc = udc;
3017 udc->gadget.ep0 = &udc->ep[0].ep;
3018
24a28e42
RS		 3019 /* init software state */
3020 udc->gadget.dev.parent = dev;
3021 udc->pdev = pdev;
3022 udc->dev = &pdev->dev;
3023 udc->enabled = 0;
3024
3025 if (pdev->dev.of_node) {
3026 isp1301_node = of_parse_phandle(pdev->dev.of_node,
3027 "transceiver", 0);
3028 } else {
3029 isp1301_node = NULL;
3030 }
3031
3032 udc->isp1301_i2c_client = isp1301_get_client(isp1301_node);
c4846a18 3033 if (!udc->isp1301_i2c_client) {
408b56ca 3034 return -EPROBE_DEFER;
c4846a18 3035 }
24a28e42
RS		 3036
3037 dev_info(udc->dev, "ISP1301 I2C device at address 0x%x\n",
3038 udc->isp1301_i2c_client->addr);
3039
3040 pdev->dev.dma_mask = &lpc32xx_usbd_dmamask;
22d9d8e8
RK		 3041 retval = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
3042 if (retval)
408b56ca 3043 return retval;
24a28e42
RS		 3044
3045 udc->board = &lpc32xx_usbddata;
3046
3047 /*
3048 * Resources are mapped as follows:
3049 * IORESOURCE_MEM, base address and size of USB space
3050 * IORESOURCE_IRQ, USB device low priority interrupt number
3051 * IORESOURCE_IRQ, USB device high priority interrupt number
3052 * IORESOURCE_IRQ, USB device interrupt number
3053 * IORESOURCE_IRQ, USB transceiver interrupt number
3054 */
3055 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
408b56ca
AB		 3056 if (!res)
3057 return -ENXIO;
24a28e42
RS		 3058
3059 spin_lock_init(&udc->lock);
3060
3061 /* Get IRQs */
3062 for (i = 0; i < 4; i++) {
3063 udc->udp_irq[i] = platform_get_irq(pdev, i);
3064 if (udc->udp_irq[i] < 0) {
3065 dev_err(udc->dev,
3066 "irq resource %d not available!\n", i);
408b56ca 3067 return udc->udp_irq[i];
24a28e42
RS		 3068 }
3069 }
3070
408b56ca 3071 udc->udp_baseaddr = devm_ioremap_resource(dev, res);
42cc6886 3072 if (IS_ERR(udc->udp_baseaddr)) {
24a28e42 3073 dev_err(udc->dev, "IO map failure\n");
42cc6886 3074 return PTR_ERR(udc->udp_baseaddr);
24a28e42
RS		 3075 }
3076
59e05272 3077 /* Get USB device clock */
408b56ca 3078 udc->usb_slv_clk = devm_clk_get(&pdev->dev, NULL);
24a28e42
RS		 3079 if (IS_ERR(udc->usb_slv_clk)) {
3080 dev_err(udc->dev, "failed to acquire USB device clock\n");
408b56ca 3081 return PTR_ERR(udc->usb_slv_clk);
24a28e42 3082 }
24a28e42 3083
24a28e42 3084 /* Enable USB device clock */
68726e77 3085 retval = clk_prepare_enable(udc->usb_slv_clk);
24a28e42
RS		 3086 if (retval < 0) {
3087 dev_err(udc->dev, "failed to start USB device clock\n");
408b56ca 3088 return retval;
24a28e42
RS		 3089 }
3090
24a28e42
RS		 3091 /* Setup deferred workqueue data */
3092 udc->poweron = udc->pullup = 0;
3093 INIT_WORK(&udc->pullup_job, pullup_work);
24a28e42
RS		 3094#ifdef CONFIG_PM
3095 INIT_WORK(&udc->power_job, power_work);
3096#endif
3097
3098 /* All clocks are now on */
3099 udc->clocked = 1;
3100
3101 isp1301_udc_configure(udc);
3102 /* Allocate memory for the UDCA */
3103 udc->udca_v_base = dma_alloc_coherent(&pdev->dev, UDCA_BUFF_SIZE,
3104 &dma_handle,
3105 (GFP_KERNEL | GFP_DMA));
3106 if (!udc->udca_v_base) {
3107 dev_err(udc->dev, "error getting UDCA region\n");
3108 retval = -ENOMEM;
3109 goto i2c_fail;
3110 }
3111 udc->udca_p_base = dma_handle;
3112 dev_dbg(udc->dev, "DMA buffer(0x%x bytes), P:0x%08x, V:0x%p\n",
3113 UDCA_BUFF_SIZE, udc->udca_p_base, udc->udca_v_base);
3114
3115 /* Setup the DD DMA memory pool */
3116 udc->dd_cache = dma_pool_create("udc_dd", udc->dev,
3117 sizeof(struct lpc32xx_usbd_dd_gad),
3118 sizeof(u32), 0);
3119 if (!udc->dd_cache) {
3120 dev_err(udc->dev, "error getting DD DMA region\n");
3121 retval = -ENOMEM;
3122 goto dma_alloc_fail;
3123 }
3124
3125 /* Clear USB peripheral and initialize gadget endpoints */
3126 udc_disable(udc);
3127 udc_reinit(udc);
3128
24a28e42
RS		 3129 /* Request IRQs - low and high priority USB device IRQs are routed to
3130 * the same handler, while the DMA interrupt is routed elsewhere */
408b56ca
AB		 3131 retval = devm_request_irq(dev, udc->udp_irq[IRQ_USB_LP],
3132 lpc32xx_usb_lp_irq, 0, "udc_lp", udc);
24a28e42
RS		 3133 if (retval < 0) {
3134 dev_err(udc->dev, "LP request irq %d failed\n",
3135 udc->udp_irq[IRQ_USB_LP]);
408b56ca 3136 goto irq_req_fail;
24a28e42 3137 }
408b56ca
AB		 3138 retval = devm_request_irq(dev, udc->udp_irq[IRQ_USB_HP],
3139 lpc32xx_usb_hp_irq, 0, "udc_hp", udc);
24a28e42
RS		 3140 if (retval < 0) {
3141 dev_err(udc->dev, "HP request irq %d failed\n",
3142 udc->udp_irq[IRQ_USB_HP]);
408b56ca 3143 goto irq_req_fail;
24a28e42
RS		 3144 }
3145
408b56ca
AB		 3146 retval = devm_request_irq(dev, udc->udp_irq[IRQ_USB_DEVDMA],
3147 lpc32xx_usb_devdma_irq, 0, "udc_dma", udc);
24a28e42
RS		 3148 if (retval < 0) {
3149 dev_err(udc->dev, "DEV request irq %d failed\n",
3150 udc->udp_irq[IRQ_USB_DEVDMA]);
408b56ca 3151 goto irq_req_fail;
24a28e42
RS		 3152 }
3153
3154 /* The transceiver interrupt is used for VBUS detection and will
3155 kick off the VBUS handler function */
59a9901e
AB		 3156 retval = devm_request_threaded_irq(dev, udc->udp_irq[IRQ_USB_ATX], NULL,
3157 lpc32xx_usb_vbus_irq, IRQF_ONESHOT,
3158 "udc_otg", udc);
24a28e42
RS		 3159 if (retval < 0) {
3160 dev_err(udc->dev, "VBUS request irq %d failed\n",
3161 udc->udp_irq[IRQ_USB_ATX]);
408b56ca 3162 goto irq_req_fail;
24a28e42
RS		 3163 }
3164
3165 /* Initialize wait queue */
3166 init_waitqueue_head(&udc->ep_disable_wait_queue);
3167 atomic_set(&udc->enabled_ep_cnt, 0);
3168
24a28e42
RS		 3169 retval = usb_add_gadget_udc(dev, &udc->gadget);
3170 if (retval < 0)
3171 goto add_gadget_fail;
3172
3173 dev_set_drvdata(dev, udc);
3174 device_init_wakeup(dev, 1);
3175 create_debug_file(udc);
3176
3177 /* Disable clocks for now */
3178 udc_clk_set(udc, 0);
3179
3180 dev_info(udc->dev, "%s version %s\n", driver_name, DRIVER_VERSION);
3181 return 0;
3182
3183add_gadget_fail:
408b56ca 3184irq_req_fail:
24a28e42
RS		 3185 dma_pool_destroy(udc->dd_cache);
3186dma_alloc_fail:
3187 dma_free_coherent(&pdev->dev, UDCA_BUFF_SIZE,
3188 udc->udca_v_base, udc->udca_p_base);
3189i2c_fail:
68726e77 3190 clk_disable_unprepare(udc->usb_slv_clk);
24a28e42 3191 dev_err(udc->dev, "%s probe failed, %d\n", driver_name, retval);
408b56ca 3192
24a28e42
RS		 3193 return retval;
3194}
3195
fb4e98ab 3196static int lpc32xx_udc_remove(struct platform_device *pdev)
24a28e42
RS		 3197{
3198 struct lpc32xx_udc *udc = platform_get_drvdata(pdev);
3199
3200 usb_del_gadget_udc(&udc->gadget);
3201 if (udc->driver)
3202 return -EBUSY;
3203
3204 udc_clk_set(udc, 1);
3205 udc_disable(udc);
3206 pullup(udc, 0);
3207
24a28e42
RS		 3208 device_init_wakeup(&pdev->dev, 0);
3209 remove_debug_file(udc);
3210
3211 dma_pool_destroy(udc->dd_cache);
3212 dma_free_coherent(&pdev->dev, UDCA_BUFF_SIZE,
3213 udc->udca_v_base, udc->udca_p_base);
24a28e42 3214
68726e77 3215 clk_disable_unprepare(udc->usb_slv_clk);
24a28e42
RS		 3216
3217 return 0;
3218}
3219
3220#ifdef CONFIG_PM
3221static int lpc32xx_udc_suspend(struct platform_device *pdev, pm_message_t mesg)
3222{
24a28e42
RS		 3223 struct lpc32xx_udc *udc = platform_get_drvdata(pdev);
3224
3225 if (udc->clocked) {
3226 /* Power down ISP */
3227 udc->poweron = 0;
3228 isp1301_set_powerstate(udc, 0);
3229
3230 /* Disable clocking */
3231 udc_clk_set(udc, 0);
3232
3233 /* Keep clock flag on, so we know to re-enable clocks
3234 on resume */
3235 udc->clocked = 1;
3236
24a28e42 3237 /* Kill global USB clock */
68726e77 3238 clk_disable_unprepare(udc->usb_slv_clk);
24a28e42
RS		 3239 }
3240
3241 return 0;
3242}
3243
3244static int lpc32xx_udc_resume(struct platform_device *pdev)
3245{
3246 struct lpc32xx_udc *udc = platform_get_drvdata(pdev);
3247
3248 if (udc->clocked) {
3249 /* Enable global USB clock */
68726e77 3250 clk_prepare_enable(udc->usb_slv_clk);
24a28e42
RS		 3251
3252 /* Enable clocking */
3253 udc_clk_set(udc, 1);
3254
3255 /* ISP back to normal power mode */
3256 udc->poweron = 1;
3257 isp1301_set_powerstate(udc, 1);
3258 }
3259
3260 return 0;
3261}
3262#else
3263#define lpc32xx_udc_suspend NULL
3264#define lpc32xx_udc_resume NULL
3265#endif
3266
3267#ifdef CONFIG_OF
ca118b78 3268static const struct of_device_id lpc32xx_udc_of_match[] = {
24a28e42
RS		 3269 { .compatible = "nxp,lpc3220-udc", },
3270 { },
3271};
3272MODULE_DEVICE_TABLE(of, lpc32xx_udc_of_match);
3273#endif
3274
3275static struct platform_driver lpc32xx_udc_driver = {
7690417d 3276 .remove = lpc32xx_udc_remove,
24a28e42
RS		 3277 .shutdown = lpc32xx_udc_shutdown,
3278 .suspend = lpc32xx_udc_suspend,
3279 .resume = lpc32xx_udc_resume,
3280 .driver = {
3281 .name = (char *) driver_name,
24a28e42
RS		 3282 .of_match_table = of_match_ptr(lpc32xx_udc_of_match),
3283 },
3284};
3285
52f7a82b 3286module_platform_driver_probe(lpc32xx_udc_driver, lpc32xx_udc_probe);
24a28e42
RS		 3287
3288MODULE_DESCRIPTION("LPC32XX udc driver");
3289MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
3290MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
3291MODULE_LICENSE("GPL");
3292MODULE_ALIAS("platform:lpc32xx_udc");
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