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[mirror_ubuntu-bionic-kernel.git] / drivers / usb / gadget / udc / net2280.h
CommitLineData
1da177e4
LT
1/*
2 * NetChip 2280 high/full speed USB device controller.
3 * Unlike many such controllers, this one talks PCI.
4 */
5
6/*
7 * Copyright (C) 2002 NetChip Technology, Inc. (http://www.netchip.com)
8 * Copyright (C) 2003 David Brownell
adc82f77 9 * Copyright (C) 2014 Ricardo Ribalda - Qtechnology/AS
1da177e4
LT
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
1da177e4
LT
15 */
16
9fc4831c 17#include <linux/usb/net2280.h>
adc82f77 18#include <linux/usb/usb338x.h>
1da177e4
LT
19
20/*-------------------------------------------------------------------------*/
21
22#ifdef __KERNEL__
23
24/* indexed registers [11.10] are accessed indirectly
25 * caller must own the device lock.
26 */
27
fae3c158 28static inline u32 get_idx_reg(struct net2280_regs __iomem *regs, u32 index)
1da177e4 29{
fae3c158 30 writel(index, &regs->idxaddr);
1da177e4 31 /* NOTE: synchs device/cpu memory views */
fae3c158 32 return readl(&regs->idxdata);
1da177e4
LT
33}
34
35static inline void
fae3c158 36set_idx_reg(struct net2280_regs __iomem *regs, u32 index, u32 value)
1da177e4 37{
fae3c158
RRD
38 writel(index, &regs->idxaddr);
39 writel(value, &regs->idxdata);
1da177e4
LT
40 /* posted, may not be visible yet */
41}
42
43#endif /* __KERNEL__ */
44
c2db8a8a 45#define PCI_VENDOR_ID_PLX_LEGACY 0x17cc
1da177e4 46
2eeb0016
RRD
47#define PLX_LEGACY BIT(0)
48#define PLX_2280 BIT(1)
49#define PLX_SUPERSPEED BIT(2)
50
1da177e4
LT
51#define REG_DIAG 0x0
52#define RETRY_COUNTER 16
53#define FORCE_PCI_SERR 11
54#define FORCE_PCI_INTERRUPT 10
55#define FORCE_USB_INTERRUPT 9
56#define FORCE_CPU_INTERRUPT 8
57#define ILLEGAL_BYTE_ENABLES 5
58#define FAST_TIMES 4
59#define FORCE_RECEIVE_ERROR 2
60#define FORCE_TRANSMIT_CRC_ERROR 0
61#define REG_FRAME 0x02 /* from last sof */
62#define REG_CHIPREV 0x03 /* in bcd */
63#define REG_HS_NAK_RATE 0x0a /* NAK per N uframes */
64
65#define CHIPREV_1 0x0100
66#define CHIPREV_1A 0x0110
67
adc82f77
RRD
68/* DEFECT 7374 */
69#define DEFECT_7374_NUMBEROF_MAX_WAIT_LOOPS 200
70#define DEFECT_7374_PROCESSOR_WAIT_TIME 10
1da177e4 71
adc82f77
RRD
72/* ep0 max packet size */
73#define EP0_SS_MAX_PACKET_SIZE 0x200
74#define EP0_HS_MAX_PACKET_SIZE 0x40
75#ifdef __KERNEL__
1da177e4
LT
76
77/*-------------------------------------------------------------------------*/
78
79/* [8.3] for scatter/gather i/o
80 * use struct net2280_dma_regs bitfields
81 */
82struct net2280_dma {
83 __le32 dmacount;
84 __le32 dmaaddr; /* the buffer */
85 __le32 dmadesc; /* next dma descriptor */
86 __le32 _reserved;
fae3c158 87} __aligned(16);
1da177e4
LT
88
89/*-------------------------------------------------------------------------*/
90
91/* DRIVER DATA STRUCTURES and UTILITIES */
92
93struct net2280_ep {
94 struct usb_ep ep;
adc82f77 95 struct net2280_ep_regs __iomem *cfg;
1da177e4
LT
96 struct net2280_ep_regs __iomem *regs;
97 struct net2280_dma_regs __iomem *dma;
98 struct net2280_dma *dummy;
99 dma_addr_t td_dma; /* of dummy */
100 struct net2280 *dev;
101 unsigned long irqs;
102
103 /* analogous to a host-side qh */
104 struct list_head queue;
105 const struct usb_endpoint_descriptor *desc;
106 unsigned num : 8,
107 fifo_size : 12,
108 in_fifo_validate : 1,
109 out_overflow : 1,
110 stopped : 1,
8066134f 111 wedged : 1,
1da177e4 112 is_in : 1,
1f26e28d
AS
113 is_iso : 1,
114 responded : 1;
1da177e4
LT
115};
116
fae3c158 117static inline void allow_status(struct net2280_ep *ep)
1da177e4
LT
118{
119 /* ep0 only */
3e76fdcb
RRD
120 writel(BIT(CLEAR_CONTROL_STATUS_PHASE_HANDSHAKE) |
121 BIT(CLEAR_NAK_OUT_PACKETS) |
ae8e530a
RRD
122 BIT(CLEAR_NAK_OUT_PACKETS_MODE),
123 &ep->regs->ep_rsp);
1da177e4
LT
124 ep->stopped = 1;
125}
126
6897d4b2 127static inline void allow_status_338x(struct net2280_ep *ep)
1da177e4 128{
adc82f77
RRD
129 /*
130 * Control Status Phase Handshake was set by the chip when the setup
131 * packet arrived. While set, the chip automatically NAKs the host's
132 * Status Phase tokens.
133 */
3e76fdcb 134 writel(BIT(CLEAR_CONTROL_STATUS_PHASE_HANDSHAKE), &ep->regs->ep_rsp);
adc82f77
RRD
135
136 ep->stopped = 1;
137
138 /* TD 9.9 Halt Endpoint test. TD 9.22 set feature test. */
139 ep->responded = 0;
1da177e4
LT
140}
141
142struct net2280_request {
143 struct usb_request req;
144 struct net2280_dma *td;
145 dma_addr_t td_dma;
146 struct list_head queue;
147 unsigned mapped : 1,
148 valid : 1;
149};
150
151struct net2280 {
152 /* each pci device provides one gadget, several endpoints */
153 struct usb_gadget gadget;
154 spinlock_t lock;
adc82f77 155 struct net2280_ep ep[9];
fae3c158 156 struct usb_gadget_driver *driver;
1da177e4
LT
157 unsigned enabled : 1,
158 protocol_stall : 1,
159 softconnect : 1,
160 got_irq : 1,
adc82f77
RRD
161 region:1,
162 u1_enable:1,
163 u2_enable:1,
164 ltm_enable:1,
165 wakeup_enable:1,
5517525e
RRD
166 addressed_state:1,
167 bug7734_patched:1;
1da177e4 168 u16 chiprev;
adc82f77
RRD
169 int enhanced_mode;
170 int n_ep;
2eeb0016
RRD
171 kernel_ulong_t quirks;
172
1da177e4
LT
173
174 /* pci state used to access those endpoints */
175 struct pci_dev *pdev;
176 struct net2280_regs __iomem *regs;
177 struct net2280_usb_regs __iomem *usb;
adc82f77 178 struct usb338x_usb_ext_regs __iomem *usb_ext;
1da177e4
LT
179 struct net2280_pci_regs __iomem *pci;
180 struct net2280_dma_regs __iomem *dma;
181 struct net2280_dep_regs __iomem *dep;
182 struct net2280_ep_regs __iomem *epregs;
adc82f77
RRD
183 struct usb338x_ll_regs __iomem *llregs;
184 struct usb338x_ll_lfps_regs __iomem *ll_lfps_regs;
185 struct usb338x_ll_tsn_regs __iomem *ll_tsn_regs;
186 struct usb338x_ll_chi_regs __iomem *ll_chicken_reg;
187 struct usb338x_pl_regs __iomem *plregs;
1da177e4
LT
188
189 struct pci_pool *requests;
fae3c158 190 /* statistics...*/
1da177e4
LT
191};
192
fae3c158 193static inline void set_halt(struct net2280_ep *ep)
1da177e4
LT
194{
195 /* ep0 and bulk/intr endpoints */
3e76fdcb
RRD
196 writel(BIT(CLEAR_CONTROL_STATUS_PHASE_HANDSHAKE) |
197 /* set NAK_OUT for erratum 0114 */
198 ((ep->dev->chiprev == CHIPREV_1) << SET_NAK_OUT_PACKETS) |
199 BIT(SET_ENDPOINT_HALT),
200 &ep->regs->ep_rsp);
1da177e4
LT
201}
202
fae3c158 203static inline void clear_halt(struct net2280_ep *ep)
1da177e4
LT
204{
205 /* ep0 and bulk/intr endpoints */
3e76fdcb
RRD
206 writel(BIT(CLEAR_ENDPOINT_HALT) |
207 BIT(CLEAR_ENDPOINT_TOGGLE) |
208 /*
209 * unless the gadget driver left a short packet in the
1da177e4
LT
210 * fifo, this reverses the erratum 0114 workaround.
211 */
3e76fdcb
RRD
212 ((ep->dev->chiprev == CHIPREV_1) << CLEAR_NAK_OUT_PACKETS),
213 &ep->regs->ep_rsp);
1da177e4
LT
214}
215
adc82f77
RRD
216/*
217 * FSM value for Defect 7374 (U1U2 Test) is managed in
218 * chip's SCRATCH register:
219 */
220#define DEFECT7374_FSM_FIELD 28
221
222/* Waiting for Control Read:
223 * - A transition to this state indicates a fresh USB connection,
224 * before the first Setup Packet. The connection speed is not
225 * known. Firmware is waiting for the first Control Read.
226 * - Starting state: This state can be thought of as the FSM's typical
227 * starting state.
228 * - Tip: Upon the first SS Control Read the FSM never
229 * returns to this state.
230 */
3e76fdcb 231#define DEFECT7374_FSM_WAITING_FOR_CONTROL_READ BIT(DEFECT7374_FSM_FIELD)
adc82f77
RRD
232
233/* Non-SS Control Read:
234 * - A transition to this state indicates detection of the first HS
235 * or FS Control Read.
236 * - Tip: Upon the first SS Control Read the FSM never
237 * returns to this state.
238 */
239#define DEFECT7374_FSM_NON_SS_CONTROL_READ (2 << DEFECT7374_FSM_FIELD)
240
241/* SS Control Read:
242 * - A transition to this state indicates detection of the
243 * first SS Control Read.
244 * - This state indicates workaround completion. Workarounds no longer
245 * need to be applied (as long as the chip remains powered up).
246 * - Tip: Once in this state the FSM state does not change (until
247 * the chip's power is lost and restored).
248 * - This can be thought of as the final state of the FSM;
249 * the FSM 'locks-up' in this state until the chip loses power.
250 */
251#define DEFECT7374_FSM_SS_CONTROL_READ (3 << DEFECT7374_FSM_FIELD)
252
1da177e4
LT
253#ifdef USE_RDK_LEDS
254
fae3c158 255static inline void net2280_led_init(struct net2280 *dev)
1da177e4
LT
256{
257 /* LED3 (green) is on during USB activity. note erratum 0113. */
3e76fdcb
RRD
258 writel(BIT(GPIO3_LED_SELECT) |
259 BIT(GPIO3_OUTPUT_ENABLE) |
260 BIT(GPIO2_OUTPUT_ENABLE) |
261 BIT(GPIO1_OUTPUT_ENABLE) |
262 BIT(GPIO0_OUTPUT_ENABLE),
263 &dev->regs->gpioctl);
1da177e4
LT
264}
265
266/* indicate speed with bi-color LED 0/1 */
267static inline
fae3c158 268void net2280_led_speed(struct net2280 *dev, enum usb_device_speed speed)
1da177e4 269{
fae3c158 270 u32 val = readl(&dev->regs->gpioctl);
1da177e4 271 switch (speed) {
adc82f77 272 case USB_SPEED_SUPER: /* green + red */
3e76fdcb 273 val |= BIT(GPIO0_DATA) | BIT(GPIO1_DATA);
adc82f77 274 break;
1da177e4 275 case USB_SPEED_HIGH: /* green */
3e76fdcb
RRD
276 val &= ~BIT(GPIO0_DATA);
277 val |= BIT(GPIO1_DATA);
1da177e4
LT
278 break;
279 case USB_SPEED_FULL: /* red */
3e76fdcb
RRD
280 val &= ~BIT(GPIO1_DATA);
281 val |= BIT(GPIO0_DATA);
1da177e4
LT
282 break;
283 default: /* (off/black) */
3e76fdcb 284 val &= ~(BIT(GPIO1_DATA) | BIT(GPIO0_DATA));
1da177e4
LT
285 break;
286 }
fae3c158 287 writel(val, &dev->regs->gpioctl);
1da177e4
LT
288}
289
290/* indicate power with LED 2 */
fae3c158 291static inline void net2280_led_active(struct net2280 *dev, int is_active)
1da177e4 292{
fae3c158 293 u32 val = readl(&dev->regs->gpioctl);
1da177e4 294
fae3c158 295 /* FIXME this LED never seems to turn on.*/
1da177e4
LT
296 if (is_active)
297 val |= GPIO2_DATA;
298 else
299 val &= ~GPIO2_DATA;
fae3c158 300 writel(val, &dev->regs->gpioctl);
1da177e4 301}
fae3c158
RRD
302
303static inline void net2280_led_shutdown(struct net2280 *dev)
1da177e4
LT
304{
305 /* turn off all four GPIO*_DATA bits */
fae3c158 306 writel(readl(&dev->regs->gpioctl) & ~0x0f,
1da177e4
LT
307 &dev->regs->gpioctl);
308}
309
310#else
311
312#define net2280_led_init(dev) do { } while (0)
313#define net2280_led_speed(dev, speed) do { } while (0)
314#define net2280_led_shutdown(dev) do { } while (0)
315
316#endif
317
318/*-------------------------------------------------------------------------*/
319
e56e69cc
RRD
320#define ep_dbg(ndev, fmt, args...) \
321 dev_dbg((&((ndev)->pdev->dev)), fmt, ##args)
1da177e4 322
e56e69cc
RRD
323#define ep_vdbg(ndev, fmt, args...) \
324 dev_vdbg((&((ndev)->pdev->dev)), fmt, ##args)
1da177e4 325
e56e69cc
RRD
326#define ep_info(ndev, fmt, args...) \
327 dev_info((&((ndev)->pdev->dev)), fmt, ##args)
328
329#define ep_warn(ndev, fmt, args...) \
330 dev_warn((&((ndev)->pdev->dev)), fmt, ##args)
1da177e4 331
e56e69cc
RRD
332#define ep_err(ndev, fmt, args...) \
333 dev_err((&((ndev)->pdev->dev)), fmt, ##args)
1da177e4
LT
334
335/*-------------------------------------------------------------------------*/
336
adc82f77
RRD
337static inline void set_fifo_bytecount(struct net2280_ep *ep, unsigned count)
338{
339 if (ep->dev->pdev->vendor == 0x17cc)
340 writeb(count, 2 + (u8 __iomem *) &ep->regs->ep_cfg);
341 else{
342 u32 tmp = readl(&ep->cfg->ep_cfg) &
343 (~(0x07 << EP_FIFO_BYTE_COUNT));
344 writel(tmp | (count << EP_FIFO_BYTE_COUNT), &ep->cfg->ep_cfg);
345 }
346}
347
fae3c158 348static inline void start_out_naking(struct net2280_ep *ep)
1da177e4
LT
349{
350 /* NOTE: hardware races lurk here, and PING protocol issues */
3e76fdcb 351 writel(BIT(SET_NAK_OUT_PACKETS), &ep->regs->ep_rsp);
1da177e4 352 /* synch with device */
fae3c158 353 readl(&ep->regs->ep_rsp);
1da177e4
LT
354}
355
fae3c158 356static inline void stop_out_naking(struct net2280_ep *ep)
1da177e4
LT
357{
358 u32 tmp;
359
fae3c158 360 tmp = readl(&ep->regs->ep_stat);
3e76fdcb
RRD
361 if ((tmp & BIT(NAK_OUT_PACKETS)) != 0)
362 writel(BIT(CLEAR_NAK_OUT_PACKETS), &ep->regs->ep_rsp);
1da177e4
LT
363}
364
adc82f77
RRD
365
366static inline void set_max_speed(struct net2280_ep *ep, u32 max)
367{
368 u32 reg;
369 static const u32 ep_enhanced[9] = { 0x10, 0x60, 0x30, 0x80,
370 0x50, 0x20, 0x70, 0x40, 0x90 };
371
ca1c1189 372 if (ep->dev->enhanced_mode) {
adc82f77 373 reg = ep_enhanced[ep->num];
ca1c1189
SA
374 switch (ep->dev->gadget.speed) {
375 case USB_SPEED_SUPER:
376 reg += 2;
377 break;
378 case USB_SPEED_FULL:
379 reg += 1;
380 break;
381 case USB_SPEED_HIGH:
382 default:
383 break;
384 }
385 } else {
adc82f77
RRD
386 reg = (ep->num + 1) * 0x10;
387 if (ep->dev->gadget.speed != USB_SPEED_HIGH)
388 reg += 1;
389 }
390
391 set_idx_reg(ep->dev->regs, reg, max);
392}
393
1da177e4 394#endif /* __KERNEL__ */