[mirror_ubuntu-jammy-kernel.git] / drivers / usb / host / bcma-hcd.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Broadcom specific Advanced Microcontroller Bus
 * Broadcom USB-core driver (BCMA bus glue)
 *
 * Copyright 2011-2015 Hauke Mehrtens <hauke@hauke-m.de>
 * Copyright 2015 Felix Fietkau <nbd@openwrt.org>
 *
 * Based on ssb-ohci driver
 * Copyright 2007 Michael Buesch <m@bues.ch>
 *
 * Derived from the OHCI-PCI driver
 * Copyright 1999 Roman Weissgaerber
 * Copyright 2000-2002 David Brownell
 * Copyright 1999 Linus Torvalds
 * Copyright 1999 Gregory P. Smith
 *
 * Derived from the USBcore related parts of Broadcom-SB
 * Copyright 2005-2011 Broadcom Corporation
 *
 * Licensed under the GNU/GPL. See COPYING for details.
 */
#include <linux/bcma/bcma.h>
#include <linux/delay.h>
#include <linux/gpio/consumer.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/of_gpio.h>
#include <linux/of_platform.h>
#include <linux/usb/ehci_pdriver.h>
#include <linux/usb/ohci_pdriver.h>

MODULE_AUTHOR("Hauke Mehrtens");
MODULE_DESCRIPTION("Common USB driver for BCMA Bus");
MODULE_LICENSE("GPL");

/* See BCMA_CLKCTLST_EXTRESREQ and BCMA_CLKCTLST_EXTRESST */
#define USB_BCMA_CLKCTLST_USB_CLK_REQ			0x00000100

struct bcma_hcd_device {
	struct bcma_device *core;
	struct platform_device *ehci_dev;
	struct platform_device *ohci_dev;
	struct gpio_desc *gpio_desc;
};

/* Wait for bitmask in a register to get set or cleared.
 * timeout is in units of ten-microseconds.
 */
static int bcma_wait_bits(struct bcma_device *dev, u16 reg, u32 bitmask,
			  int timeout)
{
	int i;
	u32 val;

	for (i = 0; i < timeout; i++) {
		val = bcma_read32(dev, reg);
		if ((val & bitmask) == bitmask)
			return 0;
		udelay(10);
	}

	return -ETIMEDOUT;
}

static void bcma_hcd_4716wa(struct bcma_device *dev)
{
#ifdef CONFIG_BCMA_DRIVER_MIPS
	/* Work around for 4716 failures. */
	if (dev->bus->chipinfo.id == 0x4716) {
		u32 tmp;

		tmp = bcma_cpu_clock(&dev->bus->drv_mips);
		if (tmp >= 480000000)
			tmp = 0x1846b; /* set CDR to 0x11(fast) */
		else if (tmp == 453000000)
			tmp = 0x1046b; /* set CDR to 0x10(slow) */
		else
			tmp = 0;

		/* Change Shim mdio control reg to fix host not acking at
		 * high frequencies
		 */
		if (tmp) {
			bcma_write32(dev, 0x524, 0x1); /* write sel to enable */
			udelay(500);

			bcma_write32(dev, 0x524, tmp);
			udelay(500);
			bcma_write32(dev, 0x524, 0x4ab);
			udelay(500);
			bcma_read32(dev, 0x528);
			bcma_write32(dev, 0x528, 0x80000000);
		}
	}
#endif /* CONFIG_BCMA_DRIVER_MIPS */
}

/* based on arch/mips/brcm-boards/bcm947xx/pcibios.c */
static void bcma_hcd_init_chip_mips(struct bcma_device *dev)
{
	u32 tmp;

	/*
	 * USB 2.0 special considerations:
	 *
	 * 1. Since the core supports both OHCI and EHCI functions, it must
	 *    only be reset once.
	 *
	 * 2. In addition to the standard SI reset sequence, the Host Control
	 *    Register must be programmed to bring the USB core and various
	 *    phy components out of reset.
	 */
	if (!bcma_core_is_enabled(dev)) {
		bcma_core_enable(dev, 0);
		mdelay(10);
		if (dev->id.rev >= 5) {
			/* Enable Misc PLL */
			tmp = bcma_read32(dev, 0x1e0);
			tmp |= 0x100;
			bcma_write32(dev, 0x1e0, tmp);
			if (bcma_wait_bits(dev, 0x1e0, 1 << 24, 100))
				printk(KERN_EMERG "Failed to enable misc PPL!\n");

			/* Take out of resets */
			bcma_write32(dev, 0x200, 0x4ff);
			udelay(25);
			bcma_write32(dev, 0x200, 0x6ff);
			udelay(25);

			/* Make sure digital and AFE are locked in USB PHY */
			bcma_write32(dev, 0x524, 0x6b);
			udelay(50);
			tmp = bcma_read32(dev, 0x524);
			udelay(50);
			bcma_write32(dev, 0x524, 0xab);
			udelay(50);
			tmp = bcma_read32(dev, 0x524);
			udelay(50);
			bcma_write32(dev, 0x524, 0x2b);
			udelay(50);
			tmp = bcma_read32(dev, 0x524);
			udelay(50);
			bcma_write32(dev, 0x524, 0x10ab);
			udelay(50);
			tmp = bcma_read32(dev, 0x524);

			if (bcma_wait_bits(dev, 0x528, 0xc000, 10000)) {
				tmp = bcma_read32(dev, 0x528);
				printk(KERN_EMERG
				       "USB20H mdio_rddata 0x%08x\n", tmp);
			}
			bcma_write32(dev, 0x528, 0x80000000);
			tmp = bcma_read32(dev, 0x314);
			udelay(265);
			bcma_write32(dev, 0x200, 0x7ff);
			udelay(10);

			/* Take USB and HSIC out of non-driving modes */
			bcma_write32(dev, 0x510, 0);
		} else {
			bcma_write32(dev, 0x200, 0x7ff);

			udelay(1);
		}

		bcma_hcd_4716wa(dev);
	}
}

/**
 * bcma_hcd_usb20_old_arm_init - Initialize old USB 2.0 controller on ARM
 *
 * Old USB 2.0 core is identified as BCMA_CORE_USB20_HOST and was introduced
 * long before Northstar devices. It seems some cheaper chipsets like BCM53573
 * still use it.
 * Initialization of this old core differs between MIPS and ARM.
 */
static int bcma_hcd_usb20_old_arm_init(struct bcma_hcd_device *usb_dev)
{
	struct bcma_device *core = usb_dev->core;
	struct device *dev = &core->dev;
	struct bcma_device *pmu_core;

	usleep_range(10000, 20000);
	if (core->id.rev < 5)
		return 0;

	pmu_core = bcma_find_core(core->bus, BCMA_CORE_PMU);
	if (!pmu_core) {
		dev_err(dev, "Could not find PMU core\n");
		return -ENOENT;
	}

	/* Take USB core out of reset */
	bcma_awrite32(core, BCMA_IOCTL, BCMA_IOCTL_CLK | BCMA_IOCTL_FGC);
	usleep_range(100, 200);
	bcma_awrite32(core, BCMA_RESET_CTL, BCMA_RESET_CTL_RESET);
	usleep_range(100, 200);
	bcma_awrite32(core, BCMA_RESET_CTL, 0);
	usleep_range(100, 200);
	bcma_awrite32(core, BCMA_IOCTL, BCMA_IOCTL_CLK);
	usleep_range(100, 200);

	/* Enable Misc PLL */
	bcma_write32(core, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT |
					  BCMA_CLKCTLST_HQCLKREQ |
					  USB_BCMA_CLKCTLST_USB_CLK_REQ);
	usleep_range(100, 200);

	bcma_write32(core, 0x510, 0xc7f85000);
	bcma_write32(core, 0x510, 0xc7f85003);
	usleep_range(300, 600);

	/* Program USB PHY PLL parameters */
	bcma_write32(pmu_core, BCMA_CC_PMU_PLLCTL_ADDR, 0x6);
	bcma_write32(pmu_core, BCMA_CC_PMU_PLLCTL_DATA, 0x005360c1);
	usleep_range(100, 200);
	bcma_write32(pmu_core, BCMA_CC_PMU_PLLCTL_ADDR, 0x7);
	bcma_write32(pmu_core, BCMA_CC_PMU_PLLCTL_DATA, 0x0);
	usleep_range(100, 200);
	bcma_set32(pmu_core, BCMA_CC_PMU_CTL, BCMA_CC_PMU_CTL_PLL_UPD);
	usleep_range(100, 200);

	bcma_write32(core, 0x510, 0x7f8d007);
	udelay(1000);

	/* Take controller out of reset */
	bcma_write32(core, 0x200, 0x4ff);
	usleep_range(25, 50);
	bcma_write32(core, 0x200, 0x6ff);
	usleep_range(25, 50);
	bcma_write32(core, 0x200, 0x7ff);
	usleep_range(25, 50);

	of_platform_default_populate(dev->of_node, NULL, dev);

	return 0;
}

static void bcma_hcd_usb20_ns_init_hc(struct bcma_device *dev)
{
	u32 val;

	/* Set packet buffer OUT threshold */
	val = bcma_read32(dev, 0x94);
	val &= 0xffff;
	val |= 0x80 << 16;
	bcma_write32(dev, 0x94, val);

	/* Enable break memory transfer */
	val = bcma_read32(dev, 0x9c);
	val |= 1;
	bcma_write32(dev, 0x9c, val);

	/*
	 * Broadcom initializes PHY and then waits to ensure HC is ready to be
	 * configured. In our case the order is reversed. We just initialized
	 * controller and we let HCD initialize PHY, so let's wait (sleep) now.
	 */
	usleep_range(1000, 2000);
}

/**
 * bcma_hcd_usb20_ns_init - Initialize Northstar USB 2.0 controller
 */
static int bcma_hcd_usb20_ns_init(struct bcma_hcd_device *bcma_hcd)
{
	struct bcma_device *core = bcma_hcd->core;
	struct bcma_chipinfo *ci = &core->bus->chipinfo;
	struct device *dev = &core->dev;

	bcma_core_enable(core, 0);

	if (ci->id == BCMA_CHIP_ID_BCM4707 ||
	    ci->id == BCMA_CHIP_ID_BCM53018)
		bcma_hcd_usb20_ns_init_hc(core);

	of_platform_default_populate(dev->of_node, NULL, dev);

	return 0;
}

static void bcma_hci_platform_power_gpio(struct bcma_device *dev, bool val)
{
	struct bcma_hcd_device *usb_dev = bcma_get_drvdata(dev);

	if (IS_ERR_OR_NULL(usb_dev->gpio_desc))
		return;

	gpiod_set_value(usb_dev->gpio_desc, val);
}

static const struct usb_ehci_pdata ehci_pdata = {
};

static const struct usb_ohci_pdata ohci_pdata = {
};

static struct platform_device *bcma_hcd_create_pdev(struct bcma_device *dev,
						    const char *name, u32 addr,
						    const void *data,
						    size_t size)
{
	struct platform_device *hci_dev;
	struct resource hci_res[2];
	int ret;

	memset(hci_res, 0, sizeof(hci_res));

	hci_res[0].start = addr;
	hci_res[0].end = hci_res[0].start + 0x1000 - 1;
	hci_res[0].flags = IORESOURCE_MEM;

	hci_res[1].start = dev->irq;
	hci_res[1].flags = IORESOURCE_IRQ;

	hci_dev = platform_device_alloc(name, 0);
	if (!hci_dev)
		return ERR_PTR(-ENOMEM);

	hci_dev->dev.parent = &dev->dev;
	hci_dev->dev.dma_mask = &hci_dev->dev.coherent_dma_mask;

	ret = platform_device_add_resources(hci_dev, hci_res,
					    ARRAY_SIZE(hci_res));
	if (ret)
		goto err_alloc;
	if (data)
		ret = platform_device_add_data(hci_dev, data, size);
	if (ret)
		goto err_alloc;
	ret = platform_device_add(hci_dev);
	if (ret)
		goto err_alloc;

	return hci_dev;

err_alloc:
	platform_device_put(hci_dev);
	return ERR_PTR(ret);
}

static int bcma_hcd_usb20_init(struct bcma_hcd_device *usb_dev)
{
	struct bcma_device *dev = usb_dev->core;
	struct bcma_chipinfo *chipinfo = &dev->bus->chipinfo;
	u32 ohci_addr;
	int err;

	if (dma_set_mask_and_coherent(dev->dma_dev, DMA_BIT_MASK(32)))
		return -EOPNOTSUPP;

	bcma_hcd_init_chip_mips(dev);

	/* In AI chips EHCI is addrspace 0, OHCI is 1 */
	ohci_addr = dev->addr_s[0];
	if ((chipinfo->id == BCMA_CHIP_ID_BCM5357 ||
	     chipinfo->id == BCMA_CHIP_ID_BCM4749)
	    && chipinfo->rev == 0)
		ohci_addr = 0x18009000;

	usb_dev->ohci_dev = bcma_hcd_create_pdev(dev, "ohci-platform",
						 ohci_addr, &ohci_pdata,
						 sizeof(ohci_pdata));
	if (IS_ERR(usb_dev->ohci_dev))
		return PTR_ERR(usb_dev->ohci_dev);

	usb_dev->ehci_dev = bcma_hcd_create_pdev(dev, "ehci-platform",
						 dev->addr, &ehci_pdata,
						 sizeof(ehci_pdata));
	if (IS_ERR(usb_dev->ehci_dev)) {
		err = PTR_ERR(usb_dev->ehci_dev);
		goto err_unregister_ohci_dev;
	}

	return 0;

err_unregister_ohci_dev:
	platform_device_unregister(usb_dev->ohci_dev);
	return err;
}

static int bcma_hcd_usb30_init(struct bcma_hcd_device *bcma_hcd)
{
	struct bcma_device *core = bcma_hcd->core;
	struct device *dev = &core->dev;

	bcma_core_enable(core, 0);

	of_platform_default_populate(dev->of_node, NULL, dev);

	return 0;
}

static int bcma_hcd_probe(struct bcma_device *core)
{
	int err;
	struct bcma_hcd_device *usb_dev;

	/* TODO: Probably need checks here; is the core connected? */

	usb_dev = devm_kzalloc(&core->dev, sizeof(struct bcma_hcd_device),
			       GFP_KERNEL);
	if (!usb_dev)
		return -ENOMEM;
	usb_dev->core = core;

	if (core->dev.of_node)
		usb_dev->gpio_desc = devm_gpiod_get(&core->dev, "vcc",
						    GPIOD_OUT_HIGH);

	switch (core->id.id) {
	case BCMA_CORE_USB20_HOST:
		if (IS_ENABLED(CONFIG_ARM))
			err = bcma_hcd_usb20_old_arm_init(usb_dev);
		else if (IS_ENABLED(CONFIG_MIPS))
			err = bcma_hcd_usb20_init(usb_dev);
		else
			err = -ENOTSUPP;
		break;
	case BCMA_CORE_NS_USB20:
		err = bcma_hcd_usb20_ns_init(usb_dev);
		break;
	case BCMA_CORE_NS_USB30:
		err = bcma_hcd_usb30_init(usb_dev);
		break;
	default:
		return -ENODEV;
	}
	if (err)
		return err;

	bcma_set_drvdata(core, usb_dev);
	return 0;
}

static void bcma_hcd_remove(struct bcma_device *dev)
{
	struct bcma_hcd_device *usb_dev = bcma_get_drvdata(dev);
	struct platform_device *ohci_dev = usb_dev->ohci_dev;
	struct platform_device *ehci_dev = usb_dev->ehci_dev;

	if (ohci_dev)
		platform_device_unregister(ohci_dev);
	if (ehci_dev)
		platform_device_unregister(ehci_dev);

	bcma_core_disable(dev, 0);
}

static void bcma_hcd_shutdown(struct bcma_device *dev)
{
	bcma_hci_platform_power_gpio(dev, false);
	bcma_core_disable(dev, 0);
}

#ifdef CONFIG_PM

static int bcma_hcd_suspend(struct bcma_device *dev)
{
	bcma_hci_platform_power_gpio(dev, false);
	bcma_core_disable(dev, 0);

	return 0;
}

static int bcma_hcd_resume(struct bcma_device *dev)
{
	bcma_hci_platform_power_gpio(dev, true);
	bcma_core_enable(dev, 0);

	return 0;
}

#else /* !CONFIG_PM */
#define bcma_hcd_suspend	NULL
#define bcma_hcd_resume	NULL
#endif /* CONFIG_PM */

static const struct bcma_device_id bcma_hcd_table[] = {
	BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_USB20_HOST, BCMA_ANY_REV, BCMA_ANY_CLASS),
	BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_NS_USB20, BCMA_ANY_REV, BCMA_ANY_CLASS),
	BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_NS_USB30, BCMA_ANY_REV, BCMA_ANY_CLASS),
	{},
};
MODULE_DEVICE_TABLE(bcma, bcma_hcd_table);

static struct bcma_driver bcma_hcd_driver = {
	.name		= KBUILD_MODNAME,
	.id_table	= bcma_hcd_table,
	.probe		= bcma_hcd_probe,
	.remove		= bcma_hcd_remove,
	.shutdown	= bcma_hcd_shutdown,
	.suspend	= bcma_hcd_suspend,
	.resume		= bcma_hcd_resume,
};

static int __init bcma_hcd_init(void)
{
	return bcma_driver_register(&bcma_hcd_driver);
}
module_init(bcma_hcd_init);

static void __exit bcma_hcd_exit(void)
{
	bcma_driver_unregister(&bcma_hcd_driver);
}
module_exit(bcma_hcd_exit);
Commit	Line	Data
5fd54ace	1	// SPDX-License-Identifier: GPL-2.0
62e11d1b HM	2	/*
	3	* Broadcom specific Advanced Microcontroller Bus
	4	* Broadcom USB-core driver (BCMA bus glue)
	5	*
10bc04b7 HM	6	* Copyright 2011-2015 Hauke Mehrtens <hauke@hauke-m.de>
10bc04b7 HM	7	* Copyright 2015 Felix Fietkau <nbd@openwrt.org>
62e11d1b HM	8	*
	9	* Based on ssb-ohci driver
	10	* Copyright 2007 Michael Buesch <m@bues.ch>
	11	*
	12	* Derived from the OHCI-PCI driver
	13	* Copyright 1999 Roman Weissgaerber
	14	* Copyright 2000-2002 David Brownell
	15	* Copyright 1999 Linus Torvalds
	16	* Copyright 1999 Gregory P. Smith
	17	*
	18	* Derived from the USBcore related parts of Broadcom-SB
	19	* Copyright 2005-2011 Broadcom Corporation
	20	*
	21	* Licensed under the GNU/GPL. See COPYING for details.
	22	*/
	23	#include <linux/bcma/bcma.h>
	24	#include <linux/delay.h>
9faae5a3	25	#include <linux/gpio/consumer.h>
62e11d1b HM	26	#include <linux/platform_device.h>
62e11d1b HM	27	#include <linux/module.h>
6ba0d809	28	#include <linux/slab.h>
eb4861c3 HM	29	#include <linux/of.h>
eb4861c3 HM	30	#include <linux/of_gpio.h>
3cc7e7b7	31	#include <linux/of_platform.h>
62e11d1b HM	32	#include <linux/usb/ehci_pdriver.h>
	33	#include <linux/usb/ohci_pdriver.h>
	34
	35	MODULE_AUTHOR("Hauke Mehrtens");
	36	MODULE_DESCRIPTION("Common USB driver for BCMA Bus");
	37	MODULE_LICENSE("GPL");
	38
d6b76c4d RM	39	/* See BCMA_CLKCTLST_EXTRESREQ and BCMA_CLKCTLST_EXTRESST */
	40	#define USB_BCMA_CLKCTLST_USB_CLK_REQ 0x00000100
	41
62e11d1b	42	struct bcma_hcd_device {
adbff3a4	43	struct bcma_device *core;
62e11d1b HM	44	struct platform_device *ehci_dev;
62e11d1b HM	45	struct platform_device *ohci_dev;
9faae5a3	46	struct gpio_desc *gpio_desc;
62e11d1b HM	47	};
	48
	49	/* Wait for bitmask in a register to get set or cleared.
	50	* timeout is in units of ten-microseconds.
	51	*/
	52	static int bcma_wait_bits(struct bcma_device *dev, u16 reg, u32 bitmask,
	53	int timeout)
	54	{
	55	int i;
	56	u32 val;
	57
	58	for (i = 0; i < timeout; i++) {
	59	val = bcma_read32(dev, reg);
	60	if ((val & bitmask) == bitmask)
	61	return 0;
	62	udelay(10);
	63	}
	64
	65	return -ETIMEDOUT;
	66	}
	67
41ac7b3a	68	static void bcma_hcd_4716wa(struct bcma_device *dev)
62e11d1b HM	69	{
	70	#ifdef CONFIG_BCMA_DRIVER_MIPS
	71	/* Work around for 4716 failures. */
	72	if (dev->bus->chipinfo.id == 0x4716) {
	73	u32 tmp;
	74
	75	tmp = bcma_cpu_clock(&dev->bus->drv_mips);
	76	if (tmp >= 480000000)
	77	tmp = 0x1846b; /* set CDR to 0x11(fast) */
	78	else if (tmp == 453000000)
	79	tmp = 0x1046b; /* set CDR to 0x10(slow) */
	80	else
	81	tmp = 0;
	82
	83	/* Change Shim mdio control reg to fix host not acking at
	84	* high frequencies
	85	*/
	86	if (tmp) {
	87	bcma_write32(dev, 0x524, 0x1); /* write sel to enable */
	88	udelay(500);
	89
	90	bcma_write32(dev, 0x524, tmp);
	91	udelay(500);
	92	bcma_write32(dev, 0x524, 0x4ab);
	93	udelay(500);
	94	bcma_read32(dev, 0x528);
	95	bcma_write32(dev, 0x528, 0x80000000);
	96	}
	97	}
	98	#endif /* CONFIG_BCMA_DRIVER_MIPS */
	99	}
	100
	101	/* based on arch/mips/brcm-boards/bcm947xx/pcibios.c */
10bc04b7	102	static void bcma_hcd_init_chip_mips(struct bcma_device *dev)
62e11d1b HM	103	{
	104	u32 tmp;
	105
	106	/*
	107	* USB 2.0 special considerations:
	108	*
	109	* 1. Since the core supports both OHCI and EHCI functions, it must
	110	* only be reset once.
	111	*
	112	* 2. In addition to the standard SI reset sequence, the Host Control
	113	* Register must be programmed to bring the USB core and various
	114	* phy components out of reset.
	115	*/
	116	if (!bcma_core_is_enabled(dev)) {
	117	bcma_core_enable(dev, 0);
	118	mdelay(10);
	119	if (dev->id.rev >= 5) {
	120	/* Enable Misc PLL */
	121	tmp = bcma_read32(dev, 0x1e0);
	122	tmp \|= 0x100;
	123	bcma_write32(dev, 0x1e0, tmp);
	124	if (bcma_wait_bits(dev, 0x1e0, 1 << 24, 100))
	125	printk(KERN_EMERG "Failed to enable misc PPL!\n");
	126
	127	/* Take out of resets */
	128	bcma_write32(dev, 0x200, 0x4ff);
	129	udelay(25);
	130	bcma_write32(dev, 0x200, 0x6ff);
	131	udelay(25);
	132
	133	/* Make sure digital and AFE are locked in USB PHY */
	134	bcma_write32(dev, 0x524, 0x6b);
	135	udelay(50);
	136	tmp = bcma_read32(dev, 0x524);
	137	udelay(50);
	138	bcma_write32(dev, 0x524, 0xab);
	139	udelay(50);
	140	tmp = bcma_read32(dev, 0x524);
	141	udelay(50);
	142	bcma_write32(dev, 0x524, 0x2b);
	143	udelay(50);
	144	tmp = bcma_read32(dev, 0x524);
	145	udelay(50);
	146	bcma_write32(dev, 0x524, 0x10ab);
	147	udelay(50);
	148	tmp = bcma_read32(dev, 0x524);
	149
	150	if (bcma_wait_bits(dev, 0x528, 0xc000, 10000)) {
	151	tmp = bcma_read32(dev, 0x528);
	152	printk(KERN_EMERG
	153	"USB20H mdio_rddata 0x%08x\n", tmp);
	154	}
	155	bcma_write32(dev, 0x528, 0x80000000);
	156	tmp = bcma_read32(dev, 0x314);
	157	udelay(265);
	158	bcma_write32(dev, 0x200, 0x7ff);
	159	udelay(10);
	160
	161	/* Take USB and HSIC out of non-driving modes */
	162	bcma_write32(dev, 0x510, 0);
	163	} else {
	164	bcma_write32(dev, 0x200, 0x7ff);
	165
	166	udelay(1);
167	}
168
169	bcma_hcd_4716wa(dev);
170	}
171	}
172
d6b76c4d RM	173	/**
	174	* bcma_hcd_usb20_old_arm_init - Initialize old USB 2.0 controller on ARM
	175	*
	176	* Old USB 2.0 core is identified as BCMA_CORE_USB20_HOST and was introduced
	177	* long before Northstar devices. It seems some cheaper chipsets like BCM53573
	178	* still use it.
	179	* Initialization of this old core differs between MIPS and ARM.
	180	*/
	181	static int bcma_hcd_usb20_old_arm_init(struct bcma_hcd_device *usb_dev)
	182	{
	183	struct bcma_device *core = usb_dev->core;
	184	struct device *dev = &core->dev;
	185	struct bcma_device *pmu_core;
	186
	187	usleep_range(10000, 20000);
	188	if (core->id.rev < 5)
	189	return 0;
	190
	191	pmu_core = bcma_find_core(core->bus, BCMA_CORE_PMU);
	192	if (!pmu_core) {
	193	dev_err(dev, "Could not find PMU core\n");
	194	return -ENOENT;
	195	}
	196
	197	/* Take USB core out of reset */
	198	bcma_awrite32(core, BCMA_IOCTL, BCMA_IOCTL_CLK \| BCMA_IOCTL_FGC);
	199	usleep_range(100, 200);
	200	bcma_awrite32(core, BCMA_RESET_CTL, BCMA_RESET_CTL_RESET);
	201	usleep_range(100, 200);
	202	bcma_awrite32(core, BCMA_RESET_CTL, 0);
	203	usleep_range(100, 200);
	204	bcma_awrite32(core, BCMA_IOCTL, BCMA_IOCTL_CLK);
	205	usleep_range(100, 200);
	206
	207	/* Enable Misc PLL */
	208	bcma_write32(core, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT \|
	209	BCMA_CLKCTLST_HQCLKREQ \|
	210	USB_BCMA_CLKCTLST_USB_CLK_REQ);
	211	usleep_range(100, 200);
	212
	213	bcma_write32(core, 0x510, 0xc7f85000);
	214	bcma_write32(core, 0x510, 0xc7f85003);
	215	usleep_range(300, 600);
	216
	217	/* Program USB PHY PLL parameters */
	218	bcma_write32(pmu_core, BCMA_CC_PMU_PLLCTL_ADDR, 0x6);
	219	bcma_write32(pmu_core, BCMA_CC_PMU_PLLCTL_DATA, 0x005360c1);
	220	usleep_range(100, 200);
	221	bcma_write32(pmu_core, BCMA_CC_PMU_PLLCTL_ADDR, 0x7);
	222	bcma_write32(pmu_core, BCMA_CC_PMU_PLLCTL_DATA, 0x0);
	223	usleep_range(100, 200);
	224	bcma_set32(pmu_core, BCMA_CC_PMU_CTL, BCMA_CC_PMU_CTL_PLL_UPD);
	225	usleep_range(100, 200);
	226
	227	bcma_write32(core, 0x510, 0x7f8d007);
	228	udelay(1000);
	229
	230	/* Take controller out of reset */
	231	bcma_write32(core, 0x200, 0x4ff);
	232	usleep_range(25, 50);
	233	bcma_write32(core, 0x200, 0x6ff);
	234	usleep_range(25, 50);
	235	bcma_write32(core, 0x200, 0x7ff);
	236	usleep_range(25, 50);
237
238	of_platform_default_populate(dev->of_node, NULL, dev);
239
240	return 0;
241	}
242
e8624859	243	static void bcma_hcd_usb20_ns_init_hc(struct bcma_device *dev)
10bc04b7 HM	244	{
	245	u32 val;
	246
10bc04b7 HM	247	/* Set packet buffer OUT threshold */
	248	val = bcma_read32(dev, 0x94);
	249	val &= 0xffff;
	250	val \|= 0x80 << 16;
	251	bcma_write32(dev, 0x94, val);
	252
	253	/* Enable break memory transfer */
	254	val = bcma_read32(dev, 0x9c);
	255	val \|= 1;
	256	bcma_write32(dev, 0x9c, val);
e8624859 RM	257
	258	/*
	259	* Broadcom initializes PHY and then waits to ensure HC is ready to be
	260	* configured. In our case the order is reversed. We just initialized
	261	* controller and we let HCD initialize PHY, so let's wait (sleep) now.
	262	*/
	263	usleep_range(1000, 2000);
10bc04b7 HM	264	}
10bc04b7 HM	265
e8624859 RM	266	/**
	267	* bcma_hcd_usb20_ns_init - Initialize Northstar USB 2.0 controller
	268	*/
	269	static int bcma_hcd_usb20_ns_init(struct bcma_hcd_device *bcma_hcd)
10bc04b7	270	{
e8624859 RM	271	struct bcma_device *core = bcma_hcd->core;
	272	struct bcma_chipinfo *ci = &core->bus->chipinfo;
	273	struct device *dev = &core->dev;
10bc04b7	274
e8624859	275	bcma_core_enable(core, 0);
10bc04b7	276
e8624859 RM	277	if (ci->id == BCMA_CHIP_ID_BCM4707 \|\|
	278	ci->id == BCMA_CHIP_ID_BCM53018)
	279	bcma_hcd_usb20_ns_init_hc(core);
	280
	281	of_platform_default_populate(dev->of_node, NULL, dev);
	282
	283	return 0;
10bc04b7 HM	284	}
10bc04b7 HM	285
eb4861c3 HM	286	static void bcma_hci_platform_power_gpio(struct bcma_device *dev, bool val)
eb4861c3 HM	287	{
9faae5a3	288	struct bcma_hcd_device *usb_dev = bcma_get_drvdata(dev);
eb4861c3	289
9faae5a3	290	if (IS_ERR_OR_NULL(usb_dev->gpio_desc))
eb4861c3 HM	291	return;
eb4861c3 HM	292
9faae5a3	293	gpiod_set_value(usb_dev->gpio_desc, val);
eb4861c3 HM	294	}
eb4861c3 HM	295
62e11d1b HM	296	static const struct usb_ehci_pdata ehci_pdata = {
	297	};
	298
	299	static const struct usb_ohci_pdata ohci_pdata = {
	300	};
	301
352d9e2e RM	302	static struct platform_device bcma_hcd_create_pdev(struct bcma_device dev,
	303	const char *name, u32 addr,
	304	const void *data,
	305	size_t size)
62e11d1b HM	306	{
	307	struct platform_device *hci_dev;
	308	struct resource hci_res[2];
ab2de579	309	int ret;
62e11d1b HM	310
	311	memset(hci_res, 0, sizeof(hci_res));
	312
	313	hci_res[0].start = addr;
	314	hci_res[0].end = hci_res[0].start + 0x1000 - 1;
	315	hci_res[0].flags = IORESOURCE_MEM;
	316
	317	hci_res[1].start = dev->irq;
	318	hci_res[1].flags = IORESOURCE_IRQ;
	319
352d9e2e	320	hci_dev = platform_device_alloc(name, 0);
62e11d1b	321	if (!hci_dev)
ab2de579	322	return ERR_PTR(-ENOMEM);
62e11d1b HM	323
	324	hci_dev->dev.parent = &dev->dev;
	325	hci_dev->dev.dma_mask = &hci_dev->dev.coherent_dma_mask;
	326
	327	ret = platform_device_add_resources(hci_dev, hci_res,
	328	ARRAY_SIZE(hci_res));
	329	if (ret)
	330	goto err_alloc;
352d9e2e RM	331	if (data)
352d9e2e RM	332	ret = platform_device_add_data(hci_dev, data, size);
62e11d1b HM	333	if (ret)
	334	goto err_alloc;
	335	ret = platform_device_add(hci_dev);
	336	if (ret)
	337	goto err_alloc;
	338
	339	return hci_dev;
	340
	341	err_alloc:
	342	platform_device_put(hci_dev);
	343	return ERR_PTR(ret);
	344	}
	345
adbff3a4	346	static int bcma_hcd_usb20_init(struct bcma_hcd_device *usb_dev)
62e11d1b	347	{
adbff3a4 RM	348	struct bcma_device *dev = usb_dev->core;
adbff3a4 RM	349	struct bcma_chipinfo *chipinfo = &dev->bus->chipinfo;
62e11d1b	350	u32 ohci_addr;
adbff3a4	351	int err;
62e11d1b	352
d288059e	353	if (dma_set_mask_and_coherent(dev->dma_dev, DMA_BIT_MASK(32)))
62e11d1b HM	354	return -EOPNOTSUPP;
62e11d1b HM	355
e8624859	356	bcma_hcd_init_chip_mips(dev);
62e11d1b HM	357
62e11d1b HM	358	/* In AI chips EHCI is addrspace 0, OHCI is 1 */
23a2f39c	359	ohci_addr = dev->addr_s[0];
98e13e05 HM	360	if ((chipinfo->id == BCMA_CHIP_ID_BCM5357 \|\|
98e13e05 HM	361	chipinfo->id == BCMA_CHIP_ID_BCM4749)
62e11d1b HM	362	&& chipinfo->rev == 0)
	363	ohci_addr = 0x18009000;
	364
352d9e2e RM	365	usb_dev->ohci_dev = bcma_hcd_create_pdev(dev, "ohci-platform",
	366	ohci_addr, &ohci_pdata,
	367	sizeof(ohci_pdata));
c27da2b2 HM	368	if (IS_ERR(usb_dev->ohci_dev))
c27da2b2 HM	369	return PTR_ERR(usb_dev->ohci_dev);
62e11d1b	370
352d9e2e RM	371	usb_dev->ehci_dev = bcma_hcd_create_pdev(dev, "ehci-platform",
	372	dev->addr, &ehci_pdata,
	373	sizeof(ehci_pdata));
62e11d1b HM	374	if (IS_ERR(usb_dev->ehci_dev)) {
	375	err = PTR_ERR(usb_dev->ehci_dev);
	376	goto err_unregister_ohci_dev;
	377	}
	378
62e11d1b HM	379	return 0;
	380
	381	err_unregister_ohci_dev:
	382	platform_device_unregister(usb_dev->ohci_dev);
62e11d1b HM	383	return err;
	384	}
	385
3cc7e7b7 RM	386	static int bcma_hcd_usb30_init(struct bcma_hcd_device *bcma_hcd)
	387	{
	388	struct bcma_device *core = bcma_hcd->core;
	389	struct device *dev = &core->dev;
	390
	391	bcma_core_enable(core, 0);
	392
	393	of_platform_default_populate(dev->of_node, NULL, dev);
	394
	395	return 0;
	396	}
	397
adbff3a4 RM	398	static int bcma_hcd_probe(struct bcma_device *core)
	399	{
	400	int err;
	401	struct bcma_hcd_device *usb_dev;
	402
	403	/* TODO: Probably need checks here; is the core connected? */
	404
	405	usb_dev = devm_kzalloc(&core->dev, sizeof(struct bcma_hcd_device),
	406	GFP_KERNEL);
	407	if (!usb_dev)
	408	return -ENOMEM;
	409	usb_dev->core = core;
	410
	411	if (core->dev.of_node)
1507372b RM	412	usb_dev->gpio_desc = devm_gpiod_get(&core->dev, "vcc",
1507372b RM	413	GPIOD_OUT_HIGH);
adbff3a4 RM	414
	415	switch (core->id.id) {
	416	case BCMA_CORE_USB20_HOST:
d6b76c4d RM	417	if (IS_ENABLED(CONFIG_ARM))
	418	err = bcma_hcd_usb20_old_arm_init(usb_dev);
	419	else if (IS_ENABLED(CONFIG_MIPS))
	420	err = bcma_hcd_usb20_init(usb_dev);
	421	else
	422	err = -ENOTSUPP;
	423	break;
adbff3a4	424	case BCMA_CORE_NS_USB20:
e8624859	425	err = bcma_hcd_usb20_ns_init(usb_dev);
adbff3a4	426	break;
3cc7e7b7 RM	427	case BCMA_CORE_NS_USB30:
3cc7e7b7 RM	428	err = bcma_hcd_usb30_init(usb_dev);
3cc7e7b7	429	break;
adbff3a4 RM	430	default:
	431	return -ENODEV;
	432	}
d6b76c4d RM	433	if (err)
d6b76c4d RM	434	return err;
adbff3a4 RM	435
	436	bcma_set_drvdata(core, usb_dev);
	437	return 0;
	438	}
	439
fb4e98ab	440	static void bcma_hcd_remove(struct bcma_device *dev)
62e11d1b HM	441	{
	442	struct bcma_hcd_device *usb_dev = bcma_get_drvdata(dev);
	443	struct platform_device *ohci_dev = usb_dev->ohci_dev;
	444	struct platform_device *ehci_dev = usb_dev->ehci_dev;
	445
	446	if (ohci_dev)
	447	platform_device_unregister(ohci_dev);
	448	if (ehci_dev)
	449	platform_device_unregister(ehci_dev);
	450
	451	bcma_core_disable(dev, 0);
	452	}
	453
	454	static void bcma_hcd_shutdown(struct bcma_device *dev)
	455	{
eb4861c3	456	bcma_hci_platform_power_gpio(dev, false);
62e11d1b HM	457	bcma_core_disable(dev, 0);
	458	}
	459
	460	#ifdef CONFIG_PM
	461
1f6155f5	462	static int bcma_hcd_suspend(struct bcma_device *dev)
62e11d1b	463	{
eb4861c3	464	bcma_hci_platform_power_gpio(dev, false);
62e11d1b HM	465	bcma_core_disable(dev, 0);
	466
	467	return 0;
	468	}
	469
	470	static int bcma_hcd_resume(struct bcma_device *dev)
	471	{
eb4861c3	472	bcma_hci_platform_power_gpio(dev, true);
62e11d1b HM	473	bcma_core_enable(dev, 0);
	474
	475	return 0;
	476	}
	477
	478	#else /* !CONFIG_PM */
	479	#define bcma_hcd_suspend NULL
	480	#define bcma_hcd_resume NULL
	481	#endif /* CONFIG_PM */
	482
2f82686e	483	static const struct bcma_device_id bcma_hcd_table[] = {
62e11d1b	484	BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_USB20_HOST, BCMA_ANY_REV, BCMA_ANY_CLASS),
10bc04b7	485	BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_NS_USB20, BCMA_ANY_REV, BCMA_ANY_CLASS),
3cc7e7b7	486	BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_NS_USB30, BCMA_ANY_REV, BCMA_ANY_CLASS),
f7219b52	487	{},
62e11d1b HM	488	};
	489	MODULE_DEVICE_TABLE(bcma, bcma_hcd_table);
	490
	491	static struct bcma_driver bcma_hcd_driver = {
	492	.name = KBUILD_MODNAME,
	493	.id_table = bcma_hcd_table,
	494	.probe = bcma_hcd_probe,
7690417d	495	.remove = bcma_hcd_remove,
62e11d1b HM	496	.shutdown = bcma_hcd_shutdown,
	497	.suspend = bcma_hcd_suspend,
	498	.resume = bcma_hcd_resume,
	499	};
	500
	501	static int __init bcma_hcd_init(void)
	502	{
	503	return bcma_driver_register(&bcma_hcd_driver);
	504	}
	505	module_init(bcma_hcd_init);
	506
	507	static void __exit bcma_hcd_exit(void)
	508	{
	509	bcma_driver_unregister(&bcma_hcd_driver);
	510	}
	511	module_exit(bcma_hcd_exit);