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5fd54ace | 1 | // SPDX-License-Identifier: GPL-2.0+ |
80cb9aee | 2 | /* |
1af10774 | 3 | * Copyright 2005-2009 MontaVista Software, Inc. |
ca07e1c1 | 4 | * Copyright 2008,2012,2015 Freescale Semiconductor, Inc. |
80cb9aee RV |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License as published by the | |
8 | * Free Software Foundation; either version 2 of the License, or (at your | |
9 | * option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but | |
12 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
13 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
14 | * for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software Foundation, | |
18 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
19 | * | |
20 | * Ported to 834x by Randy Vinson <rvinson@mvista.com> using code provided | |
21 | * by Hunter Wu. | |
1af10774 AV |
22 | * Power Management support by Dave Liu <daveliu@freescale.com>, |
23 | * Jerry Huang <Chang-Ming.Huang@freescale.com> and | |
24 | * Anton Vorontsov <avorontsov@ru.mvista.com>. | |
80cb9aee RV |
25 | */ |
26 | ||
1af10774 | 27 | #include <linux/kernel.h> |
ca07e1c1 | 28 | #include <linux/module.h> |
1af10774 AV |
29 | #include <linux/types.h> |
30 | #include <linux/delay.h> | |
31 | #include <linux/pm.h> | |
ded017ee | 32 | #include <linux/err.h> |
ca07e1c1 RM |
33 | #include <linux/usb.h> |
34 | #include <linux/usb/ehci_def.h> | |
35 | #include <linux/usb/hcd.h> | |
36 | #include <linux/usb/otg.h> | |
80cb9aee RV |
37 | #include <linux/platform_device.h> |
38 | #include <linux/fsl_devices.h> | |
6f5429d9 | 39 | #include <linux/of_platform.h> |
80cb9aee | 40 | |
ca07e1c1 | 41 | #include "ehci.h" |
80cb9aee RV |
42 | #include "ehci-fsl.h" |
43 | ||
ca07e1c1 RM |
44 | #define DRIVER_DESC "Freescale EHCI Host controller driver" |
45 | #define DRV_NAME "ehci-fsl" | |
46 | ||
47 | static struct hc_driver __read_mostly fsl_ehci_hc_driver; | |
48 | ||
80cb9aee RV |
49 | /* configure so an HC device and id are always provided */ |
50 | /* always called with process context; sleeping is OK */ | |
51 | ||
ca07e1c1 RM |
52 | /* |
53 | * fsl_ehci_drv_probe - initialize FSL-based HCDs | |
80cb9aee RV |
54 | * @pdev: USB Host Controller being probed |
55 | * Context: !in_interrupt() | |
56 | * | |
57 | * Allocates basic resources for this USB host controller. | |
58 | * | |
59 | */ | |
ca07e1c1 | 60 | static int fsl_ehci_drv_probe(struct platform_device *pdev) |
80cb9aee RV |
61 | { |
62 | struct fsl_usb2_platform_data *pdata; | |
63 | struct usb_hcd *hcd; | |
64 | struct resource *res; | |
65 | int irq; | |
66 | int retval; | |
80cb9aee RV |
67 | |
68 | pr_debug("initializing FSL-SOC USB Controller\n"); | |
69 | ||
70 | /* Need platform data for setup */ | |
37c3a3c4 | 71 | pdata = dev_get_platdata(&pdev->dev); |
80cb9aee RV |
72 | if (!pdata) { |
73 | dev_err(&pdev->dev, | |
7071a3ce | 74 | "No platform data for %s.\n", dev_name(&pdev->dev)); |
80cb9aee RV |
75 | return -ENODEV; |
76 | } | |
77 | ||
78 | /* | |
79 | * This is a host mode driver, verify that we're supposed to be | |
80 | * in host mode. | |
81 | */ | |
82 | if (!((pdata->operating_mode == FSL_USB2_DR_HOST) || | |
ba02978a LY |
83 | (pdata->operating_mode == FSL_USB2_MPH_HOST) || |
84 | (pdata->operating_mode == FSL_USB2_DR_OTG))) { | |
80cb9aee RV |
85 | dev_err(&pdev->dev, |
86 | "Non Host Mode configured for %s. Wrong driver linked.\n", | |
7071a3ce | 87 | dev_name(&pdev->dev)); |
80cb9aee RV |
88 | return -ENODEV; |
89 | } | |
90 | ||
91 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
92 | if (!res) { | |
93 | dev_err(&pdev->dev, | |
94 | "Found HC with no IRQ. Check %s setup!\n", | |
7071a3ce | 95 | dev_name(&pdev->dev)); |
80cb9aee RV |
96 | return -ENODEV; |
97 | } | |
98 | irq = res->start; | |
99 | ||
8123e495 AB |
100 | hcd = __usb_create_hcd(&fsl_ehci_hc_driver, pdev->dev.parent, |
101 | &pdev->dev, dev_name(&pdev->dev), NULL); | |
80cb9aee RV |
102 | if (!hcd) { |
103 | retval = -ENOMEM; | |
104 | goto err1; | |
105 | } | |
106 | ||
107 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
7667fe69 JH |
108 | hcd->regs = devm_ioremap_resource(&pdev->dev, res); |
109 | if (IS_ERR(hcd->regs)) { | |
110 | retval = PTR_ERR(hcd->regs); | |
80cb9aee RV |
111 | goto err2; |
112 | } | |
80cb9aee | 113 | |
ce98f548 VB |
114 | hcd->rsrc_start = res->start; |
115 | hcd->rsrc_len = resource_size(res); | |
116 | ||
230f7ede | 117 | pdata->regs = hcd->regs; |
80cb9aee | 118 | |
83722bc9 AG |
119 | if (pdata->power_budget) |
120 | hcd->power_budget = pdata->power_budget; | |
121 | ||
230f7ede AG |
122 | /* |
123 | * do platform specific init: check the clock, grab/config pins, etc. | |
124 | */ | |
125 | if (pdata->init && pdata->init(pdev)) { | |
126 | retval = -ENODEV; | |
7667fe69 | 127 | goto err2; |
230f7ede AG |
128 | } |
129 | ||
230f7ede | 130 | /* Enable USB controller, 83xx or 8536 */ |
ad1260e9 | 131 | if (pdata->have_sysif_regs && pdata->controller_ver < FSL_USB_VER_1_6) |
4e02bea8 NB |
132 | clrsetbits_be32(hcd->regs + FSL_SOC_USB_CTRL, |
133 | CONTROL_REGISTER_W1C_MASK, 0x4); | |
230f7ede | 134 | |
523f1dec NB |
135 | /* |
136 | * Enable UTMI phy and program PTS field in UTMI mode before asserting | |
137 | * controller reset for USB Controller version 2.5 | |
138 | */ | |
139 | if (pdata->has_fsl_erratum_a007792) { | |
4e02bea8 NB |
140 | clrsetbits_be32(hcd->regs + FSL_SOC_USB_CTRL, |
141 | CONTROL_REGISTER_W1C_MASK, CTRL_UTMI_PHY_EN); | |
523f1dec NB |
142 | writel(PORT_PTS_UTMI, hcd->regs + FSL_SOC_USB_PORTSC1); |
143 | } | |
144 | ||
230f7ede | 145 | /* Don't need to set host mode here. It will be done by tdi_reset() */ |
80cb9aee | 146 | |
b5dd18d8 | 147 | retval = usb_add_hcd(hcd, irq, IRQF_SHARED); |
80cb9aee | 148 | if (retval != 0) |
7667fe69 | 149 | goto err2; |
3c9740a1 | 150 | device_wakeup_enable(hcd->self.controller); |
83722bc9 AG |
151 | |
152 | #ifdef CONFIG_USB_OTG | |
153 | if (pdata->operating_mode == FSL_USB2_DR_OTG) { | |
154 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | |
155 | ||
3d46e73d | 156 | hcd->usb_phy = usb_get_phy(USB_PHY_TYPE_USB2); |
c2e935a7 | 157 | dev_dbg(&pdev->dev, "hcd=0x%p ehci=0x%p, phy=0x%p\n", |
3d46e73d | 158 | hcd, ehci, hcd->usb_phy); |
83722bc9 | 159 | |
3d46e73d AT |
160 | if (!IS_ERR_OR_NULL(hcd->usb_phy)) { |
161 | retval = otg_set_host(hcd->usb_phy->otg, | |
83722bc9 AG |
162 | &ehci_to_hcd(ehci)->self); |
163 | if (retval) { | |
3d46e73d | 164 | usb_put_phy(hcd->usb_phy); |
7667fe69 | 165 | goto err2; |
83722bc9 AG |
166 | } |
167 | } else { | |
c2e935a7 | 168 | dev_err(&pdev->dev, "can't find phy\n"); |
83722bc9 | 169 | retval = -ENODEV; |
7667fe69 | 170 | goto err2; |
83722bc9 AG |
171 | } |
172 | } | |
173 | #endif | |
80cb9aee RV |
174 | return retval; |
175 | ||
80cb9aee RV |
176 | err2: |
177 | usb_put_hcd(hcd); | |
178 | err1: | |
7071a3ce | 179 | dev_err(&pdev->dev, "init %s fail, %d\n", dev_name(&pdev->dev), retval); |
230f7ede AG |
180 | if (pdata->exit) |
181 | pdata->exit(pdev); | |
80cb9aee RV |
182 | return retval; |
183 | } | |
184 | ||
3735ba8d | 185 | static int ehci_fsl_setup_phy(struct usb_hcd *hcd, |
230f7ede AG |
186 | enum fsl_usb2_phy_modes phy_mode, |
187 | unsigned int port_offset) | |
80cb9aee | 188 | { |
3735ba8d | 189 | u32 portsc; |
58c559e6 | 190 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); |
28c56ea1 | 191 | void __iomem *non_ehci = hcd->regs; |
58c559e6 | 192 | struct device *dev = hcd->self.controller; |
d4f09e28 | 193 | struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev); |
f941f692 | 194 | |
58c559e6 RM |
195 | if (pdata->controller_ver < 0) { |
196 | dev_warn(hcd->self.controller, "Could not get controller version\n"); | |
d479c911 | 197 | return -ENODEV; |
58c559e6 | 198 | } |
230f7ede AG |
199 | |
200 | portsc = ehci_readl(ehci, &ehci->regs->port_status[port_offset]); | |
201 | portsc &= ~(PORT_PTS_MSK | PORT_PTS_PTW); | |
202 | ||
80cb9aee RV |
203 | switch (phy_mode) { |
204 | case FSL_USB2_PHY_ULPI: | |
f66dea70 | 205 | if (pdata->have_sysif_regs && pdata->controller_ver) { |
58c559e6 | 206 | /* controller version 1.6 or above */ |
4e02bea8 NB |
207 | clrbits32(non_ehci + FSL_SOC_USB_CTRL, |
208 | CONTROL_REGISTER_W1C_MASK | UTMI_PHY_EN); | |
209 | clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL, | |
210 | CONTROL_REGISTER_W1C_MASK, | |
211 | ULPI_PHY_CLK_SEL | USB_CTRL_USB_EN); | |
58c559e6 | 212 | } |
80cb9aee RV |
213 | portsc |= PORT_PTS_ULPI; |
214 | break; | |
215 | case FSL_USB2_PHY_SERIAL: | |
216 | portsc |= PORT_PTS_SERIAL; | |
217 | break; | |
218 | case FSL_USB2_PHY_UTMI_WIDE: | |
219 | portsc |= PORT_PTS_PTW; | |
220 | /* fall through */ | |
221 | case FSL_USB2_PHY_UTMI: | |
6009d95e | 222 | case FSL_USB2_PHY_UTMI_DUAL: |
f66dea70 | 223 | if (pdata->have_sysif_regs && pdata->controller_ver) { |
58c559e6 | 224 | /* controller version 1.6 or above */ |
4e02bea8 NB |
225 | clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL, |
226 | CONTROL_REGISTER_W1C_MASK, UTMI_PHY_EN); | |
58c559e6 RM |
227 | mdelay(FSL_UTMI_PHY_DLY); /* Delay for UTMI PHY CLK to |
228 | become stable - 10ms*/ | |
229 | } | |
28c56ea1 | 230 | /* enable UTMI PHY */ |
f941f692 | 231 | if (pdata->have_sysif_regs) |
4e02bea8 NB |
232 | clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL, |
233 | CONTROL_REGISTER_W1C_MASK, | |
234 | CTRL_UTMI_PHY_EN); | |
80cb9aee RV |
235 | portsc |= PORT_PTS_UTMI; |
236 | break; | |
237 | case FSL_USB2_PHY_NONE: | |
238 | break; | |
239 | } | |
3735ba8d | 240 | |
f4fdfaa2 NB |
241 | /* |
242 | * check PHY_CLK_VALID to determine phy clock presence before writing | |
243 | * to portsc | |
244 | */ | |
245 | if (pdata->check_phy_clk_valid) { | |
6f5429d9 SD |
246 | if (!(ioread32be(non_ehci + FSL_SOC_USB_CTRL) & |
247 | PHY_CLK_VALID)) { | |
f4fdfaa2 NB |
248 | dev_warn(hcd->self.controller, |
249 | "USB PHY clock invalid\n"); | |
3735ba8d SL |
250 | return -EINVAL; |
251 | } | |
252 | } | |
253 | ||
083522d7 | 254 | ehci_writel(ehci, portsc, &ehci->regs->port_status[port_offset]); |
3735ba8d | 255 | |
f66dea70 | 256 | if (phy_mode != FSL_USB2_PHY_ULPI && pdata->have_sysif_regs) |
4e02bea8 NB |
257 | clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL, |
258 | CONTROL_REGISTER_W1C_MASK, USB_CTRL_USB_EN); | |
3735ba8d SL |
259 | |
260 | return 0; | |
80cb9aee RV |
261 | } |
262 | ||
3735ba8d | 263 | static int ehci_fsl_usb_setup(struct ehci_hcd *ehci) |
80cb9aee | 264 | { |
230f7ede | 265 | struct usb_hcd *hcd = ehci_to_hcd(ehci); |
80cb9aee RV |
266 | struct fsl_usb2_platform_data *pdata; |
267 | void __iomem *non_ehci = hcd->regs; | |
268 | ||
d4f09e28 | 269 | pdata = dev_get_platdata(hcd->self.controller); |
230f7ede | 270 | |
230f7ede | 271 | if (pdata->have_sysif_regs) { |
4c954326 PJ |
272 | /* |
273 | * Turn on cache snooping hardware, since some PowerPC platforms | |
274 | * wholly rely on hardware to deal with cache coherent | |
275 | */ | |
40acc095 | 276 | |
4c954326 PJ |
277 | /* Setup Snooping for all the 4GB space */ |
278 | /* SNOOP1 starts from 0x0, size 2G */ | |
6f5429d9 SD |
279 | iowrite32be(0x0 | SNOOP_SIZE_2GB, |
280 | non_ehci + FSL_SOC_USB_SNOOP1); | |
4c954326 | 281 | /* SNOOP2 starts from 0x80000000, size 2G */ |
6f5429d9 SD |
282 | iowrite32be(0x80000000 | SNOOP_SIZE_2GB, |
283 | non_ehci + FSL_SOC_USB_SNOOP2); | |
4c954326 | 284 | } |
40acc095 | 285 | |
f8786a91 NB |
286 | /* Deal with USB erratum A-005275 */ |
287 | if (pdata->has_fsl_erratum_a005275 == 1) | |
288 | ehci->has_fsl_hs_errata = 1; | |
289 | ||
9d4b8270 CH |
290 | if (pdata->has_fsl_erratum_a005697 == 1) |
291 | ehci->has_fsl_susp_errata = 1; | |
292 | ||
ba02978a LY |
293 | if ((pdata->operating_mode == FSL_USB2_DR_HOST) || |
294 | (pdata->operating_mode == FSL_USB2_DR_OTG)) | |
3735ba8d SL |
295 | if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 0)) |
296 | return -EINVAL; | |
80cb9aee RV |
297 | |
298 | if (pdata->operating_mode == FSL_USB2_MPH_HOST) { | |
8cd42e97 KG |
299 | unsigned int chip, rev, svr; |
300 | ||
301 | svr = mfspr(SPRN_SVR); | |
302 | chip = svr >> 16; | |
303 | rev = (svr >> 4) & 0xf; | |
304 | ||
305 | /* Deal with USB Erratum #14 on MPC834x Rev 1.0 & 1.1 chips */ | |
306 | if ((rev == 1) && (chip >= 0x8050) && (chip <= 0x8055)) | |
307 | ehci->has_fsl_port_bug = 1; | |
308 | ||
80cb9aee | 309 | if (pdata->port_enables & FSL_USB2_PORT0_ENABLED) |
3735ba8d SL |
310 | if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 0)) |
311 | return -EINVAL; | |
312 | ||
80cb9aee | 313 | if (pdata->port_enables & FSL_USB2_PORT1_ENABLED) |
3735ba8d SL |
314 | if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 1)) |
315 | return -EINVAL; | |
80cb9aee RV |
316 | } |
317 | ||
230f7ede | 318 | if (pdata->have_sysif_regs) { |
08d7660d | 319 | #ifdef CONFIG_FSL_SOC_BOOKE |
6f5429d9 SD |
320 | iowrite32be(0x00000008, non_ehci + FSL_SOC_USB_PRICTRL); |
321 | iowrite32be(0x00000080, non_ehci + FSL_SOC_USB_AGECNTTHRSH); | |
4f534258 | 322 | #else |
6f5429d9 SD |
323 | iowrite32be(0x0000000c, non_ehci + FSL_SOC_USB_PRICTRL); |
324 | iowrite32be(0x00000040, non_ehci + FSL_SOC_USB_AGECNTTHRSH); | |
4f534258 | 325 | #endif |
6f5429d9 | 326 | iowrite32be(0x00000001, non_ehci + FSL_SOC_USB_SICTRL); |
230f7ede | 327 | } |
3735ba8d SL |
328 | |
329 | return 0; | |
80cb9aee RV |
330 | } |
331 | ||
332 | /* called after powerup, by probe or system-pm "wakeup" */ | |
333 | static int ehci_fsl_reinit(struct ehci_hcd *ehci) | |
334 | { | |
3735ba8d SL |
335 | if (ehci_fsl_usb_setup(ehci)) |
336 | return -EINVAL; | |
80cb9aee RV |
337 | |
338 | return 0; | |
339 | } | |
340 | ||
341 | /* called during probe() after chip reset completes */ | |
342 | static int ehci_fsl_setup(struct usb_hcd *hcd) | |
343 | { | |
344 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | |
345 | int retval; | |
230f7ede | 346 | struct fsl_usb2_platform_data *pdata; |
761bbcb7 | 347 | struct device *dev; |
230f7ede | 348 | |
761bbcb7 | 349 | dev = hcd->self.controller; |
d4f09e28 | 350 | pdata = dev_get_platdata(hcd->self.controller); |
230f7ede AG |
351 | ehci->big_endian_desc = pdata->big_endian_desc; |
352 | ehci->big_endian_mmio = pdata->big_endian_mmio; | |
80cb9aee RV |
353 | |
354 | /* EHCI registers start at offset 0x100 */ | |
355 | ehci->caps = hcd->regs + 0x100; | |
80cb9aee | 356 | |
e6604a7f CE |
357 | #ifdef CONFIG_PPC_83xx |
358 | /* | |
359 | * Deal with MPC834X that need port power to be cycled after the power | |
360 | * fault condition is removed. Otherwise the state machine does not | |
361 | * reflect PORTSC[CSC] correctly. | |
362 | */ | |
363 | ehci->need_oc_pp_cycle = 1; | |
364 | #endif | |
365 | ||
65fd4272 MC |
366 | hcd->has_tt = 1; |
367 | ||
1a49e2ac | 368 | retval = ehci_setup(hcd); |
80cb9aee RV |
369 | if (retval) |
370 | return retval; | |
371 | ||
761bbcb7 AG |
372 | if (of_device_is_compatible(dev->parent->of_node, |
373 | "fsl,mpc5121-usb2-dr")) { | |
374 | /* | |
375 | * set SBUSCFG:AHBBRST so that control msgs don't | |
376 | * fail when doing heavy PATA writes. | |
377 | */ | |
378 | ehci_writel(ehci, SBUSCFG_INCR8, | |
379 | hcd->regs + FSL_SOC_USB_SBUSCFG); | |
380 | } | |
381 | ||
80cb9aee RV |
382 | retval = ehci_fsl_reinit(ehci); |
383 | return retval; | |
384 | } | |
385 | ||
1af10774 AV |
386 | struct ehci_fsl { |
387 | struct ehci_hcd ehci; | |
388 | ||
389 | #ifdef CONFIG_PM | |
390 | /* Saved USB PHY settings, need to restore after deep sleep. */ | |
391 | u32 usb_ctrl; | |
392 | #endif | |
393 | }; | |
394 | ||
395 | #ifdef CONFIG_PM | |
396 | ||
13b7ee2a AG |
397 | #ifdef CONFIG_PPC_MPC512x |
398 | static int ehci_fsl_mpc512x_drv_suspend(struct device *dev) | |
399 | { | |
400 | struct usb_hcd *hcd = dev_get_drvdata(dev); | |
401 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | |
d4f09e28 | 402 | struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev); |
13b7ee2a AG |
403 | u32 tmp; |
404 | ||
1c20163d | 405 | #ifdef CONFIG_DYNAMIC_DEBUG |
13b7ee2a AG |
406 | u32 mode = ehci_readl(ehci, hcd->regs + FSL_SOC_USB_USBMODE); |
407 | mode &= USBMODE_CM_MASK; | |
408 | tmp = ehci_readl(ehci, hcd->regs + 0x140); /* usbcmd */ | |
409 | ||
410 | dev_dbg(dev, "suspend=%d already_suspended=%d " | |
411 | "mode=%d usbcmd %08x\n", pdata->suspended, | |
412 | pdata->already_suspended, mode, tmp); | |
413 | #endif | |
414 | ||
415 | /* | |
416 | * If the controller is already suspended, then this must be a | |
417 | * PM suspend. Remember this fact, so that we will leave the | |
418 | * controller suspended at PM resume time. | |
419 | */ | |
420 | if (pdata->suspended) { | |
421 | dev_dbg(dev, "already suspended, leaving early\n"); | |
422 | pdata->already_suspended = 1; | |
423 | return 0; | |
424 | } | |
425 | ||
426 | dev_dbg(dev, "suspending...\n"); | |
427 | ||
e8799906 | 428 | ehci->rh_state = EHCI_RH_SUSPENDED; |
13b7ee2a AG |
429 | dev->power.power_state = PMSG_SUSPEND; |
430 | ||
431 | /* ignore non-host interrupts */ | |
432 | clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); | |
433 | ||
434 | /* stop the controller */ | |
435 | tmp = ehci_readl(ehci, &ehci->regs->command); | |
436 | tmp &= ~CMD_RUN; | |
437 | ehci_writel(ehci, tmp, &ehci->regs->command); | |
438 | ||
439 | /* save EHCI registers */ | |
440 | pdata->pm_command = ehci_readl(ehci, &ehci->regs->command); | |
441 | pdata->pm_command &= ~CMD_RUN; | |
442 | pdata->pm_status = ehci_readl(ehci, &ehci->regs->status); | |
443 | pdata->pm_intr_enable = ehci_readl(ehci, &ehci->regs->intr_enable); | |
444 | pdata->pm_frame_index = ehci_readl(ehci, &ehci->regs->frame_index); | |
445 | pdata->pm_segment = ehci_readl(ehci, &ehci->regs->segment); | |
446 | pdata->pm_frame_list = ehci_readl(ehci, &ehci->regs->frame_list); | |
447 | pdata->pm_async_next = ehci_readl(ehci, &ehci->regs->async_next); | |
448 | pdata->pm_configured_flag = | |
449 | ehci_readl(ehci, &ehci->regs->configured_flag); | |
450 | pdata->pm_portsc = ehci_readl(ehci, &ehci->regs->port_status[0]); | |
451 | pdata->pm_usbgenctrl = ehci_readl(ehci, | |
452 | hcd->regs + FSL_SOC_USB_USBGENCTRL); | |
453 | ||
454 | /* clear the W1C bits */ | |
455 | pdata->pm_portsc &= cpu_to_hc32(ehci, ~PORT_RWC_BITS); | |
456 | ||
457 | pdata->suspended = 1; | |
458 | ||
459 | /* clear PP to cut power to the port */ | |
460 | tmp = ehci_readl(ehci, &ehci->regs->port_status[0]); | |
461 | tmp &= ~PORT_POWER; | |
462 | ehci_writel(ehci, tmp, &ehci->regs->port_status[0]); | |
463 | ||
464 | return 0; | |
465 | } | |
466 | ||
467 | static int ehci_fsl_mpc512x_drv_resume(struct device *dev) | |
468 | { | |
469 | struct usb_hcd *hcd = dev_get_drvdata(dev); | |
470 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | |
d4f09e28 | 471 | struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev); |
13b7ee2a AG |
472 | u32 tmp; |
473 | ||
474 | dev_dbg(dev, "suspend=%d already_suspended=%d\n", | |
475 | pdata->suspended, pdata->already_suspended); | |
476 | ||
477 | /* | |
478 | * If the controller was already suspended at suspend time, | |
479 | * then don't resume it now. | |
480 | */ | |
481 | if (pdata->already_suspended) { | |
482 | dev_dbg(dev, "already suspended, leaving early\n"); | |
483 | pdata->already_suspended = 0; | |
484 | return 0; | |
485 | } | |
486 | ||
487 | if (!pdata->suspended) { | |
488 | dev_dbg(dev, "not suspended, leaving early\n"); | |
489 | return 0; | |
490 | } | |
491 | ||
492 | pdata->suspended = 0; | |
493 | ||
494 | dev_dbg(dev, "resuming...\n"); | |
495 | ||
496 | /* set host mode */ | |
497 | tmp = USBMODE_CM_HOST | (pdata->es ? USBMODE_ES : 0); | |
498 | ehci_writel(ehci, tmp, hcd->regs + FSL_SOC_USB_USBMODE); | |
499 | ||
500 | ehci_writel(ehci, pdata->pm_usbgenctrl, | |
501 | hcd->regs + FSL_SOC_USB_USBGENCTRL); | |
502 | ehci_writel(ehci, ISIPHYCTRL_PXE | ISIPHYCTRL_PHYE, | |
503 | hcd->regs + FSL_SOC_USB_ISIPHYCTRL); | |
504 | ||
761bbcb7 AG |
505 | ehci_writel(ehci, SBUSCFG_INCR8, hcd->regs + FSL_SOC_USB_SBUSCFG); |
506 | ||
13b7ee2a AG |
507 | /* restore EHCI registers */ |
508 | ehci_writel(ehci, pdata->pm_command, &ehci->regs->command); | |
509 | ehci_writel(ehci, pdata->pm_intr_enable, &ehci->regs->intr_enable); | |
510 | ehci_writel(ehci, pdata->pm_frame_index, &ehci->regs->frame_index); | |
511 | ehci_writel(ehci, pdata->pm_segment, &ehci->regs->segment); | |
512 | ehci_writel(ehci, pdata->pm_frame_list, &ehci->regs->frame_list); | |
513 | ehci_writel(ehci, pdata->pm_async_next, &ehci->regs->async_next); | |
514 | ehci_writel(ehci, pdata->pm_configured_flag, | |
515 | &ehci->regs->configured_flag); | |
516 | ehci_writel(ehci, pdata->pm_portsc, &ehci->regs->port_status[0]); | |
517 | ||
518 | set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); | |
e8799906 | 519 | ehci->rh_state = EHCI_RH_RUNNING; |
13b7ee2a AG |
520 | dev->power.power_state = PMSG_ON; |
521 | ||
522 | tmp = ehci_readl(ehci, &ehci->regs->command); | |
523 | tmp |= CMD_RUN; | |
524 | ehci_writel(ehci, tmp, &ehci->regs->command); | |
525 | ||
526 | usb_hcd_resume_root_hub(hcd); | |
527 | ||
528 | return 0; | |
529 | } | |
530 | #else | |
531 | static inline int ehci_fsl_mpc512x_drv_suspend(struct device *dev) | |
532 | { | |
533 | return 0; | |
534 | } | |
535 | ||
536 | static inline int ehci_fsl_mpc512x_drv_resume(struct device *dev) | |
537 | { | |
538 | return 0; | |
539 | } | |
540 | #endif /* CONFIG_PPC_MPC512x */ | |
541 | ||
1af10774 AV |
542 | static struct ehci_fsl *hcd_to_ehci_fsl(struct usb_hcd *hcd) |
543 | { | |
544 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | |
545 | ||
546 | return container_of(ehci, struct ehci_fsl, ehci); | |
547 | } | |
548 | ||
549 | static int ehci_fsl_drv_suspend(struct device *dev) | |
550 | { | |
551 | struct usb_hcd *hcd = dev_get_drvdata(dev); | |
552 | struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd); | |
553 | void __iomem *non_ehci = hcd->regs; | |
554 | ||
13b7ee2a AG |
555 | if (of_device_is_compatible(dev->parent->of_node, |
556 | "fsl,mpc5121-usb2-dr")) { | |
557 | return ehci_fsl_mpc512x_drv_suspend(dev); | |
558 | } | |
559 | ||
4147200d AS |
560 | ehci_prepare_ports_for_controller_suspend(hcd_to_ehci(hcd), |
561 | device_may_wakeup(dev)); | |
1af10774 AV |
562 | if (!fsl_deep_sleep()) |
563 | return 0; | |
564 | ||
6f5429d9 | 565 | ehci_fsl->usb_ctrl = ioread32be(non_ehci + FSL_SOC_USB_CTRL); |
1af10774 AV |
566 | return 0; |
567 | } | |
568 | ||
569 | static int ehci_fsl_drv_resume(struct device *dev) | |
570 | { | |
571 | struct usb_hcd *hcd = dev_get_drvdata(dev); | |
572 | struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd); | |
573 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | |
574 | void __iomem *non_ehci = hcd->regs; | |
575 | ||
13b7ee2a AG |
576 | if (of_device_is_compatible(dev->parent->of_node, |
577 | "fsl,mpc5121-usb2-dr")) { | |
578 | return ehci_fsl_mpc512x_drv_resume(dev); | |
579 | } | |
580 | ||
16032c4f | 581 | ehci_prepare_ports_for_controller_resume(ehci); |
1af10774 AV |
582 | if (!fsl_deep_sleep()) |
583 | return 0; | |
584 | ||
585 | usb_root_hub_lost_power(hcd->self.root_hub); | |
586 | ||
587 | /* Restore USB PHY settings and enable the controller. */ | |
6f5429d9 | 588 | iowrite32be(ehci_fsl->usb_ctrl, non_ehci + FSL_SOC_USB_CTRL); |
1af10774 AV |
589 | |
590 | ehci_reset(ehci); | |
591 | ehci_fsl_reinit(ehci); | |
592 | ||
593 | return 0; | |
594 | } | |
595 | ||
596 | static int ehci_fsl_drv_restore(struct device *dev) | |
597 | { | |
598 | struct usb_hcd *hcd = dev_get_drvdata(dev); | |
599 | ||
600 | usb_root_hub_lost_power(hcd->self.root_hub); | |
601 | return 0; | |
602 | } | |
603 | ||
fd7723e2 | 604 | static const struct dev_pm_ops ehci_fsl_pm_ops = { |
1af10774 AV |
605 | .suspend = ehci_fsl_drv_suspend, |
606 | .resume = ehci_fsl_drv_resume, | |
607 | .restore = ehci_fsl_drv_restore, | |
608 | }; | |
609 | ||
610 | #define EHCI_FSL_PM_OPS (&ehci_fsl_pm_ops) | |
611 | #else | |
612 | #define EHCI_FSL_PM_OPS NULL | |
613 | #endif /* CONFIG_PM */ | |
614 | ||
83722bc9 AG |
615 | #ifdef CONFIG_USB_OTG |
616 | static int ehci_start_port_reset(struct usb_hcd *hcd, unsigned port) | |
617 | { | |
618 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | |
619 | u32 status; | |
620 | ||
621 | if (!port) | |
622 | return -EINVAL; | |
623 | ||
624 | port--; | |
625 | ||
626 | /* start port reset before HNP protocol time out */ | |
627 | status = readl(&ehci->regs->port_status[port]); | |
628 | if (!(status & PORT_CONNECT)) | |
629 | return -ENODEV; | |
630 | ||
37ebb549 | 631 | /* hub_wq will finish the reset later */ |
83722bc9 AG |
632 | if (ehci_is_TDI(ehci)) { |
633 | writel(PORT_RESET | | |
634 | (status & ~(PORT_CSC | PORT_PEC | PORT_OCC)), | |
635 | &ehci->regs->port_status[port]); | |
636 | } else { | |
637 | writel(PORT_RESET, &ehci->regs->port_status[port]); | |
638 | } | |
639 | ||
640 | return 0; | |
641 | } | |
642 | #else | |
643 | #define ehci_start_port_reset NULL | |
644 | #endif /* CONFIG_USB_OTG */ | |
645 | ||
b491f61e | 646 | static const struct ehci_driver_overrides ehci_fsl_overrides __initconst = { |
ca07e1c1 RM |
647 | .extra_priv_size = sizeof(struct ehci_fsl), |
648 | .reset = ehci_fsl_setup, | |
649 | }; | |
83722bc9 | 650 | |
ca07e1c1 RM |
651 | /** |
652 | * fsl_ehci_drv_remove - shutdown processing for FSL-based HCDs | |
653 | * @dev: USB Host Controller being removed | |
654 | * Context: !in_interrupt() | |
655 | * | |
656 | * Reverses the effect of usb_hcd_fsl_probe(). | |
657 | * | |
658 | */ | |
80cb9aee | 659 | |
ca07e1c1 RM |
660 | static int fsl_ehci_drv_remove(struct platform_device *pdev) |
661 | { | |
662 | struct fsl_usb2_platform_data *pdata = dev_get_platdata(&pdev->dev); | |
663 | struct usb_hcd *hcd = platform_get_drvdata(pdev); | |
80cb9aee | 664 | |
ca07e1c1 RM |
665 | if (!IS_ERR_OR_NULL(hcd->usb_phy)) { |
666 | otg_set_host(hcd->usb_phy->otg, NULL); | |
667 | usb_put_phy(hcd->usb_phy); | |
668 | } | |
80cb9aee | 669 | |
ca07e1c1 | 670 | usb_remove_hcd(hcd); |
80cb9aee RV |
671 | |
672 | /* | |
ca07e1c1 RM |
673 | * do platform specific un-initialization: |
674 | * release iomux pins, disable clock, etc. | |
80cb9aee | 675 | */ |
ca07e1c1 RM |
676 | if (pdata->exit) |
677 | pdata->exit(pdev); | |
678 | usb_put_hcd(hcd); | |
80cb9aee | 679 | |
ca07e1c1 RM |
680 | return 0; |
681 | } | |
682 | ||
683 | static struct platform_driver ehci_fsl_driver = { | |
684 | .probe = fsl_ehci_drv_probe, | |
685 | .remove = fsl_ehci_drv_remove, | |
686 | .shutdown = usb_hcd_platform_shutdown, | |
687 | .driver = { | |
688 | .name = "fsl-ehci", | |
689 | .pm = EHCI_FSL_PM_OPS, | |
690 | }, | |
80cb9aee RV |
691 | }; |
692 | ||
ca07e1c1 | 693 | static int __init ehci_fsl_init(void) |
80cb9aee RV |
694 | { |
695 | if (usb_disabled()) | |
696 | return -ENODEV; | |
697 | ||
ca07e1c1 | 698 | pr_info(DRV_NAME ": " DRIVER_DESC "\n"); |
80cb9aee | 699 | |
ca07e1c1 | 700 | ehci_init_driver(&fsl_ehci_hc_driver, &ehci_fsl_overrides); |
80cb9aee | 701 | |
ca07e1c1 RM |
702 | fsl_ehci_hc_driver.product_desc = |
703 | "Freescale On-Chip EHCI Host Controller"; | |
704 | fsl_ehci_hc_driver.start_port_reset = ehci_start_port_reset; | |
705 | ||
706 | ||
707 | return platform_driver_register(&ehci_fsl_driver); | |
80cb9aee | 708 | } |
ca07e1c1 | 709 | module_init(ehci_fsl_init); |
80cb9aee | 710 | |
ca07e1c1 RM |
711 | static void __exit ehci_fsl_cleanup(void) |
712 | { | |
713 | platform_driver_unregister(&ehci_fsl_driver); | |
714 | } | |
715 | module_exit(ehci_fsl_cleanup); | |
80cb9aee | 716 | |
ca07e1c1 RM |
717 | MODULE_DESCRIPTION(DRIVER_DESC); |
718 | MODULE_LICENSE("GPL"); | |
719 | MODULE_ALIAS("platform:" DRV_NAME); |