]>
Commit | Line | Data |
---|---|---|
5fd54ace | 1 | // SPDX-License-Identifier: GPL-2.0+ |
58c559e6 | 2 | /* Copyright (C) 2005-2010,2012 Freescale Semiconductor, Inc. |
80cb9aee RV |
3 | * Copyright (c) 2005 MontaVista Software |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License as published by the | |
7 | * Free Software Foundation; either version 2 of the License, or (at your | |
8 | * option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, but | |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
13 | * General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License along | |
16 | * with this program; if not, write to the Free Software Foundation, Inc., | |
17 | * 675 Mass Ave, Cambridge, MA 02139, USA. | |
18 | */ | |
19 | #ifndef _EHCI_FSL_H | |
20 | #define _EHCI_FSL_H | |
21 | ||
22 | /* offsets for the non-ehci registers in the FSL SOC USB controller */ | |
761bbcb7 AG |
23 | #define FSL_SOC_USB_SBUSCFG 0x90 |
24 | #define SBUSCFG_INCR8 0x02 /* INCR8, specified */ | |
80cb9aee RV |
25 | #define FSL_SOC_USB_ULPIVP 0x170 |
26 | #define FSL_SOC_USB_PORTSC1 0x184 | |
27 | #define PORT_PTS_MSK (3<<30) | |
28 | #define PORT_PTS_UTMI (0<<30) | |
29 | #define PORT_PTS_ULPI (2<<30) | |
30 | #define PORT_PTS_SERIAL (3<<30) | |
31 | #define PORT_PTS_PTW (1<<28) | |
32 | #define FSL_SOC_USB_PORTSC2 0x188 | |
13b7ee2a AG |
33 | #define FSL_SOC_USB_USBMODE 0x1a8 |
34 | #define USBMODE_CM_MASK (3 << 0) /* controller mode mask */ | |
35 | #define USBMODE_CM_HOST (3 << 0) /* controller mode: host */ | |
36 | #define USBMODE_ES (1 << 2) /* (Big) Endian Select */ | |
230f7ede AG |
37 | |
38 | #define FSL_SOC_USB_USBGENCTRL 0x200 | |
39 | #define USBGENCTRL_PPP (1 << 3) | |
40 | #define USBGENCTRL_PFP (1 << 2) | |
41 | #define FSL_SOC_USB_ISIPHYCTRL 0x204 | |
42 | #define ISIPHYCTRL_PXE (1) | |
43 | #define ISIPHYCTRL_PHYE (1 << 4) | |
44 | ||
80cb9aee RV |
45 | #define FSL_SOC_USB_SNOOP1 0x400 /* NOTE: big-endian */ |
46 | #define FSL_SOC_USB_SNOOP2 0x404 /* NOTE: big-endian */ | |
47 | #define FSL_SOC_USB_AGECNTTHRSH 0x408 /* NOTE: big-endian */ | |
7378c57a CE |
48 | #define FSL_SOC_USB_PRICTRL 0x40c /* NOTE: big-endian */ |
49 | #define FSL_SOC_USB_SICTRL 0x410 /* NOTE: big-endian */ | |
80cb9aee | 50 | #define FSL_SOC_USB_CTRL 0x500 /* NOTE: big-endian */ |
28c56ea1 | 51 | #define CTRL_UTMI_PHY_EN (1<<9) |
529febee | 52 | #define CTRL_PHY_CLK_VALID (1 << 17) |
40acc095 | 53 | #define SNOOP_SIZE_2GB 0x1e |
58c559e6 RM |
54 | |
55 | /* control Register Bit Masks */ | |
4e02bea8 | 56 | #define CONTROL_REGISTER_W1C_MASK 0x00020000 /* W1C: PHY_CLK_VALID */ |
58c559e6 RM |
57 | #define ULPI_INT_EN (1<<0) |
58 | #define WU_INT_EN (1<<1) | |
59 | #define USB_CTRL_USB_EN (1<<2) | |
60 | #define LINE_STATE_FILTER__EN (1<<3) | |
61 | #define KEEP_OTG_ON (1<<4) | |
62 | #define OTG_PORT (1<<5) | |
63 | #define PLL_RESET (1<<8) | |
64 | #define UTMI_PHY_EN (1<<9) | |
65 | #define ULPI_PHY_CLK_SEL (1<<10) | |
3735ba8d | 66 | #define PHY_CLK_VALID (1<<17) |
80cb9aee | 67 | #endif /* _EHCI_FSL_H */ |