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1da177e4 LT |
1 | /* |
2 | * Copyright (c) 2000-2004 by David Brownell | |
53bd6a60 | 3 | * |
1da177e4 LT |
4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms of the GNU General Public License as published by the | |
6 | * Free Software Foundation; either version 2 of the License, or (at your | |
7 | * option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but | |
10 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
11 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 | * for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software Foundation, | |
16 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
17 | */ | |
18 | ||
1da177e4 LT |
19 | #include <linux/module.h> |
20 | #include <linux/pci.h> | |
21 | #include <linux/dmapool.h> | |
22 | #include <linux/kernel.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/ioport.h> | |
25 | #include <linux/sched.h> | |
26 | #include <linux/slab.h> | |
1da177e4 LT |
27 | #include <linux/errno.h> |
28 | #include <linux/init.h> | |
29 | #include <linux/timer.h> | |
30 | #include <linux/list.h> | |
31 | #include <linux/interrupt.h> | |
32 | #include <linux/reboot.h> | |
33 | #include <linux/usb.h> | |
34 | #include <linux/moduleparam.h> | |
35 | #include <linux/dma-mapping.h> | |
36 | ||
37 | #include "../core/hcd.h" | |
38 | ||
39 | #include <asm/byteorder.h> | |
40 | #include <asm/io.h> | |
41 | #include <asm/irq.h> | |
42 | #include <asm/system.h> | |
43 | #include <asm/unaligned.h> | |
48fda451 IK |
44 | #ifdef CONFIG_PPC_PS3 |
45 | #include <asm/firmware.h> | |
46 | #endif | |
1da177e4 LT |
47 | |
48 | ||
49 | /*-------------------------------------------------------------------------*/ | |
50 | ||
51 | /* | |
52 | * EHCI hc_driver implementation ... experimental, incomplete. | |
53 | * Based on the final 1.0 register interface specification. | |
54 | * | |
55 | * USB 2.0 shows up in upcoming www.pcmcia.org technology. | |
56 | * First was PCMCIA, like ISA; then CardBus, which is PCI. | |
57 | * Next comes "CardBay", using USB 2.0 signals. | |
58 | * | |
59 | * Contains additional contributions by Brad Hards, Rory Bolt, and others. | |
60 | * Special thanks to Intel and VIA for providing host controllers to | |
61 | * test this driver on, and Cypress (including In-System Design) for | |
62 | * providing early devices for those host controllers to talk to! | |
63 | * | |
64 | * HISTORY: | |
65 | * | |
66 | * 2004-05-10 Root hub and PCI suspend/resume support; remote wakeup. (db) | |
67 | * 2004-02-24 Replace pci_* with generic dma_* API calls (dsaxena@plexity.net) | |
68 | * 2003-12-29 Rewritten high speed iso transfer support (by Michal Sojka, | |
69 | * <sojkam@centrum.cz>, updates by DB). | |
70 | * | |
71 | * 2002-11-29 Correct handling for hw async_next register. | |
72 | * 2002-08-06 Handling for bulk and interrupt transfers is mostly shared; | |
73 | * only scheduling is different, no arbitrary limitations. | |
74 | * 2002-07-25 Sanity check PCI reads, mostly for better cardbus support, | |
53bd6a60 | 75 | * clean up HC run state handshaking. |
1da177e4 LT |
76 | * 2002-05-24 Preliminary FS/LS interrupts, using scheduling shortcuts |
77 | * 2002-05-11 Clear TT errors for FS/LS ctrl/bulk. Fill in some other | |
78 | * missing pieces: enabling 64bit dma, handoff from BIOS/SMM. | |
79 | * 2002-05-07 Some error path cleanups to report better errors; wmb(); | |
80 | * use non-CVS version id; better iso bandwidth claim. | |
81 | * 2002-04-19 Control/bulk/interrupt submit no longer uses giveback() on | |
82 | * errors in submit path. Bugfixes to interrupt scheduling/processing. | |
83 | * 2002-03-05 Initial high-speed ISO support; reduce ITD memory; shift | |
84 | * more checking to generic hcd framework (db). Make it work with | |
85 | * Philips EHCI; reduce PCI traffic; shorten IRQ path (Rory Bolt). | |
86 | * 2002-01-14 Minor cleanup; version synch. | |
87 | * 2002-01-08 Fix roothub handoff of FS/LS to companion controllers. | |
88 | * 2002-01-04 Control/Bulk queuing behaves. | |
89 | * | |
90 | * 2001-12-12 Initial patch version for Linux 2.5.1 kernel. | |
91 | * 2001-June Works with usb-storage and NEC EHCI on 2.4 | |
92 | */ | |
93 | ||
94 | #define DRIVER_VERSION "10 Dec 2004" | |
95 | #define DRIVER_AUTHOR "David Brownell" | |
96 | #define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver" | |
97 | ||
98 | static const char hcd_name [] = "ehci_hcd"; | |
99 | ||
100 | ||
101 | #undef EHCI_VERBOSE_DEBUG | |
102 | #undef EHCI_URB_TRACE | |
103 | ||
104 | #ifdef DEBUG | |
105 | #define EHCI_STATS | |
106 | #endif | |
107 | ||
108 | /* magic numbers that can affect system performance */ | |
109 | #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */ | |
110 | #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */ | |
111 | #define EHCI_TUNE_RL_TT 0 | |
112 | #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */ | |
113 | #define EHCI_TUNE_MULT_TT 1 | |
114 | #define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */ | |
115 | ||
64f89798 | 116 | #define EHCI_IAA_JIFFIES (HZ/100) /* arbitrary; ~10 msec */ |
1da177e4 LT |
117 | #define EHCI_IO_JIFFIES (HZ/10) /* io watchdog > irq_thresh */ |
118 | #define EHCI_ASYNC_JIFFIES (HZ/20) /* async idle timeout */ | |
119 | #define EHCI_SHRINK_JIFFIES (HZ/200) /* async qh unlink delay */ | |
120 | ||
121 | /* Initial IRQ latency: faster than hw default */ | |
122 | static int log2_irq_thresh = 0; // 0 to 6 | |
123 | module_param (log2_irq_thresh, int, S_IRUGO); | |
124 | MODULE_PARM_DESC (log2_irq_thresh, "log2 IRQ latency, 1-64 microframes"); | |
125 | ||
126 | /* initial park setting: slower than hw default */ | |
127 | static unsigned park = 0; | |
128 | module_param (park, uint, S_IRUGO); | |
129 | MODULE_PARM_DESC (park, "park setting; 1-3 back-to-back async packets"); | |
130 | ||
93f1a47c DB |
131 | /* for flakey hardware, ignore overcurrent indicators */ |
132 | static int ignore_oc = 0; | |
133 | module_param (ignore_oc, bool, S_IRUGO); | |
134 | MODULE_PARM_DESC (ignore_oc, "ignore bogus hardware overcurrent indications"); | |
135 | ||
1da177e4 LT |
136 | #define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT) |
137 | ||
138 | /*-------------------------------------------------------------------------*/ | |
139 | ||
140 | #include "ehci.h" | |
141 | #include "ehci-dbg.c" | |
142 | ||
143 | /*-------------------------------------------------------------------------*/ | |
144 | ||
145 | /* | |
146 | * handshake - spin reading hc until handshake completes or fails | |
147 | * @ptr: address of hc register to be read | |
148 | * @mask: bits to look at in result of read | |
149 | * @done: value of those bits when handshake succeeds | |
150 | * @usec: timeout in microseconds | |
151 | * | |
152 | * Returns negative errno, or zero on success | |
153 | * | |
154 | * Success happens when the "mask" bits have the specified value (hardware | |
155 | * handshake done). There are two failure modes: "usec" have passed (major | |
156 | * hardware flakeout), or the register reads as all-ones (hardware removed). | |
157 | * | |
158 | * That last failure should_only happen in cases like physical cardbus eject | |
159 | * before driver shutdown. But it also seems to be caused by bugs in cardbus | |
160 | * bridge shutdown: shutting down the bridge before the devices using it. | |
161 | */ | |
083522d7 BH |
162 | static int handshake (struct ehci_hcd *ehci, void __iomem *ptr, |
163 | u32 mask, u32 done, int usec) | |
1da177e4 LT |
164 | { |
165 | u32 result; | |
166 | ||
167 | do { | |
083522d7 | 168 | result = ehci_readl(ehci, ptr); |
1da177e4 LT |
169 | if (result == ~(u32)0) /* card removed */ |
170 | return -ENODEV; | |
171 | result &= mask; | |
172 | if (result == done) | |
173 | return 0; | |
174 | udelay (1); | |
175 | usec--; | |
176 | } while (usec > 0); | |
177 | return -ETIMEDOUT; | |
178 | } | |
179 | ||
180 | /* force HC to halt state from unknown (EHCI spec section 2.3) */ | |
181 | static int ehci_halt (struct ehci_hcd *ehci) | |
182 | { | |
083522d7 | 183 | u32 temp = ehci_readl(ehci, &ehci->regs->status); |
1da177e4 | 184 | |
72f30b6f | 185 | /* disable any irqs left enabled by previous code */ |
083522d7 | 186 | ehci_writel(ehci, 0, &ehci->regs->intr_enable); |
72f30b6f | 187 | |
1da177e4 LT |
188 | if ((temp & STS_HALT) != 0) |
189 | return 0; | |
190 | ||
083522d7 | 191 | temp = ehci_readl(ehci, &ehci->regs->command); |
1da177e4 | 192 | temp &= ~CMD_RUN; |
083522d7 BH |
193 | ehci_writel(ehci, temp, &ehci->regs->command); |
194 | return handshake (ehci, &ehci->regs->status, | |
195 | STS_HALT, STS_HALT, 16 * 125); | |
1da177e4 LT |
196 | } |
197 | ||
198 | /* put TDI/ARC silicon into EHCI mode */ | |
199 | static void tdi_reset (struct ehci_hcd *ehci) | |
200 | { | |
201 | u32 __iomem *reg_ptr; | |
202 | u32 tmp; | |
203 | ||
204 | reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + 0x68); | |
083522d7 | 205 | tmp = ehci_readl(ehci, reg_ptr); |
1da177e4 | 206 | tmp |= 0x3; |
083522d7 | 207 | ehci_writel(ehci, tmp, reg_ptr); |
1da177e4 LT |
208 | } |
209 | ||
210 | /* reset a non-running (STS_HALT == 1) controller */ | |
211 | static int ehci_reset (struct ehci_hcd *ehci) | |
212 | { | |
213 | int retval; | |
083522d7 | 214 | u32 command = ehci_readl(ehci, &ehci->regs->command); |
1da177e4 LT |
215 | |
216 | command |= CMD_RESET; | |
217 | dbg_cmd (ehci, "reset", command); | |
083522d7 | 218 | ehci_writel(ehci, command, &ehci->regs->command); |
1da177e4 LT |
219 | ehci_to_hcd(ehci)->state = HC_STATE_HALT; |
220 | ehci->next_statechange = jiffies; | |
083522d7 BH |
221 | retval = handshake (ehci, &ehci->regs->command, |
222 | CMD_RESET, 0, 250 * 1000); | |
1da177e4 LT |
223 | |
224 | if (retval) | |
225 | return retval; | |
226 | ||
227 | if (ehci_is_TDI(ehci)) | |
228 | tdi_reset (ehci); | |
229 | ||
230 | return retval; | |
231 | } | |
232 | ||
233 | /* idle the controller (from running) */ | |
234 | static void ehci_quiesce (struct ehci_hcd *ehci) | |
235 | { | |
236 | u32 temp; | |
237 | ||
238 | #ifdef DEBUG | |
239 | if (!HC_IS_RUNNING (ehci_to_hcd(ehci)->state)) | |
240 | BUG (); | |
241 | #endif | |
242 | ||
243 | /* wait for any schedule enables/disables to take effect */ | |
083522d7 | 244 | temp = ehci_readl(ehci, &ehci->regs->command) << 10; |
1da177e4 | 245 | temp &= STS_ASS | STS_PSS; |
083522d7 | 246 | if (handshake (ehci, &ehci->regs->status, STS_ASS | STS_PSS, |
1da177e4 LT |
247 | temp, 16 * 125) != 0) { |
248 | ehci_to_hcd(ehci)->state = HC_STATE_HALT; | |
249 | return; | |
250 | } | |
251 | ||
252 | /* then disable anything that's still active */ | |
083522d7 | 253 | temp = ehci_readl(ehci, &ehci->regs->command); |
1da177e4 | 254 | temp &= ~(CMD_ASE | CMD_IAAD | CMD_PSE); |
083522d7 | 255 | ehci_writel(ehci, temp, &ehci->regs->command); |
1da177e4 LT |
256 | |
257 | /* hardware can take 16 microframes to turn off ... */ | |
083522d7 | 258 | if (handshake (ehci, &ehci->regs->status, STS_ASS | STS_PSS, |
1da177e4 LT |
259 | 0, 16 * 125) != 0) { |
260 | ehci_to_hcd(ehci)->state = HC_STATE_HALT; | |
261 | return; | |
262 | } | |
263 | } | |
264 | ||
265 | /*-------------------------------------------------------------------------*/ | |
266 | ||
7d12e780 | 267 | static void ehci_work(struct ehci_hcd *ehci); |
1da177e4 LT |
268 | |
269 | #include "ehci-hub.c" | |
270 | #include "ehci-mem.c" | |
271 | #include "ehci-q.c" | |
272 | #include "ehci-sched.c" | |
273 | ||
274 | /*-------------------------------------------------------------------------*/ | |
275 | ||
196705c9 SD |
276 | #ifdef CONFIG_CPU_FREQ |
277 | ||
278 | #include <linux/cpufreq.h> | |
279 | ||
280 | static void ehci_cpufreq_pause (struct ehci_hcd *ehci) | |
281 | { | |
282 | unsigned long flags; | |
283 | ||
284 | spin_lock_irqsave(&ehci->lock, flags); | |
285 | if (!ehci->cpufreq_changing++) | |
286 | qh_inactivate_split_intr_qhs(ehci); | |
287 | spin_unlock_irqrestore(&ehci->lock, flags); | |
288 | } | |
289 | ||
290 | static void ehci_cpufreq_unpause (struct ehci_hcd *ehci) | |
291 | { | |
292 | unsigned long flags; | |
293 | ||
294 | spin_lock_irqsave(&ehci->lock, flags); | |
295 | if (!--ehci->cpufreq_changing) | |
296 | qh_reactivate_split_intr_qhs(ehci); | |
297 | spin_unlock_irqrestore(&ehci->lock, flags); | |
298 | } | |
299 | ||
300 | /* | |
301 | * ehci_cpufreq_notifier is needed to avoid MMF errors that occur when | |
302 | * EHCI controllers that don't cache many uframes get delayed trying to | |
303 | * read main memory during CPU frequency transitions. This can cause | |
304 | * split interrupt transactions to not be completed in the required uframe. | |
305 | * This has been observed on the Broadcom/ServerWorks HT1000 controller. | |
306 | */ | |
307 | static int ehci_cpufreq_notifier(struct notifier_block *nb, unsigned long val, | |
308 | void *data) | |
309 | { | |
310 | struct ehci_hcd *ehci = container_of(nb, struct ehci_hcd, | |
311 | cpufreq_transition); | |
312 | ||
313 | switch (val) { | |
314 | case CPUFREQ_PRECHANGE: | |
315 | ehci_cpufreq_pause(ehci); | |
316 | break; | |
317 | case CPUFREQ_POSTCHANGE: | |
318 | ehci_cpufreq_unpause(ehci); | |
319 | break; | |
320 | } | |
321 | return 0; | |
322 | } | |
323 | ||
324 | #endif | |
325 | ||
326 | /*-------------------------------------------------------------------------*/ | |
327 | ||
64f89798 | 328 | static void ehci_watchdog (unsigned long param) |
1da177e4 LT |
329 | { |
330 | struct ehci_hcd *ehci = (struct ehci_hcd *) param; | |
331 | unsigned long flags; | |
332 | ||
333 | spin_lock_irqsave (&ehci->lock, flags); | |
334 | ||
64f89798 | 335 | /* lost IAA irqs wedge things badly; seen with a vt8235 */ |
1da177e4 | 336 | if (ehci->reclaim) { |
083522d7 | 337 | u32 status = ehci_readl(ehci, &ehci->regs->status); |
1da177e4 LT |
338 | if (status & STS_IAA) { |
339 | ehci_vdbg (ehci, "lost IAA\n"); | |
340 | COUNT (ehci->stats.lost_iaa); | |
083522d7 | 341 | ehci_writel(ehci, STS_IAA, &ehci->regs->status); |
64f89798 | 342 | ehci->reclaim_ready = 1; |
1da177e4 LT |
343 | } |
344 | } | |
345 | ||
64f89798 | 346 | /* stop async processing after it's idled a bit */ |
1da177e4 | 347 | if (test_bit (TIMER_ASYNC_OFF, &ehci->actions)) |
26f953fd | 348 | start_unlink_async (ehci, ehci->async); |
1da177e4 LT |
349 | |
350 | /* ehci could run by timer, without IRQs ... */ | |
7d12e780 | 351 | ehci_work (ehci); |
1da177e4 LT |
352 | |
353 | spin_unlock_irqrestore (&ehci->lock, flags); | |
354 | } | |
355 | ||
8903795a AS |
356 | /* On some systems, leaving remote wakeup enabled prevents system shutdown. |
357 | * The firmware seems to think that powering off is a wakeup event! | |
358 | * This routine turns off remote wakeup and everything else, on all ports. | |
359 | */ | |
360 | static void ehci_turn_off_all_ports(struct ehci_hcd *ehci) | |
361 | { | |
362 | int port = HCS_N_PORTS(ehci->hcs_params); | |
363 | ||
364 | while (port--) | |
365 | ehci_writel(ehci, PORT_RWC_BITS, | |
366 | &ehci->regs->port_status[port]); | |
367 | } | |
368 | ||
64a21d02 | 369 | /* ehci_shutdown kick in for silicon on any bus (not just pci, etc). |
72f30b6f DB |
370 | * This forcibly disables dma and IRQs, helping kexec and other cases |
371 | * where the next system software may expect clean state. | |
372 | */ | |
64a21d02 AG |
373 | static void |
374 | ehci_shutdown (struct usb_hcd *hcd) | |
1da177e4 | 375 | { |
64a21d02 | 376 | struct ehci_hcd *ehci; |
1da177e4 | 377 | |
64a21d02 | 378 | ehci = hcd_to_ehci (hcd); |
72f30b6f | 379 | (void) ehci_halt (ehci); |
8903795a | 380 | ehci_turn_off_all_ports(ehci); |
1da177e4 LT |
381 | |
382 | /* make BIOS/etc use companion controller during reboot */ | |
083522d7 | 383 | ehci_writel(ehci, 0, &ehci->regs->configured_flag); |
8903795a AS |
384 | |
385 | /* unblock posted writes */ | |
386 | ehci_readl(ehci, &ehci->regs->configured_flag); | |
1da177e4 LT |
387 | } |
388 | ||
56c1e26d DB |
389 | static void ehci_port_power (struct ehci_hcd *ehci, int is_on) |
390 | { | |
391 | unsigned port; | |
392 | ||
393 | if (!HCS_PPC (ehci->hcs_params)) | |
394 | return; | |
395 | ||
396 | ehci_dbg (ehci, "...power%s ports...\n", is_on ? "up" : "down"); | |
397 | for (port = HCS_N_PORTS (ehci->hcs_params); port > 0; ) | |
398 | (void) ehci_hub_control(ehci_to_hcd(ehci), | |
399 | is_on ? SetPortFeature : ClearPortFeature, | |
400 | USB_PORT_FEAT_POWER, | |
401 | port--, NULL, 0); | |
402 | msleep(20); | |
403 | } | |
404 | ||
7ff71d6a | 405 | /*-------------------------------------------------------------------------*/ |
1da177e4 | 406 | |
7ff71d6a MP |
407 | /* |
408 | * ehci_work is called from some interrupts, timers, and so on. | |
409 | * it calls driver completion functions, after dropping ehci->lock. | |
410 | */ | |
7d12e780 | 411 | static void ehci_work (struct ehci_hcd *ehci) |
7ff71d6a MP |
412 | { |
413 | timer_action_done (ehci, TIMER_IO_WATCHDOG); | |
64f89798 GKH |
414 | if (ehci->reclaim_ready) |
415 | end_unlink_async (ehci); | |
7ff71d6a MP |
416 | |
417 | /* another CPU may drop ehci->lock during a schedule scan while | |
418 | * it reports urb completions. this flag guards against bogus | |
419 | * attempts at re-entrant schedule scanning. | |
420 | */ | |
421 | if (ehci->scanning) | |
422 | return; | |
423 | ehci->scanning = 1; | |
7d12e780 | 424 | scan_async (ehci); |
7ff71d6a | 425 | if (ehci->next_uframe != -1) |
7d12e780 | 426 | scan_periodic (ehci); |
7ff71d6a MP |
427 | ehci->scanning = 0; |
428 | ||
429 | /* the IO watchdog guards against hardware or driver bugs that | |
430 | * misplace IRQs, and should let us run completely without IRQs. | |
431 | * such lossage has been observed on both VT6202 and VT8235. | |
432 | */ | |
433 | if (HC_IS_RUNNING (ehci_to_hcd(ehci)->state) && | |
434 | (ehci->async->qh_next.ptr != NULL || | |
435 | ehci->periodic_sched != 0)) | |
436 | timer_action (ehci, TIMER_IO_WATCHDOG); | |
437 | } | |
1da177e4 | 438 | |
7ff71d6a | 439 | static void ehci_stop (struct usb_hcd *hcd) |
1da177e4 LT |
440 | { |
441 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
1da177e4 | 442 | |
7ff71d6a | 443 | ehci_dbg (ehci, "stop\n"); |
1da177e4 | 444 | |
7ff71d6a MP |
445 | /* Turn off port power on all root hub ports. */ |
446 | ehci_port_power (ehci, 0); | |
1da177e4 | 447 | |
7ff71d6a MP |
448 | /* no more interrupts ... */ |
449 | del_timer_sync (&ehci->watchdog); | |
56c1e26d | 450 | |
7ff71d6a MP |
451 | spin_lock_irq(&ehci->lock); |
452 | if (HC_IS_RUNNING (hcd->state)) | |
453 | ehci_quiesce (ehci); | |
1da177e4 | 454 | |
7ff71d6a | 455 | ehci_reset (ehci); |
083522d7 | 456 | ehci_writel(ehci, 0, &ehci->regs->intr_enable); |
7ff71d6a | 457 | spin_unlock_irq(&ehci->lock); |
1da177e4 | 458 | |
196705c9 SD |
459 | #ifdef CONFIG_CPU_FREQ |
460 | cpufreq_unregister_notifier(&ehci->cpufreq_transition, | |
461 | CPUFREQ_TRANSITION_NOTIFIER); | |
462 | #endif | |
7ff71d6a | 463 | /* let companion controllers work when we aren't */ |
083522d7 | 464 | ehci_writel(ehci, 0, &ehci->regs->configured_flag); |
56c1e26d | 465 | |
57e06c11 | 466 | remove_companion_file(ehci); |
7ff71d6a | 467 | remove_debug_files (ehci); |
1da177e4 | 468 | |
7ff71d6a MP |
469 | /* root hub is shut down separately (first, when possible) */ |
470 | spin_lock_irq (&ehci->lock); | |
471 | if (ehci->async) | |
7d12e780 | 472 | ehci_work (ehci); |
7ff71d6a MP |
473 | spin_unlock_irq (&ehci->lock); |
474 | ehci_mem_cleanup (ehci); | |
1da177e4 | 475 | |
7ff71d6a MP |
476 | #ifdef EHCI_STATS |
477 | ehci_dbg (ehci, "irq normal %ld err %ld reclaim %ld (lost %ld)\n", | |
478 | ehci->stats.normal, ehci->stats.error, ehci->stats.reclaim, | |
479 | ehci->stats.lost_iaa); | |
480 | ehci_dbg (ehci, "complete %ld unlink %ld\n", | |
481 | ehci->stats.complete, ehci->stats.unlink); | |
1da177e4 | 482 | #endif |
1da177e4 | 483 | |
083522d7 BH |
484 | dbg_status (ehci, "ehci_stop completed", |
485 | ehci_readl(ehci, &ehci->regs->status)); | |
1da177e4 LT |
486 | } |
487 | ||
18807521 DB |
488 | /* one-time init, only for memory state */ |
489 | static int ehci_init(struct usb_hcd *hcd) | |
1da177e4 | 490 | { |
18807521 | 491 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); |
1da177e4 | 492 | u32 temp; |
1da177e4 LT |
493 | int retval; |
494 | u32 hcc_params; | |
18807521 DB |
495 | |
496 | spin_lock_init(&ehci->lock); | |
497 | ||
498 | init_timer(&ehci->watchdog); | |
499 | ehci->watchdog.function = ehci_watchdog; | |
500 | ehci->watchdog.data = (unsigned long) ehci; | |
1da177e4 LT |
501 | |
502 | /* | |
503 | * hw default: 1K periodic list heads, one per frame. | |
504 | * periodic_size can shrink by USBCMD update if hcc_params allows. | |
505 | */ | |
506 | ehci->periodic_size = DEFAULT_I_TDPS; | |
18807521 | 507 | if ((retval = ehci_mem_init(ehci, GFP_KERNEL)) < 0) |
1da177e4 LT |
508 | return retval; |
509 | ||
510 | /* controllers may cache some of the periodic schedule ... */ | |
083522d7 | 511 | hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params); |
53bd6a60 | 512 | if (HCC_ISOC_CACHE(hcc_params)) // full frame cache |
1da177e4 LT |
513 | ehci->i_thresh = 8; |
514 | else // N microframes cached | |
18807521 | 515 | ehci->i_thresh = 2 + HCC_ISOC_THRES(hcc_params); |
1da177e4 LT |
516 | |
517 | ehci->reclaim = NULL; | |
64f89798 | 518 | ehci->reclaim_ready = 0; |
1da177e4 LT |
519 | ehci->next_uframe = -1; |
520 | ||
1da177e4 LT |
521 | /* |
522 | * dedicate a qh for the async ring head, since we couldn't unlink | |
523 | * a 'real' qh without stopping the async schedule [4.8]. use it | |
524 | * as the 'reclamation list head' too. | |
525 | * its dummy is used in hw_alt_next of many tds, to prevent the qh | |
526 | * from automatically advancing to the next td after short reads. | |
527 | */ | |
18807521 | 528 | ehci->async->qh_next.qh = NULL; |
6dbd682b SR |
529 | ehci->async->hw_next = QH_NEXT(ehci, ehci->async->qh_dma); |
530 | ehci->async->hw_info1 = cpu_to_hc32(ehci, QH_HEAD); | |
531 | ehci->async->hw_token = cpu_to_hc32(ehci, QTD_STS_HALT); | |
532 | ehci->async->hw_qtd_next = EHCI_LIST_END(ehci); | |
18807521 | 533 | ehci->async->qh_state = QH_STATE_LINKED; |
6dbd682b | 534 | ehci->async->hw_alt_next = QTD_NEXT(ehci, ehci->async->dummy->qtd_dma); |
1da177e4 LT |
535 | |
536 | /* clear interrupt enables, set irq latency */ | |
537 | if (log2_irq_thresh < 0 || log2_irq_thresh > 6) | |
538 | log2_irq_thresh = 0; | |
539 | temp = 1 << (16 + log2_irq_thresh); | |
540 | if (HCC_CANPARK(hcc_params)) { | |
541 | /* HW default park == 3, on hardware that supports it (like | |
542 | * NVidia and ALI silicon), maximizes throughput on the async | |
543 | * schedule by avoiding QH fetches between transfers. | |
544 | * | |
545 | * With fast usb storage devices and NForce2, "park" seems to | |
546 | * make problems: throughput reduction (!), data errors... | |
547 | */ | |
548 | if (park) { | |
18807521 | 549 | park = min(park, (unsigned) 3); |
1da177e4 LT |
550 | temp |= CMD_PARK; |
551 | temp |= park << 8; | |
552 | } | |
18807521 | 553 | ehci_dbg(ehci, "park %d\n", park); |
1da177e4 | 554 | } |
18807521 | 555 | if (HCC_PGM_FRAMELISTLEN(hcc_params)) { |
1da177e4 LT |
556 | /* periodic schedule size can be smaller than default */ |
557 | temp &= ~(3 << 2); | |
558 | temp |= (EHCI_TUNE_FLS << 2); | |
559 | switch (EHCI_TUNE_FLS) { | |
560 | case 0: ehci->periodic_size = 1024; break; | |
561 | case 1: ehci->periodic_size = 512; break; | |
562 | case 2: ehci->periodic_size = 256; break; | |
18807521 | 563 | default: BUG(); |
1da177e4 LT |
564 | } |
565 | } | |
18807521 DB |
566 | ehci->command = temp; |
567 | ||
196705c9 SD |
568 | #ifdef CONFIG_CPU_FREQ |
569 | INIT_LIST_HEAD(&ehci->split_intr_qhs); | |
570 | /* | |
571 | * If the EHCI controller caches enough uframes, this probably | |
572 | * isn't needed unless there are so many low/full speed devices | |
573 | * that the controller's can't cache it all. | |
574 | */ | |
575 | ehci->cpufreq_transition.notifier_call = ehci_cpufreq_notifier; | |
576 | cpufreq_register_notifier(&ehci->cpufreq_transition, | |
577 | CPUFREQ_TRANSITION_NOTIFIER); | |
578 | #endif | |
18807521 DB |
579 | return 0; |
580 | } | |
581 | ||
582 | /* start HC running; it's halted, ehci_init() has been run (once) */ | |
583 | static int ehci_run (struct usb_hcd *hcd) | |
584 | { | |
585 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
586 | int retval; | |
587 | u32 temp; | |
588 | u32 hcc_params; | |
589 | ||
1d619f12 MT |
590 | hcd->uses_new_polling = 1; |
591 | hcd->poll_rh = 0; | |
592 | ||
18807521 DB |
593 | /* EHCI spec section 4.1 */ |
594 | if ((retval = ehci_reset(ehci)) != 0) { | |
18807521 DB |
595 | ehci_mem_cleanup(ehci); |
596 | return retval; | |
597 | } | |
083522d7 BH |
598 | ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list); |
599 | ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next); | |
18807521 DB |
600 | |
601 | /* | |
602 | * hcc_params controls whether ehci->regs->segment must (!!!) | |
603 | * be used; it constrains QH/ITD/SITD and QTD locations. | |
604 | * pci_pool consistent memory always uses segment zero. | |
605 | * streaming mappings for I/O buffers, like pci_map_single(), | |
606 | * can return segments above 4GB, if the device allows. | |
607 | * | |
608 | * NOTE: the dma mask is visible through dma_supported(), so | |
609 | * drivers can pass this info along ... like NETIF_F_HIGHDMA, | |
610 | * Scsi_Host.highmem_io, and so forth. It's readonly to all | |
611 | * host side drivers though. | |
612 | */ | |
083522d7 | 613 | hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params); |
18807521 | 614 | if (HCC_64BIT_ADDR(hcc_params)) { |
083522d7 | 615 | ehci_writel(ehci, 0, &ehci->regs->segment); |
18807521 DB |
616 | #if 0 |
617 | // this is deeply broken on almost all architectures | |
618 | if (!dma_set_mask(hcd->self.controller, DMA_64BIT_MASK)) | |
619 | ehci_info(ehci, "enabled 64bit DMA\n"); | |
620 | #endif | |
621 | } | |
622 | ||
623 | ||
1da177e4 LT |
624 | // Philips, Intel, and maybe others need CMD_RUN before the |
625 | // root hub will detect new devices (why?); NEC doesn't | |
18807521 DB |
626 | ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET); |
627 | ehci->command |= CMD_RUN; | |
083522d7 | 628 | ehci_writel(ehci, ehci->command, &ehci->regs->command); |
18807521 | 629 | dbg_cmd (ehci, "init", ehci->command); |
1da177e4 | 630 | |
1da177e4 LT |
631 | /* |
632 | * Start, enabling full USB 2.0 functionality ... usb 1.1 devices | |
633 | * are explicitly handed to companion controller(s), so no TT is | |
634 | * involved with the root hub. (Except where one is integrated, | |
635 | * and there's no companion controller unless maybe for USB OTG.) | |
636 | */ | |
1da177e4 | 637 | hcd->state = HC_STATE_RUNNING; |
083522d7 BH |
638 | ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag); |
639 | ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */ | |
1da177e4 | 640 | |
083522d7 | 641 | temp = HC_VERSION(ehci_readl(ehci, &ehci->caps->hc_capbase)); |
1da177e4 | 642 | ehci_info (ehci, |
93f1a47c | 643 | "USB %x.%x started, EHCI %x.%02x, driver %s%s\n", |
7ff71d6a | 644 | ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f), |
93f1a47c DB |
645 | temp >> 8, temp & 0xff, DRIVER_VERSION, |
646 | ignore_oc ? ", overcurrent ignored" : ""); | |
1da177e4 | 647 | |
083522d7 BH |
648 | ehci_writel(ehci, INTR_MASK, |
649 | &ehci->regs->intr_enable); /* Turn On Interrupts */ | |
1da177e4 | 650 | |
18807521 DB |
651 | /* GRR this is run-once init(), being done every time the HC starts. |
652 | * So long as they're part of class devices, we can't do it init() | |
653 | * since the class device isn't created that early. | |
654 | */ | |
655 | create_debug_files(ehci); | |
57e06c11 | 656 | create_companion_file(ehci); |
1da177e4 LT |
657 | |
658 | return 0; | |
659 | } | |
660 | ||
1da177e4 LT |
661 | /*-------------------------------------------------------------------------*/ |
662 | ||
7d12e780 | 663 | static irqreturn_t ehci_irq (struct usb_hcd *hcd) |
1da177e4 LT |
664 | { |
665 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
1d619f12 | 666 | u32 status, pcd_status = 0; |
1da177e4 LT |
667 | int bh; |
668 | ||
669 | spin_lock (&ehci->lock); | |
670 | ||
083522d7 | 671 | status = ehci_readl(ehci, &ehci->regs->status); |
1da177e4 LT |
672 | |
673 | /* e.g. cardbus physical eject */ | |
674 | if (status == ~(u32) 0) { | |
675 | ehci_dbg (ehci, "device removed\n"); | |
676 | goto dead; | |
677 | } | |
678 | ||
679 | status &= INTR_MASK; | |
680 | if (!status) { /* irq sharing? */ | |
681 | spin_unlock(&ehci->lock); | |
682 | return IRQ_NONE; | |
683 | } | |
684 | ||
685 | /* clear (just) interrupts */ | |
083522d7 BH |
686 | ehci_writel(ehci, status, &ehci->regs->status); |
687 | ehci_readl(ehci, &ehci->regs->command); /* unblock posted write */ | |
1da177e4 LT |
688 | bh = 0; |
689 | ||
690 | #ifdef EHCI_VERBOSE_DEBUG | |
691 | /* unrequested/ignored: Frame List Rollover */ | |
692 | dbg_status (ehci, "irq", status); | |
693 | #endif | |
694 | ||
695 | /* INT, ERR, and IAA interrupt rates can be throttled */ | |
696 | ||
697 | /* normal [4.15.1.2] or error [4.15.1.1] completion */ | |
698 | if (likely ((status & (STS_INT|STS_ERR)) != 0)) { | |
699 | if (likely ((status & STS_ERR) == 0)) | |
700 | COUNT (ehci->stats.normal); | |
701 | else | |
702 | COUNT (ehci->stats.error); | |
703 | bh = 1; | |
704 | } | |
705 | ||
706 | /* complete the unlinking of some qh [4.15.2.3] */ | |
707 | if (status & STS_IAA) { | |
708 | COUNT (ehci->stats.reclaim); | |
64f89798 | 709 | ehci->reclaim_ready = 1; |
1da177e4 LT |
710 | bh = 1; |
711 | } | |
712 | ||
713 | /* remote wakeup [4.3.1] */ | |
d97cc2f2 | 714 | if (status & STS_PCD) { |
1da177e4 | 715 | unsigned i = HCS_N_PORTS (ehci->hcs_params); |
1d619f12 | 716 | pcd_status = status; |
1da177e4 LT |
717 | |
718 | /* resume root hub? */ | |
083522d7 | 719 | if (!(ehci_readl(ehci, &ehci->regs->command) & CMD_RUN)) |
8c03356a | 720 | usb_hcd_resume_root_hub(hcd); |
1da177e4 LT |
721 | |
722 | while (i--) { | |
083522d7 BH |
723 | int pstatus = ehci_readl(ehci, |
724 | &ehci->regs->port_status [i]); | |
b972b68c DB |
725 | |
726 | if (pstatus & PORT_OWNER) | |
1da177e4 | 727 | continue; |
b972b68c | 728 | if (!(pstatus & PORT_RESUME) |
1da177e4 LT |
729 | || ehci->reset_done [i] != 0) |
730 | continue; | |
731 | ||
732 | /* start 20 msec resume signaling from this port, | |
733 | * and make khubd collect PORT_STAT_C_SUSPEND to | |
734 | * stop that signaling. | |
735 | */ | |
736 | ehci->reset_done [i] = jiffies + msecs_to_jiffies (20); | |
1da177e4 | 737 | ehci_dbg (ehci, "port %d remote wakeup\n", i + 1); |
61e8b858 | 738 | mod_timer(&hcd->rh_timer, ehci->reset_done[i]); |
1da177e4 LT |
739 | } |
740 | } | |
741 | ||
742 | /* PCI errors [4.15.2.4] */ | |
743 | if (unlikely ((status & STS_FATAL) != 0)) { | |
744 | /* bogus "fatal" IRQs appear on some chips... why? */ | |
083522d7 BH |
745 | status = ehci_readl(ehci, &ehci->regs->status); |
746 | dbg_cmd (ehci, "fatal", ehci_readl(ehci, | |
747 | &ehci->regs->command)); | |
1da177e4 LT |
748 | dbg_status (ehci, "fatal", status); |
749 | if (status & STS_HALT) { | |
750 | ehci_err (ehci, "fatal error\n"); | |
751 | dead: | |
752 | ehci_reset (ehci); | |
083522d7 | 753 | ehci_writel(ehci, 0, &ehci->regs->configured_flag); |
1da177e4 LT |
754 | /* generic layer kills/unlinks all urbs, then |
755 | * uses ehci_stop to clean up the rest | |
756 | */ | |
757 | bh = 1; | |
758 | } | |
759 | } | |
760 | ||
761 | if (bh) | |
7d12e780 | 762 | ehci_work (ehci); |
1da177e4 | 763 | spin_unlock (&ehci->lock); |
1d619f12 MT |
764 | if (pcd_status & STS_PCD) |
765 | usb_hcd_poll_rh_status(hcd); | |
1da177e4 LT |
766 | return IRQ_HANDLED; |
767 | } | |
768 | ||
769 | /*-------------------------------------------------------------------------*/ | |
770 | ||
771 | /* | |
772 | * non-error returns are a promise to giveback() the urb later | |
773 | * we drop ownership so next owner (or urb unlink) can get it | |
774 | * | |
775 | * urb + dev is in hcd.self.controller.urb_list | |
776 | * we're queueing TDs onto software and hardware lists | |
777 | * | |
778 | * hcd-specific init for hcpriv hasn't been done yet | |
779 | * | |
780 | * NOTE: control, bulk, and interrupt share the same code to append TDs | |
781 | * to a (possibly active) QH, and the same QH scanning code. | |
782 | */ | |
783 | static int ehci_urb_enqueue ( | |
784 | struct usb_hcd *hcd, | |
785 | struct usb_host_endpoint *ep, | |
786 | struct urb *urb, | |
55016f10 | 787 | gfp_t mem_flags |
1da177e4 LT |
788 | ) { |
789 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
790 | struct list_head qtd_list; | |
791 | ||
792 | INIT_LIST_HEAD (&qtd_list); | |
793 | ||
794 | switch (usb_pipetype (urb->pipe)) { | |
795 | // case PIPE_CONTROL: | |
796 | // case PIPE_BULK: | |
797 | default: | |
798 | if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags)) | |
799 | return -ENOMEM; | |
800 | return submit_async (ehci, ep, urb, &qtd_list, mem_flags); | |
801 | ||
802 | case PIPE_INTERRUPT: | |
803 | if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags)) | |
804 | return -ENOMEM; | |
805 | return intr_submit (ehci, ep, urb, &qtd_list, mem_flags); | |
806 | ||
807 | case PIPE_ISOCHRONOUS: | |
808 | if (urb->dev->speed == USB_SPEED_HIGH) | |
809 | return itd_submit (ehci, urb, mem_flags); | |
810 | else | |
811 | return sitd_submit (ehci, urb, mem_flags); | |
812 | } | |
813 | } | |
814 | ||
815 | static void unlink_async (struct ehci_hcd *ehci, struct ehci_qh *qh) | |
816 | { | |
64f89798 GKH |
817 | /* if we need to use IAA and it's busy, defer */ |
818 | if (qh->qh_state == QH_STATE_LINKED | |
819 | && ehci->reclaim | |
820 | && HC_IS_RUNNING (ehci_to_hcd(ehci)->state)) { | |
1da177e4 LT |
821 | struct ehci_qh *last; |
822 | ||
823 | for (last = ehci->reclaim; | |
824 | last->reclaim; | |
825 | last = last->reclaim) | |
826 | continue; | |
827 | qh->qh_state = QH_STATE_UNLINK_WAIT; | |
828 | last->reclaim = qh; | |
829 | ||
64f89798 GKH |
830 | /* bypass IAA if the hc can't care */ |
831 | } else if (!HC_IS_RUNNING (ehci_to_hcd(ehci)->state) && ehci->reclaim) | |
832 | end_unlink_async (ehci); | |
833 | ||
834 | /* something else might have unlinked the qh by now */ | |
835 | if (qh->qh_state == QH_STATE_LINKED) | |
1da177e4 LT |
836 | start_unlink_async (ehci, qh); |
837 | } | |
838 | ||
839 | /* remove from hardware lists | |
840 | * completions normally happen asynchronously | |
841 | */ | |
842 | ||
843 | static int ehci_urb_dequeue (struct usb_hcd *hcd, struct urb *urb) | |
844 | { | |
845 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
846 | struct ehci_qh *qh; | |
847 | unsigned long flags; | |
848 | ||
849 | spin_lock_irqsave (&ehci->lock, flags); | |
850 | switch (usb_pipetype (urb->pipe)) { | |
851 | // case PIPE_CONTROL: | |
852 | // case PIPE_BULK: | |
853 | default: | |
854 | qh = (struct ehci_qh *) urb->hcpriv; | |
855 | if (!qh) | |
856 | break; | |
64f89798 | 857 | unlink_async (ehci, qh); |
1da177e4 LT |
858 | break; |
859 | ||
860 | case PIPE_INTERRUPT: | |
861 | qh = (struct ehci_qh *) urb->hcpriv; | |
862 | if (!qh) | |
863 | break; | |
864 | switch (qh->qh_state) { | |
865 | case QH_STATE_LINKED: | |
866 | intr_deschedule (ehci, qh); | |
867 | /* FALL THROUGH */ | |
868 | case QH_STATE_IDLE: | |
7d12e780 | 869 | qh_completions (ehci, qh); |
1da177e4 LT |
870 | break; |
871 | default: | |
872 | ehci_dbg (ehci, "bogus qh %p state %d\n", | |
873 | qh, qh->qh_state); | |
874 | goto done; | |
875 | } | |
876 | ||
877 | /* reschedule QH iff another request is queued */ | |
878 | if (!list_empty (&qh->qtd_list) | |
879 | && HC_IS_RUNNING (hcd->state)) { | |
880 | int status; | |
881 | ||
882 | status = qh_schedule (ehci, qh); | |
883 | spin_unlock_irqrestore (&ehci->lock, flags); | |
884 | ||
885 | if (status != 0) { | |
886 | // shouldn't happen often, but ... | |
887 | // FIXME kill those tds' urbs | |
888 | err ("can't reschedule qh %p, err %d", | |
889 | qh, status); | |
890 | } | |
891 | return status; | |
892 | } | |
893 | break; | |
894 | ||
895 | case PIPE_ISOCHRONOUS: | |
896 | // itd or sitd ... | |
897 | ||
898 | // wait till next completion, do it then. | |
899 | // completion irqs can wait up to 1024 msec, | |
900 | break; | |
901 | } | |
902 | done: | |
903 | spin_unlock_irqrestore (&ehci->lock, flags); | |
904 | return 0; | |
905 | } | |
906 | ||
907 | /*-------------------------------------------------------------------------*/ | |
908 | ||
909 | // bulk qh holds the data toggle | |
910 | ||
911 | static void | |
912 | ehci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep) | |
913 | { | |
914 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
915 | unsigned long flags; | |
916 | struct ehci_qh *qh, *tmp; | |
917 | ||
918 | /* ASSERT: any requests/urbs are being unlinked */ | |
919 | /* ASSERT: nobody can be submitting urbs for this any more */ | |
920 | ||
921 | rescan: | |
922 | spin_lock_irqsave (&ehci->lock, flags); | |
923 | qh = ep->hcpriv; | |
924 | if (!qh) | |
925 | goto done; | |
926 | ||
927 | /* endpoints can be iso streams. for now, we don't | |
928 | * accelerate iso completions ... so spin a while. | |
929 | */ | |
930 | if (qh->hw_info1 == 0) { | |
931 | ehci_vdbg (ehci, "iso delay\n"); | |
932 | goto idle_timeout; | |
933 | } | |
934 | ||
935 | if (!HC_IS_RUNNING (hcd->state)) | |
936 | qh->qh_state = QH_STATE_IDLE; | |
937 | switch (qh->qh_state) { | |
938 | case QH_STATE_LINKED: | |
939 | for (tmp = ehci->async->qh_next.qh; | |
940 | tmp && tmp != qh; | |
941 | tmp = tmp->qh_next.qh) | |
942 | continue; | |
943 | /* periodic qh self-unlinks on empty */ | |
944 | if (!tmp) | |
945 | goto nogood; | |
946 | unlink_async (ehci, qh); | |
947 | /* FALL THROUGH */ | |
948 | case QH_STATE_UNLINK: /* wait for hw to finish? */ | |
949 | idle_timeout: | |
950 | spin_unlock_irqrestore (&ehci->lock, flags); | |
22c43863 | 951 | schedule_timeout_uninterruptible(1); |
1da177e4 LT |
952 | goto rescan; |
953 | case QH_STATE_IDLE: /* fully unlinked */ | |
954 | if (list_empty (&qh->qtd_list)) { | |
955 | qh_put (qh); | |
956 | break; | |
957 | } | |
958 | /* else FALL THROUGH */ | |
959 | default: | |
960 | nogood: | |
961 | /* caller was supposed to have unlinked any requests; | |
962 | * that's not our job. just leak this memory. | |
963 | */ | |
964 | ehci_err (ehci, "qh %p (#%02x) state %d%s\n", | |
965 | qh, ep->desc.bEndpointAddress, qh->qh_state, | |
966 | list_empty (&qh->qtd_list) ? "" : "(has tds)"); | |
967 | break; | |
968 | } | |
969 | ep->hcpriv = NULL; | |
970 | done: | |
971 | spin_unlock_irqrestore (&ehci->lock, flags); | |
972 | return; | |
973 | } | |
974 | ||
7ff71d6a MP |
975 | static int ehci_get_frame (struct usb_hcd *hcd) |
976 | { | |
977 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
083522d7 BH |
978 | return (ehci_readl(ehci, &ehci->regs->frame_index) >> 3) % |
979 | ehci->periodic_size; | |
7ff71d6a | 980 | } |
1da177e4 LT |
981 | |
982 | /*-------------------------------------------------------------------------*/ | |
983 | ||
1da177e4 LT |
984 | #define DRIVER_INFO DRIVER_VERSION " " DRIVER_DESC |
985 | ||
986 | MODULE_DESCRIPTION (DRIVER_INFO); | |
987 | MODULE_AUTHOR (DRIVER_AUTHOR); | |
988 | MODULE_LICENSE ("GPL"); | |
989 | ||
7ff71d6a MP |
990 | #ifdef CONFIG_PCI |
991 | #include "ehci-pci.c" | |
01cced25 | 992 | #define PCI_DRIVER ehci_pci_driver |
7ff71d6a | 993 | #endif |
1da177e4 | 994 | |
a11570f2 | 995 | #ifdef CONFIG_MPC834x |
80cb9aee | 996 | #include "ehci-fsl.c" |
01cced25 | 997 | #define PLATFORM_DRIVER ehci_fsl_driver |
80cb9aee RV |
998 | #endif |
999 | ||
dfbaa7d8 | 1000 | #ifdef CONFIG_SOC_AU1200 |
76fa9a24 | 1001 | #include "ehci-au1xxx.c" |
01cced25 | 1002 | #define PLATFORM_DRIVER ehci_hcd_au1xxx_driver |
76fa9a24 JC |
1003 | #endif |
1004 | ||
ad75a410 GL |
1005 | #ifdef CONFIG_PPC_PS3 |
1006 | #include "ehci-ps3.c" | |
1007 | #define PS3_SYSTEM_BUS_DRIVER ps3_ehci_sb_driver | |
1008 | #endif | |
1009 | ||
1010 | #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \ | |
1011 | !defined(PS3_SYSTEM_BUS_DRIVER) | |
7ff71d6a MP |
1012 | #error "missing bus glue for ehci-hcd" |
1013 | #endif | |
01cced25 KG |
1014 | |
1015 | static int __init ehci_hcd_init(void) | |
1016 | { | |
1017 | int retval = 0; | |
1018 | ||
1019 | pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n", | |
1020 | hcd_name, | |
1021 | sizeof(struct ehci_qh), sizeof(struct ehci_qtd), | |
1022 | sizeof(struct ehci_itd), sizeof(struct ehci_sitd)); | |
1023 | ||
1024 | #ifdef PLATFORM_DRIVER | |
1025 | retval = platform_driver_register(&PLATFORM_DRIVER); | |
1026 | if (retval < 0) | |
1027 | return retval; | |
1028 | #endif | |
1029 | ||
1030 | #ifdef PCI_DRIVER | |
1031 | retval = pci_register_driver(&PCI_DRIVER); | |
1032 | if (retval < 0) { | |
1033 | #ifdef PLATFORM_DRIVER | |
1034 | platform_driver_unregister(&PLATFORM_DRIVER); | |
1035 | #endif | |
ad75a410 GL |
1036 | return retval; |
1037 | } | |
1038 | #endif | |
1039 | ||
1040 | #ifdef PS3_SYSTEM_BUS_DRIVER | |
48fda451 IK |
1041 | if (firmware_has_feature(FW_FEATURE_PS3_LV1)) { |
1042 | retval = ps3_system_bus_driver_register( | |
1043 | &PS3_SYSTEM_BUS_DRIVER); | |
1044 | if (retval < 0) { | |
ad75a410 | 1045 | #ifdef PLATFORM_DRIVER |
48fda451 | 1046 | platform_driver_unregister(&PLATFORM_DRIVER); |
ad75a410 GL |
1047 | #endif |
1048 | #ifdef PCI_DRIVER | |
48fda451 | 1049 | pci_unregister_driver(&PCI_DRIVER); |
ad75a410 | 1050 | #endif |
48fda451 IK |
1051 | return retval; |
1052 | } | |
01cced25 KG |
1053 | } |
1054 | #endif | |
1055 | ||
1056 | return retval; | |
1057 | } | |
1058 | module_init(ehci_hcd_init); | |
1059 | ||
1060 | static void __exit ehci_hcd_cleanup(void) | |
1061 | { | |
1062 | #ifdef PLATFORM_DRIVER | |
1063 | platform_driver_unregister(&PLATFORM_DRIVER); | |
1064 | #endif | |
1065 | #ifdef PCI_DRIVER | |
1066 | pci_unregister_driver(&PCI_DRIVER); | |
1067 | #endif | |
ad75a410 | 1068 | #ifdef PS3_SYSTEM_BUS_DRIVER |
48fda451 IK |
1069 | if (firmware_has_feature(FW_FEATURE_PS3_LV1)) |
1070 | ps3_system_bus_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); | |
ad75a410 | 1071 | #endif |
01cced25 KG |
1072 | } |
1073 | module_exit(ehci_hcd_cleanup); | |
1074 |