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1da177e4 LT |
1 | /* |
2 | * Copyright (c) 2000-2004 by David Brownell | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms of the GNU General Public License as published by the | |
6 | * Free Software Foundation; either version 2 of the License, or (at your | |
7 | * option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but | |
10 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
11 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 | * for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software Foundation, | |
16 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
17 | */ | |
18 | ||
19 | #include <linux/config.h> | |
20 | ||
21 | #ifdef CONFIG_USB_DEBUG | |
22 | #define DEBUG | |
23 | #else | |
24 | #undef DEBUG | |
25 | #endif | |
26 | ||
27 | #include <linux/module.h> | |
28 | #include <linux/pci.h> | |
29 | #include <linux/dmapool.h> | |
30 | #include <linux/kernel.h> | |
31 | #include <linux/delay.h> | |
32 | #include <linux/ioport.h> | |
33 | #include <linux/sched.h> | |
34 | #include <linux/slab.h> | |
35 | #include <linux/smp_lock.h> | |
36 | #include <linux/errno.h> | |
37 | #include <linux/init.h> | |
38 | #include <linux/timer.h> | |
39 | #include <linux/list.h> | |
40 | #include <linux/interrupt.h> | |
41 | #include <linux/reboot.h> | |
42 | #include <linux/usb.h> | |
43 | #include <linux/moduleparam.h> | |
44 | #include <linux/dma-mapping.h> | |
45 | ||
46 | #include "../core/hcd.h" | |
47 | ||
48 | #include <asm/byteorder.h> | |
49 | #include <asm/io.h> | |
50 | #include <asm/irq.h> | |
51 | #include <asm/system.h> | |
52 | #include <asm/unaligned.h> | |
53 | ||
54 | ||
55 | /*-------------------------------------------------------------------------*/ | |
56 | ||
57 | /* | |
58 | * EHCI hc_driver implementation ... experimental, incomplete. | |
59 | * Based on the final 1.0 register interface specification. | |
60 | * | |
61 | * USB 2.0 shows up in upcoming www.pcmcia.org technology. | |
62 | * First was PCMCIA, like ISA; then CardBus, which is PCI. | |
63 | * Next comes "CardBay", using USB 2.0 signals. | |
64 | * | |
65 | * Contains additional contributions by Brad Hards, Rory Bolt, and others. | |
66 | * Special thanks to Intel and VIA for providing host controllers to | |
67 | * test this driver on, and Cypress (including In-System Design) for | |
68 | * providing early devices for those host controllers to talk to! | |
69 | * | |
70 | * HISTORY: | |
71 | * | |
72 | * 2004-05-10 Root hub and PCI suspend/resume support; remote wakeup. (db) | |
73 | * 2004-02-24 Replace pci_* with generic dma_* API calls (dsaxena@plexity.net) | |
74 | * 2003-12-29 Rewritten high speed iso transfer support (by Michal Sojka, | |
75 | * <sojkam@centrum.cz>, updates by DB). | |
76 | * | |
77 | * 2002-11-29 Correct handling for hw async_next register. | |
78 | * 2002-08-06 Handling for bulk and interrupt transfers is mostly shared; | |
79 | * only scheduling is different, no arbitrary limitations. | |
80 | * 2002-07-25 Sanity check PCI reads, mostly for better cardbus support, | |
81 | * clean up HC run state handshaking. | |
82 | * 2002-05-24 Preliminary FS/LS interrupts, using scheduling shortcuts | |
83 | * 2002-05-11 Clear TT errors for FS/LS ctrl/bulk. Fill in some other | |
84 | * missing pieces: enabling 64bit dma, handoff from BIOS/SMM. | |
85 | * 2002-05-07 Some error path cleanups to report better errors; wmb(); | |
86 | * use non-CVS version id; better iso bandwidth claim. | |
87 | * 2002-04-19 Control/bulk/interrupt submit no longer uses giveback() on | |
88 | * errors in submit path. Bugfixes to interrupt scheduling/processing. | |
89 | * 2002-03-05 Initial high-speed ISO support; reduce ITD memory; shift | |
90 | * more checking to generic hcd framework (db). Make it work with | |
91 | * Philips EHCI; reduce PCI traffic; shorten IRQ path (Rory Bolt). | |
92 | * 2002-01-14 Minor cleanup; version synch. | |
93 | * 2002-01-08 Fix roothub handoff of FS/LS to companion controllers. | |
94 | * 2002-01-04 Control/Bulk queuing behaves. | |
95 | * | |
96 | * 2001-12-12 Initial patch version for Linux 2.5.1 kernel. | |
97 | * 2001-June Works with usb-storage and NEC EHCI on 2.4 | |
98 | */ | |
99 | ||
100 | #define DRIVER_VERSION "10 Dec 2004" | |
101 | #define DRIVER_AUTHOR "David Brownell" | |
102 | #define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver" | |
103 | ||
104 | static const char hcd_name [] = "ehci_hcd"; | |
105 | ||
106 | ||
107 | #undef EHCI_VERBOSE_DEBUG | |
108 | #undef EHCI_URB_TRACE | |
109 | ||
110 | #ifdef DEBUG | |
111 | #define EHCI_STATS | |
112 | #endif | |
113 | ||
114 | /* magic numbers that can affect system performance */ | |
115 | #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */ | |
116 | #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */ | |
117 | #define EHCI_TUNE_RL_TT 0 | |
118 | #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */ | |
119 | #define EHCI_TUNE_MULT_TT 1 | |
120 | #define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */ | |
121 | ||
122 | #define EHCI_IAA_JIFFIES (HZ/100) /* arbitrary; ~10 msec */ | |
123 | #define EHCI_IO_JIFFIES (HZ/10) /* io watchdog > irq_thresh */ | |
124 | #define EHCI_ASYNC_JIFFIES (HZ/20) /* async idle timeout */ | |
125 | #define EHCI_SHRINK_JIFFIES (HZ/200) /* async qh unlink delay */ | |
126 | ||
127 | /* Initial IRQ latency: faster than hw default */ | |
128 | static int log2_irq_thresh = 0; // 0 to 6 | |
129 | module_param (log2_irq_thresh, int, S_IRUGO); | |
130 | MODULE_PARM_DESC (log2_irq_thresh, "log2 IRQ latency, 1-64 microframes"); | |
131 | ||
132 | /* initial park setting: slower than hw default */ | |
133 | static unsigned park = 0; | |
134 | module_param (park, uint, S_IRUGO); | |
135 | MODULE_PARM_DESC (park, "park setting; 1-3 back-to-back async packets"); | |
136 | ||
137 | #define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT) | |
138 | ||
139 | /*-------------------------------------------------------------------------*/ | |
140 | ||
141 | #include "ehci.h" | |
142 | #include "ehci-dbg.c" | |
143 | ||
144 | /*-------------------------------------------------------------------------*/ | |
145 | ||
146 | /* | |
147 | * handshake - spin reading hc until handshake completes or fails | |
148 | * @ptr: address of hc register to be read | |
149 | * @mask: bits to look at in result of read | |
150 | * @done: value of those bits when handshake succeeds | |
151 | * @usec: timeout in microseconds | |
152 | * | |
153 | * Returns negative errno, or zero on success | |
154 | * | |
155 | * Success happens when the "mask" bits have the specified value (hardware | |
156 | * handshake done). There are two failure modes: "usec" have passed (major | |
157 | * hardware flakeout), or the register reads as all-ones (hardware removed). | |
158 | * | |
159 | * That last failure should_only happen in cases like physical cardbus eject | |
160 | * before driver shutdown. But it also seems to be caused by bugs in cardbus | |
161 | * bridge shutdown: shutting down the bridge before the devices using it. | |
162 | */ | |
163 | static int handshake (void __iomem *ptr, u32 mask, u32 done, int usec) | |
164 | { | |
165 | u32 result; | |
166 | ||
167 | do { | |
168 | result = readl (ptr); | |
169 | if (result == ~(u32)0) /* card removed */ | |
170 | return -ENODEV; | |
171 | result &= mask; | |
172 | if (result == done) | |
173 | return 0; | |
174 | udelay (1); | |
175 | usec--; | |
176 | } while (usec > 0); | |
177 | return -ETIMEDOUT; | |
178 | } | |
179 | ||
180 | /* force HC to halt state from unknown (EHCI spec section 2.3) */ | |
181 | static int ehci_halt (struct ehci_hcd *ehci) | |
182 | { | |
183 | u32 temp = readl (&ehci->regs->status); | |
184 | ||
185 | if ((temp & STS_HALT) != 0) | |
186 | return 0; | |
187 | ||
188 | temp = readl (&ehci->regs->command); | |
189 | temp &= ~CMD_RUN; | |
190 | writel (temp, &ehci->regs->command); | |
191 | return handshake (&ehci->regs->status, STS_HALT, STS_HALT, 16 * 125); | |
192 | } | |
193 | ||
194 | /* put TDI/ARC silicon into EHCI mode */ | |
195 | static void tdi_reset (struct ehci_hcd *ehci) | |
196 | { | |
197 | u32 __iomem *reg_ptr; | |
198 | u32 tmp; | |
199 | ||
200 | reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + 0x68); | |
201 | tmp = readl (reg_ptr); | |
202 | tmp |= 0x3; | |
203 | writel (tmp, reg_ptr); | |
204 | } | |
205 | ||
206 | /* reset a non-running (STS_HALT == 1) controller */ | |
207 | static int ehci_reset (struct ehci_hcd *ehci) | |
208 | { | |
209 | int retval; | |
210 | u32 command = readl (&ehci->regs->command); | |
211 | ||
212 | command |= CMD_RESET; | |
213 | dbg_cmd (ehci, "reset", command); | |
214 | writel (command, &ehci->regs->command); | |
215 | ehci_to_hcd(ehci)->state = HC_STATE_HALT; | |
216 | ehci->next_statechange = jiffies; | |
217 | retval = handshake (&ehci->regs->command, CMD_RESET, 0, 250 * 1000); | |
218 | ||
219 | if (retval) | |
220 | return retval; | |
221 | ||
222 | if (ehci_is_TDI(ehci)) | |
223 | tdi_reset (ehci); | |
224 | ||
225 | return retval; | |
226 | } | |
227 | ||
228 | /* idle the controller (from running) */ | |
229 | static void ehci_quiesce (struct ehci_hcd *ehci) | |
230 | { | |
231 | u32 temp; | |
232 | ||
233 | #ifdef DEBUG | |
234 | if (!HC_IS_RUNNING (ehci_to_hcd(ehci)->state)) | |
235 | BUG (); | |
236 | #endif | |
237 | ||
238 | /* wait for any schedule enables/disables to take effect */ | |
239 | temp = readl (&ehci->regs->command) << 10; | |
240 | temp &= STS_ASS | STS_PSS; | |
241 | if (handshake (&ehci->regs->status, STS_ASS | STS_PSS, | |
242 | temp, 16 * 125) != 0) { | |
243 | ehci_to_hcd(ehci)->state = HC_STATE_HALT; | |
244 | return; | |
245 | } | |
246 | ||
247 | /* then disable anything that's still active */ | |
248 | temp = readl (&ehci->regs->command); | |
249 | temp &= ~(CMD_ASE | CMD_IAAD | CMD_PSE); | |
250 | writel (temp, &ehci->regs->command); | |
251 | ||
252 | /* hardware can take 16 microframes to turn off ... */ | |
253 | if (handshake (&ehci->regs->status, STS_ASS | STS_PSS, | |
254 | 0, 16 * 125) != 0) { | |
255 | ehci_to_hcd(ehci)->state = HC_STATE_HALT; | |
256 | return; | |
257 | } | |
258 | } | |
259 | ||
260 | /*-------------------------------------------------------------------------*/ | |
261 | ||
262 | static void ehci_work(struct ehci_hcd *ehci, struct pt_regs *regs); | |
263 | ||
264 | #include "ehci-hub.c" | |
265 | #include "ehci-mem.c" | |
266 | #include "ehci-q.c" | |
267 | #include "ehci-sched.c" | |
268 | ||
269 | /*-------------------------------------------------------------------------*/ | |
270 | ||
271 | static void ehci_watchdog (unsigned long param) | |
272 | { | |
273 | struct ehci_hcd *ehci = (struct ehci_hcd *) param; | |
274 | unsigned long flags; | |
275 | ||
276 | spin_lock_irqsave (&ehci->lock, flags); | |
277 | ||
278 | /* lost IAA irqs wedge things badly; seen with a vt8235 */ | |
279 | if (ehci->reclaim) { | |
280 | u32 status = readl (&ehci->regs->status); | |
281 | ||
282 | if (status & STS_IAA) { | |
283 | ehci_vdbg (ehci, "lost IAA\n"); | |
284 | COUNT (ehci->stats.lost_iaa); | |
285 | writel (STS_IAA, &ehci->regs->status); | |
286 | ehci->reclaim_ready = 1; | |
287 | } | |
288 | } | |
289 | ||
290 | /* stop async processing after it's idled a bit */ | |
291 | if (test_bit (TIMER_ASYNC_OFF, &ehci->actions)) | |
292 | start_unlink_async (ehci, ehci->async); | |
293 | ||
294 | /* ehci could run by timer, without IRQs ... */ | |
295 | ehci_work (ehci, NULL); | |
296 | ||
297 | spin_unlock_irqrestore (&ehci->lock, flags); | |
298 | } | |
299 | ||
300 | #ifdef CONFIG_PCI | |
301 | ||
302 | /* EHCI 0.96 (and later) section 5.1 says how to kick BIOS/SMM/... | |
303 | * off the controller (maybe it can boot from highspeed USB disks). | |
304 | */ | |
305 | static int bios_handoff (struct ehci_hcd *ehci, int where, u32 cap) | |
306 | { | |
d49d4317 DB |
307 | struct pci_dev *pdev = to_pci_dev(ehci_to_hcd(ehci)->self.controller); |
308 | ||
309 | /* always say Linux will own the hardware */ | |
310 | pci_write_config_byte(pdev, where + 3, 1); | |
311 | ||
312 | /* maybe wait a while for BIOS to respond */ | |
1da177e4 LT |
313 | if (cap & (1 << 16)) { |
314 | int msec = 5000; | |
1da177e4 | 315 | |
1da177e4 LT |
316 | do { |
317 | msleep(10); | |
318 | msec -= 10; | |
319 | pci_read_config_dword(pdev, where, &cap); | |
320 | } while ((cap & (1 << 16)) && msec); | |
321 | if (cap & (1 << 16)) { | |
d49d4317 | 322 | ehci_err(ehci, "BIOS handoff failed (%d, %08x)\n", |
1da177e4 LT |
323 | where, cap); |
324 | // some BIOS versions seem buggy... | |
325 | // return 1; | |
326 | ehci_warn (ehci, "continuing after BIOS bug...\n"); | |
d49d4317 DB |
327 | /* disable all SMIs, and clear "BIOS owns" flag */ |
328 | pci_write_config_dword(pdev, where + 4, 0); | |
329 | pci_write_config_byte(pdev, where + 2, 0); | |
330 | } else | |
331 | ehci_dbg(ehci, "BIOS handoff succeeded\n"); | |
1da177e4 LT |
332 | } |
333 | return 0; | |
334 | } | |
335 | ||
336 | #endif | |
337 | ||
338 | static int | |
339 | ehci_reboot (struct notifier_block *self, unsigned long code, void *null) | |
340 | { | |
341 | struct ehci_hcd *ehci; | |
342 | ||
343 | ehci = container_of (self, struct ehci_hcd, reboot_notifier); | |
344 | ||
345 | /* make BIOS/etc use companion controller during reboot */ | |
346 | writel (0, &ehci->regs->configured_flag); | |
347 | return 0; | |
348 | } | |
349 | ||
56c1e26d DB |
350 | static void ehci_port_power (struct ehci_hcd *ehci, int is_on) |
351 | { | |
352 | unsigned port; | |
353 | ||
354 | if (!HCS_PPC (ehci->hcs_params)) | |
355 | return; | |
356 | ||
357 | ehci_dbg (ehci, "...power%s ports...\n", is_on ? "up" : "down"); | |
358 | for (port = HCS_N_PORTS (ehci->hcs_params); port > 0; ) | |
359 | (void) ehci_hub_control(ehci_to_hcd(ehci), | |
360 | is_on ? SetPortFeature : ClearPortFeature, | |
361 | USB_PORT_FEAT_POWER, | |
362 | port--, NULL, 0); | |
363 | msleep(20); | |
364 | } | |
365 | ||
1da177e4 LT |
366 | |
367 | /* called by khubd or root hub init threads */ | |
368 | ||
369 | static int ehci_hc_reset (struct usb_hcd *hcd) | |
370 | { | |
371 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
372 | u32 temp; | |
373 | unsigned count = 256/4; | |
374 | ||
375 | spin_lock_init (&ehci->lock); | |
376 | ||
377 | ehci->caps = hcd->regs; | |
378 | ehci->regs = hcd->regs + HC_LENGTH (readl (&ehci->caps->hc_capbase)); | |
379 | dbg_hcs_params (ehci, "reset"); | |
380 | dbg_hcc_params (ehci, "reset"); | |
381 | ||
56c1e26d DB |
382 | /* cache this readonly data; minimize chip reads */ |
383 | ehci->hcs_params = readl (&ehci->caps->hcs_params); | |
384 | ||
1da177e4 | 385 | #ifdef CONFIG_PCI |
1da177e4 LT |
386 | if (hcd->self.controller->bus == &pci_bus_type) { |
387 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); | |
388 | ||
389 | switch (pdev->vendor) { | |
390 | case PCI_VENDOR_ID_TDI: | |
391 | if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) { | |
392 | ehci->is_tdi_rh_tt = 1; | |
393 | tdi_reset (ehci); | |
394 | } | |
395 | break; | |
396 | case PCI_VENDOR_ID_AMD: | |
397 | /* AMD8111 EHCI doesn't work, according to AMD errata */ | |
398 | if (pdev->device == 0x7463) { | |
399 | ehci_info (ehci, "ignoring AMD8111 (errata)\n"); | |
400 | return -EIO; | |
401 | } | |
402 | break; | |
403 | } | |
404 | ||
56c1e26d DB |
405 | /* optional debug port, normally in the first BAR */ |
406 | temp = pci_find_capability (pdev, 0x0a); | |
407 | if (temp) { | |
408 | pci_read_config_dword(pdev, temp, &temp); | |
409 | temp >>= 16; | |
410 | if ((temp & (3 << 13)) == (1 << 13)) { | |
411 | temp &= 0x1fff; | |
412 | ehci->debug = hcd->regs + temp; | |
413 | temp = readl (&ehci->debug->control); | |
414 | ehci_info (ehci, "debug port %d%s\n", | |
415 | HCS_DEBUG_PORT(ehci->hcs_params), | |
416 | (temp & DBGP_ENABLED) | |
417 | ? " IN USE" | |
418 | : ""); | |
419 | if (!(temp & DBGP_ENABLED)) | |
420 | ehci->debug = NULL; | |
421 | } | |
422 | } | |
423 | ||
1da177e4 LT |
424 | temp = HCC_EXT_CAPS (readl (&ehci->caps->hcc_params)); |
425 | } else | |
426 | temp = 0; | |
56c1e26d DB |
427 | |
428 | /* EHCI 0.96 and later may have "extended capabilities" */ | |
1da177e4 LT |
429 | while (temp && count--) { |
430 | u32 cap; | |
431 | ||
432 | pci_read_config_dword (to_pci_dev(hcd->self.controller), | |
433 | temp, &cap); | |
434 | ehci_dbg (ehci, "capability %04x at %02x\n", cap, temp); | |
435 | switch (cap & 0xff) { | |
436 | case 1: /* BIOS/SMM/... handoff */ | |
437 | if (bios_handoff (ehci, temp, cap) != 0) | |
438 | return -EOPNOTSUPP; | |
439 | break; | |
440 | case 0: /* illegal reserved capability */ | |
441 | ehci_warn (ehci, "illegal capability!\n"); | |
442 | cap = 0; | |
443 | /* FALLTHROUGH */ | |
444 | default: /* unknown */ | |
445 | break; | |
446 | } | |
447 | temp = (cap >> 8) & 0xff; | |
448 | } | |
449 | if (!count) { | |
450 | ehci_err (ehci, "bogus capabilities ... PCI problems!\n"); | |
451 | return -EIO; | |
452 | } | |
453 | if (ehci_is_TDI(ehci)) | |
454 | ehci_reset (ehci); | |
455 | #endif | |
456 | ||
56c1e26d | 457 | ehci_port_power (ehci, 0); |
1da177e4 LT |
458 | |
459 | /* at least the Genesys GL880S needs fixup here */ | |
460 | temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params); | |
461 | temp &= 0x0f; | |
462 | if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) { | |
463 | ehci_dbg (ehci, "bogus port configuration: " | |
464 | "cc=%d x pcc=%d < ports=%d\n", | |
465 | HCS_N_CC(ehci->hcs_params), | |
466 | HCS_N_PCC(ehci->hcs_params), | |
467 | HCS_N_PORTS(ehci->hcs_params)); | |
468 | ||
469 | #ifdef CONFIG_PCI | |
470 | if (hcd->self.controller->bus == &pci_bus_type) { | |
471 | struct pci_dev *pdev; | |
472 | ||
473 | pdev = to_pci_dev(hcd->self.controller); | |
474 | switch (pdev->vendor) { | |
475 | case 0x17a0: /* GENESYS */ | |
476 | /* GL880S: should be PORTS=2 */ | |
477 | temp |= (ehci->hcs_params & ~0xf); | |
478 | ehci->hcs_params = temp; | |
479 | break; | |
480 | case PCI_VENDOR_ID_NVIDIA: | |
481 | /* NF4: should be PCC=10 */ | |
482 | break; | |
483 | } | |
484 | } | |
485 | #endif | |
486 | } | |
487 | ||
488 | /* force HC to halt state */ | |
489 | return ehci_halt (ehci); | |
490 | } | |
491 | ||
492 | static int ehci_start (struct usb_hcd *hcd) | |
493 | { | |
494 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
495 | u32 temp; | |
1da177e4 LT |
496 | int retval; |
497 | u32 hcc_params; | |
498 | u8 sbrn = 0; | |
499 | int first; | |
500 | ||
501 | /* skip some things on restart paths */ | |
502 | first = (ehci->watchdog.data == 0); | |
503 | if (first) { | |
504 | init_timer (&ehci->watchdog); | |
505 | ehci->watchdog.function = ehci_watchdog; | |
506 | ehci->watchdog.data = (unsigned long) ehci; | |
507 | } | |
508 | ||
509 | /* | |
510 | * hw default: 1K periodic list heads, one per frame. | |
511 | * periodic_size can shrink by USBCMD update if hcc_params allows. | |
512 | */ | |
513 | ehci->periodic_size = DEFAULT_I_TDPS; | |
514 | if (first && (retval = ehci_mem_init (ehci, GFP_KERNEL)) < 0) | |
515 | return retval; | |
516 | ||
517 | /* controllers may cache some of the periodic schedule ... */ | |
518 | hcc_params = readl (&ehci->caps->hcc_params); | |
519 | if (HCC_ISOC_CACHE (hcc_params)) // full frame cache | |
520 | ehci->i_thresh = 8; | |
521 | else // N microframes cached | |
522 | ehci->i_thresh = 2 + HCC_ISOC_THRES (hcc_params); | |
523 | ||
524 | ehci->reclaim = NULL; | |
525 | ehci->reclaim_ready = 0; | |
526 | ehci->next_uframe = -1; | |
527 | ||
528 | /* controller state: unknown --> reset */ | |
529 | ||
530 | /* EHCI spec section 4.1 */ | |
531 | if ((retval = ehci_reset (ehci)) != 0) { | |
532 | ehci_mem_cleanup (ehci); | |
533 | return retval; | |
534 | } | |
535 | writel (ehci->periodic_dma, &ehci->regs->frame_list); | |
536 | ||
537 | #ifdef CONFIG_PCI | |
538 | if (hcd->self.controller->bus == &pci_bus_type) { | |
539 | struct pci_dev *pdev; | |
540 | u16 port_wake; | |
541 | ||
542 | pdev = to_pci_dev(hcd->self.controller); | |
543 | ||
544 | /* Serial Bus Release Number is at PCI 0x60 offset */ | |
545 | pci_read_config_byte(pdev, 0x60, &sbrn); | |
546 | ||
547 | /* port wake capability, reported by boot firmware */ | |
548 | pci_read_config_word(pdev, 0x62, &port_wake); | |
549 | hcd->can_wakeup = (port_wake & 1) != 0; | |
550 | ||
551 | /* help hc dma work well with cachelines */ | |
552 | pci_set_mwi (pdev); | |
553 | } | |
554 | #endif | |
555 | ||
556 | /* | |
557 | * dedicate a qh for the async ring head, since we couldn't unlink | |
558 | * a 'real' qh without stopping the async schedule [4.8]. use it | |
559 | * as the 'reclamation list head' too. | |
560 | * its dummy is used in hw_alt_next of many tds, to prevent the qh | |
561 | * from automatically advancing to the next td after short reads. | |
562 | */ | |
563 | if (first) { | |
564 | ehci->async->qh_next.qh = NULL; | |
565 | ehci->async->hw_next = QH_NEXT (ehci->async->qh_dma); | |
566 | ehci->async->hw_info1 = cpu_to_le32 (QH_HEAD); | |
567 | ehci->async->hw_token = cpu_to_le32 (QTD_STS_HALT); | |
568 | ehci->async->hw_qtd_next = EHCI_LIST_END; | |
569 | ehci->async->qh_state = QH_STATE_LINKED; | |
570 | ehci->async->hw_alt_next = QTD_NEXT (ehci->async->dummy->qtd_dma); | |
571 | } | |
572 | writel ((u32)ehci->async->qh_dma, &ehci->regs->async_next); | |
573 | ||
574 | /* | |
575 | * hcc_params controls whether ehci->regs->segment must (!!!) | |
576 | * be used; it constrains QH/ITD/SITD and QTD locations. | |
577 | * pci_pool consistent memory always uses segment zero. | |
578 | * streaming mappings for I/O buffers, like pci_map_single(), | |
579 | * can return segments above 4GB, if the device allows. | |
580 | * | |
581 | * NOTE: the dma mask is visible through dma_supported(), so | |
582 | * drivers can pass this info along ... like NETIF_F_HIGHDMA, | |
583 | * Scsi_Host.highmem_io, and so forth. It's readonly to all | |
584 | * host side drivers though. | |
585 | */ | |
586 | if (HCC_64BIT_ADDR (hcc_params)) { | |
587 | writel (0, &ehci->regs->segment); | |
588 | #if 0 | |
589 | // this is deeply broken on almost all architectures | |
d49d4317 DB |
590 | if (!dma_set_mask (hcd->self.controller, DMA_64BIT_MASK)) |
591 | ehci_info (ehci, "enabled 64bit DMA\n"); | |
1da177e4 LT |
592 | #endif |
593 | } | |
594 | ||
595 | /* clear interrupt enables, set irq latency */ | |
596 | if (log2_irq_thresh < 0 || log2_irq_thresh > 6) | |
597 | log2_irq_thresh = 0; | |
598 | temp = 1 << (16 + log2_irq_thresh); | |
599 | if (HCC_CANPARK(hcc_params)) { | |
600 | /* HW default park == 3, on hardware that supports it (like | |
601 | * NVidia and ALI silicon), maximizes throughput on the async | |
602 | * schedule by avoiding QH fetches between transfers. | |
603 | * | |
604 | * With fast usb storage devices and NForce2, "park" seems to | |
605 | * make problems: throughput reduction (!), data errors... | |
606 | */ | |
607 | if (park) { | |
608 | park = min (park, (unsigned) 3); | |
609 | temp |= CMD_PARK; | |
610 | temp |= park << 8; | |
611 | } | |
612 | ehci_info (ehci, "park %d\n", park); | |
613 | } | |
614 | if (HCC_PGM_FRAMELISTLEN (hcc_params)) { | |
615 | /* periodic schedule size can be smaller than default */ | |
616 | temp &= ~(3 << 2); | |
617 | temp |= (EHCI_TUNE_FLS << 2); | |
618 | switch (EHCI_TUNE_FLS) { | |
619 | case 0: ehci->periodic_size = 1024; break; | |
620 | case 1: ehci->periodic_size = 512; break; | |
621 | case 2: ehci->periodic_size = 256; break; | |
622 | default: BUG (); | |
623 | } | |
624 | } | |
625 | // Philips, Intel, and maybe others need CMD_RUN before the | |
626 | // root hub will detect new devices (why?); NEC doesn't | |
627 | temp |= CMD_RUN; | |
628 | writel (temp, &ehci->regs->command); | |
629 | dbg_cmd (ehci, "init", temp); | |
630 | ||
631 | /* set async sleep time = 10 us ... ? */ | |
632 | ||
1da177e4 LT |
633 | /* |
634 | * Start, enabling full USB 2.0 functionality ... usb 1.1 devices | |
635 | * are explicitly handed to companion controller(s), so no TT is | |
636 | * involved with the root hub. (Except where one is integrated, | |
637 | * and there's no companion controller unless maybe for USB OTG.) | |
638 | */ | |
639 | if (first) { | |
640 | ehci->reboot_notifier.notifier_call = ehci_reboot; | |
641 | register_reboot_notifier (&ehci->reboot_notifier); | |
642 | } | |
643 | ||
644 | hcd->state = HC_STATE_RUNNING; | |
645 | writel (FLAG_CF, &ehci->regs->configured_flag); | |
646 | readl (&ehci->regs->command); /* unblock posted write */ | |
647 | ||
648 | temp = HC_VERSION(readl (&ehci->caps->hc_capbase)); | |
649 | ehci_info (ehci, | |
650 | "USB %x.%x %s, EHCI %x.%02x, driver %s\n", | |
651 | ((sbrn & 0xf0)>>4), (sbrn & 0x0f), | |
652 | first ? "initialized" : "restarted", | |
653 | temp >> 8, temp & 0xff, DRIVER_VERSION); | |
654 | ||
1da177e4 LT |
655 | writel (INTR_MASK, &ehci->regs->intr_enable); /* Turn On Interrupts */ |
656 | ||
657 | if (first) | |
658 | create_debug_files (ehci); | |
659 | ||
660 | return 0; | |
661 | } | |
662 | ||
663 | /* always called by thread; normally rmmod */ | |
664 | ||
665 | static void ehci_stop (struct usb_hcd *hcd) | |
666 | { | |
667 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
1da177e4 LT |
668 | |
669 | ehci_dbg (ehci, "stop\n"); | |
670 | ||
671 | /* Turn off port power on all root hub ports. */ | |
56c1e26d | 672 | ehci_port_power (ehci, 0); |
1da177e4 LT |
673 | |
674 | /* no more interrupts ... */ | |
675 | del_timer_sync (&ehci->watchdog); | |
676 | ||
677 | spin_lock_irq(&ehci->lock); | |
678 | if (HC_IS_RUNNING (hcd->state)) | |
679 | ehci_quiesce (ehci); | |
680 | ||
681 | ehci_reset (ehci); | |
682 | writel (0, &ehci->regs->intr_enable); | |
683 | spin_unlock_irq(&ehci->lock); | |
684 | ||
685 | /* let companion controllers work when we aren't */ | |
686 | writel (0, &ehci->regs->configured_flag); | |
687 | unregister_reboot_notifier (&ehci->reboot_notifier); | |
688 | ||
689 | remove_debug_files (ehci); | |
690 | ||
691 | /* root hub is shut down separately (first, when possible) */ | |
692 | spin_lock_irq (&ehci->lock); | |
693 | if (ehci->async) | |
694 | ehci_work (ehci, NULL); | |
695 | spin_unlock_irq (&ehci->lock); | |
696 | ehci_mem_cleanup (ehci); | |
697 | ||
698 | #ifdef EHCI_STATS | |
699 | ehci_dbg (ehci, "irq normal %ld err %ld reclaim %ld (lost %ld)\n", | |
700 | ehci->stats.normal, ehci->stats.error, ehci->stats.reclaim, | |
701 | ehci->stats.lost_iaa); | |
702 | ehci_dbg (ehci, "complete %ld unlink %ld\n", | |
703 | ehci->stats.complete, ehci->stats.unlink); | |
704 | #endif | |
705 | ||
706 | dbg_status (ehci, "ehci_stop completed", readl (&ehci->regs->status)); | |
707 | } | |
708 | ||
709 | static int ehci_get_frame (struct usb_hcd *hcd) | |
710 | { | |
711 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
712 | return (readl (&ehci->regs->frame_index) >> 3) % ehci->periodic_size; | |
713 | } | |
714 | ||
715 | /*-------------------------------------------------------------------------*/ | |
716 | ||
717 | #ifdef CONFIG_PM | |
718 | ||
719 | /* suspend/resume, section 4.3 */ | |
720 | ||
721 | /* These routines rely on the bus (pci, platform, etc) | |
722 | * to handle powerdown and wakeup, and currently also on | |
723 | * transceivers that don't need any software attention to set up | |
724 | * the right sort of wakeup. | |
725 | */ | |
726 | ||
9a5d3e98 | 727 | static int ehci_suspend (struct usb_hcd *hcd, pm_message_t message) |
1da177e4 LT |
728 | { |
729 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
730 | ||
731 | if (time_before (jiffies, ehci->next_statechange)) | |
732 | msleep (100); | |
733 | ||
734 | #ifdef CONFIG_USB_SUSPEND | |
9a5d3e98 | 735 | (void) usb_suspend_device (hcd->self.root_hub, message); |
1da177e4 LT |
736 | #else |
737 | usb_lock_device (hcd->self.root_hub); | |
738 | (void) ehci_hub_suspend (hcd); | |
739 | usb_unlock_device (hcd->self.root_hub); | |
740 | #endif | |
741 | ||
742 | // save (PCI) FLADJ in case of Vaux power loss | |
743 | // ... we'd only use it to handle clock skew | |
744 | ||
745 | return 0; | |
746 | } | |
747 | ||
748 | static int ehci_resume (struct usb_hcd *hcd) | |
749 | { | |
750 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
751 | unsigned port; | |
752 | struct usb_device *root = hcd->self.root_hub; | |
753 | int retval = -EINVAL; | |
1da177e4 LT |
754 | |
755 | // maybe restore (PCI) FLADJ | |
756 | ||
757 | if (time_before (jiffies, ehci->next_statechange)) | |
758 | msleep (100); | |
759 | ||
760 | /* If any port is suspended, we know we can/must resume the HC. */ | |
761 | for (port = HCS_N_PORTS (ehci->hcs_params); port > 0; ) { | |
762 | u32 status; | |
763 | port--; | |
764 | status = readl (&ehci->regs->port_status [port]); | |
765 | if (status & PORT_SUSPEND) { | |
766 | down (&hcd->self.root_hub->serialize); | |
767 | retval = ehci_hub_resume (hcd); | |
768 | up (&hcd->self.root_hub->serialize); | |
769 | break; | |
770 | } | |
1da177e4 LT |
771 | if (!root->children [port]) |
772 | continue; | |
773 | dbg_port (ehci, __FUNCTION__, port + 1, status); | |
774 | usb_set_device_state (root->children[port], | |
775 | USB_STATE_NOTATTACHED); | |
776 | } | |
777 | ||
778 | /* Else reset, to cope with power loss or flush-to-storage | |
779 | * style "resume" having activated BIOS during reboot. | |
780 | */ | |
781 | if (port == 0) { | |
782 | (void) ehci_halt (ehci); | |
783 | (void) ehci_reset (ehci); | |
784 | (void) ehci_hc_reset (hcd); | |
785 | ||
786 | /* emptying the schedule aborts any urbs */ | |
787 | spin_lock_irq (&ehci->lock); | |
788 | if (ehci->reclaim) | |
789 | ehci->reclaim_ready = 1; | |
790 | ehci_work (ehci, NULL); | |
791 | spin_unlock_irq (&ehci->lock); | |
792 | ||
793 | /* restart; khubd will disconnect devices */ | |
794 | retval = ehci_start (hcd); | |
795 | ||
796 | /* here we "know" root ports should always stay powered; | |
56c1e26d | 797 | * but some controllers may lose all power. |
1da177e4 | 798 | */ |
56c1e26d | 799 | ehci_port_power (ehci, 1); |
1da177e4 LT |
800 | } |
801 | ||
802 | return retval; | |
803 | } | |
804 | ||
805 | #endif | |
806 | ||
807 | /*-------------------------------------------------------------------------*/ | |
808 | ||
809 | /* | |
810 | * ehci_work is called from some interrupts, timers, and so on. | |
811 | * it calls driver completion functions, after dropping ehci->lock. | |
812 | */ | |
813 | static void ehci_work (struct ehci_hcd *ehci, struct pt_regs *regs) | |
814 | { | |
815 | timer_action_done (ehci, TIMER_IO_WATCHDOG); | |
816 | if (ehci->reclaim_ready) | |
817 | end_unlink_async (ehci, regs); | |
818 | ||
819 | /* another CPU may drop ehci->lock during a schedule scan while | |
820 | * it reports urb completions. this flag guards against bogus | |
821 | * attempts at re-entrant schedule scanning. | |
822 | */ | |
823 | if (ehci->scanning) | |
824 | return; | |
825 | ehci->scanning = 1; | |
826 | scan_async (ehci, regs); | |
827 | if (ehci->next_uframe != -1) | |
828 | scan_periodic (ehci, regs); | |
829 | ehci->scanning = 0; | |
830 | ||
831 | /* the IO watchdog guards against hardware or driver bugs that | |
832 | * misplace IRQs, and should let us run completely without IRQs. | |
833 | * such lossage has been observed on both VT6202 and VT8235. | |
834 | */ | |
835 | if (HC_IS_RUNNING (ehci_to_hcd(ehci)->state) && | |
836 | (ehci->async->qh_next.ptr != NULL || | |
837 | ehci->periodic_sched != 0)) | |
838 | timer_action (ehci, TIMER_IO_WATCHDOG); | |
839 | } | |
840 | ||
841 | /*-------------------------------------------------------------------------*/ | |
842 | ||
843 | static irqreturn_t ehci_irq (struct usb_hcd *hcd, struct pt_regs *regs) | |
844 | { | |
845 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
846 | u32 status; | |
847 | int bh; | |
848 | ||
849 | spin_lock (&ehci->lock); | |
850 | ||
851 | status = readl (&ehci->regs->status); | |
852 | ||
853 | /* e.g. cardbus physical eject */ | |
854 | if (status == ~(u32) 0) { | |
855 | ehci_dbg (ehci, "device removed\n"); | |
856 | goto dead; | |
857 | } | |
858 | ||
859 | status &= INTR_MASK; | |
860 | if (!status) { /* irq sharing? */ | |
861 | spin_unlock(&ehci->lock); | |
862 | return IRQ_NONE; | |
863 | } | |
864 | ||
865 | /* clear (just) interrupts */ | |
866 | writel (status, &ehci->regs->status); | |
867 | readl (&ehci->regs->command); /* unblock posted write */ | |
868 | bh = 0; | |
869 | ||
870 | #ifdef EHCI_VERBOSE_DEBUG | |
871 | /* unrequested/ignored: Frame List Rollover */ | |
872 | dbg_status (ehci, "irq", status); | |
873 | #endif | |
874 | ||
875 | /* INT, ERR, and IAA interrupt rates can be throttled */ | |
876 | ||
877 | /* normal [4.15.1.2] or error [4.15.1.1] completion */ | |
878 | if (likely ((status & (STS_INT|STS_ERR)) != 0)) { | |
879 | if (likely ((status & STS_ERR) == 0)) | |
880 | COUNT (ehci->stats.normal); | |
881 | else | |
882 | COUNT (ehci->stats.error); | |
883 | bh = 1; | |
884 | } | |
885 | ||
886 | /* complete the unlinking of some qh [4.15.2.3] */ | |
887 | if (status & STS_IAA) { | |
888 | COUNT (ehci->stats.reclaim); | |
889 | ehci->reclaim_ready = 1; | |
890 | bh = 1; | |
891 | } | |
892 | ||
893 | /* remote wakeup [4.3.1] */ | |
894 | if ((status & STS_PCD) && hcd->remote_wakeup) { | |
895 | unsigned i = HCS_N_PORTS (ehci->hcs_params); | |
896 | ||
897 | /* resume root hub? */ | |
898 | status = readl (&ehci->regs->command); | |
899 | if (!(status & CMD_RUN)) | |
900 | writel (status | CMD_RUN, &ehci->regs->command); | |
901 | ||
902 | while (i--) { | |
903 | status = readl (&ehci->regs->port_status [i]); | |
904 | if (status & PORT_OWNER) | |
905 | continue; | |
906 | if (!(status & PORT_RESUME) | |
907 | || ehci->reset_done [i] != 0) | |
908 | continue; | |
909 | ||
910 | /* start 20 msec resume signaling from this port, | |
911 | * and make khubd collect PORT_STAT_C_SUSPEND to | |
912 | * stop that signaling. | |
913 | */ | |
914 | ehci->reset_done [i] = jiffies + msecs_to_jiffies (20); | |
915 | mod_timer (&hcd->rh_timer, | |
916 | ehci->reset_done [i] + 1); | |
917 | ehci_dbg (ehci, "port %d remote wakeup\n", i + 1); | |
918 | } | |
919 | } | |
920 | ||
921 | /* PCI errors [4.15.2.4] */ | |
922 | if (unlikely ((status & STS_FATAL) != 0)) { | |
923 | /* bogus "fatal" IRQs appear on some chips... why? */ | |
924 | status = readl (&ehci->regs->status); | |
925 | dbg_cmd (ehci, "fatal", readl (&ehci->regs->command)); | |
926 | dbg_status (ehci, "fatal", status); | |
927 | if (status & STS_HALT) { | |
928 | ehci_err (ehci, "fatal error\n"); | |
929 | dead: | |
930 | ehci_reset (ehci); | |
931 | writel (0, &ehci->regs->configured_flag); | |
932 | /* generic layer kills/unlinks all urbs, then | |
933 | * uses ehci_stop to clean up the rest | |
934 | */ | |
935 | bh = 1; | |
936 | } | |
937 | } | |
938 | ||
939 | if (bh) | |
940 | ehci_work (ehci, regs); | |
941 | spin_unlock (&ehci->lock); | |
942 | return IRQ_HANDLED; | |
943 | } | |
944 | ||
945 | /*-------------------------------------------------------------------------*/ | |
946 | ||
947 | /* | |
948 | * non-error returns are a promise to giveback() the urb later | |
949 | * we drop ownership so next owner (or urb unlink) can get it | |
950 | * | |
951 | * urb + dev is in hcd.self.controller.urb_list | |
952 | * we're queueing TDs onto software and hardware lists | |
953 | * | |
954 | * hcd-specific init for hcpriv hasn't been done yet | |
955 | * | |
956 | * NOTE: control, bulk, and interrupt share the same code to append TDs | |
957 | * to a (possibly active) QH, and the same QH scanning code. | |
958 | */ | |
959 | static int ehci_urb_enqueue ( | |
960 | struct usb_hcd *hcd, | |
961 | struct usb_host_endpoint *ep, | |
962 | struct urb *urb, | |
963 | int mem_flags | |
964 | ) { | |
965 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
966 | struct list_head qtd_list; | |
967 | ||
968 | INIT_LIST_HEAD (&qtd_list); | |
969 | ||
970 | switch (usb_pipetype (urb->pipe)) { | |
971 | // case PIPE_CONTROL: | |
972 | // case PIPE_BULK: | |
973 | default: | |
974 | if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags)) | |
975 | return -ENOMEM; | |
976 | return submit_async (ehci, ep, urb, &qtd_list, mem_flags); | |
977 | ||
978 | case PIPE_INTERRUPT: | |
979 | if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags)) | |
980 | return -ENOMEM; | |
981 | return intr_submit (ehci, ep, urb, &qtd_list, mem_flags); | |
982 | ||
983 | case PIPE_ISOCHRONOUS: | |
984 | if (urb->dev->speed == USB_SPEED_HIGH) | |
985 | return itd_submit (ehci, urb, mem_flags); | |
986 | else | |
987 | return sitd_submit (ehci, urb, mem_flags); | |
988 | } | |
989 | } | |
990 | ||
991 | static void unlink_async (struct ehci_hcd *ehci, struct ehci_qh *qh) | |
992 | { | |
993 | /* if we need to use IAA and it's busy, defer */ | |
994 | if (qh->qh_state == QH_STATE_LINKED | |
995 | && ehci->reclaim | |
996 | && HC_IS_RUNNING (ehci_to_hcd(ehci)->state)) { | |
997 | struct ehci_qh *last; | |
998 | ||
999 | for (last = ehci->reclaim; | |
1000 | last->reclaim; | |
1001 | last = last->reclaim) | |
1002 | continue; | |
1003 | qh->qh_state = QH_STATE_UNLINK_WAIT; | |
1004 | last->reclaim = qh; | |
1005 | ||
1006 | /* bypass IAA if the hc can't care */ | |
1007 | } else if (!HC_IS_RUNNING (ehci_to_hcd(ehci)->state) && ehci->reclaim) | |
1008 | end_unlink_async (ehci, NULL); | |
1009 | ||
1010 | /* something else might have unlinked the qh by now */ | |
1011 | if (qh->qh_state == QH_STATE_LINKED) | |
1012 | start_unlink_async (ehci, qh); | |
1013 | } | |
1014 | ||
1015 | /* remove from hardware lists | |
1016 | * completions normally happen asynchronously | |
1017 | */ | |
1018 | ||
1019 | static int ehci_urb_dequeue (struct usb_hcd *hcd, struct urb *urb) | |
1020 | { | |
1021 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
1022 | struct ehci_qh *qh; | |
1023 | unsigned long flags; | |
1024 | ||
1025 | spin_lock_irqsave (&ehci->lock, flags); | |
1026 | switch (usb_pipetype (urb->pipe)) { | |
1027 | // case PIPE_CONTROL: | |
1028 | // case PIPE_BULK: | |
1029 | default: | |
1030 | qh = (struct ehci_qh *) urb->hcpriv; | |
1031 | if (!qh) | |
1032 | break; | |
1033 | unlink_async (ehci, qh); | |
1034 | break; | |
1035 | ||
1036 | case PIPE_INTERRUPT: | |
1037 | qh = (struct ehci_qh *) urb->hcpriv; | |
1038 | if (!qh) | |
1039 | break; | |
1040 | switch (qh->qh_state) { | |
1041 | case QH_STATE_LINKED: | |
1042 | intr_deschedule (ehci, qh); | |
1043 | /* FALL THROUGH */ | |
1044 | case QH_STATE_IDLE: | |
1045 | qh_completions (ehci, qh, NULL); | |
1046 | break; | |
1047 | default: | |
1048 | ehci_dbg (ehci, "bogus qh %p state %d\n", | |
1049 | qh, qh->qh_state); | |
1050 | goto done; | |
1051 | } | |
1052 | ||
1053 | /* reschedule QH iff another request is queued */ | |
1054 | if (!list_empty (&qh->qtd_list) | |
1055 | && HC_IS_RUNNING (hcd->state)) { | |
1056 | int status; | |
1057 | ||
1058 | status = qh_schedule (ehci, qh); | |
1059 | spin_unlock_irqrestore (&ehci->lock, flags); | |
1060 | ||
1061 | if (status != 0) { | |
1062 | // shouldn't happen often, but ... | |
1063 | // FIXME kill those tds' urbs | |
1064 | err ("can't reschedule qh %p, err %d", | |
1065 | qh, status); | |
1066 | } | |
1067 | return status; | |
1068 | } | |
1069 | break; | |
1070 | ||
1071 | case PIPE_ISOCHRONOUS: | |
1072 | // itd or sitd ... | |
1073 | ||
1074 | // wait till next completion, do it then. | |
1075 | // completion irqs can wait up to 1024 msec, | |
1076 | break; | |
1077 | } | |
1078 | done: | |
1079 | spin_unlock_irqrestore (&ehci->lock, flags); | |
1080 | return 0; | |
1081 | } | |
1082 | ||
1083 | /*-------------------------------------------------------------------------*/ | |
1084 | ||
1085 | // bulk qh holds the data toggle | |
1086 | ||
1087 | static void | |
1088 | ehci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep) | |
1089 | { | |
1090 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
1091 | unsigned long flags; | |
1092 | struct ehci_qh *qh, *tmp; | |
1093 | ||
1094 | /* ASSERT: any requests/urbs are being unlinked */ | |
1095 | /* ASSERT: nobody can be submitting urbs for this any more */ | |
1096 | ||
1097 | rescan: | |
1098 | spin_lock_irqsave (&ehci->lock, flags); | |
1099 | qh = ep->hcpriv; | |
1100 | if (!qh) | |
1101 | goto done; | |
1102 | ||
1103 | /* endpoints can be iso streams. for now, we don't | |
1104 | * accelerate iso completions ... so spin a while. | |
1105 | */ | |
1106 | if (qh->hw_info1 == 0) { | |
1107 | ehci_vdbg (ehci, "iso delay\n"); | |
1108 | goto idle_timeout; | |
1109 | } | |
1110 | ||
1111 | if (!HC_IS_RUNNING (hcd->state)) | |
1112 | qh->qh_state = QH_STATE_IDLE; | |
1113 | switch (qh->qh_state) { | |
1114 | case QH_STATE_LINKED: | |
1115 | for (tmp = ehci->async->qh_next.qh; | |
1116 | tmp && tmp != qh; | |
1117 | tmp = tmp->qh_next.qh) | |
1118 | continue; | |
1119 | /* periodic qh self-unlinks on empty */ | |
1120 | if (!tmp) | |
1121 | goto nogood; | |
1122 | unlink_async (ehci, qh); | |
1123 | /* FALL THROUGH */ | |
1124 | case QH_STATE_UNLINK: /* wait for hw to finish? */ | |
1125 | idle_timeout: | |
1126 | spin_unlock_irqrestore (&ehci->lock, flags); | |
1127 | set_current_state (TASK_UNINTERRUPTIBLE); | |
1128 | schedule_timeout (1); | |
1129 | goto rescan; | |
1130 | case QH_STATE_IDLE: /* fully unlinked */ | |
1131 | if (list_empty (&qh->qtd_list)) { | |
1132 | qh_put (qh); | |
1133 | break; | |
1134 | } | |
1135 | /* else FALL THROUGH */ | |
1136 | default: | |
1137 | nogood: | |
1138 | /* caller was supposed to have unlinked any requests; | |
1139 | * that's not our job. just leak this memory. | |
1140 | */ | |
1141 | ehci_err (ehci, "qh %p (#%02x) state %d%s\n", | |
1142 | qh, ep->desc.bEndpointAddress, qh->qh_state, | |
1143 | list_empty (&qh->qtd_list) ? "" : "(has tds)"); | |
1144 | break; | |
1145 | } | |
1146 | ep->hcpriv = NULL; | |
1147 | done: | |
1148 | spin_unlock_irqrestore (&ehci->lock, flags); | |
1149 | return; | |
1150 | } | |
1151 | ||
1152 | /*-------------------------------------------------------------------------*/ | |
1153 | ||
1154 | static const struct hc_driver ehci_driver = { | |
1155 | .description = hcd_name, | |
1156 | .product_desc = "EHCI Host Controller", | |
1157 | .hcd_priv_size = sizeof(struct ehci_hcd), | |
1158 | ||
1159 | /* | |
1160 | * generic hardware linkage | |
1161 | */ | |
1162 | .irq = ehci_irq, | |
1163 | .flags = HCD_MEMORY | HCD_USB2, | |
1164 | ||
1165 | /* | |
1166 | * basic lifecycle operations | |
1167 | */ | |
1168 | .reset = ehci_hc_reset, | |
1169 | .start = ehci_start, | |
1170 | #ifdef CONFIG_PM | |
1171 | .suspend = ehci_suspend, | |
1172 | .resume = ehci_resume, | |
1173 | #endif | |
1174 | .stop = ehci_stop, | |
1175 | ||
1176 | /* | |
1177 | * managing i/o requests and associated device resources | |
1178 | */ | |
1179 | .urb_enqueue = ehci_urb_enqueue, | |
1180 | .urb_dequeue = ehci_urb_dequeue, | |
1181 | .endpoint_disable = ehci_endpoint_disable, | |
1182 | ||
1183 | /* | |
1184 | * scheduling support | |
1185 | */ | |
1186 | .get_frame_number = ehci_get_frame, | |
1187 | ||
1188 | /* | |
1189 | * root hub support | |
1190 | */ | |
1191 | .hub_status_data = ehci_hub_status_data, | |
1192 | .hub_control = ehci_hub_control, | |
1193 | .hub_suspend = ehci_hub_suspend, | |
1194 | .hub_resume = ehci_hub_resume, | |
1195 | }; | |
1196 | ||
1197 | /*-------------------------------------------------------------------------*/ | |
1198 | ||
1199 | /* EHCI 1.0 doesn't require PCI */ | |
1200 | ||
1201 | #ifdef CONFIG_PCI | |
1202 | ||
1203 | /* PCI driver selection metadata; PCI hotplugging uses this */ | |
1204 | static const struct pci_device_id pci_ids [] = { { | |
1205 | /* handle any USB 2.0 EHCI controller */ | |
1206 | PCI_DEVICE_CLASS(((PCI_CLASS_SERIAL_USB << 8) | 0x20), ~0), | |
1207 | .driver_data = (unsigned long) &ehci_driver, | |
1208 | }, | |
1209 | { /* end: all zeroes */ } | |
1210 | }; | |
1211 | MODULE_DEVICE_TABLE (pci, pci_ids); | |
1212 | ||
1213 | /* pci driver glue; this is a "new style" PCI driver module */ | |
1214 | static struct pci_driver ehci_pci_driver = { | |
1215 | .name = (char *) hcd_name, | |
1216 | .id_table = pci_ids, | |
1217 | ||
1218 | .probe = usb_hcd_pci_probe, | |
1219 | .remove = usb_hcd_pci_remove, | |
1220 | ||
1221 | #ifdef CONFIG_PM | |
1222 | .suspend = usb_hcd_pci_suspend, | |
1223 | .resume = usb_hcd_pci_resume, | |
1224 | #endif | |
1225 | }; | |
1226 | ||
1227 | #endif /* PCI */ | |
1228 | ||
1229 | ||
1230 | #define DRIVER_INFO DRIVER_VERSION " " DRIVER_DESC | |
1231 | ||
1232 | MODULE_DESCRIPTION (DRIVER_INFO); | |
1233 | MODULE_AUTHOR (DRIVER_AUTHOR); | |
1234 | MODULE_LICENSE ("GPL"); | |
1235 | ||
1236 | static int __init init (void) | |
1237 | { | |
1238 | if (usb_disabled()) | |
1239 | return -ENODEV; | |
1240 | ||
1241 | pr_debug ("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n", | |
1242 | hcd_name, | |
1243 | sizeof (struct ehci_qh), sizeof (struct ehci_qtd), | |
1244 | sizeof (struct ehci_itd), sizeof (struct ehci_sitd)); | |
1245 | ||
1246 | return pci_register_driver (&ehci_pci_driver); | |
1247 | } | |
1248 | module_init (init); | |
1249 | ||
1250 | static void __exit cleanup (void) | |
1251 | { | |
1252 | pci_unregister_driver (&ehci_pci_driver); | |
1253 | } | |
1254 | module_exit (cleanup); |