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1da177e4 LT |
1 | /* |
2 | * Copyright (c) 2000-2004 by David Brownell | |
53bd6a60 | 3 | * |
1da177e4 LT |
4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms of the GNU General Public License as published by the | |
6 | * Free Software Foundation; either version 2 of the License, or (at your | |
7 | * option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but | |
10 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
11 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 | * for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software Foundation, | |
16 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
17 | */ | |
18 | ||
1da177e4 LT |
19 | #include <linux/module.h> |
20 | #include <linux/pci.h> | |
21 | #include <linux/dmapool.h> | |
22 | #include <linux/kernel.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/ioport.h> | |
25 | #include <linux/sched.h> | |
26 | #include <linux/slab.h> | |
3c04e20e | 27 | #include <linux/vmalloc.h> |
1da177e4 LT |
28 | #include <linux/errno.h> |
29 | #include <linux/init.h> | |
30 | #include <linux/timer.h> | |
31 | #include <linux/list.h> | |
32 | #include <linux/interrupt.h> | |
33 | #include <linux/reboot.h> | |
34 | #include <linux/usb.h> | |
35 | #include <linux/moduleparam.h> | |
36 | #include <linux/dma-mapping.h> | |
694cc208 | 37 | #include <linux/debugfs.h> |
1da177e4 LT |
38 | |
39 | #include "../core/hcd.h" | |
40 | ||
41 | #include <asm/byteorder.h> | |
42 | #include <asm/io.h> | |
43 | #include <asm/irq.h> | |
44 | #include <asm/system.h> | |
45 | #include <asm/unaligned.h> | |
1da177e4 LT |
46 | |
47 | /*-------------------------------------------------------------------------*/ | |
48 | ||
49 | /* | |
50 | * EHCI hc_driver implementation ... experimental, incomplete. | |
51 | * Based on the final 1.0 register interface specification. | |
52 | * | |
53 | * USB 2.0 shows up in upcoming www.pcmcia.org technology. | |
54 | * First was PCMCIA, like ISA; then CardBus, which is PCI. | |
55 | * Next comes "CardBay", using USB 2.0 signals. | |
56 | * | |
57 | * Contains additional contributions by Brad Hards, Rory Bolt, and others. | |
58 | * Special thanks to Intel and VIA for providing host controllers to | |
59 | * test this driver on, and Cypress (including In-System Design) for | |
60 | * providing early devices for those host controllers to talk to! | |
1da177e4 LT |
61 | */ |
62 | ||
1da177e4 LT |
63 | #define DRIVER_AUTHOR "David Brownell" |
64 | #define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver" | |
65 | ||
66 | static const char hcd_name [] = "ehci_hcd"; | |
67 | ||
68 | ||
9776afc8 | 69 | #undef VERBOSE_DEBUG |
1da177e4 LT |
70 | #undef EHCI_URB_TRACE |
71 | ||
72 | #ifdef DEBUG | |
73 | #define EHCI_STATS | |
74 | #endif | |
75 | ||
76 | /* magic numbers that can affect system performance */ | |
77 | #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */ | |
78 | #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */ | |
79 | #define EHCI_TUNE_RL_TT 0 | |
80 | #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */ | |
81 | #define EHCI_TUNE_MULT_TT 1 | |
82 | #define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */ | |
83 | ||
07d29b63 | 84 | #define EHCI_IAA_MSECS 10 /* arbitrary */ |
1da177e4 LT |
85 | #define EHCI_IO_JIFFIES (HZ/10) /* io watchdog > irq_thresh */ |
86 | #define EHCI_ASYNC_JIFFIES (HZ/20) /* async idle timeout */ | |
b9638011 | 87 | #define EHCI_SHRINK_FRAMES 5 /* async qh unlink delay */ |
1da177e4 LT |
88 | |
89 | /* Initial IRQ latency: faster than hw default */ | |
90 | static int log2_irq_thresh = 0; // 0 to 6 | |
91 | module_param (log2_irq_thresh, int, S_IRUGO); | |
92 | MODULE_PARM_DESC (log2_irq_thresh, "log2 IRQ latency, 1-64 microframes"); | |
93 | ||
94 | /* initial park setting: slower than hw default */ | |
95 | static unsigned park = 0; | |
96 | module_param (park, uint, S_IRUGO); | |
97 | MODULE_PARM_DESC (park, "park setting; 1-3 back-to-back async packets"); | |
98 | ||
93f1a47c DB |
99 | /* for flakey hardware, ignore overcurrent indicators */ |
100 | static int ignore_oc = 0; | |
101 | module_param (ignore_oc, bool, S_IRUGO); | |
102 | MODULE_PARM_DESC (ignore_oc, "ignore bogus hardware overcurrent indications"); | |
103 | ||
1da177e4 LT |
104 | #define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT) |
105 | ||
106 | /*-------------------------------------------------------------------------*/ | |
107 | ||
108 | #include "ehci.h" | |
109 | #include "ehci-dbg.c" | |
110 | ||
111 | /*-------------------------------------------------------------------------*/ | |
112 | ||
113 | /* | |
114 | * handshake - spin reading hc until handshake completes or fails | |
115 | * @ptr: address of hc register to be read | |
116 | * @mask: bits to look at in result of read | |
117 | * @done: value of those bits when handshake succeeds | |
118 | * @usec: timeout in microseconds | |
119 | * | |
120 | * Returns negative errno, or zero on success | |
121 | * | |
122 | * Success happens when the "mask" bits have the specified value (hardware | |
123 | * handshake done). There are two failure modes: "usec" have passed (major | |
124 | * hardware flakeout), or the register reads as all-ones (hardware removed). | |
125 | * | |
126 | * That last failure should_only happen in cases like physical cardbus eject | |
127 | * before driver shutdown. But it also seems to be caused by bugs in cardbus | |
128 | * bridge shutdown: shutting down the bridge before the devices using it. | |
129 | */ | |
083522d7 BH |
130 | static int handshake (struct ehci_hcd *ehci, void __iomem *ptr, |
131 | u32 mask, u32 done, int usec) | |
1da177e4 LT |
132 | { |
133 | u32 result; | |
134 | ||
135 | do { | |
083522d7 | 136 | result = ehci_readl(ehci, ptr); |
1da177e4 LT |
137 | if (result == ~(u32)0) /* card removed */ |
138 | return -ENODEV; | |
139 | result &= mask; | |
140 | if (result == done) | |
141 | return 0; | |
142 | udelay (1); | |
143 | usec--; | |
144 | } while (usec > 0); | |
145 | return -ETIMEDOUT; | |
146 | } | |
147 | ||
148 | /* force HC to halt state from unknown (EHCI spec section 2.3) */ | |
149 | static int ehci_halt (struct ehci_hcd *ehci) | |
150 | { | |
083522d7 | 151 | u32 temp = ehci_readl(ehci, &ehci->regs->status); |
1da177e4 | 152 | |
72f30b6f | 153 | /* disable any irqs left enabled by previous code */ |
083522d7 | 154 | ehci_writel(ehci, 0, &ehci->regs->intr_enable); |
72f30b6f | 155 | |
1da177e4 LT |
156 | if ((temp & STS_HALT) != 0) |
157 | return 0; | |
158 | ||
083522d7 | 159 | temp = ehci_readl(ehci, &ehci->regs->command); |
1da177e4 | 160 | temp &= ~CMD_RUN; |
083522d7 BH |
161 | ehci_writel(ehci, temp, &ehci->regs->command); |
162 | return handshake (ehci, &ehci->regs->status, | |
163 | STS_HALT, STS_HALT, 16 * 125); | |
1da177e4 LT |
164 | } |
165 | ||
0bcfeb3e DB |
166 | static int handshake_on_error_set_halt(struct ehci_hcd *ehci, void __iomem *ptr, |
167 | u32 mask, u32 done, int usec) | |
168 | { | |
169 | int error; | |
170 | ||
171 | error = handshake(ehci, ptr, mask, done, usec); | |
172 | if (error) { | |
173 | ehci_halt(ehci); | |
174 | ehci_to_hcd(ehci)->state = HC_STATE_HALT; | |
175 | ehci_err(ehci, "force halt; handhake %p %08x %08x -> %d\n", | |
176 | ptr, mask, done, error); | |
177 | } | |
178 | ||
179 | return error; | |
180 | } | |
181 | ||
1da177e4 LT |
182 | /* put TDI/ARC silicon into EHCI mode */ |
183 | static void tdi_reset (struct ehci_hcd *ehci) | |
184 | { | |
185 | u32 __iomem *reg_ptr; | |
186 | u32 tmp; | |
187 | ||
d23a1377 | 188 | reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + USBMODE); |
083522d7 | 189 | tmp = ehci_readl(ehci, reg_ptr); |
d23a1377 VB |
190 | tmp |= USBMODE_CM_HC; |
191 | /* The default byte access to MMR space is LE after | |
192 | * controller reset. Set the required endian mode | |
193 | * for transfer buffers to match the host microprocessor | |
194 | */ | |
195 | if (ehci_big_endian_mmio(ehci)) | |
196 | tmp |= USBMODE_BE; | |
083522d7 | 197 | ehci_writel(ehci, tmp, reg_ptr); |
1da177e4 LT |
198 | } |
199 | ||
200 | /* reset a non-running (STS_HALT == 1) controller */ | |
201 | static int ehci_reset (struct ehci_hcd *ehci) | |
202 | { | |
203 | int retval; | |
083522d7 | 204 | u32 command = ehci_readl(ehci, &ehci->regs->command); |
1da177e4 LT |
205 | |
206 | command |= CMD_RESET; | |
207 | dbg_cmd (ehci, "reset", command); | |
083522d7 | 208 | ehci_writel(ehci, command, &ehci->regs->command); |
1da177e4 LT |
209 | ehci_to_hcd(ehci)->state = HC_STATE_HALT; |
210 | ehci->next_statechange = jiffies; | |
083522d7 BH |
211 | retval = handshake (ehci, &ehci->regs->command, |
212 | CMD_RESET, 0, 250 * 1000); | |
1da177e4 LT |
213 | |
214 | if (retval) | |
215 | return retval; | |
216 | ||
217 | if (ehci_is_TDI(ehci)) | |
218 | tdi_reset (ehci); | |
219 | ||
220 | return retval; | |
221 | } | |
222 | ||
223 | /* idle the controller (from running) */ | |
224 | static void ehci_quiesce (struct ehci_hcd *ehci) | |
225 | { | |
226 | u32 temp; | |
227 | ||
228 | #ifdef DEBUG | |
229 | if (!HC_IS_RUNNING (ehci_to_hcd(ehci)->state)) | |
230 | BUG (); | |
231 | #endif | |
232 | ||
233 | /* wait for any schedule enables/disables to take effect */ | |
083522d7 | 234 | temp = ehci_readl(ehci, &ehci->regs->command) << 10; |
1da177e4 | 235 | temp &= STS_ASS | STS_PSS; |
c765d4ca KW |
236 | if (handshake_on_error_set_halt(ehci, &ehci->regs->status, |
237 | STS_ASS | STS_PSS, temp, 16 * 125)) | |
1da177e4 | 238 | return; |
1da177e4 LT |
239 | |
240 | /* then disable anything that's still active */ | |
083522d7 | 241 | temp = ehci_readl(ehci, &ehci->regs->command); |
1da177e4 | 242 | temp &= ~(CMD_ASE | CMD_IAAD | CMD_PSE); |
083522d7 | 243 | ehci_writel(ehci, temp, &ehci->regs->command); |
1da177e4 LT |
244 | |
245 | /* hardware can take 16 microframes to turn off ... */ | |
c765d4ca KW |
246 | handshake_on_error_set_halt(ehci, &ehci->regs->status, |
247 | STS_ASS | STS_PSS, 0, 16 * 125); | |
1da177e4 LT |
248 | } |
249 | ||
250 | /*-------------------------------------------------------------------------*/ | |
251 | ||
07d29b63 | 252 | static void end_unlink_async(struct ehci_hcd *ehci); |
7d12e780 | 253 | static void ehci_work(struct ehci_hcd *ehci); |
1da177e4 LT |
254 | |
255 | #include "ehci-hub.c" | |
256 | #include "ehci-mem.c" | |
257 | #include "ehci-q.c" | |
258 | #include "ehci-sched.c" | |
259 | ||
260 | /*-------------------------------------------------------------------------*/ | |
261 | ||
07d29b63 | 262 | static void ehci_iaa_watchdog(unsigned long param) |
1da177e4 LT |
263 | { |
264 | struct ehci_hcd *ehci = (struct ehci_hcd *) param; | |
265 | unsigned long flags; | |
266 | ||
267 | spin_lock_irqsave (&ehci->lock, flags); | |
268 | ||
e82cc128 DB |
269 | /* Lost IAA irqs wedge things badly; seen first with a vt8235. |
270 | * So we need this watchdog, but must protect it against both | |
271 | * (a) SMP races against real IAA firing and retriggering, and | |
272 | * (b) clean HC shutdown, when IAA watchdog was pending. | |
273 | */ | |
274 | if (ehci->reclaim | |
275 | && !timer_pending(&ehci->iaa_watchdog) | |
276 | && HC_IS_RUNNING(ehci_to_hcd(ehci)->state)) { | |
277 | u32 cmd, status; | |
278 | ||
279 | /* If we get here, IAA is *REALLY* late. It's barely | |
280 | * conceivable that the system is so busy that CMD_IAAD | |
281 | * is still legitimately set, so let's be sure it's | |
282 | * clear before we read STS_IAA. (The HC should clear | |
283 | * CMD_IAAD when it sets STS_IAA.) | |
284 | */ | |
285 | cmd = ehci_readl(ehci, &ehci->regs->command); | |
286 | if (cmd & CMD_IAAD) | |
287 | ehci_writel(ehci, cmd & ~CMD_IAAD, | |
288 | &ehci->regs->command); | |
289 | ||
290 | /* If IAA is set here it either legitimately triggered | |
291 | * before we cleared IAAD above (but _way_ late, so we'll | |
292 | * still count it as lost) ... or a silicon erratum: | |
293 | * - VIA seems to set IAA without triggering the IRQ; | |
294 | * - IAAD potentially cleared without setting IAA. | |
295 | */ | |
296 | status = ehci_readl(ehci, &ehci->regs->status); | |
297 | if ((status & STS_IAA) || !(cmd & CMD_IAAD)) { | |
1da177e4 | 298 | COUNT (ehci->stats.lost_iaa); |
083522d7 | 299 | ehci_writel(ehci, STS_IAA, &ehci->regs->status); |
1da177e4 | 300 | } |
e82cc128 DB |
301 | |
302 | ehci_vdbg(ehci, "IAA watchdog: status %x cmd %x\n", | |
303 | status, cmd); | |
07d29b63 | 304 | end_unlink_async(ehci); |
1da177e4 LT |
305 | } |
306 | ||
07d29b63 AS |
307 | spin_unlock_irqrestore(&ehci->lock, flags); |
308 | } | |
309 | ||
310 | static void ehci_watchdog(unsigned long param) | |
311 | { | |
312 | struct ehci_hcd *ehci = (struct ehci_hcd *) param; | |
313 | unsigned long flags; | |
314 | ||
315 | spin_lock_irqsave(&ehci->lock, flags); | |
316 | ||
317 | /* stop async processing after it's idled a bit */ | |
1da177e4 | 318 | if (test_bit (TIMER_ASYNC_OFF, &ehci->actions)) |
26f953fd | 319 | start_unlink_async (ehci, ehci->async); |
1da177e4 LT |
320 | |
321 | /* ehci could run by timer, without IRQs ... */ | |
7d12e780 | 322 | ehci_work (ehci); |
1da177e4 LT |
323 | |
324 | spin_unlock_irqrestore (&ehci->lock, flags); | |
325 | } | |
326 | ||
8903795a AS |
327 | /* On some systems, leaving remote wakeup enabled prevents system shutdown. |
328 | * The firmware seems to think that powering off is a wakeup event! | |
329 | * This routine turns off remote wakeup and everything else, on all ports. | |
330 | */ | |
331 | static void ehci_turn_off_all_ports(struct ehci_hcd *ehci) | |
332 | { | |
333 | int port = HCS_N_PORTS(ehci->hcs_params); | |
334 | ||
335 | while (port--) | |
336 | ehci_writel(ehci, PORT_RWC_BITS, | |
337 | &ehci->regs->port_status[port]); | |
338 | } | |
339 | ||
21da84a8 SS |
340 | /* |
341 | * Halt HC, turn off all ports, and let the BIOS use the companion controllers. | |
342 | * Should be called with ehci->lock held. | |
72f30b6f | 343 | */ |
21da84a8 | 344 | static void ehci_silence_controller(struct ehci_hcd *ehci) |
1da177e4 | 345 | { |
21da84a8 | 346 | ehci_halt(ehci); |
8903795a | 347 | ehci_turn_off_all_ports(ehci); |
1da177e4 LT |
348 | |
349 | /* make BIOS/etc use companion controller during reboot */ | |
083522d7 | 350 | ehci_writel(ehci, 0, &ehci->regs->configured_flag); |
8903795a AS |
351 | |
352 | /* unblock posted writes */ | |
353 | ehci_readl(ehci, &ehci->regs->configured_flag); | |
1da177e4 LT |
354 | } |
355 | ||
21da84a8 SS |
356 | /* ehci_shutdown kick in for silicon on any bus (not just pci, etc). |
357 | * This forcibly disables dma and IRQs, helping kexec and other cases | |
358 | * where the next system software may expect clean state. | |
359 | */ | |
360 | static void ehci_shutdown(struct usb_hcd *hcd) | |
361 | { | |
362 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | |
363 | ||
364 | del_timer_sync(&ehci->watchdog); | |
365 | del_timer_sync(&ehci->iaa_watchdog); | |
366 | ||
367 | spin_lock_irq(&ehci->lock); | |
368 | ehci_silence_controller(ehci); | |
369 | spin_unlock_irq(&ehci->lock); | |
370 | } | |
371 | ||
56c1e26d DB |
372 | static void ehci_port_power (struct ehci_hcd *ehci, int is_on) |
373 | { | |
374 | unsigned port; | |
375 | ||
376 | if (!HCS_PPC (ehci->hcs_params)) | |
377 | return; | |
378 | ||
379 | ehci_dbg (ehci, "...power%s ports...\n", is_on ? "up" : "down"); | |
380 | for (port = HCS_N_PORTS (ehci->hcs_params); port > 0; ) | |
381 | (void) ehci_hub_control(ehci_to_hcd(ehci), | |
382 | is_on ? SetPortFeature : ClearPortFeature, | |
383 | USB_PORT_FEAT_POWER, | |
384 | port--, NULL, 0); | |
383975d7 AS |
385 | /* Flush those writes */ |
386 | ehci_readl(ehci, &ehci->regs->command); | |
56c1e26d DB |
387 | msleep(20); |
388 | } | |
389 | ||
7ff71d6a | 390 | /*-------------------------------------------------------------------------*/ |
1da177e4 | 391 | |
7ff71d6a MP |
392 | /* |
393 | * ehci_work is called from some interrupts, timers, and so on. | |
394 | * it calls driver completion functions, after dropping ehci->lock. | |
395 | */ | |
7d12e780 | 396 | static void ehci_work (struct ehci_hcd *ehci) |
7ff71d6a MP |
397 | { |
398 | timer_action_done (ehci, TIMER_IO_WATCHDOG); | |
7ff71d6a MP |
399 | |
400 | /* another CPU may drop ehci->lock during a schedule scan while | |
401 | * it reports urb completions. this flag guards against bogus | |
402 | * attempts at re-entrant schedule scanning. | |
403 | */ | |
404 | if (ehci->scanning) | |
405 | return; | |
406 | ehci->scanning = 1; | |
7d12e780 | 407 | scan_async (ehci); |
7ff71d6a | 408 | if (ehci->next_uframe != -1) |
7d12e780 | 409 | scan_periodic (ehci); |
7ff71d6a MP |
410 | ehci->scanning = 0; |
411 | ||
412 | /* the IO watchdog guards against hardware or driver bugs that | |
413 | * misplace IRQs, and should let us run completely without IRQs. | |
414 | * such lossage has been observed on both VT6202 and VT8235. | |
415 | */ | |
416 | if (HC_IS_RUNNING (ehci_to_hcd(ehci)->state) && | |
417 | (ehci->async->qh_next.ptr != NULL || | |
418 | ehci->periodic_sched != 0)) | |
419 | timer_action (ehci, TIMER_IO_WATCHDOG); | |
420 | } | |
1da177e4 | 421 | |
21da84a8 SS |
422 | /* |
423 | * Called when the ehci_hcd module is removed. | |
424 | */ | |
7ff71d6a | 425 | static void ehci_stop (struct usb_hcd *hcd) |
1da177e4 LT |
426 | { |
427 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
1da177e4 | 428 | |
7ff71d6a | 429 | ehci_dbg (ehci, "stop\n"); |
1da177e4 | 430 | |
7ff71d6a MP |
431 | /* no more interrupts ... */ |
432 | del_timer_sync (&ehci->watchdog); | |
07d29b63 | 433 | del_timer_sync(&ehci->iaa_watchdog); |
56c1e26d | 434 | |
7ff71d6a MP |
435 | spin_lock_irq(&ehci->lock); |
436 | if (HC_IS_RUNNING (hcd->state)) | |
437 | ehci_quiesce (ehci); | |
1da177e4 | 438 | |
21da84a8 | 439 | ehci_silence_controller(ehci); |
7ff71d6a | 440 | ehci_reset (ehci); |
7ff71d6a | 441 | spin_unlock_irq(&ehci->lock); |
1da177e4 | 442 | |
57e06c11 | 443 | remove_companion_file(ehci); |
7ff71d6a | 444 | remove_debug_files (ehci); |
1da177e4 | 445 | |
7ff71d6a MP |
446 | /* root hub is shut down separately (first, when possible) */ |
447 | spin_lock_irq (&ehci->lock); | |
448 | if (ehci->async) | |
7d12e780 | 449 | ehci_work (ehci); |
7ff71d6a MP |
450 | spin_unlock_irq (&ehci->lock); |
451 | ehci_mem_cleanup (ehci); | |
1da177e4 | 452 | |
7ff71d6a MP |
453 | #ifdef EHCI_STATS |
454 | ehci_dbg (ehci, "irq normal %ld err %ld reclaim %ld (lost %ld)\n", | |
455 | ehci->stats.normal, ehci->stats.error, ehci->stats.reclaim, | |
456 | ehci->stats.lost_iaa); | |
457 | ehci_dbg (ehci, "complete %ld unlink %ld\n", | |
458 | ehci->stats.complete, ehci->stats.unlink); | |
1da177e4 | 459 | #endif |
1da177e4 | 460 | |
083522d7 BH |
461 | dbg_status (ehci, "ehci_stop completed", |
462 | ehci_readl(ehci, &ehci->regs->status)); | |
1da177e4 LT |
463 | } |
464 | ||
18807521 DB |
465 | /* one-time init, only for memory state */ |
466 | static int ehci_init(struct usb_hcd *hcd) | |
1da177e4 | 467 | { |
18807521 | 468 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); |
1da177e4 | 469 | u32 temp; |
1da177e4 LT |
470 | int retval; |
471 | u32 hcc_params; | |
18807521 DB |
472 | |
473 | spin_lock_init(&ehci->lock); | |
474 | ||
475 | init_timer(&ehci->watchdog); | |
476 | ehci->watchdog.function = ehci_watchdog; | |
477 | ehci->watchdog.data = (unsigned long) ehci; | |
1da177e4 | 478 | |
07d29b63 AS |
479 | init_timer(&ehci->iaa_watchdog); |
480 | ehci->iaa_watchdog.function = ehci_iaa_watchdog; | |
481 | ehci->iaa_watchdog.data = (unsigned long) ehci; | |
482 | ||
1da177e4 LT |
483 | /* |
484 | * hw default: 1K periodic list heads, one per frame. | |
485 | * periodic_size can shrink by USBCMD update if hcc_params allows. | |
486 | */ | |
487 | ehci->periodic_size = DEFAULT_I_TDPS; | |
18807521 | 488 | if ((retval = ehci_mem_init(ehci, GFP_KERNEL)) < 0) |
1da177e4 LT |
489 | return retval; |
490 | ||
491 | /* controllers may cache some of the periodic schedule ... */ | |
083522d7 | 492 | hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params); |
53bd6a60 | 493 | if (HCC_ISOC_CACHE(hcc_params)) // full frame cache |
1da177e4 LT |
494 | ehci->i_thresh = 8; |
495 | else // N microframes cached | |
18807521 | 496 | ehci->i_thresh = 2 + HCC_ISOC_THRES(hcc_params); |
1da177e4 LT |
497 | |
498 | ehci->reclaim = NULL; | |
1da177e4 LT |
499 | ehci->next_uframe = -1; |
500 | ||
1da177e4 LT |
501 | /* |
502 | * dedicate a qh for the async ring head, since we couldn't unlink | |
503 | * a 'real' qh without stopping the async schedule [4.8]. use it | |
504 | * as the 'reclamation list head' too. | |
505 | * its dummy is used in hw_alt_next of many tds, to prevent the qh | |
506 | * from automatically advancing to the next td after short reads. | |
507 | */ | |
18807521 | 508 | ehci->async->qh_next.qh = NULL; |
6dbd682b SR |
509 | ehci->async->hw_next = QH_NEXT(ehci, ehci->async->qh_dma); |
510 | ehci->async->hw_info1 = cpu_to_hc32(ehci, QH_HEAD); | |
511 | ehci->async->hw_token = cpu_to_hc32(ehci, QTD_STS_HALT); | |
512 | ehci->async->hw_qtd_next = EHCI_LIST_END(ehci); | |
18807521 | 513 | ehci->async->qh_state = QH_STATE_LINKED; |
6dbd682b | 514 | ehci->async->hw_alt_next = QTD_NEXT(ehci, ehci->async->dummy->qtd_dma); |
1da177e4 LT |
515 | |
516 | /* clear interrupt enables, set irq latency */ | |
517 | if (log2_irq_thresh < 0 || log2_irq_thresh > 6) | |
518 | log2_irq_thresh = 0; | |
519 | temp = 1 << (16 + log2_irq_thresh); | |
520 | if (HCC_CANPARK(hcc_params)) { | |
521 | /* HW default park == 3, on hardware that supports it (like | |
522 | * NVidia and ALI silicon), maximizes throughput on the async | |
523 | * schedule by avoiding QH fetches between transfers. | |
524 | * | |
525 | * With fast usb storage devices and NForce2, "park" seems to | |
526 | * make problems: throughput reduction (!), data errors... | |
527 | */ | |
528 | if (park) { | |
18807521 | 529 | park = min(park, (unsigned) 3); |
1da177e4 LT |
530 | temp |= CMD_PARK; |
531 | temp |= park << 8; | |
532 | } | |
18807521 | 533 | ehci_dbg(ehci, "park %d\n", park); |
1da177e4 | 534 | } |
18807521 | 535 | if (HCC_PGM_FRAMELISTLEN(hcc_params)) { |
1da177e4 LT |
536 | /* periodic schedule size can be smaller than default */ |
537 | temp &= ~(3 << 2); | |
538 | temp |= (EHCI_TUNE_FLS << 2); | |
539 | switch (EHCI_TUNE_FLS) { | |
540 | case 0: ehci->periodic_size = 1024; break; | |
541 | case 1: ehci->periodic_size = 512; break; | |
542 | case 2: ehci->periodic_size = 256; break; | |
18807521 | 543 | default: BUG(); |
1da177e4 LT |
544 | } |
545 | } | |
18807521 DB |
546 | ehci->command = temp; |
547 | ||
18807521 DB |
548 | return 0; |
549 | } | |
550 | ||
551 | /* start HC running; it's halted, ehci_init() has been run (once) */ | |
552 | static int ehci_run (struct usb_hcd *hcd) | |
553 | { | |
554 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
555 | int retval; | |
556 | u32 temp; | |
557 | u32 hcc_params; | |
558 | ||
1d619f12 MT |
559 | hcd->uses_new_polling = 1; |
560 | hcd->poll_rh = 0; | |
561 | ||
18807521 DB |
562 | /* EHCI spec section 4.1 */ |
563 | if ((retval = ehci_reset(ehci)) != 0) { | |
18807521 DB |
564 | ehci_mem_cleanup(ehci); |
565 | return retval; | |
566 | } | |
083522d7 BH |
567 | ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list); |
568 | ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next); | |
18807521 DB |
569 | |
570 | /* | |
571 | * hcc_params controls whether ehci->regs->segment must (!!!) | |
572 | * be used; it constrains QH/ITD/SITD and QTD locations. | |
573 | * pci_pool consistent memory always uses segment zero. | |
574 | * streaming mappings for I/O buffers, like pci_map_single(), | |
575 | * can return segments above 4GB, if the device allows. | |
576 | * | |
577 | * NOTE: the dma mask is visible through dma_supported(), so | |
578 | * drivers can pass this info along ... like NETIF_F_HIGHDMA, | |
579 | * Scsi_Host.highmem_io, and so forth. It's readonly to all | |
580 | * host side drivers though. | |
581 | */ | |
083522d7 | 582 | hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params); |
18807521 | 583 | if (HCC_64BIT_ADDR(hcc_params)) { |
083522d7 | 584 | ehci_writel(ehci, 0, &ehci->regs->segment); |
18807521 DB |
585 | #if 0 |
586 | // this is deeply broken on almost all architectures | |
587 | if (!dma_set_mask(hcd->self.controller, DMA_64BIT_MASK)) | |
588 | ehci_info(ehci, "enabled 64bit DMA\n"); | |
589 | #endif | |
590 | } | |
591 | ||
592 | ||
1da177e4 LT |
593 | // Philips, Intel, and maybe others need CMD_RUN before the |
594 | // root hub will detect new devices (why?); NEC doesn't | |
18807521 DB |
595 | ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET); |
596 | ehci->command |= CMD_RUN; | |
083522d7 | 597 | ehci_writel(ehci, ehci->command, &ehci->regs->command); |
18807521 | 598 | dbg_cmd (ehci, "init", ehci->command); |
1da177e4 | 599 | |
1da177e4 LT |
600 | /* |
601 | * Start, enabling full USB 2.0 functionality ... usb 1.1 devices | |
602 | * are explicitly handed to companion controller(s), so no TT is | |
603 | * involved with the root hub. (Except where one is integrated, | |
604 | * and there's no companion controller unless maybe for USB OTG.) | |
32fe0198 AS |
605 | * |
606 | * Turning on the CF flag will transfer ownership of all ports | |
607 | * from the companions to the EHCI controller. If any of the | |
608 | * companions are in the middle of a port reset at the time, it | |
609 | * could cause trouble. Write-locking ehci_cf_port_reset_rwsem | |
1cb52658 DB |
610 | * guarantees that no resets are in progress. After we set CF, |
611 | * a short delay lets the hardware catch up; new resets shouldn't | |
612 | * be started before the port switching actions could complete. | |
1da177e4 | 613 | */ |
32fe0198 | 614 | down_write(&ehci_cf_port_reset_rwsem); |
1da177e4 | 615 | hcd->state = HC_STATE_RUNNING; |
083522d7 BH |
616 | ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag); |
617 | ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */ | |
1cb52658 | 618 | msleep(5); |
32fe0198 | 619 | up_write(&ehci_cf_port_reset_rwsem); |
1da177e4 | 620 | |
083522d7 | 621 | temp = HC_VERSION(ehci_readl(ehci, &ehci->caps->hc_capbase)); |
1da177e4 | 622 | ehci_info (ehci, |
2b70f073 | 623 | "USB %x.%x started, EHCI %x.%02x%s\n", |
7ff71d6a | 624 | ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f), |
2b70f073 | 625 | temp >> 8, temp & 0xff, |
93f1a47c | 626 | ignore_oc ? ", overcurrent ignored" : ""); |
1da177e4 | 627 | |
083522d7 BH |
628 | ehci_writel(ehci, INTR_MASK, |
629 | &ehci->regs->intr_enable); /* Turn On Interrupts */ | |
1da177e4 | 630 | |
18807521 DB |
631 | /* GRR this is run-once init(), being done every time the HC starts. |
632 | * So long as they're part of class devices, we can't do it init() | |
633 | * since the class device isn't created that early. | |
634 | */ | |
635 | create_debug_files(ehci); | |
57e06c11 | 636 | create_companion_file(ehci); |
1da177e4 LT |
637 | |
638 | return 0; | |
639 | } | |
640 | ||
1da177e4 LT |
641 | /*-------------------------------------------------------------------------*/ |
642 | ||
7d12e780 | 643 | static irqreturn_t ehci_irq (struct usb_hcd *hcd) |
1da177e4 LT |
644 | { |
645 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
e82cc128 | 646 | u32 status, pcd_status = 0, cmd; |
1da177e4 LT |
647 | int bh; |
648 | ||
649 | spin_lock (&ehci->lock); | |
650 | ||
083522d7 | 651 | status = ehci_readl(ehci, &ehci->regs->status); |
1da177e4 LT |
652 | |
653 | /* e.g. cardbus physical eject */ | |
654 | if (status == ~(u32) 0) { | |
655 | ehci_dbg (ehci, "device removed\n"); | |
656 | goto dead; | |
657 | } | |
658 | ||
659 | status &= INTR_MASK; | |
660 | if (!status) { /* irq sharing? */ | |
661 | spin_unlock(&ehci->lock); | |
662 | return IRQ_NONE; | |
663 | } | |
664 | ||
665 | /* clear (just) interrupts */ | |
083522d7 | 666 | ehci_writel(ehci, status, &ehci->regs->status); |
e82cc128 | 667 | cmd = ehci_readl(ehci, &ehci->regs->command); |
1da177e4 LT |
668 | bh = 0; |
669 | ||
9776afc8 | 670 | #ifdef VERBOSE_DEBUG |
1da177e4 LT |
671 | /* unrequested/ignored: Frame List Rollover */ |
672 | dbg_status (ehci, "irq", status); | |
673 | #endif | |
674 | ||
675 | /* INT, ERR, and IAA interrupt rates can be throttled */ | |
676 | ||
677 | /* normal [4.15.1.2] or error [4.15.1.1] completion */ | |
678 | if (likely ((status & (STS_INT|STS_ERR)) != 0)) { | |
679 | if (likely ((status & STS_ERR) == 0)) | |
680 | COUNT (ehci->stats.normal); | |
681 | else | |
682 | COUNT (ehci->stats.error); | |
683 | bh = 1; | |
684 | } | |
685 | ||
686 | /* complete the unlinking of some qh [4.15.2.3] */ | |
687 | if (status & STS_IAA) { | |
e82cc128 DB |
688 | /* guard against (alleged) silicon errata */ |
689 | if (cmd & CMD_IAAD) { | |
690 | ehci_writel(ehci, cmd & ~CMD_IAAD, | |
691 | &ehci->regs->command); | |
692 | ehci_dbg(ehci, "IAA with IAAD still set?\n"); | |
693 | } | |
694 | if (ehci->reclaim) { | |
695 | COUNT(ehci->stats.reclaim); | |
696 | end_unlink_async(ehci); | |
697 | } else | |
698 | ehci_dbg(ehci, "IAA with nothing to reclaim?\n"); | |
1da177e4 LT |
699 | } |
700 | ||
701 | /* remote wakeup [4.3.1] */ | |
d97cc2f2 | 702 | if (status & STS_PCD) { |
1da177e4 | 703 | unsigned i = HCS_N_PORTS (ehci->hcs_params); |
d1b1842c DB |
704 | |
705 | /* kick root hub later */ | |
1d619f12 | 706 | pcd_status = status; |
1da177e4 LT |
707 | |
708 | /* resume root hub? */ | |
083522d7 | 709 | if (!(ehci_readl(ehci, &ehci->regs->command) & CMD_RUN)) |
8c03356a | 710 | usb_hcd_resume_root_hub(hcd); |
1da177e4 LT |
711 | |
712 | while (i--) { | |
083522d7 BH |
713 | int pstatus = ehci_readl(ehci, |
714 | &ehci->regs->port_status [i]); | |
b972b68c DB |
715 | |
716 | if (pstatus & PORT_OWNER) | |
1da177e4 | 717 | continue; |
b972b68c | 718 | if (!(pstatus & PORT_RESUME) |
1da177e4 LT |
719 | || ehci->reset_done [i] != 0) |
720 | continue; | |
721 | ||
722 | /* start 20 msec resume signaling from this port, | |
723 | * and make khubd collect PORT_STAT_C_SUSPEND to | |
724 | * stop that signaling. | |
725 | */ | |
726 | ehci->reset_done [i] = jiffies + msecs_to_jiffies (20); | |
1da177e4 | 727 | ehci_dbg (ehci, "port %d remote wakeup\n", i + 1); |
61e8b858 | 728 | mod_timer(&hcd->rh_timer, ehci->reset_done[i]); |
1da177e4 LT |
729 | } |
730 | } | |
731 | ||
732 | /* PCI errors [4.15.2.4] */ | |
733 | if (unlikely ((status & STS_FATAL) != 0)) { | |
083522d7 BH |
734 | dbg_cmd (ehci, "fatal", ehci_readl(ehci, |
735 | &ehci->regs->command)); | |
1da177e4 LT |
736 | dbg_status (ehci, "fatal", status); |
737 | if (status & STS_HALT) { | |
738 | ehci_err (ehci, "fatal error\n"); | |
739 | dead: | |
740 | ehci_reset (ehci); | |
083522d7 | 741 | ehci_writel(ehci, 0, &ehci->regs->configured_flag); |
1da177e4 LT |
742 | /* generic layer kills/unlinks all urbs, then |
743 | * uses ehci_stop to clean up the rest | |
744 | */ | |
745 | bh = 1; | |
746 | } | |
747 | } | |
748 | ||
749 | if (bh) | |
7d12e780 | 750 | ehci_work (ehci); |
1da177e4 | 751 | spin_unlock (&ehci->lock); |
d1b1842c | 752 | if (pcd_status) |
1d619f12 | 753 | usb_hcd_poll_rh_status(hcd); |
1da177e4 LT |
754 | return IRQ_HANDLED; |
755 | } | |
756 | ||
757 | /*-------------------------------------------------------------------------*/ | |
758 | ||
759 | /* | |
760 | * non-error returns are a promise to giveback() the urb later | |
761 | * we drop ownership so next owner (or urb unlink) can get it | |
762 | * | |
763 | * urb + dev is in hcd.self.controller.urb_list | |
764 | * we're queueing TDs onto software and hardware lists | |
765 | * | |
766 | * hcd-specific init for hcpriv hasn't been done yet | |
767 | * | |
768 | * NOTE: control, bulk, and interrupt share the same code to append TDs | |
769 | * to a (possibly active) QH, and the same QH scanning code. | |
770 | */ | |
771 | static int ehci_urb_enqueue ( | |
772 | struct usb_hcd *hcd, | |
1da177e4 | 773 | struct urb *urb, |
55016f10 | 774 | gfp_t mem_flags |
1da177e4 LT |
775 | ) { |
776 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
777 | struct list_head qtd_list; | |
778 | ||
779 | INIT_LIST_HEAD (&qtd_list); | |
780 | ||
781 | switch (usb_pipetype (urb->pipe)) { | |
25b70a86 DB |
782 | case PIPE_CONTROL: |
783 | /* qh_completions() code doesn't handle all the fault cases | |
784 | * in multi-TD control transfers. Even 1KB is rare anyway. | |
785 | */ | |
786 | if (urb->transfer_buffer_length > (16 * 1024)) | |
787 | return -EMSGSIZE; | |
788 | /* FALLTHROUGH */ | |
789 | /* case PIPE_BULK: */ | |
1da177e4 LT |
790 | default: |
791 | if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags)) | |
792 | return -ENOMEM; | |
e9df41c5 | 793 | return submit_async(ehci, urb, &qtd_list, mem_flags); |
1da177e4 LT |
794 | |
795 | case PIPE_INTERRUPT: | |
796 | if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags)) | |
797 | return -ENOMEM; | |
e9df41c5 | 798 | return intr_submit(ehci, urb, &qtd_list, mem_flags); |
1da177e4 LT |
799 | |
800 | case PIPE_ISOCHRONOUS: | |
801 | if (urb->dev->speed == USB_SPEED_HIGH) | |
802 | return itd_submit (ehci, urb, mem_flags); | |
803 | else | |
804 | return sitd_submit (ehci, urb, mem_flags); | |
805 | } | |
806 | } | |
807 | ||
808 | static void unlink_async (struct ehci_hcd *ehci, struct ehci_qh *qh) | |
809 | { | |
07d29b63 | 810 | /* failfast */ |
e82cc128 | 811 | if (!HC_IS_RUNNING(ehci_to_hcd(ehci)->state) && ehci->reclaim) |
07d29b63 AS |
812 | end_unlink_async(ehci); |
813 | ||
814 | /* if it's not linked then there's nothing to do */ | |
815 | if (qh->qh_state != QH_STATE_LINKED) | |
816 | ; | |
817 | ||
818 | /* defer till later if busy */ | |
819 | else if (ehci->reclaim) { | |
1da177e4 LT |
820 | struct ehci_qh *last; |
821 | ||
822 | for (last = ehci->reclaim; | |
823 | last->reclaim; | |
824 | last = last->reclaim) | |
825 | continue; | |
826 | qh->qh_state = QH_STATE_UNLINK_WAIT; | |
827 | last->reclaim = qh; | |
828 | ||
07d29b63 AS |
829 | /* start IAA cycle */ |
830 | } else | |
1da177e4 LT |
831 | start_unlink_async (ehci, qh); |
832 | } | |
833 | ||
834 | /* remove from hardware lists | |
835 | * completions normally happen asynchronously | |
836 | */ | |
837 | ||
e9df41c5 | 838 | static int ehci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) |
1da177e4 LT |
839 | { |
840 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
841 | struct ehci_qh *qh; | |
842 | unsigned long flags; | |
e9df41c5 | 843 | int rc; |
1da177e4 LT |
844 | |
845 | spin_lock_irqsave (&ehci->lock, flags); | |
e9df41c5 AS |
846 | rc = usb_hcd_check_unlink_urb(hcd, urb, status); |
847 | if (rc) | |
848 | goto done; | |
849 | ||
1da177e4 LT |
850 | switch (usb_pipetype (urb->pipe)) { |
851 | // case PIPE_CONTROL: | |
852 | // case PIPE_BULK: | |
853 | default: | |
854 | qh = (struct ehci_qh *) urb->hcpriv; | |
855 | if (!qh) | |
856 | break; | |
07d29b63 AS |
857 | switch (qh->qh_state) { |
858 | case QH_STATE_LINKED: | |
859 | case QH_STATE_COMPLETING: | |
860 | unlink_async(ehci, qh); | |
861 | break; | |
862 | case QH_STATE_UNLINK: | |
863 | case QH_STATE_UNLINK_WAIT: | |
864 | /* already started */ | |
865 | break; | |
866 | case QH_STATE_IDLE: | |
867 | WARN_ON(1); | |
868 | break; | |
869 | } | |
1da177e4 LT |
870 | break; |
871 | ||
872 | case PIPE_INTERRUPT: | |
873 | qh = (struct ehci_qh *) urb->hcpriv; | |
874 | if (!qh) | |
875 | break; | |
876 | switch (qh->qh_state) { | |
877 | case QH_STATE_LINKED: | |
878 | intr_deschedule (ehci, qh); | |
879 | /* FALL THROUGH */ | |
880 | case QH_STATE_IDLE: | |
7d12e780 | 881 | qh_completions (ehci, qh); |
1da177e4 LT |
882 | break; |
883 | default: | |
884 | ehci_dbg (ehci, "bogus qh %p state %d\n", | |
885 | qh, qh->qh_state); | |
886 | goto done; | |
887 | } | |
888 | ||
889 | /* reschedule QH iff another request is queued */ | |
890 | if (!list_empty (&qh->qtd_list) | |
891 | && HC_IS_RUNNING (hcd->state)) { | |
e1a49142 DB |
892 | rc = qh_schedule(ehci, qh); |
893 | ||
894 | /* An error here likely indicates handshake failure | |
895 | * or no space left in the schedule. Neither fault | |
896 | * should happen often ... | |
897 | * | |
898 | * FIXME kill the now-dysfunctional queued urbs | |
899 | */ | |
900 | if (rc != 0) | |
901 | ehci_err(ehci, | |
902 | "can't reschedule qh %p, err %d", | |
903 | qh, rc); | |
1da177e4 LT |
904 | } |
905 | break; | |
906 | ||
907 | case PIPE_ISOCHRONOUS: | |
908 | // itd or sitd ... | |
909 | ||
910 | // wait till next completion, do it then. | |
911 | // completion irqs can wait up to 1024 msec, | |
912 | break; | |
913 | } | |
914 | done: | |
915 | spin_unlock_irqrestore (&ehci->lock, flags); | |
e9df41c5 | 916 | return rc; |
1da177e4 LT |
917 | } |
918 | ||
919 | /*-------------------------------------------------------------------------*/ | |
920 | ||
921 | // bulk qh holds the data toggle | |
922 | ||
923 | static void | |
924 | ehci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep) | |
925 | { | |
926 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
927 | unsigned long flags; | |
928 | struct ehci_qh *qh, *tmp; | |
929 | ||
930 | /* ASSERT: any requests/urbs are being unlinked */ | |
931 | /* ASSERT: nobody can be submitting urbs for this any more */ | |
932 | ||
933 | rescan: | |
934 | spin_lock_irqsave (&ehci->lock, flags); | |
935 | qh = ep->hcpriv; | |
936 | if (!qh) | |
937 | goto done; | |
938 | ||
939 | /* endpoints can be iso streams. for now, we don't | |
940 | * accelerate iso completions ... so spin a while. | |
941 | */ | |
942 | if (qh->hw_info1 == 0) { | |
943 | ehci_vdbg (ehci, "iso delay\n"); | |
944 | goto idle_timeout; | |
945 | } | |
946 | ||
947 | if (!HC_IS_RUNNING (hcd->state)) | |
948 | qh->qh_state = QH_STATE_IDLE; | |
949 | switch (qh->qh_state) { | |
950 | case QH_STATE_LINKED: | |
951 | for (tmp = ehci->async->qh_next.qh; | |
952 | tmp && tmp != qh; | |
953 | tmp = tmp->qh_next.qh) | |
954 | continue; | |
955 | /* periodic qh self-unlinks on empty */ | |
956 | if (!tmp) | |
957 | goto nogood; | |
958 | unlink_async (ehci, qh); | |
959 | /* FALL THROUGH */ | |
960 | case QH_STATE_UNLINK: /* wait for hw to finish? */ | |
07d29b63 | 961 | case QH_STATE_UNLINK_WAIT: |
1da177e4 LT |
962 | idle_timeout: |
963 | spin_unlock_irqrestore (&ehci->lock, flags); | |
22c43863 | 964 | schedule_timeout_uninterruptible(1); |
1da177e4 LT |
965 | goto rescan; |
966 | case QH_STATE_IDLE: /* fully unlinked */ | |
967 | if (list_empty (&qh->qtd_list)) { | |
968 | qh_put (qh); | |
969 | break; | |
970 | } | |
971 | /* else FALL THROUGH */ | |
972 | default: | |
973 | nogood: | |
974 | /* caller was supposed to have unlinked any requests; | |
975 | * that's not our job. just leak this memory. | |
976 | */ | |
977 | ehci_err (ehci, "qh %p (#%02x) state %d%s\n", | |
978 | qh, ep->desc.bEndpointAddress, qh->qh_state, | |
979 | list_empty (&qh->qtd_list) ? "" : "(has tds)"); | |
980 | break; | |
981 | } | |
982 | ep->hcpriv = NULL; | |
983 | done: | |
984 | spin_unlock_irqrestore (&ehci->lock, flags); | |
985 | return; | |
986 | } | |
987 | ||
7ff71d6a MP |
988 | static int ehci_get_frame (struct usb_hcd *hcd) |
989 | { | |
990 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
083522d7 BH |
991 | return (ehci_readl(ehci, &ehci->regs->frame_index) >> 3) % |
992 | ehci->periodic_size; | |
7ff71d6a | 993 | } |
1da177e4 LT |
994 | |
995 | /*-------------------------------------------------------------------------*/ | |
996 | ||
2b70f073 | 997 | MODULE_DESCRIPTION(DRIVER_DESC); |
1da177e4 LT |
998 | MODULE_AUTHOR (DRIVER_AUTHOR); |
999 | MODULE_LICENSE ("GPL"); | |
1000 | ||
7ff71d6a MP |
1001 | #ifdef CONFIG_PCI |
1002 | #include "ehci-pci.c" | |
01cced25 | 1003 | #define PCI_DRIVER ehci_pci_driver |
7ff71d6a | 1004 | #endif |
1da177e4 | 1005 | |
ba02978a | 1006 | #ifdef CONFIG_USB_EHCI_FSL |
80cb9aee | 1007 | #include "ehci-fsl.c" |
01cced25 | 1008 | #define PLATFORM_DRIVER ehci_fsl_driver |
80cb9aee RV |
1009 | #endif |
1010 | ||
dfbaa7d8 | 1011 | #ifdef CONFIG_SOC_AU1200 |
76fa9a24 | 1012 | #include "ehci-au1xxx.c" |
01cced25 | 1013 | #define PLATFORM_DRIVER ehci_hcd_au1xxx_driver |
76fa9a24 JC |
1014 | #endif |
1015 | ||
ad75a410 GL |
1016 | #ifdef CONFIG_PPC_PS3 |
1017 | #include "ehci-ps3.c" | |
7a4eb7fd | 1018 | #define PS3_SYSTEM_BUS_DRIVER ps3_ehci_driver |
ad75a410 GL |
1019 | #endif |
1020 | ||
da0e8fb0 VB |
1021 | #ifdef CONFIG_USB_EHCI_HCD_PPC_OF |
1022 | #include "ehci-ppc-of.c" | |
1023 | #define OF_PLATFORM_DRIVER ehci_hcd_ppc_of_driver | |
1024 | #endif | |
1025 | ||
705a7521 | 1026 | #ifdef CONFIG_PLAT_ORION |
e96ffe2f TP |
1027 | #include "ehci-orion.c" |
1028 | #define PLATFORM_DRIVER ehci_orion_driver | |
1029 | #endif | |
1030 | ||
91bc4d31 VB |
1031 | #ifdef CONFIG_ARCH_IXP4XX |
1032 | #include "ehci-ixp4xx.c" | |
1033 | #define PLATFORM_DRIVER ixp4xx_ehci_driver | |
1034 | #endif | |
1035 | ||
ad75a410 | 1036 | #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \ |
c6dd2e61 | 1037 | !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) |
7ff71d6a MP |
1038 | #error "missing bus glue for ehci-hcd" |
1039 | #endif | |
01cced25 KG |
1040 | |
1041 | static int __init ehci_hcd_init(void) | |
1042 | { | |
1043 | int retval = 0; | |
1044 | ||
2b70f073 AS |
1045 | if (usb_disabled()) |
1046 | return -ENODEV; | |
1047 | ||
1048 | printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name); | |
9beeee65 AS |
1049 | set_bit(USB_EHCI_LOADED, &usb_hcds_loaded); |
1050 | if (test_bit(USB_UHCI_LOADED, &usb_hcds_loaded) || | |
1051 | test_bit(USB_OHCI_LOADED, &usb_hcds_loaded)) | |
1052 | printk(KERN_WARNING "Warning! ehci_hcd should always be loaded" | |
1053 | " before uhci_hcd and ohci_hcd, not after\n"); | |
1054 | ||
01cced25 KG |
1055 | pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n", |
1056 | hcd_name, | |
1057 | sizeof(struct ehci_qh), sizeof(struct ehci_qtd), | |
1058 | sizeof(struct ehci_itd), sizeof(struct ehci_sitd)); | |
1059 | ||
694cc208 TJ |
1060 | #ifdef DEBUG |
1061 | ehci_debug_root = debugfs_create_dir("ehci", NULL); | |
9beeee65 AS |
1062 | if (!ehci_debug_root) { |
1063 | retval = -ENOENT; | |
1064 | goto err_debug; | |
1065 | } | |
694cc208 TJ |
1066 | #endif |
1067 | ||
01cced25 KG |
1068 | #ifdef PLATFORM_DRIVER |
1069 | retval = platform_driver_register(&PLATFORM_DRIVER); | |
da0e8fb0 VB |
1070 | if (retval < 0) |
1071 | goto clean0; | |
01cced25 KG |
1072 | #endif |
1073 | ||
1074 | #ifdef PCI_DRIVER | |
1075 | retval = pci_register_driver(&PCI_DRIVER); | |
da0e8fb0 VB |
1076 | if (retval < 0) |
1077 | goto clean1; | |
ad75a410 GL |
1078 | #endif |
1079 | ||
1080 | #ifdef PS3_SYSTEM_BUS_DRIVER | |
7a4eb7fd | 1081 | retval = ps3_ehci_driver_register(&PS3_SYSTEM_BUS_DRIVER); |
da0e8fb0 VB |
1082 | if (retval < 0) |
1083 | goto clean2; | |
694cc208 | 1084 | #endif |
da0e8fb0 VB |
1085 | |
1086 | #ifdef OF_PLATFORM_DRIVER | |
1087 | retval = of_register_platform_driver(&OF_PLATFORM_DRIVER); | |
1088 | if (retval < 0) | |
1089 | goto clean3; | |
1090 | #endif | |
1091 | return retval; | |
1092 | ||
1093 | #ifdef OF_PLATFORM_DRIVER | |
1094 | /* of_unregister_platform_driver(&OF_PLATFORM_DRIVER); */ | |
1095 | clean3: | |
1096 | #endif | |
1097 | #ifdef PS3_SYSTEM_BUS_DRIVER | |
1098 | ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); | |
1099 | clean2: | |
ad75a410 GL |
1100 | #endif |
1101 | #ifdef PCI_DRIVER | |
da0e8fb0 VB |
1102 | pci_unregister_driver(&PCI_DRIVER); |
1103 | clean1: | |
ad75a410 | 1104 | #endif |
da0e8fb0 VB |
1105 | #ifdef PLATFORM_DRIVER |
1106 | platform_driver_unregister(&PLATFORM_DRIVER); | |
1107 | clean0: | |
1108 | #endif | |
1109 | #ifdef DEBUG | |
1110 | debugfs_remove(ehci_debug_root); | |
1111 | ehci_debug_root = NULL; | |
01cced25 | 1112 | #endif |
9beeee65 AS |
1113 | err_debug: |
1114 | clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded); | |
01cced25 KG |
1115 | return retval; |
1116 | } | |
1117 | module_init(ehci_hcd_init); | |
1118 | ||
1119 | static void __exit ehci_hcd_cleanup(void) | |
1120 | { | |
da0e8fb0 VB |
1121 | #ifdef OF_PLATFORM_DRIVER |
1122 | of_unregister_platform_driver(&OF_PLATFORM_DRIVER); | |
1123 | #endif | |
01cced25 KG |
1124 | #ifdef PLATFORM_DRIVER |
1125 | platform_driver_unregister(&PLATFORM_DRIVER); | |
1126 | #endif | |
1127 | #ifdef PCI_DRIVER | |
1128 | pci_unregister_driver(&PCI_DRIVER); | |
1129 | #endif | |
ad75a410 | 1130 | #ifdef PS3_SYSTEM_BUS_DRIVER |
7a4eb7fd | 1131 | ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); |
ad75a410 | 1132 | #endif |
694cc208 TJ |
1133 | #ifdef DEBUG |
1134 | debugfs_remove(ehci_debug_root); | |
1135 | #endif | |
9beeee65 | 1136 | clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded); |
01cced25 KG |
1137 | } |
1138 | module_exit(ehci_hcd_cleanup); | |
1139 |