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Commit | Line | Data |
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1da177e4 | 1 | /* |
578333ab AS |
2 | * Enhanced Host Controller Interface (EHCI) driver for USB. |
3 | * | |
4 | * Maintainer: Alan Stern <stern@rowland.harvard.edu> | |
5 | * | |
1da177e4 | 6 | * Copyright (c) 2000-2004 by David Brownell |
53bd6a60 | 7 | * |
1da177e4 LT |
8 | * This program is free software; you can redistribute it and/or modify it |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | * for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software Foundation, | |
20 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
1da177e4 LT |
23 | #include <linux/module.h> |
24 | #include <linux/pci.h> | |
25 | #include <linux/dmapool.h> | |
26 | #include <linux/kernel.h> | |
27 | #include <linux/delay.h> | |
28 | #include <linux/ioport.h> | |
29 | #include <linux/sched.h> | |
3c04e20e | 30 | #include <linux/vmalloc.h> |
1da177e4 LT |
31 | #include <linux/errno.h> |
32 | #include <linux/init.h> | |
33 | #include <linux/timer.h> | |
ee4ecb8a | 34 | #include <linux/ktime.h> |
1da177e4 LT |
35 | #include <linux/list.h> |
36 | #include <linux/interrupt.h> | |
1da177e4 | 37 | #include <linux/usb.h> |
27729aad | 38 | #include <linux/usb/hcd.h> |
1da177e4 LT |
39 | #include <linux/moduleparam.h> |
40 | #include <linux/dma-mapping.h> | |
694cc208 | 41 | #include <linux/debugfs.h> |
5a0e3ad6 | 42 | #include <linux/slab.h> |
aa4d8342 | 43 | #include <linux/uaccess.h> |
1da177e4 | 44 | |
1da177e4 LT |
45 | #include <asm/byteorder.h> |
46 | #include <asm/io.h> | |
47 | #include <asm/irq.h> | |
48 | #include <asm/system.h> | |
49 | #include <asm/unaligned.h> | |
1da177e4 | 50 | |
df7c1ca2 GL |
51 | #if defined(CONFIG_PPC_PS3) |
52 | #include <asm/firmware.h> | |
53 | #endif | |
54 | ||
1da177e4 LT |
55 | /*-------------------------------------------------------------------------*/ |
56 | ||
57 | /* | |
58 | * EHCI hc_driver implementation ... experimental, incomplete. | |
59 | * Based on the final 1.0 register interface specification. | |
60 | * | |
61 | * USB 2.0 shows up in upcoming www.pcmcia.org technology. | |
62 | * First was PCMCIA, like ISA; then CardBus, which is PCI. | |
63 | * Next comes "CardBay", using USB 2.0 signals. | |
64 | * | |
65 | * Contains additional contributions by Brad Hards, Rory Bolt, and others. | |
66 | * Special thanks to Intel and VIA for providing host controllers to | |
67 | * test this driver on, and Cypress (including In-System Design) for | |
68 | * providing early devices for those host controllers to talk to! | |
1da177e4 LT |
69 | */ |
70 | ||
1da177e4 LT |
71 | #define DRIVER_AUTHOR "David Brownell" |
72 | #define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver" | |
73 | ||
74 | static const char hcd_name [] = "ehci_hcd"; | |
75 | ||
76 | ||
9776afc8 | 77 | #undef VERBOSE_DEBUG |
1da177e4 LT |
78 | #undef EHCI_URB_TRACE |
79 | ||
80 | #ifdef DEBUG | |
81 | #define EHCI_STATS | |
82 | #endif | |
83 | ||
84 | /* magic numbers that can affect system performance */ | |
85 | #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */ | |
86 | #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */ | |
87 | #define EHCI_TUNE_RL_TT 0 | |
88 | #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */ | |
89 | #define EHCI_TUNE_MULT_TT 1 | |
ffda0803 AS |
90 | /* |
91 | * Some drivers think it's safe to schedule isochronous transfers more than | |
92 | * 256 ms into the future (partly as a result of an old bug in the scheduling | |
93 | * code). In an attempt to avoid trouble, we will use a minimum scheduling | |
94 | * length of 512 frames instead of 256. | |
95 | */ | |
96 | #define EHCI_TUNE_FLS 1 /* (medium) 512-frame schedule */ | |
1da177e4 | 97 | |
07d29b63 | 98 | #define EHCI_IAA_MSECS 10 /* arbitrary */ |
1da177e4 LT |
99 | #define EHCI_IO_JIFFIES (HZ/10) /* io watchdog > irq_thresh */ |
100 | #define EHCI_ASYNC_JIFFIES (HZ/20) /* async idle timeout */ | |
004c1968 | 101 | #define EHCI_SHRINK_JIFFIES (DIV_ROUND_UP(HZ, 200) + 1) |
fcda37cb | 102 | /* 5-ms async qh unlink delay */ |
1da177e4 LT |
103 | |
104 | /* Initial IRQ latency: faster than hw default */ | |
105 | static int log2_irq_thresh = 0; // 0 to 6 | |
106 | module_param (log2_irq_thresh, int, S_IRUGO); | |
107 | MODULE_PARM_DESC (log2_irq_thresh, "log2 IRQ latency, 1-64 microframes"); | |
108 | ||
109 | /* initial park setting: slower than hw default */ | |
110 | static unsigned park = 0; | |
111 | module_param (park, uint, S_IRUGO); | |
112 | MODULE_PARM_DESC (park, "park setting; 1-3 back-to-back async packets"); | |
113 | ||
93f1a47c DB |
114 | /* for flakey hardware, ignore overcurrent indicators */ |
115 | static int ignore_oc = 0; | |
116 | module_param (ignore_oc, bool, S_IRUGO); | |
117 | MODULE_PARM_DESC (ignore_oc, "ignore bogus hardware overcurrent indications"); | |
118 | ||
48f24970 AD |
119 | /* for link power management(LPM) feature */ |
120 | static unsigned int hird; | |
121 | module_param(hird, int, S_IRUGO); | |
cc556871 | 122 | MODULE_PARM_DESC(hird, "host initiated resume duration, +1 for each 75us"); |
48f24970 | 123 | |
1da177e4 LT |
124 | #define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT) |
125 | ||
126 | /*-------------------------------------------------------------------------*/ | |
127 | ||
128 | #include "ehci.h" | |
129 | #include "ehci-dbg.c" | |
ad93562b | 130 | #include "pci-quirks.h" |
1da177e4 LT |
131 | |
132 | /*-------------------------------------------------------------------------*/ | |
133 | ||
bc29847e AS |
134 | static void |
135 | timer_action(struct ehci_hcd *ehci, enum ehci_timer_action action) | |
136 | { | |
137 | /* Don't override timeouts which shrink or (later) disable | |
138 | * the async ring; just the I/O watchdog. Note that if a | |
139 | * SHRINK were pending, OFF would never be requested. | |
140 | */ | |
141 | if (timer_pending(&ehci->watchdog) | |
142 | && ((BIT(TIMER_ASYNC_SHRINK) | BIT(TIMER_ASYNC_OFF)) | |
143 | & ehci->actions)) | |
144 | return; | |
145 | ||
146 | if (!test_and_set_bit(action, &ehci->actions)) { | |
147 | unsigned long t; | |
148 | ||
149 | switch (action) { | |
150 | case TIMER_IO_WATCHDOG: | |
403dbd36 AD |
151 | if (!ehci->need_io_watchdog) |
152 | return; | |
bc29847e AS |
153 | t = EHCI_IO_JIFFIES; |
154 | break; | |
155 | case TIMER_ASYNC_OFF: | |
156 | t = EHCI_ASYNC_JIFFIES; | |
157 | break; | |
158 | /* case TIMER_ASYNC_SHRINK: */ | |
159 | default: | |
004c1968 | 160 | t = EHCI_SHRINK_JIFFIES; |
bc29847e AS |
161 | break; |
162 | } | |
163 | mod_timer(&ehci->watchdog, t + jiffies); | |
164 | } | |
165 | } | |
166 | ||
167 | /*-------------------------------------------------------------------------*/ | |
168 | ||
1da177e4 LT |
169 | /* |
170 | * handshake - spin reading hc until handshake completes or fails | |
171 | * @ptr: address of hc register to be read | |
172 | * @mask: bits to look at in result of read | |
173 | * @done: value of those bits when handshake succeeds | |
174 | * @usec: timeout in microseconds | |
175 | * | |
176 | * Returns negative errno, or zero on success | |
177 | * | |
178 | * Success happens when the "mask" bits have the specified value (hardware | |
179 | * handshake done). There are two failure modes: "usec" have passed (major | |
180 | * hardware flakeout), or the register reads as all-ones (hardware removed). | |
181 | * | |
182 | * That last failure should_only happen in cases like physical cardbus eject | |
183 | * before driver shutdown. But it also seems to be caused by bugs in cardbus | |
184 | * bridge shutdown: shutting down the bridge before the devices using it. | |
185 | */ | |
083522d7 BH |
186 | static int handshake (struct ehci_hcd *ehci, void __iomem *ptr, |
187 | u32 mask, u32 done, int usec) | |
1da177e4 LT |
188 | { |
189 | u32 result; | |
190 | ||
191 | do { | |
083522d7 | 192 | result = ehci_readl(ehci, ptr); |
1da177e4 LT |
193 | if (result == ~(u32)0) /* card removed */ |
194 | return -ENODEV; | |
195 | result &= mask; | |
196 | if (result == done) | |
197 | return 0; | |
198 | udelay (1); | |
199 | usec--; | |
200 | } while (usec > 0); | |
201 | return -ETIMEDOUT; | |
202 | } | |
203 | ||
65fd4272 MC |
204 | /* check TDI/ARC silicon is in host mode */ |
205 | static int tdi_in_host_mode (struct ehci_hcd *ehci) | |
206 | { | |
207 | u32 __iomem *reg_ptr; | |
208 | u32 tmp; | |
209 | ||
210 | reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + USBMODE); | |
211 | tmp = ehci_readl(ehci, reg_ptr); | |
212 | return (tmp & 3) == USBMODE_CM_HC; | |
213 | } | |
214 | ||
1da177e4 LT |
215 | /* force HC to halt state from unknown (EHCI spec section 2.3) */ |
216 | static int ehci_halt (struct ehci_hcd *ehci) | |
217 | { | |
083522d7 | 218 | u32 temp = ehci_readl(ehci, &ehci->regs->status); |
1da177e4 | 219 | |
72f30b6f | 220 | /* disable any irqs left enabled by previous code */ |
083522d7 | 221 | ehci_writel(ehci, 0, &ehci->regs->intr_enable); |
72f30b6f | 222 | |
65fd4272 MC |
223 | if (ehci_is_TDI(ehci) && tdi_in_host_mode(ehci) == 0) { |
224 | return 0; | |
225 | } | |
226 | ||
1da177e4 LT |
227 | if ((temp & STS_HALT) != 0) |
228 | return 0; | |
229 | ||
083522d7 | 230 | temp = ehci_readl(ehci, &ehci->regs->command); |
1da177e4 | 231 | temp &= ~CMD_RUN; |
083522d7 BH |
232 | ehci_writel(ehci, temp, &ehci->regs->command); |
233 | return handshake (ehci, &ehci->regs->status, | |
234 | STS_HALT, STS_HALT, 16 * 125); | |
1da177e4 LT |
235 | } |
236 | ||
df7c1ca2 GL |
237 | #if defined(CONFIG_USB_SUSPEND) && defined(CONFIG_PPC_PS3) |
238 | ||
239 | /* | |
240 | * The EHCI controller of the Cell Super Companion Chip used in the | |
241 | * PS3 will stop the root hub after all root hub ports are suspended. | |
242 | * When in this condition handshake will return -ETIMEDOUT. The | |
243 | * STS_HLT bit will not be set, so inspection of the frame index is | |
244 | * used here to test for the condition. If the condition is found | |
245 | * return success to allow the USB suspend to complete. | |
246 | */ | |
247 | ||
248 | static int handshake_for_broken_root_hub(struct ehci_hcd *ehci, | |
249 | void __iomem *ptr, u32 mask, u32 done, | |
250 | int usec) | |
251 | { | |
252 | unsigned int old_index; | |
253 | int error; | |
254 | ||
255 | if (!firmware_has_feature(FW_FEATURE_PS3_LV1)) | |
256 | return -ETIMEDOUT; | |
257 | ||
258 | old_index = ehci_read_frame_index(ehci); | |
259 | ||
260 | error = handshake(ehci, ptr, mask, done, usec); | |
261 | ||
262 | if (error == -ETIMEDOUT && ehci_read_frame_index(ehci) == old_index) | |
263 | return 0; | |
264 | ||
265 | return error; | |
266 | } | |
267 | ||
268 | #else | |
269 | ||
270 | static int handshake_for_broken_root_hub(struct ehci_hcd *ehci, | |
271 | void __iomem *ptr, u32 mask, u32 done, | |
272 | int usec) | |
273 | { | |
274 | return -ETIMEDOUT; | |
275 | } | |
276 | ||
277 | #endif | |
278 | ||
0bcfeb3e DB |
279 | static int handshake_on_error_set_halt(struct ehci_hcd *ehci, void __iomem *ptr, |
280 | u32 mask, u32 done, int usec) | |
281 | { | |
282 | int error; | |
283 | ||
284 | error = handshake(ehci, ptr, mask, done, usec); | |
df7c1ca2 GL |
285 | if (error == -ETIMEDOUT) |
286 | error = handshake_for_broken_root_hub(ehci, ptr, mask, done, | |
287 | usec); | |
288 | ||
0bcfeb3e DB |
289 | if (error) { |
290 | ehci_halt(ehci); | |
e8799906 | 291 | ehci->rh_state = EHCI_RH_HALTED; |
65cb76ba | 292 | ehci_err(ehci, "force halt; handshake %p %08x %08x -> %d\n", |
0bcfeb3e DB |
293 | ptr, mask, done, error); |
294 | } | |
295 | ||
296 | return error; | |
297 | } | |
298 | ||
1da177e4 LT |
299 | /* put TDI/ARC silicon into EHCI mode */ |
300 | static void tdi_reset (struct ehci_hcd *ehci) | |
301 | { | |
302 | u32 __iomem *reg_ptr; | |
303 | u32 tmp; | |
304 | ||
d23a1377 | 305 | reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + USBMODE); |
083522d7 | 306 | tmp = ehci_readl(ehci, reg_ptr); |
d23a1377 VB |
307 | tmp |= USBMODE_CM_HC; |
308 | /* The default byte access to MMR space is LE after | |
309 | * controller reset. Set the required endian mode | |
310 | * for transfer buffers to match the host microprocessor | |
311 | */ | |
312 | if (ehci_big_endian_mmio(ehci)) | |
313 | tmp |= USBMODE_BE; | |
083522d7 | 314 | ehci_writel(ehci, tmp, reg_ptr); |
1da177e4 LT |
315 | } |
316 | ||
317 | /* reset a non-running (STS_HALT == 1) controller */ | |
318 | static int ehci_reset (struct ehci_hcd *ehci) | |
319 | { | |
320 | int retval; | |
083522d7 | 321 | u32 command = ehci_readl(ehci, &ehci->regs->command); |
1da177e4 | 322 | |
8d053c79 JW |
323 | /* If the EHCI debug controller is active, special care must be |
324 | * taken before and after a host controller reset */ | |
325 | if (ehci->debug && !dbgp_reset_prep()) | |
326 | ehci->debug = NULL; | |
327 | ||
1da177e4 LT |
328 | command |= CMD_RESET; |
329 | dbg_cmd (ehci, "reset", command); | |
083522d7 | 330 | ehci_writel(ehci, command, &ehci->regs->command); |
e8799906 | 331 | ehci->rh_state = EHCI_RH_HALTED; |
1da177e4 | 332 | ehci->next_statechange = jiffies; |
083522d7 BH |
333 | retval = handshake (ehci, &ehci->regs->command, |
334 | CMD_RESET, 0, 250 * 1000); | |
1da177e4 | 335 | |
331ac6b2 AD |
336 | if (ehci->has_hostpc) { |
337 | ehci_writel(ehci, USBMODE_EX_HC | USBMODE_EX_VBPS, | |
338 | (u32 __iomem *)(((u8 *)ehci->regs) + USBMODE_EX)); | |
339 | ehci_writel(ehci, TXFIFO_DEFAULT, | |
340 | (u32 __iomem *)(((u8 *)ehci->regs) + TXFILLTUNING)); | |
341 | } | |
1da177e4 LT |
342 | if (retval) |
343 | return retval; | |
344 | ||
345 | if (ehci_is_TDI(ehci)) | |
346 | tdi_reset (ehci); | |
347 | ||
8d053c79 JW |
348 | if (ehci->debug) |
349 | dbgp_external_startup(); | |
350 | ||
1da177e4 LT |
351 | return retval; |
352 | } | |
353 | ||
354 | /* idle the controller (from running) */ | |
355 | static void ehci_quiesce (struct ehci_hcd *ehci) | |
356 | { | |
357 | u32 temp; | |
358 | ||
359 | #ifdef DEBUG | |
e8799906 | 360 | if (ehci->rh_state != EHCI_RH_RUNNING) |
1da177e4 LT |
361 | BUG (); |
362 | #endif | |
363 | ||
364 | /* wait for any schedule enables/disables to take effect */ | |
083522d7 | 365 | temp = ehci_readl(ehci, &ehci->regs->command) << 10; |
1da177e4 | 366 | temp &= STS_ASS | STS_PSS; |
c765d4ca KW |
367 | if (handshake_on_error_set_halt(ehci, &ehci->regs->status, |
368 | STS_ASS | STS_PSS, temp, 16 * 125)) | |
1da177e4 | 369 | return; |
1da177e4 LT |
370 | |
371 | /* then disable anything that's still active */ | |
083522d7 | 372 | temp = ehci_readl(ehci, &ehci->regs->command); |
1da177e4 | 373 | temp &= ~(CMD_ASE | CMD_IAAD | CMD_PSE); |
083522d7 | 374 | ehci_writel(ehci, temp, &ehci->regs->command); |
1da177e4 LT |
375 | |
376 | /* hardware can take 16 microframes to turn off ... */ | |
c765d4ca KW |
377 | handshake_on_error_set_halt(ehci, &ehci->regs->status, |
378 | STS_ASS | STS_PSS, 0, 16 * 125); | |
1da177e4 LT |
379 | } |
380 | ||
381 | /*-------------------------------------------------------------------------*/ | |
382 | ||
07d29b63 | 383 | static void end_unlink_async(struct ehci_hcd *ehci); |
7d12e780 | 384 | static void ehci_work(struct ehci_hcd *ehci); |
1da177e4 LT |
385 | |
386 | #include "ehci-hub.c" | |
48f24970 | 387 | #include "ehci-lpm.c" |
1da177e4 LT |
388 | #include "ehci-mem.c" |
389 | #include "ehci-q.c" | |
390 | #include "ehci-sched.c" | |
4c67045b | 391 | #include "ehci-sysfs.c" |
1da177e4 LT |
392 | |
393 | /*-------------------------------------------------------------------------*/ | |
394 | ||
07d29b63 | 395 | static void ehci_iaa_watchdog(unsigned long param) |
1da177e4 LT |
396 | { |
397 | struct ehci_hcd *ehci = (struct ehci_hcd *) param; | |
398 | unsigned long flags; | |
399 | ||
400 | spin_lock_irqsave (&ehci->lock, flags); | |
401 | ||
e82cc128 DB |
402 | /* Lost IAA irqs wedge things badly; seen first with a vt8235. |
403 | * So we need this watchdog, but must protect it against both | |
404 | * (a) SMP races against real IAA firing and retriggering, and | |
405 | * (b) clean HC shutdown, when IAA watchdog was pending. | |
406 | */ | |
407 | if (ehci->reclaim | |
408 | && !timer_pending(&ehci->iaa_watchdog) | |
e8799906 | 409 | && ehci->rh_state == EHCI_RH_RUNNING) { |
e82cc128 DB |
410 | u32 cmd, status; |
411 | ||
412 | /* If we get here, IAA is *REALLY* late. It's barely | |
413 | * conceivable that the system is so busy that CMD_IAAD | |
414 | * is still legitimately set, so let's be sure it's | |
415 | * clear before we read STS_IAA. (The HC should clear | |
416 | * CMD_IAAD when it sets STS_IAA.) | |
417 | */ | |
418 | cmd = ehci_readl(ehci, &ehci->regs->command); | |
419 | if (cmd & CMD_IAAD) | |
420 | ehci_writel(ehci, cmd & ~CMD_IAAD, | |
421 | &ehci->regs->command); | |
422 | ||
423 | /* If IAA is set here it either legitimately triggered | |
424 | * before we cleared IAAD above (but _way_ late, so we'll | |
425 | * still count it as lost) ... or a silicon erratum: | |
426 | * - VIA seems to set IAA without triggering the IRQ; | |
427 | * - IAAD potentially cleared without setting IAA. | |
428 | */ | |
429 | status = ehci_readl(ehci, &ehci->regs->status); | |
430 | if ((status & STS_IAA) || !(cmd & CMD_IAAD)) { | |
1da177e4 | 431 | COUNT (ehci->stats.lost_iaa); |
083522d7 | 432 | ehci_writel(ehci, STS_IAA, &ehci->regs->status); |
1da177e4 | 433 | } |
e82cc128 DB |
434 | |
435 | ehci_vdbg(ehci, "IAA watchdog: status %x cmd %x\n", | |
436 | status, cmd); | |
07d29b63 | 437 | end_unlink_async(ehci); |
1da177e4 LT |
438 | } |
439 | ||
07d29b63 AS |
440 | spin_unlock_irqrestore(&ehci->lock, flags); |
441 | } | |
442 | ||
443 | static void ehci_watchdog(unsigned long param) | |
444 | { | |
445 | struct ehci_hcd *ehci = (struct ehci_hcd *) param; | |
446 | unsigned long flags; | |
447 | ||
448 | spin_lock_irqsave(&ehci->lock, flags); | |
449 | ||
450 | /* stop async processing after it's idled a bit */ | |
1da177e4 | 451 | if (test_bit (TIMER_ASYNC_OFF, &ehci->actions)) |
26f953fd | 452 | start_unlink_async (ehci, ehci->async); |
1da177e4 LT |
453 | |
454 | /* ehci could run by timer, without IRQs ... */ | |
7d12e780 | 455 | ehci_work (ehci); |
1da177e4 LT |
456 | |
457 | spin_unlock_irqrestore (&ehci->lock, flags); | |
458 | } | |
459 | ||
8903795a AS |
460 | /* On some systems, leaving remote wakeup enabled prevents system shutdown. |
461 | * The firmware seems to think that powering off is a wakeup event! | |
462 | * This routine turns off remote wakeup and everything else, on all ports. | |
463 | */ | |
464 | static void ehci_turn_off_all_ports(struct ehci_hcd *ehci) | |
465 | { | |
466 | int port = HCS_N_PORTS(ehci->hcs_params); | |
467 | ||
468 | while (port--) | |
469 | ehci_writel(ehci, PORT_RWC_BITS, | |
470 | &ehci->regs->port_status[port]); | |
471 | } | |
472 | ||
21da84a8 SS |
473 | /* |
474 | * Halt HC, turn off all ports, and let the BIOS use the companion controllers. | |
475 | * Should be called with ehci->lock held. | |
72f30b6f | 476 | */ |
21da84a8 | 477 | static void ehci_silence_controller(struct ehci_hcd *ehci) |
1da177e4 | 478 | { |
21da84a8 | 479 | ehci_halt(ehci); |
8903795a | 480 | ehci_turn_off_all_ports(ehci); |
1da177e4 LT |
481 | |
482 | /* make BIOS/etc use companion controller during reboot */ | |
083522d7 | 483 | ehci_writel(ehci, 0, &ehci->regs->configured_flag); |
8903795a AS |
484 | |
485 | /* unblock posted writes */ | |
486 | ehci_readl(ehci, &ehci->regs->configured_flag); | |
1da177e4 LT |
487 | } |
488 | ||
21da84a8 SS |
489 | /* ehci_shutdown kick in for silicon on any bus (not just pci, etc). |
490 | * This forcibly disables dma and IRQs, helping kexec and other cases | |
491 | * where the next system software may expect clean state. | |
492 | */ | |
493 | static void ehci_shutdown(struct usb_hcd *hcd) | |
494 | { | |
495 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | |
496 | ||
497 | del_timer_sync(&ehci->watchdog); | |
498 | del_timer_sync(&ehci->iaa_watchdog); | |
499 | ||
500 | spin_lock_irq(&ehci->lock); | |
501 | ehci_silence_controller(ehci); | |
502 | spin_unlock_irq(&ehci->lock); | |
503 | } | |
504 | ||
56c1e26d DB |
505 | static void ehci_port_power (struct ehci_hcd *ehci, int is_on) |
506 | { | |
507 | unsigned port; | |
508 | ||
509 | if (!HCS_PPC (ehci->hcs_params)) | |
510 | return; | |
511 | ||
512 | ehci_dbg (ehci, "...power%s ports...\n", is_on ? "up" : "down"); | |
513 | for (port = HCS_N_PORTS (ehci->hcs_params); port > 0; ) | |
514 | (void) ehci_hub_control(ehci_to_hcd(ehci), | |
515 | is_on ? SetPortFeature : ClearPortFeature, | |
516 | USB_PORT_FEAT_POWER, | |
517 | port--, NULL, 0); | |
383975d7 AS |
518 | /* Flush those writes */ |
519 | ehci_readl(ehci, &ehci->regs->command); | |
56c1e26d DB |
520 | msleep(20); |
521 | } | |
522 | ||
7ff71d6a | 523 | /*-------------------------------------------------------------------------*/ |
1da177e4 | 524 | |
7ff71d6a MP |
525 | /* |
526 | * ehci_work is called from some interrupts, timers, and so on. | |
527 | * it calls driver completion functions, after dropping ehci->lock. | |
528 | */ | |
7d12e780 | 529 | static void ehci_work (struct ehci_hcd *ehci) |
7ff71d6a MP |
530 | { |
531 | timer_action_done (ehci, TIMER_IO_WATCHDOG); | |
7ff71d6a MP |
532 | |
533 | /* another CPU may drop ehci->lock during a schedule scan while | |
534 | * it reports urb completions. this flag guards against bogus | |
535 | * attempts at re-entrant schedule scanning. | |
536 | */ | |
537 | if (ehci->scanning) | |
538 | return; | |
539 | ehci->scanning = 1; | |
7d12e780 | 540 | scan_async (ehci); |
7ff71d6a | 541 | if (ehci->next_uframe != -1) |
7d12e780 | 542 | scan_periodic (ehci); |
7ff71d6a MP |
543 | ehci->scanning = 0; |
544 | ||
545 | /* the IO watchdog guards against hardware or driver bugs that | |
546 | * misplace IRQs, and should let us run completely without IRQs. | |
547 | * such lossage has been observed on both VT6202 and VT8235. | |
548 | */ | |
e8799906 | 549 | if (ehci->rh_state == EHCI_RH_RUNNING && |
7ff71d6a MP |
550 | (ehci->async->qh_next.ptr != NULL || |
551 | ehci->periodic_sched != 0)) | |
552 | timer_action (ehci, TIMER_IO_WATCHDOG); | |
553 | } | |
1da177e4 | 554 | |
21da84a8 SS |
555 | /* |
556 | * Called when the ehci_hcd module is removed. | |
557 | */ | |
7ff71d6a | 558 | static void ehci_stop (struct usb_hcd *hcd) |
1da177e4 LT |
559 | { |
560 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
1da177e4 | 561 | |
7ff71d6a | 562 | ehci_dbg (ehci, "stop\n"); |
1da177e4 | 563 | |
7ff71d6a MP |
564 | /* no more interrupts ... */ |
565 | del_timer_sync (&ehci->watchdog); | |
07d29b63 | 566 | del_timer_sync(&ehci->iaa_watchdog); |
56c1e26d | 567 | |
7ff71d6a | 568 | spin_lock_irq(&ehci->lock); |
e8799906 | 569 | if (ehci->rh_state == EHCI_RH_RUNNING) |
7ff71d6a | 570 | ehci_quiesce (ehci); |
1da177e4 | 571 | |
21da84a8 | 572 | ehci_silence_controller(ehci); |
7ff71d6a | 573 | ehci_reset (ehci); |
7ff71d6a | 574 | spin_unlock_irq(&ehci->lock); |
1da177e4 | 575 | |
4c67045b | 576 | remove_sysfs_files(ehci); |
7ff71d6a | 577 | remove_debug_files (ehci); |
1da177e4 | 578 | |
7ff71d6a MP |
579 | /* root hub is shut down separately (first, when possible) */ |
580 | spin_lock_irq (&ehci->lock); | |
581 | if (ehci->async) | |
7d12e780 | 582 | ehci_work (ehci); |
7ff71d6a MP |
583 | spin_unlock_irq (&ehci->lock); |
584 | ehci_mem_cleanup (ehci); | |
1da177e4 | 585 | |
ad93562b AX |
586 | if (ehci->amd_pll_fix == 1) |
587 | usb_amd_dev_put(); | |
05570297 | 588 | |
7ff71d6a MP |
589 | #ifdef EHCI_STATS |
590 | ehci_dbg (ehci, "irq normal %ld err %ld reclaim %ld (lost %ld)\n", | |
591 | ehci->stats.normal, ehci->stats.error, ehci->stats.reclaim, | |
592 | ehci->stats.lost_iaa); | |
593 | ehci_dbg (ehci, "complete %ld unlink %ld\n", | |
594 | ehci->stats.complete, ehci->stats.unlink); | |
1da177e4 | 595 | #endif |
1da177e4 | 596 | |
083522d7 BH |
597 | dbg_status (ehci, "ehci_stop completed", |
598 | ehci_readl(ehci, &ehci->regs->status)); | |
1da177e4 LT |
599 | } |
600 | ||
18807521 DB |
601 | /* one-time init, only for memory state */ |
602 | static int ehci_init(struct usb_hcd *hcd) | |
1da177e4 | 603 | { |
18807521 | 604 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); |
1da177e4 | 605 | u32 temp; |
1da177e4 LT |
606 | int retval; |
607 | u32 hcc_params; | |
3807e26d | 608 | struct ehci_qh_hw *hw; |
18807521 DB |
609 | |
610 | spin_lock_init(&ehci->lock); | |
611 | ||
403dbd36 AD |
612 | /* |
613 | * keep io watchdog by default, those good HCDs could turn off it later | |
614 | */ | |
615 | ehci->need_io_watchdog = 1; | |
18807521 DB |
616 | init_timer(&ehci->watchdog); |
617 | ehci->watchdog.function = ehci_watchdog; | |
618 | ehci->watchdog.data = (unsigned long) ehci; | |
1da177e4 | 619 | |
07d29b63 AS |
620 | init_timer(&ehci->iaa_watchdog); |
621 | ehci->iaa_watchdog.function = ehci_iaa_watchdog; | |
622 | ehci->iaa_watchdog.data = (unsigned long) ehci; | |
623 | ||
f75593ce AS |
624 | hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params); |
625 | ||
cc62a7eb KS |
626 | /* |
627 | * by default set standard 80% (== 100 usec/uframe) max periodic | |
628 | * bandwidth as required by USB 2.0 | |
629 | */ | |
630 | ehci->uframe_periodic_max = 100; | |
631 | ||
1da177e4 LT |
632 | /* |
633 | * hw default: 1K periodic list heads, one per frame. | |
634 | * periodic_size can shrink by USBCMD update if hcc_params allows. | |
635 | */ | |
636 | ehci->periodic_size = DEFAULT_I_TDPS; | |
9aa09d2f | 637 | INIT_LIST_HEAD(&ehci->cached_itd_list); |
0e5f231b | 638 | INIT_LIST_HEAD(&ehci->cached_sitd_list); |
f75593ce AS |
639 | |
640 | if (HCC_PGM_FRAMELISTLEN(hcc_params)) { | |
641 | /* periodic schedule size can be smaller than default */ | |
642 | switch (EHCI_TUNE_FLS) { | |
643 | case 0: ehci->periodic_size = 1024; break; | |
644 | case 1: ehci->periodic_size = 512; break; | |
645 | case 2: ehci->periodic_size = 256; break; | |
646 | default: BUG(); | |
647 | } | |
648 | } | |
18807521 | 649 | if ((retval = ehci_mem_init(ehci, GFP_KERNEL)) < 0) |
1da177e4 LT |
650 | return retval; |
651 | ||
652 | /* controllers may cache some of the periodic schedule ... */ | |
53bd6a60 | 653 | if (HCC_ISOC_CACHE(hcc_params)) // full frame cache |
dccd574c | 654 | ehci->i_thresh = 2 + 8; |
1da177e4 | 655 | else // N microframes cached |
18807521 | 656 | ehci->i_thresh = 2 + HCC_ISOC_THRES(hcc_params); |
1da177e4 LT |
657 | |
658 | ehci->reclaim = NULL; | |
1da177e4 | 659 | ehci->next_uframe = -1; |
9aa09d2f | 660 | ehci->clock_frame = -1; |
1da177e4 | 661 | |
1da177e4 LT |
662 | /* |
663 | * dedicate a qh for the async ring head, since we couldn't unlink | |
664 | * a 'real' qh without stopping the async schedule [4.8]. use it | |
665 | * as the 'reclamation list head' too. | |
666 | * its dummy is used in hw_alt_next of many tds, to prevent the qh | |
667 | * from automatically advancing to the next td after short reads. | |
668 | */ | |
18807521 | 669 | ehci->async->qh_next.qh = NULL; |
3807e26d AD |
670 | hw = ehci->async->hw; |
671 | hw->hw_next = QH_NEXT(ehci, ehci->async->qh_dma); | |
672 | hw->hw_info1 = cpu_to_hc32(ehci, QH_HEAD); | |
aaa0ef28 | 673 | hw->hw_info1 |= cpu_to_hc32(ehci, (1 << 7)); /* I = 1 */ |
3807e26d AD |
674 | hw->hw_token = cpu_to_hc32(ehci, QTD_STS_HALT); |
675 | hw->hw_qtd_next = EHCI_LIST_END(ehci); | |
18807521 | 676 | ehci->async->qh_state = QH_STATE_LINKED; |
3807e26d | 677 | hw->hw_alt_next = QTD_NEXT(ehci, ehci->async->dummy->qtd_dma); |
1da177e4 LT |
678 | |
679 | /* clear interrupt enables, set irq latency */ | |
680 | if (log2_irq_thresh < 0 || log2_irq_thresh > 6) | |
681 | log2_irq_thresh = 0; | |
682 | temp = 1 << (16 + log2_irq_thresh); | |
5a9cdf33 AD |
683 | if (HCC_PER_PORT_CHANGE_EVENT(hcc_params)) { |
684 | ehci->has_ppcd = 1; | |
685 | ehci_dbg(ehci, "enable per-port change event\n"); | |
686 | temp |= CMD_PPCEE; | |
687 | } | |
1da177e4 LT |
688 | if (HCC_CANPARK(hcc_params)) { |
689 | /* HW default park == 3, on hardware that supports it (like | |
690 | * NVidia and ALI silicon), maximizes throughput on the async | |
691 | * schedule by avoiding QH fetches between transfers. | |
692 | * | |
693 | * With fast usb storage devices and NForce2, "park" seems to | |
694 | * make problems: throughput reduction (!), data errors... | |
695 | */ | |
696 | if (park) { | |
18807521 | 697 | park = min(park, (unsigned) 3); |
1da177e4 LT |
698 | temp |= CMD_PARK; |
699 | temp |= park << 8; | |
700 | } | |
18807521 | 701 | ehci_dbg(ehci, "park %d\n", park); |
1da177e4 | 702 | } |
18807521 | 703 | if (HCC_PGM_FRAMELISTLEN(hcc_params)) { |
1da177e4 LT |
704 | /* periodic schedule size can be smaller than default */ |
705 | temp &= ~(3 << 2); | |
706 | temp |= (EHCI_TUNE_FLS << 2); | |
1da177e4 | 707 | } |
48f24970 AD |
708 | if (HCC_LPM(hcc_params)) { |
709 | /* support link power management EHCI 1.1 addendum */ | |
710 | ehci_dbg(ehci, "support lpm\n"); | |
711 | ehci->has_lpm = 1; | |
712 | if (hird > 0xf) { | |
713 | ehci_dbg(ehci, "hird %d invalid, use default 0", | |
714 | hird); | |
715 | hird = 0; | |
716 | } | |
717 | temp |= hird << 24; | |
718 | } | |
18807521 DB |
719 | ehci->command = temp; |
720 | ||
40f8db8f | 721 | /* Accept arbitrarily long scatter-gather lists */ |
4307a28e AR |
722 | if (!(hcd->driver->flags & HCD_LOCAL_MEM)) |
723 | hcd->self.sg_tablesize = ~0; | |
18807521 DB |
724 | return 0; |
725 | } | |
726 | ||
727 | /* start HC running; it's halted, ehci_init() has been run (once) */ | |
728 | static int ehci_run (struct usb_hcd *hcd) | |
729 | { | |
730 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
18807521 DB |
731 | u32 temp; |
732 | u32 hcc_params; | |
733 | ||
1d619f12 | 734 | hcd->uses_new_polling = 1; |
1d619f12 | 735 | |
18807521 | 736 | /* EHCI spec section 4.1 */ |
876e0df9 | 737 | |
083522d7 BH |
738 | ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list); |
739 | ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next); | |
18807521 DB |
740 | |
741 | /* | |
742 | * hcc_params controls whether ehci->regs->segment must (!!!) | |
743 | * be used; it constrains QH/ITD/SITD and QTD locations. | |
744 | * pci_pool consistent memory always uses segment zero. | |
745 | * streaming mappings for I/O buffers, like pci_map_single(), | |
746 | * can return segments above 4GB, if the device allows. | |
747 | * | |
748 | * NOTE: the dma mask is visible through dma_supported(), so | |
749 | * drivers can pass this info along ... like NETIF_F_HIGHDMA, | |
750 | * Scsi_Host.highmem_io, and so forth. It's readonly to all | |
751 | * host side drivers though. | |
752 | */ | |
083522d7 | 753 | hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params); |
18807521 | 754 | if (HCC_64BIT_ADDR(hcc_params)) { |
083522d7 | 755 | ehci_writel(ehci, 0, &ehci->regs->segment); |
18807521 DB |
756 | #if 0 |
757 | // this is deeply broken on almost all architectures | |
6a35528a | 758 | if (!dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64))) |
18807521 DB |
759 | ehci_info(ehci, "enabled 64bit DMA\n"); |
760 | #endif | |
761 | } | |
762 | ||
763 | ||
1da177e4 LT |
764 | // Philips, Intel, and maybe others need CMD_RUN before the |
765 | // root hub will detect new devices (why?); NEC doesn't | |
18807521 DB |
766 | ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET); |
767 | ehci->command |= CMD_RUN; | |
083522d7 | 768 | ehci_writel(ehci, ehci->command, &ehci->regs->command); |
18807521 | 769 | dbg_cmd (ehci, "init", ehci->command); |
1da177e4 | 770 | |
1da177e4 LT |
771 | /* |
772 | * Start, enabling full USB 2.0 functionality ... usb 1.1 devices | |
773 | * are explicitly handed to companion controller(s), so no TT is | |
774 | * involved with the root hub. (Except where one is integrated, | |
775 | * and there's no companion controller unless maybe for USB OTG.) | |
32fe0198 AS |
776 | * |
777 | * Turning on the CF flag will transfer ownership of all ports | |
778 | * from the companions to the EHCI controller. If any of the | |
779 | * companions are in the middle of a port reset at the time, it | |
780 | * could cause trouble. Write-locking ehci_cf_port_reset_rwsem | |
1cb52658 DB |
781 | * guarantees that no resets are in progress. After we set CF, |
782 | * a short delay lets the hardware catch up; new resets shouldn't | |
783 | * be started before the port switching actions could complete. | |
1da177e4 | 784 | */ |
32fe0198 | 785 | down_write(&ehci_cf_port_reset_rwsem); |
e8799906 | 786 | ehci->rh_state = EHCI_RH_RUNNING; |
083522d7 BH |
787 | ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag); |
788 | ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */ | |
1cb52658 | 789 | msleep(5); |
32fe0198 | 790 | up_write(&ehci_cf_port_reset_rwsem); |
ee4ecb8a | 791 | ehci->last_periodic_enable = ktime_get_real(); |
1da177e4 | 792 | |
c430131a | 793 | temp = HC_VERSION(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase)); |
1da177e4 | 794 | ehci_info (ehci, |
2b70f073 | 795 | "USB %x.%x started, EHCI %x.%02x%s\n", |
7ff71d6a | 796 | ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f), |
2b70f073 | 797 | temp >> 8, temp & 0xff, |
93f1a47c | 798 | ignore_oc ? ", overcurrent ignored" : ""); |
1da177e4 | 799 | |
083522d7 BH |
800 | ehci_writel(ehci, INTR_MASK, |
801 | &ehci->regs->intr_enable); /* Turn On Interrupts */ | |
1da177e4 | 802 | |
18807521 DB |
803 | /* GRR this is run-once init(), being done every time the HC starts. |
804 | * So long as they're part of class devices, we can't do it init() | |
805 | * since the class device isn't created that early. | |
806 | */ | |
807 | create_debug_files(ehci); | |
4c67045b | 808 | create_sysfs_files(ehci); |
1da177e4 LT |
809 | |
810 | return 0; | |
811 | } | |
812 | ||
2093c6b4 MC |
813 | static int __maybe_unused ehci_setup (struct usb_hcd *hcd) |
814 | { | |
815 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | |
816 | int retval; | |
817 | ||
818 | ehci->regs = (void __iomem *)ehci->caps + | |
819 | HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase)); | |
820 | dbg_hcs_params(ehci, "reset"); | |
821 | dbg_hcc_params(ehci, "reset"); | |
822 | ||
823 | /* cache this readonly data; minimize chip reads */ | |
824 | ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); | |
825 | ||
826 | ehci->sbrn = HCD_USB2; | |
827 | ||
828 | retval = ehci_halt(ehci); | |
829 | if (retval) | |
830 | return retval; | |
831 | ||
832 | /* data structure init */ | |
833 | retval = ehci_init(hcd); | |
834 | if (retval) | |
835 | return retval; | |
836 | ||
837 | ehci_reset(ehci); | |
838 | ||
839 | return 0; | |
840 | } | |
841 | ||
1da177e4 LT |
842 | /*-------------------------------------------------------------------------*/ |
843 | ||
7d12e780 | 844 | static irqreturn_t ehci_irq (struct usb_hcd *hcd) |
1da177e4 LT |
845 | { |
846 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
67b2e029 | 847 | u32 status, masked_status, pcd_status = 0, cmd; |
1da177e4 LT |
848 | int bh; |
849 | ||
850 | spin_lock (&ehci->lock); | |
851 | ||
083522d7 | 852 | status = ehci_readl(ehci, &ehci->regs->status); |
1da177e4 LT |
853 | |
854 | /* e.g. cardbus physical eject */ | |
855 | if (status == ~(u32) 0) { | |
856 | ehci_dbg (ehci, "device removed\n"); | |
857 | goto dead; | |
858 | } | |
859 | ||
69fff59d | 860 | /* Shared IRQ? */ |
67b2e029 | 861 | masked_status = status & INTR_MASK; |
e8799906 | 862 | if (!masked_status || unlikely(ehci->rh_state == EHCI_RH_HALTED)) { |
1da177e4 LT |
863 | spin_unlock(&ehci->lock); |
864 | return IRQ_NONE; | |
865 | } | |
866 | ||
867 | /* clear (just) interrupts */ | |
67b2e029 | 868 | ehci_writel(ehci, masked_status, &ehci->regs->status); |
e82cc128 | 869 | cmd = ehci_readl(ehci, &ehci->regs->command); |
1da177e4 LT |
870 | bh = 0; |
871 | ||
9776afc8 | 872 | #ifdef VERBOSE_DEBUG |
1da177e4 LT |
873 | /* unrequested/ignored: Frame List Rollover */ |
874 | dbg_status (ehci, "irq", status); | |
875 | #endif | |
876 | ||
877 | /* INT, ERR, and IAA interrupt rates can be throttled */ | |
878 | ||
879 | /* normal [4.15.1.2] or error [4.15.1.1] completion */ | |
880 | if (likely ((status & (STS_INT|STS_ERR)) != 0)) { | |
881 | if (likely ((status & STS_ERR) == 0)) | |
882 | COUNT (ehci->stats.normal); | |
883 | else | |
884 | COUNT (ehci->stats.error); | |
885 | bh = 1; | |
886 | } | |
887 | ||
888 | /* complete the unlinking of some qh [4.15.2.3] */ | |
889 | if (status & STS_IAA) { | |
e82cc128 DB |
890 | /* guard against (alleged) silicon errata */ |
891 | if (cmd & CMD_IAAD) { | |
892 | ehci_writel(ehci, cmd & ~CMD_IAAD, | |
893 | &ehci->regs->command); | |
894 | ehci_dbg(ehci, "IAA with IAAD still set?\n"); | |
895 | } | |
896 | if (ehci->reclaim) { | |
897 | COUNT(ehci->stats.reclaim); | |
898 | end_unlink_async(ehci); | |
899 | } else | |
900 | ehci_dbg(ehci, "IAA with nothing to reclaim?\n"); | |
1da177e4 LT |
901 | } |
902 | ||
903 | /* remote wakeup [4.3.1] */ | |
d97cc2f2 | 904 | if (status & STS_PCD) { |
1da177e4 | 905 | unsigned i = HCS_N_PORTS (ehci->hcs_params); |
5a9cdf33 | 906 | u32 ppcd = 0; |
d1b1842c DB |
907 | |
908 | /* kick root hub later */ | |
1d619f12 | 909 | pcd_status = status; |
1da177e4 LT |
910 | |
911 | /* resume root hub? */ | |
eafe5b99 | 912 | if (!(cmd & CMD_RUN)) |
8c03356a | 913 | usb_hcd_resume_root_hub(hcd); |
1da177e4 | 914 | |
5a9cdf33 AD |
915 | /* get per-port change detect bits */ |
916 | if (ehci->has_ppcd) | |
917 | ppcd = status >> 16; | |
918 | ||
1da177e4 | 919 | while (i--) { |
5a9cdf33 AD |
920 | int pstatus; |
921 | ||
922 | /* leverage per-port change bits feature */ | |
923 | if (ehci->has_ppcd && !(ppcd & (1 << i))) | |
924 | continue; | |
925 | pstatus = ehci_readl(ehci, | |
926 | &ehci->regs->port_status[i]); | |
b972b68c DB |
927 | |
928 | if (pstatus & PORT_OWNER) | |
1da177e4 | 929 | continue; |
eafe5b99 AS |
930 | if (!(test_bit(i, &ehci->suspended_ports) && |
931 | ((pstatus & PORT_RESUME) || | |
932 | !(pstatus & PORT_SUSPEND)) && | |
933 | (pstatus & PORT_PE) && | |
934 | ehci->reset_done[i] == 0)) | |
1da177e4 LT |
935 | continue; |
936 | ||
937 | /* start 20 msec resume signaling from this port, | |
938 | * and make khubd collect PORT_STAT_C_SUSPEND to | |
49d0f078 AS |
939 | * stop that signaling. Use 5 ms extra for safety, |
940 | * like usb_port_resume() does. | |
1da177e4 | 941 | */ |
49d0f078 | 942 | ehci->reset_done[i] = jiffies + msecs_to_jiffies(25); |
1da177e4 | 943 | ehci_dbg (ehci, "port %d remote wakeup\n", i + 1); |
61e8b858 | 944 | mod_timer(&hcd->rh_timer, ehci->reset_done[i]); |
1da177e4 LT |
945 | } |
946 | } | |
947 | ||
948 | /* PCI errors [4.15.2.4] */ | |
949 | if (unlikely ((status & STS_FATAL) != 0)) { | |
67b2e029 | 950 | ehci_err(ehci, "fatal error\n"); |
eafe5b99 AS |
951 | dbg_cmd(ehci, "fatal", cmd); |
952 | dbg_status(ehci, "fatal", status); | |
67b2e029 | 953 | ehci_halt(ehci); |
1da177e4 | 954 | dead: |
67b2e029 AS |
955 | ehci_reset(ehci); |
956 | ehci_writel(ehci, 0, &ehci->regs->configured_flag); | |
69fff59d | 957 | usb_hc_died(hcd); |
67b2e029 AS |
958 | /* generic layer kills/unlinks all urbs, then |
959 | * uses ehci_stop to clean up the rest | |
960 | */ | |
961 | bh = 1; | |
1da177e4 LT |
962 | } |
963 | ||
964 | if (bh) | |
7d12e780 | 965 | ehci_work (ehci); |
1da177e4 | 966 | spin_unlock (&ehci->lock); |
d1b1842c | 967 | if (pcd_status) |
1d619f12 | 968 | usb_hcd_poll_rh_status(hcd); |
1da177e4 LT |
969 | return IRQ_HANDLED; |
970 | } | |
971 | ||
972 | /*-------------------------------------------------------------------------*/ | |
973 | ||
974 | /* | |
975 | * non-error returns are a promise to giveback() the urb later | |
976 | * we drop ownership so next owner (or urb unlink) can get it | |
977 | * | |
978 | * urb + dev is in hcd.self.controller.urb_list | |
979 | * we're queueing TDs onto software and hardware lists | |
980 | * | |
981 | * hcd-specific init for hcpriv hasn't been done yet | |
982 | * | |
983 | * NOTE: control, bulk, and interrupt share the same code to append TDs | |
984 | * to a (possibly active) QH, and the same QH scanning code. | |
985 | */ | |
986 | static int ehci_urb_enqueue ( | |
987 | struct usb_hcd *hcd, | |
1da177e4 | 988 | struct urb *urb, |
55016f10 | 989 | gfp_t mem_flags |
1da177e4 LT |
990 | ) { |
991 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
992 | struct list_head qtd_list; | |
993 | ||
994 | INIT_LIST_HEAD (&qtd_list); | |
995 | ||
996 | switch (usb_pipetype (urb->pipe)) { | |
25b70a86 DB |
997 | case PIPE_CONTROL: |
998 | /* qh_completions() code doesn't handle all the fault cases | |
999 | * in multi-TD control transfers. Even 1KB is rare anyway. | |
1000 | */ | |
1001 | if (urb->transfer_buffer_length > (16 * 1024)) | |
1002 | return -EMSGSIZE; | |
1003 | /* FALLTHROUGH */ | |
1004 | /* case PIPE_BULK: */ | |
1da177e4 LT |
1005 | default: |
1006 | if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags)) | |
1007 | return -ENOMEM; | |
e9df41c5 | 1008 | return submit_async(ehci, urb, &qtd_list, mem_flags); |
1da177e4 LT |
1009 | |
1010 | case PIPE_INTERRUPT: | |
1011 | if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags)) | |
1012 | return -ENOMEM; | |
e9df41c5 | 1013 | return intr_submit(ehci, urb, &qtd_list, mem_flags); |
1da177e4 LT |
1014 | |
1015 | case PIPE_ISOCHRONOUS: | |
1016 | if (urb->dev->speed == USB_SPEED_HIGH) | |
1017 | return itd_submit (ehci, urb, mem_flags); | |
1018 | else | |
1019 | return sitd_submit (ehci, urb, mem_flags); | |
1020 | } | |
1021 | } | |
1022 | ||
1023 | static void unlink_async (struct ehci_hcd *ehci, struct ehci_qh *qh) | |
1024 | { | |
07d29b63 | 1025 | /* failfast */ |
e8799906 | 1026 | if (ehci->rh_state != EHCI_RH_RUNNING && ehci->reclaim) |
07d29b63 AS |
1027 | end_unlink_async(ehci); |
1028 | ||
3a44494e AS |
1029 | /* If the QH isn't linked then there's nothing we can do |
1030 | * unless we were called during a giveback, in which case | |
1031 | * qh_completions() has to deal with it. | |
1032 | */ | |
1033 | if (qh->qh_state != QH_STATE_LINKED) { | |
1034 | if (qh->qh_state == QH_STATE_COMPLETING) | |
1035 | qh->needs_rescan = 1; | |
1036 | return; | |
1037 | } | |
07d29b63 AS |
1038 | |
1039 | /* defer till later if busy */ | |
3a44494e | 1040 | if (ehci->reclaim) { |
1da177e4 LT |
1041 | struct ehci_qh *last; |
1042 | ||
1043 | for (last = ehci->reclaim; | |
1044 | last->reclaim; | |
1045 | last = last->reclaim) | |
1046 | continue; | |
1047 | qh->qh_state = QH_STATE_UNLINK_WAIT; | |
1048 | last->reclaim = qh; | |
1049 | ||
07d29b63 AS |
1050 | /* start IAA cycle */ |
1051 | } else | |
1da177e4 LT |
1052 | start_unlink_async (ehci, qh); |
1053 | } | |
1054 | ||
1055 | /* remove from hardware lists | |
1056 | * completions normally happen asynchronously | |
1057 | */ | |
1058 | ||
e9df41c5 | 1059 | static int ehci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) |
1da177e4 LT |
1060 | { |
1061 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
1062 | struct ehci_qh *qh; | |
1063 | unsigned long flags; | |
e9df41c5 | 1064 | int rc; |
1da177e4 LT |
1065 | |
1066 | spin_lock_irqsave (&ehci->lock, flags); | |
e9df41c5 AS |
1067 | rc = usb_hcd_check_unlink_urb(hcd, urb, status); |
1068 | if (rc) | |
1069 | goto done; | |
1070 | ||
1da177e4 LT |
1071 | switch (usb_pipetype (urb->pipe)) { |
1072 | // case PIPE_CONTROL: | |
1073 | // case PIPE_BULK: | |
1074 | default: | |
1075 | qh = (struct ehci_qh *) urb->hcpriv; | |
1076 | if (!qh) | |
1077 | break; | |
07d29b63 AS |
1078 | switch (qh->qh_state) { |
1079 | case QH_STATE_LINKED: | |
1080 | case QH_STATE_COMPLETING: | |
1081 | unlink_async(ehci, qh); | |
1082 | break; | |
1083 | case QH_STATE_UNLINK: | |
1084 | case QH_STATE_UNLINK_WAIT: | |
1085 | /* already started */ | |
1086 | break; | |
1087 | case QH_STATE_IDLE: | |
7a0f0d95 AS |
1088 | /* QH might be waiting for a Clear-TT-Buffer */ |
1089 | qh_completions(ehci, qh); | |
07d29b63 AS |
1090 | break; |
1091 | } | |
1da177e4 LT |
1092 | break; |
1093 | ||
1094 | case PIPE_INTERRUPT: | |
1095 | qh = (struct ehci_qh *) urb->hcpriv; | |
1096 | if (!qh) | |
1097 | break; | |
1098 | switch (qh->qh_state) { | |
1099 | case QH_STATE_LINKED: | |
a448c9d8 | 1100 | case QH_STATE_COMPLETING: |
1da177e4 | 1101 | intr_deschedule (ehci, qh); |
a448c9d8 | 1102 | break; |
1da177e4 | 1103 | case QH_STATE_IDLE: |
7d12e780 | 1104 | qh_completions (ehci, qh); |
1da177e4 LT |
1105 | break; |
1106 | default: | |
1107 | ehci_dbg (ehci, "bogus qh %p state %d\n", | |
1108 | qh, qh->qh_state); | |
1109 | goto done; | |
1110 | } | |
1da177e4 LT |
1111 | break; |
1112 | ||
1113 | case PIPE_ISOCHRONOUS: | |
1114 | // itd or sitd ... | |
1115 | ||
1116 | // wait till next completion, do it then. | |
1117 | // completion irqs can wait up to 1024 msec, | |
1118 | break; | |
1119 | } | |
1120 | done: | |
1121 | spin_unlock_irqrestore (&ehci->lock, flags); | |
e9df41c5 | 1122 | return rc; |
1da177e4 LT |
1123 | } |
1124 | ||
1125 | /*-------------------------------------------------------------------------*/ | |
1126 | ||
1127 | // bulk qh holds the data toggle | |
1128 | ||
1129 | static void | |
1130 | ehci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep) | |
1131 | { | |
1132 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
1133 | unsigned long flags; | |
1134 | struct ehci_qh *qh, *tmp; | |
1135 | ||
1136 | /* ASSERT: any requests/urbs are being unlinked */ | |
1137 | /* ASSERT: nobody can be submitting urbs for this any more */ | |
1138 | ||
1139 | rescan: | |
1140 | spin_lock_irqsave (&ehci->lock, flags); | |
1141 | qh = ep->hcpriv; | |
1142 | if (!qh) | |
1143 | goto done; | |
1144 | ||
1145 | /* endpoints can be iso streams. for now, we don't | |
1146 | * accelerate iso completions ... so spin a while. | |
1147 | */ | |
1082f57a | 1148 | if (qh->hw == NULL) { |
1da177e4 LT |
1149 | ehci_vdbg (ehci, "iso delay\n"); |
1150 | goto idle_timeout; | |
1151 | } | |
1152 | ||
e8799906 | 1153 | if (ehci->rh_state != EHCI_RH_RUNNING) |
1da177e4 LT |
1154 | qh->qh_state = QH_STATE_IDLE; |
1155 | switch (qh->qh_state) { | |
1156 | case QH_STATE_LINKED: | |
3a44494e | 1157 | case QH_STATE_COMPLETING: |
1da177e4 LT |
1158 | for (tmp = ehci->async->qh_next.qh; |
1159 | tmp && tmp != qh; | |
1160 | tmp = tmp->qh_next.qh) | |
1161 | continue; | |
02e2c51b AS |
1162 | /* periodic qh self-unlinks on empty, and a COMPLETING qh |
1163 | * may already be unlinked. | |
1164 | */ | |
1165 | if (tmp) | |
1166 | unlink_async(ehci, qh); | |
1da177e4 LT |
1167 | /* FALL THROUGH */ |
1168 | case QH_STATE_UNLINK: /* wait for hw to finish? */ | |
07d29b63 | 1169 | case QH_STATE_UNLINK_WAIT: |
1da177e4 LT |
1170 | idle_timeout: |
1171 | spin_unlock_irqrestore (&ehci->lock, flags); | |
22c43863 | 1172 | schedule_timeout_uninterruptible(1); |
1da177e4 LT |
1173 | goto rescan; |
1174 | case QH_STATE_IDLE: /* fully unlinked */ | |
914b7012 AS |
1175 | if (qh->clearing_tt) |
1176 | goto idle_timeout; | |
1da177e4 LT |
1177 | if (list_empty (&qh->qtd_list)) { |
1178 | qh_put (qh); | |
1179 | break; | |
1180 | } | |
1181 | /* else FALL THROUGH */ | |
1182 | default: | |
1da177e4 LT |
1183 | /* caller was supposed to have unlinked any requests; |
1184 | * that's not our job. just leak this memory. | |
1185 | */ | |
1186 | ehci_err (ehci, "qh %p (#%02x) state %d%s\n", | |
1187 | qh, ep->desc.bEndpointAddress, qh->qh_state, | |
1188 | list_empty (&qh->qtd_list) ? "" : "(has tds)"); | |
1189 | break; | |
1190 | } | |
1191 | ep->hcpriv = NULL; | |
1192 | done: | |
1193 | spin_unlock_irqrestore (&ehci->lock, flags); | |
1da177e4 LT |
1194 | } |
1195 | ||
b18ffd49 AS |
1196 | static void |
1197 | ehci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep) | |
1198 | { | |
1199 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | |
1200 | struct ehci_qh *qh; | |
1201 | int eptype = usb_endpoint_type(&ep->desc); | |
a455212d AS |
1202 | int epnum = usb_endpoint_num(&ep->desc); |
1203 | int is_out = usb_endpoint_dir_out(&ep->desc); | |
1204 | unsigned long flags; | |
b18ffd49 AS |
1205 | |
1206 | if (eptype != USB_ENDPOINT_XFER_BULK && eptype != USB_ENDPOINT_XFER_INT) | |
1207 | return; | |
1208 | ||
a455212d | 1209 | spin_lock_irqsave(&ehci->lock, flags); |
b18ffd49 AS |
1210 | qh = ep->hcpriv; |
1211 | ||
1212 | /* For Bulk and Interrupt endpoints we maintain the toggle state | |
1213 | * in the hardware; the toggle bits in udev aren't used at all. | |
1214 | * When an endpoint is reset by usb_clear_halt() we must reset | |
1215 | * the toggle bit in the QH. | |
1216 | */ | |
1217 | if (qh) { | |
a455212d | 1218 | usb_settoggle(qh->dev, epnum, is_out, 0); |
b18ffd49 AS |
1219 | if (!list_empty(&qh->qtd_list)) { |
1220 | WARN_ONCE(1, "clear_halt for a busy endpoint\n"); | |
3a44494e AS |
1221 | } else if (qh->qh_state == QH_STATE_LINKED || |
1222 | qh->qh_state == QH_STATE_COMPLETING) { | |
a455212d AS |
1223 | |
1224 | /* The toggle value in the QH can't be updated | |
1225 | * while the QH is active. Unlink it now; | |
1226 | * re-linking will call qh_refresh(). | |
b18ffd49 | 1227 | */ |
a448c9d8 | 1228 | if (eptype == USB_ENDPOINT_XFER_BULK) |
a455212d | 1229 | unlink_async(ehci, qh); |
a448c9d8 | 1230 | else |
a455212d | 1231 | intr_deschedule(ehci, qh); |
b18ffd49 AS |
1232 | } |
1233 | } | |
a455212d | 1234 | spin_unlock_irqrestore(&ehci->lock, flags); |
b18ffd49 AS |
1235 | } |
1236 | ||
7ff71d6a MP |
1237 | static int ehci_get_frame (struct usb_hcd *hcd) |
1238 | { | |
1239 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
68aa95d5 | 1240 | return (ehci_read_frame_index(ehci) >> 3) % ehci->periodic_size; |
7ff71d6a | 1241 | } |
1da177e4 LT |
1242 | |
1243 | /*-------------------------------------------------------------------------*/ | |
1244 | ||
2b70f073 | 1245 | MODULE_DESCRIPTION(DRIVER_DESC); |
1da177e4 LT |
1246 | MODULE_AUTHOR (DRIVER_AUTHOR); |
1247 | MODULE_LICENSE ("GPL"); | |
1248 | ||
7ff71d6a MP |
1249 | #ifdef CONFIG_PCI |
1250 | #include "ehci-pci.c" | |
01cced25 | 1251 | #define PCI_DRIVER ehci_pci_driver |
7ff71d6a | 1252 | #endif |
1da177e4 | 1253 | |
ba02978a | 1254 | #ifdef CONFIG_USB_EHCI_FSL |
80cb9aee | 1255 | #include "ehci-fsl.c" |
01cced25 | 1256 | #define PLATFORM_DRIVER ehci_fsl_driver |
80cb9aee RV |
1257 | #endif |
1258 | ||
7e8d5cd9 DM |
1259 | #ifdef CONFIG_USB_EHCI_MXC |
1260 | #include "ehci-mxc.c" | |
1261 | #define PLATFORM_DRIVER ehci_mxc_driver | |
1262 | #endif | |
1263 | ||
60b0bf0f | 1264 | #ifdef CONFIG_USB_EHCI_SH |
63c84552 PM |
1265 | #include "ehci-sh.c" |
1266 | #define PLATFORM_DRIVER ehci_hcd_sh_driver | |
1267 | #endif | |
1268 | ||
37663860 | 1269 | #ifdef CONFIG_MIPS_ALCHEMY |
76fa9a24 | 1270 | #include "ehci-au1xxx.c" |
01cced25 | 1271 | #define PLATFORM_DRIVER ehci_hcd_au1xxx_driver |
76fa9a24 JC |
1272 | #endif |
1273 | ||
7f124f4b | 1274 | #ifdef CONFIG_USB_EHCI_HCD_OMAP |
54ab2b02 FB |
1275 | #include "ehci-omap.c" |
1276 | #define PLATFORM_DRIVER ehci_hcd_omap_driver | |
1277 | #endif | |
1278 | ||
ad75a410 GL |
1279 | #ifdef CONFIG_PPC_PS3 |
1280 | #include "ehci-ps3.c" | |
7a4eb7fd | 1281 | #define PS3_SYSTEM_BUS_DRIVER ps3_ehci_driver |
ad75a410 GL |
1282 | #endif |
1283 | ||
da0e8fb0 VB |
1284 | #ifdef CONFIG_USB_EHCI_HCD_PPC_OF |
1285 | #include "ehci-ppc-of.c" | |
1286 | #define OF_PLATFORM_DRIVER ehci_hcd_ppc_of_driver | |
1287 | #endif | |
1288 | ||
08d3c18e JZ |
1289 | #ifdef CONFIG_XPS_USB_HCD_XILINX |
1290 | #include "ehci-xilinx-of.c" | |
1f23b2d9 | 1291 | #define XILINX_OF_PLATFORM_DRIVER ehci_hcd_xilinx_of_driver |
08d3c18e JZ |
1292 | #endif |
1293 | ||
705a7521 | 1294 | #ifdef CONFIG_PLAT_ORION |
e96ffe2f TP |
1295 | #include "ehci-orion.c" |
1296 | #define PLATFORM_DRIVER ehci_orion_driver | |
1297 | #endif | |
1298 | ||
91bc4d31 VB |
1299 | #ifdef CONFIG_ARCH_IXP4XX |
1300 | #include "ehci-ixp4xx.c" | |
1301 | #define PLATFORM_DRIVER ixp4xx_ehci_driver | |
1302 | #endif | |
1303 | ||
586dfc8c WZ |
1304 | #ifdef CONFIG_USB_W90X900_EHCI |
1305 | #include "ehci-w90x900.c" | |
1306 | #define PLATFORM_DRIVER ehci_hcd_w90x900_driver | |
1307 | #endif | |
1308 | ||
501c9c08 NF |
1309 | #ifdef CONFIG_ARCH_AT91 |
1310 | #include "ehci-atmel.c" | |
1311 | #define PLATFORM_DRIVER ehci_atmel_driver | |
1312 | #endif | |
1313 | ||
1643accd DD |
1314 | #ifdef CONFIG_USB_OCTEON_EHCI |
1315 | #include "ehci-octeon.c" | |
1316 | #define PLATFORM_DRIVER ehci_octeon_driver | |
1317 | #endif | |
1318 | ||
760efe69 ML |
1319 | #ifdef CONFIG_USB_CNS3XXX_EHCI |
1320 | #include "ehci-cns3xxx.c" | |
1321 | #define PLATFORM_DRIVER cns3xxx_ehci_driver | |
1322 | #endif | |
1323 | ||
ad78acaf AC |
1324 | #ifdef CONFIG_ARCH_VT8500 |
1325 | #include "ehci-vt8500.c" | |
1326 | #define PLATFORM_DRIVER vt8500_ehci_driver | |
1327 | #endif | |
1328 | ||
c8c38de9 DS |
1329 | #ifdef CONFIG_PLAT_SPEAR |
1330 | #include "ehci-spear.c" | |
1331 | #define PLATFORM_DRIVER spear_ehci_hcd_driver | |
1332 | #endif | |
1333 | ||
b0848aea PK |
1334 | #ifdef CONFIG_USB_EHCI_MSM |
1335 | #include "ehci-msm.c" | |
1336 | #define PLATFORM_DRIVER ehci_msm_driver | |
1337 | #endif | |
1338 | ||
22ced687 A |
1339 | #ifdef CONFIG_USB_EHCI_HCD_PMC_MSP |
1340 | #include "ehci-pmcmsp.c" | |
1341 | #define PLATFORM_DRIVER ehci_hcd_msp_driver | |
1342 | #endif | |
1343 | ||
79ad3b5a BG |
1344 | #ifdef CONFIG_USB_EHCI_TEGRA |
1345 | #include "ehci-tegra.c" | |
1346 | #define PLATFORM_DRIVER tegra_ehci_driver | |
1347 | #endif | |
1348 | ||
1bcc5aa8 JS |
1349 | #ifdef CONFIG_USB_EHCI_S5P |
1350 | #include "ehci-s5p.c" | |
1351 | #define PLATFORM_DRIVER s5p_ehci_driver | |
1352 | #endif | |
1353 | ||
502fa841 GJ |
1354 | #ifdef CONFIG_USB_EHCI_ATH79 |
1355 | #include "ehci-ath79.c" | |
1356 | #define PLATFORM_DRIVER ehci_ath79_driver | |
1357 | #endif | |
1358 | ||
9be03929 JA |
1359 | #ifdef CONFIG_SPARC_LEON |
1360 | #include "ehci-grlib.c" | |
1361 | #define PLATFORM_DRIVER ehci_grlib_driver | |
1362 | #endif | |
1363 | ||
3abd7f68 TU |
1364 | #ifdef CONFIG_USB_PXA168_EHCI |
1365 | #include "ehci-pxa168.c" | |
1366 | #define PLATFORM_DRIVER ehci_pxa168_driver | |
1367 | #endif | |
1368 | ||
23106343 J |
1369 | #ifdef CONFIG_NLM_XLR |
1370 | #include "ehci-xls.c" | |
1371 | #define PLATFORM_DRIVER ehci_xls_driver | |
1372 | #endif | |
1373 | ||
ad75a410 | 1374 | #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \ |
1f23b2d9 GL |
1375 | !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \ |
1376 | !defined(XILINX_OF_PLATFORM_DRIVER) | |
7ff71d6a MP |
1377 | #error "missing bus glue for ehci-hcd" |
1378 | #endif | |
01cced25 KG |
1379 | |
1380 | static int __init ehci_hcd_init(void) | |
1381 | { | |
1382 | int retval = 0; | |
1383 | ||
2b70f073 AS |
1384 | if (usb_disabled()) |
1385 | return -ENODEV; | |
1386 | ||
1387 | printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name); | |
9beeee65 AS |
1388 | set_bit(USB_EHCI_LOADED, &usb_hcds_loaded); |
1389 | if (test_bit(USB_UHCI_LOADED, &usb_hcds_loaded) || | |
1390 | test_bit(USB_OHCI_LOADED, &usb_hcds_loaded)) | |
1391 | printk(KERN_WARNING "Warning! ehci_hcd should always be loaded" | |
1392 | " before uhci_hcd and ohci_hcd, not after\n"); | |
1393 | ||
01cced25 KG |
1394 | pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n", |
1395 | hcd_name, | |
1396 | sizeof(struct ehci_qh), sizeof(struct ehci_qtd), | |
1397 | sizeof(struct ehci_itd), sizeof(struct ehci_sitd)); | |
1398 | ||
694cc208 | 1399 | #ifdef DEBUG |
08f4e586 | 1400 | ehci_debug_root = debugfs_create_dir("ehci", usb_debug_root); |
9beeee65 AS |
1401 | if (!ehci_debug_root) { |
1402 | retval = -ENOENT; | |
1403 | goto err_debug; | |
1404 | } | |
694cc208 TJ |
1405 | #endif |
1406 | ||
01cced25 KG |
1407 | #ifdef PLATFORM_DRIVER |
1408 | retval = platform_driver_register(&PLATFORM_DRIVER); | |
da0e8fb0 VB |
1409 | if (retval < 0) |
1410 | goto clean0; | |
01cced25 KG |
1411 | #endif |
1412 | ||
1413 | #ifdef PCI_DRIVER | |
1414 | retval = pci_register_driver(&PCI_DRIVER); | |
da0e8fb0 VB |
1415 | if (retval < 0) |
1416 | goto clean1; | |
ad75a410 GL |
1417 | #endif |
1418 | ||
1419 | #ifdef PS3_SYSTEM_BUS_DRIVER | |
7a4eb7fd | 1420 | retval = ps3_ehci_driver_register(&PS3_SYSTEM_BUS_DRIVER); |
da0e8fb0 VB |
1421 | if (retval < 0) |
1422 | goto clean2; | |
694cc208 | 1423 | #endif |
da0e8fb0 VB |
1424 | |
1425 | #ifdef OF_PLATFORM_DRIVER | |
d35fb641 | 1426 | retval = platform_driver_register(&OF_PLATFORM_DRIVER); |
da0e8fb0 VB |
1427 | if (retval < 0) |
1428 | goto clean3; | |
1429 | #endif | |
1f23b2d9 GL |
1430 | |
1431 | #ifdef XILINX_OF_PLATFORM_DRIVER | |
d35fb641 | 1432 | retval = platform_driver_register(&XILINX_OF_PLATFORM_DRIVER); |
1f23b2d9 GL |
1433 | if (retval < 0) |
1434 | goto clean4; | |
1435 | #endif | |
da0e8fb0 VB |
1436 | return retval; |
1437 | ||
1f23b2d9 | 1438 | #ifdef XILINX_OF_PLATFORM_DRIVER |
d35fb641 | 1439 | /* platform_driver_unregister(&XILINX_OF_PLATFORM_DRIVER); */ |
1f23b2d9 GL |
1440 | clean4: |
1441 | #endif | |
da0e8fb0 | 1442 | #ifdef OF_PLATFORM_DRIVER |
d35fb641 | 1443 | platform_driver_unregister(&OF_PLATFORM_DRIVER); |
da0e8fb0 VB |
1444 | clean3: |
1445 | #endif | |
1446 | #ifdef PS3_SYSTEM_BUS_DRIVER | |
1447 | ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); | |
1448 | clean2: | |
ad75a410 GL |
1449 | #endif |
1450 | #ifdef PCI_DRIVER | |
da0e8fb0 VB |
1451 | pci_unregister_driver(&PCI_DRIVER); |
1452 | clean1: | |
ad75a410 | 1453 | #endif |
da0e8fb0 VB |
1454 | #ifdef PLATFORM_DRIVER |
1455 | platform_driver_unregister(&PLATFORM_DRIVER); | |
1456 | clean0: | |
1457 | #endif | |
1458 | #ifdef DEBUG | |
1459 | debugfs_remove(ehci_debug_root); | |
1460 | ehci_debug_root = NULL; | |
9beeee65 | 1461 | err_debug: |
a9b6148d | 1462 | #endif |
9beeee65 | 1463 | clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded); |
01cced25 KG |
1464 | return retval; |
1465 | } | |
1466 | module_init(ehci_hcd_init); | |
1467 | ||
1468 | static void __exit ehci_hcd_cleanup(void) | |
1469 | { | |
1f23b2d9 | 1470 | #ifdef XILINX_OF_PLATFORM_DRIVER |
d35fb641 | 1471 | platform_driver_unregister(&XILINX_OF_PLATFORM_DRIVER); |
1f23b2d9 | 1472 | #endif |
da0e8fb0 | 1473 | #ifdef OF_PLATFORM_DRIVER |
d35fb641 | 1474 | platform_driver_unregister(&OF_PLATFORM_DRIVER); |
da0e8fb0 | 1475 | #endif |
01cced25 KG |
1476 | #ifdef PLATFORM_DRIVER |
1477 | platform_driver_unregister(&PLATFORM_DRIVER); | |
1478 | #endif | |
1479 | #ifdef PCI_DRIVER | |
1480 | pci_unregister_driver(&PCI_DRIVER); | |
1481 | #endif | |
ad75a410 | 1482 | #ifdef PS3_SYSTEM_BUS_DRIVER |
7a4eb7fd | 1483 | ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); |
ad75a410 | 1484 | #endif |
694cc208 TJ |
1485 | #ifdef DEBUG |
1486 | debugfs_remove(ehci_debug_root); | |
1487 | #endif | |
9beeee65 | 1488 | clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded); |
01cced25 KG |
1489 | } |
1490 | module_exit(ehci_hcd_cleanup); | |
1491 |