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1da177e4 LT |
1 | /* |
2 | * Copyright (c) 2000-2004 by David Brownell | |
53bd6a60 | 3 | * |
1da177e4 LT |
4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms of the GNU General Public License as published by the | |
6 | * Free Software Foundation; either version 2 of the License, or (at your | |
7 | * option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but | |
10 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
11 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 | * for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software Foundation, | |
16 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
17 | */ | |
18 | ||
1da177e4 LT |
19 | #include <linux/module.h> |
20 | #include <linux/pci.h> | |
21 | #include <linux/dmapool.h> | |
22 | #include <linux/kernel.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/ioport.h> | |
25 | #include <linux/sched.h> | |
3c04e20e | 26 | #include <linux/vmalloc.h> |
1da177e4 LT |
27 | #include <linux/errno.h> |
28 | #include <linux/init.h> | |
29 | #include <linux/timer.h> | |
ee4ecb8a | 30 | #include <linux/ktime.h> |
1da177e4 LT |
31 | #include <linux/list.h> |
32 | #include <linux/interrupt.h> | |
1da177e4 | 33 | #include <linux/usb.h> |
27729aad | 34 | #include <linux/usb/hcd.h> |
1da177e4 LT |
35 | #include <linux/moduleparam.h> |
36 | #include <linux/dma-mapping.h> | |
694cc208 | 37 | #include <linux/debugfs.h> |
5a0e3ad6 | 38 | #include <linux/slab.h> |
aa4d8342 | 39 | #include <linux/uaccess.h> |
1da177e4 | 40 | |
1da177e4 LT |
41 | #include <asm/byteorder.h> |
42 | #include <asm/io.h> | |
43 | #include <asm/irq.h> | |
44 | #include <asm/system.h> | |
45 | #include <asm/unaligned.h> | |
1da177e4 LT |
46 | |
47 | /*-------------------------------------------------------------------------*/ | |
48 | ||
49 | /* | |
50 | * EHCI hc_driver implementation ... experimental, incomplete. | |
51 | * Based on the final 1.0 register interface specification. | |
52 | * | |
53 | * USB 2.0 shows up in upcoming www.pcmcia.org technology. | |
54 | * First was PCMCIA, like ISA; then CardBus, which is PCI. | |
55 | * Next comes "CardBay", using USB 2.0 signals. | |
56 | * | |
57 | * Contains additional contributions by Brad Hards, Rory Bolt, and others. | |
58 | * Special thanks to Intel and VIA for providing host controllers to | |
59 | * test this driver on, and Cypress (including In-System Design) for | |
60 | * providing early devices for those host controllers to talk to! | |
1da177e4 LT |
61 | */ |
62 | ||
1da177e4 LT |
63 | #define DRIVER_AUTHOR "David Brownell" |
64 | #define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver" | |
65 | ||
66 | static const char hcd_name [] = "ehci_hcd"; | |
67 | ||
68 | ||
9776afc8 | 69 | #undef VERBOSE_DEBUG |
1da177e4 LT |
70 | #undef EHCI_URB_TRACE |
71 | ||
72 | #ifdef DEBUG | |
73 | #define EHCI_STATS | |
74 | #endif | |
75 | ||
76 | /* magic numbers that can affect system performance */ | |
77 | #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */ | |
78 | #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */ | |
79 | #define EHCI_TUNE_RL_TT 0 | |
80 | #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */ | |
81 | #define EHCI_TUNE_MULT_TT 1 | |
ffda0803 AS |
82 | /* |
83 | * Some drivers think it's safe to schedule isochronous transfers more than | |
84 | * 256 ms into the future (partly as a result of an old bug in the scheduling | |
85 | * code). In an attempt to avoid trouble, we will use a minimum scheduling | |
86 | * length of 512 frames instead of 256. | |
87 | */ | |
88 | #define EHCI_TUNE_FLS 1 /* (medium) 512-frame schedule */ | |
1da177e4 | 89 | |
07d29b63 | 90 | #define EHCI_IAA_MSECS 10 /* arbitrary */ |
1da177e4 LT |
91 | #define EHCI_IO_JIFFIES (HZ/10) /* io watchdog > irq_thresh */ |
92 | #define EHCI_ASYNC_JIFFIES (HZ/20) /* async idle timeout */ | |
b9638011 | 93 | #define EHCI_SHRINK_FRAMES 5 /* async qh unlink delay */ |
1da177e4 LT |
94 | |
95 | /* Initial IRQ latency: faster than hw default */ | |
96 | static int log2_irq_thresh = 0; // 0 to 6 | |
97 | module_param (log2_irq_thresh, int, S_IRUGO); | |
98 | MODULE_PARM_DESC (log2_irq_thresh, "log2 IRQ latency, 1-64 microframes"); | |
99 | ||
100 | /* initial park setting: slower than hw default */ | |
101 | static unsigned park = 0; | |
102 | module_param (park, uint, S_IRUGO); | |
103 | MODULE_PARM_DESC (park, "park setting; 1-3 back-to-back async packets"); | |
104 | ||
93f1a47c DB |
105 | /* for flakey hardware, ignore overcurrent indicators */ |
106 | static int ignore_oc = 0; | |
107 | module_param (ignore_oc, bool, S_IRUGO); | |
108 | MODULE_PARM_DESC (ignore_oc, "ignore bogus hardware overcurrent indications"); | |
109 | ||
48f24970 AD |
110 | /* for link power management(LPM) feature */ |
111 | static unsigned int hird; | |
112 | module_param(hird, int, S_IRUGO); | |
113 | MODULE_PARM_DESC(hird, "host initiated resume duration, +1 for each 75us\n"); | |
114 | ||
1da177e4 LT |
115 | #define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT) |
116 | ||
117 | /*-------------------------------------------------------------------------*/ | |
118 | ||
119 | #include "ehci.h" | |
120 | #include "ehci-dbg.c" | |
121 | ||
122 | /*-------------------------------------------------------------------------*/ | |
123 | ||
bc29847e AS |
124 | static void |
125 | timer_action(struct ehci_hcd *ehci, enum ehci_timer_action action) | |
126 | { | |
127 | /* Don't override timeouts which shrink or (later) disable | |
128 | * the async ring; just the I/O watchdog. Note that if a | |
129 | * SHRINK were pending, OFF would never be requested. | |
130 | */ | |
131 | if (timer_pending(&ehci->watchdog) | |
132 | && ((BIT(TIMER_ASYNC_SHRINK) | BIT(TIMER_ASYNC_OFF)) | |
133 | & ehci->actions)) | |
134 | return; | |
135 | ||
136 | if (!test_and_set_bit(action, &ehci->actions)) { | |
137 | unsigned long t; | |
138 | ||
139 | switch (action) { | |
140 | case TIMER_IO_WATCHDOG: | |
403dbd36 AD |
141 | if (!ehci->need_io_watchdog) |
142 | return; | |
bc29847e AS |
143 | t = EHCI_IO_JIFFIES; |
144 | break; | |
145 | case TIMER_ASYNC_OFF: | |
146 | t = EHCI_ASYNC_JIFFIES; | |
147 | break; | |
148 | /* case TIMER_ASYNC_SHRINK: */ | |
149 | default: | |
150 | /* add a jiffie since we synch against the | |
151 | * 8 KHz uframe counter. | |
152 | */ | |
153 | t = DIV_ROUND_UP(EHCI_SHRINK_FRAMES * HZ, 1000) + 1; | |
154 | break; | |
155 | } | |
156 | mod_timer(&ehci->watchdog, t + jiffies); | |
157 | } | |
158 | } | |
159 | ||
160 | /*-------------------------------------------------------------------------*/ | |
161 | ||
1da177e4 LT |
162 | /* |
163 | * handshake - spin reading hc until handshake completes or fails | |
164 | * @ptr: address of hc register to be read | |
165 | * @mask: bits to look at in result of read | |
166 | * @done: value of those bits when handshake succeeds | |
167 | * @usec: timeout in microseconds | |
168 | * | |
169 | * Returns negative errno, or zero on success | |
170 | * | |
171 | * Success happens when the "mask" bits have the specified value (hardware | |
172 | * handshake done). There are two failure modes: "usec" have passed (major | |
173 | * hardware flakeout), or the register reads as all-ones (hardware removed). | |
174 | * | |
175 | * That last failure should_only happen in cases like physical cardbus eject | |
176 | * before driver shutdown. But it also seems to be caused by bugs in cardbus | |
177 | * bridge shutdown: shutting down the bridge before the devices using it. | |
178 | */ | |
083522d7 BH |
179 | static int handshake (struct ehci_hcd *ehci, void __iomem *ptr, |
180 | u32 mask, u32 done, int usec) | |
1da177e4 LT |
181 | { |
182 | u32 result; | |
183 | ||
184 | do { | |
083522d7 | 185 | result = ehci_readl(ehci, ptr); |
1da177e4 LT |
186 | if (result == ~(u32)0) /* card removed */ |
187 | return -ENODEV; | |
188 | result &= mask; | |
189 | if (result == done) | |
190 | return 0; | |
191 | udelay (1); | |
192 | usec--; | |
193 | } while (usec > 0); | |
194 | return -ETIMEDOUT; | |
195 | } | |
196 | ||
65fd4272 MC |
197 | /* check TDI/ARC silicon is in host mode */ |
198 | static int tdi_in_host_mode (struct ehci_hcd *ehci) | |
199 | { | |
200 | u32 __iomem *reg_ptr; | |
201 | u32 tmp; | |
202 | ||
203 | reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + USBMODE); | |
204 | tmp = ehci_readl(ehci, reg_ptr); | |
205 | return (tmp & 3) == USBMODE_CM_HC; | |
206 | } | |
207 | ||
1da177e4 LT |
208 | /* force HC to halt state from unknown (EHCI spec section 2.3) */ |
209 | static int ehci_halt (struct ehci_hcd *ehci) | |
210 | { | |
083522d7 | 211 | u32 temp = ehci_readl(ehci, &ehci->regs->status); |
1da177e4 | 212 | |
72f30b6f | 213 | /* disable any irqs left enabled by previous code */ |
083522d7 | 214 | ehci_writel(ehci, 0, &ehci->regs->intr_enable); |
72f30b6f | 215 | |
65fd4272 MC |
216 | if (ehci_is_TDI(ehci) && tdi_in_host_mode(ehci) == 0) { |
217 | return 0; | |
218 | } | |
219 | ||
1da177e4 LT |
220 | if ((temp & STS_HALT) != 0) |
221 | return 0; | |
222 | ||
083522d7 | 223 | temp = ehci_readl(ehci, &ehci->regs->command); |
1da177e4 | 224 | temp &= ~CMD_RUN; |
083522d7 BH |
225 | ehci_writel(ehci, temp, &ehci->regs->command); |
226 | return handshake (ehci, &ehci->regs->status, | |
227 | STS_HALT, STS_HALT, 16 * 125); | |
1da177e4 LT |
228 | } |
229 | ||
0bcfeb3e DB |
230 | static int handshake_on_error_set_halt(struct ehci_hcd *ehci, void __iomem *ptr, |
231 | u32 mask, u32 done, int usec) | |
232 | { | |
233 | int error; | |
234 | ||
235 | error = handshake(ehci, ptr, mask, done, usec); | |
236 | if (error) { | |
237 | ehci_halt(ehci); | |
238 | ehci_to_hcd(ehci)->state = HC_STATE_HALT; | |
65cb76ba | 239 | ehci_err(ehci, "force halt; handshake %p %08x %08x -> %d\n", |
0bcfeb3e DB |
240 | ptr, mask, done, error); |
241 | } | |
242 | ||
243 | return error; | |
244 | } | |
245 | ||
1da177e4 LT |
246 | /* put TDI/ARC silicon into EHCI mode */ |
247 | static void tdi_reset (struct ehci_hcd *ehci) | |
248 | { | |
249 | u32 __iomem *reg_ptr; | |
250 | u32 tmp; | |
251 | ||
d23a1377 | 252 | reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + USBMODE); |
083522d7 | 253 | tmp = ehci_readl(ehci, reg_ptr); |
d23a1377 VB |
254 | tmp |= USBMODE_CM_HC; |
255 | /* The default byte access to MMR space is LE after | |
256 | * controller reset. Set the required endian mode | |
257 | * for transfer buffers to match the host microprocessor | |
258 | */ | |
259 | if (ehci_big_endian_mmio(ehci)) | |
260 | tmp |= USBMODE_BE; | |
083522d7 | 261 | ehci_writel(ehci, tmp, reg_ptr); |
1da177e4 LT |
262 | } |
263 | ||
264 | /* reset a non-running (STS_HALT == 1) controller */ | |
265 | static int ehci_reset (struct ehci_hcd *ehci) | |
266 | { | |
267 | int retval; | |
083522d7 | 268 | u32 command = ehci_readl(ehci, &ehci->regs->command); |
1da177e4 | 269 | |
8d053c79 JW |
270 | /* If the EHCI debug controller is active, special care must be |
271 | * taken before and after a host controller reset */ | |
272 | if (ehci->debug && !dbgp_reset_prep()) | |
273 | ehci->debug = NULL; | |
274 | ||
1da177e4 LT |
275 | command |= CMD_RESET; |
276 | dbg_cmd (ehci, "reset", command); | |
083522d7 | 277 | ehci_writel(ehci, command, &ehci->regs->command); |
1da177e4 LT |
278 | ehci_to_hcd(ehci)->state = HC_STATE_HALT; |
279 | ehci->next_statechange = jiffies; | |
083522d7 BH |
280 | retval = handshake (ehci, &ehci->regs->command, |
281 | CMD_RESET, 0, 250 * 1000); | |
1da177e4 | 282 | |
331ac6b2 AD |
283 | if (ehci->has_hostpc) { |
284 | ehci_writel(ehci, USBMODE_EX_HC | USBMODE_EX_VBPS, | |
285 | (u32 __iomem *)(((u8 *)ehci->regs) + USBMODE_EX)); | |
286 | ehci_writel(ehci, TXFIFO_DEFAULT, | |
287 | (u32 __iomem *)(((u8 *)ehci->regs) + TXFILLTUNING)); | |
288 | } | |
1da177e4 LT |
289 | if (retval) |
290 | return retval; | |
291 | ||
292 | if (ehci_is_TDI(ehci)) | |
293 | tdi_reset (ehci); | |
294 | ||
8d053c79 JW |
295 | if (ehci->debug) |
296 | dbgp_external_startup(); | |
297 | ||
1da177e4 LT |
298 | return retval; |
299 | } | |
300 | ||
301 | /* idle the controller (from running) */ | |
302 | static void ehci_quiesce (struct ehci_hcd *ehci) | |
303 | { | |
304 | u32 temp; | |
305 | ||
306 | #ifdef DEBUG | |
307 | if (!HC_IS_RUNNING (ehci_to_hcd(ehci)->state)) | |
308 | BUG (); | |
309 | #endif | |
310 | ||
311 | /* wait for any schedule enables/disables to take effect */ | |
083522d7 | 312 | temp = ehci_readl(ehci, &ehci->regs->command) << 10; |
1da177e4 | 313 | temp &= STS_ASS | STS_PSS; |
c765d4ca KW |
314 | if (handshake_on_error_set_halt(ehci, &ehci->regs->status, |
315 | STS_ASS | STS_PSS, temp, 16 * 125)) | |
1da177e4 | 316 | return; |
1da177e4 LT |
317 | |
318 | /* then disable anything that's still active */ | |
083522d7 | 319 | temp = ehci_readl(ehci, &ehci->regs->command); |
1da177e4 | 320 | temp &= ~(CMD_ASE | CMD_IAAD | CMD_PSE); |
083522d7 | 321 | ehci_writel(ehci, temp, &ehci->regs->command); |
1da177e4 LT |
322 | |
323 | /* hardware can take 16 microframes to turn off ... */ | |
c765d4ca KW |
324 | handshake_on_error_set_halt(ehci, &ehci->regs->status, |
325 | STS_ASS | STS_PSS, 0, 16 * 125); | |
1da177e4 LT |
326 | } |
327 | ||
328 | /*-------------------------------------------------------------------------*/ | |
329 | ||
07d29b63 | 330 | static void end_unlink_async(struct ehci_hcd *ehci); |
7d12e780 | 331 | static void ehci_work(struct ehci_hcd *ehci); |
1da177e4 LT |
332 | |
333 | #include "ehci-hub.c" | |
48f24970 | 334 | #include "ehci-lpm.c" |
1da177e4 LT |
335 | #include "ehci-mem.c" |
336 | #include "ehci-q.c" | |
337 | #include "ehci-sched.c" | |
338 | ||
339 | /*-------------------------------------------------------------------------*/ | |
340 | ||
07d29b63 | 341 | static void ehci_iaa_watchdog(unsigned long param) |
1da177e4 LT |
342 | { |
343 | struct ehci_hcd *ehci = (struct ehci_hcd *) param; | |
344 | unsigned long flags; | |
345 | ||
346 | spin_lock_irqsave (&ehci->lock, flags); | |
347 | ||
e82cc128 DB |
348 | /* Lost IAA irqs wedge things badly; seen first with a vt8235. |
349 | * So we need this watchdog, but must protect it against both | |
350 | * (a) SMP races against real IAA firing and retriggering, and | |
351 | * (b) clean HC shutdown, when IAA watchdog was pending. | |
352 | */ | |
353 | if (ehci->reclaim | |
354 | && !timer_pending(&ehci->iaa_watchdog) | |
355 | && HC_IS_RUNNING(ehci_to_hcd(ehci)->state)) { | |
356 | u32 cmd, status; | |
357 | ||
358 | /* If we get here, IAA is *REALLY* late. It's barely | |
359 | * conceivable that the system is so busy that CMD_IAAD | |
360 | * is still legitimately set, so let's be sure it's | |
361 | * clear before we read STS_IAA. (The HC should clear | |
362 | * CMD_IAAD when it sets STS_IAA.) | |
363 | */ | |
364 | cmd = ehci_readl(ehci, &ehci->regs->command); | |
365 | if (cmd & CMD_IAAD) | |
366 | ehci_writel(ehci, cmd & ~CMD_IAAD, | |
367 | &ehci->regs->command); | |
368 | ||
369 | /* If IAA is set here it either legitimately triggered | |
370 | * before we cleared IAAD above (but _way_ late, so we'll | |
371 | * still count it as lost) ... or a silicon erratum: | |
372 | * - VIA seems to set IAA without triggering the IRQ; | |
373 | * - IAAD potentially cleared without setting IAA. | |
374 | */ | |
375 | status = ehci_readl(ehci, &ehci->regs->status); | |
376 | if ((status & STS_IAA) || !(cmd & CMD_IAAD)) { | |
1da177e4 | 377 | COUNT (ehci->stats.lost_iaa); |
083522d7 | 378 | ehci_writel(ehci, STS_IAA, &ehci->regs->status); |
1da177e4 | 379 | } |
e82cc128 DB |
380 | |
381 | ehci_vdbg(ehci, "IAA watchdog: status %x cmd %x\n", | |
382 | status, cmd); | |
07d29b63 | 383 | end_unlink_async(ehci); |
1da177e4 LT |
384 | } |
385 | ||
07d29b63 AS |
386 | spin_unlock_irqrestore(&ehci->lock, flags); |
387 | } | |
388 | ||
389 | static void ehci_watchdog(unsigned long param) | |
390 | { | |
391 | struct ehci_hcd *ehci = (struct ehci_hcd *) param; | |
392 | unsigned long flags; | |
393 | ||
394 | spin_lock_irqsave(&ehci->lock, flags); | |
395 | ||
396 | /* stop async processing after it's idled a bit */ | |
1da177e4 | 397 | if (test_bit (TIMER_ASYNC_OFF, &ehci->actions)) |
26f953fd | 398 | start_unlink_async (ehci, ehci->async); |
1da177e4 LT |
399 | |
400 | /* ehci could run by timer, without IRQs ... */ | |
7d12e780 | 401 | ehci_work (ehci); |
1da177e4 LT |
402 | |
403 | spin_unlock_irqrestore (&ehci->lock, flags); | |
404 | } | |
405 | ||
8903795a AS |
406 | /* On some systems, leaving remote wakeup enabled prevents system shutdown. |
407 | * The firmware seems to think that powering off is a wakeup event! | |
408 | * This routine turns off remote wakeup and everything else, on all ports. | |
409 | */ | |
410 | static void ehci_turn_off_all_ports(struct ehci_hcd *ehci) | |
411 | { | |
412 | int port = HCS_N_PORTS(ehci->hcs_params); | |
413 | ||
414 | while (port--) | |
415 | ehci_writel(ehci, PORT_RWC_BITS, | |
416 | &ehci->regs->port_status[port]); | |
417 | } | |
418 | ||
21da84a8 SS |
419 | /* |
420 | * Halt HC, turn off all ports, and let the BIOS use the companion controllers. | |
421 | * Should be called with ehci->lock held. | |
72f30b6f | 422 | */ |
21da84a8 | 423 | static void ehci_silence_controller(struct ehci_hcd *ehci) |
1da177e4 | 424 | { |
21da84a8 | 425 | ehci_halt(ehci); |
8903795a | 426 | ehci_turn_off_all_ports(ehci); |
1da177e4 LT |
427 | |
428 | /* make BIOS/etc use companion controller during reboot */ | |
083522d7 | 429 | ehci_writel(ehci, 0, &ehci->regs->configured_flag); |
8903795a AS |
430 | |
431 | /* unblock posted writes */ | |
432 | ehci_readl(ehci, &ehci->regs->configured_flag); | |
1da177e4 LT |
433 | } |
434 | ||
21da84a8 SS |
435 | /* ehci_shutdown kick in for silicon on any bus (not just pci, etc). |
436 | * This forcibly disables dma and IRQs, helping kexec and other cases | |
437 | * where the next system software may expect clean state. | |
438 | */ | |
439 | static void ehci_shutdown(struct usb_hcd *hcd) | |
440 | { | |
441 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | |
442 | ||
443 | del_timer_sync(&ehci->watchdog); | |
444 | del_timer_sync(&ehci->iaa_watchdog); | |
445 | ||
446 | spin_lock_irq(&ehci->lock); | |
447 | ehci_silence_controller(ehci); | |
448 | spin_unlock_irq(&ehci->lock); | |
449 | } | |
450 | ||
56c1e26d DB |
451 | static void ehci_port_power (struct ehci_hcd *ehci, int is_on) |
452 | { | |
453 | unsigned port; | |
454 | ||
455 | if (!HCS_PPC (ehci->hcs_params)) | |
456 | return; | |
457 | ||
458 | ehci_dbg (ehci, "...power%s ports...\n", is_on ? "up" : "down"); | |
459 | for (port = HCS_N_PORTS (ehci->hcs_params); port > 0; ) | |
460 | (void) ehci_hub_control(ehci_to_hcd(ehci), | |
461 | is_on ? SetPortFeature : ClearPortFeature, | |
462 | USB_PORT_FEAT_POWER, | |
463 | port--, NULL, 0); | |
383975d7 AS |
464 | /* Flush those writes */ |
465 | ehci_readl(ehci, &ehci->regs->command); | |
56c1e26d DB |
466 | msleep(20); |
467 | } | |
468 | ||
7ff71d6a | 469 | /*-------------------------------------------------------------------------*/ |
1da177e4 | 470 | |
7ff71d6a MP |
471 | /* |
472 | * ehci_work is called from some interrupts, timers, and so on. | |
473 | * it calls driver completion functions, after dropping ehci->lock. | |
474 | */ | |
7d12e780 | 475 | static void ehci_work (struct ehci_hcd *ehci) |
7ff71d6a MP |
476 | { |
477 | timer_action_done (ehci, TIMER_IO_WATCHDOG); | |
7ff71d6a MP |
478 | |
479 | /* another CPU may drop ehci->lock during a schedule scan while | |
480 | * it reports urb completions. this flag guards against bogus | |
481 | * attempts at re-entrant schedule scanning. | |
482 | */ | |
483 | if (ehci->scanning) | |
484 | return; | |
485 | ehci->scanning = 1; | |
7d12e780 | 486 | scan_async (ehci); |
7ff71d6a | 487 | if (ehci->next_uframe != -1) |
7d12e780 | 488 | scan_periodic (ehci); |
7ff71d6a MP |
489 | ehci->scanning = 0; |
490 | ||
491 | /* the IO watchdog guards against hardware or driver bugs that | |
492 | * misplace IRQs, and should let us run completely without IRQs. | |
493 | * such lossage has been observed on both VT6202 and VT8235. | |
494 | */ | |
495 | if (HC_IS_RUNNING (ehci_to_hcd(ehci)->state) && | |
496 | (ehci->async->qh_next.ptr != NULL || | |
497 | ehci->periodic_sched != 0)) | |
498 | timer_action (ehci, TIMER_IO_WATCHDOG); | |
499 | } | |
1da177e4 | 500 | |
21da84a8 SS |
501 | /* |
502 | * Called when the ehci_hcd module is removed. | |
503 | */ | |
7ff71d6a | 504 | static void ehci_stop (struct usb_hcd *hcd) |
1da177e4 LT |
505 | { |
506 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
1da177e4 | 507 | |
7ff71d6a | 508 | ehci_dbg (ehci, "stop\n"); |
1da177e4 | 509 | |
7ff71d6a MP |
510 | /* no more interrupts ... */ |
511 | del_timer_sync (&ehci->watchdog); | |
07d29b63 | 512 | del_timer_sync(&ehci->iaa_watchdog); |
56c1e26d | 513 | |
7ff71d6a MP |
514 | spin_lock_irq(&ehci->lock); |
515 | if (HC_IS_RUNNING (hcd->state)) | |
516 | ehci_quiesce (ehci); | |
1da177e4 | 517 | |
21da84a8 | 518 | ehci_silence_controller(ehci); |
7ff71d6a | 519 | ehci_reset (ehci); |
7ff71d6a | 520 | spin_unlock_irq(&ehci->lock); |
1da177e4 | 521 | |
57e06c11 | 522 | remove_companion_file(ehci); |
7ff71d6a | 523 | remove_debug_files (ehci); |
1da177e4 | 524 | |
7ff71d6a MP |
525 | /* root hub is shut down separately (first, when possible) */ |
526 | spin_lock_irq (&ehci->lock); | |
527 | if (ehci->async) | |
7d12e780 | 528 | ehci_work (ehci); |
7ff71d6a MP |
529 | spin_unlock_irq (&ehci->lock); |
530 | ehci_mem_cleanup (ehci); | |
1da177e4 | 531 | |
7ff71d6a MP |
532 | #ifdef EHCI_STATS |
533 | ehci_dbg (ehci, "irq normal %ld err %ld reclaim %ld (lost %ld)\n", | |
534 | ehci->stats.normal, ehci->stats.error, ehci->stats.reclaim, | |
535 | ehci->stats.lost_iaa); | |
536 | ehci_dbg (ehci, "complete %ld unlink %ld\n", | |
537 | ehci->stats.complete, ehci->stats.unlink); | |
1da177e4 | 538 | #endif |
1da177e4 | 539 | |
083522d7 BH |
540 | dbg_status (ehci, "ehci_stop completed", |
541 | ehci_readl(ehci, &ehci->regs->status)); | |
1da177e4 LT |
542 | } |
543 | ||
18807521 DB |
544 | /* one-time init, only for memory state */ |
545 | static int ehci_init(struct usb_hcd *hcd) | |
1da177e4 | 546 | { |
18807521 | 547 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); |
1da177e4 | 548 | u32 temp; |
1da177e4 LT |
549 | int retval; |
550 | u32 hcc_params; | |
3807e26d | 551 | struct ehci_qh_hw *hw; |
18807521 DB |
552 | |
553 | spin_lock_init(&ehci->lock); | |
554 | ||
403dbd36 AD |
555 | /* |
556 | * keep io watchdog by default, those good HCDs could turn off it later | |
557 | */ | |
558 | ehci->need_io_watchdog = 1; | |
18807521 DB |
559 | init_timer(&ehci->watchdog); |
560 | ehci->watchdog.function = ehci_watchdog; | |
561 | ehci->watchdog.data = (unsigned long) ehci; | |
1da177e4 | 562 | |
07d29b63 AS |
563 | init_timer(&ehci->iaa_watchdog); |
564 | ehci->iaa_watchdog.function = ehci_iaa_watchdog; | |
565 | ehci->iaa_watchdog.data = (unsigned long) ehci; | |
566 | ||
1da177e4 LT |
567 | /* |
568 | * hw default: 1K periodic list heads, one per frame. | |
569 | * periodic_size can shrink by USBCMD update if hcc_params allows. | |
570 | */ | |
571 | ehci->periodic_size = DEFAULT_I_TDPS; | |
9aa09d2f | 572 | INIT_LIST_HEAD(&ehci->cached_itd_list); |
0e5f231b | 573 | INIT_LIST_HEAD(&ehci->cached_sitd_list); |
18807521 | 574 | if ((retval = ehci_mem_init(ehci, GFP_KERNEL)) < 0) |
1da177e4 LT |
575 | return retval; |
576 | ||
577 | /* controllers may cache some of the periodic schedule ... */ | |
083522d7 | 578 | hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params); |
53bd6a60 | 579 | if (HCC_ISOC_CACHE(hcc_params)) // full frame cache |
dccd574c | 580 | ehci->i_thresh = 2 + 8; |
1da177e4 | 581 | else // N microframes cached |
18807521 | 582 | ehci->i_thresh = 2 + HCC_ISOC_THRES(hcc_params); |
1da177e4 LT |
583 | |
584 | ehci->reclaim = NULL; | |
1da177e4 | 585 | ehci->next_uframe = -1; |
9aa09d2f | 586 | ehci->clock_frame = -1; |
1da177e4 | 587 | |
1da177e4 LT |
588 | /* |
589 | * dedicate a qh for the async ring head, since we couldn't unlink | |
590 | * a 'real' qh without stopping the async schedule [4.8]. use it | |
591 | * as the 'reclamation list head' too. | |
592 | * its dummy is used in hw_alt_next of many tds, to prevent the qh | |
593 | * from automatically advancing to the next td after short reads. | |
594 | */ | |
18807521 | 595 | ehci->async->qh_next.qh = NULL; |
3807e26d AD |
596 | hw = ehci->async->hw; |
597 | hw->hw_next = QH_NEXT(ehci, ehci->async->qh_dma); | |
598 | hw->hw_info1 = cpu_to_hc32(ehci, QH_HEAD); | |
599 | hw->hw_token = cpu_to_hc32(ehci, QTD_STS_HALT); | |
600 | hw->hw_qtd_next = EHCI_LIST_END(ehci); | |
18807521 | 601 | ehci->async->qh_state = QH_STATE_LINKED; |
3807e26d | 602 | hw->hw_alt_next = QTD_NEXT(ehci, ehci->async->dummy->qtd_dma); |
1da177e4 LT |
603 | |
604 | /* clear interrupt enables, set irq latency */ | |
605 | if (log2_irq_thresh < 0 || log2_irq_thresh > 6) | |
606 | log2_irq_thresh = 0; | |
607 | temp = 1 << (16 + log2_irq_thresh); | |
5a9cdf33 AD |
608 | if (HCC_PER_PORT_CHANGE_EVENT(hcc_params)) { |
609 | ehci->has_ppcd = 1; | |
610 | ehci_dbg(ehci, "enable per-port change event\n"); | |
611 | temp |= CMD_PPCEE; | |
612 | } | |
1da177e4 LT |
613 | if (HCC_CANPARK(hcc_params)) { |
614 | /* HW default park == 3, on hardware that supports it (like | |
615 | * NVidia and ALI silicon), maximizes throughput on the async | |
616 | * schedule by avoiding QH fetches between transfers. | |
617 | * | |
618 | * With fast usb storage devices and NForce2, "park" seems to | |
619 | * make problems: throughput reduction (!), data errors... | |
620 | */ | |
621 | if (park) { | |
18807521 | 622 | park = min(park, (unsigned) 3); |
1da177e4 LT |
623 | temp |= CMD_PARK; |
624 | temp |= park << 8; | |
625 | } | |
18807521 | 626 | ehci_dbg(ehci, "park %d\n", park); |
1da177e4 | 627 | } |
18807521 | 628 | if (HCC_PGM_FRAMELISTLEN(hcc_params)) { |
1da177e4 LT |
629 | /* periodic schedule size can be smaller than default */ |
630 | temp &= ~(3 << 2); | |
631 | temp |= (EHCI_TUNE_FLS << 2); | |
632 | switch (EHCI_TUNE_FLS) { | |
633 | case 0: ehci->periodic_size = 1024; break; | |
634 | case 1: ehci->periodic_size = 512; break; | |
635 | case 2: ehci->periodic_size = 256; break; | |
18807521 | 636 | default: BUG(); |
1da177e4 LT |
637 | } |
638 | } | |
48f24970 AD |
639 | if (HCC_LPM(hcc_params)) { |
640 | /* support link power management EHCI 1.1 addendum */ | |
641 | ehci_dbg(ehci, "support lpm\n"); | |
642 | ehci->has_lpm = 1; | |
643 | if (hird > 0xf) { | |
644 | ehci_dbg(ehci, "hird %d invalid, use default 0", | |
645 | hird); | |
646 | hird = 0; | |
647 | } | |
648 | temp |= hird << 24; | |
649 | } | |
18807521 DB |
650 | ehci->command = temp; |
651 | ||
40f8db8f | 652 | /* Accept arbitrarily long scatter-gather lists */ |
4307a28e AR |
653 | if (!(hcd->driver->flags & HCD_LOCAL_MEM)) |
654 | hcd->self.sg_tablesize = ~0; | |
18807521 DB |
655 | return 0; |
656 | } | |
657 | ||
658 | /* start HC running; it's halted, ehci_init() has been run (once) */ | |
659 | static int ehci_run (struct usb_hcd *hcd) | |
660 | { | |
661 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
662 | int retval; | |
663 | u32 temp; | |
664 | u32 hcc_params; | |
665 | ||
1d619f12 | 666 | hcd->uses_new_polling = 1; |
1d619f12 | 667 | |
18807521 DB |
668 | /* EHCI spec section 4.1 */ |
669 | if ((retval = ehci_reset(ehci)) != 0) { | |
18807521 DB |
670 | ehci_mem_cleanup(ehci); |
671 | return retval; | |
672 | } | |
083522d7 BH |
673 | ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list); |
674 | ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next); | |
18807521 DB |
675 | |
676 | /* | |
677 | * hcc_params controls whether ehci->regs->segment must (!!!) | |
678 | * be used; it constrains QH/ITD/SITD and QTD locations. | |
679 | * pci_pool consistent memory always uses segment zero. | |
680 | * streaming mappings for I/O buffers, like pci_map_single(), | |
681 | * can return segments above 4GB, if the device allows. | |
682 | * | |
683 | * NOTE: the dma mask is visible through dma_supported(), so | |
684 | * drivers can pass this info along ... like NETIF_F_HIGHDMA, | |
685 | * Scsi_Host.highmem_io, and so forth. It's readonly to all | |
686 | * host side drivers though. | |
687 | */ | |
083522d7 | 688 | hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params); |
18807521 | 689 | if (HCC_64BIT_ADDR(hcc_params)) { |
083522d7 | 690 | ehci_writel(ehci, 0, &ehci->regs->segment); |
18807521 DB |
691 | #if 0 |
692 | // this is deeply broken on almost all architectures | |
6a35528a | 693 | if (!dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64))) |
18807521 DB |
694 | ehci_info(ehci, "enabled 64bit DMA\n"); |
695 | #endif | |
696 | } | |
697 | ||
698 | ||
1da177e4 LT |
699 | // Philips, Intel, and maybe others need CMD_RUN before the |
700 | // root hub will detect new devices (why?); NEC doesn't | |
18807521 DB |
701 | ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET); |
702 | ehci->command |= CMD_RUN; | |
083522d7 | 703 | ehci_writel(ehci, ehci->command, &ehci->regs->command); |
18807521 | 704 | dbg_cmd (ehci, "init", ehci->command); |
1da177e4 | 705 | |
1da177e4 LT |
706 | /* |
707 | * Start, enabling full USB 2.0 functionality ... usb 1.1 devices | |
708 | * are explicitly handed to companion controller(s), so no TT is | |
709 | * involved with the root hub. (Except where one is integrated, | |
710 | * and there's no companion controller unless maybe for USB OTG.) | |
32fe0198 AS |
711 | * |
712 | * Turning on the CF flag will transfer ownership of all ports | |
713 | * from the companions to the EHCI controller. If any of the | |
714 | * companions are in the middle of a port reset at the time, it | |
715 | * could cause trouble. Write-locking ehci_cf_port_reset_rwsem | |
1cb52658 DB |
716 | * guarantees that no resets are in progress. After we set CF, |
717 | * a short delay lets the hardware catch up; new resets shouldn't | |
718 | * be started before the port switching actions could complete. | |
1da177e4 | 719 | */ |
32fe0198 | 720 | down_write(&ehci_cf_port_reset_rwsem); |
1da177e4 | 721 | hcd->state = HC_STATE_RUNNING; |
083522d7 BH |
722 | ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag); |
723 | ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */ | |
1cb52658 | 724 | msleep(5); |
32fe0198 | 725 | up_write(&ehci_cf_port_reset_rwsem); |
ee4ecb8a | 726 | ehci->last_periodic_enable = ktime_get_real(); |
1da177e4 | 727 | |
083522d7 | 728 | temp = HC_VERSION(ehci_readl(ehci, &ehci->caps->hc_capbase)); |
1da177e4 | 729 | ehci_info (ehci, |
2b70f073 | 730 | "USB %x.%x started, EHCI %x.%02x%s\n", |
7ff71d6a | 731 | ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f), |
2b70f073 | 732 | temp >> 8, temp & 0xff, |
93f1a47c | 733 | ignore_oc ? ", overcurrent ignored" : ""); |
1da177e4 | 734 | |
083522d7 BH |
735 | ehci_writel(ehci, INTR_MASK, |
736 | &ehci->regs->intr_enable); /* Turn On Interrupts */ | |
1da177e4 | 737 | |
18807521 DB |
738 | /* GRR this is run-once init(), being done every time the HC starts. |
739 | * So long as they're part of class devices, we can't do it init() | |
740 | * since the class device isn't created that early. | |
741 | */ | |
742 | create_debug_files(ehci); | |
57e06c11 | 743 | create_companion_file(ehci); |
1da177e4 LT |
744 | |
745 | return 0; | |
746 | } | |
747 | ||
1da177e4 LT |
748 | /*-------------------------------------------------------------------------*/ |
749 | ||
7d12e780 | 750 | static irqreturn_t ehci_irq (struct usb_hcd *hcd) |
1da177e4 LT |
751 | { |
752 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
67b2e029 | 753 | u32 status, masked_status, pcd_status = 0, cmd; |
1da177e4 LT |
754 | int bh; |
755 | ||
756 | spin_lock (&ehci->lock); | |
757 | ||
083522d7 | 758 | status = ehci_readl(ehci, &ehci->regs->status); |
1da177e4 LT |
759 | |
760 | /* e.g. cardbus physical eject */ | |
761 | if (status == ~(u32) 0) { | |
762 | ehci_dbg (ehci, "device removed\n"); | |
763 | goto dead; | |
764 | } | |
765 | ||
67b2e029 AS |
766 | masked_status = status & INTR_MASK; |
767 | if (!masked_status) { /* irq sharing? */ | |
1da177e4 LT |
768 | spin_unlock(&ehci->lock); |
769 | return IRQ_NONE; | |
770 | } | |
771 | ||
772 | /* clear (just) interrupts */ | |
67b2e029 | 773 | ehci_writel(ehci, masked_status, &ehci->regs->status); |
e82cc128 | 774 | cmd = ehci_readl(ehci, &ehci->regs->command); |
1da177e4 LT |
775 | bh = 0; |
776 | ||
9776afc8 | 777 | #ifdef VERBOSE_DEBUG |
1da177e4 LT |
778 | /* unrequested/ignored: Frame List Rollover */ |
779 | dbg_status (ehci, "irq", status); | |
780 | #endif | |
781 | ||
782 | /* INT, ERR, and IAA interrupt rates can be throttled */ | |
783 | ||
784 | /* normal [4.15.1.2] or error [4.15.1.1] completion */ | |
785 | if (likely ((status & (STS_INT|STS_ERR)) != 0)) { | |
786 | if (likely ((status & STS_ERR) == 0)) | |
787 | COUNT (ehci->stats.normal); | |
788 | else | |
789 | COUNT (ehci->stats.error); | |
790 | bh = 1; | |
791 | } | |
792 | ||
793 | /* complete the unlinking of some qh [4.15.2.3] */ | |
794 | if (status & STS_IAA) { | |
e82cc128 DB |
795 | /* guard against (alleged) silicon errata */ |
796 | if (cmd & CMD_IAAD) { | |
797 | ehci_writel(ehci, cmd & ~CMD_IAAD, | |
798 | &ehci->regs->command); | |
799 | ehci_dbg(ehci, "IAA with IAAD still set?\n"); | |
800 | } | |
801 | if (ehci->reclaim) { | |
802 | COUNT(ehci->stats.reclaim); | |
803 | end_unlink_async(ehci); | |
804 | } else | |
805 | ehci_dbg(ehci, "IAA with nothing to reclaim?\n"); | |
1da177e4 LT |
806 | } |
807 | ||
808 | /* remote wakeup [4.3.1] */ | |
d97cc2f2 | 809 | if (status & STS_PCD) { |
1da177e4 | 810 | unsigned i = HCS_N_PORTS (ehci->hcs_params); |
5a9cdf33 | 811 | u32 ppcd = 0; |
d1b1842c DB |
812 | |
813 | /* kick root hub later */ | |
1d619f12 | 814 | pcd_status = status; |
1da177e4 LT |
815 | |
816 | /* resume root hub? */ | |
eafe5b99 | 817 | if (!(cmd & CMD_RUN)) |
8c03356a | 818 | usb_hcd_resume_root_hub(hcd); |
1da177e4 | 819 | |
5a9cdf33 AD |
820 | /* get per-port change detect bits */ |
821 | if (ehci->has_ppcd) | |
822 | ppcd = status >> 16; | |
823 | ||
1da177e4 | 824 | while (i--) { |
5a9cdf33 AD |
825 | int pstatus; |
826 | ||
827 | /* leverage per-port change bits feature */ | |
828 | if (ehci->has_ppcd && !(ppcd & (1 << i))) | |
829 | continue; | |
830 | pstatus = ehci_readl(ehci, | |
831 | &ehci->regs->port_status[i]); | |
b972b68c DB |
832 | |
833 | if (pstatus & PORT_OWNER) | |
1da177e4 | 834 | continue; |
eafe5b99 AS |
835 | if (!(test_bit(i, &ehci->suspended_ports) && |
836 | ((pstatus & PORT_RESUME) || | |
837 | !(pstatus & PORT_SUSPEND)) && | |
838 | (pstatus & PORT_PE) && | |
839 | ehci->reset_done[i] == 0)) | |
1da177e4 LT |
840 | continue; |
841 | ||
842 | /* start 20 msec resume signaling from this port, | |
843 | * and make khubd collect PORT_STAT_C_SUSPEND to | |
49d0f078 AS |
844 | * stop that signaling. Use 5 ms extra for safety, |
845 | * like usb_port_resume() does. | |
1da177e4 | 846 | */ |
49d0f078 | 847 | ehci->reset_done[i] = jiffies + msecs_to_jiffies(25); |
1da177e4 | 848 | ehci_dbg (ehci, "port %d remote wakeup\n", i + 1); |
61e8b858 | 849 | mod_timer(&hcd->rh_timer, ehci->reset_done[i]); |
1da177e4 LT |
850 | } |
851 | } | |
852 | ||
853 | /* PCI errors [4.15.2.4] */ | |
854 | if (unlikely ((status & STS_FATAL) != 0)) { | |
67b2e029 | 855 | ehci_err(ehci, "fatal error\n"); |
eafe5b99 AS |
856 | dbg_cmd(ehci, "fatal", cmd); |
857 | dbg_status(ehci, "fatal", status); | |
67b2e029 | 858 | ehci_halt(ehci); |
1da177e4 | 859 | dead: |
67b2e029 AS |
860 | ehci_reset(ehci); |
861 | ehci_writel(ehci, 0, &ehci->regs->configured_flag); | |
862 | /* generic layer kills/unlinks all urbs, then | |
863 | * uses ehci_stop to clean up the rest | |
864 | */ | |
865 | bh = 1; | |
1da177e4 LT |
866 | } |
867 | ||
868 | if (bh) | |
7d12e780 | 869 | ehci_work (ehci); |
1da177e4 | 870 | spin_unlock (&ehci->lock); |
d1b1842c | 871 | if (pcd_status) |
1d619f12 | 872 | usb_hcd_poll_rh_status(hcd); |
1da177e4 LT |
873 | return IRQ_HANDLED; |
874 | } | |
875 | ||
876 | /*-------------------------------------------------------------------------*/ | |
877 | ||
878 | /* | |
879 | * non-error returns are a promise to giveback() the urb later | |
880 | * we drop ownership so next owner (or urb unlink) can get it | |
881 | * | |
882 | * urb + dev is in hcd.self.controller.urb_list | |
883 | * we're queueing TDs onto software and hardware lists | |
884 | * | |
885 | * hcd-specific init for hcpriv hasn't been done yet | |
886 | * | |
887 | * NOTE: control, bulk, and interrupt share the same code to append TDs | |
888 | * to a (possibly active) QH, and the same QH scanning code. | |
889 | */ | |
890 | static int ehci_urb_enqueue ( | |
891 | struct usb_hcd *hcd, | |
1da177e4 | 892 | struct urb *urb, |
55016f10 | 893 | gfp_t mem_flags |
1da177e4 LT |
894 | ) { |
895 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
896 | struct list_head qtd_list; | |
897 | ||
898 | INIT_LIST_HEAD (&qtd_list); | |
899 | ||
900 | switch (usb_pipetype (urb->pipe)) { | |
25b70a86 DB |
901 | case PIPE_CONTROL: |
902 | /* qh_completions() code doesn't handle all the fault cases | |
903 | * in multi-TD control transfers. Even 1KB is rare anyway. | |
904 | */ | |
905 | if (urb->transfer_buffer_length > (16 * 1024)) | |
906 | return -EMSGSIZE; | |
907 | /* FALLTHROUGH */ | |
908 | /* case PIPE_BULK: */ | |
1da177e4 LT |
909 | default: |
910 | if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags)) | |
911 | return -ENOMEM; | |
e9df41c5 | 912 | return submit_async(ehci, urb, &qtd_list, mem_flags); |
1da177e4 LT |
913 | |
914 | case PIPE_INTERRUPT: | |
915 | if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags)) | |
916 | return -ENOMEM; | |
e9df41c5 | 917 | return intr_submit(ehci, urb, &qtd_list, mem_flags); |
1da177e4 LT |
918 | |
919 | case PIPE_ISOCHRONOUS: | |
920 | if (urb->dev->speed == USB_SPEED_HIGH) | |
921 | return itd_submit (ehci, urb, mem_flags); | |
922 | else | |
923 | return sitd_submit (ehci, urb, mem_flags); | |
924 | } | |
925 | } | |
926 | ||
927 | static void unlink_async (struct ehci_hcd *ehci, struct ehci_qh *qh) | |
928 | { | |
07d29b63 | 929 | /* failfast */ |
e82cc128 | 930 | if (!HC_IS_RUNNING(ehci_to_hcd(ehci)->state) && ehci->reclaim) |
07d29b63 AS |
931 | end_unlink_async(ehci); |
932 | ||
3a44494e AS |
933 | /* If the QH isn't linked then there's nothing we can do |
934 | * unless we were called during a giveback, in which case | |
935 | * qh_completions() has to deal with it. | |
936 | */ | |
937 | if (qh->qh_state != QH_STATE_LINKED) { | |
938 | if (qh->qh_state == QH_STATE_COMPLETING) | |
939 | qh->needs_rescan = 1; | |
940 | return; | |
941 | } | |
07d29b63 AS |
942 | |
943 | /* defer till later if busy */ | |
3a44494e | 944 | if (ehci->reclaim) { |
1da177e4 LT |
945 | struct ehci_qh *last; |
946 | ||
947 | for (last = ehci->reclaim; | |
948 | last->reclaim; | |
949 | last = last->reclaim) | |
950 | continue; | |
951 | qh->qh_state = QH_STATE_UNLINK_WAIT; | |
952 | last->reclaim = qh; | |
953 | ||
07d29b63 AS |
954 | /* start IAA cycle */ |
955 | } else | |
1da177e4 LT |
956 | start_unlink_async (ehci, qh); |
957 | } | |
958 | ||
959 | /* remove from hardware lists | |
960 | * completions normally happen asynchronously | |
961 | */ | |
962 | ||
e9df41c5 | 963 | static int ehci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) |
1da177e4 LT |
964 | { |
965 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
966 | struct ehci_qh *qh; | |
967 | unsigned long flags; | |
e9df41c5 | 968 | int rc; |
1da177e4 LT |
969 | |
970 | spin_lock_irqsave (&ehci->lock, flags); | |
e9df41c5 AS |
971 | rc = usb_hcd_check_unlink_urb(hcd, urb, status); |
972 | if (rc) | |
973 | goto done; | |
974 | ||
1da177e4 LT |
975 | switch (usb_pipetype (urb->pipe)) { |
976 | // case PIPE_CONTROL: | |
977 | // case PIPE_BULK: | |
978 | default: | |
979 | qh = (struct ehci_qh *) urb->hcpriv; | |
980 | if (!qh) | |
981 | break; | |
07d29b63 AS |
982 | switch (qh->qh_state) { |
983 | case QH_STATE_LINKED: | |
984 | case QH_STATE_COMPLETING: | |
985 | unlink_async(ehci, qh); | |
986 | break; | |
987 | case QH_STATE_UNLINK: | |
988 | case QH_STATE_UNLINK_WAIT: | |
989 | /* already started */ | |
990 | break; | |
991 | case QH_STATE_IDLE: | |
7a0f0d95 AS |
992 | /* QH might be waiting for a Clear-TT-Buffer */ |
993 | qh_completions(ehci, qh); | |
07d29b63 AS |
994 | break; |
995 | } | |
1da177e4 LT |
996 | break; |
997 | ||
998 | case PIPE_INTERRUPT: | |
999 | qh = (struct ehci_qh *) urb->hcpriv; | |
1000 | if (!qh) | |
1001 | break; | |
1002 | switch (qh->qh_state) { | |
1003 | case QH_STATE_LINKED: | |
a448c9d8 | 1004 | case QH_STATE_COMPLETING: |
1da177e4 | 1005 | intr_deschedule (ehci, qh); |
a448c9d8 | 1006 | break; |
1da177e4 | 1007 | case QH_STATE_IDLE: |
7d12e780 | 1008 | qh_completions (ehci, qh); |
1da177e4 LT |
1009 | break; |
1010 | default: | |
1011 | ehci_dbg (ehci, "bogus qh %p state %d\n", | |
1012 | qh, qh->qh_state); | |
1013 | goto done; | |
1014 | } | |
1da177e4 LT |
1015 | break; |
1016 | ||
1017 | case PIPE_ISOCHRONOUS: | |
1018 | // itd or sitd ... | |
1019 | ||
1020 | // wait till next completion, do it then. | |
1021 | // completion irqs can wait up to 1024 msec, | |
1022 | break; | |
1023 | } | |
1024 | done: | |
1025 | spin_unlock_irqrestore (&ehci->lock, flags); | |
e9df41c5 | 1026 | return rc; |
1da177e4 LT |
1027 | } |
1028 | ||
1029 | /*-------------------------------------------------------------------------*/ | |
1030 | ||
1031 | // bulk qh holds the data toggle | |
1032 | ||
1033 | static void | |
1034 | ehci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep) | |
1035 | { | |
1036 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
1037 | unsigned long flags; | |
1038 | struct ehci_qh *qh, *tmp; | |
1039 | ||
1040 | /* ASSERT: any requests/urbs are being unlinked */ | |
1041 | /* ASSERT: nobody can be submitting urbs for this any more */ | |
1042 | ||
1043 | rescan: | |
1044 | spin_lock_irqsave (&ehci->lock, flags); | |
1045 | qh = ep->hcpriv; | |
1046 | if (!qh) | |
1047 | goto done; | |
1048 | ||
1049 | /* endpoints can be iso streams. for now, we don't | |
1050 | * accelerate iso completions ... so spin a while. | |
1051 | */ | |
1082f57a | 1052 | if (qh->hw == NULL) { |
1da177e4 LT |
1053 | ehci_vdbg (ehci, "iso delay\n"); |
1054 | goto idle_timeout; | |
1055 | } | |
1056 | ||
1057 | if (!HC_IS_RUNNING (hcd->state)) | |
1058 | qh->qh_state = QH_STATE_IDLE; | |
1059 | switch (qh->qh_state) { | |
1060 | case QH_STATE_LINKED: | |
3a44494e | 1061 | case QH_STATE_COMPLETING: |
1da177e4 LT |
1062 | for (tmp = ehci->async->qh_next.qh; |
1063 | tmp && tmp != qh; | |
1064 | tmp = tmp->qh_next.qh) | |
1065 | continue; | |
1066 | /* periodic qh self-unlinks on empty */ | |
1067 | if (!tmp) | |
1068 | goto nogood; | |
1069 | unlink_async (ehci, qh); | |
1070 | /* FALL THROUGH */ | |
1071 | case QH_STATE_UNLINK: /* wait for hw to finish? */ | |
07d29b63 | 1072 | case QH_STATE_UNLINK_WAIT: |
1da177e4 LT |
1073 | idle_timeout: |
1074 | spin_unlock_irqrestore (&ehci->lock, flags); | |
22c43863 | 1075 | schedule_timeout_uninterruptible(1); |
1da177e4 LT |
1076 | goto rescan; |
1077 | case QH_STATE_IDLE: /* fully unlinked */ | |
914b7012 AS |
1078 | if (qh->clearing_tt) |
1079 | goto idle_timeout; | |
1da177e4 LT |
1080 | if (list_empty (&qh->qtd_list)) { |
1081 | qh_put (qh); | |
1082 | break; | |
1083 | } | |
1084 | /* else FALL THROUGH */ | |
1085 | default: | |
1086 | nogood: | |
1087 | /* caller was supposed to have unlinked any requests; | |
1088 | * that's not our job. just leak this memory. | |
1089 | */ | |
1090 | ehci_err (ehci, "qh %p (#%02x) state %d%s\n", | |
1091 | qh, ep->desc.bEndpointAddress, qh->qh_state, | |
1092 | list_empty (&qh->qtd_list) ? "" : "(has tds)"); | |
1093 | break; | |
1094 | } | |
1095 | ep->hcpriv = NULL; | |
1096 | done: | |
1097 | spin_unlock_irqrestore (&ehci->lock, flags); | |
1da177e4 LT |
1098 | } |
1099 | ||
b18ffd49 AS |
1100 | static void |
1101 | ehci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep) | |
1102 | { | |
1103 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | |
1104 | struct ehci_qh *qh; | |
1105 | int eptype = usb_endpoint_type(&ep->desc); | |
a455212d AS |
1106 | int epnum = usb_endpoint_num(&ep->desc); |
1107 | int is_out = usb_endpoint_dir_out(&ep->desc); | |
1108 | unsigned long flags; | |
b18ffd49 AS |
1109 | |
1110 | if (eptype != USB_ENDPOINT_XFER_BULK && eptype != USB_ENDPOINT_XFER_INT) | |
1111 | return; | |
1112 | ||
a455212d | 1113 | spin_lock_irqsave(&ehci->lock, flags); |
b18ffd49 AS |
1114 | qh = ep->hcpriv; |
1115 | ||
1116 | /* For Bulk and Interrupt endpoints we maintain the toggle state | |
1117 | * in the hardware; the toggle bits in udev aren't used at all. | |
1118 | * When an endpoint is reset by usb_clear_halt() we must reset | |
1119 | * the toggle bit in the QH. | |
1120 | */ | |
1121 | if (qh) { | |
a455212d | 1122 | usb_settoggle(qh->dev, epnum, is_out, 0); |
b18ffd49 AS |
1123 | if (!list_empty(&qh->qtd_list)) { |
1124 | WARN_ONCE(1, "clear_halt for a busy endpoint\n"); | |
3a44494e AS |
1125 | } else if (qh->qh_state == QH_STATE_LINKED || |
1126 | qh->qh_state == QH_STATE_COMPLETING) { | |
a455212d AS |
1127 | |
1128 | /* The toggle value in the QH can't be updated | |
1129 | * while the QH is active. Unlink it now; | |
1130 | * re-linking will call qh_refresh(). | |
b18ffd49 | 1131 | */ |
a448c9d8 | 1132 | if (eptype == USB_ENDPOINT_XFER_BULK) |
a455212d | 1133 | unlink_async(ehci, qh); |
a448c9d8 | 1134 | else |
a455212d | 1135 | intr_deschedule(ehci, qh); |
b18ffd49 AS |
1136 | } |
1137 | } | |
a455212d | 1138 | spin_unlock_irqrestore(&ehci->lock, flags); |
b18ffd49 AS |
1139 | } |
1140 | ||
7ff71d6a MP |
1141 | static int ehci_get_frame (struct usb_hcd *hcd) |
1142 | { | |
1143 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
083522d7 BH |
1144 | return (ehci_readl(ehci, &ehci->regs->frame_index) >> 3) % |
1145 | ehci->periodic_size; | |
7ff71d6a | 1146 | } |
1da177e4 LT |
1147 | |
1148 | /*-------------------------------------------------------------------------*/ | |
1149 | ||
2b70f073 | 1150 | MODULE_DESCRIPTION(DRIVER_DESC); |
1da177e4 LT |
1151 | MODULE_AUTHOR (DRIVER_AUTHOR); |
1152 | MODULE_LICENSE ("GPL"); | |
1153 | ||
7ff71d6a MP |
1154 | #ifdef CONFIG_PCI |
1155 | #include "ehci-pci.c" | |
01cced25 | 1156 | #define PCI_DRIVER ehci_pci_driver |
7ff71d6a | 1157 | #endif |
1da177e4 | 1158 | |
ba02978a | 1159 | #ifdef CONFIG_USB_EHCI_FSL |
80cb9aee | 1160 | #include "ehci-fsl.c" |
01cced25 | 1161 | #define PLATFORM_DRIVER ehci_fsl_driver |
80cb9aee RV |
1162 | #endif |
1163 | ||
7e8d5cd9 DM |
1164 | #ifdef CONFIG_USB_EHCI_MXC |
1165 | #include "ehci-mxc.c" | |
1166 | #define PLATFORM_DRIVER ehci_mxc_driver | |
1167 | #endif | |
1168 | ||
dfbaa7d8 | 1169 | #ifdef CONFIG_SOC_AU1200 |
76fa9a24 | 1170 | #include "ehci-au1xxx.c" |
01cced25 | 1171 | #define PLATFORM_DRIVER ehci_hcd_au1xxx_driver |
76fa9a24 JC |
1172 | #endif |
1173 | ||
a8eb7ca0 | 1174 | #ifdef CONFIG_ARCH_OMAP3 |
54ab2b02 FB |
1175 | #include "ehci-omap.c" |
1176 | #define PLATFORM_DRIVER ehci_hcd_omap_driver | |
1177 | #endif | |
1178 | ||
ad75a410 GL |
1179 | #ifdef CONFIG_PPC_PS3 |
1180 | #include "ehci-ps3.c" | |
7a4eb7fd | 1181 | #define PS3_SYSTEM_BUS_DRIVER ps3_ehci_driver |
ad75a410 GL |
1182 | #endif |
1183 | ||
da0e8fb0 VB |
1184 | #ifdef CONFIG_USB_EHCI_HCD_PPC_OF |
1185 | #include "ehci-ppc-of.c" | |
1186 | #define OF_PLATFORM_DRIVER ehci_hcd_ppc_of_driver | |
1187 | #endif | |
1188 | ||
08d3c18e JZ |
1189 | #ifdef CONFIG_XPS_USB_HCD_XILINX |
1190 | #include "ehci-xilinx-of.c" | |
1f23b2d9 | 1191 | #define XILINX_OF_PLATFORM_DRIVER ehci_hcd_xilinx_of_driver |
08d3c18e JZ |
1192 | #endif |
1193 | ||
705a7521 | 1194 | #ifdef CONFIG_PLAT_ORION |
e96ffe2f TP |
1195 | #include "ehci-orion.c" |
1196 | #define PLATFORM_DRIVER ehci_orion_driver | |
1197 | #endif | |
1198 | ||
91bc4d31 VB |
1199 | #ifdef CONFIG_ARCH_IXP4XX |
1200 | #include "ehci-ixp4xx.c" | |
1201 | #define PLATFORM_DRIVER ixp4xx_ehci_driver | |
1202 | #endif | |
1203 | ||
586dfc8c WZ |
1204 | #ifdef CONFIG_USB_W90X900_EHCI |
1205 | #include "ehci-w90x900.c" | |
1206 | #define PLATFORM_DRIVER ehci_hcd_w90x900_driver | |
1207 | #endif | |
1208 | ||
501c9c08 NF |
1209 | #ifdef CONFIG_ARCH_AT91 |
1210 | #include "ehci-atmel.c" | |
1211 | #define PLATFORM_DRIVER ehci_atmel_driver | |
1212 | #endif | |
1213 | ||
1643accd DD |
1214 | #ifdef CONFIG_USB_OCTEON_EHCI |
1215 | #include "ehci-octeon.c" | |
1216 | #define PLATFORM_DRIVER ehci_octeon_driver | |
1217 | #endif | |
1218 | ||
ad78acaf AC |
1219 | #ifdef CONFIG_ARCH_VT8500 |
1220 | #include "ehci-vt8500.c" | |
1221 | #define PLATFORM_DRIVER vt8500_ehci_driver | |
1222 | #endif | |
1223 | ||
ad75a410 | 1224 | #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \ |
1f23b2d9 GL |
1225 | !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \ |
1226 | !defined(XILINX_OF_PLATFORM_DRIVER) | |
7ff71d6a MP |
1227 | #error "missing bus glue for ehci-hcd" |
1228 | #endif | |
01cced25 KG |
1229 | |
1230 | static int __init ehci_hcd_init(void) | |
1231 | { | |
1232 | int retval = 0; | |
1233 | ||
2b70f073 AS |
1234 | if (usb_disabled()) |
1235 | return -ENODEV; | |
1236 | ||
1237 | printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name); | |
9beeee65 AS |
1238 | set_bit(USB_EHCI_LOADED, &usb_hcds_loaded); |
1239 | if (test_bit(USB_UHCI_LOADED, &usb_hcds_loaded) || | |
1240 | test_bit(USB_OHCI_LOADED, &usb_hcds_loaded)) | |
1241 | printk(KERN_WARNING "Warning! ehci_hcd should always be loaded" | |
1242 | " before uhci_hcd and ohci_hcd, not after\n"); | |
1243 | ||
01cced25 KG |
1244 | pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n", |
1245 | hcd_name, | |
1246 | sizeof(struct ehci_qh), sizeof(struct ehci_qtd), | |
1247 | sizeof(struct ehci_itd), sizeof(struct ehci_sitd)); | |
1248 | ||
694cc208 | 1249 | #ifdef DEBUG |
08f4e586 | 1250 | ehci_debug_root = debugfs_create_dir("ehci", usb_debug_root); |
9beeee65 AS |
1251 | if (!ehci_debug_root) { |
1252 | retval = -ENOENT; | |
1253 | goto err_debug; | |
1254 | } | |
694cc208 TJ |
1255 | #endif |
1256 | ||
01cced25 KG |
1257 | #ifdef PLATFORM_DRIVER |
1258 | retval = platform_driver_register(&PLATFORM_DRIVER); | |
da0e8fb0 VB |
1259 | if (retval < 0) |
1260 | goto clean0; | |
01cced25 KG |
1261 | #endif |
1262 | ||
1263 | #ifdef PCI_DRIVER | |
1264 | retval = pci_register_driver(&PCI_DRIVER); | |
da0e8fb0 VB |
1265 | if (retval < 0) |
1266 | goto clean1; | |
ad75a410 GL |
1267 | #endif |
1268 | ||
1269 | #ifdef PS3_SYSTEM_BUS_DRIVER | |
7a4eb7fd | 1270 | retval = ps3_ehci_driver_register(&PS3_SYSTEM_BUS_DRIVER); |
da0e8fb0 VB |
1271 | if (retval < 0) |
1272 | goto clean2; | |
694cc208 | 1273 | #endif |
da0e8fb0 VB |
1274 | |
1275 | #ifdef OF_PLATFORM_DRIVER | |
1276 | retval = of_register_platform_driver(&OF_PLATFORM_DRIVER); | |
1277 | if (retval < 0) | |
1278 | goto clean3; | |
1279 | #endif | |
1f23b2d9 GL |
1280 | |
1281 | #ifdef XILINX_OF_PLATFORM_DRIVER | |
1282 | retval = of_register_platform_driver(&XILINX_OF_PLATFORM_DRIVER); | |
1283 | if (retval < 0) | |
1284 | goto clean4; | |
1285 | #endif | |
da0e8fb0 VB |
1286 | return retval; |
1287 | ||
1f23b2d9 GL |
1288 | #ifdef XILINX_OF_PLATFORM_DRIVER |
1289 | /* of_unregister_platform_driver(&XILINX_OF_PLATFORM_DRIVER); */ | |
1290 | clean4: | |
1291 | #endif | |
da0e8fb0 | 1292 | #ifdef OF_PLATFORM_DRIVER |
1f23b2d9 | 1293 | of_unregister_platform_driver(&OF_PLATFORM_DRIVER); |
da0e8fb0 VB |
1294 | clean3: |
1295 | #endif | |
1296 | #ifdef PS3_SYSTEM_BUS_DRIVER | |
1297 | ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); | |
1298 | clean2: | |
ad75a410 GL |
1299 | #endif |
1300 | #ifdef PCI_DRIVER | |
da0e8fb0 VB |
1301 | pci_unregister_driver(&PCI_DRIVER); |
1302 | clean1: | |
ad75a410 | 1303 | #endif |
da0e8fb0 VB |
1304 | #ifdef PLATFORM_DRIVER |
1305 | platform_driver_unregister(&PLATFORM_DRIVER); | |
1306 | clean0: | |
1307 | #endif | |
1308 | #ifdef DEBUG | |
1309 | debugfs_remove(ehci_debug_root); | |
1310 | ehci_debug_root = NULL; | |
9beeee65 | 1311 | err_debug: |
a9b6148d | 1312 | #endif |
9beeee65 | 1313 | clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded); |
01cced25 KG |
1314 | return retval; |
1315 | } | |
1316 | module_init(ehci_hcd_init); | |
1317 | ||
1318 | static void __exit ehci_hcd_cleanup(void) | |
1319 | { | |
1f23b2d9 GL |
1320 | #ifdef XILINX_OF_PLATFORM_DRIVER |
1321 | of_unregister_platform_driver(&XILINX_OF_PLATFORM_DRIVER); | |
1322 | #endif | |
da0e8fb0 VB |
1323 | #ifdef OF_PLATFORM_DRIVER |
1324 | of_unregister_platform_driver(&OF_PLATFORM_DRIVER); | |
1325 | #endif | |
01cced25 KG |
1326 | #ifdef PLATFORM_DRIVER |
1327 | platform_driver_unregister(&PLATFORM_DRIVER); | |
1328 | #endif | |
1329 | #ifdef PCI_DRIVER | |
1330 | pci_unregister_driver(&PCI_DRIVER); | |
1331 | #endif | |
ad75a410 | 1332 | #ifdef PS3_SYSTEM_BUS_DRIVER |
7a4eb7fd | 1333 | ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); |
ad75a410 | 1334 | #endif |
694cc208 TJ |
1335 | #ifdef DEBUG |
1336 | debugfs_remove(ehci_debug_root); | |
1337 | #endif | |
9beeee65 | 1338 | clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded); |
01cced25 KG |
1339 | } |
1340 | module_exit(ehci_hcd_cleanup); | |
1341 |