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Commit | Line | Data |
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7ff71d6a MP |
1 | /* |
2 | * EHCI HCD (Host Controller Driver) PCI Bus Glue. | |
3 | * | |
4 | * Copyright (c) 2000-2004 by David Brownell | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License as published by the | |
8 | * Free Software Foundation; either version 2 of the License, or (at your | |
9 | * option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but | |
12 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
13 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
14 | * for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software Foundation, | |
18 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
19 | */ | |
20 | ||
21 | #ifndef CONFIG_PCI | |
22 | #error "This file is PCI bus glue. CONFIG_PCI must be defined." | |
23 | #endif | |
24 | ||
25 | /*-------------------------------------------------------------------------*/ | |
26 | ||
18807521 DB |
27 | /* called after powerup, by probe or system-pm "wakeup" */ |
28 | static int ehci_pci_reinit(struct ehci_hcd *ehci, struct pci_dev *pdev) | |
29 | { | |
30 | u32 temp; | |
31 | int retval; | |
18807521 DB |
32 | |
33 | /* optional debug port, normally in the first BAR */ | |
34 | temp = pci_find_capability(pdev, 0x0a); | |
35 | if (temp) { | |
36 | pci_read_config_dword(pdev, temp, &temp); | |
37 | temp >>= 16; | |
38 | if ((temp & (3 << 13)) == (1 << 13)) { | |
39 | temp &= 0x1fff; | |
40 | ehci->debug = ehci_to_hcd(ehci)->regs + temp; | |
41 | temp = readl(&ehci->debug->control); | |
42 | ehci_info(ehci, "debug port %d%s\n", | |
43 | HCS_DEBUG_PORT(ehci->hcs_params), | |
44 | (temp & DBGP_ENABLED) | |
45 | ? " IN USE" | |
46 | : ""); | |
47 | if (!(temp & DBGP_ENABLED)) | |
48 | ehci->debug = NULL; | |
49 | } | |
50 | } | |
51 | ||
401feafa DB |
52 | /* we expect static quirk code to handle the "extended capabilities" |
53 | * (currently just BIOS handoff) allowed starting with EHCI 0.96 | |
54 | */ | |
18807521 DB |
55 | |
56 | /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ | |
57 | retval = pci_set_mwi(pdev); | |
58 | if (!retval) | |
59 | ehci_dbg(ehci, "MWI active\n"); | |
60 | ||
61 | ehci_port_power(ehci, 0); | |
62 | ||
63 | return 0; | |
64 | } | |
65 | ||
8926bfa7 DB |
66 | /* called during probe() after chip reset completes */ |
67 | static int ehci_pci_setup(struct usb_hcd *hcd) | |
7ff71d6a | 68 | { |
abcc9448 DB |
69 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); |
70 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); | |
7ff71d6a | 71 | u32 temp; |
18807521 | 72 | int retval; |
7ff71d6a MP |
73 | |
74 | ehci->caps = hcd->regs; | |
abcc9448 DB |
75 | ehci->regs = hcd->regs + HC_LENGTH(readl(&ehci->caps->hc_capbase)); |
76 | dbg_hcs_params(ehci, "reset"); | |
77 | dbg_hcc_params(ehci, "reset"); | |
7ff71d6a | 78 | |
c32ba30f PS |
79 | /* ehci_init() causes memory for DMA transfers to be |
80 | * allocated. Thus, any vendor-specific workarounds based on | |
81 | * limiting the type of memory used for DMA transfers must | |
82 | * happen before ehci_init() is called. */ | |
83 | switch (pdev->vendor) { | |
84 | case PCI_VENDOR_ID_NVIDIA: | |
85 | /* NVidia reports that certain chips don't handle | |
86 | * QH, ITD, or SITD addresses above 2GB. (But TD, | |
87 | * data buffer, and periodic schedule are normal.) | |
88 | */ | |
89 | switch (pdev->device) { | |
90 | case 0x003c: /* MCP04 */ | |
91 | case 0x005b: /* CK804 */ | |
92 | case 0x00d8: /* CK8 */ | |
93 | case 0x00e8: /* CK8S */ | |
94 | if (pci_set_consistent_dma_mask(pdev, | |
95 | DMA_31BIT_MASK) < 0) | |
96 | ehci_warn(ehci, "can't enable NVidia " | |
97 | "workaround for >2GB RAM\n"); | |
98 | break; | |
99 | } | |
100 | break; | |
101 | } | |
102 | ||
7ff71d6a | 103 | /* cache this readonly data; minimize chip reads */ |
abcc9448 | 104 | ehci->hcs_params = readl(&ehci->caps->hcs_params); |
7ff71d6a | 105 | |
18807521 DB |
106 | retval = ehci_halt(ehci); |
107 | if (retval) | |
108 | return retval; | |
109 | ||
8926bfa7 DB |
110 | /* data structure init */ |
111 | retval = ehci_init(hcd); | |
112 | if (retval) | |
113 | return retval; | |
114 | ||
abcc9448 DB |
115 | switch (pdev->vendor) { |
116 | case PCI_VENDOR_ID_TDI: | |
117 | if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) { | |
118 | ehci->is_tdi_rh_tt = 1; | |
119 | tdi_reset(ehci); | |
120 | } | |
121 | break; | |
122 | case PCI_VENDOR_ID_AMD: | |
123 | /* AMD8111 EHCI doesn't work, according to AMD errata */ | |
124 | if (pdev->device == 0x7463) { | |
125 | ehci_info(ehci, "ignoring AMD8111 (errata)\n"); | |
8926bfa7 DB |
126 | retval = -EIO; |
127 | goto done; | |
abcc9448 DB |
128 | } |
129 | break; | |
130 | case PCI_VENDOR_ID_NVIDIA: | |
f8aeb3bb | 131 | switch (pdev->device) { |
f8aeb3bb DB |
132 | /* Some NForce2 chips have problems with selective suspend; |
133 | * fixed in newer silicon. | |
134 | */ | |
135 | case 0x0068: | |
136 | pci_read_config_dword(pdev, PCI_REVISION_ID, &temp); | |
137 | if ((temp & 0xff) < 0xa4) | |
138 | ehci->no_selective_suspend = 1; | |
139 | break; | |
7ff71d6a | 140 | } |
abcc9448 DB |
141 | break; |
142 | } | |
7ff71d6a | 143 | |
7ff71d6a | 144 | if (ehci_is_TDI(ehci)) |
abcc9448 | 145 | ehci_reset(ehci); |
7ff71d6a | 146 | |
7ff71d6a MP |
147 | /* at least the Genesys GL880S needs fixup here */ |
148 | temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params); | |
149 | temp &= 0x0f; | |
150 | if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) { | |
abcc9448 | 151 | ehci_dbg(ehci, "bogus port configuration: " |
7ff71d6a MP |
152 | "cc=%d x pcc=%d < ports=%d\n", |
153 | HCS_N_CC(ehci->hcs_params), | |
154 | HCS_N_PCC(ehci->hcs_params), | |
155 | HCS_N_PORTS(ehci->hcs_params)); | |
156 | ||
abcc9448 DB |
157 | switch (pdev->vendor) { |
158 | case 0x17a0: /* GENESYS */ | |
159 | /* GL880S: should be PORTS=2 */ | |
160 | temp |= (ehci->hcs_params & ~0xf); | |
161 | ehci->hcs_params = temp; | |
162 | break; | |
163 | case PCI_VENDOR_ID_NVIDIA: | |
164 | /* NF4: should be PCC=10 */ | |
165 | break; | |
7ff71d6a MP |
166 | } |
167 | } | |
168 | ||
abcc9448 DB |
169 | /* Serial Bus Release Number is at PCI 0x60 offset */ |
170 | pci_read_config_byte(pdev, 0x60, &ehci->sbrn); | |
7ff71d6a | 171 | |
2c1c3c4c DB |
172 | /* Workaround current PCI init glitch: wakeup bits aren't |
173 | * being set from PCI PM capability. | |
174 | */ | |
175 | if (!device_can_wakeup(&pdev->dev)) { | |
176 | u16 port_wake; | |
177 | ||
178 | pci_read_config_word(pdev, 0x62, &port_wake); | |
179 | if (port_wake & 0x0001) | |
180 | device_init_wakeup(&pdev->dev, 1); | |
181 | } | |
7ff71d6a | 182 | |
f8aeb3bb DB |
183 | #ifdef CONFIG_USB_SUSPEND |
184 | /* REVISIT: the controller works fine for wakeup iff the root hub | |
185 | * itself is "globally" suspended, but usbcore currently doesn't | |
186 | * understand such things. | |
187 | * | |
188 | * System suspend currently expects to be able to suspend the entire | |
189 | * device tree, device-at-a-time. If we failed selective suspend | |
190 | * reports, system suspend would fail; so the root hub code must claim | |
191 | * success. That's lying to usbcore, and it matters for for runtime | |
192 | * PM scenarios with selective suspend and remote wakeup... | |
193 | */ | |
194 | if (ehci->no_selective_suspend && device_can_wakeup(&pdev->dev)) | |
195 | ehci_warn(ehci, "selective suspend/wakeup unavailable\n"); | |
196 | #endif | |
197 | ||
18807521 | 198 | retval = ehci_pci_reinit(ehci, pdev); |
8926bfa7 DB |
199 | done: |
200 | return retval; | |
7ff71d6a MP |
201 | } |
202 | ||
203 | /*-------------------------------------------------------------------------*/ | |
204 | ||
205 | #ifdef CONFIG_PM | |
206 | ||
207 | /* suspend/resume, section 4.3 */ | |
208 | ||
f03c17fc | 209 | /* These routines rely on the PCI bus glue |
7ff71d6a MP |
210 | * to handle powerdown and wakeup, and currently also on |
211 | * transceivers that don't need any software attention to set up | |
212 | * the right sort of wakeup. | |
f03c17fc | 213 | * Also they depend on separate root hub suspend/resume. |
7ff71d6a MP |
214 | */ |
215 | ||
abcc9448 | 216 | static int ehci_pci_suspend(struct usb_hcd *hcd, pm_message_t message) |
7ff71d6a | 217 | { |
abcc9448 | 218 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); |
8de98402 BH |
219 | unsigned long flags; |
220 | int rc = 0; | |
7ff71d6a | 221 | |
abcc9448 DB |
222 | if (time_before(jiffies, ehci->next_statechange)) |
223 | msleep(10); | |
7ff71d6a | 224 | |
8de98402 BH |
225 | /* Root hub was already suspended. Disable irq emission and |
226 | * mark HW unaccessible, bail out if RH has been resumed. Use | |
227 | * the spinlock to properly synchronize with possible pending | |
228 | * RH suspend or resume activity. | |
229 | * | |
230 | * This is still racy as hcd->state is manipulated outside of | |
231 | * any locks =P But that will be a different fix. | |
232 | */ | |
233 | spin_lock_irqsave (&ehci->lock, flags); | |
234 | if (hcd->state != HC_STATE_SUSPENDED) { | |
235 | rc = -EINVAL; | |
236 | goto bail; | |
237 | } | |
238 | writel (0, &ehci->regs->intr_enable); | |
239 | (void)readl(&ehci->regs->intr_enable); | |
240 | ||
18584999 DB |
241 | /* make sure snapshot being resumed re-enumerates everything */ |
242 | if (message.event == PM_EVENT_PRETHAW) { | |
243 | ehci_halt(ehci); | |
244 | ehci_reset(ehci); | |
245 | } | |
246 | ||
8de98402 BH |
247 | clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); |
248 | bail: | |
249 | spin_unlock_irqrestore (&ehci->lock, flags); | |
250 | ||
f03c17fc | 251 | // could save FLADJ in case of Vaux power loss |
7ff71d6a MP |
252 | // ... we'd only use it to handle clock skew |
253 | ||
8de98402 | 254 | return rc; |
7ff71d6a MP |
255 | } |
256 | ||
abcc9448 | 257 | static int ehci_pci_resume(struct usb_hcd *hcd) |
7ff71d6a | 258 | { |
abcc9448 | 259 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); |
7ff71d6a | 260 | unsigned port; |
18807521 | 261 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); |
7ff71d6a MP |
262 | int retval = -EINVAL; |
263 | ||
f03c17fc | 264 | // maybe restore FLADJ |
7ff71d6a | 265 | |
abcc9448 DB |
266 | if (time_before(jiffies, ehci->next_statechange)) |
267 | msleep(100); | |
7ff71d6a | 268 | |
8de98402 BH |
269 | /* Mark hardware accessible again as we are out of D3 state by now */ |
270 | set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); | |
271 | ||
f03c17fc | 272 | /* If CF is clear, we lost PCI Vaux power and need to restart. */ |
18807521 | 273 | if (readl(&ehci->regs->configured_flag) != FLAG_CF) |
f03c17fc DB |
274 | goto restart; |
275 | ||
7ff71d6a MP |
276 | /* If any port is suspended (or owned by the companion), |
277 | * we know we can/must resume the HC (and mustn't reset it). | |
f03c17fc | 278 | * We just defer that to the root hub code. |
7ff71d6a | 279 | */ |
abcc9448 | 280 | for (port = HCS_N_PORTS(ehci->hcs_params); port > 0; ) { |
7ff71d6a MP |
281 | u32 status; |
282 | port--; | |
abcc9448 | 283 | status = readl(&ehci->regs->port_status [port]); |
7ff71d6a MP |
284 | if (!(status & PORT_POWER)) |
285 | continue; | |
f03c17fc DB |
286 | if (status & (PORT_SUSPEND | PORT_RESUME | PORT_OWNER)) { |
287 | usb_hcd_resume_root_hub(hcd); | |
288 | return 0; | |
7ff71d6a | 289 | } |
f03c17fc DB |
290 | } |
291 | ||
292 | restart: | |
293 | ehci_dbg(ehci, "lost power, restarting\n"); | |
1c50c317 | 294 | usb_root_hub_lost_power(hcd->self.root_hub); |
7ff71d6a MP |
295 | |
296 | /* Else reset, to cope with power loss or flush-to-storage | |
f03c17fc | 297 | * style "resume" having let BIOS kick in during reboot. |
7ff71d6a | 298 | */ |
abcc9448 DB |
299 | (void) ehci_halt(ehci); |
300 | (void) ehci_reset(ehci); | |
18807521 | 301 | (void) ehci_pci_reinit(ehci, pdev); |
f03c17fc DB |
302 | |
303 | /* emptying the schedule aborts any urbs */ | |
abcc9448 | 304 | spin_lock_irq(&ehci->lock); |
f03c17fc | 305 | if (ehci->reclaim) |
7d12e780 DH |
306 | end_unlink_async (ehci); |
307 | ehci_work(ehci); | |
abcc9448 | 308 | spin_unlock_irq(&ehci->lock); |
f03c17fc DB |
309 | |
310 | /* restart; khubd will disconnect devices */ | |
abcc9448 | 311 | retval = ehci_run(hcd); |
f03c17fc | 312 | |
18807521 | 313 | /* here we "know" root ports should always stay powered */ |
abcc9448 | 314 | ehci_port_power(ehci, 1); |
7ff71d6a MP |
315 | |
316 | return retval; | |
317 | } | |
318 | #endif | |
319 | ||
320 | static const struct hc_driver ehci_pci_hc_driver = { | |
321 | .description = hcd_name, | |
322 | .product_desc = "EHCI Host Controller", | |
323 | .hcd_priv_size = sizeof(struct ehci_hcd), | |
324 | ||
325 | /* | |
326 | * generic hardware linkage | |
327 | */ | |
328 | .irq = ehci_irq, | |
329 | .flags = HCD_MEMORY | HCD_USB2, | |
330 | ||
331 | /* | |
332 | * basic lifecycle operations | |
333 | */ | |
8926bfa7 | 334 | .reset = ehci_pci_setup, |
18807521 | 335 | .start = ehci_run, |
7ff71d6a MP |
336 | #ifdef CONFIG_PM |
337 | .suspend = ehci_pci_suspend, | |
338 | .resume = ehci_pci_resume, | |
339 | #endif | |
18807521 | 340 | .stop = ehci_stop, |
64a21d02 | 341 | .shutdown = ehci_shutdown, |
7ff71d6a MP |
342 | |
343 | /* | |
344 | * managing i/o requests and associated device resources | |
345 | */ | |
346 | .urb_enqueue = ehci_urb_enqueue, | |
347 | .urb_dequeue = ehci_urb_dequeue, | |
348 | .endpoint_disable = ehci_endpoint_disable, | |
349 | ||
350 | /* | |
351 | * scheduling support | |
352 | */ | |
353 | .get_frame_number = ehci_get_frame, | |
354 | ||
355 | /* | |
356 | * root hub support | |
357 | */ | |
358 | .hub_status_data = ehci_hub_status_data, | |
359 | .hub_control = ehci_hub_control, | |
0c0382e3 AS |
360 | .bus_suspend = ehci_bus_suspend, |
361 | .bus_resume = ehci_bus_resume, | |
7ff71d6a MP |
362 | }; |
363 | ||
364 | /*-------------------------------------------------------------------------*/ | |
365 | ||
366 | /* PCI driver selection metadata; PCI hotplugging uses this */ | |
367 | static const struct pci_device_id pci_ids [] = { { | |
368 | /* handle any USB 2.0 EHCI controller */ | |
c67808ee | 369 | PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_EHCI, ~0), |
7ff71d6a MP |
370 | .driver_data = (unsigned long) &ehci_pci_hc_driver, |
371 | }, | |
372 | { /* end: all zeroes */ } | |
373 | }; | |
abcc9448 | 374 | MODULE_DEVICE_TABLE(pci, pci_ids); |
7ff71d6a MP |
375 | |
376 | /* pci driver glue; this is a "new style" PCI driver module */ | |
377 | static struct pci_driver ehci_pci_driver = { | |
378 | .name = (char *) hcd_name, | |
379 | .id_table = pci_ids, | |
380 | ||
381 | .probe = usb_hcd_pci_probe, | |
382 | .remove = usb_hcd_pci_remove, | |
383 | ||
384 | #ifdef CONFIG_PM | |
385 | .suspend = usb_hcd_pci_suspend, | |
386 | .resume = usb_hcd_pci_resume, | |
387 | #endif | |
64a21d02 | 388 | .shutdown = usb_hcd_pci_shutdown, |
7ff71d6a | 389 | }; |