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Commit | Line | Data |
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7ff71d6a MP |
1 | /* |
2 | * EHCI HCD (Host Controller Driver) PCI Bus Glue. | |
3 | * | |
4 | * Copyright (c) 2000-2004 by David Brownell | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License as published by the | |
8 | * Free Software Foundation; either version 2 of the License, or (at your | |
9 | * option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but | |
12 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
13 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
14 | * for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software Foundation, | |
18 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
19 | */ | |
20 | ||
21 | #ifndef CONFIG_PCI | |
22 | #error "This file is PCI bus glue. CONFIG_PCI must be defined." | |
23 | #endif | |
24 | ||
25 | /*-------------------------------------------------------------------------*/ | |
26 | ||
18807521 DB |
27 | /* called after powerup, by probe or system-pm "wakeup" */ |
28 | static int ehci_pci_reinit(struct ehci_hcd *ehci, struct pci_dev *pdev) | |
29 | { | |
30 | u32 temp; | |
31 | int retval; | |
18807521 DB |
32 | |
33 | /* optional debug port, normally in the first BAR */ | |
34 | temp = pci_find_capability(pdev, 0x0a); | |
35 | if (temp) { | |
36 | pci_read_config_dword(pdev, temp, &temp); | |
37 | temp >>= 16; | |
38 | if ((temp & (3 << 13)) == (1 << 13)) { | |
39 | temp &= 0x1fff; | |
40 | ehci->debug = ehci_to_hcd(ehci)->regs + temp; | |
083522d7 | 41 | temp = ehci_readl(ehci, &ehci->debug->control); |
18807521 DB |
42 | ehci_info(ehci, "debug port %d%s\n", |
43 | HCS_DEBUG_PORT(ehci->hcs_params), | |
44 | (temp & DBGP_ENABLED) | |
45 | ? " IN USE" | |
46 | : ""); | |
47 | if (!(temp & DBGP_ENABLED)) | |
48 | ehci->debug = NULL; | |
49 | } | |
50 | } | |
51 | ||
401feafa DB |
52 | /* we expect static quirk code to handle the "extended capabilities" |
53 | * (currently just BIOS handoff) allowed starting with EHCI 0.96 | |
54 | */ | |
18807521 DB |
55 | |
56 | /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ | |
57 | retval = pci_set_mwi(pdev); | |
58 | if (!retval) | |
59 | ehci_dbg(ehci, "MWI active\n"); | |
60 | ||
18807521 DB |
61 | return 0; |
62 | } | |
63 | ||
8926bfa7 DB |
64 | /* called during probe() after chip reset completes */ |
65 | static int ehci_pci_setup(struct usb_hcd *hcd) | |
7ff71d6a | 66 | { |
abcc9448 DB |
67 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); |
68 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); | |
b09bc6cb AX |
69 | struct pci_dev *p_smbus; |
70 | u8 rev; | |
7ff71d6a | 71 | u32 temp; |
18807521 | 72 | int retval; |
7ff71d6a | 73 | |
083522d7 BH |
74 | switch (pdev->vendor) { |
75 | case PCI_VENDOR_ID_TOSHIBA_2: | |
76 | /* celleb's companion chip */ | |
77 | if (pdev->device == 0x01b5) { | |
78 | #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO | |
79 | ehci->big_endian_mmio = 1; | |
80 | #else | |
81 | ehci_warn(ehci, | |
82 | "unsupported big endian Toshiba quirk\n"); | |
83 | #endif | |
84 | } | |
85 | break; | |
86 | } | |
87 | ||
7ff71d6a | 88 | ehci->caps = hcd->regs; |
083522d7 BH |
89 | ehci->regs = hcd->regs + |
90 | HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase)); | |
91 | ||
abcc9448 DB |
92 | dbg_hcs_params(ehci, "reset"); |
93 | dbg_hcc_params(ehci, "reset"); | |
7ff71d6a | 94 | |
c32ba30f PS |
95 | /* ehci_init() causes memory for DMA transfers to be |
96 | * allocated. Thus, any vendor-specific workarounds based on | |
97 | * limiting the type of memory used for DMA transfers must | |
98 | * happen before ehci_init() is called. */ | |
99 | switch (pdev->vendor) { | |
100 | case PCI_VENDOR_ID_NVIDIA: | |
101 | /* NVidia reports that certain chips don't handle | |
102 | * QH, ITD, or SITD addresses above 2GB. (But TD, | |
103 | * data buffer, and periodic schedule are normal.) | |
104 | */ | |
105 | switch (pdev->device) { | |
106 | case 0x003c: /* MCP04 */ | |
107 | case 0x005b: /* CK804 */ | |
108 | case 0x00d8: /* CK8 */ | |
109 | case 0x00e8: /* CK8S */ | |
110 | if (pci_set_consistent_dma_mask(pdev, | |
929a22a5 | 111 | DMA_BIT_MASK(31)) < 0) |
c32ba30f PS |
112 | ehci_warn(ehci, "can't enable NVidia " |
113 | "workaround for >2GB RAM\n"); | |
114 | break; | |
115 | } | |
116 | break; | |
117 | } | |
118 | ||
7ff71d6a | 119 | /* cache this readonly data; minimize chip reads */ |
083522d7 | 120 | ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); |
7ff71d6a | 121 | |
18807521 DB |
122 | retval = ehci_halt(ehci); |
123 | if (retval) | |
124 | return retval; | |
125 | ||
8926bfa7 DB |
126 | /* data structure init */ |
127 | retval = ehci_init(hcd); | |
128 | if (retval) | |
129 | return retval; | |
130 | ||
abcc9448 DB |
131 | switch (pdev->vendor) { |
132 | case PCI_VENDOR_ID_TDI: | |
133 | if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) { | |
7329e211 | 134 | hcd->has_tt = 1; |
abcc9448 DB |
135 | tdi_reset(ehci); |
136 | } | |
137 | break; | |
138 | case PCI_VENDOR_ID_AMD: | |
139 | /* AMD8111 EHCI doesn't work, according to AMD errata */ | |
140 | if (pdev->device == 0x7463) { | |
141 | ehci_info(ehci, "ignoring AMD8111 (errata)\n"); | |
8926bfa7 DB |
142 | retval = -EIO; |
143 | goto done; | |
abcc9448 DB |
144 | } |
145 | break; | |
146 | case PCI_VENDOR_ID_NVIDIA: | |
f8aeb3bb | 147 | switch (pdev->device) { |
f8aeb3bb DB |
148 | /* Some NForce2 chips have problems with selective suspend; |
149 | * fixed in newer silicon. | |
150 | */ | |
151 | case 0x0068: | |
44c10138 | 152 | if (pdev->revision < 0xa4) |
f8aeb3bb DB |
153 | ehci->no_selective_suspend = 1; |
154 | break; | |
7ff71d6a | 155 | } |
abcc9448 | 156 | break; |
055b93c9 RH |
157 | case PCI_VENDOR_ID_VIA: |
158 | if (pdev->device == 0x3104 && (pdev->revision & 0xf0) == 0x60) { | |
159 | u8 tmp; | |
160 | ||
161 | /* The VT6212 defaults to a 1 usec EHCI sleep time which | |
162 | * hogs the PCI bus *badly*. Setting bit 5 of 0x4B makes | |
163 | * that sleep time use the conventional 10 usec. | |
164 | */ | |
165 | pci_read_config_byte(pdev, 0x4b, &tmp); | |
166 | if (tmp & 0x20) | |
167 | break; | |
168 | pci_write_config_byte(pdev, 0x4b, tmp | 0x20); | |
169 | } | |
170 | break; | |
b09bc6cb | 171 | case PCI_VENDOR_ID_ATI: |
0a99e8ac | 172 | /* SB600 and old version of SB700 have a bug in EHCI controller, |
b09bc6cb AX |
173 | * which causes usb devices lose response in some cases. |
174 | */ | |
0a99e8ac | 175 | if ((pdev->device == 0x4386) || (pdev->device == 0x4396)) { |
b09bc6cb AX |
176 | p_smbus = pci_get_device(PCI_VENDOR_ID_ATI, |
177 | PCI_DEVICE_ID_ATI_SBX00_SMBUS, | |
178 | NULL); | |
179 | if (!p_smbus) | |
180 | break; | |
181 | rev = p_smbus->revision; | |
0a99e8ac SH |
182 | if ((pdev->device == 0x4386) || (rev == 0x3a) |
183 | || (rev == 0x3b)) { | |
b09bc6cb | 184 | u8 tmp; |
0a99e8ac SH |
185 | ehci_info(ehci, "applying AMD SB600/SB700 USB " |
186 | "freeze workaround\n"); | |
b09bc6cb AX |
187 | pci_read_config_byte(pdev, 0x53, &tmp); |
188 | pci_write_config_byte(pdev, 0x53, tmp | (1<<3)); | |
189 | } | |
190 | pci_dev_put(p_smbus); | |
191 | } | |
192 | break; | |
abcc9448 | 193 | } |
7ff71d6a | 194 | |
af1c51fc | 195 | ehci_reset(ehci); |
7ff71d6a | 196 | |
7ff71d6a MP |
197 | /* at least the Genesys GL880S needs fixup here */ |
198 | temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params); | |
199 | temp &= 0x0f; | |
200 | if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) { | |
abcc9448 | 201 | ehci_dbg(ehci, "bogus port configuration: " |
7ff71d6a MP |
202 | "cc=%d x pcc=%d < ports=%d\n", |
203 | HCS_N_CC(ehci->hcs_params), | |
204 | HCS_N_PCC(ehci->hcs_params), | |
205 | HCS_N_PORTS(ehci->hcs_params)); | |
206 | ||
abcc9448 DB |
207 | switch (pdev->vendor) { |
208 | case 0x17a0: /* GENESYS */ | |
209 | /* GL880S: should be PORTS=2 */ | |
210 | temp |= (ehci->hcs_params & ~0xf); | |
211 | ehci->hcs_params = temp; | |
212 | break; | |
213 | case PCI_VENDOR_ID_NVIDIA: | |
214 | /* NF4: should be PCC=10 */ | |
215 | break; | |
7ff71d6a MP |
216 | } |
217 | } | |
218 | ||
abcc9448 DB |
219 | /* Serial Bus Release Number is at PCI 0x60 offset */ |
220 | pci_read_config_byte(pdev, 0x60, &ehci->sbrn); | |
7ff71d6a | 221 | |
6fd9086a AS |
222 | /* Keep this around for a while just in case some EHCI |
223 | * implementation uses legacy PCI PM support. This test | |
224 | * can be removed on 17 Dec 2009 if the dev_warn() hasn't | |
225 | * been triggered by then. | |
2c1c3c4c DB |
226 | */ |
227 | if (!device_can_wakeup(&pdev->dev)) { | |
228 | u16 port_wake; | |
229 | ||
230 | pci_read_config_word(pdev, 0x62, &port_wake); | |
6fd9086a AS |
231 | if (port_wake & 0x0001) { |
232 | dev_warn(&pdev->dev, "Enabling legacy PCI PM\n"); | |
bcca06ef | 233 | device_set_wakeup_capable(&pdev->dev, 1); |
6fd9086a | 234 | } |
2c1c3c4c | 235 | } |
7ff71d6a | 236 | |
f8aeb3bb DB |
237 | #ifdef CONFIG_USB_SUSPEND |
238 | /* REVISIT: the controller works fine for wakeup iff the root hub | |
239 | * itself is "globally" suspended, but usbcore currently doesn't | |
240 | * understand such things. | |
241 | * | |
242 | * System suspend currently expects to be able to suspend the entire | |
243 | * device tree, device-at-a-time. If we failed selective suspend | |
244 | * reports, system suspend would fail; so the root hub code must claim | |
245 | * success. That's lying to usbcore, and it matters for for runtime | |
246 | * PM scenarios with selective suspend and remote wakeup... | |
247 | */ | |
248 | if (ehci->no_selective_suspend && device_can_wakeup(&pdev->dev)) | |
249 | ehci_warn(ehci, "selective suspend/wakeup unavailable\n"); | |
250 | #endif | |
251 | ||
aff6d18f | 252 | ehci_port_power(ehci, 1); |
18807521 | 253 | retval = ehci_pci_reinit(ehci, pdev); |
8926bfa7 DB |
254 | done: |
255 | return retval; | |
7ff71d6a MP |
256 | } |
257 | ||
258 | /*-------------------------------------------------------------------------*/ | |
259 | ||
260 | #ifdef CONFIG_PM | |
261 | ||
262 | /* suspend/resume, section 4.3 */ | |
263 | ||
f03c17fc | 264 | /* These routines rely on the PCI bus glue |
7ff71d6a MP |
265 | * to handle powerdown and wakeup, and currently also on |
266 | * transceivers that don't need any software attention to set up | |
267 | * the right sort of wakeup. | |
f03c17fc | 268 | * Also they depend on separate root hub suspend/resume. |
7ff71d6a MP |
269 | */ |
270 | ||
6ec4beb5 | 271 | static int ehci_pci_suspend(struct usb_hcd *hcd) |
7ff71d6a | 272 | { |
abcc9448 | 273 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); |
8de98402 BH |
274 | unsigned long flags; |
275 | int rc = 0; | |
7ff71d6a | 276 | |
abcc9448 DB |
277 | if (time_before(jiffies, ehci->next_statechange)) |
278 | msleep(10); | |
7ff71d6a | 279 | |
8de98402 BH |
280 | /* Root hub was already suspended. Disable irq emission and |
281 | * mark HW unaccessible, bail out if RH has been resumed. Use | |
282 | * the spinlock to properly synchronize with possible pending | |
283 | * RH suspend or resume activity. | |
284 | * | |
285 | * This is still racy as hcd->state is manipulated outside of | |
286 | * any locks =P But that will be a different fix. | |
287 | */ | |
288 | spin_lock_irqsave (&ehci->lock, flags); | |
289 | if (hcd->state != HC_STATE_SUSPENDED) { | |
290 | rc = -EINVAL; | |
291 | goto bail; | |
292 | } | |
083522d7 BH |
293 | ehci_writel(ehci, 0, &ehci->regs->intr_enable); |
294 | (void)ehci_readl(ehci, &ehci->regs->intr_enable); | |
8de98402 BH |
295 | |
296 | clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); | |
297 | bail: | |
298 | spin_unlock_irqrestore (&ehci->lock, flags); | |
299 | ||
f03c17fc | 300 | // could save FLADJ in case of Vaux power loss |
7ff71d6a MP |
301 | // ... we'd only use it to handle clock skew |
302 | ||
8de98402 | 303 | return rc; |
7ff71d6a MP |
304 | } |
305 | ||
6ec4beb5 | 306 | static int ehci_pci_resume(struct usb_hcd *hcd, bool hibernated) |
7ff71d6a | 307 | { |
abcc9448 | 308 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); |
18807521 | 309 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); |
7ff71d6a | 310 | |
f03c17fc | 311 | // maybe restore FLADJ |
7ff71d6a | 312 | |
abcc9448 DB |
313 | if (time_before(jiffies, ehci->next_statechange)) |
314 | msleep(100); | |
7ff71d6a | 315 | |
8de98402 BH |
316 | /* Mark hardware accessible again as we are out of D3 state by now */ |
317 | set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); | |
318 | ||
6ec4beb5 AS |
319 | /* If CF is still set and we aren't resuming from hibernation |
320 | * then we maintained PCI Vaux power. | |
8c03356a | 321 | * Just undo the effect of ehci_pci_suspend(). |
7ff71d6a | 322 | */ |
6ec4beb5 AS |
323 | if (ehci_readl(ehci, &ehci->regs->configured_flag) == FLAG_CF && |
324 | !hibernated) { | |
8c03356a AS |
325 | int mask = INTR_MASK; |
326 | ||
58a97ffe | 327 | if (!hcd->self.root_hub->do_remote_wakeup) |
8c03356a | 328 | mask &= ~STS_PCD; |
083522d7 BH |
329 | ehci_writel(ehci, mask, &ehci->regs->intr_enable); |
330 | ehci_readl(ehci, &ehci->regs->intr_enable); | |
8c03356a | 331 | return 0; |
f03c17fc DB |
332 | } |
333 | ||
1c50c317 | 334 | usb_root_hub_lost_power(hcd->self.root_hub); |
7ff71d6a MP |
335 | |
336 | /* Else reset, to cope with power loss or flush-to-storage | |
f03c17fc | 337 | * style "resume" having let BIOS kick in during reboot. |
7ff71d6a | 338 | */ |
abcc9448 DB |
339 | (void) ehci_halt(ehci); |
340 | (void) ehci_reset(ehci); | |
18807521 | 341 | (void) ehci_pci_reinit(ehci, pdev); |
f03c17fc DB |
342 | |
343 | /* emptying the schedule aborts any urbs */ | |
abcc9448 | 344 | spin_lock_irq(&ehci->lock); |
f03c17fc | 345 | if (ehci->reclaim) |
07d29b63 | 346 | end_unlink_async(ehci); |
7d12e780 | 347 | ehci_work(ehci); |
abcc9448 | 348 | spin_unlock_irq(&ehci->lock); |
f03c17fc | 349 | |
083522d7 BH |
350 | ehci_writel(ehci, ehci->command, &ehci->regs->command); |
351 | ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag); | |
352 | ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */ | |
8c03356a | 353 | |
383975d7 AS |
354 | /* here we "know" root ports should always stay powered */ |
355 | ehci_port_power(ehci, 1); | |
383975d7 | 356 | |
8c03356a AS |
357 | hcd->state = HC_STATE_SUSPENDED; |
358 | return 0; | |
7ff71d6a MP |
359 | } |
360 | #endif | |
361 | ||
362 | static const struct hc_driver ehci_pci_hc_driver = { | |
363 | .description = hcd_name, | |
364 | .product_desc = "EHCI Host Controller", | |
365 | .hcd_priv_size = sizeof(struct ehci_hcd), | |
366 | ||
367 | /* | |
368 | * generic hardware linkage | |
369 | */ | |
370 | .irq = ehci_irq, | |
371 | .flags = HCD_MEMORY | HCD_USB2, | |
372 | ||
373 | /* | |
374 | * basic lifecycle operations | |
375 | */ | |
8926bfa7 | 376 | .reset = ehci_pci_setup, |
18807521 | 377 | .start = ehci_run, |
7ff71d6a | 378 | #ifdef CONFIG_PM |
7be7d741 AS |
379 | .pci_suspend = ehci_pci_suspend, |
380 | .pci_resume = ehci_pci_resume, | |
7ff71d6a | 381 | #endif |
18807521 | 382 | .stop = ehci_stop, |
64a21d02 | 383 | .shutdown = ehci_shutdown, |
7ff71d6a MP |
384 | |
385 | /* | |
386 | * managing i/o requests and associated device resources | |
387 | */ | |
388 | .urb_enqueue = ehci_urb_enqueue, | |
389 | .urb_dequeue = ehci_urb_dequeue, | |
390 | .endpoint_disable = ehci_endpoint_disable, | |
b18ffd49 | 391 | .endpoint_reset = ehci_endpoint_reset, |
7ff71d6a MP |
392 | |
393 | /* | |
394 | * scheduling support | |
395 | */ | |
396 | .get_frame_number = ehci_get_frame, | |
397 | ||
398 | /* | |
399 | * root hub support | |
400 | */ | |
401 | .hub_status_data = ehci_hub_status_data, | |
402 | .hub_control = ehci_hub_control, | |
0c0382e3 AS |
403 | .bus_suspend = ehci_bus_suspend, |
404 | .bus_resume = ehci_bus_resume, | |
a8e51775 | 405 | .relinquish_port = ehci_relinquish_port, |
3a31155c | 406 | .port_handed_over = ehci_port_handed_over, |
914b7012 AS |
407 | |
408 | .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, | |
7ff71d6a MP |
409 | }; |
410 | ||
411 | /*-------------------------------------------------------------------------*/ | |
412 | ||
413 | /* PCI driver selection metadata; PCI hotplugging uses this */ | |
414 | static const struct pci_device_id pci_ids [] = { { | |
415 | /* handle any USB 2.0 EHCI controller */ | |
c67808ee | 416 | PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_EHCI, ~0), |
7ff71d6a MP |
417 | .driver_data = (unsigned long) &ehci_pci_hc_driver, |
418 | }, | |
419 | { /* end: all zeroes */ } | |
420 | }; | |
abcc9448 | 421 | MODULE_DEVICE_TABLE(pci, pci_ids); |
7ff71d6a MP |
422 | |
423 | /* pci driver glue; this is a "new style" PCI driver module */ | |
424 | static struct pci_driver ehci_pci_driver = { | |
425 | .name = (char *) hcd_name, | |
426 | .id_table = pci_ids, | |
427 | ||
428 | .probe = usb_hcd_pci_probe, | |
429 | .remove = usb_hcd_pci_remove, | |
abb30641 | 430 | .shutdown = usb_hcd_pci_shutdown, |
7ff71d6a | 431 | |
abb30641 AS |
432 | #ifdef CONFIG_PM_SLEEP |
433 | .driver = { | |
434 | .pm = &usb_hcd_pci_pm_ops | |
435 | }, | |
7ff71d6a MP |
436 | #endif |
437 | }; |