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Commit | Line | Data |
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7ff71d6a MP |
1 | /* |
2 | * EHCI HCD (Host Controller Driver) PCI Bus Glue. | |
3 | * | |
4 | * Copyright (c) 2000-2004 by David Brownell | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License as published by the | |
8 | * Free Software Foundation; either version 2 of the License, or (at your | |
9 | * option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but | |
12 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
13 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
14 | * for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software Foundation, | |
18 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
19 | */ | |
20 | ||
adfa79d1 AS |
21 | #include <linux/kernel.h> |
22 | #include <linux/module.h> | |
23 | #include <linux/pci.h> | |
24 | #include <linux/usb.h> | |
25 | #include <linux/usb/hcd.h> | |
26 | ||
27 | #include "ehci.h" | |
28 | #include "pci-quirks.h" | |
29 | ||
30 | #define DRIVER_DESC "EHCI PCI platform driver" | |
31 | ||
32 | static const char hcd_name[] = "ehci-pci"; | |
7ff71d6a | 33 | |
4f683843 DB |
34 | /* defined here to avoid adding to pci_ids.h for single instance use */ |
35 | #define PCI_DEVICE_ID_INTEL_CE4100_USB 0x2e70 | |
36 | ||
7ff71d6a MP |
37 | /*-------------------------------------------------------------------------*/ |
38 | ||
18807521 DB |
39 | /* called after powerup, by probe or system-pm "wakeup" */ |
40 | static int ehci_pci_reinit(struct ehci_hcd *ehci, struct pci_dev *pdev) | |
41 | { | |
18807521 | 42 | int retval; |
18807521 | 43 | |
401feafa DB |
44 | /* we expect static quirk code to handle the "extended capabilities" |
45 | * (currently just BIOS handoff) allowed starting with EHCI 0.96 | |
46 | */ | |
18807521 DB |
47 | |
48 | /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ | |
49 | retval = pci_set_mwi(pdev); | |
50 | if (!retval) | |
51 | ehci_dbg(ehci, "MWI active\n"); | |
52 | ||
18807521 DB |
53 | return 0; |
54 | } | |
55 | ||
8926bfa7 DB |
56 | /* called during probe() after chip reset completes */ |
57 | static int ehci_pci_setup(struct usb_hcd *hcd) | |
7ff71d6a | 58 | { |
abcc9448 DB |
59 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); |
60 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); | |
b09bc6cb AX |
61 | struct pci_dev *p_smbus; |
62 | u8 rev; | |
7ff71d6a | 63 | u32 temp; |
18807521 | 64 | int retval; |
7ff71d6a | 65 | |
1a49e2ac AS |
66 | ehci->caps = hcd->regs; |
67 | ||
68 | /* | |
69 | * ehci_init() causes memory for DMA transfers to be | |
70 | * allocated. Thus, any vendor-specific workarounds based on | |
71 | * limiting the type of memory used for DMA transfers must | |
72 | * happen before ehci_setup() is called. | |
73 | * | |
74 | * Most other workarounds can be done either before or after | |
75 | * init and reset; they are located here too. | |
76 | */ | |
083522d7 BH |
77 | switch (pdev->vendor) { |
78 | case PCI_VENDOR_ID_TOSHIBA_2: | |
79 | /* celleb's companion chip */ | |
80 | if (pdev->device == 0x01b5) { | |
81 | #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO | |
82 | ehci->big_endian_mmio = 1; | |
83 | #else | |
84 | ehci_warn(ehci, | |
85 | "unsupported big endian Toshiba quirk\n"); | |
86 | #endif | |
87 | } | |
88 | break; | |
c32ba30f PS |
89 | case PCI_VENDOR_ID_NVIDIA: |
90 | /* NVidia reports that certain chips don't handle | |
91 | * QH, ITD, or SITD addresses above 2GB. (But TD, | |
92 | * data buffer, and periodic schedule are normal.) | |
93 | */ | |
94 | switch (pdev->device) { | |
95 | case 0x003c: /* MCP04 */ | |
96 | case 0x005b: /* CK804 */ | |
97 | case 0x00d8: /* CK8 */ | |
98 | case 0x00e8: /* CK8S */ | |
99 | if (pci_set_consistent_dma_mask(pdev, | |
929a22a5 | 100 | DMA_BIT_MASK(31)) < 0) |
c32ba30f PS |
101 | ehci_warn(ehci, "can't enable NVidia " |
102 | "workaround for >2GB RAM\n"); | |
103 | break; | |
7ff71d6a | 104 | |
1a49e2ac AS |
105 | /* Some NForce2 chips have problems with selective suspend; |
106 | * fixed in newer silicon. | |
3d091a6f | 107 | */ |
1a49e2ac AS |
108 | case 0x0068: |
109 | if (pdev->revision < 0xa4) | |
110 | ehci->no_selective_suspend = 1; | |
111 | break; | |
112 | } | |
3681d8f3 | 113 | break; |
403dbd36 | 114 | case PCI_VENDOR_ID_INTEL: |
1a49e2ac | 115 | if (pdev->device == PCI_DEVICE_ID_INTEL_CE4100_USB) |
4f683843 | 116 | hcd->has_tt = 1; |
403dbd36 | 117 | break; |
abcc9448 | 118 | case PCI_VENDOR_ID_TDI: |
1a49e2ac | 119 | if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) |
7329e211 | 120 | hcd->has_tt = 1; |
abcc9448 DB |
121 | break; |
122 | case PCI_VENDOR_ID_AMD: | |
ad93562b AX |
123 | /* AMD PLL quirk */ |
124 | if (usb_amd_find_chipset_info()) | |
125 | ehci->amd_pll_fix = 1; | |
abcc9448 DB |
126 | /* AMD8111 EHCI doesn't work, according to AMD errata */ |
127 | if (pdev->device == 0x7463) { | |
128 | ehci_info(ehci, "ignoring AMD8111 (errata)\n"); | |
8926bfa7 DB |
129 | retval = -EIO; |
130 | goto done; | |
abcc9448 | 131 | } |
a85b4e7f | 132 | |
1a49e2ac AS |
133 | /* |
134 | * EHCI controller on AMD SB700/SB800/Hudson-2/3 platforms may | |
135 | * read/write memory space which does not belong to it when | |
136 | * there is NULL pointer with T-bit set to 1 in the frame list | |
137 | * table. To avoid the issue, the frame list link pointer | |
138 | * should always contain a valid pointer to a inactive qh. | |
a85b4e7f | 139 | */ |
1a49e2ac AS |
140 | if (pdev->device == 0x7808) { |
141 | ehci->use_dummy_qh = 1; | |
142 | ehci_info(ehci, "applying AMD SB700/SB800/Hudson-2/3 EHCI dummy qh workaround\n"); | |
7ff71d6a | 143 | } |
abcc9448 | 144 | break; |
055b93c9 RH |
145 | case PCI_VENDOR_ID_VIA: |
146 | if (pdev->device == 0x3104 && (pdev->revision & 0xf0) == 0x60) { | |
147 | u8 tmp; | |
148 | ||
149 | /* The VT6212 defaults to a 1 usec EHCI sleep time which | |
150 | * hogs the PCI bus *badly*. Setting bit 5 of 0x4B makes | |
151 | * that sleep time use the conventional 10 usec. | |
152 | */ | |
153 | pci_read_config_byte(pdev, 0x4b, &tmp); | |
154 | if (tmp & 0x20) | |
155 | break; | |
156 | pci_write_config_byte(pdev, 0x4b, tmp | 0x20); | |
157 | } | |
158 | break; | |
b09bc6cb | 159 | case PCI_VENDOR_ID_ATI: |
ad93562b AX |
160 | /* AMD PLL quirk */ |
161 | if (usb_amd_find_chipset_info()) | |
162 | ehci->amd_pll_fix = 1; | |
1a49e2ac AS |
163 | |
164 | /* | |
165 | * EHCI controller on AMD SB700/SB800/Hudson-2/3 platforms may | |
166 | * read/write memory space which does not belong to it when | |
167 | * there is NULL pointer with T-bit set to 1 in the frame list | |
168 | * table. To avoid the issue, the frame list link pointer | |
169 | * should always contain a valid pointer to a inactive qh. | |
170 | */ | |
171 | if (pdev->device == 0x4396) { | |
172 | ehci->use_dummy_qh = 1; | |
173 | ehci_info(ehci, "applying AMD SB700/SB800/Hudson-2/3 EHCI dummy qh workaround\n"); | |
174 | } | |
0a99e8ac | 175 | /* SB600 and old version of SB700 have a bug in EHCI controller, |
b09bc6cb AX |
176 | * which causes usb devices lose response in some cases. |
177 | */ | |
0a99e8ac | 178 | if ((pdev->device == 0x4386) || (pdev->device == 0x4396)) { |
b09bc6cb AX |
179 | p_smbus = pci_get_device(PCI_VENDOR_ID_ATI, |
180 | PCI_DEVICE_ID_ATI_SBX00_SMBUS, | |
181 | NULL); | |
182 | if (!p_smbus) | |
183 | break; | |
184 | rev = p_smbus->revision; | |
0a99e8ac SH |
185 | if ((pdev->device == 0x4386) || (rev == 0x3a) |
186 | || (rev == 0x3b)) { | |
b09bc6cb | 187 | u8 tmp; |
0a99e8ac SH |
188 | ehci_info(ehci, "applying AMD SB600/SB700 USB " |
189 | "freeze workaround\n"); | |
b09bc6cb AX |
190 | pci_read_config_byte(pdev, 0x53, &tmp); |
191 | pci_write_config_byte(pdev, 0x53, tmp | (1<<3)); | |
192 | } | |
193 | pci_dev_put(p_smbus); | |
194 | } | |
195 | break; | |
68aa95d5 AS |
196 | case PCI_VENDOR_ID_NETMOS: |
197 | /* MosChip frame-index-register bug */ | |
198 | ehci_info(ehci, "applying MosChip frame-index workaround\n"); | |
199 | ehci->frame_index_bug = 1; | |
200 | break; | |
abcc9448 | 201 | } |
7ff71d6a | 202 | |
1a49e2ac AS |
203 | retval = ehci_setup(hcd); |
204 | if (retval) | |
205 | return retval; | |
206 | ||
207 | /* These workarounds need to be applied after ehci_setup() */ | |
208 | switch (pdev->vendor) { | |
209 | case PCI_VENDOR_ID_NEC: | |
210 | ehci->need_io_watchdog = 0; | |
211 | break; | |
212 | case PCI_VENDOR_ID_INTEL: | |
213 | ehci->need_io_watchdog = 0; | |
1a49e2ac AS |
214 | break; |
215 | case PCI_VENDOR_ID_NVIDIA: | |
216 | switch (pdev->device) { | |
217 | /* MCP89 chips on the MacBookAir3,1 give EPROTO when | |
218 | * fetching device descriptors unless LPM is disabled. | |
219 | * There are also intermittent problems enumerating | |
220 | * devices with PPCD enabled. | |
221 | */ | |
222 | case 0x0d9d: | |
4968f951 | 223 | ehci_info(ehci, "disable ppcd for nvidia mcp89\n"); |
1a49e2ac AS |
224 | ehci->has_ppcd = 0; |
225 | ehci->command &= ~CMD_PPCEE; | |
226 | break; | |
227 | } | |
228 | break; | |
229 | } | |
230 | ||
8d053c79 JW |
231 | /* optional debug port, normally in the first BAR */ |
232 | temp = pci_find_capability(pdev, 0x0a); | |
233 | if (temp) { | |
234 | pci_read_config_dword(pdev, temp, &temp); | |
235 | temp >>= 16; | |
236 | if ((temp & (3 << 13)) == (1 << 13)) { | |
237 | temp &= 0x1fff; | |
1a49e2ac | 238 | ehci->debug = hcd->regs + temp; |
8d053c79 JW |
239 | temp = ehci_readl(ehci, &ehci->debug->control); |
240 | ehci_info(ehci, "debug port %d%s\n", | |
241 | HCS_DEBUG_PORT(ehci->hcs_params), | |
242 | (temp & DBGP_ENABLED) | |
243 | ? " IN USE" | |
244 | : ""); | |
245 | if (!(temp & DBGP_ENABLED)) | |
246 | ehci->debug = NULL; | |
247 | } | |
248 | } | |
249 | ||
7ff71d6a MP |
250 | /* at least the Genesys GL880S needs fixup here */ |
251 | temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params); | |
252 | temp &= 0x0f; | |
253 | if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) { | |
abcc9448 | 254 | ehci_dbg(ehci, "bogus port configuration: " |
7ff71d6a MP |
255 | "cc=%d x pcc=%d < ports=%d\n", |
256 | HCS_N_CC(ehci->hcs_params), | |
257 | HCS_N_PCC(ehci->hcs_params), | |
258 | HCS_N_PORTS(ehci->hcs_params)); | |
259 | ||
abcc9448 DB |
260 | switch (pdev->vendor) { |
261 | case 0x17a0: /* GENESYS */ | |
262 | /* GL880S: should be PORTS=2 */ | |
263 | temp |= (ehci->hcs_params & ~0xf); | |
264 | ehci->hcs_params = temp; | |
265 | break; | |
266 | case PCI_VENDOR_ID_NVIDIA: | |
267 | /* NF4: should be PCC=10 */ | |
268 | break; | |
7ff71d6a MP |
269 | } |
270 | } | |
271 | ||
abcc9448 | 272 | /* Serial Bus Release Number is at PCI 0x60 offset */ |
3a0bac06 AR |
273 | if (pdev->vendor == PCI_VENDOR_ID_STMICRO |
274 | && pdev->device == PCI_DEVICE_ID_STMICRO_USB_HOST) | |
1a49e2ac AS |
275 | ; /* ConneXT has no sbrn register */ |
276 | else | |
277 | pci_read_config_byte(pdev, 0x60, &ehci->sbrn); | |
7ff71d6a | 278 | |
6fd9086a AS |
279 | /* Keep this around for a while just in case some EHCI |
280 | * implementation uses legacy PCI PM support. This test | |
281 | * can be removed on 17 Dec 2009 if the dev_warn() hasn't | |
282 | * been triggered by then. | |
2c1c3c4c DB |
283 | */ |
284 | if (!device_can_wakeup(&pdev->dev)) { | |
285 | u16 port_wake; | |
286 | ||
287 | pci_read_config_word(pdev, 0x62, &port_wake); | |
6fd9086a AS |
288 | if (port_wake & 0x0001) { |
289 | dev_warn(&pdev->dev, "Enabling legacy PCI PM\n"); | |
bcca06ef | 290 | device_set_wakeup_capable(&pdev->dev, 1); |
6fd9086a | 291 | } |
2c1c3c4c | 292 | } |
7ff71d6a | 293 | |
f8aeb3bb DB |
294 | #ifdef CONFIG_USB_SUSPEND |
295 | /* REVISIT: the controller works fine for wakeup iff the root hub | |
296 | * itself is "globally" suspended, but usbcore currently doesn't | |
297 | * understand such things. | |
298 | * | |
299 | * System suspend currently expects to be able to suspend the entire | |
300 | * device tree, device-at-a-time. If we failed selective suspend | |
301 | * reports, system suspend would fail; so the root hub code must claim | |
411c9403 | 302 | * success. That's lying to usbcore, and it matters for runtime |
f8aeb3bb DB |
303 | * PM scenarios with selective suspend and remote wakeup... |
304 | */ | |
305 | if (ehci->no_selective_suspend && device_can_wakeup(&pdev->dev)) | |
306 | ehci_warn(ehci, "selective suspend/wakeup unavailable\n"); | |
307 | #endif | |
308 | ||
18807521 | 309 | retval = ehci_pci_reinit(ehci, pdev); |
8926bfa7 DB |
310 | done: |
311 | return retval; | |
7ff71d6a MP |
312 | } |
313 | ||
314 | /*-------------------------------------------------------------------------*/ | |
315 | ||
316 | #ifdef CONFIG_PM | |
317 | ||
318 | /* suspend/resume, section 4.3 */ | |
319 | ||
f03c17fc | 320 | /* These routines rely on the PCI bus glue |
7ff71d6a MP |
321 | * to handle powerdown and wakeup, and currently also on |
322 | * transceivers that don't need any software attention to set up | |
323 | * the right sort of wakeup. | |
f03c17fc | 324 | * Also they depend on separate root hub suspend/resume. |
7ff71d6a MP |
325 | */ |
326 | ||
69e848c2 SS |
327 | static bool usb_is_intel_switchable_ehci(struct pci_dev *pdev) |
328 | { | |
329 | return pdev->class == PCI_CLASS_SERIAL_USB_EHCI && | |
330 | pdev->vendor == PCI_VENDOR_ID_INTEL && | |
1c12443a SS |
331 | (pdev->device == 0x1E26 || |
332 | pdev->device == 0x8C2D || | |
333 | pdev->device == 0x8C26); | |
69e848c2 SS |
334 | } |
335 | ||
336 | static void ehci_enable_xhci_companion(void) | |
337 | { | |
338 | struct pci_dev *companion = NULL; | |
339 | ||
340 | /* The xHCI and EHCI controllers are not on the same PCI slot */ | |
341 | for_each_pci_dev(companion) { | |
342 | if (!usb_is_intel_switchable_xhci(companion)) | |
343 | continue; | |
344 | usb_enable_xhci_ports(companion); | |
345 | return; | |
346 | } | |
347 | } | |
348 | ||
6ec4beb5 | 349 | static int ehci_pci_resume(struct usb_hcd *hcd, bool hibernated) |
7ff71d6a | 350 | { |
abcc9448 | 351 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); |
18807521 | 352 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); |
7ff71d6a | 353 | |
69e848c2 SS |
354 | /* The BIOS on systems with the Intel Panther Point chipset may or may |
355 | * not support xHCI natively. That means that during system resume, it | |
356 | * may switch the ports back to EHCI so that users can use their | |
357 | * keyboard to select a kernel from GRUB after resume from hibernate. | |
358 | * | |
359 | * The BIOS is supposed to remember whether the OS had xHCI ports | |
360 | * enabled before resume, and switch the ports back to xHCI when the | |
361 | * BIOS/OS semaphore is written, but we all know we can't trust BIOS | |
362 | * writers. | |
363 | * | |
364 | * Unconditionally switch the ports back to xHCI after a system resume. | |
365 | * We can't tell whether the EHCI or xHCI controller will be resumed | |
366 | * first, so we have to do the port switchover in both drivers. Writing | |
367 | * a '1' to the port switchover registers should have no effect if the | |
368 | * port was already switched over. | |
369 | */ | |
370 | if (usb_is_intel_switchable_ehci(pdev)) | |
371 | ehci_enable_xhci_companion(); | |
372 | ||
c5cf9212 AS |
373 | if (ehci_resume(hcd, hibernated) != 0) |
374 | (void) ehci_pci_reinit(ehci, pdev); | |
8c03356a | 375 | return 0; |
7ff71d6a | 376 | } |
7ff71d6a | 377 | |
adfa79d1 | 378 | #else |
7ff71d6a | 379 | |
adfa79d1 AS |
380 | #define ehci_suspend NULL |
381 | #define ehci_pci_resume NULL | |
382 | #endif /* CONFIG_PM */ | |
7ff71d6a | 383 | |
adfa79d1 | 384 | static struct hc_driver __read_mostly ehci_pci_hc_driver; |
7ff71d6a | 385 | |
adfa79d1 AS |
386 | static const struct ehci_driver_overrides overrides = { |
387 | .product_desc = "EHCI PCI host controller", | |
388 | .reset = ehci_pci_setup, | |
7ff71d6a MP |
389 | }; |
390 | ||
391 | /*-------------------------------------------------------------------------*/ | |
392 | ||
393 | /* PCI driver selection metadata; PCI hotplugging uses this */ | |
394 | static const struct pci_device_id pci_ids [] = { { | |
395 | /* handle any USB 2.0 EHCI controller */ | |
c67808ee | 396 | PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_EHCI, ~0), |
7ff71d6a | 397 | .driver_data = (unsigned long) &ehci_pci_hc_driver, |
3a0bac06 AR |
398 | }, { |
399 | PCI_VDEVICE(STMICRO, PCI_DEVICE_ID_STMICRO_USB_HOST), | |
400 | .driver_data = (unsigned long) &ehci_pci_hc_driver, | |
7ff71d6a MP |
401 | }, |
402 | { /* end: all zeroes */ } | |
403 | }; | |
abcc9448 | 404 | MODULE_DEVICE_TABLE(pci, pci_ids); |
7ff71d6a MP |
405 | |
406 | /* pci driver glue; this is a "new style" PCI driver module */ | |
407 | static struct pci_driver ehci_pci_driver = { | |
408 | .name = (char *) hcd_name, | |
409 | .id_table = pci_ids, | |
410 | ||
411 | .probe = usb_hcd_pci_probe, | |
412 | .remove = usb_hcd_pci_remove, | |
abb30641 | 413 | .shutdown = usb_hcd_pci_shutdown, |
7ff71d6a | 414 | |
abb30641 AS |
415 | #ifdef CONFIG_PM_SLEEP |
416 | .driver = { | |
417 | .pm = &usb_hcd_pci_pm_ops | |
418 | }, | |
7ff71d6a MP |
419 | #endif |
420 | }; | |
adfa79d1 AS |
421 | |
422 | static int __init ehci_pci_init(void) | |
423 | { | |
424 | if (usb_disabled()) | |
425 | return -ENODEV; | |
426 | ||
427 | pr_info("%s: " DRIVER_DESC "\n", hcd_name); | |
428 | ||
429 | ehci_init_driver(&ehci_pci_hc_driver, &overrides); | |
430 | ||
431 | /* Entries for the PCI suspend/resume callbacks are special */ | |
432 | ehci_pci_hc_driver.pci_suspend = ehci_suspend; | |
433 | ehci_pci_hc_driver.pci_resume = ehci_pci_resume; | |
434 | ||
435 | return pci_register_driver(&ehci_pci_driver); | |
436 | } | |
437 | module_init(ehci_pci_init); | |
438 | ||
439 | static void __exit ehci_pci_cleanup(void) | |
440 | { | |
441 | pci_unregister_driver(&ehci_pci_driver); | |
442 | } | |
443 | module_exit(ehci_pci_cleanup); | |
444 | ||
445 | MODULE_DESCRIPTION(DRIVER_DESC); | |
446 | MODULE_AUTHOR("David Brownell"); | |
447 | MODULE_AUTHOR("Alan Stern"); | |
448 | MODULE_LICENSE("GPL"); |