[mirror_ubuntu-artful-kernel.git] / drivers / usb / host / ehci-pci.c

/*
 * EHCI HCD (Host Controller Driver) PCI Bus Glue.
 *
 * Copyright (c) 2000-2004 by David Brownell
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
 * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 * for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software Foundation,
 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#ifndef CONFIG_PCI
#error "This file is PCI bus glue.  CONFIG_PCI must be defined."
#endif

/* defined here to avoid adding to pci_ids.h for single instance use */
#define PCI_DEVICE_ID_INTEL_CE4100_USB	0x2e70

/*-------------------------------------------------------------------------*/

/* called after powerup, by probe or system-pm "wakeup" */
static int ehci_pci_reinit(struct ehci_hcd *ehci, struct pci_dev *pdev)
{
	int			retval;

	/* we expect static quirk code to handle the "extended capabilities"
	 * (currently just BIOS handoff) allowed starting with EHCI 0.96
	 */

	/* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
	retval = pci_set_mwi(pdev);
	if (!retval)
		ehci_dbg(ehci, "MWI active\n");

	return 0;
}

/* called during probe() after chip reset completes */
static int ehci_pci_setup(struct usb_hcd *hcd)
{
	struct ehci_hcd		*ehci = hcd_to_ehci(hcd);
	struct pci_dev		*pdev = to_pci_dev(hcd->self.controller);
	struct pci_dev		*p_smbus;
	u8			rev;
	u32			temp;
	int			retval;

	ehci->caps = hcd->regs;

	/*
	 * ehci_init() causes memory for DMA transfers to be
	 * allocated.  Thus, any vendor-specific workarounds based on
	 * limiting the type of memory used for DMA transfers must
	 * happen before ehci_setup() is called.
	 *
	 * Most other workarounds can be done either before or after
	 * init and reset; they are located here too.
	 */
	switch (pdev->vendor) {
	case PCI_VENDOR_ID_TOSHIBA_2:
		/* celleb's companion chip */
		if (pdev->device == 0x01b5) {
#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
			ehci->big_endian_mmio = 1;
#else
			ehci_warn(ehci,
				  "unsupported big endian Toshiba quirk\n");
#endif
		}
		break;
	case PCI_VENDOR_ID_NVIDIA:
		/* NVidia reports that certain chips don't handle
		 * QH, ITD, or SITD addresses above 2GB.  (But TD,
		 * data buffer, and periodic schedule are normal.)
		 */
		switch (pdev->device) {
		case 0x003c:	/* MCP04 */
		case 0x005b:	/* CK804 */
		case 0x00d8:	/* CK8 */
		case 0x00e8:	/* CK8S */
			if (pci_set_consistent_dma_mask(pdev,
						DMA_BIT_MASK(31)) < 0)
				ehci_warn(ehci, "can't enable NVidia "
					"workaround for >2GB RAM\n");
			break;

		/* Some NForce2 chips have problems with selective suspend;
		 * fixed in newer silicon.
		 */
		case 0x0068:
			if (pdev->revision < 0xa4)
				ehci->no_selective_suspend = 1;
			break;
		}
		break;
	case PCI_VENDOR_ID_INTEL:
		if (pdev->device == PCI_DEVICE_ID_INTEL_CE4100_USB)
			hcd->has_tt = 1;
		break;
	case PCI_VENDOR_ID_TDI:
		if (pdev->device == PCI_DEVICE_ID_TDI_EHCI)
			hcd->has_tt = 1;
		break;
	case PCI_VENDOR_ID_AMD:
		/* AMD PLL quirk */
		if (usb_amd_find_chipset_info())
			ehci->amd_pll_fix = 1;
		/* AMD8111 EHCI doesn't work, according to AMD errata */
		if (pdev->device == 0x7463) {
			ehci_info(ehci, "ignoring AMD8111 (errata)\n");
			retval = -EIO;
			goto done;
		}

		/*
		 * EHCI controller on AMD SB700/SB800/Hudson-2/3 platforms may
		 * read/write memory space which does not belong to it when
		 * there is NULL pointer with T-bit set to 1 in the frame list
		 * table. To avoid the issue, the frame list link pointer
		 * should always contain a valid pointer to a inactive qh.
		 */
		if (pdev->device == 0x7808) {
			ehci->use_dummy_qh = 1;
			ehci_info(ehci, "applying AMD SB700/SB800/Hudson-2/3 EHCI dummy qh workaround\n");
		}
		break;
	case PCI_VENDOR_ID_VIA:
		if (pdev->device == 0x3104 && (pdev->revision & 0xf0) == 0x60) {
			u8 tmp;

			/* The VT6212 defaults to a 1 usec EHCI sleep time which
			 * hogs the PCI bus *badly*. Setting bit 5 of 0x4B makes
			 * that sleep time use the conventional 10 usec.
			 */
			pci_read_config_byte(pdev, 0x4b, &tmp);
			if (tmp & 0x20)
				break;
			pci_write_config_byte(pdev, 0x4b, tmp | 0x20);
		}
		break;
	case PCI_VENDOR_ID_ATI:
		/* AMD PLL quirk */
		if (usb_amd_find_chipset_info())
			ehci->amd_pll_fix = 1;

		/*
		 * EHCI controller on AMD SB700/SB800/Hudson-2/3 platforms may
		 * read/write memory space which does not belong to it when
		 * there is NULL pointer with T-bit set to 1 in the frame list
		 * table. To avoid the issue, the frame list link pointer
		 * should always contain a valid pointer to a inactive qh.
		 */
		if (pdev->device == 0x4396) {
			ehci->use_dummy_qh = 1;
			ehci_info(ehci, "applying AMD SB700/SB800/Hudson-2/3 EHCI dummy qh workaround\n");
		}
		/* SB600 and old version of SB700 have a bug in EHCI controller,
		 * which causes usb devices lose response in some cases.
		 */
		if ((pdev->device == 0x4386) || (pdev->device == 0x4396)) {
			p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
						 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
						 NULL);
			if (!p_smbus)
				break;
			rev = p_smbus->revision;
			if ((pdev->device == 0x4386) || (rev == 0x3a)
			    || (rev == 0x3b)) {
				u8 tmp;
				ehci_info(ehci, "applying AMD SB600/SB700 USB "
					"freeze workaround\n");
				pci_read_config_byte(pdev, 0x53, &tmp);
				pci_write_config_byte(pdev, 0x53, tmp | (1<<3));
			}
			pci_dev_put(p_smbus);
		}
		break;
	case PCI_VENDOR_ID_NETMOS:
		/* MosChip frame-index-register bug */
		ehci_info(ehci, "applying MosChip frame-index workaround\n");
		ehci->frame_index_bug = 1;
		break;
	}

	retval = ehci_setup(hcd);
	if (retval)
		return retval;

	/* These workarounds need to be applied after ehci_setup() */
	switch (pdev->vendor) {
	case PCI_VENDOR_ID_NEC:
		ehci->need_io_watchdog = 0;
		break;
	case PCI_VENDOR_ID_INTEL:
		ehci->need_io_watchdog = 0;
		if (pdev->device == 0x0806 || pdev->device == 0x0811
				|| pdev->device == 0x0829) {
			ehci_info(ehci, "disable lpm for langwell/penwell\n");
			ehci->has_lpm = 0;
		}
		break;
	case PCI_VENDOR_ID_NVIDIA:
		switch (pdev->device) {
		/* MCP89 chips on the MacBookAir3,1 give EPROTO when
		 * fetching device descriptors unless LPM is disabled.
		 * There are also intermittent problems enumerating
		 * devices with PPCD enabled.
		 */
		case 0x0d9d:
			ehci_info(ehci, "disable lpm/ppcd for nvidia mcp89");
			ehci->has_lpm = 0;
			ehci->has_ppcd = 0;
			ehci->command &= ~CMD_PPCEE;
			break;
		}
		break;
	}

	/* optional debug port, normally in the first BAR */
	temp = pci_find_capability(pdev, 0x0a);
	if (temp) {
		pci_read_config_dword(pdev, temp, &temp);
		temp >>= 16;
		if ((temp & (3 << 13)) == (1 << 13)) {
			temp &= 0x1fff;
			ehci->debug = hcd->regs + temp;
			temp = ehci_readl(ehci, &ehci->debug->control);
			ehci_info(ehci, "debug port %d%s\n",
				HCS_DEBUG_PORT(ehci->hcs_params),
				(temp & DBGP_ENABLED)
					? " IN USE"
					: "");
			if (!(temp & DBGP_ENABLED))
				ehci->debug = NULL;
		}
	}

	/* at least the Genesys GL880S needs fixup here */
	temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params);
	temp &= 0x0f;
	if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) {
		ehci_dbg(ehci, "bogus port configuration: "
			"cc=%d x pcc=%d < ports=%d\n",
			HCS_N_CC(ehci->hcs_params),
			HCS_N_PCC(ehci->hcs_params),
			HCS_N_PORTS(ehci->hcs_params));

		switch (pdev->vendor) {
		case 0x17a0:		/* GENESYS */
			/* GL880S: should be PORTS=2 */
			temp |= (ehci->hcs_params & ~0xf);
			ehci->hcs_params = temp;
			break;
		case PCI_VENDOR_ID_NVIDIA:
			/* NF4: should be PCC=10 */
			break;
		}
	}

	/* Serial Bus Release Number is at PCI 0x60 offset */
	if (pdev->vendor == PCI_VENDOR_ID_STMICRO
	    && pdev->device == PCI_DEVICE_ID_STMICRO_USB_HOST)
		;	/* ConneXT has no sbrn register */
	else
		pci_read_config_byte(pdev, 0x60, &ehci->sbrn);

	/* Keep this around for a while just in case some EHCI
	 * implementation uses legacy PCI PM support.  This test
	 * can be removed on 17 Dec 2009 if the dev_warn() hasn't
	 * been triggered by then.
	 */
	if (!device_can_wakeup(&pdev->dev)) {
		u16	port_wake;

		pci_read_config_word(pdev, 0x62, &port_wake);
		if (port_wake & 0x0001) {
			dev_warn(&pdev->dev, "Enabling legacy PCI PM\n");
			device_set_wakeup_capable(&pdev->dev, 1);
		}
	}

#ifdef	CONFIG_USB_SUSPEND
	/* REVISIT: the controller works fine for wakeup iff the root hub
	 * itself is "globally" suspended, but usbcore currently doesn't
	 * understand such things.
	 *
	 * System suspend currently expects to be able to suspend the entire
	 * device tree, device-at-a-time.  If we failed selective suspend
	 * reports, system suspend would fail; so the root hub code must claim
	 * success.  That's lying to usbcore, and it matters for runtime
	 * PM scenarios with selective suspend and remote wakeup...
	 */
	if (ehci->no_selective_suspend && device_can_wakeup(&pdev->dev))
		ehci_warn(ehci, "selective suspend/wakeup unavailable\n");
#endif

	ehci_port_power(ehci, 1);
	retval = ehci_pci_reinit(ehci, pdev);
done:
	return retval;
}

/*-------------------------------------------------------------------------*/

#ifdef	CONFIG_PM

/* suspend/resume, section 4.3 */

/* These routines rely on the PCI bus glue
 * to handle powerdown and wakeup, and currently also on
 * transceivers that don't need any software attention to set up
 * the right sort of wakeup.
 * Also they depend on separate root hub suspend/resume.
 */

static int ehci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
{
	return ehci_suspend(hcd, do_wakeup);
}

static bool usb_is_intel_switchable_ehci(struct pci_dev *pdev)
{
	return pdev->class == PCI_CLASS_SERIAL_USB_EHCI &&
		pdev->vendor == PCI_VENDOR_ID_INTEL &&
		(pdev->device == 0x1E26 ||
		 pdev->device == 0x8C2D ||
		 pdev->device == 0x8C26);
}

static void ehci_enable_xhci_companion(void)
{
	struct pci_dev		*companion = NULL;

	/* The xHCI and EHCI controllers are not on the same PCI slot */
	for_each_pci_dev(companion) {
		if (!usb_is_intel_switchable_xhci(companion))
			continue;
		usb_enable_xhci_ports(companion);
		return;
	}
}

static int ehci_pci_resume(struct usb_hcd *hcd, bool hibernated)
{
	struct ehci_hcd		*ehci = hcd_to_ehci(hcd);
	struct pci_dev		*pdev = to_pci_dev(hcd->self.controller);

	/* The BIOS on systems with the Intel Panther Point chipset may or may
	 * not support xHCI natively.  That means that during system resume, it
	 * may switch the ports back to EHCI so that users can use their
	 * keyboard to select a kernel from GRUB after resume from hibernate.
	 *
	 * The BIOS is supposed to remember whether the OS had xHCI ports
	 * enabled before resume, and switch the ports back to xHCI when the
	 * BIOS/OS semaphore is written, but we all know we can't trust BIOS
	 * writers.
	 *
	 * Unconditionally switch the ports back to xHCI after a system resume.
	 * We can't tell whether the EHCI or xHCI controller will be resumed
	 * first, so we have to do the port switchover in both drivers.  Writing
	 * a '1' to the port switchover registers should have no effect if the
	 * port was already switched over.
	 */
	if (usb_is_intel_switchable_ehci(pdev))
		ehci_enable_xhci_companion();

	if (ehci_resume(hcd, hibernated) != 0)
		(void) ehci_pci_reinit(ehci, pdev);
	return 0;
}
#endif

static const struct hc_driver ehci_pci_hc_driver = {
	.description =		hcd_name,
	.product_desc =		"EHCI Host Controller",
	.hcd_priv_size =	sizeof(struct ehci_hcd),

	/*
	 * generic hardware linkage
	 */
	.irq =			ehci_irq,
	.flags =		HCD_MEMORY | HCD_USB2,

	/*
	 * basic lifecycle operations
	 */
	.reset =		ehci_pci_setup,
	.start =		ehci_run,
#ifdef	CONFIG_PM
	.pci_suspend =		ehci_pci_suspend,
	.pci_resume =		ehci_pci_resume,
#endif
	.stop =			ehci_stop,
	.shutdown =		ehci_shutdown,

	/*
	 * managing i/o requests and associated device resources
	 */
	.urb_enqueue =		ehci_urb_enqueue,
	.urb_dequeue =		ehci_urb_dequeue,
	.endpoint_disable =	ehci_endpoint_disable,
	.endpoint_reset =	ehci_endpoint_reset,

	/*
	 * scheduling support
	 */
	.get_frame_number =	ehci_get_frame,

	/*
	 * root hub support
	 */
	.hub_status_data =	ehci_hub_status_data,
	.hub_control =		ehci_hub_control,
	.bus_suspend =		ehci_bus_suspend,
	.bus_resume =		ehci_bus_resume,
	.relinquish_port =	ehci_relinquish_port,
	.port_handed_over =	ehci_port_handed_over,

	/*
	 * call back when device connected and addressed
	 */
	.update_device =	ehci_update_device,

	.clear_tt_buffer_complete	= ehci_clear_tt_buffer_complete,
};

/*-------------------------------------------------------------------------*/

/* PCI driver selection metadata; PCI hotplugging uses this */
static const struct pci_device_id pci_ids [] = { {
	/* handle any USB 2.0 EHCI controller */
	PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_EHCI, ~0),
	.driver_data =	(unsigned long) &ehci_pci_hc_driver,
	}, {
	PCI_VDEVICE(STMICRO, PCI_DEVICE_ID_STMICRO_USB_HOST),
	.driver_data = (unsigned long) &ehci_pci_hc_driver,
	},
	{ /* end: all zeroes */ }
};
MODULE_DEVICE_TABLE(pci, pci_ids);

/* pci driver glue; this is a "new style" PCI driver module */
static struct pci_driver ehci_pci_driver = {
	.name =		(char *) hcd_name,
	.id_table =	pci_ids,

	.probe =	usb_hcd_pci_probe,
	.remove =	usb_hcd_pci_remove,
	.shutdown = 	usb_hcd_pci_shutdown,

#ifdef CONFIG_PM_SLEEP
	.driver =	{
		.pm =	&usb_hcd_pci_pm_ops
	},
#endif
};
Commit	Line	Data
7ff71d6a MP	1	/*
	2	* EHCI HCD (Host Controller Driver) PCI Bus Glue.
	3	*
	4	* Copyright (c) 2000-2004 by David Brownell
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License as published by the
	8	* Free Software Foundation; either version 2 of the License, or (at your
	9	* option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful, but
	12	* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	13	* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	14	* for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software Foundation,
	18	* Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	19	*/
	20
	21	#ifndef CONFIG_PCI
	22	#error "This file is PCI bus glue. CONFIG_PCI must be defined."
	23	#endif
	24
4f683843 DB	25	/* defined here to avoid adding to pci_ids.h for single instance use */
	26	#define PCI_DEVICE_ID_INTEL_CE4100_USB 0x2e70
	27
7ff71d6a MP	28	/-------------------------------------------------------------------------/
7ff71d6a MP	29
18807521 DB	30	/* called after powerup, by probe or system-pm "wakeup" */
	31	static int ehci_pci_reinit(struct ehci_hcd ehci, struct pci_dev pdev)
	32	{
18807521	33	int retval;
18807521	34
401feafa DB	35	/* we expect static quirk code to handle the "extended capabilities"
	36	* (currently just BIOS handoff) allowed starting with EHCI 0.96
	37	*/
18807521 DB	38
	39	/* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
	40	retval = pci_set_mwi(pdev);
	41	if (!retval)
	42	ehci_dbg(ehci, "MWI active\n");
	43
18807521 DB	44	return 0;
	45	}
	46
8926bfa7 DB	47	/* called during probe() after chip reset completes */
8926bfa7 DB	48	static int ehci_pci_setup(struct usb_hcd *hcd)
7ff71d6a	49	{
abcc9448 DB	50	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
abcc9448 DB	51	struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
b09bc6cb AX	52	struct pci_dev *p_smbus;
b09bc6cb AX	53	u8 rev;
7ff71d6a	54	u32 temp;
18807521	55	int retval;
7ff71d6a	56
1a49e2ac AS	57	ehci->caps = hcd->regs;
	58
	59	/*
	60	* ehci_init() causes memory for DMA transfers to be
	61	* allocated. Thus, any vendor-specific workarounds based on
	62	* limiting the type of memory used for DMA transfers must
	63	* happen before ehci_setup() is called.
	64	*
	65	* Most other workarounds can be done either before or after
	66	* init and reset; they are located here too.
	67	*/
083522d7 BH	68	switch (pdev->vendor) {
	69	case PCI_VENDOR_ID_TOSHIBA_2:
	70	/* celleb's companion chip */
	71	if (pdev->device == 0x01b5) {
	72	#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
	73	ehci->big_endian_mmio = 1;
	74	#else
	75	ehci_warn(ehci,
	76	"unsupported big endian Toshiba quirk\n");
	77	#endif
	78	}
	79	break;
c32ba30f PS	80	case PCI_VENDOR_ID_NVIDIA:
	81	/* NVidia reports that certain chips don't handle
	82	* QH, ITD, or SITD addresses above 2GB. (But TD,
	83	* data buffer, and periodic schedule are normal.)
	84	*/
	85	switch (pdev->device) {
	86	case 0x003c: /* MCP04 */
	87	case 0x005b: /* CK804 */
	88	case 0x00d8: /* CK8 */
	89	case 0x00e8: /* CK8S */
	90	if (pci_set_consistent_dma_mask(pdev,
929a22a5	91	DMA_BIT_MASK(31)) < 0)
c32ba30f PS	92	ehci_warn(ehci, "can't enable NVidia "
	93	"workaround for >2GB RAM\n");
	94	break;
7ff71d6a	95
1a49e2ac AS	96	/* Some NForce2 chips have problems with selective suspend;
1a49e2ac AS	97	* fixed in newer silicon.
3d091a6f	98	*/
1a49e2ac AS	99	case 0x0068:
	100	if (pdev->revision < 0xa4)
	101	ehci->no_selective_suspend = 1;
	102	break;
	103	}
3681d8f3	104	break;
403dbd36	105	case PCI_VENDOR_ID_INTEL:
1a49e2ac	106	if (pdev->device == PCI_DEVICE_ID_INTEL_CE4100_USB)
4f683843	107	hcd->has_tt = 1;
403dbd36	108	break;
abcc9448	109	case PCI_VENDOR_ID_TDI:
1a49e2ac	110	if (pdev->device == PCI_DEVICE_ID_TDI_EHCI)
7329e211	111	hcd->has_tt = 1;
abcc9448 DB	112	break;
abcc9448 DB	113	case PCI_VENDOR_ID_AMD:
ad93562b AX	114	/* AMD PLL quirk */
	115	if (usb_amd_find_chipset_info())
	116	ehci->amd_pll_fix = 1;
abcc9448 DB	117	/* AMD8111 EHCI doesn't work, according to AMD errata */
	118	if (pdev->device == 0x7463) {
	119	ehci_info(ehci, "ignoring AMD8111 (errata)\n");
8926bfa7 DB	120	retval = -EIO;
8926bfa7 DB	121	goto done;
abcc9448	122	}
a85b4e7f	123
1a49e2ac AS	124	/*
	125	* EHCI controller on AMD SB700/SB800/Hudson-2/3 platforms may
	126	* read/write memory space which does not belong to it when
	127	* there is NULL pointer with T-bit set to 1 in the frame list
	128	* table. To avoid the issue, the frame list link pointer
	129	* should always contain a valid pointer to a inactive qh.
a85b4e7f	130	*/
1a49e2ac AS	131	if (pdev->device == 0x7808) {
	132	ehci->use_dummy_qh = 1;
	133	ehci_info(ehci, "applying AMD SB700/SB800/Hudson-2/3 EHCI dummy qh workaround\n");
7ff71d6a	134	}
abcc9448	135	break;
055b93c9 RH	136	case PCI_VENDOR_ID_VIA:
	137	if (pdev->device == 0x3104 && (pdev->revision & 0xf0) == 0x60) {
	138	u8 tmp;
	139
	140	/* The VT6212 defaults to a 1 usec EHCI sleep time which
	141	* hogs the PCI bus badly. Setting bit 5 of 0x4B makes
	142	* that sleep time use the conventional 10 usec.
	143	*/
	144	pci_read_config_byte(pdev, 0x4b, &tmp);
	145	if (tmp & 0x20)
	146	break;
	147	pci_write_config_byte(pdev, 0x4b, tmp \| 0x20);
	148	}
	149	break;
b09bc6cb	150	case PCI_VENDOR_ID_ATI:
ad93562b AX	151	/* AMD PLL quirk */
	152	if (usb_amd_find_chipset_info())
	153	ehci->amd_pll_fix = 1;
1a49e2ac AS	154
	155	/*
	156	* EHCI controller on AMD SB700/SB800/Hudson-2/3 platforms may
	157	* read/write memory space which does not belong to it when
	158	* there is NULL pointer with T-bit set to 1 in the frame list
	159	* table. To avoid the issue, the frame list link pointer
	160	* should always contain a valid pointer to a inactive qh.
	161	*/
	162	if (pdev->device == 0x4396) {
	163	ehci->use_dummy_qh = 1;
	164	ehci_info(ehci, "applying AMD SB700/SB800/Hudson-2/3 EHCI dummy qh workaround\n");
	165	}
0a99e8ac	166	/* SB600 and old version of SB700 have a bug in EHCI controller,
b09bc6cb AX	167	* which causes usb devices lose response in some cases.
b09bc6cb AX	168	*/
0a99e8ac	169	if ((pdev->device == 0x4386) \|\| (pdev->device == 0x4396)) {
b09bc6cb AX	170	p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
	171	PCI_DEVICE_ID_ATI_SBX00_SMBUS,
	172	NULL);
	173	if (!p_smbus)
	174	break;
	175	rev = p_smbus->revision;
0a99e8ac SH	176	if ((pdev->device == 0x4386) \|\| (rev == 0x3a)
0a99e8ac SH	177	\|\| (rev == 0x3b)) {
b09bc6cb	178	u8 tmp;
0a99e8ac SH	179	ehci_info(ehci, "applying AMD SB600/SB700 USB "
0a99e8ac SH	180	"freeze workaround\n");
b09bc6cb AX	181	pci_read_config_byte(pdev, 0x53, &tmp);
	182	pci_write_config_byte(pdev, 0x53, tmp \| (1<<3));
	183	}
	184	pci_dev_put(p_smbus);
	185	}
	186	break;
68aa95d5 AS	187	case PCI_VENDOR_ID_NETMOS:
	188	/* MosChip frame-index-register bug */
	189	ehci_info(ehci, "applying MosChip frame-index workaround\n");
	190	ehci->frame_index_bug = 1;
	191	break;
abcc9448	192	}
7ff71d6a	193
1a49e2ac AS	194	retval = ehci_setup(hcd);
	195	if (retval)
	196	return retval;
	197
	198	/* These workarounds need to be applied after ehci_setup() */
	199	switch (pdev->vendor) {
	200	case PCI_VENDOR_ID_NEC:
	201	ehci->need_io_watchdog = 0;
	202	break;
	203	case PCI_VENDOR_ID_INTEL:
	204	ehci->need_io_watchdog = 0;
	205	if (pdev->device == 0x0806 \|\| pdev->device == 0x0811
	206	\|\| pdev->device == 0x0829) {
	207	ehci_info(ehci, "disable lpm for langwell/penwell\n");
	208	ehci->has_lpm = 0;
	209	}
	210	break;
	211	case PCI_VENDOR_ID_NVIDIA:
	212	switch (pdev->device) {
	213	/* MCP89 chips on the MacBookAir3,1 give EPROTO when
	214	* fetching device descriptors unless LPM is disabled.
	215	* There are also intermittent problems enumerating
	216	* devices with PPCD enabled.
	217	*/
	218	case 0x0d9d:
	219	ehci_info(ehci, "disable lpm/ppcd for nvidia mcp89");
	220	ehci->has_lpm = 0;
	221	ehci->has_ppcd = 0;
	222	ehci->command &= ~CMD_PPCEE;
	223	break;
	224	}
	225	break;
	226	}
	227
8d053c79 JW	228	/* optional debug port, normally in the first BAR */
	229	temp = pci_find_capability(pdev, 0x0a);
	230	if (temp) {
	231	pci_read_config_dword(pdev, temp, &temp);
	232	temp >>= 16;
	233	if ((temp & (3 << 13)) == (1 << 13)) {
	234	temp &= 0x1fff;
1a49e2ac	235	ehci->debug = hcd->regs + temp;
8d053c79 JW	236	temp = ehci_readl(ehci, &ehci->debug->control);
	237	ehci_info(ehci, "debug port %d%s\n",
	238	HCS_DEBUG_PORT(ehci->hcs_params),
	239	(temp & DBGP_ENABLED)
	240	? " IN USE"
	241	: "");
	242	if (!(temp & DBGP_ENABLED))
	243	ehci->debug = NULL;
	244	}
	245	}
	246
7ff71d6a MP	247	/* at least the Genesys GL880S needs fixup here */
	248	temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params);
	249	temp &= 0x0f;
	250	if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) {
abcc9448	251	ehci_dbg(ehci, "bogus port configuration: "
7ff71d6a MP	252	"cc=%d x pcc=%d < ports=%d\n",
	253	HCS_N_CC(ehci->hcs_params),
	254	HCS_N_PCC(ehci->hcs_params),
	255	HCS_N_PORTS(ehci->hcs_params));
	256
abcc9448 DB	257	switch (pdev->vendor) {
	258	case 0x17a0: /* GENESYS */
	259	/* GL880S: should be PORTS=2 */
	260	temp \|= (ehci->hcs_params & ~0xf);
	261	ehci->hcs_params = temp;
	262	break;
	263	case PCI_VENDOR_ID_NVIDIA:
	264	/* NF4: should be PCC=10 */
	265	break;
7ff71d6a MP	266	}
	267	}
	268
abcc9448	269	/* Serial Bus Release Number is at PCI 0x60 offset */
3a0bac06 AR	270	if (pdev->vendor == PCI_VENDOR_ID_STMICRO
3a0bac06 AR	271	&& pdev->device == PCI_DEVICE_ID_STMICRO_USB_HOST)
1a49e2ac AS	272	; /* ConneXT has no sbrn register */
	273	else
	274	pci_read_config_byte(pdev, 0x60, &ehci->sbrn);
7ff71d6a	275
6fd9086a AS	276	/* Keep this around for a while just in case some EHCI
	277	* implementation uses legacy PCI PM support. This test
	278	* can be removed on 17 Dec 2009 if the dev_warn() hasn't
	279	* been triggered by then.
2c1c3c4c DB	280	*/
	281	if (!device_can_wakeup(&pdev->dev)) {
	282	u16 port_wake;
	283
	284	pci_read_config_word(pdev, 0x62, &port_wake);
6fd9086a AS	285	if (port_wake & 0x0001) {
6fd9086a AS	286	dev_warn(&pdev->dev, "Enabling legacy PCI PM\n");
bcca06ef	287	device_set_wakeup_capable(&pdev->dev, 1);
6fd9086a	288	}
2c1c3c4c	289	}
7ff71d6a	290
f8aeb3bb DB	291	#ifdef CONFIG_USB_SUSPEND
	292	/* REVISIT: the controller works fine for wakeup iff the root hub
	293	* itself is "globally" suspended, but usbcore currently doesn't
	294	* understand such things.
	295	*
	296	* System suspend currently expects to be able to suspend the entire
	297	* device tree, device-at-a-time. If we failed selective suspend
	298	* reports, system suspend would fail; so the root hub code must claim
411c9403	299	* success. That's lying to usbcore, and it matters for runtime
f8aeb3bb DB	300	* PM scenarios with selective suspend and remote wakeup...
	301	*/
	302	if (ehci->no_selective_suspend && device_can_wakeup(&pdev->dev))
	303	ehci_warn(ehci, "selective suspend/wakeup unavailable\n");
	304	#endif
	305
aff6d18f	306	ehci_port_power(ehci, 1);
18807521	307	retval = ehci_pci_reinit(ehci, pdev);
8926bfa7 DB	308	done:
8926bfa7 DB	309	return retval;
7ff71d6a MP	310	}
	311
	312	/-------------------------------------------------------------------------/
	313
	314	#ifdef CONFIG_PM
	315
	316	/* suspend/resume, section 4.3 */
	317
f03c17fc	318	/* These routines rely on the PCI bus glue
7ff71d6a MP	319	* to handle powerdown and wakeup, and currently also on
	320	* transceivers that don't need any software attention to set up
	321	* the right sort of wakeup.
f03c17fc	322	* Also they depend on separate root hub suspend/resume.
7ff71d6a MP	323	*/
7ff71d6a MP	324
4147200d	325	static int ehci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
7ff71d6a	326	{
c5cf9212	327	return ehci_suspend(hcd, do_wakeup);
7ff71d6a MP	328	}
7ff71d6a MP	329
69e848c2 SS	330	static bool usb_is_intel_switchable_ehci(struct pci_dev *pdev)
	331	{
	332	return pdev->class == PCI_CLASS_SERIAL_USB_EHCI &&
	333	pdev->vendor == PCI_VENDOR_ID_INTEL &&
1c12443a SS	334	(pdev->device == 0x1E26 \|\|
	335	pdev->device == 0x8C2D \|\|
	336	pdev->device == 0x8C26);
69e848c2 SS	337	}
	338
	339	static void ehci_enable_xhci_companion(void)
	340	{
	341	struct pci_dev *companion = NULL;
	342
	343	/* The xHCI and EHCI controllers are not on the same PCI slot */
	344	for_each_pci_dev(companion) {
	345	if (!usb_is_intel_switchable_xhci(companion))
	346	continue;
	347	usb_enable_xhci_ports(companion);
	348	return;
	349	}
	350	}
	351
6ec4beb5	352	static int ehci_pci_resume(struct usb_hcd *hcd, bool hibernated)
7ff71d6a	353	{
abcc9448	354	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
18807521	355	struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
7ff71d6a	356
69e848c2 SS	357	/* The BIOS on systems with the Intel Panther Point chipset may or may
	358	* not support xHCI natively. That means that during system resume, it
	359	* may switch the ports back to EHCI so that users can use their
	360	* keyboard to select a kernel from GRUB after resume from hibernate.
	361	*
	362	* The BIOS is supposed to remember whether the OS had xHCI ports
	363	* enabled before resume, and switch the ports back to xHCI when the
	364	* BIOS/OS semaphore is written, but we all know we can't trust BIOS
	365	* writers.
	366	*
	367	* Unconditionally switch the ports back to xHCI after a system resume.
	368	* We can't tell whether the EHCI or xHCI controller will be resumed
	369	* first, so we have to do the port switchover in both drivers. Writing
	370	* a '1' to the port switchover registers should have no effect if the
	371	* port was already switched over.
	372	*/
	373	if (usb_is_intel_switchable_ehci(pdev))
	374	ehci_enable_xhci_companion();
	375
c5cf9212 AS	376	if (ehci_resume(hcd, hibernated) != 0)
c5cf9212 AS	377	(void) ehci_pci_reinit(ehci, pdev);
8c03356a	378	return 0;
7ff71d6a MP	379	}
	380	#endif
	381
	382	static const struct hc_driver ehci_pci_hc_driver = {
	383	.description = hcd_name,
	384	.product_desc = "EHCI Host Controller",
	385	.hcd_priv_size = sizeof(struct ehci_hcd),
	386
	387	/*
	388	* generic hardware linkage
	389	*/
	390	.irq = ehci_irq,
	391	.flags = HCD_MEMORY \| HCD_USB2,
	392
	393	/*
	394	* basic lifecycle operations
	395	*/
8926bfa7	396	.reset = ehci_pci_setup,
18807521	397	.start = ehci_run,
7ff71d6a	398	#ifdef CONFIG_PM
7be7d741 AS	399	.pci_suspend = ehci_pci_suspend,
7be7d741 AS	400	.pci_resume = ehci_pci_resume,
7ff71d6a	401	#endif
18807521	402	.stop = ehci_stop,
64a21d02	403	.shutdown = ehci_shutdown,
7ff71d6a MP	404
	405	/*
	406	* managing i/o requests and associated device resources
	407	*/
	408	.urb_enqueue = ehci_urb_enqueue,
	409	.urb_dequeue = ehci_urb_dequeue,
	410	.endpoint_disable = ehci_endpoint_disable,
b18ffd49	411	.endpoint_reset = ehci_endpoint_reset,
7ff71d6a MP	412
	413	/*
	414	* scheduling support
	415	*/
	416	.get_frame_number = ehci_get_frame,
	417
	418	/*
	419	* root hub support
	420	*/
	421	.hub_status_data = ehci_hub_status_data,
	422	.hub_control = ehci_hub_control,
0c0382e3 AS	423	.bus_suspend = ehci_bus_suspend,
0c0382e3 AS	424	.bus_resume = ehci_bus_resume,
a8e51775	425	.relinquish_port = ehci_relinquish_port,
3a31155c	426	.port_handed_over = ehci_port_handed_over,
914b7012	427
48f24970 AD	428	/*
	429	* call back when device connected and addressed
	430	*/
	431	.update_device = ehci_update_device,
	432
914b7012	433	.clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
7ff71d6a MP	434	};
	435
	436	/-------------------------------------------------------------------------/
	437
	438	/* PCI driver selection metadata; PCI hotplugging uses this */
	439	static const struct pci_device_id pci_ids [] = { {
	440	/* handle any USB 2.0 EHCI controller */
c67808ee	441	PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_EHCI, ~0),
7ff71d6a	442	.driver_data = (unsigned long) &ehci_pci_hc_driver,
3a0bac06 AR	443	}, {
	444	PCI_VDEVICE(STMICRO, PCI_DEVICE_ID_STMICRO_USB_HOST),
	445	.driver_data = (unsigned long) &ehci_pci_hc_driver,
7ff71d6a MP	446	},
	447	{ /* end: all zeroes */ }
	448	};
abcc9448	449	MODULE_DEVICE_TABLE(pci, pci_ids);
7ff71d6a MP	450
	451	/* pci driver glue; this is a "new style" PCI driver module */
	452	static struct pci_driver ehci_pci_driver = {
	453	.name = (char *) hcd_name,
	454	.id_table = pci_ids,
	455
	456	.probe = usb_hcd_pci_probe,
	457	.remove = usb_hcd_pci_remove,
abb30641	458	.shutdown = usb_hcd_pci_shutdown,
7ff71d6a	459
abb30641 AS	460	#ifdef CONFIG_PM_SLEEP
	461	.driver = {
	462	.pm = &usb_hcd_pci_pm_ops
	463	},
7ff71d6a MP	464	#endif
7ff71d6a MP	465	};