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1da177e4 | 1 | /* |
d49d4317 | 2 | * Copyright (C) 2001-2004 by David Brownell |
53bd6a60 | 3 | * |
1da177e4 LT |
4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms of the GNU General Public License as published by the | |
6 | * Free Software Foundation; either version 2 of the License, or (at your | |
7 | * option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but | |
10 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
11 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 | * for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software Foundation, | |
16 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
17 | */ | |
18 | ||
19 | /* this file is part of ehci-hcd.c */ | |
20 | ||
21 | /*-------------------------------------------------------------------------*/ | |
22 | ||
23 | /* | |
24 | * EHCI hardware queue manipulation ... the core. QH/QTD manipulation. | |
25 | * | |
26 | * Control, bulk, and interrupt traffic all use "qh" lists. They list "qtd" | |
27 | * entries describing USB transactions, max 16-20kB/entry (with 4kB-aligned | |
28 | * buffers needed for the larger number). We use one QH per endpoint, queue | |
29 | * multiple urbs (all three types) per endpoint. URBs may need several qtds. | |
30 | * | |
31 | * ISO traffic uses "ISO TD" (itd, and sitd) records, and (along with | |
32 | * interrupts) needs careful scheduling. Performance improvements can be | |
33 | * an ongoing challenge. That's in "ehci-sched.c". | |
53bd6a60 | 34 | * |
1da177e4 LT |
35 | * USB 1.1 devices are handled (a) by "companion" OHCI or UHCI root hubs, |
36 | * or otherwise through transaction translators (TTs) in USB 2.0 hubs using | |
37 | * (b) special fields in qh entries or (c) split iso entries. TTs will | |
38 | * buffer low/full speed data so the host collects it at high speed. | |
39 | */ | |
40 | ||
41 | /*-------------------------------------------------------------------------*/ | |
42 | ||
43 | /* fill a qtd, returning how much of the buffer we were able to queue up */ | |
44 | ||
45 | static int | |
6dbd682b SR |
46 | qtd_fill(struct ehci_hcd *ehci, struct ehci_qtd *qtd, dma_addr_t buf, |
47 | size_t len, int token, int maxpacket) | |
1da177e4 LT |
48 | { |
49 | int i, count; | |
50 | u64 addr = buf; | |
51 | ||
52 | /* one buffer entry per 4K ... first might be short or unaligned */ | |
6dbd682b SR |
53 | qtd->hw_buf[0] = cpu_to_hc32(ehci, (u32)addr); |
54 | qtd->hw_buf_hi[0] = cpu_to_hc32(ehci, (u32)(addr >> 32)); | |
1da177e4 LT |
55 | count = 0x1000 - (buf & 0x0fff); /* rest of that page */ |
56 | if (likely (len < count)) /* ... iff needed */ | |
57 | count = len; | |
58 | else { | |
59 | buf += 0x1000; | |
60 | buf &= ~0x0fff; | |
61 | ||
62 | /* per-qtd limit: from 16K to 20K (best alignment) */ | |
63 | for (i = 1; count < len && i < 5; i++) { | |
64 | addr = buf; | |
6dbd682b SR |
65 | qtd->hw_buf[i] = cpu_to_hc32(ehci, (u32)addr); |
66 | qtd->hw_buf_hi[i] = cpu_to_hc32(ehci, | |
67 | (u32)(addr >> 32)); | |
1da177e4 LT |
68 | buf += 0x1000; |
69 | if ((count + 0x1000) < len) | |
70 | count += 0x1000; | |
71 | else | |
72 | count = len; | |
73 | } | |
74 | ||
75 | /* short packets may only terminate transfers */ | |
76 | if (count != len) | |
77 | count -= (count % maxpacket); | |
78 | } | |
6dbd682b | 79 | qtd->hw_token = cpu_to_hc32(ehci, (count << 16) | token); |
1da177e4 LT |
80 | qtd->length = count; |
81 | ||
82 | return count; | |
83 | } | |
84 | ||
85 | /*-------------------------------------------------------------------------*/ | |
86 | ||
87 | static inline void | |
88 | qh_update (struct ehci_hcd *ehci, struct ehci_qh *qh, struct ehci_qtd *qtd) | |
89 | { | |
90 | /* writes to an active overlay are unsafe */ | |
91 | BUG_ON(qh->qh_state != QH_STATE_IDLE); | |
92 | ||
6dbd682b SR |
93 | qh->hw_qtd_next = QTD_NEXT(ehci, qtd->qtd_dma); |
94 | qh->hw_alt_next = EHCI_LIST_END(ehci); | |
1da177e4 LT |
95 | |
96 | /* Except for control endpoints, we make hardware maintain data | |
97 | * toggle (like OHCI) ... here (re)initialize the toggle in the QH, | |
98 | * and set the pseudo-toggle in udev. Only usb_clear_halt() will | |
99 | * ever clear it. | |
100 | */ | |
6dbd682b | 101 | if (!(qh->hw_info1 & cpu_to_hc32(ehci, 1 << 14))) { |
1da177e4 LT |
102 | unsigned is_out, epnum; |
103 | ||
6dbd682b SR |
104 | is_out = !(qtd->hw_token & cpu_to_hc32(ehci, 1 << 8)); |
105 | epnum = (hc32_to_cpup(ehci, &qh->hw_info1) >> 8) & 0x0f; | |
1da177e4 | 106 | if (unlikely (!usb_gettoggle (qh->dev, epnum, is_out))) { |
6dbd682b | 107 | qh->hw_token &= ~cpu_to_hc32(ehci, QTD_TOGGLE); |
1da177e4 LT |
108 | usb_settoggle (qh->dev, epnum, is_out, 1); |
109 | } | |
110 | } | |
111 | ||
112 | /* HC must see latest qtd and qh data before we clear ACTIVE+HALT */ | |
113 | wmb (); | |
6dbd682b | 114 | qh->hw_token &= cpu_to_hc32(ehci, QTD_TOGGLE | QTD_STS_PING); |
1da177e4 LT |
115 | } |
116 | ||
117 | /* if it weren't for a common silicon quirk (writing the dummy into the qh | |
118 | * overlay, so qh->hw_token wrongly becomes inactive/halted), only fault | |
119 | * recovery (including urb dequeue) would need software changes to a QH... | |
120 | */ | |
121 | static void | |
122 | qh_refresh (struct ehci_hcd *ehci, struct ehci_qh *qh) | |
123 | { | |
124 | struct ehci_qtd *qtd; | |
125 | ||
126 | if (list_empty (&qh->qtd_list)) | |
127 | qtd = qh->dummy; | |
128 | else { | |
129 | qtd = list_entry (qh->qtd_list.next, | |
130 | struct ehci_qtd, qtd_list); | |
131 | /* first qtd may already be partially processed */ | |
6dbd682b | 132 | if (cpu_to_hc32(ehci, qtd->qtd_dma) == qh->hw_current) |
1da177e4 LT |
133 | qtd = NULL; |
134 | } | |
135 | ||
136 | if (qtd) | |
137 | qh_update (ehci, qh, qtd); | |
138 | } | |
139 | ||
140 | /*-------------------------------------------------------------------------*/ | |
141 | ||
14c04c0f | 142 | static int qtd_copy_status ( |
1da177e4 LT |
143 | struct ehci_hcd *ehci, |
144 | struct urb *urb, | |
145 | size_t length, | |
146 | u32 token | |
147 | ) | |
148 | { | |
14c04c0f AS |
149 | int status = -EINPROGRESS; |
150 | ||
1da177e4 LT |
151 | /* count IN/OUT bytes, not SETUP (even short packets) */ |
152 | if (likely (QTD_PID (token) != 2)) | |
153 | urb->actual_length += length - QTD_LENGTH (token); | |
154 | ||
155 | /* don't modify error codes */ | |
eb231054 | 156 | if (unlikely(urb->unlinked)) |
14c04c0f | 157 | return status; |
1da177e4 LT |
158 | |
159 | /* force cleanup after short read; not always an error */ | |
160 | if (unlikely (IS_SHORT_READ (token))) | |
14c04c0f | 161 | status = -EREMOTEIO; |
1da177e4 LT |
162 | |
163 | /* serious "can't proceed" faults reported by the hardware */ | |
164 | if (token & QTD_STS_HALT) { | |
165 | if (token & QTD_STS_BABBLE) { | |
166 | /* FIXME "must" disable babbling device's port too */ | |
14c04c0f | 167 | status = -EOVERFLOW; |
1da177e4 LT |
168 | } else if (token & QTD_STS_MMF) { |
169 | /* fs/ls interrupt xfer missed the complete-split */ | |
14c04c0f | 170 | status = -EPROTO; |
1da177e4 | 171 | } else if (token & QTD_STS_DBE) { |
14c04c0f | 172 | status = (QTD_PID (token) == 1) /* IN ? */ |
1da177e4 LT |
173 | ? -ENOSR /* hc couldn't read data */ |
174 | : -ECOMM; /* hc couldn't write data */ | |
175 | } else if (token & QTD_STS_XACT) { | |
176 | /* timeout, bad crc, wrong PID, etc; retried */ | |
177 | if (QTD_CERR (token)) | |
14c04c0f | 178 | status = -EPIPE; |
1da177e4 LT |
179 | else { |
180 | ehci_dbg (ehci, "devpath %s ep%d%s 3strikes\n", | |
181 | urb->dev->devpath, | |
182 | usb_pipeendpoint (urb->pipe), | |
183 | usb_pipein (urb->pipe) ? "in" : "out"); | |
14c04c0f | 184 | status = -EPROTO; |
1da177e4 LT |
185 | } |
186 | /* CERR nonzero + no errors + halt --> stall */ | |
187 | } else if (QTD_CERR (token)) | |
14c04c0f | 188 | status = -EPIPE; |
1da177e4 | 189 | else /* unknown */ |
14c04c0f | 190 | status = -EPROTO; |
1da177e4 LT |
191 | |
192 | ehci_vdbg (ehci, | |
193 | "dev%d ep%d%s qtd token %08x --> status %d\n", | |
194 | usb_pipedevice (urb->pipe), | |
195 | usb_pipeendpoint (urb->pipe), | |
196 | usb_pipein (urb->pipe) ? "in" : "out", | |
14c04c0f | 197 | token, status); |
1da177e4 LT |
198 | |
199 | /* if async CSPLIT failed, try cleaning out the TT buffer */ | |
14c04c0f | 200 | if (status != -EPIPE |
340ba5f9 DB |
201 | && urb->dev->tt |
202 | && !usb_pipeint(urb->pipe) | |
1da177e4 LT |
203 | && ((token & QTD_STS_MMF) != 0 |
204 | || QTD_CERR(token) == 0) | |
205 | && (!ehci_is_TDI(ehci) | |
53bd6a60 | 206 | || urb->dev->tt->hub != |
1da177e4 LT |
207 | ehci_to_hcd(ehci)->self.root_hub)) { |
208 | #ifdef DEBUG | |
209 | struct usb_device *tt = urb->dev->tt->hub; | |
210 | dev_dbg (&tt->dev, | |
211 | "clear tt buffer port %d, a%d ep%d t%08x\n", | |
212 | urb->dev->ttport, urb->dev->devnum, | |
213 | usb_pipeendpoint (urb->pipe), token); | |
214 | #endif /* DEBUG */ | |
340ba5f9 DB |
215 | /* REVISIT ARC-derived cores don't clear the root |
216 | * hub TT buffer in this way... | |
217 | */ | |
1da177e4 LT |
218 | usb_hub_tt_clear_buffer (urb->dev, urb->pipe); |
219 | } | |
220 | } | |
14c04c0f AS |
221 | |
222 | return status; | |
1da177e4 LT |
223 | } |
224 | ||
225 | static void | |
14c04c0f | 226 | ehci_urb_done(struct ehci_hcd *ehci, struct urb *urb, int status) |
1da177e4 LT |
227 | __releases(ehci->lock) |
228 | __acquires(ehci->lock) | |
229 | { | |
230 | if (likely (urb->hcpriv != NULL)) { | |
231 | struct ehci_qh *qh = (struct ehci_qh *) urb->hcpriv; | |
232 | ||
233 | /* S-mask in a QH means it's an interrupt urb */ | |
6dbd682b | 234 | if ((qh->hw_info2 & cpu_to_hc32(ehci, QH_SMASK)) != 0) { |
1da177e4 LT |
235 | |
236 | /* ... update hc-wide periodic stats (for usbfs) */ | |
237 | ehci_to_hcd(ehci)->self.bandwidth_int_reqs--; | |
238 | } | |
239 | qh_put (qh); | |
240 | } | |
241 | ||
eb231054 AS |
242 | if (unlikely(urb->unlinked)) { |
243 | COUNT(ehci->stats.unlink); | |
244 | } else { | |
14c04c0f AS |
245 | if (likely(status == -EINPROGRESS)) |
246 | status = 0; | |
eb231054 | 247 | COUNT(ehci->stats.complete); |
1da177e4 | 248 | } |
1da177e4 LT |
249 | |
250 | #ifdef EHCI_URB_TRACE | |
251 | ehci_dbg (ehci, | |
252 | "%s %s urb %p ep%d%s status %d len %d/%d\n", | |
253 | __FUNCTION__, urb->dev->devpath, urb, | |
254 | usb_pipeendpoint (urb->pipe), | |
255 | usb_pipein (urb->pipe) ? "in" : "out", | |
14c04c0f | 256 | status, |
1da177e4 LT |
257 | urb->actual_length, urb->transfer_buffer_length); |
258 | #endif | |
259 | ||
260 | /* complete() can reenter this HCD */ | |
e9df41c5 | 261 | usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb); |
1da177e4 | 262 | spin_unlock (&ehci->lock); |
4a00027d | 263 | usb_hcd_giveback_urb(ehci_to_hcd(ehci), urb, status); |
1da177e4 LT |
264 | spin_lock (&ehci->lock); |
265 | } | |
266 | ||
267 | static void start_unlink_async (struct ehci_hcd *ehci, struct ehci_qh *qh); | |
268 | static void unlink_async (struct ehci_hcd *ehci, struct ehci_qh *qh); | |
269 | ||
270 | static void intr_deschedule (struct ehci_hcd *ehci, struct ehci_qh *qh); | |
271 | static int qh_schedule (struct ehci_hcd *ehci, struct ehci_qh *qh); | |
272 | ||
273 | /* | |
274 | * Process and free completed qtds for a qh, returning URBs to drivers. | |
275 | * Chases up to qh->hw_current. Returns number of completions called, | |
276 | * indicating how much "real" work we did. | |
277 | */ | |
1da177e4 | 278 | static unsigned |
7d12e780 | 279 | qh_completions (struct ehci_hcd *ehci, struct ehci_qh *qh) |
1da177e4 LT |
280 | { |
281 | struct ehci_qtd *last = NULL, *end = qh->dummy; | |
282 | struct list_head *entry, *tmp; | |
14c04c0f | 283 | int last_status = -EINPROGRESS; |
1da177e4 LT |
284 | int stopped; |
285 | unsigned count = 0; | |
286 | int do_status = 0; | |
287 | u8 state; | |
6dbd682b | 288 | u32 halt = HALT_BIT(ehci); |
1da177e4 LT |
289 | |
290 | if (unlikely (list_empty (&qh->qtd_list))) | |
291 | return count; | |
292 | ||
293 | /* completions (or tasks on other cpus) must never clobber HALT | |
294 | * till we've gone through and cleaned everything up, even when | |
295 | * they add urbs to this qh's queue or mark them for unlinking. | |
296 | * | |
297 | * NOTE: unlinking expects to be done in queue order. | |
298 | */ | |
299 | state = qh->qh_state; | |
300 | qh->qh_state = QH_STATE_COMPLETING; | |
301 | stopped = (state == QH_STATE_IDLE); | |
302 | ||
303 | /* remove de-activated QTDs from front of queue. | |
304 | * after faults (including short reads), cleanup this urb | |
305 | * then let the queue advance. | |
306 | * if queue is stopped, handles unlinks. | |
307 | */ | |
308 | list_for_each_safe (entry, tmp, &qh->qtd_list) { | |
309 | struct ehci_qtd *qtd; | |
310 | struct urb *urb; | |
311 | u32 token = 0; | |
14c04c0f | 312 | int qtd_status; |
1da177e4 LT |
313 | |
314 | qtd = list_entry (entry, struct ehci_qtd, qtd_list); | |
315 | urb = qtd->urb; | |
316 | ||
317 | /* clean up any state from previous QTD ...*/ | |
318 | if (last) { | |
319 | if (likely (last->urb != urb)) { | |
14c04c0f | 320 | ehci_urb_done(ehci, last->urb, last_status); |
1da177e4 LT |
321 | count++; |
322 | } | |
323 | ehci_qtd_free (ehci, last); | |
324 | last = NULL; | |
14c04c0f | 325 | last_status = -EINPROGRESS; |
1da177e4 LT |
326 | } |
327 | ||
328 | /* ignore urbs submitted during completions we reported */ | |
329 | if (qtd == end) | |
330 | break; | |
331 | ||
332 | /* hardware copies qtd out of qh overlay */ | |
333 | rmb (); | |
6dbd682b | 334 | token = hc32_to_cpu(ehci, qtd->hw_token); |
1da177e4 LT |
335 | |
336 | /* always clean up qtds the hc de-activated */ | |
337 | if ((token & QTD_STS_ACTIVE) == 0) { | |
338 | ||
339 | if ((token & QTD_STS_HALT) != 0) { | |
340 | stopped = 1; | |
341 | ||
342 | /* magic dummy for some short reads; qh won't advance. | |
343 | * that silicon quirk can kick in with this dummy too. | |
344 | */ | |
345 | } else if (IS_SHORT_READ (token) | |
6dbd682b SR |
346 | && !(qtd->hw_alt_next |
347 | & EHCI_LIST_END(ehci))) { | |
1da177e4 LT |
348 | stopped = 1; |
349 | goto halt; | |
350 | } | |
351 | ||
352 | /* stop scanning when we reach qtds the hc is using */ | |
353 | } else if (likely (!stopped | |
354 | && HC_IS_RUNNING (ehci_to_hcd(ehci)->state))) { | |
355 | break; | |
356 | ||
357 | } else { | |
358 | stopped = 1; | |
359 | ||
360 | if (unlikely (!HC_IS_RUNNING (ehci_to_hcd(ehci)->state))) | |
14c04c0f | 361 | last_status = -ESHUTDOWN; |
1da177e4 LT |
362 | |
363 | /* ignore active urbs unless some previous qtd | |
364 | * for the urb faulted (including short read) or | |
365 | * its urb was canceled. we may patch qh or qtds. | |
366 | */ | |
14c04c0f | 367 | if (likely(last_status == -EINPROGRESS && |
eb231054 | 368 | !urb->unlinked)) |
1da177e4 | 369 | continue; |
53bd6a60 | 370 | |
1da177e4 LT |
371 | /* issue status after short control reads */ |
372 | if (unlikely (do_status != 0) | |
373 | && QTD_PID (token) == 0 /* OUT */) { | |
374 | do_status = 0; | |
375 | continue; | |
376 | } | |
377 | ||
378 | /* token in overlay may be most current */ | |
379 | if (state == QH_STATE_IDLE | |
6dbd682b | 380 | && cpu_to_hc32(ehci, qtd->qtd_dma) |
1da177e4 | 381 | == qh->hw_current) |
6dbd682b | 382 | token = hc32_to_cpu(ehci, qh->hw_token); |
1da177e4 LT |
383 | |
384 | /* force halt for unlinked or blocked qh, so we'll | |
385 | * patch the qh later and so that completions can't | |
386 | * activate it while we "know" it's stopped. | |
387 | */ | |
6dbd682b | 388 | if ((halt & qh->hw_token) == 0) { |
1da177e4 | 389 | halt: |
6dbd682b | 390 | qh->hw_token |= halt; |
1da177e4 LT |
391 | wmb (); |
392 | } | |
393 | } | |
53bd6a60 | 394 | |
1da177e4 | 395 | /* remove it from the queue */ |
14c04c0f AS |
396 | qtd_status = qtd_copy_status(ehci, urb, qtd->length, token); |
397 | if (unlikely(qtd_status == -EREMOTEIO)) { | |
eb231054 AS |
398 | do_status = (!urb->unlinked && |
399 | usb_pipecontrol(urb->pipe)); | |
14c04c0f | 400 | qtd_status = 0; |
b0d9efba | 401 | } |
14c04c0f AS |
402 | if (likely(last_status == -EINPROGRESS)) |
403 | last_status = qtd_status; | |
1da177e4 LT |
404 | |
405 | if (stopped && qtd->qtd_list.prev != &qh->qtd_list) { | |
406 | last = list_entry (qtd->qtd_list.prev, | |
407 | struct ehci_qtd, qtd_list); | |
408 | last->hw_next = qtd->hw_next; | |
409 | } | |
410 | list_del (&qtd->qtd_list); | |
411 | last = qtd; | |
412 | } | |
413 | ||
414 | /* last urb's completion might still need calling */ | |
415 | if (likely (last != NULL)) { | |
14c04c0f | 416 | ehci_urb_done(ehci, last->urb, last_status); |
1da177e4 LT |
417 | count++; |
418 | ehci_qtd_free (ehci, last); | |
419 | } | |
420 | ||
421 | /* restore original state; caller must unlink or relink */ | |
422 | qh->qh_state = state; | |
423 | ||
424 | /* be sure the hardware's done with the qh before refreshing | |
425 | * it after fault cleanup, or recovering from silicon wrongly | |
426 | * overlaying the dummy qtd (which reduces DMA chatter). | |
427 | */ | |
6dbd682b | 428 | if (stopped != 0 || qh->hw_qtd_next == EHCI_LIST_END(ehci)) { |
1da177e4 LT |
429 | switch (state) { |
430 | case QH_STATE_IDLE: | |
431 | qh_refresh(ehci, qh); | |
432 | break; | |
433 | case QH_STATE_LINKED: | |
434 | /* should be rare for periodic transfers, | |
435 | * except maybe high bandwidth ... | |
436 | */ | |
6dbd682b | 437 | if ((cpu_to_hc32(ehci, QH_SMASK) |
7dedacf4 | 438 | & qh->hw_info2) != 0) { |
1da177e4 LT |
439 | intr_deschedule (ehci, qh); |
440 | (void) qh_schedule (ehci, qh); | |
441 | } else | |
442 | unlink_async (ehci, qh); | |
443 | break; | |
444 | /* otherwise, unlink already started */ | |
445 | } | |
446 | } | |
447 | ||
448 | return count; | |
449 | } | |
450 | ||
451 | /*-------------------------------------------------------------------------*/ | |
452 | ||
453 | // high bandwidth multiplier, as encoded in highspeed endpoint descriptors | |
454 | #define hb_mult(wMaxPacketSize) (1 + (((wMaxPacketSize) >> 11) & 0x03)) | |
455 | // ... and packet size, for any kind of endpoint descriptor | |
456 | #define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff) | |
457 | ||
458 | /* | |
459 | * reverse of qh_urb_transaction: free a list of TDs. | |
460 | * used for cleanup after errors, before HC sees an URB's TDs. | |
461 | */ | |
462 | static void qtd_list_free ( | |
463 | struct ehci_hcd *ehci, | |
464 | struct urb *urb, | |
465 | struct list_head *qtd_list | |
466 | ) { | |
467 | struct list_head *entry, *temp; | |
468 | ||
469 | list_for_each_safe (entry, temp, qtd_list) { | |
470 | struct ehci_qtd *qtd; | |
471 | ||
472 | qtd = list_entry (entry, struct ehci_qtd, qtd_list); | |
473 | list_del (&qtd->qtd_list); | |
474 | ehci_qtd_free (ehci, qtd); | |
475 | } | |
476 | } | |
477 | ||
478 | /* | |
479 | * create a list of filled qtds for this URB; won't link into qh. | |
480 | */ | |
481 | static struct list_head * | |
482 | qh_urb_transaction ( | |
483 | struct ehci_hcd *ehci, | |
484 | struct urb *urb, | |
485 | struct list_head *head, | |
55016f10 | 486 | gfp_t flags |
1da177e4 LT |
487 | ) { |
488 | struct ehci_qtd *qtd, *qtd_prev; | |
489 | dma_addr_t buf; | |
490 | int len, maxpacket; | |
491 | int is_input; | |
492 | u32 token; | |
493 | ||
494 | /* | |
495 | * URBs map to sequences of QTDs: one logical transaction | |
496 | */ | |
497 | qtd = ehci_qtd_alloc (ehci, flags); | |
498 | if (unlikely (!qtd)) | |
499 | return NULL; | |
500 | list_add_tail (&qtd->qtd_list, head); | |
501 | qtd->urb = urb; | |
502 | ||
503 | token = QTD_STS_ACTIVE; | |
504 | token |= (EHCI_TUNE_CERR << 10); | |
505 | /* for split transactions, SplitXState initialized to zero */ | |
506 | ||
507 | len = urb->transfer_buffer_length; | |
508 | is_input = usb_pipein (urb->pipe); | |
509 | if (usb_pipecontrol (urb->pipe)) { | |
510 | /* SETUP pid */ | |
6dbd682b SR |
511 | qtd_fill(ehci, qtd, urb->setup_dma, |
512 | sizeof (struct usb_ctrlrequest), | |
513 | token | (2 /* "setup" */ << 8), 8); | |
1da177e4 LT |
514 | |
515 | /* ... and always at least one more pid */ | |
516 | token ^= QTD_TOGGLE; | |
517 | qtd_prev = qtd; | |
518 | qtd = ehci_qtd_alloc (ehci, flags); | |
519 | if (unlikely (!qtd)) | |
520 | goto cleanup; | |
521 | qtd->urb = urb; | |
6dbd682b | 522 | qtd_prev->hw_next = QTD_NEXT(ehci, qtd->qtd_dma); |
1da177e4 | 523 | list_add_tail (&qtd->qtd_list, head); |
6912354a AS |
524 | |
525 | /* for zero length DATA stages, STATUS is always IN */ | |
526 | if (len == 0) | |
527 | token |= (1 /* "in" */ << 8); | |
53bd6a60 | 528 | } |
1da177e4 LT |
529 | |
530 | /* | |
531 | * data transfer stage: buffer setup | |
532 | */ | |
6912354a | 533 | buf = urb->transfer_dma; |
1da177e4 | 534 | |
6912354a | 535 | if (is_input) |
1da177e4 LT |
536 | token |= (1 /* "in" */ << 8); |
537 | /* else it's already initted to "out" pid (0 << 8) */ | |
538 | ||
539 | maxpacket = max_packet(usb_maxpacket(urb->dev, urb->pipe, !is_input)); | |
540 | ||
541 | /* | |
542 | * buffer gets wrapped in one or more qtds; | |
543 | * last one may be "short" (including zero len) | |
544 | * and may serve as a control status ack | |
545 | */ | |
546 | for (;;) { | |
547 | int this_qtd_len; | |
548 | ||
6dbd682b | 549 | this_qtd_len = qtd_fill(ehci, qtd, buf, len, token, maxpacket); |
1da177e4 LT |
550 | len -= this_qtd_len; |
551 | buf += this_qtd_len; | |
552 | if (is_input) | |
553 | qtd->hw_alt_next = ehci->async->hw_alt_next; | |
554 | ||
555 | /* qh makes control packets use qtd toggle; maybe switch it */ | |
556 | if ((maxpacket & (this_qtd_len + (maxpacket - 1))) == 0) | |
557 | token ^= QTD_TOGGLE; | |
558 | ||
559 | if (likely (len <= 0)) | |
560 | break; | |
561 | ||
562 | qtd_prev = qtd; | |
563 | qtd = ehci_qtd_alloc (ehci, flags); | |
564 | if (unlikely (!qtd)) | |
565 | goto cleanup; | |
566 | qtd->urb = urb; | |
6dbd682b | 567 | qtd_prev->hw_next = QTD_NEXT(ehci, qtd->qtd_dma); |
1da177e4 LT |
568 | list_add_tail (&qtd->qtd_list, head); |
569 | } | |
570 | ||
571 | /* unless the bulk/interrupt caller wants a chance to clean | |
572 | * up after short reads, hc should advance qh past this urb | |
573 | */ | |
574 | if (likely ((urb->transfer_flags & URB_SHORT_NOT_OK) == 0 | |
575 | || usb_pipecontrol (urb->pipe))) | |
6dbd682b | 576 | qtd->hw_alt_next = EHCI_LIST_END(ehci); |
1da177e4 LT |
577 | |
578 | /* | |
579 | * control requests may need a terminating data "status" ack; | |
580 | * bulk ones may need a terminating short packet (zero length). | |
581 | */ | |
6912354a | 582 | if (likely (urb->transfer_buffer_length != 0)) { |
1da177e4 LT |
583 | int one_more = 0; |
584 | ||
585 | if (usb_pipecontrol (urb->pipe)) { | |
586 | one_more = 1; | |
587 | token ^= 0x0100; /* "in" <--> "out" */ | |
588 | token |= QTD_TOGGLE; /* force DATA1 */ | |
589 | } else if (usb_pipebulk (urb->pipe) | |
590 | && (urb->transfer_flags & URB_ZERO_PACKET) | |
591 | && !(urb->transfer_buffer_length % maxpacket)) { | |
592 | one_more = 1; | |
593 | } | |
594 | if (one_more) { | |
595 | qtd_prev = qtd; | |
596 | qtd = ehci_qtd_alloc (ehci, flags); | |
597 | if (unlikely (!qtd)) | |
598 | goto cleanup; | |
599 | qtd->urb = urb; | |
6dbd682b | 600 | qtd_prev->hw_next = QTD_NEXT(ehci, qtd->qtd_dma); |
1da177e4 LT |
601 | list_add_tail (&qtd->qtd_list, head); |
602 | ||
603 | /* never any data in such packets */ | |
6dbd682b | 604 | qtd_fill(ehci, qtd, 0, 0, token, 0); |
1da177e4 LT |
605 | } |
606 | } | |
607 | ||
608 | /* by default, enable interrupt on urb completion */ | |
609 | if (likely (!(urb->transfer_flags & URB_NO_INTERRUPT))) | |
6dbd682b | 610 | qtd->hw_token |= cpu_to_hc32(ehci, QTD_IOC); |
1da177e4 LT |
611 | return head; |
612 | ||
613 | cleanup: | |
614 | qtd_list_free (ehci, urb, head); | |
615 | return NULL; | |
616 | } | |
617 | ||
618 | /*-------------------------------------------------------------------------*/ | |
619 | ||
620 | // Would be best to create all qh's from config descriptors, | |
621 | // when each interface/altsetting is established. Unlink | |
622 | // any previous qh and cancel its urbs first; endpoints are | |
623 | // implicitly reset then (data toggle too). | |
624 | // That'd mean updating how usbcore talks to HCDs. (2.7?) | |
625 | ||
626 | ||
627 | /* | |
628 | * Each QH holds a qtd list; a QH is used for everything except iso. | |
629 | * | |
630 | * For interrupt urbs, the scheduler must set the microframe scheduling | |
631 | * mask(s) each time the QH gets scheduled. For highspeed, that's | |
632 | * just one microframe in the s-mask. For split interrupt transactions | |
633 | * there are additional complications: c-mask, maybe FSTNs. | |
634 | */ | |
635 | static struct ehci_qh * | |
636 | qh_make ( | |
637 | struct ehci_hcd *ehci, | |
638 | struct urb *urb, | |
55016f10 | 639 | gfp_t flags |
1da177e4 LT |
640 | ) { |
641 | struct ehci_qh *qh = ehci_qh_alloc (ehci, flags); | |
642 | u32 info1 = 0, info2 = 0; | |
643 | int is_input, type; | |
644 | int maxp = 0; | |
340ba5f9 | 645 | struct usb_tt *tt = urb->dev->tt; |
1da177e4 LT |
646 | |
647 | if (!qh) | |
648 | return qh; | |
649 | ||
650 | /* | |
651 | * init endpoint/device data for this QH | |
652 | */ | |
653 | info1 |= usb_pipeendpoint (urb->pipe) << 8; | |
654 | info1 |= usb_pipedevice (urb->pipe) << 0; | |
655 | ||
656 | is_input = usb_pipein (urb->pipe); | |
657 | type = usb_pipetype (urb->pipe); | |
658 | maxp = usb_maxpacket (urb->dev, urb->pipe, !is_input); | |
659 | ||
660 | /* Compute interrupt scheduling parameters just once, and save. | |
661 | * - allowing for high bandwidth, how many nsec/uframe are used? | |
662 | * - split transactions need a second CSPLIT uframe; same question | |
663 | * - splits also need a schedule gap (for full/low speed I/O) | |
664 | * - qh has a polling interval | |
665 | * | |
666 | * For control/bulk requests, the HC or TT handles these. | |
667 | */ | |
668 | if (type == PIPE_INTERRUPT) { | |
340ba5f9 DB |
669 | qh->usecs = NS_TO_US(usb_calc_bus_time(USB_SPEED_HIGH, |
670 | is_input, 0, | |
671 | hb_mult(maxp) * max_packet(maxp))); | |
1da177e4 LT |
672 | qh->start = NO_FRAME; |
673 | ||
674 | if (urb->dev->speed == USB_SPEED_HIGH) { | |
675 | qh->c_usecs = 0; | |
676 | qh->gap_uf = 0; | |
677 | ||
678 | qh->period = urb->interval >> 3; | |
679 | if (qh->period == 0 && urb->interval != 1) { | |
680 | /* NOTE interval 2 or 4 uframes could work. | |
681 | * But interval 1 scheduling is simpler, and | |
682 | * includes high bandwidth. | |
683 | */ | |
684 | dbg ("intr period %d uframes, NYET!", | |
685 | urb->interval); | |
686 | goto done; | |
687 | } | |
688 | } else { | |
d0384200 DB |
689 | int think_time; |
690 | ||
1da177e4 LT |
691 | /* gap is f(FS/LS transfer times) */ |
692 | qh->gap_uf = 1 + usb_calc_bus_time (urb->dev->speed, | |
693 | is_input, 0, maxp) / (125 * 1000); | |
694 | ||
695 | /* FIXME this just approximates SPLIT/CSPLIT times */ | |
696 | if (is_input) { // SPLIT, gap, CSPLIT+DATA | |
697 | qh->c_usecs = qh->usecs + HS_USECS (0); | |
698 | qh->usecs = HS_USECS (1); | |
699 | } else { // SPLIT+DATA, gap, CSPLIT | |
700 | qh->usecs += HS_USECS (1); | |
701 | qh->c_usecs = HS_USECS (0); | |
702 | } | |
703 | ||
d0384200 DB |
704 | think_time = tt ? tt->think_time : 0; |
705 | qh->tt_usecs = NS_TO_US (think_time + | |
706 | usb_calc_bus_time (urb->dev->speed, | |
707 | is_input, 0, max_packet (maxp))); | |
1da177e4 LT |
708 | qh->period = urb->interval; |
709 | } | |
710 | } | |
711 | ||
712 | /* support for tt scheduling, and access to toggles */ | |
6a8e87b2 | 713 | qh->dev = urb->dev; |
1da177e4 LT |
714 | |
715 | /* using TT? */ | |
716 | switch (urb->dev->speed) { | |
717 | case USB_SPEED_LOW: | |
718 | info1 |= (1 << 12); /* EPS "low" */ | |
719 | /* FALL THROUGH */ | |
720 | ||
721 | case USB_SPEED_FULL: | |
722 | /* EPS 0 means "full" */ | |
723 | if (type != PIPE_INTERRUPT) | |
724 | info1 |= (EHCI_TUNE_RL_TT << 28); | |
725 | if (type == PIPE_CONTROL) { | |
726 | info1 |= (1 << 27); /* for TT */ | |
727 | info1 |= 1 << 14; /* toggle from qtd */ | |
728 | } | |
729 | info1 |= maxp << 16; | |
730 | ||
731 | info2 |= (EHCI_TUNE_MULT_TT << 30); | |
8cd42e97 KG |
732 | |
733 | /* Some Freescale processors have an erratum in which the | |
734 | * port number in the queue head was 0..N-1 instead of 1..N. | |
735 | */ | |
736 | if (ehci_has_fsl_portno_bug(ehci)) | |
737 | info2 |= (urb->dev->ttport-1) << 23; | |
738 | else | |
739 | info2 |= urb->dev->ttport << 23; | |
1da177e4 LT |
740 | |
741 | /* set the address of the TT; for TDI's integrated | |
742 | * root hub tt, leave it zeroed. | |
743 | */ | |
340ba5f9 DB |
744 | if (tt && tt->hub != ehci_to_hcd(ehci)->self.root_hub) |
745 | info2 |= tt->hub->devnum << 16; | |
1da177e4 LT |
746 | |
747 | /* NOTE: if (PIPE_INTERRUPT) { scheduler sets c-mask } */ | |
748 | ||
749 | break; | |
750 | ||
751 | case USB_SPEED_HIGH: /* no TT involved */ | |
752 | info1 |= (2 << 12); /* EPS "high" */ | |
753 | if (type == PIPE_CONTROL) { | |
754 | info1 |= (EHCI_TUNE_RL_HS << 28); | |
755 | info1 |= 64 << 16; /* usb2 fixed maxpacket */ | |
756 | info1 |= 1 << 14; /* toggle from qtd */ | |
757 | info2 |= (EHCI_TUNE_MULT_HS << 30); | |
758 | } else if (type == PIPE_BULK) { | |
759 | info1 |= (EHCI_TUNE_RL_HS << 28); | |
760 | info1 |= 512 << 16; /* usb2 fixed maxpacket */ | |
761 | info2 |= (EHCI_TUNE_MULT_HS << 30); | |
762 | } else { /* PIPE_INTERRUPT */ | |
763 | info1 |= max_packet (maxp) << 16; | |
764 | info2 |= hb_mult (maxp) << 30; | |
765 | } | |
766 | break; | |
767 | default: | |
53bd6a60 | 768 | dbg ("bogus dev %p speed %d", urb->dev, urb->dev->speed); |
1da177e4 LT |
769 | done: |
770 | qh_put (qh); | |
771 | return NULL; | |
772 | } | |
773 | ||
774 | /* NOTE: if (PIPE_INTERRUPT) { scheduler sets s-mask } */ | |
775 | ||
776 | /* init as live, toggle clear, advance to dummy */ | |
777 | qh->qh_state = QH_STATE_IDLE; | |
6dbd682b SR |
778 | qh->hw_info1 = cpu_to_hc32(ehci, info1); |
779 | qh->hw_info2 = cpu_to_hc32(ehci, info2); | |
1da177e4 LT |
780 | usb_settoggle (urb->dev, usb_pipeendpoint (urb->pipe), !is_input, 1); |
781 | qh_refresh (ehci, qh); | |
782 | return qh; | |
783 | } | |
784 | ||
785 | /*-------------------------------------------------------------------------*/ | |
786 | ||
787 | /* move qh (and its qtds) onto async queue; maybe enable queue. */ | |
788 | ||
789 | static void qh_link_async (struct ehci_hcd *ehci, struct ehci_qh *qh) | |
790 | { | |
6dbd682b | 791 | __hc32 dma = QH_NEXT(ehci, qh->qh_dma); |
1da177e4 LT |
792 | struct ehci_qh *head; |
793 | ||
794 | /* (re)start the async schedule? */ | |
795 | head = ehci->async; | |
796 | timer_action_done (ehci, TIMER_ASYNC_OFF); | |
797 | if (!head->qh_next.qh) { | |
083522d7 | 798 | u32 cmd = ehci_readl(ehci, &ehci->regs->command); |
1da177e4 LT |
799 | |
800 | if (!(cmd & CMD_ASE)) { | |
801 | /* in case a clear of CMD_ASE didn't take yet */ | |
083522d7 BH |
802 | (void)handshake(ehci, &ehci->regs->status, |
803 | STS_ASS, 0, 150); | |
1da177e4 | 804 | cmd |= CMD_ASE | CMD_RUN; |
083522d7 | 805 | ehci_writel(ehci, cmd, &ehci->regs->command); |
1da177e4 LT |
806 | ehci_to_hcd(ehci)->state = HC_STATE_RUNNING; |
807 | /* posted write need not be known to HC yet ... */ | |
808 | } | |
809 | } | |
810 | ||
811 | /* clear halt and/or toggle; and maybe recover from silicon quirk */ | |
812 | if (qh->qh_state == QH_STATE_IDLE) | |
813 | qh_refresh (ehci, qh); | |
814 | ||
815 | /* splice right after start */ | |
816 | qh->qh_next = head->qh_next; | |
817 | qh->hw_next = head->hw_next; | |
818 | wmb (); | |
819 | ||
820 | head->qh_next.qh = qh; | |
821 | head->hw_next = dma; | |
822 | ||
823 | qh->qh_state = QH_STATE_LINKED; | |
824 | /* qtd completions reported later by interrupt */ | |
825 | } | |
826 | ||
827 | /*-------------------------------------------------------------------------*/ | |
828 | ||
1da177e4 LT |
829 | /* |
830 | * For control/bulk/interrupt, return QH with these TDs appended. | |
831 | * Allocates and initializes the QH if necessary. | |
832 | * Returns null if it can't allocate a QH it needs to. | |
833 | * If the QH has TDs (urbs) already, that's great. | |
834 | */ | |
835 | static struct ehci_qh *qh_append_tds ( | |
836 | struct ehci_hcd *ehci, | |
837 | struct urb *urb, | |
838 | struct list_head *qtd_list, | |
839 | int epnum, | |
840 | void **ptr | |
841 | ) | |
842 | { | |
843 | struct ehci_qh *qh = NULL; | |
6dbd682b | 844 | u32 qh_addr_mask = cpu_to_hc32(ehci, 0x7f); |
1da177e4 LT |
845 | |
846 | qh = (struct ehci_qh *) *ptr; | |
847 | if (unlikely (qh == NULL)) { | |
848 | /* can't sleep here, we have ehci->lock... */ | |
849 | qh = qh_make (ehci, urb, GFP_ATOMIC); | |
850 | *ptr = qh; | |
851 | } | |
852 | if (likely (qh != NULL)) { | |
853 | struct ehci_qtd *qtd; | |
854 | ||
855 | if (unlikely (list_empty (qtd_list))) | |
856 | qtd = NULL; | |
857 | else | |
858 | qtd = list_entry (qtd_list->next, struct ehci_qtd, | |
859 | qtd_list); | |
860 | ||
861 | /* control qh may need patching ... */ | |
862 | if (unlikely (epnum == 0)) { | |
863 | ||
864 | /* usb_reset_device() briefly reverts to address 0 */ | |
865 | if (usb_pipedevice (urb->pipe) == 0) | |
6dbd682b | 866 | qh->hw_info1 &= ~qh_addr_mask; |
1da177e4 LT |
867 | } |
868 | ||
869 | /* just one way to queue requests: swap with the dummy qtd. | |
870 | * only hc or qh_refresh() ever modify the overlay. | |
871 | */ | |
872 | if (likely (qtd != NULL)) { | |
873 | struct ehci_qtd *dummy; | |
874 | dma_addr_t dma; | |
6dbd682b | 875 | __hc32 token; |
1da177e4 LT |
876 | |
877 | /* to avoid racing the HC, use the dummy td instead of | |
878 | * the first td of our list (becomes new dummy). both | |
879 | * tds stay deactivated until we're done, when the | |
880 | * HC is allowed to fetch the old dummy (4.10.2). | |
881 | */ | |
882 | token = qtd->hw_token; | |
6dbd682b | 883 | qtd->hw_token = HALT_BIT(ehci); |
1da177e4 LT |
884 | wmb (); |
885 | dummy = qh->dummy; | |
886 | ||
887 | dma = dummy->qtd_dma; | |
888 | *dummy = *qtd; | |
889 | dummy->qtd_dma = dma; | |
890 | ||
891 | list_del (&qtd->qtd_list); | |
892 | list_add (&dummy->qtd_list, qtd_list); | |
893 | __list_splice (qtd_list, qh->qtd_list.prev); | |
894 | ||
6dbd682b | 895 | ehci_qtd_init(ehci, qtd, qtd->qtd_dma); |
1da177e4 LT |
896 | qh->dummy = qtd; |
897 | ||
898 | /* hc must see the new dummy at list end */ | |
899 | dma = qtd->qtd_dma; | |
900 | qtd = list_entry (qh->qtd_list.prev, | |
901 | struct ehci_qtd, qtd_list); | |
6dbd682b | 902 | qtd->hw_next = QTD_NEXT(ehci, dma); |
1da177e4 LT |
903 | |
904 | /* let the hc process these next qtds */ | |
905 | wmb (); | |
906 | dummy->hw_token = token; | |
907 | ||
908 | urb->hcpriv = qh_get (qh); | |
909 | } | |
910 | } | |
911 | return qh; | |
912 | } | |
913 | ||
914 | /*-------------------------------------------------------------------------*/ | |
915 | ||
916 | static int | |
917 | submit_async ( | |
918 | struct ehci_hcd *ehci, | |
1da177e4 LT |
919 | struct urb *urb, |
920 | struct list_head *qtd_list, | |
55016f10 | 921 | gfp_t mem_flags |
1da177e4 LT |
922 | ) { |
923 | struct ehci_qtd *qtd; | |
924 | int epnum; | |
925 | unsigned long flags; | |
926 | struct ehci_qh *qh = NULL; | |
e9df41c5 | 927 | int rc; |
1da177e4 LT |
928 | |
929 | qtd = list_entry (qtd_list->next, struct ehci_qtd, qtd_list); | |
e9df41c5 | 930 | epnum = urb->ep->desc.bEndpointAddress; |
1da177e4 LT |
931 | |
932 | #ifdef EHCI_URB_TRACE | |
933 | ehci_dbg (ehci, | |
934 | "%s %s urb %p ep%d%s len %d, qtd %p [qh %p]\n", | |
935 | __FUNCTION__, urb->dev->devpath, urb, | |
936 | epnum & 0x0f, (epnum & USB_DIR_IN) ? "in" : "out", | |
937 | urb->transfer_buffer_length, | |
e9df41c5 | 938 | qtd, urb->ep->hcpriv); |
1da177e4 LT |
939 | #endif |
940 | ||
941 | spin_lock_irqsave (&ehci->lock, flags); | |
8de98402 BH |
942 | if (unlikely(!test_bit(HCD_FLAG_HW_ACCESSIBLE, |
943 | &ehci_to_hcd(ehci)->flags))) { | |
944 | rc = -ESHUTDOWN; | |
945 | goto done; | |
946 | } | |
e9df41c5 AS |
947 | rc = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb); |
948 | if (unlikely(rc)) | |
949 | goto done; | |
8de98402 | 950 | |
e9df41c5 | 951 | qh = qh_append_tds(ehci, urb, qtd_list, epnum, &urb->ep->hcpriv); |
8de98402 | 952 | if (unlikely(qh == NULL)) { |
e9df41c5 | 953 | usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb); |
8de98402 BH |
954 | rc = -ENOMEM; |
955 | goto done; | |
956 | } | |
1da177e4 LT |
957 | |
958 | /* Control/bulk operations through TTs don't need scheduling, | |
959 | * the HC and TT handle it when the TT has a buffer ready. | |
960 | */ | |
8de98402 BH |
961 | if (likely (qh->qh_state == QH_STATE_IDLE)) |
962 | qh_link_async (ehci, qh_get (qh)); | |
963 | done: | |
1da177e4 | 964 | spin_unlock_irqrestore (&ehci->lock, flags); |
8de98402 | 965 | if (unlikely (qh == NULL)) |
1da177e4 | 966 | qtd_list_free (ehci, urb, qtd_list); |
8de98402 | 967 | return rc; |
1da177e4 LT |
968 | } |
969 | ||
970 | /*-------------------------------------------------------------------------*/ | |
971 | ||
972 | /* the async qh for the qtds being reclaimed are now unlinked from the HC */ | |
973 | ||
7d12e780 | 974 | static void end_unlink_async (struct ehci_hcd *ehci) |
1da177e4 LT |
975 | { |
976 | struct ehci_qh *qh = ehci->reclaim; | |
977 | struct ehci_qh *next; | |
978 | ||
07d29b63 | 979 | iaa_watchdog_done(ehci); |
1da177e4 | 980 | |
6dbd682b | 981 | // qh->hw_next = cpu_to_hc32(qh->qh_dma); |
1da177e4 LT |
982 | qh->qh_state = QH_STATE_IDLE; |
983 | qh->qh_next.qh = NULL; | |
53bd6a60 | 984 | qh_put (qh); // refcount from reclaim |
1da177e4 LT |
985 | |
986 | /* other unlink(s) may be pending (in QH_STATE_UNLINK_WAIT) */ | |
987 | next = qh->reclaim; | |
988 | ehci->reclaim = next; | |
1da177e4 LT |
989 | qh->reclaim = NULL; |
990 | ||
7d12e780 | 991 | qh_completions (ehci, qh); |
1da177e4 LT |
992 | |
993 | if (!list_empty (&qh->qtd_list) | |
994 | && HC_IS_RUNNING (ehci_to_hcd(ehci)->state)) | |
995 | qh_link_async (ehci, qh); | |
996 | else { | |
997 | qh_put (qh); // refcount from async list | |
998 | ||
999 | /* it's not free to turn the async schedule on/off; leave it | |
1000 | * active but idle for a while once it empties. | |
1001 | */ | |
1002 | if (HC_IS_RUNNING (ehci_to_hcd(ehci)->state) | |
1003 | && ehci->async->qh_next.qh == NULL) | |
1004 | timer_action (ehci, TIMER_ASYNC_OFF); | |
1005 | } | |
1006 | ||
1007 | if (next) { | |
1008 | ehci->reclaim = NULL; | |
1009 | start_unlink_async (ehci, next); | |
1010 | } | |
1011 | } | |
1012 | ||
1013 | /* makes sure the async qh will become idle */ | |
1014 | /* caller must own ehci->lock */ | |
1015 | ||
1016 | static void start_unlink_async (struct ehci_hcd *ehci, struct ehci_qh *qh) | |
1017 | { | |
083522d7 | 1018 | int cmd = ehci_readl(ehci, &ehci->regs->command); |
1da177e4 LT |
1019 | struct ehci_qh *prev; |
1020 | ||
1021 | #ifdef DEBUG | |
1022 | assert_spin_locked(&ehci->lock); | |
1023 | if (ehci->reclaim | |
1024 | || (qh->qh_state != QH_STATE_LINKED | |
1025 | && qh->qh_state != QH_STATE_UNLINK_WAIT) | |
1026 | ) | |
1027 | BUG (); | |
1028 | #endif | |
1029 | ||
1030 | /* stop async schedule right now? */ | |
1031 | if (unlikely (qh == ehci->async)) { | |
1032 | /* can't get here without STS_ASS set */ | |
d0852299 DB |
1033 | if (ehci_to_hcd(ehci)->state != HC_STATE_HALT |
1034 | && !ehci->reclaim) { | |
1035 | /* ... and CMD_IAAD clear */ | |
083522d7 BH |
1036 | ehci_writel(ehci, cmd & ~CMD_ASE, |
1037 | &ehci->regs->command); | |
1da177e4 LT |
1038 | wmb (); |
1039 | // handshake later, if we need to | |
d0852299 | 1040 | timer_action_done (ehci, TIMER_ASYNC_OFF); |
1da177e4 | 1041 | } |
1da177e4 | 1042 | return; |
53bd6a60 | 1043 | } |
1da177e4 LT |
1044 | |
1045 | qh->qh_state = QH_STATE_UNLINK; | |
1046 | ehci->reclaim = qh = qh_get (qh); | |
1047 | ||
1048 | prev = ehci->async; | |
1049 | while (prev->qh_next.qh != qh) | |
1050 | prev = prev->qh_next.qh; | |
1051 | ||
1052 | prev->hw_next = qh->hw_next; | |
1053 | prev->qh_next = qh->qh_next; | |
1054 | wmb (); | |
1055 | ||
1056 | if (unlikely (ehci_to_hcd(ehci)->state == HC_STATE_HALT)) { | |
1057 | /* if (unlikely (qh->reclaim != 0)) | |
53bd6a60 | 1058 | * this will recurse, probably not much |
1da177e4 | 1059 | */ |
7d12e780 | 1060 | end_unlink_async (ehci); |
1da177e4 LT |
1061 | return; |
1062 | } | |
1063 | ||
1da177e4 | 1064 | cmd |= CMD_IAAD; |
083522d7 BH |
1065 | ehci_writel(ehci, cmd, &ehci->regs->command); |
1066 | (void)ehci_readl(ehci, &ehci->regs->command); | |
07d29b63 | 1067 | iaa_watchdog_start(ehci); |
1da177e4 LT |
1068 | } |
1069 | ||
1070 | /*-------------------------------------------------------------------------*/ | |
1071 | ||
7d12e780 | 1072 | static void scan_async (struct ehci_hcd *ehci) |
1da177e4 LT |
1073 | { |
1074 | struct ehci_qh *qh; | |
1075 | enum ehci_timer_action action = TIMER_IO_WATCHDOG; | |
1076 | ||
1077 | if (!++(ehci->stamp)) | |
1078 | ehci->stamp++; | |
1079 | timer_action_done (ehci, TIMER_ASYNC_SHRINK); | |
1080 | rescan: | |
1081 | qh = ehci->async->qh_next.qh; | |
1082 | if (likely (qh != NULL)) { | |
1083 | do { | |
1084 | /* clean any finished work for this qh */ | |
1085 | if (!list_empty (&qh->qtd_list) | |
1086 | && qh->stamp != ehci->stamp) { | |
1087 | int temp; | |
1088 | ||
1089 | /* unlinks could happen here; completion | |
1090 | * reporting drops the lock. rescan using | |
1091 | * the latest schedule, but don't rescan | |
1092 | * qhs we already finished (no looping). | |
1093 | */ | |
1094 | qh = qh_get (qh); | |
1095 | qh->stamp = ehci->stamp; | |
7d12e780 | 1096 | temp = qh_completions (ehci, qh); |
1da177e4 LT |
1097 | qh_put (qh); |
1098 | if (temp != 0) { | |
1099 | goto rescan; | |
1100 | } | |
1101 | } | |
1102 | ||
1103 | /* unlink idle entries, reducing HC PCI usage as well | |
1104 | * as HCD schedule-scanning costs. delay for any qh | |
1105 | * we just scanned, there's a not-unusual case that it | |
1106 | * doesn't stay idle for long. | |
1107 | * (plus, avoids some kind of re-activation race.) | |
1108 | */ | |
1109 | if (list_empty (&qh->qtd_list)) { | |
1110 | if (qh->stamp == ehci->stamp) | |
1111 | action = TIMER_ASYNC_SHRINK; | |
1112 | else if (!ehci->reclaim | |
1113 | && qh->qh_state == QH_STATE_LINKED) | |
1114 | start_unlink_async (ehci, qh); | |
1115 | } | |
1116 | ||
1117 | qh = qh->qh_next.qh; | |
1118 | } while (qh); | |
1119 | } | |
1120 | if (action == TIMER_ASYNC_SHRINK) | |
1121 | timer_action (ehci, TIMER_ASYNC_SHRINK); | |
1122 | } |