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1da177e4 LT |
1 | /* |
2 | * Copyright (c) 2001-2002 by David Brownell | |
53bd6a60 | 3 | * |
1da177e4 LT |
4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms of the GNU General Public License as published by the | |
6 | * Free Software Foundation; either version 2 of the License, or (at your | |
7 | * option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but | |
10 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
11 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 | * for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software Foundation, | |
16 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
17 | */ | |
18 | ||
19 | #ifndef __LINUX_EHCI_HCD_H | |
20 | #define __LINUX_EHCI_HCD_H | |
21 | ||
22 | /* definitions used for the EHCI driver */ | |
23 | ||
6dbd682b SR |
24 | /* |
25 | * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to | |
26 | * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on | |
27 | * the host controller implementation. | |
28 | * | |
29 | * To facilitate the strongest possible byte-order checking from "sparse" | |
30 | * and so on, we use __leXX unless that's not practical. | |
31 | */ | |
32 | #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC | |
33 | typedef __u32 __bitwise __hc32; | |
34 | typedef __u16 __bitwise __hc16; | |
35 | #else | |
36 | #define __hc32 __le32 | |
37 | #define __hc16 __le16 | |
38 | #endif | |
39 | ||
1da177e4 LT |
40 | /* statistics can be kept for for tuning/monitoring */ |
41 | struct ehci_stats { | |
42 | /* irq usage */ | |
43 | unsigned long normal; | |
44 | unsigned long error; | |
45 | unsigned long reclaim; | |
46 | unsigned long lost_iaa; | |
47 | ||
48 | /* termination of urbs from core */ | |
49 | unsigned long complete; | |
50 | unsigned long unlink; | |
51 | }; | |
52 | ||
53 | /* ehci_hcd->lock guards shared data against other CPUs: | |
54 | * ehci_hcd: async, reclaim, periodic (and shadow), ... | |
55 | * usb_host_endpoint: hcpriv | |
56 | * ehci_qh: qh_next, qtd_list | |
57 | * ehci_qtd: qtd_list | |
58 | * | |
59 | * Also, hold this lock when talking to HC registers or | |
60 | * when updating hw_* fields in shared qh/qtd/... structures. | |
61 | */ | |
62 | ||
63 | #define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */ | |
64 | ||
65 | struct ehci_hcd { /* one per controller */ | |
56c1e26d DB |
66 | /* glue to PCI and HCD framework */ |
67 | struct ehci_caps __iomem *caps; | |
68 | struct ehci_regs __iomem *regs; | |
69 | struct ehci_dbg_port __iomem *debug; | |
70 | ||
71 | __u32 hcs_params; /* cached register copy */ | |
1da177e4 LT |
72 | spinlock_t lock; |
73 | ||
196705c9 SD |
74 | #ifdef CONFIG_CPU_FREQ |
75 | struct notifier_block cpufreq_transition; | |
76 | int cpufreq_changing; | |
77 | struct list_head split_intr_qhs; | |
78 | #endif | |
79 | ||
1da177e4 LT |
80 | /* async schedule support */ |
81 | struct ehci_qh *async; | |
82 | struct ehci_qh *reclaim; | |
64f89798 | 83 | unsigned reclaim_ready : 1; |
1da177e4 LT |
84 | unsigned scanning : 1; |
85 | ||
86 | /* periodic schedule support */ | |
87 | #define DEFAULT_I_TDPS 1024 /* some HCs can do less */ | |
88 | unsigned periodic_size; | |
6dbd682b | 89 | __hc32 *periodic; /* hw periodic table */ |
1da177e4 LT |
90 | dma_addr_t periodic_dma; |
91 | unsigned i_thresh; /* uframes HC might cache */ | |
92 | ||
93 | union ehci_shadow *pshadow; /* mirror hw periodic table */ | |
94 | int next_uframe; /* scan periodic, start here */ | |
95 | unsigned periodic_sched; /* periodic activity count */ | |
96 | ||
97 | /* per root hub port */ | |
98 | unsigned long reset_done [EHCI_MAX_ROOT_PORTS]; | |
57e06c11 AS |
99 | /* bit vectors (one bit per port) */ |
100 | unsigned long bus_suspended; /* which ports were | |
101 | already suspended at the start of a bus suspend */ | |
102 | unsigned long companion_ports; /* which ports are | |
103 | dedicated to the companion controller */ | |
1da177e4 LT |
104 | |
105 | /* per-HC memory pools (could be per-bus, but ...) */ | |
106 | struct dma_pool *qh_pool; /* qh per active urb */ | |
107 | struct dma_pool *qtd_pool; /* one or more per qh */ | |
108 | struct dma_pool *itd_pool; /* itd per iso urb */ | |
109 | struct dma_pool *sitd_pool; /* sitd per split iso urb */ | |
110 | ||
111 | struct timer_list watchdog; | |
1da177e4 LT |
112 | unsigned long actions; |
113 | unsigned stamp; | |
114 | unsigned long next_statechange; | |
115 | u32 command; | |
116 | ||
8cd42e97 | 117 | /* SILICON QUIRKS */ |
1da177e4 | 118 | unsigned is_tdi_rh_tt:1; /* TDI roothub with TT */ |
f8aeb3bb | 119 | unsigned no_selective_suspend:1; |
8cd42e97 | 120 | unsigned has_fsl_port_bug:1; /* FreeScale */ |
083522d7 | 121 | unsigned big_endian_mmio:1; |
6dbd682b | 122 | unsigned big_endian_desc:1; |
8cd42e97 | 123 | |
f8aeb3bb | 124 | u8 sbrn; /* packed release number */ |
1da177e4 | 125 | |
1da177e4 LT |
126 | /* irq statistics */ |
127 | #ifdef EHCI_STATS | |
128 | struct ehci_stats stats; | |
129 | # define COUNT(x) do { (x)++; } while (0) | |
130 | #else | |
131 | # define COUNT(x) do {} while (0) | |
132 | #endif | |
133 | }; | |
134 | ||
53bd6a60 | 135 | /* convert between an HCD pointer and the corresponding EHCI_HCD */ |
1da177e4 LT |
136 | static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd) |
137 | { | |
138 | return (struct ehci_hcd *) (hcd->hcd_priv); | |
139 | } | |
140 | static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci) | |
141 | { | |
142 | return container_of ((void *) ehci, struct usb_hcd, hcd_priv); | |
143 | } | |
144 | ||
145 | ||
146 | enum ehci_timer_action { | |
147 | TIMER_IO_WATCHDOG, | |
64f89798 | 148 | TIMER_IAA_WATCHDOG, |
1da177e4 LT |
149 | TIMER_ASYNC_SHRINK, |
150 | TIMER_ASYNC_OFF, | |
151 | }; | |
152 | ||
153 | static inline void | |
154 | timer_action_done (struct ehci_hcd *ehci, enum ehci_timer_action action) | |
155 | { | |
156 | clear_bit (action, &ehci->actions); | |
157 | } | |
158 | ||
159 | static inline void | |
160 | timer_action (struct ehci_hcd *ehci, enum ehci_timer_action action) | |
161 | { | |
162 | if (!test_and_set_bit (action, &ehci->actions)) { | |
163 | unsigned long t; | |
164 | ||
165 | switch (action) { | |
64f89798 GKH |
166 | case TIMER_IAA_WATCHDOG: |
167 | t = EHCI_IAA_JIFFIES; | |
168 | break; | |
1da177e4 LT |
169 | case TIMER_IO_WATCHDOG: |
170 | t = EHCI_IO_JIFFIES; | |
171 | break; | |
172 | case TIMER_ASYNC_OFF: | |
173 | t = EHCI_ASYNC_JIFFIES; | |
174 | break; | |
175 | // case TIMER_ASYNC_SHRINK: | |
176 | default: | |
177 | t = EHCI_SHRINK_JIFFIES; | |
178 | break; | |
179 | } | |
180 | t += jiffies; | |
181 | // all timings except IAA watchdog can be overridden. | |
182 | // async queue SHRINK often precedes IAA. while it's ready | |
183 | // to go OFF neither can matter, and afterwards the IO | |
184 | // watchdog stops unless there's still periodic traffic. | |
64f89798 GKH |
185 | if (action != TIMER_IAA_WATCHDOG |
186 | && t > ehci->watchdog.expires | |
1da177e4 LT |
187 | && timer_pending (&ehci->watchdog)) |
188 | return; | |
189 | mod_timer (&ehci->watchdog, t); | |
190 | } | |
191 | } | |
192 | ||
193 | /*-------------------------------------------------------------------------*/ | |
194 | ||
195 | /* EHCI register interface, corresponds to EHCI Revision 0.95 specification */ | |
196 | ||
197 | /* Section 2.2 Host Controller Capability Registers */ | |
198 | struct ehci_caps { | |
199 | /* these fields are specified as 8 and 16 bit registers, | |
200 | * but some hosts can't perform 8 or 16 bit PCI accesses. | |
201 | */ | |
56c1e26d | 202 | u32 hc_capbase; |
1da177e4 LT |
203 | #define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */ |
204 | #define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */ | |
205 | u32 hcs_params; /* HCSPARAMS - offset 0x4 */ | |
206 | #define HCS_DEBUG_PORT(p) (((p)>>20)&0xf) /* bits 23:20, debug port? */ | |
207 | #define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */ | |
208 | #define HCS_N_CC(p) (((p)>>12)&0xf) /* bits 15:12, #companion HCs */ | |
209 | #define HCS_N_PCC(p) (((p)>>8)&0xf) /* bits 11:8, ports per CC */ | |
53bd6a60 DB |
210 | #define HCS_PORTROUTED(p) ((p)&(1 << 7)) /* true: port routing */ |
211 | #define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */ | |
1da177e4 LT |
212 | #define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */ |
213 | ||
214 | u32 hcc_params; /* HCCPARAMS - offset 0x8 */ | |
215 | #define HCC_EXT_CAPS(p) (((p)>>8)&0xff) /* for pci extended caps */ | |
216 | #define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */ | |
217 | #define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */ | |
218 | #define HCC_CANPARK(p) ((p)&(1 << 2)) /* true: can park on async qh */ | |
219 | #define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1)) /* true: periodic_size changes*/ | |
220 | #define HCC_64BIT_ADDR(p) ((p)&(1)) /* true: can use 64-bit addr */ | |
221 | u8 portroute [8]; /* nibbles for routing - offset 0xC */ | |
222 | } __attribute__ ((packed)); | |
223 | ||
224 | ||
225 | /* Section 2.3 Host Controller Operational Registers */ | |
226 | struct ehci_regs { | |
227 | ||
228 | /* USBCMD: offset 0x00 */ | |
229 | u32 command; | |
230 | /* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */ | |
231 | #define CMD_PARK (1<<11) /* enable "park" on async qh */ | |
232 | #define CMD_PARK_CNT(c) (((c)>>8)&3) /* how many transfers to park for */ | |
233 | #define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */ | |
234 | #define CMD_IAAD (1<<6) /* "doorbell" interrupt async advance */ | |
235 | #define CMD_ASE (1<<5) /* async schedule enable */ | |
53bd6a60 | 236 | #define CMD_PSE (1<<4) /* periodic schedule enable */ |
1da177e4 LT |
237 | /* 3:2 is periodic frame list size */ |
238 | #define CMD_RESET (1<<1) /* reset HC not bus */ | |
239 | #define CMD_RUN (1<<0) /* start/stop HC */ | |
240 | ||
241 | /* USBSTS: offset 0x04 */ | |
242 | u32 status; | |
243 | #define STS_ASS (1<<15) /* Async Schedule Status */ | |
244 | #define STS_PSS (1<<14) /* Periodic Schedule Status */ | |
245 | #define STS_RECL (1<<13) /* Reclamation */ | |
246 | #define STS_HALT (1<<12) /* Not running (any reason) */ | |
247 | /* some bits reserved */ | |
248 | /* these STS_* flags are also intr_enable bits (USBINTR) */ | |
249 | #define STS_IAA (1<<5) /* Interrupted on async advance */ | |
250 | #define STS_FATAL (1<<4) /* such as some PCI access errors */ | |
251 | #define STS_FLR (1<<3) /* frame list rolled over */ | |
252 | #define STS_PCD (1<<2) /* port change detect */ | |
253 | #define STS_ERR (1<<1) /* "error" completion (overflow, ...) */ | |
254 | #define STS_INT (1<<0) /* "normal" completion (short, ...) */ | |
255 | ||
256 | /* USBINTR: offset 0x08 */ | |
257 | u32 intr_enable; | |
258 | ||
259 | /* FRINDEX: offset 0x0C */ | |
260 | u32 frame_index; /* current microframe number */ | |
261 | /* CTRLDSSEGMENT: offset 0x10 */ | |
53bd6a60 | 262 | u32 segment; /* address bits 63:32 if needed */ |
1da177e4 | 263 | /* PERIODICLISTBASE: offset 0x14 */ |
53bd6a60 | 264 | u32 frame_list; /* points to periodic list */ |
1da177e4 LT |
265 | /* ASYNCLISTADDR: offset 0x18 */ |
266 | u32 async_next; /* address of next async queue head */ | |
267 | ||
268 | u32 reserved [9]; | |
269 | ||
270 | /* CONFIGFLAG: offset 0x40 */ | |
271 | u32 configured_flag; | |
272 | #define FLAG_CF (1<<0) /* true: we'll support "high speed" */ | |
273 | ||
274 | /* PORTSC: offset 0x44 */ | |
275 | u32 port_status [0]; /* up to N_PORTS */ | |
276 | /* 31:23 reserved */ | |
277 | #define PORT_WKOC_E (1<<22) /* wake on overcurrent (enable) */ | |
278 | #define PORT_WKDISC_E (1<<21) /* wake on disconnect (enable) */ | |
279 | #define PORT_WKCONN_E (1<<20) /* wake on connect (enable) */ | |
280 | /* 19:16 for port testing */ | |
281 | #define PORT_LED_OFF (0<<14) | |
282 | #define PORT_LED_AMBER (1<<14) | |
283 | #define PORT_LED_GREEN (2<<14) | |
284 | #define PORT_LED_MASK (3<<14) | |
285 | #define PORT_OWNER (1<<13) /* true: companion hc owns this port */ | |
286 | #define PORT_POWER (1<<12) /* true: has power (see PPC) */ | |
287 | #define PORT_USB11(x) (((x)&(3<<10))==(1<<10)) /* USB 1.1 device */ | |
288 | /* 11:10 for detecting lowspeed devices (reset vs release ownership) */ | |
289 | /* 9 reserved */ | |
290 | #define PORT_RESET (1<<8) /* reset port */ | |
291 | #define PORT_SUSPEND (1<<7) /* suspend port */ | |
292 | #define PORT_RESUME (1<<6) /* resume it */ | |
293 | #define PORT_OCC (1<<5) /* over current change */ | |
294 | #define PORT_OC (1<<4) /* over current active */ | |
295 | #define PORT_PEC (1<<3) /* port enable change */ | |
296 | #define PORT_PE (1<<2) /* port enable */ | |
297 | #define PORT_CSC (1<<1) /* connect status change */ | |
298 | #define PORT_CONNECT (1<<0) /* device connected */ | |
10f6524a | 299 | #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC) |
1da177e4 LT |
300 | } __attribute__ ((packed)); |
301 | ||
302 | /* Appendix C, Debug port ... intended for use with special "debug devices" | |
303 | * that can help if there's no serial console. (nonstandard enumeration.) | |
304 | */ | |
305 | struct ehci_dbg_port { | |
306 | u32 control; | |
307 | #define DBGP_OWNER (1<<30) | |
308 | #define DBGP_ENABLED (1<<28) | |
309 | #define DBGP_DONE (1<<16) | |
310 | #define DBGP_INUSE (1<<10) | |
56c1e26d | 311 | #define DBGP_ERRCODE(x) (((x)>>7)&0x07) |
1da177e4 LT |
312 | # define DBGP_ERR_BAD 1 |
313 | # define DBGP_ERR_SIGNAL 2 | |
314 | #define DBGP_ERROR (1<<6) | |
315 | #define DBGP_GO (1<<5) | |
316 | #define DBGP_OUT (1<<4) | |
317 | #define DBGP_LEN(x) (((x)>>0)&0x0f) | |
318 | u32 pids; | |
319 | #define DBGP_PID_GET(x) (((x)>>16)&0xff) | |
56c1e26d | 320 | #define DBGP_PID_SET(data,tok) (((data)<<8)|(tok)) |
1da177e4 LT |
321 | u32 data03; |
322 | u32 data47; | |
323 | u32 address; | |
56c1e26d | 324 | #define DBGP_EPADDR(dev,ep) (((dev)<<8)|(ep)) |
1da177e4 LT |
325 | } __attribute__ ((packed)); |
326 | ||
327 | /*-------------------------------------------------------------------------*/ | |
328 | ||
6dbd682b | 329 | #define QTD_NEXT(ehci, dma) cpu_to_hc32(ehci, (u32)dma) |
1da177e4 LT |
330 | |
331 | /* | |
332 | * EHCI Specification 0.95 Section 3.5 | |
53bd6a60 | 333 | * QTD: describe data transfer components (buffer, direction, ...) |
1da177e4 LT |
334 | * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram". |
335 | * | |
336 | * These are associated only with "QH" (Queue Head) structures, | |
337 | * used with control, bulk, and interrupt transfers. | |
338 | */ | |
339 | struct ehci_qtd { | |
340 | /* first part defined by EHCI spec */ | |
6dbd682b SR |
341 | __hc32 hw_next; /* see EHCI 3.5.1 */ |
342 | __hc32 hw_alt_next; /* see EHCI 3.5.2 */ | |
343 | __hc32 hw_token; /* see EHCI 3.5.3 */ | |
1da177e4 LT |
344 | #define QTD_TOGGLE (1 << 31) /* data toggle */ |
345 | #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff) | |
346 | #define QTD_IOC (1 << 15) /* interrupt on complete */ | |
347 | #define QTD_CERR(tok) (((tok)>>10) & 0x3) | |
348 | #define QTD_PID(tok) (((tok)>>8) & 0x3) | |
349 | #define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */ | |
350 | #define QTD_STS_HALT (1 << 6) /* halted on error */ | |
351 | #define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */ | |
352 | #define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */ | |
353 | #define QTD_STS_XACT (1 << 3) /* device gave illegal response */ | |
354 | #define QTD_STS_MMF (1 << 2) /* incomplete split transaction */ | |
355 | #define QTD_STS_STS (1 << 1) /* split transaction state */ | |
356 | #define QTD_STS_PING (1 << 0) /* issue PING? */ | |
6dbd682b SR |
357 | |
358 | #define ACTIVE_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_ACTIVE) | |
359 | #define HALT_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_HALT) | |
360 | #define STATUS_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_STS) | |
361 | ||
362 | __hc32 hw_buf [5]; /* see EHCI 3.5.4 */ | |
363 | __hc32 hw_buf_hi [5]; /* Appendix B */ | |
1da177e4 LT |
364 | |
365 | /* the rest is HCD-private */ | |
366 | dma_addr_t qtd_dma; /* qtd address */ | |
367 | struct list_head qtd_list; /* sw qtd list */ | |
368 | struct urb *urb; /* qtd's urb */ | |
369 | size_t length; /* length of buffer */ | |
370 | } __attribute__ ((aligned (32))); | |
371 | ||
372 | /* mask NakCnt+T in qh->hw_alt_next */ | |
6dbd682b | 373 | #define QTD_MASK(ehci) cpu_to_hc32 (ehci, ~0x1f) |
1da177e4 LT |
374 | |
375 | #define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1) | |
376 | ||
377 | /*-------------------------------------------------------------------------*/ | |
378 | ||
379 | /* type tag from {qh,itd,sitd,fstn}->hw_next */ | |
6dbd682b | 380 | #define Q_NEXT_TYPE(ehci,dma) ((dma) & cpu_to_hc32(ehci, 3 << 1)) |
1da177e4 | 381 | |
6dbd682b SR |
382 | /* |
383 | * Now the following defines are not converted using the | |
384 | * __constant_cpu_to_le32() macro anymore, since we have to support | |
385 | * "dynamic" switching between be and le support, so that the driver | |
386 | * can be used on one system with SoC EHCI controller using big-endian | |
387 | * descriptors as well as a normal little-endian PCI EHCI controller. | |
388 | */ | |
1da177e4 | 389 | /* values for that type tag */ |
6dbd682b SR |
390 | #define Q_TYPE_ITD (0 << 1) |
391 | #define Q_TYPE_QH (1 << 1) | |
392 | #define Q_TYPE_SITD (2 << 1) | |
393 | #define Q_TYPE_FSTN (3 << 1) | |
1da177e4 LT |
394 | |
395 | /* next async queue entry, or pointer to interrupt/periodic QH */ | |
6dbd682b | 396 | #define QH_NEXT(ehci,dma) (cpu_to_hc32(ehci, (((u32)dma)&~0x01f)|Q_TYPE_QH)) |
1da177e4 LT |
397 | |
398 | /* for periodic/async schedules and qtd lists, mark end of list */ | |
6dbd682b | 399 | #define EHCI_LIST_END(ehci) cpu_to_hc32(ehci, 1) /* "null pointer" to hw */ |
1da177e4 LT |
400 | |
401 | /* | |
402 | * Entries in periodic shadow table are pointers to one of four kinds | |
403 | * of data structure. That's dictated by the hardware; a type tag is | |
404 | * encoded in the low bits of the hardware's periodic schedule. Use | |
405 | * Q_NEXT_TYPE to get the tag. | |
406 | * | |
407 | * For entries in the async schedule, the type tag always says "qh". | |
408 | */ | |
409 | union ehci_shadow { | |
53bd6a60 | 410 | struct ehci_qh *qh; /* Q_TYPE_QH */ |
1da177e4 LT |
411 | struct ehci_itd *itd; /* Q_TYPE_ITD */ |
412 | struct ehci_sitd *sitd; /* Q_TYPE_SITD */ | |
413 | struct ehci_fstn *fstn; /* Q_TYPE_FSTN */ | |
6dbd682b | 414 | __hc32 *hw_next; /* (all types) */ |
1da177e4 LT |
415 | void *ptr; |
416 | }; | |
417 | ||
418 | /*-------------------------------------------------------------------------*/ | |
419 | ||
420 | /* | |
421 | * EHCI Specification 0.95 Section 3.6 | |
422 | * QH: describes control/bulk/interrupt endpoints | |
423 | * See Fig 3-7 "Queue Head Structure Layout". | |
424 | * | |
425 | * These appear in both the async and (for interrupt) periodic schedules. | |
426 | */ | |
427 | ||
428 | struct ehci_qh { | |
429 | /* first part defined by EHCI spec */ | |
6dbd682b SR |
430 | __hc32 hw_next; /* see EHCI 3.6.1 */ |
431 | __hc32 hw_info1; /* see EHCI 3.6.2 */ | |
1da177e4 | 432 | #define QH_HEAD 0x00008000 |
196705c9 | 433 | #define QH_INACTIVATE 0x00000080 |
6dbd682b SR |
434 | |
435 | #define INACTIVATE_BIT(ehci) cpu_to_hc32(ehci, QH_INACTIVATE) | |
436 | ||
437 | __hc32 hw_info2; /* see EHCI 3.6.2 */ | |
7dedacf4 DB |
438 | #define QH_SMASK 0x000000ff |
439 | #define QH_CMASK 0x0000ff00 | |
440 | #define QH_HUBADDR 0x007f0000 | |
441 | #define QH_HUBPORT 0x3f800000 | |
442 | #define QH_MULT 0xc0000000 | |
6dbd682b | 443 | __hc32 hw_current; /* qtd list - see EHCI 3.6.4 */ |
53bd6a60 | 444 | |
1da177e4 | 445 | /* qtd overlay (hardware parts of a struct ehci_qtd) */ |
6dbd682b SR |
446 | __hc32 hw_qtd_next; |
447 | __hc32 hw_alt_next; | |
448 | __hc32 hw_token; | |
449 | __hc32 hw_buf [5]; | |
450 | __hc32 hw_buf_hi [5]; | |
1da177e4 LT |
451 | |
452 | /* the rest is HCD-private */ | |
453 | dma_addr_t qh_dma; /* address of qh */ | |
454 | union ehci_shadow qh_next; /* ptr to qh; or periodic */ | |
455 | struct list_head qtd_list; /* sw qtd list */ | |
456 | struct ehci_qtd *dummy; | |
457 | struct ehci_qh *reclaim; /* next to reclaim */ | |
458 | ||
459 | struct ehci_hcd *ehci; | |
9c033e81 DB |
460 | |
461 | /* | |
462 | * Do NOT use atomic operations for QH refcounting. On some CPUs | |
463 | * (PPC7448 for example), atomic operations cannot be performed on | |
464 | * memory that is cache-inhibited (i.e. being used for DMA). | |
465 | * Spinlocks are used to protect all QH fields. | |
466 | */ | |
467 | u32 refcount; | |
1da177e4 LT |
468 | unsigned stamp; |
469 | ||
470 | u8 qh_state; | |
471 | #define QH_STATE_LINKED 1 /* HC sees this */ | |
472 | #define QH_STATE_UNLINK 2 /* HC may still see this */ | |
473 | #define QH_STATE_IDLE 3 /* HC doesn't see this */ | |
474 | #define QH_STATE_UNLINK_WAIT 4 /* LINKED and on reclaim q */ | |
475 | #define QH_STATE_COMPLETING 5 /* don't touch token.HALT */ | |
476 | ||
477 | /* periodic schedule info */ | |
478 | u8 usecs; /* intr bandwidth */ | |
479 | u8 gap_uf; /* uframes split/csplit gap */ | |
480 | u8 c_usecs; /* ... split completion bw */ | |
d0384200 | 481 | u16 tt_usecs; /* tt downstream bandwidth */ |
1da177e4 LT |
482 | unsigned short period; /* polling interval */ |
483 | unsigned short start; /* where polling starts */ | |
484 | #define NO_FRAME ((unsigned short)~0) /* pick new start */ | |
485 | struct usb_device *dev; /* access to TT */ | |
196705c9 SD |
486 | #ifdef CONFIG_CPU_FREQ |
487 | struct list_head split_intr_qhs; /* list of split qhs */ | |
488 | __le32 was_active; /* active bit before "i" set */ | |
489 | #endif | |
1da177e4 LT |
490 | } __attribute__ ((aligned (32))); |
491 | ||
492 | /*-------------------------------------------------------------------------*/ | |
493 | ||
494 | /* description of one iso transaction (up to 3 KB data if highspeed) */ | |
495 | struct ehci_iso_packet { | |
496 | /* These will be copied to iTD when scheduling */ | |
497 | u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */ | |
6dbd682b | 498 | __hc32 transaction; /* itd->hw_transaction[i] |= */ |
1da177e4 LT |
499 | u8 cross; /* buf crosses pages */ |
500 | /* for full speed OUT splits */ | |
501 | u32 buf1; | |
502 | }; | |
503 | ||
504 | /* temporary schedule data for packets from iso urbs (both speeds) | |
505 | * each packet is one logical usb transaction to the device (not TT), | |
506 | * beginning at stream->next_uframe | |
507 | */ | |
508 | struct ehci_iso_sched { | |
509 | struct list_head td_list; | |
510 | unsigned span; | |
511 | struct ehci_iso_packet packet [0]; | |
512 | }; | |
513 | ||
514 | /* | |
515 | * ehci_iso_stream - groups all (s)itds for this endpoint. | |
516 | * acts like a qh would, if EHCI had them for ISO. | |
517 | */ | |
518 | struct ehci_iso_stream { | |
519 | /* first two fields match QH, but info1 == 0 */ | |
6dbd682b SR |
520 | __hc32 hw_next; |
521 | __hc32 hw_info1; | |
1da177e4 LT |
522 | |
523 | u32 refcount; | |
524 | u8 bEndpointAddress; | |
525 | u8 highspeed; | |
526 | u16 depth; /* depth in uframes */ | |
527 | struct list_head td_list; /* queued itds/sitds */ | |
528 | struct list_head free_list; /* list of unused itds/sitds */ | |
529 | struct usb_device *udev; | |
53bd6a60 | 530 | struct usb_host_endpoint *ep; |
1da177e4 LT |
531 | |
532 | /* output of (re)scheduling */ | |
533 | unsigned long start; /* jiffies */ | |
534 | unsigned long rescheduled; | |
535 | int next_uframe; | |
6dbd682b | 536 | __hc32 splits; |
1da177e4 LT |
537 | |
538 | /* the rest is derived from the endpoint descriptor, | |
539 | * trusting urb->interval == f(epdesc->bInterval) and | |
540 | * including the extra info for hw_bufp[0..2] | |
541 | */ | |
542 | u8 interval; | |
543 | u8 usecs, c_usecs; | |
d0384200 | 544 | u16 tt_usecs; |
1da177e4 LT |
545 | u16 maxp; |
546 | u16 raw_mask; | |
547 | unsigned bandwidth; | |
548 | ||
549 | /* This is used to initialize iTD's hw_bufp fields */ | |
6dbd682b SR |
550 | __hc32 buf0; |
551 | __hc32 buf1; | |
552 | __hc32 buf2; | |
1da177e4 LT |
553 | |
554 | /* this is used to initialize sITD's tt info */ | |
6dbd682b | 555 | __hc32 address; |
1da177e4 LT |
556 | }; |
557 | ||
558 | /*-------------------------------------------------------------------------*/ | |
559 | ||
560 | /* | |
561 | * EHCI Specification 0.95 Section 3.3 | |
562 | * Fig 3-4 "Isochronous Transaction Descriptor (iTD)" | |
563 | * | |
564 | * Schedule records for high speed iso xfers | |
565 | */ | |
566 | struct ehci_itd { | |
567 | /* first part defined by EHCI spec */ | |
6dbd682b SR |
568 | __hc32 hw_next; /* see EHCI 3.3.1 */ |
569 | __hc32 hw_transaction [8]; /* see EHCI 3.3.2 */ | |
1da177e4 LT |
570 | #define EHCI_ISOC_ACTIVE (1<<31) /* activate transfer this slot */ |
571 | #define EHCI_ISOC_BUF_ERR (1<<30) /* Data buffer error */ | |
572 | #define EHCI_ISOC_BABBLE (1<<29) /* babble detected */ | |
573 | #define EHCI_ISOC_XACTERR (1<<28) /* XactErr - transaction error */ | |
574 | #define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff) | |
575 | #define EHCI_ITD_IOC (1 << 15) /* interrupt on complete */ | |
576 | ||
6dbd682b | 577 | #define ITD_ACTIVE(ehci) cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE) |
1da177e4 | 578 | |
6dbd682b SR |
579 | __hc32 hw_bufp [7]; /* see EHCI 3.3.3 */ |
580 | __hc32 hw_bufp_hi [7]; /* Appendix B */ | |
1da177e4 LT |
581 | |
582 | /* the rest is HCD-private */ | |
583 | dma_addr_t itd_dma; /* for this itd */ | |
584 | union ehci_shadow itd_next; /* ptr to periodic q entry */ | |
585 | ||
586 | struct urb *urb; | |
587 | struct ehci_iso_stream *stream; /* endpoint's queue */ | |
588 | struct list_head itd_list; /* list of stream's itds */ | |
589 | ||
590 | /* any/all hw_transactions here may be used by that urb */ | |
591 | unsigned frame; /* where scheduled */ | |
592 | unsigned pg; | |
593 | unsigned index[8]; /* in urb->iso_frame_desc */ | |
594 | u8 usecs[8]; | |
595 | } __attribute__ ((aligned (32))); | |
596 | ||
597 | /*-------------------------------------------------------------------------*/ | |
598 | ||
599 | /* | |
53bd6a60 | 600 | * EHCI Specification 0.95 Section 3.4 |
1da177e4 LT |
601 | * siTD, aka split-transaction isochronous Transfer Descriptor |
602 | * ... describe full speed iso xfers through TT in hubs | |
603 | * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD) | |
604 | */ | |
605 | struct ehci_sitd { | |
606 | /* first part defined by EHCI spec */ | |
6dbd682b | 607 | __hc32 hw_next; |
1da177e4 | 608 | /* uses bit field macros above - see EHCI 0.95 Table 3-8 */ |
6dbd682b SR |
609 | __hc32 hw_fullspeed_ep; /* EHCI table 3-9 */ |
610 | __hc32 hw_uframe; /* EHCI table 3-10 */ | |
611 | __hc32 hw_results; /* EHCI table 3-11 */ | |
1da177e4 LT |
612 | #define SITD_IOC (1 << 31) /* interrupt on completion */ |
613 | #define SITD_PAGE (1 << 30) /* buffer 0/1 */ | |
614 | #define SITD_LENGTH(x) (0x3ff & ((x)>>16)) | |
615 | #define SITD_STS_ACTIVE (1 << 7) /* HC may execute this */ | |
616 | #define SITD_STS_ERR (1 << 6) /* error from TT */ | |
617 | #define SITD_STS_DBE (1 << 5) /* data buffer error (in HC) */ | |
618 | #define SITD_STS_BABBLE (1 << 4) /* device was babbling */ | |
619 | #define SITD_STS_XACT (1 << 3) /* illegal IN response */ | |
620 | #define SITD_STS_MMF (1 << 2) /* incomplete split transaction */ | |
621 | #define SITD_STS_STS (1 << 1) /* split transaction state */ | |
622 | ||
6dbd682b | 623 | #define SITD_ACTIVE(ehci) cpu_to_hc32(ehci, SITD_STS_ACTIVE) |
1da177e4 | 624 | |
6dbd682b SR |
625 | __hc32 hw_buf [2]; /* EHCI table 3-12 */ |
626 | __hc32 hw_backpointer; /* EHCI table 3-13 */ | |
627 | __hc32 hw_buf_hi [2]; /* Appendix B */ | |
1da177e4 LT |
628 | |
629 | /* the rest is HCD-private */ | |
630 | dma_addr_t sitd_dma; | |
631 | union ehci_shadow sitd_next; /* ptr to periodic q entry */ | |
632 | ||
633 | struct urb *urb; | |
634 | struct ehci_iso_stream *stream; /* endpoint's queue */ | |
635 | struct list_head sitd_list; /* list of stream's sitds */ | |
636 | unsigned frame; | |
637 | unsigned index; | |
638 | } __attribute__ ((aligned (32))); | |
639 | ||
640 | /*-------------------------------------------------------------------------*/ | |
641 | ||
642 | /* | |
643 | * EHCI Specification 0.96 Section 3.7 | |
644 | * Periodic Frame Span Traversal Node (FSTN) | |
645 | * | |
646 | * Manages split interrupt transactions (using TT) that span frame boundaries | |
647 | * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN | |
648 | * makes the HC jump (back) to a QH to scan for fs/ls QH completions until | |
649 | * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work. | |
650 | */ | |
651 | struct ehci_fstn { | |
6dbd682b SR |
652 | __hc32 hw_next; /* any periodic q entry */ |
653 | __hc32 hw_prev; /* qh or EHCI_LIST_END */ | |
1da177e4 LT |
654 | |
655 | /* the rest is HCD-private */ | |
656 | dma_addr_t fstn_dma; | |
657 | union ehci_shadow fstn_next; /* ptr to periodic q entry */ | |
658 | } __attribute__ ((aligned (32))); | |
659 | ||
660 | /*-------------------------------------------------------------------------*/ | |
661 | ||
662 | #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT | |
663 | ||
664 | /* | |
665 | * Some EHCI controllers have a Transaction Translator built into the | |
666 | * root hub. This is a non-standard feature. Each controller will need | |
667 | * to add code to the following inline functions, and call them as | |
668 | * needed (mostly in root hub code). | |
669 | */ | |
670 | ||
671 | #define ehci_is_TDI(e) ((e)->is_tdi_rh_tt) | |
672 | ||
673 | /* Returns the speed of a device attached to a port on the root hub. */ | |
674 | static inline unsigned int | |
675 | ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc) | |
676 | { | |
677 | if (ehci_is_TDI(ehci)) { | |
678 | switch ((portsc>>26)&3) { | |
679 | case 0: | |
680 | return 0; | |
681 | case 1: | |
682 | return (1<<USB_PORT_FEAT_LOWSPEED); | |
683 | case 2: | |
684 | default: | |
685 | return (1<<USB_PORT_FEAT_HIGHSPEED); | |
686 | } | |
687 | } | |
688 | return (1<<USB_PORT_FEAT_HIGHSPEED); | |
689 | } | |
690 | ||
691 | #else | |
692 | ||
693 | #define ehci_is_TDI(e) (0) | |
694 | ||
695 | #define ehci_port_speed(ehci, portsc) (1<<USB_PORT_FEAT_HIGHSPEED) | |
696 | #endif | |
697 | ||
8cd42e97 KG |
698 | /*-------------------------------------------------------------------------*/ |
699 | ||
700 | #ifdef CONFIG_PPC_83xx | |
701 | /* Some Freescale processors have an erratum in which the TT | |
702 | * port number in the queue head was 0..N-1 instead of 1..N. | |
703 | */ | |
704 | #define ehci_has_fsl_portno_bug(e) ((e)->has_fsl_port_bug) | |
705 | #else | |
706 | #define ehci_has_fsl_portno_bug(e) (0) | |
707 | #endif | |
708 | ||
083522d7 BH |
709 | /* |
710 | * While most USB host controllers implement their registers in | |
711 | * little-endian format, a minority (celleb companion chip) implement | |
712 | * them in big endian format. | |
713 | * | |
714 | * This attempts to support either format at compile time without a | |
715 | * runtime penalty, or both formats with the additional overhead | |
716 | * of checking a flag bit. | |
717 | */ | |
718 | ||
719 | #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO | |
720 | #define ehci_big_endian_mmio(e) ((e)->big_endian_mmio) | |
721 | #else | |
722 | #define ehci_big_endian_mmio(e) 0 | |
723 | #endif | |
724 | ||
6dbd682b SR |
725 | /* |
726 | * Big-endian read/write functions are arch-specific. | |
727 | * Other arches can be added if/when they're needed. | |
728 | * | |
729 | * REVISIT: arch/powerpc now has readl/writel_be, so the | |
730 | * definition below can die once the 4xx support is | |
731 | * finally ported over. | |
732 | */ | |
733 | #if defined(CONFIG_PPC) | |
734 | #define readl_be(addr) in_be32((__force unsigned *)addr) | |
735 | #define writel_be(val, addr) out_be32((__force unsigned *)addr, val) | |
736 | #endif | |
737 | ||
738 | static inline unsigned int ehci_readl(const struct ehci_hcd *ehci, | |
739 | __u32 __iomem * regs) | |
083522d7 | 740 | { |
d728e327 | 741 | #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO |
083522d7 | 742 | return ehci_big_endian_mmio(ehci) ? |
68f50e52 AV |
743 | readl_be(regs) : |
744 | readl(regs); | |
d728e327 | 745 | #else |
68f50e52 | 746 | return readl(regs); |
d728e327 | 747 | #endif |
083522d7 BH |
748 | } |
749 | ||
6dbd682b SR |
750 | static inline void ehci_writel(const struct ehci_hcd *ehci, |
751 | const unsigned int val, __u32 __iomem *regs) | |
083522d7 | 752 | { |
d728e327 | 753 | #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO |
083522d7 | 754 | ehci_big_endian_mmio(ehci) ? |
68f50e52 AV |
755 | writel_be(val, regs) : |
756 | writel(val, regs); | |
d728e327 | 757 | #else |
68f50e52 | 758 | writel(val, regs); |
d728e327 | 759 | #endif |
083522d7 | 760 | } |
8cd42e97 | 761 | |
1da177e4 LT |
762 | /*-------------------------------------------------------------------------*/ |
763 | ||
6dbd682b SR |
764 | /* |
765 | * The AMCC 440EPx not only implements its EHCI registers in big-endian | |
766 | * format, but also its DMA data structures (descriptors). | |
767 | * | |
768 | * EHCI controllers accessed through PCI work normally (little-endian | |
769 | * everywhere), so we won't bother supporting a BE-only mode for now. | |
770 | */ | |
771 | #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC | |
772 | #define ehci_big_endian_desc(e) ((e)->big_endian_desc) | |
773 | ||
774 | /* cpu to ehci */ | |
775 | static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x) | |
776 | { | |
777 | return ehci_big_endian_desc(ehci) | |
778 | ? (__force __hc32)cpu_to_be32(x) | |
779 | : (__force __hc32)cpu_to_le32(x); | |
780 | } | |
781 | ||
782 | /* ehci to cpu */ | |
783 | static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x) | |
784 | { | |
785 | return ehci_big_endian_desc(ehci) | |
786 | ? be32_to_cpu((__force __be32)x) | |
787 | : le32_to_cpu((__force __le32)x); | |
788 | } | |
789 | ||
790 | static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x) | |
791 | { | |
792 | return ehci_big_endian_desc(ehci) | |
793 | ? be32_to_cpup((__force __be32 *)x) | |
794 | : le32_to_cpup((__force __le32 *)x); | |
795 | } | |
796 | ||
797 | #else | |
798 | ||
799 | /* cpu to ehci */ | |
800 | static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x) | |
801 | { | |
802 | return cpu_to_le32(x); | |
803 | } | |
804 | ||
805 | /* ehci to cpu */ | |
806 | static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x) | |
807 | { | |
808 | return le32_to_cpu(x); | |
809 | } | |
810 | ||
811 | static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x) | |
812 | { | |
813 | return le32_to_cpup(x); | |
814 | } | |
815 | ||
816 | #endif | |
817 | ||
818 | /*-------------------------------------------------------------------------*/ | |
819 | ||
1da177e4 LT |
820 | #ifndef DEBUG |
821 | #define STUB_DEBUG_FILES | |
822 | #endif /* DEBUG */ | |
823 | ||
824 | /*-------------------------------------------------------------------------*/ | |
825 | ||
826 | #endif /* __LINUX_EHCI_HCD_H */ |