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1da177e4 LT |
1 | /* |
2 | * Copyright (c) 2001-2002 by David Brownell | |
53bd6a60 | 3 | * |
1da177e4 LT |
4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms of the GNU General Public License as published by the | |
6 | * Free Software Foundation; either version 2 of the License, or (at your | |
7 | * option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but | |
10 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
11 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 | * for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software Foundation, | |
16 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
17 | */ | |
18 | ||
19 | #ifndef __LINUX_EHCI_HCD_H | |
20 | #define __LINUX_EHCI_HCD_H | |
21 | ||
22 | /* definitions used for the EHCI driver */ | |
23 | ||
6dbd682b SR |
24 | /* |
25 | * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to | |
26 | * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on | |
27 | * the host controller implementation. | |
28 | * | |
29 | * To facilitate the strongest possible byte-order checking from "sparse" | |
30 | * and so on, we use __leXX unless that's not practical. | |
31 | */ | |
32 | #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC | |
33 | typedef __u32 __bitwise __hc32; | |
34 | typedef __u16 __bitwise __hc16; | |
35 | #else | |
36 | #define __hc32 __le32 | |
37 | #define __hc16 __le16 | |
38 | #endif | |
39 | ||
1da177e4 LT |
40 | /* statistics can be kept for for tuning/monitoring */ |
41 | struct ehci_stats { | |
42 | /* irq usage */ | |
43 | unsigned long normal; | |
44 | unsigned long error; | |
45 | unsigned long reclaim; | |
46 | unsigned long lost_iaa; | |
47 | ||
48 | /* termination of urbs from core */ | |
49 | unsigned long complete; | |
50 | unsigned long unlink; | |
51 | }; | |
52 | ||
53 | /* ehci_hcd->lock guards shared data against other CPUs: | |
54 | * ehci_hcd: async, reclaim, periodic (and shadow), ... | |
55 | * usb_host_endpoint: hcpriv | |
56 | * ehci_qh: qh_next, qtd_list | |
57 | * ehci_qtd: qtd_list | |
58 | * | |
59 | * Also, hold this lock when talking to HC registers or | |
60 | * when updating hw_* fields in shared qh/qtd/... structures. | |
61 | */ | |
62 | ||
63 | #define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */ | |
64 | ||
65 | struct ehci_hcd { /* one per controller */ | |
56c1e26d DB |
66 | /* glue to PCI and HCD framework */ |
67 | struct ehci_caps __iomem *caps; | |
68 | struct ehci_regs __iomem *regs; | |
69 | struct ehci_dbg_port __iomem *debug; | |
70 | ||
71 | __u32 hcs_params; /* cached register copy */ | |
1da177e4 LT |
72 | spinlock_t lock; |
73 | ||
74 | /* async schedule support */ | |
75 | struct ehci_qh *async; | |
76 | struct ehci_qh *reclaim; | |
1da177e4 LT |
77 | unsigned scanning : 1; |
78 | ||
79 | /* periodic schedule support */ | |
80 | #define DEFAULT_I_TDPS 1024 /* some HCs can do less */ | |
81 | unsigned periodic_size; | |
6dbd682b | 82 | __hc32 *periodic; /* hw periodic table */ |
1da177e4 LT |
83 | dma_addr_t periodic_dma; |
84 | unsigned i_thresh; /* uframes HC might cache */ | |
85 | ||
86 | union ehci_shadow *pshadow; /* mirror hw periodic table */ | |
87 | int next_uframe; /* scan periodic, start here */ | |
88 | unsigned periodic_sched; /* periodic activity count */ | |
89 | ||
9aa09d2f KW |
90 | /* list of itds completed while clock_frame was still active */ |
91 | struct list_head cached_itd_list; | |
92 | unsigned clock_frame; | |
93 | ||
1da177e4 LT |
94 | /* per root hub port */ |
95 | unsigned long reset_done [EHCI_MAX_ROOT_PORTS]; | |
383975d7 | 96 | |
57e06c11 AS |
97 | /* bit vectors (one bit per port) */ |
98 | unsigned long bus_suspended; /* which ports were | |
99 | already suspended at the start of a bus suspend */ | |
100 | unsigned long companion_ports; /* which ports are | |
101 | dedicated to the companion controller */ | |
383975d7 AS |
102 | unsigned long owned_ports; /* which ports are |
103 | owned by the companion during a bus suspend */ | |
d1f114d1 AS |
104 | unsigned long port_c_suspend; /* which ports have |
105 | the change-suspend feature turned on */ | |
eafe5b99 AS |
106 | unsigned long suspended_ports; /* which ports are |
107 | suspended */ | |
1da177e4 LT |
108 | |
109 | /* per-HC memory pools (could be per-bus, but ...) */ | |
110 | struct dma_pool *qh_pool; /* qh per active urb */ | |
111 | struct dma_pool *qtd_pool; /* one or more per qh */ | |
112 | struct dma_pool *itd_pool; /* itd per iso urb */ | |
113 | struct dma_pool *sitd_pool; /* sitd per split iso urb */ | |
114 | ||
07d29b63 | 115 | struct timer_list iaa_watchdog; |
1da177e4 | 116 | struct timer_list watchdog; |
1da177e4 LT |
117 | unsigned long actions; |
118 | unsigned stamp; | |
68335e81 | 119 | unsigned random_frame; |
1da177e4 LT |
120 | unsigned long next_statechange; |
121 | u32 command; | |
122 | ||
8cd42e97 | 123 | /* SILICON QUIRKS */ |
f8aeb3bb | 124 | unsigned no_selective_suspend:1; |
8cd42e97 | 125 | unsigned has_fsl_port_bug:1; /* FreeScale */ |
083522d7 | 126 | unsigned big_endian_mmio:1; |
6dbd682b | 127 | unsigned big_endian_desc:1; |
796bcae7 VB |
128 | unsigned has_amcc_usb23:1; |
129 | ||
130 | /* required for usb32 quirk */ | |
131 | #define OHCI_CTRL_HCFS (3 << 6) | |
132 | #define OHCI_USB_OPER (2 << 6) | |
133 | #define OHCI_USB_SUSPEND (3 << 6) | |
134 | ||
135 | #define OHCI_HCCTRL_OFFSET 0x4 | |
136 | #define OHCI_HCCTRL_LEN 0x4 | |
137 | __hc32 *ohci_hcctrl_reg; | |
8cd42e97 | 138 | |
f8aeb3bb | 139 | u8 sbrn; /* packed release number */ |
1da177e4 | 140 | |
1da177e4 LT |
141 | /* irq statistics */ |
142 | #ifdef EHCI_STATS | |
143 | struct ehci_stats stats; | |
144 | # define COUNT(x) do { (x)++; } while (0) | |
145 | #else | |
146 | # define COUNT(x) do {} while (0) | |
694cc208 TJ |
147 | #endif |
148 | ||
149 | /* debug files */ | |
150 | #ifdef DEBUG | |
151 | struct dentry *debug_dir; | |
152 | struct dentry *debug_async; | |
153 | struct dentry *debug_periodic; | |
154 | struct dentry *debug_registers; | |
1da177e4 LT |
155 | #endif |
156 | }; | |
157 | ||
53bd6a60 | 158 | /* convert between an HCD pointer and the corresponding EHCI_HCD */ |
1da177e4 LT |
159 | static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd) |
160 | { | |
161 | return (struct ehci_hcd *) (hcd->hcd_priv); | |
162 | } | |
163 | static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci) | |
164 | { | |
165 | return container_of ((void *) ehci, struct usb_hcd, hcd_priv); | |
166 | } | |
167 | ||
168 | ||
07d29b63 AS |
169 | static inline void |
170 | iaa_watchdog_start(struct ehci_hcd *ehci) | |
171 | { | |
172 | WARN_ON(timer_pending(&ehci->iaa_watchdog)); | |
173 | mod_timer(&ehci->iaa_watchdog, | |
174 | jiffies + msecs_to_jiffies(EHCI_IAA_MSECS)); | |
175 | } | |
176 | ||
177 | static inline void iaa_watchdog_done(struct ehci_hcd *ehci) | |
178 | { | |
179 | del_timer(&ehci->iaa_watchdog); | |
180 | } | |
181 | ||
1da177e4 LT |
182 | enum ehci_timer_action { |
183 | TIMER_IO_WATCHDOG, | |
1da177e4 LT |
184 | TIMER_ASYNC_SHRINK, |
185 | TIMER_ASYNC_OFF, | |
186 | }; | |
187 | ||
188 | static inline void | |
189 | timer_action_done (struct ehci_hcd *ehci, enum ehci_timer_action action) | |
190 | { | |
191 | clear_bit (action, &ehci->actions); | |
192 | } | |
193 | ||
9aa09d2f KW |
194 | static void free_cached_itd_list(struct ehci_hcd *ehci); |
195 | ||
1da177e4 LT |
196 | /*-------------------------------------------------------------------------*/ |
197 | ||
0af36739 | 198 | #include <linux/usb/ehci_def.h> |
1da177e4 LT |
199 | |
200 | /*-------------------------------------------------------------------------*/ | |
201 | ||
6dbd682b | 202 | #define QTD_NEXT(ehci, dma) cpu_to_hc32(ehci, (u32)dma) |
1da177e4 LT |
203 | |
204 | /* | |
205 | * EHCI Specification 0.95 Section 3.5 | |
53bd6a60 | 206 | * QTD: describe data transfer components (buffer, direction, ...) |
1da177e4 LT |
207 | * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram". |
208 | * | |
209 | * These are associated only with "QH" (Queue Head) structures, | |
210 | * used with control, bulk, and interrupt transfers. | |
211 | */ | |
212 | struct ehci_qtd { | |
213 | /* first part defined by EHCI spec */ | |
6dbd682b SR |
214 | __hc32 hw_next; /* see EHCI 3.5.1 */ |
215 | __hc32 hw_alt_next; /* see EHCI 3.5.2 */ | |
216 | __hc32 hw_token; /* see EHCI 3.5.3 */ | |
1da177e4 LT |
217 | #define QTD_TOGGLE (1 << 31) /* data toggle */ |
218 | #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff) | |
219 | #define QTD_IOC (1 << 15) /* interrupt on complete */ | |
220 | #define QTD_CERR(tok) (((tok)>>10) & 0x3) | |
221 | #define QTD_PID(tok) (((tok)>>8) & 0x3) | |
222 | #define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */ | |
223 | #define QTD_STS_HALT (1 << 6) /* halted on error */ | |
224 | #define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */ | |
225 | #define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */ | |
226 | #define QTD_STS_XACT (1 << 3) /* device gave illegal response */ | |
227 | #define QTD_STS_MMF (1 << 2) /* incomplete split transaction */ | |
228 | #define QTD_STS_STS (1 << 1) /* split transaction state */ | |
229 | #define QTD_STS_PING (1 << 0) /* issue PING? */ | |
6dbd682b SR |
230 | |
231 | #define ACTIVE_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_ACTIVE) | |
232 | #define HALT_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_HALT) | |
233 | #define STATUS_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_STS) | |
234 | ||
235 | __hc32 hw_buf [5]; /* see EHCI 3.5.4 */ | |
236 | __hc32 hw_buf_hi [5]; /* Appendix B */ | |
1da177e4 LT |
237 | |
238 | /* the rest is HCD-private */ | |
239 | dma_addr_t qtd_dma; /* qtd address */ | |
240 | struct list_head qtd_list; /* sw qtd list */ | |
241 | struct urb *urb; /* qtd's urb */ | |
242 | size_t length; /* length of buffer */ | |
243 | } __attribute__ ((aligned (32))); | |
244 | ||
245 | /* mask NakCnt+T in qh->hw_alt_next */ | |
6dbd682b | 246 | #define QTD_MASK(ehci) cpu_to_hc32 (ehci, ~0x1f) |
1da177e4 LT |
247 | |
248 | #define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1) | |
249 | ||
250 | /*-------------------------------------------------------------------------*/ | |
251 | ||
252 | /* type tag from {qh,itd,sitd,fstn}->hw_next */ | |
6dbd682b | 253 | #define Q_NEXT_TYPE(ehci,dma) ((dma) & cpu_to_hc32(ehci, 3 << 1)) |
1da177e4 | 254 | |
6dbd682b SR |
255 | /* |
256 | * Now the following defines are not converted using the | |
551509d2 | 257 | * cpu_to_le32() macro anymore, since we have to support |
6dbd682b SR |
258 | * "dynamic" switching between be and le support, so that the driver |
259 | * can be used on one system with SoC EHCI controller using big-endian | |
260 | * descriptors as well as a normal little-endian PCI EHCI controller. | |
261 | */ | |
1da177e4 | 262 | /* values for that type tag */ |
6dbd682b SR |
263 | #define Q_TYPE_ITD (0 << 1) |
264 | #define Q_TYPE_QH (1 << 1) | |
265 | #define Q_TYPE_SITD (2 << 1) | |
266 | #define Q_TYPE_FSTN (3 << 1) | |
1da177e4 LT |
267 | |
268 | /* next async queue entry, or pointer to interrupt/periodic QH */ | |
6dbd682b | 269 | #define QH_NEXT(ehci,dma) (cpu_to_hc32(ehci, (((u32)dma)&~0x01f)|Q_TYPE_QH)) |
1da177e4 LT |
270 | |
271 | /* for periodic/async schedules and qtd lists, mark end of list */ | |
6dbd682b | 272 | #define EHCI_LIST_END(ehci) cpu_to_hc32(ehci, 1) /* "null pointer" to hw */ |
1da177e4 LT |
273 | |
274 | /* | |
275 | * Entries in periodic shadow table are pointers to one of four kinds | |
276 | * of data structure. That's dictated by the hardware; a type tag is | |
277 | * encoded in the low bits of the hardware's periodic schedule. Use | |
278 | * Q_NEXT_TYPE to get the tag. | |
279 | * | |
280 | * For entries in the async schedule, the type tag always says "qh". | |
281 | */ | |
282 | union ehci_shadow { | |
53bd6a60 | 283 | struct ehci_qh *qh; /* Q_TYPE_QH */ |
1da177e4 LT |
284 | struct ehci_itd *itd; /* Q_TYPE_ITD */ |
285 | struct ehci_sitd *sitd; /* Q_TYPE_SITD */ | |
286 | struct ehci_fstn *fstn; /* Q_TYPE_FSTN */ | |
6dbd682b | 287 | __hc32 *hw_next; /* (all types) */ |
1da177e4 LT |
288 | void *ptr; |
289 | }; | |
290 | ||
291 | /*-------------------------------------------------------------------------*/ | |
292 | ||
293 | /* | |
294 | * EHCI Specification 0.95 Section 3.6 | |
295 | * QH: describes control/bulk/interrupt endpoints | |
296 | * See Fig 3-7 "Queue Head Structure Layout". | |
297 | * | |
298 | * These appear in both the async and (for interrupt) periodic schedules. | |
299 | */ | |
300 | ||
301 | struct ehci_qh { | |
302 | /* first part defined by EHCI spec */ | |
6dbd682b SR |
303 | __hc32 hw_next; /* see EHCI 3.6.1 */ |
304 | __hc32 hw_info1; /* see EHCI 3.6.2 */ | |
1da177e4 | 305 | #define QH_HEAD 0x00008000 |
6dbd682b | 306 | __hc32 hw_info2; /* see EHCI 3.6.2 */ |
7dedacf4 DB |
307 | #define QH_SMASK 0x000000ff |
308 | #define QH_CMASK 0x0000ff00 | |
309 | #define QH_HUBADDR 0x007f0000 | |
310 | #define QH_HUBPORT 0x3f800000 | |
311 | #define QH_MULT 0xc0000000 | |
6dbd682b | 312 | __hc32 hw_current; /* qtd list - see EHCI 3.6.4 */ |
53bd6a60 | 313 | |
1da177e4 | 314 | /* qtd overlay (hardware parts of a struct ehci_qtd) */ |
6dbd682b SR |
315 | __hc32 hw_qtd_next; |
316 | __hc32 hw_alt_next; | |
317 | __hc32 hw_token; | |
318 | __hc32 hw_buf [5]; | |
319 | __hc32 hw_buf_hi [5]; | |
1da177e4 LT |
320 | |
321 | /* the rest is HCD-private */ | |
322 | dma_addr_t qh_dma; /* address of qh */ | |
323 | union ehci_shadow qh_next; /* ptr to qh; or periodic */ | |
324 | struct list_head qtd_list; /* sw qtd list */ | |
325 | struct ehci_qtd *dummy; | |
326 | struct ehci_qh *reclaim; /* next to reclaim */ | |
327 | ||
328 | struct ehci_hcd *ehci; | |
9c033e81 DB |
329 | |
330 | /* | |
331 | * Do NOT use atomic operations for QH refcounting. On some CPUs | |
332 | * (PPC7448 for example), atomic operations cannot be performed on | |
333 | * memory that is cache-inhibited (i.e. being used for DMA). | |
334 | * Spinlocks are used to protect all QH fields. | |
335 | */ | |
336 | u32 refcount; | |
1da177e4 LT |
337 | unsigned stamp; |
338 | ||
339 | u8 qh_state; | |
340 | #define QH_STATE_LINKED 1 /* HC sees this */ | |
341 | #define QH_STATE_UNLINK 2 /* HC may still see this */ | |
342 | #define QH_STATE_IDLE 3 /* HC doesn't see this */ | |
343 | #define QH_STATE_UNLINK_WAIT 4 /* LINKED and on reclaim q */ | |
344 | #define QH_STATE_COMPLETING 5 /* don't touch token.HALT */ | |
345 | ||
a2c2706e AS |
346 | u8 xacterrs; /* XactErr retry counter */ |
347 | #define QH_XACTERR_MAX 32 /* XactErr retry limit */ | |
348 | ||
1da177e4 LT |
349 | /* periodic schedule info */ |
350 | u8 usecs; /* intr bandwidth */ | |
351 | u8 gap_uf; /* uframes split/csplit gap */ | |
352 | u8 c_usecs; /* ... split completion bw */ | |
d0384200 | 353 | u16 tt_usecs; /* tt downstream bandwidth */ |
1da177e4 LT |
354 | unsigned short period; /* polling interval */ |
355 | unsigned short start; /* where polling starts */ | |
356 | #define NO_FRAME ((unsigned short)~0) /* pick new start */ | |
914b7012 | 357 | |
1da177e4 | 358 | struct usb_device *dev; /* access to TT */ |
914b7012 | 359 | unsigned clearing_tt:1; /* Clear-TT-Buf in progress */ |
1da177e4 LT |
360 | } __attribute__ ((aligned (32))); |
361 | ||
362 | /*-------------------------------------------------------------------------*/ | |
363 | ||
364 | /* description of one iso transaction (up to 3 KB data if highspeed) */ | |
365 | struct ehci_iso_packet { | |
366 | /* These will be copied to iTD when scheduling */ | |
367 | u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */ | |
6dbd682b | 368 | __hc32 transaction; /* itd->hw_transaction[i] |= */ |
1da177e4 LT |
369 | u8 cross; /* buf crosses pages */ |
370 | /* for full speed OUT splits */ | |
371 | u32 buf1; | |
372 | }; | |
373 | ||
374 | /* temporary schedule data for packets from iso urbs (both speeds) | |
375 | * each packet is one logical usb transaction to the device (not TT), | |
376 | * beginning at stream->next_uframe | |
377 | */ | |
378 | struct ehci_iso_sched { | |
379 | struct list_head td_list; | |
380 | unsigned span; | |
381 | struct ehci_iso_packet packet [0]; | |
382 | }; | |
383 | ||
384 | /* | |
385 | * ehci_iso_stream - groups all (s)itds for this endpoint. | |
386 | * acts like a qh would, if EHCI had them for ISO. | |
387 | */ | |
388 | struct ehci_iso_stream { | |
389 | /* first two fields match QH, but info1 == 0 */ | |
6dbd682b SR |
390 | __hc32 hw_next; |
391 | __hc32 hw_info1; | |
1da177e4 LT |
392 | |
393 | u32 refcount; | |
394 | u8 bEndpointAddress; | |
395 | u8 highspeed; | |
396 | u16 depth; /* depth in uframes */ | |
397 | struct list_head td_list; /* queued itds/sitds */ | |
398 | struct list_head free_list; /* list of unused itds/sitds */ | |
399 | struct usb_device *udev; | |
53bd6a60 | 400 | struct usb_host_endpoint *ep; |
1da177e4 LT |
401 | |
402 | /* output of (re)scheduling */ | |
403 | unsigned long start; /* jiffies */ | |
404 | unsigned long rescheduled; | |
405 | int next_uframe; | |
6dbd682b | 406 | __hc32 splits; |
1da177e4 LT |
407 | |
408 | /* the rest is derived from the endpoint descriptor, | |
409 | * trusting urb->interval == f(epdesc->bInterval) and | |
410 | * including the extra info for hw_bufp[0..2] | |
411 | */ | |
1da177e4 | 412 | u8 usecs, c_usecs; |
c06d4dcf | 413 | u16 interval; |
d0384200 | 414 | u16 tt_usecs; |
1da177e4 LT |
415 | u16 maxp; |
416 | u16 raw_mask; | |
417 | unsigned bandwidth; | |
418 | ||
419 | /* This is used to initialize iTD's hw_bufp fields */ | |
6dbd682b SR |
420 | __hc32 buf0; |
421 | __hc32 buf1; | |
422 | __hc32 buf2; | |
1da177e4 LT |
423 | |
424 | /* this is used to initialize sITD's tt info */ | |
6dbd682b | 425 | __hc32 address; |
1da177e4 LT |
426 | }; |
427 | ||
428 | /*-------------------------------------------------------------------------*/ | |
429 | ||
430 | /* | |
431 | * EHCI Specification 0.95 Section 3.3 | |
432 | * Fig 3-4 "Isochronous Transaction Descriptor (iTD)" | |
433 | * | |
434 | * Schedule records for high speed iso xfers | |
435 | */ | |
436 | struct ehci_itd { | |
437 | /* first part defined by EHCI spec */ | |
6dbd682b SR |
438 | __hc32 hw_next; /* see EHCI 3.3.1 */ |
439 | __hc32 hw_transaction [8]; /* see EHCI 3.3.2 */ | |
1da177e4 LT |
440 | #define EHCI_ISOC_ACTIVE (1<<31) /* activate transfer this slot */ |
441 | #define EHCI_ISOC_BUF_ERR (1<<30) /* Data buffer error */ | |
442 | #define EHCI_ISOC_BABBLE (1<<29) /* babble detected */ | |
443 | #define EHCI_ISOC_XACTERR (1<<28) /* XactErr - transaction error */ | |
444 | #define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff) | |
445 | #define EHCI_ITD_IOC (1 << 15) /* interrupt on complete */ | |
446 | ||
6dbd682b | 447 | #define ITD_ACTIVE(ehci) cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE) |
1da177e4 | 448 | |
6dbd682b SR |
449 | __hc32 hw_bufp [7]; /* see EHCI 3.3.3 */ |
450 | __hc32 hw_bufp_hi [7]; /* Appendix B */ | |
1da177e4 LT |
451 | |
452 | /* the rest is HCD-private */ | |
453 | dma_addr_t itd_dma; /* for this itd */ | |
454 | union ehci_shadow itd_next; /* ptr to periodic q entry */ | |
455 | ||
456 | struct urb *urb; | |
457 | struct ehci_iso_stream *stream; /* endpoint's queue */ | |
458 | struct list_head itd_list; /* list of stream's itds */ | |
459 | ||
460 | /* any/all hw_transactions here may be used by that urb */ | |
461 | unsigned frame; /* where scheduled */ | |
462 | unsigned pg; | |
463 | unsigned index[8]; /* in urb->iso_frame_desc */ | |
1da177e4 LT |
464 | } __attribute__ ((aligned (32))); |
465 | ||
466 | /*-------------------------------------------------------------------------*/ | |
467 | ||
468 | /* | |
53bd6a60 | 469 | * EHCI Specification 0.95 Section 3.4 |
1da177e4 LT |
470 | * siTD, aka split-transaction isochronous Transfer Descriptor |
471 | * ... describe full speed iso xfers through TT in hubs | |
472 | * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD) | |
473 | */ | |
474 | struct ehci_sitd { | |
475 | /* first part defined by EHCI spec */ | |
6dbd682b | 476 | __hc32 hw_next; |
1da177e4 | 477 | /* uses bit field macros above - see EHCI 0.95 Table 3-8 */ |
6dbd682b SR |
478 | __hc32 hw_fullspeed_ep; /* EHCI table 3-9 */ |
479 | __hc32 hw_uframe; /* EHCI table 3-10 */ | |
480 | __hc32 hw_results; /* EHCI table 3-11 */ | |
1da177e4 LT |
481 | #define SITD_IOC (1 << 31) /* interrupt on completion */ |
482 | #define SITD_PAGE (1 << 30) /* buffer 0/1 */ | |
483 | #define SITD_LENGTH(x) (0x3ff & ((x)>>16)) | |
484 | #define SITD_STS_ACTIVE (1 << 7) /* HC may execute this */ | |
485 | #define SITD_STS_ERR (1 << 6) /* error from TT */ | |
486 | #define SITD_STS_DBE (1 << 5) /* data buffer error (in HC) */ | |
487 | #define SITD_STS_BABBLE (1 << 4) /* device was babbling */ | |
488 | #define SITD_STS_XACT (1 << 3) /* illegal IN response */ | |
489 | #define SITD_STS_MMF (1 << 2) /* incomplete split transaction */ | |
490 | #define SITD_STS_STS (1 << 1) /* split transaction state */ | |
491 | ||
6dbd682b | 492 | #define SITD_ACTIVE(ehci) cpu_to_hc32(ehci, SITD_STS_ACTIVE) |
1da177e4 | 493 | |
6dbd682b SR |
494 | __hc32 hw_buf [2]; /* EHCI table 3-12 */ |
495 | __hc32 hw_backpointer; /* EHCI table 3-13 */ | |
496 | __hc32 hw_buf_hi [2]; /* Appendix B */ | |
1da177e4 LT |
497 | |
498 | /* the rest is HCD-private */ | |
499 | dma_addr_t sitd_dma; | |
500 | union ehci_shadow sitd_next; /* ptr to periodic q entry */ | |
501 | ||
502 | struct urb *urb; | |
503 | struct ehci_iso_stream *stream; /* endpoint's queue */ | |
504 | struct list_head sitd_list; /* list of stream's sitds */ | |
505 | unsigned frame; | |
506 | unsigned index; | |
507 | } __attribute__ ((aligned (32))); | |
508 | ||
509 | /*-------------------------------------------------------------------------*/ | |
510 | ||
511 | /* | |
512 | * EHCI Specification 0.96 Section 3.7 | |
513 | * Periodic Frame Span Traversal Node (FSTN) | |
514 | * | |
515 | * Manages split interrupt transactions (using TT) that span frame boundaries | |
516 | * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN | |
517 | * makes the HC jump (back) to a QH to scan for fs/ls QH completions until | |
518 | * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work. | |
519 | */ | |
520 | struct ehci_fstn { | |
6dbd682b SR |
521 | __hc32 hw_next; /* any periodic q entry */ |
522 | __hc32 hw_prev; /* qh or EHCI_LIST_END */ | |
1da177e4 LT |
523 | |
524 | /* the rest is HCD-private */ | |
525 | dma_addr_t fstn_dma; | |
526 | union ehci_shadow fstn_next; /* ptr to periodic q entry */ | |
527 | } __attribute__ ((aligned (32))); | |
528 | ||
529 | /*-------------------------------------------------------------------------*/ | |
530 | ||
531 | #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT | |
532 | ||
533 | /* | |
534 | * Some EHCI controllers have a Transaction Translator built into the | |
535 | * root hub. This is a non-standard feature. Each controller will need | |
536 | * to add code to the following inline functions, and call them as | |
537 | * needed (mostly in root hub code). | |
538 | */ | |
539 | ||
a8e51775 | 540 | #define ehci_is_TDI(e) (ehci_to_hcd(e)->has_tt) |
1da177e4 LT |
541 | |
542 | /* Returns the speed of a device attached to a port on the root hub. */ | |
543 | static inline unsigned int | |
544 | ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc) | |
545 | { | |
546 | if (ehci_is_TDI(ehci)) { | |
547 | switch ((portsc>>26)&3) { | |
548 | case 0: | |
549 | return 0; | |
550 | case 1: | |
551 | return (1<<USB_PORT_FEAT_LOWSPEED); | |
552 | case 2: | |
553 | default: | |
554 | return (1<<USB_PORT_FEAT_HIGHSPEED); | |
555 | } | |
556 | } | |
557 | return (1<<USB_PORT_FEAT_HIGHSPEED); | |
558 | } | |
559 | ||
560 | #else | |
561 | ||
562 | #define ehci_is_TDI(e) (0) | |
563 | ||
564 | #define ehci_port_speed(ehci, portsc) (1<<USB_PORT_FEAT_HIGHSPEED) | |
565 | #endif | |
566 | ||
8cd42e97 KG |
567 | /*-------------------------------------------------------------------------*/ |
568 | ||
569 | #ifdef CONFIG_PPC_83xx | |
570 | /* Some Freescale processors have an erratum in which the TT | |
571 | * port number in the queue head was 0..N-1 instead of 1..N. | |
572 | */ | |
573 | #define ehci_has_fsl_portno_bug(e) ((e)->has_fsl_port_bug) | |
574 | #else | |
575 | #define ehci_has_fsl_portno_bug(e) (0) | |
576 | #endif | |
577 | ||
083522d7 BH |
578 | /* |
579 | * While most USB host controllers implement their registers in | |
580 | * little-endian format, a minority (celleb companion chip) implement | |
581 | * them in big endian format. | |
582 | * | |
583 | * This attempts to support either format at compile time without a | |
584 | * runtime penalty, or both formats with the additional overhead | |
585 | * of checking a flag bit. | |
586 | */ | |
587 | ||
588 | #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO | |
589 | #define ehci_big_endian_mmio(e) ((e)->big_endian_mmio) | |
590 | #else | |
591 | #define ehci_big_endian_mmio(e) 0 | |
592 | #endif | |
593 | ||
6dbd682b SR |
594 | /* |
595 | * Big-endian read/write functions are arch-specific. | |
596 | * Other arches can be added if/when they're needed. | |
6dbd682b | 597 | */ |
91bc4d31 VB |
598 | #if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX) |
599 | #define readl_be(addr) __raw_readl((__force unsigned *)addr) | |
600 | #define writel_be(val, addr) __raw_writel(val, (__force unsigned *)addr) | |
601 | #endif | |
602 | ||
6dbd682b SR |
603 | static inline unsigned int ehci_readl(const struct ehci_hcd *ehci, |
604 | __u32 __iomem * regs) | |
083522d7 | 605 | { |
d728e327 | 606 | #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO |
083522d7 | 607 | return ehci_big_endian_mmio(ehci) ? |
68f50e52 AV |
608 | readl_be(regs) : |
609 | readl(regs); | |
d728e327 | 610 | #else |
68f50e52 | 611 | return readl(regs); |
d728e327 | 612 | #endif |
083522d7 BH |
613 | } |
614 | ||
6dbd682b SR |
615 | static inline void ehci_writel(const struct ehci_hcd *ehci, |
616 | const unsigned int val, __u32 __iomem *regs) | |
083522d7 | 617 | { |
d728e327 | 618 | #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO |
083522d7 | 619 | ehci_big_endian_mmio(ehci) ? |
68f50e52 AV |
620 | writel_be(val, regs) : |
621 | writel(val, regs); | |
d728e327 | 622 | #else |
68f50e52 | 623 | writel(val, regs); |
d728e327 | 624 | #endif |
083522d7 | 625 | } |
8cd42e97 | 626 | |
796bcae7 VB |
627 | /* |
628 | * On certain ppc-44x SoC there is a HW issue, that could only worked around with | |
629 | * explicit suspend/operate of OHCI. This function hereby makes sense only on that arch. | |
630 | * Other common bits are dependant on has_amcc_usb23 quirk flag. | |
631 | */ | |
632 | #ifdef CONFIG_44x | |
633 | static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational) | |
634 | { | |
635 | u32 hc_control; | |
636 | ||
637 | hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS); | |
638 | if (operational) | |
639 | hc_control |= OHCI_USB_OPER; | |
640 | else | |
641 | hc_control |= OHCI_USB_SUSPEND; | |
642 | ||
643 | writel_be(hc_control, ehci->ohci_hcctrl_reg); | |
644 | (void) readl_be(ehci->ohci_hcctrl_reg); | |
645 | } | |
646 | #else | |
647 | static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational) | |
648 | { } | |
649 | #endif | |
650 | ||
1da177e4 LT |
651 | /*-------------------------------------------------------------------------*/ |
652 | ||
6dbd682b SR |
653 | /* |
654 | * The AMCC 440EPx not only implements its EHCI registers in big-endian | |
655 | * format, but also its DMA data structures (descriptors). | |
656 | * | |
657 | * EHCI controllers accessed through PCI work normally (little-endian | |
658 | * everywhere), so we won't bother supporting a BE-only mode for now. | |
659 | */ | |
660 | #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC | |
661 | #define ehci_big_endian_desc(e) ((e)->big_endian_desc) | |
662 | ||
663 | /* cpu to ehci */ | |
664 | static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x) | |
665 | { | |
666 | return ehci_big_endian_desc(ehci) | |
667 | ? (__force __hc32)cpu_to_be32(x) | |
668 | : (__force __hc32)cpu_to_le32(x); | |
669 | } | |
670 | ||
671 | /* ehci to cpu */ | |
672 | static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x) | |
673 | { | |
674 | return ehci_big_endian_desc(ehci) | |
675 | ? be32_to_cpu((__force __be32)x) | |
676 | : le32_to_cpu((__force __le32)x); | |
677 | } | |
678 | ||
679 | static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x) | |
680 | { | |
681 | return ehci_big_endian_desc(ehci) | |
682 | ? be32_to_cpup((__force __be32 *)x) | |
683 | : le32_to_cpup((__force __le32 *)x); | |
684 | } | |
685 | ||
686 | #else | |
687 | ||
688 | /* cpu to ehci */ | |
689 | static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x) | |
690 | { | |
691 | return cpu_to_le32(x); | |
692 | } | |
693 | ||
694 | /* ehci to cpu */ | |
695 | static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x) | |
696 | { | |
697 | return le32_to_cpu(x); | |
698 | } | |
699 | ||
700 | static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x) | |
701 | { | |
702 | return le32_to_cpup(x); | |
703 | } | |
704 | ||
705 | #endif | |
706 | ||
707 | /*-------------------------------------------------------------------------*/ | |
708 | ||
1da177e4 LT |
709 | #ifndef DEBUG |
710 | #define STUB_DEBUG_FILES | |
711 | #endif /* DEBUG */ | |
712 | ||
713 | /*-------------------------------------------------------------------------*/ | |
714 | ||
715 | #endif /* __LINUX_EHCI_HCD_H */ |