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1da177e4 LT |
1 | /* |
2 | * Copyright (c) 2001-2002 by David Brownell | |
53bd6a60 | 3 | * |
1da177e4 LT |
4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms of the GNU General Public License as published by the | |
6 | * Free Software Foundation; either version 2 of the License, or (at your | |
7 | * option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but | |
10 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
11 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 | * for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software Foundation, | |
16 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
17 | */ | |
18 | ||
19 | #ifndef __LINUX_EHCI_HCD_H | |
20 | #define __LINUX_EHCI_HCD_H | |
21 | ||
22 | /* definitions used for the EHCI driver */ | |
23 | ||
6dbd682b SR |
24 | /* |
25 | * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to | |
26 | * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on | |
27 | * the host controller implementation. | |
28 | * | |
29 | * To facilitate the strongest possible byte-order checking from "sparse" | |
30 | * and so on, we use __leXX unless that's not practical. | |
31 | */ | |
32 | #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC | |
33 | typedef __u32 __bitwise __hc32; | |
34 | typedef __u16 __bitwise __hc16; | |
35 | #else | |
36 | #define __hc32 __le32 | |
37 | #define __hc16 __le16 | |
38 | #endif | |
39 | ||
411c9403 | 40 | /* statistics can be kept for tuning/monitoring */ |
1da177e4 LT |
41 | struct ehci_stats { |
42 | /* irq usage */ | |
43 | unsigned long normal; | |
44 | unsigned long error; | |
45 | unsigned long reclaim; | |
46 | unsigned long lost_iaa; | |
47 | ||
48 | /* termination of urbs from core */ | |
49 | unsigned long complete; | |
50 | unsigned long unlink; | |
51 | }; | |
52 | ||
53 | /* ehci_hcd->lock guards shared data against other CPUs: | |
54 | * ehci_hcd: async, reclaim, periodic (and shadow), ... | |
55 | * usb_host_endpoint: hcpriv | |
56 | * ehci_qh: qh_next, qtd_list | |
57 | * ehci_qtd: qtd_list | |
58 | * | |
59 | * Also, hold this lock when talking to HC registers or | |
60 | * when updating hw_* fields in shared qh/qtd/... structures. | |
61 | */ | |
62 | ||
63 | #define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */ | |
64 | ||
65 | struct ehci_hcd { /* one per controller */ | |
56c1e26d DB |
66 | /* glue to PCI and HCD framework */ |
67 | struct ehci_caps __iomem *caps; | |
68 | struct ehci_regs __iomem *regs; | |
69 | struct ehci_dbg_port __iomem *debug; | |
70 | ||
71 | __u32 hcs_params; /* cached register copy */ | |
1da177e4 LT |
72 | spinlock_t lock; |
73 | ||
74 | /* async schedule support */ | |
75 | struct ehci_qh *async; | |
3d091a6f | 76 | struct ehci_qh *dummy; /* For AMD quirk use */ |
1da177e4 | 77 | struct ehci_qh *reclaim; |
1da177e4 LT |
78 | unsigned scanning : 1; |
79 | ||
80 | /* periodic schedule support */ | |
81 | #define DEFAULT_I_TDPS 1024 /* some HCs can do less */ | |
82 | unsigned periodic_size; | |
6dbd682b | 83 | __hc32 *periodic; /* hw periodic table */ |
1da177e4 LT |
84 | dma_addr_t periodic_dma; |
85 | unsigned i_thresh; /* uframes HC might cache */ | |
86 | ||
87 | union ehci_shadow *pshadow; /* mirror hw periodic table */ | |
88 | int next_uframe; /* scan periodic, start here */ | |
89 | unsigned periodic_sched; /* periodic activity count */ | |
90 | ||
0e5f231b | 91 | /* list of itds & sitds completed while clock_frame was still active */ |
9aa09d2f | 92 | struct list_head cached_itd_list; |
0e5f231b | 93 | struct list_head cached_sitd_list; |
9aa09d2f KW |
94 | unsigned clock_frame; |
95 | ||
1da177e4 LT |
96 | /* per root hub port */ |
97 | unsigned long reset_done [EHCI_MAX_ROOT_PORTS]; | |
383975d7 | 98 | |
57e06c11 AS |
99 | /* bit vectors (one bit per port) */ |
100 | unsigned long bus_suspended; /* which ports were | |
101 | already suspended at the start of a bus suspend */ | |
102 | unsigned long companion_ports; /* which ports are | |
103 | dedicated to the companion controller */ | |
383975d7 AS |
104 | unsigned long owned_ports; /* which ports are |
105 | owned by the companion during a bus suspend */ | |
d1f114d1 AS |
106 | unsigned long port_c_suspend; /* which ports have |
107 | the change-suspend feature turned on */ | |
eafe5b99 AS |
108 | unsigned long suspended_ports; /* which ports are |
109 | suspended */ | |
1da177e4 LT |
110 | |
111 | /* per-HC memory pools (could be per-bus, but ...) */ | |
112 | struct dma_pool *qh_pool; /* qh per active urb */ | |
113 | struct dma_pool *qtd_pool; /* one or more per qh */ | |
114 | struct dma_pool *itd_pool; /* itd per iso urb */ | |
115 | struct dma_pool *sitd_pool; /* sitd per split iso urb */ | |
116 | ||
07d29b63 | 117 | struct timer_list iaa_watchdog; |
1da177e4 | 118 | struct timer_list watchdog; |
1da177e4 LT |
119 | unsigned long actions; |
120 | unsigned stamp; | |
68335e81 | 121 | unsigned random_frame; |
1da177e4 | 122 | unsigned long next_statechange; |
ee4ecb8a | 123 | ktime_t last_periodic_enable; |
1da177e4 LT |
124 | u32 command; |
125 | ||
8cd42e97 | 126 | /* SILICON QUIRKS */ |
f8aeb3bb | 127 | unsigned no_selective_suspend:1; |
8cd42e97 | 128 | unsigned has_fsl_port_bug:1; /* FreeScale */ |
083522d7 | 129 | unsigned big_endian_mmio:1; |
6dbd682b | 130 | unsigned big_endian_desc:1; |
c430131a | 131 | unsigned big_endian_capbase:1; |
796bcae7 | 132 | unsigned has_amcc_usb23:1; |
403dbd36 | 133 | unsigned need_io_watchdog:1; |
ee4ecb8a | 134 | unsigned broken_periodic:1; |
ad93562b | 135 | unsigned amd_pll_fix:1; |
ae68a83b | 136 | unsigned fs_i_thresh:1; /* Intel iso scheduling */ |
3d091a6f | 137 | unsigned use_dummy_qh:1; /* AMD Frame List table quirk*/ |
2f7ac6c1 | 138 | unsigned has_synopsys_hc_bug:1; /* Synopsys HC */ |
796bcae7 VB |
139 | |
140 | /* required for usb32 quirk */ | |
141 | #define OHCI_CTRL_HCFS (3 << 6) | |
142 | #define OHCI_USB_OPER (2 << 6) | |
143 | #define OHCI_USB_SUSPEND (3 << 6) | |
144 | ||
145 | #define OHCI_HCCTRL_OFFSET 0x4 | |
146 | #define OHCI_HCCTRL_LEN 0x4 | |
147 | __hc32 *ohci_hcctrl_reg; | |
331ac6b2 | 148 | unsigned has_hostpc:1; |
48f24970 | 149 | unsigned has_lpm:1; /* support link power management */ |
5a9cdf33 | 150 | unsigned has_ppcd:1; /* support per-port change bits */ |
f8aeb3bb | 151 | u8 sbrn; /* packed release number */ |
1da177e4 | 152 | |
1da177e4 LT |
153 | /* irq statistics */ |
154 | #ifdef EHCI_STATS | |
155 | struct ehci_stats stats; | |
156 | # define COUNT(x) do { (x)++; } while (0) | |
157 | #else | |
158 | # define COUNT(x) do {} while (0) | |
694cc208 TJ |
159 | #endif |
160 | ||
161 | /* debug files */ | |
162 | #ifdef DEBUG | |
163 | struct dentry *debug_dir; | |
1da177e4 | 164 | #endif |
83722bc9 AG |
165 | /* |
166 | * OTG controllers and transceivers need software interaction | |
167 | */ | |
168 | struct otg_transceiver *transceiver; | |
1da177e4 LT |
169 | }; |
170 | ||
53bd6a60 | 171 | /* convert between an HCD pointer and the corresponding EHCI_HCD */ |
1da177e4 LT |
172 | static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd) |
173 | { | |
174 | return (struct ehci_hcd *) (hcd->hcd_priv); | |
175 | } | |
176 | static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci) | |
177 | { | |
178 | return container_of ((void *) ehci, struct usb_hcd, hcd_priv); | |
179 | } | |
180 | ||
181 | ||
07d29b63 AS |
182 | static inline void |
183 | iaa_watchdog_start(struct ehci_hcd *ehci) | |
184 | { | |
185 | WARN_ON(timer_pending(&ehci->iaa_watchdog)); | |
186 | mod_timer(&ehci->iaa_watchdog, | |
187 | jiffies + msecs_to_jiffies(EHCI_IAA_MSECS)); | |
188 | } | |
189 | ||
190 | static inline void iaa_watchdog_done(struct ehci_hcd *ehci) | |
191 | { | |
192 | del_timer(&ehci->iaa_watchdog); | |
193 | } | |
194 | ||
1da177e4 LT |
195 | enum ehci_timer_action { |
196 | TIMER_IO_WATCHDOG, | |
1da177e4 LT |
197 | TIMER_ASYNC_SHRINK, |
198 | TIMER_ASYNC_OFF, | |
199 | }; | |
200 | ||
201 | static inline void | |
202 | timer_action_done (struct ehci_hcd *ehci, enum ehci_timer_action action) | |
203 | { | |
204 | clear_bit (action, &ehci->actions); | |
205 | } | |
206 | ||
0e5f231b | 207 | static void free_cached_lists(struct ehci_hcd *ehci); |
9aa09d2f | 208 | |
1da177e4 LT |
209 | /*-------------------------------------------------------------------------*/ |
210 | ||
0af36739 | 211 | #include <linux/usb/ehci_def.h> |
1da177e4 LT |
212 | |
213 | /*-------------------------------------------------------------------------*/ | |
214 | ||
6dbd682b | 215 | #define QTD_NEXT(ehci, dma) cpu_to_hc32(ehci, (u32)dma) |
1da177e4 LT |
216 | |
217 | /* | |
218 | * EHCI Specification 0.95 Section 3.5 | |
53bd6a60 | 219 | * QTD: describe data transfer components (buffer, direction, ...) |
1da177e4 LT |
220 | * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram". |
221 | * | |
222 | * These are associated only with "QH" (Queue Head) structures, | |
223 | * used with control, bulk, and interrupt transfers. | |
224 | */ | |
225 | struct ehci_qtd { | |
226 | /* first part defined by EHCI spec */ | |
6dbd682b SR |
227 | __hc32 hw_next; /* see EHCI 3.5.1 */ |
228 | __hc32 hw_alt_next; /* see EHCI 3.5.2 */ | |
229 | __hc32 hw_token; /* see EHCI 3.5.3 */ | |
1da177e4 LT |
230 | #define QTD_TOGGLE (1 << 31) /* data toggle */ |
231 | #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff) | |
232 | #define QTD_IOC (1 << 15) /* interrupt on complete */ | |
233 | #define QTD_CERR(tok) (((tok)>>10) & 0x3) | |
234 | #define QTD_PID(tok) (((tok)>>8) & 0x3) | |
235 | #define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */ | |
236 | #define QTD_STS_HALT (1 << 6) /* halted on error */ | |
237 | #define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */ | |
238 | #define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */ | |
239 | #define QTD_STS_XACT (1 << 3) /* device gave illegal response */ | |
240 | #define QTD_STS_MMF (1 << 2) /* incomplete split transaction */ | |
241 | #define QTD_STS_STS (1 << 1) /* split transaction state */ | |
242 | #define QTD_STS_PING (1 << 0) /* issue PING? */ | |
6dbd682b SR |
243 | |
244 | #define ACTIVE_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_ACTIVE) | |
245 | #define HALT_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_HALT) | |
246 | #define STATUS_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_STS) | |
247 | ||
248 | __hc32 hw_buf [5]; /* see EHCI 3.5.4 */ | |
249 | __hc32 hw_buf_hi [5]; /* Appendix B */ | |
1da177e4 LT |
250 | |
251 | /* the rest is HCD-private */ | |
252 | dma_addr_t qtd_dma; /* qtd address */ | |
253 | struct list_head qtd_list; /* sw qtd list */ | |
254 | struct urb *urb; /* qtd's urb */ | |
255 | size_t length; /* length of buffer */ | |
256 | } __attribute__ ((aligned (32))); | |
257 | ||
258 | /* mask NakCnt+T in qh->hw_alt_next */ | |
6dbd682b | 259 | #define QTD_MASK(ehci) cpu_to_hc32 (ehci, ~0x1f) |
1da177e4 LT |
260 | |
261 | #define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1) | |
262 | ||
263 | /*-------------------------------------------------------------------------*/ | |
264 | ||
265 | /* type tag from {qh,itd,sitd,fstn}->hw_next */ | |
6dbd682b | 266 | #define Q_NEXT_TYPE(ehci,dma) ((dma) & cpu_to_hc32(ehci, 3 << 1)) |
1da177e4 | 267 | |
6dbd682b SR |
268 | /* |
269 | * Now the following defines are not converted using the | |
551509d2 | 270 | * cpu_to_le32() macro anymore, since we have to support |
6dbd682b SR |
271 | * "dynamic" switching between be and le support, so that the driver |
272 | * can be used on one system with SoC EHCI controller using big-endian | |
273 | * descriptors as well as a normal little-endian PCI EHCI controller. | |
274 | */ | |
1da177e4 | 275 | /* values for that type tag */ |
6dbd682b SR |
276 | #define Q_TYPE_ITD (0 << 1) |
277 | #define Q_TYPE_QH (1 << 1) | |
278 | #define Q_TYPE_SITD (2 << 1) | |
279 | #define Q_TYPE_FSTN (3 << 1) | |
1da177e4 LT |
280 | |
281 | /* next async queue entry, or pointer to interrupt/periodic QH */ | |
6dbd682b | 282 | #define QH_NEXT(ehci,dma) (cpu_to_hc32(ehci, (((u32)dma)&~0x01f)|Q_TYPE_QH)) |
1da177e4 LT |
283 | |
284 | /* for periodic/async schedules and qtd lists, mark end of list */ | |
6dbd682b | 285 | #define EHCI_LIST_END(ehci) cpu_to_hc32(ehci, 1) /* "null pointer" to hw */ |
1da177e4 LT |
286 | |
287 | /* | |
288 | * Entries in periodic shadow table are pointers to one of four kinds | |
289 | * of data structure. That's dictated by the hardware; a type tag is | |
290 | * encoded in the low bits of the hardware's periodic schedule. Use | |
291 | * Q_NEXT_TYPE to get the tag. | |
292 | * | |
293 | * For entries in the async schedule, the type tag always says "qh". | |
294 | */ | |
295 | union ehci_shadow { | |
53bd6a60 | 296 | struct ehci_qh *qh; /* Q_TYPE_QH */ |
1da177e4 LT |
297 | struct ehci_itd *itd; /* Q_TYPE_ITD */ |
298 | struct ehci_sitd *sitd; /* Q_TYPE_SITD */ | |
299 | struct ehci_fstn *fstn; /* Q_TYPE_FSTN */ | |
6dbd682b | 300 | __hc32 *hw_next; /* (all types) */ |
1da177e4 LT |
301 | void *ptr; |
302 | }; | |
303 | ||
304 | /*-------------------------------------------------------------------------*/ | |
305 | ||
306 | /* | |
307 | * EHCI Specification 0.95 Section 3.6 | |
308 | * QH: describes control/bulk/interrupt endpoints | |
309 | * See Fig 3-7 "Queue Head Structure Layout". | |
310 | * | |
311 | * These appear in both the async and (for interrupt) periodic schedules. | |
312 | */ | |
313 | ||
3807e26d AD |
314 | /* first part defined by EHCI spec */ |
315 | struct ehci_qh_hw { | |
6dbd682b SR |
316 | __hc32 hw_next; /* see EHCI 3.6.1 */ |
317 | __hc32 hw_info1; /* see EHCI 3.6.2 */ | |
1da177e4 | 318 | #define QH_HEAD 0x00008000 |
6dbd682b | 319 | __hc32 hw_info2; /* see EHCI 3.6.2 */ |
7dedacf4 DB |
320 | #define QH_SMASK 0x000000ff |
321 | #define QH_CMASK 0x0000ff00 | |
322 | #define QH_HUBADDR 0x007f0000 | |
323 | #define QH_HUBPORT 0x3f800000 | |
324 | #define QH_MULT 0xc0000000 | |
6dbd682b | 325 | __hc32 hw_current; /* qtd list - see EHCI 3.6.4 */ |
53bd6a60 | 326 | |
1da177e4 | 327 | /* qtd overlay (hardware parts of a struct ehci_qtd) */ |
6dbd682b SR |
328 | __hc32 hw_qtd_next; |
329 | __hc32 hw_alt_next; | |
330 | __hc32 hw_token; | |
331 | __hc32 hw_buf [5]; | |
332 | __hc32 hw_buf_hi [5]; | |
3807e26d | 333 | } __attribute__ ((aligned(32))); |
1da177e4 | 334 | |
3807e26d AD |
335 | struct ehci_qh { |
336 | struct ehci_qh_hw *hw; | |
1da177e4 LT |
337 | /* the rest is HCD-private */ |
338 | dma_addr_t qh_dma; /* address of qh */ | |
339 | union ehci_shadow qh_next; /* ptr to qh; or periodic */ | |
340 | struct list_head qtd_list; /* sw qtd list */ | |
341 | struct ehci_qtd *dummy; | |
342 | struct ehci_qh *reclaim; /* next to reclaim */ | |
343 | ||
344 | struct ehci_hcd *ehci; | |
9c033e81 DB |
345 | |
346 | /* | |
347 | * Do NOT use atomic operations for QH refcounting. On some CPUs | |
348 | * (PPC7448 for example), atomic operations cannot be performed on | |
349 | * memory that is cache-inhibited (i.e. being used for DMA). | |
350 | * Spinlocks are used to protect all QH fields. | |
351 | */ | |
352 | u32 refcount; | |
1da177e4 LT |
353 | unsigned stamp; |
354 | ||
3a44494e | 355 | u8 needs_rescan; /* Dequeue during giveback */ |
1da177e4 LT |
356 | u8 qh_state; |
357 | #define QH_STATE_LINKED 1 /* HC sees this */ | |
358 | #define QH_STATE_UNLINK 2 /* HC may still see this */ | |
359 | #define QH_STATE_IDLE 3 /* HC doesn't see this */ | |
360 | #define QH_STATE_UNLINK_WAIT 4 /* LINKED and on reclaim q */ | |
361 | #define QH_STATE_COMPLETING 5 /* don't touch token.HALT */ | |
362 | ||
a2c2706e AS |
363 | u8 xacterrs; /* XactErr retry counter */ |
364 | #define QH_XACTERR_MAX 32 /* XactErr retry limit */ | |
365 | ||
1da177e4 LT |
366 | /* periodic schedule info */ |
367 | u8 usecs; /* intr bandwidth */ | |
368 | u8 gap_uf; /* uframes split/csplit gap */ | |
369 | u8 c_usecs; /* ... split completion bw */ | |
d0384200 | 370 | u16 tt_usecs; /* tt downstream bandwidth */ |
1da177e4 LT |
371 | unsigned short period; /* polling interval */ |
372 | unsigned short start; /* where polling starts */ | |
373 | #define NO_FRAME ((unsigned short)~0) /* pick new start */ | |
914b7012 | 374 | |
1da177e4 | 375 | struct usb_device *dev; /* access to TT */ |
914b7012 | 376 | unsigned clearing_tt:1; /* Clear-TT-Buf in progress */ |
3807e26d | 377 | }; |
1da177e4 LT |
378 | |
379 | /*-------------------------------------------------------------------------*/ | |
380 | ||
381 | /* description of one iso transaction (up to 3 KB data if highspeed) */ | |
382 | struct ehci_iso_packet { | |
383 | /* These will be copied to iTD when scheduling */ | |
384 | u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */ | |
6dbd682b | 385 | __hc32 transaction; /* itd->hw_transaction[i] |= */ |
1da177e4 LT |
386 | u8 cross; /* buf crosses pages */ |
387 | /* for full speed OUT splits */ | |
388 | u32 buf1; | |
389 | }; | |
390 | ||
391 | /* temporary schedule data for packets from iso urbs (both speeds) | |
392 | * each packet is one logical usb transaction to the device (not TT), | |
393 | * beginning at stream->next_uframe | |
394 | */ | |
395 | struct ehci_iso_sched { | |
396 | struct list_head td_list; | |
397 | unsigned span; | |
398 | struct ehci_iso_packet packet [0]; | |
399 | }; | |
400 | ||
401 | /* | |
402 | * ehci_iso_stream - groups all (s)itds for this endpoint. | |
403 | * acts like a qh would, if EHCI had them for ISO. | |
404 | */ | |
405 | struct ehci_iso_stream { | |
1082f57a CL |
406 | /* first field matches ehci_hq, but is NULL */ |
407 | struct ehci_qh_hw *hw; | |
1da177e4 LT |
408 | |
409 | u32 refcount; | |
410 | u8 bEndpointAddress; | |
411 | u8 highspeed; | |
1da177e4 LT |
412 | struct list_head td_list; /* queued itds/sitds */ |
413 | struct list_head free_list; /* list of unused itds/sitds */ | |
414 | struct usb_device *udev; | |
53bd6a60 | 415 | struct usb_host_endpoint *ep; |
1da177e4 LT |
416 | |
417 | /* output of (re)scheduling */ | |
1da177e4 | 418 | int next_uframe; |
6dbd682b | 419 | __hc32 splits; |
1da177e4 LT |
420 | |
421 | /* the rest is derived from the endpoint descriptor, | |
422 | * trusting urb->interval == f(epdesc->bInterval) and | |
423 | * including the extra info for hw_bufp[0..2] | |
424 | */ | |
1da177e4 | 425 | u8 usecs, c_usecs; |
c06d4dcf | 426 | u16 interval; |
d0384200 | 427 | u16 tt_usecs; |
1da177e4 LT |
428 | u16 maxp; |
429 | u16 raw_mask; | |
430 | unsigned bandwidth; | |
431 | ||
432 | /* This is used to initialize iTD's hw_bufp fields */ | |
6dbd682b SR |
433 | __hc32 buf0; |
434 | __hc32 buf1; | |
435 | __hc32 buf2; | |
1da177e4 LT |
436 | |
437 | /* this is used to initialize sITD's tt info */ | |
6dbd682b | 438 | __hc32 address; |
1da177e4 LT |
439 | }; |
440 | ||
441 | /*-------------------------------------------------------------------------*/ | |
442 | ||
443 | /* | |
444 | * EHCI Specification 0.95 Section 3.3 | |
445 | * Fig 3-4 "Isochronous Transaction Descriptor (iTD)" | |
446 | * | |
447 | * Schedule records for high speed iso xfers | |
448 | */ | |
449 | struct ehci_itd { | |
450 | /* first part defined by EHCI spec */ | |
6dbd682b SR |
451 | __hc32 hw_next; /* see EHCI 3.3.1 */ |
452 | __hc32 hw_transaction [8]; /* see EHCI 3.3.2 */ | |
1da177e4 LT |
453 | #define EHCI_ISOC_ACTIVE (1<<31) /* activate transfer this slot */ |
454 | #define EHCI_ISOC_BUF_ERR (1<<30) /* Data buffer error */ | |
455 | #define EHCI_ISOC_BABBLE (1<<29) /* babble detected */ | |
456 | #define EHCI_ISOC_XACTERR (1<<28) /* XactErr - transaction error */ | |
457 | #define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff) | |
458 | #define EHCI_ITD_IOC (1 << 15) /* interrupt on complete */ | |
459 | ||
6dbd682b | 460 | #define ITD_ACTIVE(ehci) cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE) |
1da177e4 | 461 | |
6dbd682b SR |
462 | __hc32 hw_bufp [7]; /* see EHCI 3.3.3 */ |
463 | __hc32 hw_bufp_hi [7]; /* Appendix B */ | |
1da177e4 LT |
464 | |
465 | /* the rest is HCD-private */ | |
466 | dma_addr_t itd_dma; /* for this itd */ | |
467 | union ehci_shadow itd_next; /* ptr to periodic q entry */ | |
468 | ||
469 | struct urb *urb; | |
470 | struct ehci_iso_stream *stream; /* endpoint's queue */ | |
471 | struct list_head itd_list; /* list of stream's itds */ | |
472 | ||
473 | /* any/all hw_transactions here may be used by that urb */ | |
474 | unsigned frame; /* where scheduled */ | |
475 | unsigned pg; | |
476 | unsigned index[8]; /* in urb->iso_frame_desc */ | |
1da177e4 LT |
477 | } __attribute__ ((aligned (32))); |
478 | ||
479 | /*-------------------------------------------------------------------------*/ | |
480 | ||
481 | /* | |
53bd6a60 | 482 | * EHCI Specification 0.95 Section 3.4 |
1da177e4 LT |
483 | * siTD, aka split-transaction isochronous Transfer Descriptor |
484 | * ... describe full speed iso xfers through TT in hubs | |
485 | * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD) | |
486 | */ | |
487 | struct ehci_sitd { | |
488 | /* first part defined by EHCI spec */ | |
6dbd682b | 489 | __hc32 hw_next; |
1da177e4 | 490 | /* uses bit field macros above - see EHCI 0.95 Table 3-8 */ |
6dbd682b SR |
491 | __hc32 hw_fullspeed_ep; /* EHCI table 3-9 */ |
492 | __hc32 hw_uframe; /* EHCI table 3-10 */ | |
493 | __hc32 hw_results; /* EHCI table 3-11 */ | |
1da177e4 LT |
494 | #define SITD_IOC (1 << 31) /* interrupt on completion */ |
495 | #define SITD_PAGE (1 << 30) /* buffer 0/1 */ | |
496 | #define SITD_LENGTH(x) (0x3ff & ((x)>>16)) | |
497 | #define SITD_STS_ACTIVE (1 << 7) /* HC may execute this */ | |
498 | #define SITD_STS_ERR (1 << 6) /* error from TT */ | |
499 | #define SITD_STS_DBE (1 << 5) /* data buffer error (in HC) */ | |
500 | #define SITD_STS_BABBLE (1 << 4) /* device was babbling */ | |
501 | #define SITD_STS_XACT (1 << 3) /* illegal IN response */ | |
502 | #define SITD_STS_MMF (1 << 2) /* incomplete split transaction */ | |
503 | #define SITD_STS_STS (1 << 1) /* split transaction state */ | |
504 | ||
6dbd682b | 505 | #define SITD_ACTIVE(ehci) cpu_to_hc32(ehci, SITD_STS_ACTIVE) |
1da177e4 | 506 | |
6dbd682b SR |
507 | __hc32 hw_buf [2]; /* EHCI table 3-12 */ |
508 | __hc32 hw_backpointer; /* EHCI table 3-13 */ | |
509 | __hc32 hw_buf_hi [2]; /* Appendix B */ | |
1da177e4 LT |
510 | |
511 | /* the rest is HCD-private */ | |
512 | dma_addr_t sitd_dma; | |
513 | union ehci_shadow sitd_next; /* ptr to periodic q entry */ | |
514 | ||
515 | struct urb *urb; | |
516 | struct ehci_iso_stream *stream; /* endpoint's queue */ | |
517 | struct list_head sitd_list; /* list of stream's sitds */ | |
518 | unsigned frame; | |
519 | unsigned index; | |
520 | } __attribute__ ((aligned (32))); | |
521 | ||
522 | /*-------------------------------------------------------------------------*/ | |
523 | ||
524 | /* | |
525 | * EHCI Specification 0.96 Section 3.7 | |
526 | * Periodic Frame Span Traversal Node (FSTN) | |
527 | * | |
528 | * Manages split interrupt transactions (using TT) that span frame boundaries | |
529 | * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN | |
530 | * makes the HC jump (back) to a QH to scan for fs/ls QH completions until | |
531 | * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work. | |
532 | */ | |
533 | struct ehci_fstn { | |
6dbd682b SR |
534 | __hc32 hw_next; /* any periodic q entry */ |
535 | __hc32 hw_prev; /* qh or EHCI_LIST_END */ | |
1da177e4 LT |
536 | |
537 | /* the rest is HCD-private */ | |
538 | dma_addr_t fstn_dma; | |
539 | union ehci_shadow fstn_next; /* ptr to periodic q entry */ | |
540 | } __attribute__ ((aligned (32))); | |
541 | ||
542 | /*-------------------------------------------------------------------------*/ | |
543 | ||
16032c4f AS |
544 | /* Prepare the PORTSC wakeup flags during controller suspend/resume */ |
545 | ||
4147200d AS |
546 | #define ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup) \ |
547 | ehci_adjust_port_wakeup_flags(ehci, true, do_wakeup); | |
16032c4f | 548 | |
4147200d AS |
549 | #define ehci_prepare_ports_for_controller_resume(ehci) \ |
550 | ehci_adjust_port_wakeup_flags(ehci, false, false); | |
16032c4f AS |
551 | |
552 | /*-------------------------------------------------------------------------*/ | |
553 | ||
1da177e4 LT |
554 | #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT |
555 | ||
556 | /* | |
557 | * Some EHCI controllers have a Transaction Translator built into the | |
558 | * root hub. This is a non-standard feature. Each controller will need | |
559 | * to add code to the following inline functions, and call them as | |
560 | * needed (mostly in root hub code). | |
561 | */ | |
562 | ||
a8e51775 | 563 | #define ehci_is_TDI(e) (ehci_to_hcd(e)->has_tt) |
1da177e4 LT |
564 | |
565 | /* Returns the speed of a device attached to a port on the root hub. */ | |
566 | static inline unsigned int | |
567 | ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc) | |
568 | { | |
569 | if (ehci_is_TDI(ehci)) { | |
331ac6b2 | 570 | switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) { |
1da177e4 LT |
571 | case 0: |
572 | return 0; | |
573 | case 1: | |
288ead45 | 574 | return USB_PORT_STAT_LOW_SPEED; |
1da177e4 LT |
575 | case 2: |
576 | default: | |
288ead45 | 577 | return USB_PORT_STAT_HIGH_SPEED; |
1da177e4 LT |
578 | } |
579 | } | |
288ead45 | 580 | return USB_PORT_STAT_HIGH_SPEED; |
1da177e4 LT |
581 | } |
582 | ||
583 | #else | |
584 | ||
585 | #define ehci_is_TDI(e) (0) | |
586 | ||
288ead45 | 587 | #define ehci_port_speed(ehci, portsc) USB_PORT_STAT_HIGH_SPEED |
1da177e4 LT |
588 | #endif |
589 | ||
8cd42e97 KG |
590 | /*-------------------------------------------------------------------------*/ |
591 | ||
592 | #ifdef CONFIG_PPC_83xx | |
593 | /* Some Freescale processors have an erratum in which the TT | |
594 | * port number in the queue head was 0..N-1 instead of 1..N. | |
595 | */ | |
596 | #define ehci_has_fsl_portno_bug(e) ((e)->has_fsl_port_bug) | |
597 | #else | |
598 | #define ehci_has_fsl_portno_bug(e) (0) | |
599 | #endif | |
600 | ||
083522d7 BH |
601 | /* |
602 | * While most USB host controllers implement their registers in | |
603 | * little-endian format, a minority (celleb companion chip) implement | |
604 | * them in big endian format. | |
605 | * | |
606 | * This attempts to support either format at compile time without a | |
607 | * runtime penalty, or both formats with the additional overhead | |
608 | * of checking a flag bit. | |
c430131a JA |
609 | * |
610 | * ehci_big_endian_capbase is a special quirk for controllers that | |
611 | * implement the HC capability registers as separate registers and not | |
612 | * as fields of a 32-bit register. | |
083522d7 BH |
613 | */ |
614 | ||
615 | #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO | |
616 | #define ehci_big_endian_mmio(e) ((e)->big_endian_mmio) | |
c430131a | 617 | #define ehci_big_endian_capbase(e) ((e)->big_endian_capbase) |
083522d7 BH |
618 | #else |
619 | #define ehci_big_endian_mmio(e) 0 | |
c430131a | 620 | #define ehci_big_endian_capbase(e) 0 |
083522d7 BH |
621 | #endif |
622 | ||
6dbd682b SR |
623 | /* |
624 | * Big-endian read/write functions are arch-specific. | |
625 | * Other arches can be added if/when they're needed. | |
6dbd682b | 626 | */ |
91bc4d31 VB |
627 | #if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX) |
628 | #define readl_be(addr) __raw_readl((__force unsigned *)addr) | |
629 | #define writel_be(val, addr) __raw_writel(val, (__force unsigned *)addr) | |
9be03929 JA |
630 | #elif defined(CONFIG_SPARC_LEON) |
631 | #define readl_be(addr) __raw_readl(addr) | |
632 | #define writel_be(val, addr) __raw_writel(val, addr) | |
91bc4d31 VB |
633 | #endif |
634 | ||
6dbd682b SR |
635 | static inline unsigned int ehci_readl(const struct ehci_hcd *ehci, |
636 | __u32 __iomem * regs) | |
083522d7 | 637 | { |
d728e327 | 638 | #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO |
083522d7 | 639 | return ehci_big_endian_mmio(ehci) ? |
68f50e52 AV |
640 | readl_be(regs) : |
641 | readl(regs); | |
d728e327 | 642 | #else |
68f50e52 | 643 | return readl(regs); |
d728e327 | 644 | #endif |
083522d7 BH |
645 | } |
646 | ||
6dbd682b SR |
647 | static inline void ehci_writel(const struct ehci_hcd *ehci, |
648 | const unsigned int val, __u32 __iomem *regs) | |
083522d7 | 649 | { |
d728e327 | 650 | #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO |
083522d7 | 651 | ehci_big_endian_mmio(ehci) ? |
68f50e52 AV |
652 | writel_be(val, regs) : |
653 | writel(val, regs); | |
d728e327 | 654 | #else |
68f50e52 | 655 | writel(val, regs); |
d728e327 | 656 | #endif |
083522d7 | 657 | } |
8cd42e97 | 658 | |
796bcae7 VB |
659 | /* |
660 | * On certain ppc-44x SoC there is a HW issue, that could only worked around with | |
661 | * explicit suspend/operate of OHCI. This function hereby makes sense only on that arch. | |
25985edc | 662 | * Other common bits are dependent on has_amcc_usb23 quirk flag. |
796bcae7 VB |
663 | */ |
664 | #ifdef CONFIG_44x | |
665 | static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational) | |
666 | { | |
667 | u32 hc_control; | |
668 | ||
669 | hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS); | |
670 | if (operational) | |
671 | hc_control |= OHCI_USB_OPER; | |
672 | else | |
673 | hc_control |= OHCI_USB_SUSPEND; | |
674 | ||
675 | writel_be(hc_control, ehci->ohci_hcctrl_reg); | |
676 | (void) readl_be(ehci->ohci_hcctrl_reg); | |
677 | } | |
678 | #else | |
679 | static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational) | |
680 | { } | |
681 | #endif | |
682 | ||
1da177e4 LT |
683 | /*-------------------------------------------------------------------------*/ |
684 | ||
6dbd682b SR |
685 | /* |
686 | * The AMCC 440EPx not only implements its EHCI registers in big-endian | |
687 | * format, but also its DMA data structures (descriptors). | |
688 | * | |
689 | * EHCI controllers accessed through PCI work normally (little-endian | |
690 | * everywhere), so we won't bother supporting a BE-only mode for now. | |
691 | */ | |
692 | #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC | |
693 | #define ehci_big_endian_desc(e) ((e)->big_endian_desc) | |
694 | ||
695 | /* cpu to ehci */ | |
696 | static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x) | |
697 | { | |
698 | return ehci_big_endian_desc(ehci) | |
699 | ? (__force __hc32)cpu_to_be32(x) | |
700 | : (__force __hc32)cpu_to_le32(x); | |
701 | } | |
702 | ||
703 | /* ehci to cpu */ | |
704 | static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x) | |
705 | { | |
706 | return ehci_big_endian_desc(ehci) | |
707 | ? be32_to_cpu((__force __be32)x) | |
708 | : le32_to_cpu((__force __le32)x); | |
709 | } | |
710 | ||
711 | static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x) | |
712 | { | |
713 | return ehci_big_endian_desc(ehci) | |
714 | ? be32_to_cpup((__force __be32 *)x) | |
715 | : le32_to_cpup((__force __le32 *)x); | |
716 | } | |
717 | ||
718 | #else | |
719 | ||
720 | /* cpu to ehci */ | |
721 | static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x) | |
722 | { | |
723 | return cpu_to_le32(x); | |
724 | } | |
725 | ||
726 | /* ehci to cpu */ | |
727 | static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x) | |
728 | { | |
729 | return le32_to_cpu(x); | |
730 | } | |
731 | ||
732 | static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x) | |
733 | { | |
734 | return le32_to_cpup(x); | |
735 | } | |
736 | ||
737 | #endif | |
738 | ||
739 | /*-------------------------------------------------------------------------*/ | |
740 | ||
1da177e4 LT |
741 | #ifndef DEBUG |
742 | #define STUB_DEBUG_FILES | |
743 | #endif /* DEBUG */ | |
744 | ||
745 | /*-------------------------------------------------------------------------*/ | |
746 | ||
747 | #endif /* __LINUX_EHCI_HCD_H */ |