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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
7d50195f FHC |
2 | #ifndef __LINUX_FOTG210_H |
3 | #define __LINUX_FOTG210_H | |
4 | ||
b1f6ccf5 CR |
5 | #include <linux/usb/ehci-dbgp.h> |
6 | ||
7d50195f FHC |
7 | /* definitions used for the EHCI driver */ |
8 | ||
9 | /* | |
10 | * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to | |
11 | * __leXX (normally) or __beXX (given FOTG210_BIG_ENDIAN_DESC), depending on | |
12 | * the host controller implementation. | |
13 | * | |
14 | * To facilitate the strongest possible byte-order checking from "sparse" | |
15 | * and so on, we use __leXX unless that's not practical. | |
16 | */ | |
17 | #define __hc32 __le32 | |
18 | #define __hc16 __le16 | |
19 | ||
20 | /* statistics can be kept for tuning/monitoring */ | |
21 | struct fotg210_stats { | |
22 | /* irq usage */ | |
23 | unsigned long normal; | |
24 | unsigned long error; | |
25 | unsigned long iaa; | |
26 | unsigned long lost_iaa; | |
27 | ||
28 | /* termination of urbs from core */ | |
29 | unsigned long complete; | |
30 | unsigned long unlink; | |
31 | }; | |
32 | ||
33 | /* fotg210_hcd->lock guards shared data against other CPUs: | |
34 | * fotg210_hcd: async, unlink, periodic (and shadow), ... | |
35 | * usb_host_endpoint: hcpriv | |
36 | * fotg210_qh: qh_next, qtd_list | |
37 | * fotg210_qtd: qtd_list | |
38 | * | |
39 | * Also, hold this lock when talking to HC registers or | |
40 | * when updating hw_* fields in shared qh/qtd/... structures. | |
41 | */ | |
42 | ||
43 | #define FOTG210_MAX_ROOT_PORTS 1 /* see HCS_N_PORTS */ | |
44 | ||
45 | /* | |
46 | * fotg210_rh_state values of FOTG210_RH_RUNNING or above mean that the | |
47 | * controller may be doing DMA. Lower values mean there's no DMA. | |
48 | */ | |
49 | enum fotg210_rh_state { | |
50 | FOTG210_RH_HALTED, | |
51 | FOTG210_RH_SUSPENDED, | |
52 | FOTG210_RH_RUNNING, | |
53 | FOTG210_RH_STOPPING | |
54 | }; | |
55 | ||
56 | /* | |
57 | * Timer events, ordered by increasing delay length. | |
58 | * Always update event_delays_ns[] and event_handlers[] (defined in | |
59 | * ehci-timer.c) in parallel with this list. | |
60 | */ | |
61 | enum fotg210_hrtimer_event { | |
62 | FOTG210_HRTIMER_POLL_ASS, /* Poll for async schedule off */ | |
63 | FOTG210_HRTIMER_POLL_PSS, /* Poll for periodic schedule off */ | |
64 | FOTG210_HRTIMER_POLL_DEAD, /* Wait for dead controller to stop */ | |
65 | FOTG210_HRTIMER_UNLINK_INTR, /* Wait for interrupt QH unlink */ | |
66 | FOTG210_HRTIMER_FREE_ITDS, /* Wait for unused iTDs and siTDs */ | |
67 | FOTG210_HRTIMER_ASYNC_UNLINKS, /* Unlink empty async QHs */ | |
68 | FOTG210_HRTIMER_IAA_WATCHDOG, /* Handle lost IAA interrupts */ | |
69 | FOTG210_HRTIMER_DISABLE_PERIODIC, /* Wait to disable periodic sched */ | |
70 | FOTG210_HRTIMER_DISABLE_ASYNC, /* Wait to disable async sched */ | |
71 | FOTG210_HRTIMER_IO_WATCHDOG, /* Check for missing IRQs */ | |
72 | FOTG210_HRTIMER_NUM_EVENTS /* Must come last */ | |
73 | }; | |
74 | #define FOTG210_HRTIMER_NO_EVENT 99 | |
75 | ||
76 | struct fotg210_hcd { /* one per controller */ | |
77 | /* timing support */ | |
78 | enum fotg210_hrtimer_event next_hrtimer_event; | |
79 | unsigned enabled_hrtimer_events; | |
80 | ktime_t hr_timeouts[FOTG210_HRTIMER_NUM_EVENTS]; | |
81 | struct hrtimer hrtimer; | |
82 | ||
83 | int PSS_poll_count; | |
84 | int ASS_poll_count; | |
85 | int died_poll_count; | |
86 | ||
87 | /* glue to PCI and HCD framework */ | |
88 | struct fotg210_caps __iomem *caps; | |
89 | struct fotg210_regs __iomem *regs; | |
9183b364 | 90 | struct ehci_dbg_port __iomem *debug; |
7d50195f FHC |
91 | |
92 | __u32 hcs_params; /* cached register copy */ | |
93 | spinlock_t lock; | |
94 | enum fotg210_rh_state rh_state; | |
95 | ||
96 | /* general schedule support */ | |
97 | bool scanning:1; | |
98 | bool need_rescan:1; | |
99 | bool intr_unlinking:1; | |
100 | bool async_unlinking:1; | |
101 | bool shutdown:1; | |
102 | struct fotg210_qh *qh_scan_next; | |
103 | ||
104 | /* async schedule support */ | |
105 | struct fotg210_qh *async; | |
106 | struct fotg210_qh *dummy; /* For AMD quirk use */ | |
107 | struct fotg210_qh *async_unlink; | |
108 | struct fotg210_qh *async_unlink_last; | |
109 | struct fotg210_qh *async_iaa; | |
110 | unsigned async_unlink_cycle; | |
111 | unsigned async_count; /* async activity count */ | |
112 | ||
113 | /* periodic schedule support */ | |
114 | #define DEFAULT_I_TDPS 1024 /* some HCs can do less */ | |
115 | unsigned periodic_size; | |
116 | __hc32 *periodic; /* hw periodic table */ | |
117 | dma_addr_t periodic_dma; | |
118 | struct list_head intr_qh_list; | |
119 | unsigned i_thresh; /* uframes HC might cache */ | |
120 | ||
121 | union fotg210_shadow *pshadow; /* mirror hw periodic table */ | |
122 | struct fotg210_qh *intr_unlink; | |
123 | struct fotg210_qh *intr_unlink_last; | |
124 | unsigned intr_unlink_cycle; | |
125 | unsigned now_frame; /* frame from HC hardware */ | |
126 | unsigned next_frame; /* scan periodic, start here */ | |
127 | unsigned intr_count; /* intr activity count */ | |
128 | unsigned isoc_count; /* isoc activity count */ | |
129 | unsigned periodic_count; /* periodic activity count */ | |
130 | /* max periodic time per uframe */ | |
131 | unsigned uframe_periodic_max; | |
132 | ||
133 | ||
134 | /* list of itds completed while now_frame was still active */ | |
135 | struct list_head cached_itd_list; | |
136 | struct fotg210_itd *last_itd_to_free; | |
137 | ||
138 | /* per root hub port */ | |
139 | unsigned long reset_done[FOTG210_MAX_ROOT_PORTS]; | |
140 | ||
259127ba PST |
141 | /* bit vectors (one bit per port) |
142 | * which ports were already suspended at the start of a bus suspend | |
143 | */ | |
144 | unsigned long bus_suspended; | |
145 | ||
146 | /* which ports are edicated to the companion controller */ | |
147 | unsigned long companion_ports; | |
148 | ||
149 | /* which ports are owned by the companion during a bus suspend */ | |
150 | unsigned long owned_ports; | |
151 | ||
152 | /* which ports have the change-suspend feature turned on */ | |
153 | unsigned long port_c_suspend; | |
154 | ||
155 | /* which ports are suspended */ | |
156 | unsigned long suspended_ports; | |
157 | ||
158 | /* which ports have started to resume */ | |
159 | unsigned long resuming_ports; | |
7d50195f FHC |
160 | |
161 | /* per-HC memory pools (could be per-bus, but ...) */ | |
162 | struct dma_pool *qh_pool; /* qh per active urb */ | |
163 | struct dma_pool *qtd_pool; /* one or more per qh */ | |
164 | struct dma_pool *itd_pool; /* itd per iso urb */ | |
165 | ||
166 | unsigned random_frame; | |
167 | unsigned long next_statechange; | |
168 | ktime_t last_periodic_enable; | |
169 | u32 command; | |
170 | ||
171 | /* SILICON QUIRKS */ | |
172 | unsigned need_io_watchdog:1; | |
173 | unsigned fs_i_thresh:1; /* Intel iso scheduling */ | |
174 | ||
175 | u8 sbrn; /* packed release number */ | |
176 | ||
177 | /* irq statistics */ | |
178 | #ifdef FOTG210_STATS | |
179 | struct fotg210_stats stats; | |
a0ef2bdf | 180 | # define INCR(x) ((x)++) |
7d50195f | 181 | #else |
a0ef2bdf | 182 | # define INCR(x) do {} while (0) |
7d50195f FHC |
183 | #endif |
184 | ||
ffa8a31b LW |
185 | /* silicon clock */ |
186 | struct clk *pclk; | |
187 | ||
7d50195f | 188 | /* debug files */ |
7d50195f | 189 | struct dentry *debug_dir; |
7d50195f FHC |
190 | }; |
191 | ||
192 | /* convert between an HCD pointer and the corresponding FOTG210_HCD */ | |
193 | static inline struct fotg210_hcd *hcd_to_fotg210(struct usb_hcd *hcd) | |
194 | { | |
195 | return (struct fotg210_hcd *)(hcd->hcd_priv); | |
196 | } | |
197 | static inline struct usb_hcd *fotg210_to_hcd(struct fotg210_hcd *fotg210) | |
198 | { | |
199 | return container_of((void *) fotg210, struct usb_hcd, hcd_priv); | |
200 | } | |
201 | ||
202 | /*-------------------------------------------------------------------------*/ | |
203 | ||
204 | /* EHCI register interface, corresponds to EHCI Revision 0.95 specification */ | |
205 | ||
206 | /* Section 2.2 Host Controller Capability Registers */ | |
207 | struct fotg210_caps { | |
208 | /* these fields are specified as 8 and 16 bit registers, | |
209 | * but some hosts can't perform 8 or 16 bit PCI accesses. | |
210 | * some hosts treat caplength and hciversion as parts of a 32-bit | |
211 | * register, others treat them as two separate registers, this | |
212 | * affects the memory map for big endian controllers. | |
213 | */ | |
214 | u32 hc_capbase; | |
215 | #define HC_LENGTH(fotg210, p) (0x00ff&((p) >> /* bits 7:0 / offset 00h */ \ | |
216 | (fotg210_big_endian_capbase(fotg210) ? 24 : 0))) | |
217 | #define HC_VERSION(fotg210, p) (0xffff&((p) >> /* bits 31:16 / offset 02h */ \ | |
218 | (fotg210_big_endian_capbase(fotg210) ? 0 : 16))) | |
219 | u32 hcs_params; /* HCSPARAMS - offset 0x4 */ | |
220 | #define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */ | |
221 | ||
222 | u32 hcc_params; /* HCCPARAMS - offset 0x8 */ | |
223 | #define HCC_CANPARK(p) ((p)&(1 << 2)) /* true: can park on async qh */ | |
224 | #define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1)) /* true: periodic_size changes*/ | |
225 | u8 portroute[8]; /* nibbles for routing - offset 0xC */ | |
226 | }; | |
227 | ||
228 | ||
229 | /* Section 2.3 Host Controller Operational Registers */ | |
230 | struct fotg210_regs { | |
231 | ||
232 | /* USBCMD: offset 0x00 */ | |
233 | u32 command; | |
234 | ||
235 | /* EHCI 1.1 addendum */ | |
236 | /* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */ | |
237 | #define CMD_PARK (1<<11) /* enable "park" on async qh */ | |
238 | #define CMD_PARK_CNT(c) (((c)>>8)&3) /* how many transfers to park for */ | |
239 | #define CMD_IAAD (1<<6) /* "doorbell" interrupt async advance */ | |
240 | #define CMD_ASE (1<<5) /* async schedule enable */ | |
241 | #define CMD_PSE (1<<4) /* periodic schedule enable */ | |
242 | /* 3:2 is periodic frame list size */ | |
243 | #define CMD_RESET (1<<1) /* reset HC not bus */ | |
244 | #define CMD_RUN (1<<0) /* start/stop HC */ | |
245 | ||
246 | /* USBSTS: offset 0x04 */ | |
247 | u32 status; | |
248 | #define STS_ASS (1<<15) /* Async Schedule Status */ | |
249 | #define STS_PSS (1<<14) /* Periodic Schedule Status */ | |
250 | #define STS_RECL (1<<13) /* Reclamation */ | |
251 | #define STS_HALT (1<<12) /* Not running (any reason) */ | |
252 | /* some bits reserved */ | |
253 | /* these STS_* flags are also intr_enable bits (USBINTR) */ | |
254 | #define STS_IAA (1<<5) /* Interrupted on async advance */ | |
255 | #define STS_FATAL (1<<4) /* such as some PCI access errors */ | |
256 | #define STS_FLR (1<<3) /* frame list rolled over */ | |
257 | #define STS_PCD (1<<2) /* port change detect */ | |
258 | #define STS_ERR (1<<1) /* "error" completion (overflow, ...) */ | |
259 | #define STS_INT (1<<0) /* "normal" completion (short, ...) */ | |
260 | ||
261 | /* USBINTR: offset 0x08 */ | |
262 | u32 intr_enable; | |
263 | ||
264 | /* FRINDEX: offset 0x0C */ | |
265 | u32 frame_index; /* current microframe number */ | |
266 | /* CTRLDSSEGMENT: offset 0x10 */ | |
267 | u32 segment; /* address bits 63:32 if needed */ | |
268 | /* PERIODICLISTBASE: offset 0x14 */ | |
269 | u32 frame_list; /* points to periodic list */ | |
270 | /* ASYNCLISTADDR: offset 0x18 */ | |
271 | u32 async_next; /* address of next async queue head */ | |
272 | ||
273 | u32 reserved1; | |
274 | /* PORTSC: offset 0x20 */ | |
275 | u32 port_status; | |
276 | /* 31:23 reserved */ | |
277 | #define PORT_USB11(x) (((x)&(3<<10)) == (1<<10)) /* USB 1.1 device */ | |
278 | #define PORT_RESET (1<<8) /* reset port */ | |
279 | #define PORT_SUSPEND (1<<7) /* suspend port */ | |
280 | #define PORT_RESUME (1<<6) /* resume it */ | |
281 | #define PORT_PEC (1<<3) /* port enable change */ | |
282 | #define PORT_PE (1<<2) /* port enable */ | |
283 | #define PORT_CSC (1<<1) /* connect status change */ | |
284 | #define PORT_CONNECT (1<<0) /* device connected */ | |
285 | #define PORT_RWC_BITS (PORT_CSC | PORT_PEC) | |
286 | u32 reserved2[19]; | |
287 | ||
288 | /* OTGCSR: offet 0x70 */ | |
289 | u32 otgcsr; | |
290 | #define OTGCSR_HOST_SPD_TYP (3 << 22) | |
291 | #define OTGCSR_A_BUS_DROP (1 << 5) | |
292 | #define OTGCSR_A_BUS_REQ (1 << 4) | |
293 | ||
294 | /* OTGISR: offset 0x74 */ | |
295 | u32 otgisr; | |
296 | #define OTGISR_OVC (1 << 10) | |
297 | ||
298 | u32 reserved3[15]; | |
299 | ||
300 | /* GMIR: offset 0xB4 */ | |
301 | u32 gmir; | |
302 | #define GMIR_INT_POLARITY (1 << 3) /*Active High*/ | |
303 | #define GMIR_MHC_INT (1 << 2) | |
304 | #define GMIR_MOTG_INT (1 << 1) | |
305 | #define GMIR_MDEV_INT (1 << 0) | |
306 | }; | |
307 | ||
7d50195f FHC |
308 | /*-------------------------------------------------------------------------*/ |
309 | ||
310 | #define QTD_NEXT(fotg210, dma) cpu_to_hc32(fotg210, (u32)dma) | |
311 | ||
312 | /* | |
313 | * EHCI Specification 0.95 Section 3.5 | |
314 | * QTD: describe data transfer components (buffer, direction, ...) | |
315 | * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram". | |
316 | * | |
317 | * These are associated only with "QH" (Queue Head) structures, | |
318 | * used with control, bulk, and interrupt transfers. | |
319 | */ | |
320 | struct fotg210_qtd { | |
321 | /* first part defined by EHCI spec */ | |
322 | __hc32 hw_next; /* see EHCI 3.5.1 */ | |
323 | __hc32 hw_alt_next; /* see EHCI 3.5.2 */ | |
324 | __hc32 hw_token; /* see EHCI 3.5.3 */ | |
325 | #define QTD_TOGGLE (1 << 31) /* data toggle */ | |
326 | #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff) | |
327 | #define QTD_IOC (1 << 15) /* interrupt on complete */ | |
328 | #define QTD_CERR(tok) (((tok)>>10) & 0x3) | |
329 | #define QTD_PID(tok) (((tok)>>8) & 0x3) | |
330 | #define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */ | |
331 | #define QTD_STS_HALT (1 << 6) /* halted on error */ | |
332 | #define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */ | |
333 | #define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */ | |
334 | #define QTD_STS_XACT (1 << 3) /* device gave illegal response */ | |
335 | #define QTD_STS_MMF (1 << 2) /* incomplete split transaction */ | |
336 | #define QTD_STS_STS (1 << 1) /* split transaction state */ | |
337 | #define QTD_STS_PING (1 << 0) /* issue PING? */ | |
338 | ||
339 | #define ACTIVE_BIT(fotg210) cpu_to_hc32(fotg210, QTD_STS_ACTIVE) | |
340 | #define HALT_BIT(fotg210) cpu_to_hc32(fotg210, QTD_STS_HALT) | |
341 | #define STATUS_BIT(fotg210) cpu_to_hc32(fotg210, QTD_STS_STS) | |
342 | ||
343 | __hc32 hw_buf[5]; /* see EHCI 3.5.4 */ | |
344 | __hc32 hw_buf_hi[5]; /* Appendix B */ | |
345 | ||
346 | /* the rest is HCD-private */ | |
347 | dma_addr_t qtd_dma; /* qtd address */ | |
348 | struct list_head qtd_list; /* sw qtd list */ | |
349 | struct urb *urb; /* qtd's urb */ | |
350 | size_t length; /* length of buffer */ | |
351 | } __aligned(32); | |
352 | ||
353 | /* mask NakCnt+T in qh->hw_alt_next */ | |
354 | #define QTD_MASK(fotg210) cpu_to_hc32(fotg210, ~0x1f) | |
355 | ||
356 | #define IS_SHORT_READ(token) (QTD_LENGTH(token) != 0 && QTD_PID(token) == 1) | |
357 | ||
358 | /*-------------------------------------------------------------------------*/ | |
359 | ||
360 | /* type tag from {qh,itd,fstn}->hw_next */ | |
361 | #define Q_NEXT_TYPE(fotg210, dma) ((dma) & cpu_to_hc32(fotg210, 3 << 1)) | |
362 | ||
363 | /* | |
364 | * Now the following defines are not converted using the | |
365 | * cpu_to_le32() macro anymore, since we have to support | |
366 | * "dynamic" switching between be and le support, so that the driver | |
367 | * can be used on one system with SoC EHCI controller using big-endian | |
368 | * descriptors as well as a normal little-endian PCI EHCI controller. | |
369 | */ | |
370 | /* values for that type tag */ | |
371 | #define Q_TYPE_ITD (0 << 1) | |
372 | #define Q_TYPE_QH (1 << 1) | |
373 | #define Q_TYPE_SITD (2 << 1) | |
374 | #define Q_TYPE_FSTN (3 << 1) | |
375 | ||
376 | /* next async queue entry, or pointer to interrupt/periodic QH */ | |
377 | #define QH_NEXT(fotg210, dma) \ | |
378 | (cpu_to_hc32(fotg210, (((u32)dma)&~0x01f)|Q_TYPE_QH)) | |
379 | ||
380 | /* for periodic/async schedules and qtd lists, mark end of list */ | |
381 | #define FOTG210_LIST_END(fotg210) \ | |
382 | cpu_to_hc32(fotg210, 1) /* "null pointer" to hw */ | |
383 | ||
384 | /* | |
385 | * Entries in periodic shadow table are pointers to one of four kinds | |
386 | * of data structure. That's dictated by the hardware; a type tag is | |
387 | * encoded in the low bits of the hardware's periodic schedule. Use | |
388 | * Q_NEXT_TYPE to get the tag. | |
389 | * | |
390 | * For entries in the async schedule, the type tag always says "qh". | |
391 | */ | |
392 | union fotg210_shadow { | |
393 | struct fotg210_qh *qh; /* Q_TYPE_QH */ | |
394 | struct fotg210_itd *itd; /* Q_TYPE_ITD */ | |
395 | struct fotg210_fstn *fstn; /* Q_TYPE_FSTN */ | |
396 | __hc32 *hw_next; /* (all types) */ | |
397 | void *ptr; | |
398 | }; | |
399 | ||
400 | /*-------------------------------------------------------------------------*/ | |
401 | ||
402 | /* | |
403 | * EHCI Specification 0.95 Section 3.6 | |
404 | * QH: describes control/bulk/interrupt endpoints | |
405 | * See Fig 3-7 "Queue Head Structure Layout". | |
406 | * | |
407 | * These appear in both the async and (for interrupt) periodic schedules. | |
408 | */ | |
409 | ||
410 | /* first part defined by EHCI spec */ | |
411 | struct fotg210_qh_hw { | |
412 | __hc32 hw_next; /* see EHCI 3.6.1 */ | |
413 | __hc32 hw_info1; /* see EHCI 3.6.2 */ | |
414 | #define QH_CONTROL_EP (1 << 27) /* FS/LS control endpoint */ | |
415 | #define QH_HEAD (1 << 15) /* Head of async reclamation list */ | |
416 | #define QH_TOGGLE_CTL (1 << 14) /* Data toggle control */ | |
417 | #define QH_HIGH_SPEED (2 << 12) /* Endpoint speed */ | |
418 | #define QH_LOW_SPEED (1 << 12) | |
419 | #define QH_FULL_SPEED (0 << 12) | |
420 | #define QH_INACTIVATE (1 << 7) /* Inactivate on next transaction */ | |
421 | __hc32 hw_info2; /* see EHCI 3.6.2 */ | |
422 | #define QH_SMASK 0x000000ff | |
423 | #define QH_CMASK 0x0000ff00 | |
424 | #define QH_HUBADDR 0x007f0000 | |
425 | #define QH_HUBPORT 0x3f800000 | |
426 | #define QH_MULT 0xc0000000 | |
427 | __hc32 hw_current; /* qtd list - see EHCI 3.6.4 */ | |
428 | ||
429 | /* qtd overlay (hardware parts of a struct fotg210_qtd) */ | |
430 | __hc32 hw_qtd_next; | |
431 | __hc32 hw_alt_next; | |
432 | __hc32 hw_token; | |
433 | __hc32 hw_buf[5]; | |
434 | __hc32 hw_buf_hi[5]; | |
435 | } __aligned(32); | |
436 | ||
437 | struct fotg210_qh { | |
438 | struct fotg210_qh_hw *hw; /* Must come first */ | |
439 | /* the rest is HCD-private */ | |
440 | dma_addr_t qh_dma; /* address of qh */ | |
441 | union fotg210_shadow qh_next; /* ptr to qh; or periodic */ | |
442 | struct list_head qtd_list; /* sw qtd list */ | |
443 | struct list_head intr_node; /* list of intr QHs */ | |
444 | struct fotg210_qtd *dummy; | |
445 | struct fotg210_qh *unlink_next; /* next on unlink list */ | |
446 | ||
447 | unsigned unlink_cycle; | |
448 | ||
449 | u8 needs_rescan; /* Dequeue during giveback */ | |
450 | u8 qh_state; | |
451 | #define QH_STATE_LINKED 1 /* HC sees this */ | |
452 | #define QH_STATE_UNLINK 2 /* HC may still see this */ | |
453 | #define QH_STATE_IDLE 3 /* HC doesn't see this */ | |
454 | #define QH_STATE_UNLINK_WAIT 4 /* LINKED and on unlink q */ | |
455 | #define QH_STATE_COMPLETING 5 /* don't touch token.HALT */ | |
456 | ||
457 | u8 xacterrs; /* XactErr retry counter */ | |
458 | #define QH_XACTERR_MAX 32 /* XactErr retry limit */ | |
459 | ||
460 | /* periodic schedule info */ | |
461 | u8 usecs; /* intr bandwidth */ | |
462 | u8 gap_uf; /* uframes split/csplit gap */ | |
463 | u8 c_usecs; /* ... split completion bw */ | |
464 | u16 tt_usecs; /* tt downstream bandwidth */ | |
465 | unsigned short period; /* polling interval */ | |
466 | unsigned short start; /* where polling starts */ | |
467 | #define NO_FRAME ((unsigned short)~0) /* pick new start */ | |
468 | ||
469 | struct usb_device *dev; /* access to TT */ | |
470 | unsigned is_out:1; /* bulk or intr OUT */ | |
471 | unsigned clearing_tt:1; /* Clear-TT-Buf in progress */ | |
472 | }; | |
473 | ||
474 | /*-------------------------------------------------------------------------*/ | |
475 | ||
476 | /* description of one iso transaction (up to 3 KB data if highspeed) */ | |
477 | struct fotg210_iso_packet { | |
478 | /* These will be copied to iTD when scheduling */ | |
479 | u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */ | |
480 | __hc32 transaction; /* itd->hw_transaction[i] |= */ | |
481 | u8 cross; /* buf crosses pages */ | |
482 | /* for full speed OUT splits */ | |
483 | u32 buf1; | |
484 | }; | |
485 | ||
486 | /* temporary schedule data for packets from iso urbs (both speeds) | |
487 | * each packet is one logical usb transaction to the device (not TT), | |
488 | * beginning at stream->next_uframe | |
489 | */ | |
490 | struct fotg210_iso_sched { | |
491 | struct list_head td_list; | |
492 | unsigned span; | |
6bc3f397 | 493 | struct fotg210_iso_packet packet[]; |
7d50195f FHC |
494 | }; |
495 | ||
496 | /* | |
497 | * fotg210_iso_stream - groups all (s)itds for this endpoint. | |
498 | * acts like a qh would, if EHCI had them for ISO. | |
499 | */ | |
500 | struct fotg210_iso_stream { | |
501 | /* first field matches fotg210_hq, but is NULL */ | |
502 | struct fotg210_qh_hw *hw; | |
503 | ||
504 | u8 bEndpointAddress; | |
505 | u8 highspeed; | |
506 | struct list_head td_list; /* queued itds */ | |
507 | struct list_head free_list; /* list of unused itds */ | |
508 | struct usb_device *udev; | |
509 | struct usb_host_endpoint *ep; | |
510 | ||
511 | /* output of (re)scheduling */ | |
512 | int next_uframe; | |
513 | __hc32 splits; | |
514 | ||
515 | /* the rest is derived from the endpoint descriptor, | |
516 | * trusting urb->interval == f(epdesc->bInterval) and | |
517 | * including the extra info for hw_bufp[0..2] | |
518 | */ | |
519 | u8 usecs, c_usecs; | |
520 | u16 interval; | |
521 | u16 tt_usecs; | |
522 | u16 maxp; | |
523 | u16 raw_mask; | |
524 | unsigned bandwidth; | |
525 | ||
526 | /* This is used to initialize iTD's hw_bufp fields */ | |
527 | __hc32 buf0; | |
528 | __hc32 buf1; | |
529 | __hc32 buf2; | |
530 | ||
531 | /* this is used to initialize sITD's tt info */ | |
532 | __hc32 address; | |
533 | }; | |
534 | ||
535 | /*-------------------------------------------------------------------------*/ | |
536 | ||
537 | /* | |
538 | * EHCI Specification 0.95 Section 3.3 | |
539 | * Fig 3-4 "Isochronous Transaction Descriptor (iTD)" | |
540 | * | |
541 | * Schedule records for high speed iso xfers | |
542 | */ | |
543 | struct fotg210_itd { | |
544 | /* first part defined by EHCI spec */ | |
545 | __hc32 hw_next; /* see EHCI 3.3.1 */ | |
546 | __hc32 hw_transaction[8]; /* see EHCI 3.3.2 */ | |
547 | #define FOTG210_ISOC_ACTIVE (1<<31) /* activate transfer this slot */ | |
548 | #define FOTG210_ISOC_BUF_ERR (1<<30) /* Data buffer error */ | |
549 | #define FOTG210_ISOC_BABBLE (1<<29) /* babble detected */ | |
550 | #define FOTG210_ISOC_XACTERR (1<<28) /* XactErr - transaction error */ | |
551 | #define FOTG210_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff) | |
552 | #define FOTG210_ITD_IOC (1 << 15) /* interrupt on complete */ | |
553 | ||
554 | #define ITD_ACTIVE(fotg210) cpu_to_hc32(fotg210, FOTG210_ISOC_ACTIVE) | |
555 | ||
556 | __hc32 hw_bufp[7]; /* see EHCI 3.3.3 */ | |
557 | __hc32 hw_bufp_hi[7]; /* Appendix B */ | |
558 | ||
559 | /* the rest is HCD-private */ | |
560 | dma_addr_t itd_dma; /* for this itd */ | |
561 | union fotg210_shadow itd_next; /* ptr to periodic q entry */ | |
562 | ||
563 | struct urb *urb; | |
564 | struct fotg210_iso_stream *stream; /* endpoint's queue */ | |
565 | struct list_head itd_list; /* list of stream's itds */ | |
566 | ||
567 | /* any/all hw_transactions here may be used by that urb */ | |
568 | unsigned frame; /* where scheduled */ | |
569 | unsigned pg; | |
570 | unsigned index[8]; /* in urb->iso_frame_desc */ | |
571 | } __aligned(32); | |
572 | ||
573 | /*-------------------------------------------------------------------------*/ | |
574 | ||
575 | /* | |
576 | * EHCI Specification 0.96 Section 3.7 | |
577 | * Periodic Frame Span Traversal Node (FSTN) | |
578 | * | |
579 | * Manages split interrupt transactions (using TT) that span frame boundaries | |
580 | * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN | |
581 | * makes the HC jump (back) to a QH to scan for fs/ls QH completions until | |
582 | * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work. | |
583 | */ | |
584 | struct fotg210_fstn { | |
585 | __hc32 hw_next; /* any periodic q entry */ | |
586 | __hc32 hw_prev; /* qh or FOTG210_LIST_END */ | |
587 | ||
588 | /* the rest is HCD-private */ | |
589 | dma_addr_t fstn_dma; | |
590 | union fotg210_shadow fstn_next; /* ptr to periodic q entry */ | |
591 | } __aligned(32); | |
592 | ||
593 | /*-------------------------------------------------------------------------*/ | |
594 | ||
595 | /* Prepare the PORTSC wakeup flags during controller suspend/resume */ | |
596 | ||
597 | #define fotg210_prepare_ports_for_controller_suspend(fotg210, do_wakeup) \ | |
259127ba | 598 | fotg210_adjust_port_wakeup_flags(fotg210, true, do_wakeup) |
7d50195f FHC |
599 | |
600 | #define fotg210_prepare_ports_for_controller_resume(fotg210) \ | |
259127ba | 601 | fotg210_adjust_port_wakeup_flags(fotg210, false, false) |
7d50195f FHC |
602 | |
603 | /*-------------------------------------------------------------------------*/ | |
604 | ||
605 | /* | |
606 | * Some EHCI controllers have a Transaction Translator built into the | |
607 | * root hub. This is a non-standard feature. Each controller will need | |
608 | * to add code to the following inline functions, and call them as | |
609 | * needed (mostly in root hub code). | |
610 | */ | |
611 | ||
612 | static inline unsigned int | |
613 | fotg210_get_speed(struct fotg210_hcd *fotg210, unsigned int portsc) | |
614 | { | |
615 | return (readl(&fotg210->regs->otgcsr) | |
616 | & OTGCSR_HOST_SPD_TYP) >> 22; | |
617 | } | |
618 | ||
619 | /* Returns the speed of a device attached to a port on the root hub. */ | |
620 | static inline unsigned int | |
621 | fotg210_port_speed(struct fotg210_hcd *fotg210, unsigned int portsc) | |
622 | { | |
623 | switch (fotg210_get_speed(fotg210, portsc)) { | |
624 | case 0: | |
625 | return 0; | |
626 | case 1: | |
627 | return USB_PORT_STAT_LOW_SPEED; | |
628 | case 2: | |
629 | default: | |
630 | return USB_PORT_STAT_HIGH_SPEED; | |
631 | } | |
632 | } | |
633 | ||
634 | /*-------------------------------------------------------------------------*/ | |
635 | ||
636 | #define fotg210_has_fsl_portno_bug(e) (0) | |
637 | ||
638 | /* | |
639 | * While most USB host controllers implement their registers in | |
640 | * little-endian format, a minority (celleb companion chip) implement | |
641 | * them in big endian format. | |
642 | * | |
643 | * This attempts to support either format at compile time without a | |
644 | * runtime penalty, or both formats with the additional overhead | |
645 | * of checking a flag bit. | |
646 | * | |
647 | */ | |
648 | ||
649 | #define fotg210_big_endian_mmio(e) 0 | |
650 | #define fotg210_big_endian_capbase(e) 0 | |
651 | ||
652 | static inline unsigned int fotg210_readl(const struct fotg210_hcd *fotg210, | |
653 | __u32 __iomem *regs) | |
654 | { | |
655 | return readl(regs); | |
656 | } | |
657 | ||
658 | static inline void fotg210_writel(const struct fotg210_hcd *fotg210, | |
659 | const unsigned int val, __u32 __iomem *regs) | |
660 | { | |
661 | writel(val, regs); | |
662 | } | |
663 | ||
664 | /* cpu to fotg210 */ | |
665 | static inline __hc32 cpu_to_hc32(const struct fotg210_hcd *fotg210, const u32 x) | |
666 | { | |
667 | return cpu_to_le32(x); | |
668 | } | |
669 | ||
670 | /* fotg210 to cpu */ | |
671 | static inline u32 hc32_to_cpu(const struct fotg210_hcd *fotg210, const __hc32 x) | |
672 | { | |
673 | return le32_to_cpu(x); | |
674 | } | |
675 | ||
676 | static inline u32 hc32_to_cpup(const struct fotg210_hcd *fotg210, | |
677 | const __hc32 *x) | |
678 | { | |
679 | return le32_to_cpup(x); | |
680 | } | |
681 | ||
682 | /*-------------------------------------------------------------------------*/ | |
683 | ||
684 | static inline unsigned fotg210_read_frame_index(struct fotg210_hcd *fotg210) | |
685 | { | |
686 | return fotg210_readl(fotg210, &fotg210->regs->frame_index); | |
687 | } | |
688 | ||
689 | #define fotg210_itdlen(urb, desc, t) ({ \ | |
690 | usb_pipein((urb)->pipe) ? \ | |
691 | (desc)->length - FOTG210_ITD_LENGTH(t) : \ | |
692 | FOTG210_ITD_LENGTH(t); \ | |
693 | }) | |
694 | /*-------------------------------------------------------------------------*/ | |
695 | ||
7d50195f | 696 | #endif /* __LINUX_FOTG210_H */ |