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a9d43091 LW |
1 | /* |
2 | * ISP1362 HCD (Host Controller Driver) for USB. | |
3 | * | |
4 | * COPYRIGHT (C) by L. Wassmann <LW@KARO-electronics.de> | |
5 | */ | |
6 | ||
7 | /* ------------------------------------------------------------------------- */ | |
8 | /* | |
9 | * Platform specific compile time options | |
10 | */ | |
10d0ca02 | 11 | #if defined(CONFIG_BLACKFIN) |
a9d43091 LW |
12 | |
13 | #include <linux/io.h> | |
14 | #define USE_32BIT 0 | |
15 | #define MAX_ROOT_PORTS 2 | |
16 | #define USE_PLATFORM_DELAY 0 | |
17 | #define USE_NDELAY 1 | |
18 | ||
19 | #define DUMMY_DELAY_ACCESS \ | |
20 | do { \ | |
21 | bfin_read16(ASYNC_BANK0_BASE); \ | |
22 | bfin_read16(ASYNC_BANK0_BASE); \ | |
23 | bfin_read16(ASYNC_BANK0_BASE); \ | |
24 | } while (0) | |
25 | ||
26 | #undef insw | |
27 | #undef outsw | |
28 | ||
29 | #define insw delayed_insw | |
30 | #define outsw delayed_outsw | |
31 | ||
32 | static inline void delayed_outsw(unsigned int addr, void *buf, int len) | |
33 | { | |
34 | unsigned short *bp = (unsigned short *)buf; | |
35 | while (len--) { | |
36 | DUMMY_DELAY_ACCESS; | |
37 | outw(*bp++, addr); | |
38 | } | |
39 | } | |
40 | ||
41 | static inline void delayed_insw(unsigned int addr, void *buf, int len) | |
42 | { | |
43 | unsigned short *bp = (unsigned short *)buf; | |
44 | while (len--) { | |
45 | DUMMY_DELAY_ACCESS; | |
0c8a32df | 46 | *bp++ = inw(addr); |
a9d43091 LW |
47 | } |
48 | } | |
49 | ||
50 | #else | |
51 | ||
52 | #define MAX_ROOT_PORTS 2 | |
53 | ||
54 | #define USE_32BIT 0 | |
55 | ||
56 | /* These options are mutually eclusive */ | |
57 | #define USE_PLATFORM_DELAY 0 | |
58 | #define USE_NDELAY 0 | |
59 | ||
60 | #define DUMMY_DELAY_ACCESS do {} while (0) | |
61 | ||
62 | #endif | |
63 | ||
64 | ||
65 | /* ------------------------------------------------------------------------- */ | |
66 | ||
67 | #define USB_RESET_WIDTH 50 | |
68 | #define MAX_XFER_SIZE 1023 | |
69 | ||
70 | /* Buffer sizes */ | |
71 | #define ISP1362_BUF_SIZE 4096 | |
72 | #define ISP1362_ISTL_BUFSIZE 512 | |
73 | #define ISP1362_INTL_BLKSIZE 64 | |
74 | #define ISP1362_INTL_BUFFERS 16 | |
75 | #define ISP1362_ATL_BLKSIZE 64 | |
76 | ||
77 | #define ISP1362_REG_WRITE_OFFSET 0x80 | |
78 | ||
79 | #ifdef ISP1362_DEBUG | |
80 | typedef const unsigned int isp1362_reg_t; | |
81 | ||
82 | #define REG_WIDTH_16 0x000 | |
83 | #define REG_WIDTH_32 0x100 | |
84 | #define REG_WIDTH_MASK 0x100 | |
85 | #define REG_NO_MASK 0x0ff | |
86 | ||
87 | #define REG_ACCESS_R 0x200 | |
88 | #define REG_ACCESS_W 0x400 | |
89 | #define REG_ACCESS_RW 0x600 | |
90 | #define REG_ACCESS_MASK 0x600 | |
91 | ||
92 | #define ISP1362_REG_NO(r) ((r) & REG_NO_MASK) | |
93 | ||
94 | #define _BUG_ON(x) BUG_ON(x) | |
95 | #define _WARN_ON(x) WARN_ON(x) | |
96 | ||
97 | #define ISP1362_REG(name, addr, width, rw) \ | |
98 | static isp1362_reg_t ISP1362_REG_##name = ((addr) | (width) | (rw)) | |
99 | ||
100 | #define REG_ACCESS_TEST(r) BUG_ON(((r) & ISP1362_REG_WRITE_OFFSET) && !((r) & REG_ACCESS_W)) | |
101 | #define REG_WIDTH_TEST(r, w) BUG_ON(((r) & REG_WIDTH_MASK) != (w)) | |
102 | #else | |
103 | typedef const unsigned char isp1362_reg_t; | |
104 | #define ISP1362_REG_NO(r) (r) | |
105 | #define _BUG_ON(x) do {} while (0) | |
106 | #define _WARN_ON(x) do {} while (0) | |
107 | ||
108 | #define ISP1362_REG(name, addr, width, rw) \ | |
109 | static isp1362_reg_t ISP1362_REG_##name = addr | |
110 | ||
111 | #define REG_ACCESS_TEST(r) do {} while (0) | |
112 | #define REG_WIDTH_TEST(r, w) do {} while (0) | |
113 | #endif | |
114 | ||
115 | /* OHCI compatible registers */ | |
116 | /* | |
117 | * Note: Some of the ISP1362 'OHCI' registers implement only | |
118 | * a subset of the bits defined in the OHCI spec. | |
119 | * | |
120 | * Bitmasks for the individual bits of these registers are defined in "ohci.h" | |
121 | */ | |
122 | ISP1362_REG(HCREVISION, 0x00, REG_WIDTH_32, REG_ACCESS_R); | |
123 | ISP1362_REG(HCCONTROL, 0x01, REG_WIDTH_32, REG_ACCESS_RW); | |
124 | ISP1362_REG(HCCMDSTAT, 0x02, REG_WIDTH_32, REG_ACCESS_RW); | |
125 | ISP1362_REG(HCINTSTAT, 0x03, REG_WIDTH_32, REG_ACCESS_RW); | |
126 | ISP1362_REG(HCINTENB, 0x04, REG_WIDTH_32, REG_ACCESS_RW); | |
127 | ISP1362_REG(HCINTDIS, 0x05, REG_WIDTH_32, REG_ACCESS_RW); | |
128 | ISP1362_REG(HCFMINTVL, 0x0d, REG_WIDTH_32, REG_ACCESS_RW); | |
129 | ISP1362_REG(HCFMREM, 0x0e, REG_WIDTH_32, REG_ACCESS_RW); | |
130 | ISP1362_REG(HCFMNUM, 0x0f, REG_WIDTH_32, REG_ACCESS_RW); | |
131 | ISP1362_REG(HCLSTHRESH, 0x11, REG_WIDTH_32, REG_ACCESS_RW); | |
132 | ISP1362_REG(HCRHDESCA, 0x12, REG_WIDTH_32, REG_ACCESS_RW); | |
133 | ISP1362_REG(HCRHDESCB, 0x13, REG_WIDTH_32, REG_ACCESS_RW); | |
134 | ISP1362_REG(HCRHSTATUS, 0x14, REG_WIDTH_32, REG_ACCESS_RW); | |
135 | ISP1362_REG(HCRHPORT1, 0x15, REG_WIDTH_32, REG_ACCESS_RW); | |
136 | ISP1362_REG(HCRHPORT2, 0x16, REG_WIDTH_32, REG_ACCESS_RW); | |
137 | ||
138 | /* Philips ISP1362 specific registers */ | |
139 | ISP1362_REG(HCHWCFG, 0x20, REG_WIDTH_16, REG_ACCESS_RW); | |
140 | #define HCHWCFG_DISABLE_SUSPEND (1 << 15) | |
141 | #define HCHWCFG_GLOBAL_PWRDOWN (1 << 14) | |
7949f4e1 KM |
142 | #define HCHWCFG_PULLDOWN_DS2 (1 << 13) |
143 | #define HCHWCFG_PULLDOWN_DS1 (1 << 12) | |
a9d43091 LW |
144 | #define HCHWCFG_CLKNOTSTOP (1 << 11) |
145 | #define HCHWCFG_ANALOG_OC (1 << 10) | |
146 | #define HCHWCFG_ONEINT (1 << 9) | |
147 | #define HCHWCFG_DACK_MODE (1 << 8) | |
148 | #define HCHWCFG_ONEDMA (1 << 7) | |
149 | #define HCHWCFG_DACK_POL (1 << 6) | |
150 | #define HCHWCFG_DREQ_POL (1 << 5) | |
151 | #define HCHWCFG_DBWIDTH_MASK (0x03 << 3) | |
152 | #define HCHWCFG_DBWIDTH(n) (((n) << 3) & HCHWCFG_DBWIDTH_MASK) | |
153 | #define HCHWCFG_INT_POL (1 << 2) | |
154 | #define HCHWCFG_INT_TRIGGER (1 << 1) | |
155 | #define HCHWCFG_INT_ENABLE (1 << 0) | |
156 | ||
157 | ISP1362_REG(HCDMACFG, 0x21, REG_WIDTH_16, REG_ACCESS_RW); | |
158 | #define HCDMACFG_CTR_ENABLE (1 << 7) | |
159 | #define HCDMACFG_BURST_LEN_MASK (0x03 << 5) | |
160 | #define HCDMACFG_BURST_LEN(n) (((n) << 5) & HCDMACFG_BURST_LEN_MASK) | |
161 | #define HCDMACFG_BURST_LEN_1 HCDMACFG_BURST_LEN(0) | |
162 | #define HCDMACFG_BURST_LEN_4 HCDMACFG_BURST_LEN(1) | |
163 | #define HCDMACFG_BURST_LEN_8 HCDMACFG_BURST_LEN(2) | |
164 | #define HCDMACFG_DMA_ENABLE (1 << 4) | |
165 | #define HCDMACFG_BUF_TYPE_MASK (0x07 << 1) | |
166 | #define HCDMACFG_BUF_TYPE(n) (((n) << 1) & HCDMACFG_BUF_TYPE_MASK) | |
167 | #define HCDMACFG_BUF_ISTL0 HCDMACFG_BUF_TYPE(0) | |
168 | #define HCDMACFG_BUF_ISTL1 HCDMACFG_BUF_TYPE(1) | |
169 | #define HCDMACFG_BUF_INTL HCDMACFG_BUF_TYPE(2) | |
170 | #define HCDMACFG_BUF_ATL HCDMACFG_BUF_TYPE(3) | |
171 | #define HCDMACFG_BUF_DIRECT HCDMACFG_BUF_TYPE(4) | |
172 | #define HCDMACFG_DMA_RW_SELECT (1 << 0) | |
173 | ||
174 | ISP1362_REG(HCXFERCTR, 0x22, REG_WIDTH_16, REG_ACCESS_RW); | |
175 | ||
176 | ISP1362_REG(HCuPINT, 0x24, REG_WIDTH_16, REG_ACCESS_RW); | |
177 | #define HCuPINT_SOF (1 << 0) | |
178 | #define HCuPINT_ISTL0 (1 << 1) | |
179 | #define HCuPINT_ISTL1 (1 << 2) | |
180 | #define HCuPINT_EOT (1 << 3) | |
181 | #define HCuPINT_OPR (1 << 4) | |
182 | #define HCuPINT_SUSP (1 << 5) | |
183 | #define HCuPINT_CLKRDY (1 << 6) | |
184 | #define HCuPINT_INTL (1 << 7) | |
185 | #define HCuPINT_ATL (1 << 8) | |
186 | #define HCuPINT_OTG (1 << 9) | |
187 | ||
188 | ISP1362_REG(HCuPINTENB, 0x25, REG_WIDTH_16, REG_ACCESS_RW); | |
189 | /* same bit definitions apply as for HCuPINT */ | |
190 | ||
191 | ISP1362_REG(HCCHIPID, 0x27, REG_WIDTH_16, REG_ACCESS_R); | |
192 | #define HCCHIPID_MASK 0xff00 | |
193 | #define HCCHIPID_MAGIC 0x3600 | |
194 | ||
195 | ISP1362_REG(HCSCRATCH, 0x28, REG_WIDTH_16, REG_ACCESS_RW); | |
196 | ||
197 | ISP1362_REG(HCSWRES, 0x29, REG_WIDTH_16, REG_ACCESS_W); | |
198 | #define HCSWRES_MAGIC 0x00f6 | |
199 | ||
200 | ISP1362_REG(HCBUFSTAT, 0x2c, REG_WIDTH_16, REG_ACCESS_RW); | |
201 | #define HCBUFSTAT_ISTL0_FULL (1 << 0) | |
202 | #define HCBUFSTAT_ISTL1_FULL (1 << 1) | |
203 | #define HCBUFSTAT_INTL_ACTIVE (1 << 2) | |
204 | #define HCBUFSTAT_ATL_ACTIVE (1 << 3) | |
205 | #define HCBUFSTAT_RESET_HWPP (1 << 4) | |
206 | #define HCBUFSTAT_ISTL0_ACTIVE (1 << 5) | |
207 | #define HCBUFSTAT_ISTL1_ACTIVE (1 << 6) | |
208 | #define HCBUFSTAT_ISTL0_DONE (1 << 8) | |
209 | #define HCBUFSTAT_ISTL1_DONE (1 << 9) | |
210 | #define HCBUFSTAT_PAIRED_PTDPP (1 << 10) | |
211 | ||
212 | ISP1362_REG(HCDIRADDR, 0x32, REG_WIDTH_32, REG_ACCESS_RW); | |
213 | #define HCDIRADDR_ADDR_MASK 0x0000ffff | |
214 | #define HCDIRADDR_ADDR(n) (((n) << 0) & HCDIRADDR_ADDR_MASK) | |
215 | #define HCDIRADDR_COUNT_MASK 0xffff0000 | |
216 | #define HCDIRADDR_COUNT(n) (((n) << 16) & HCDIRADDR_COUNT_MASK) | |
217 | ISP1362_REG(HCDIRDATA, 0x45, REG_WIDTH_16, REG_ACCESS_RW); | |
218 | ||
219 | ISP1362_REG(HCISTLBUFSZ, 0x30, REG_WIDTH_16, REG_ACCESS_RW); | |
220 | ISP1362_REG(HCISTL0PORT, 0x40, REG_WIDTH_16, REG_ACCESS_RW); | |
221 | ISP1362_REG(HCISTL1PORT, 0x42, REG_WIDTH_16, REG_ACCESS_RW); | |
222 | ISP1362_REG(HCISTLRATE, 0x47, REG_WIDTH_16, REG_ACCESS_RW); | |
223 | ||
224 | ISP1362_REG(HCINTLBUFSZ, 0x33, REG_WIDTH_16, REG_ACCESS_RW); | |
225 | ISP1362_REG(HCINTLPORT, 0x43, REG_WIDTH_16, REG_ACCESS_RW); | |
226 | ISP1362_REG(HCINTLBLKSZ, 0x53, REG_WIDTH_16, REG_ACCESS_RW); | |
227 | ISP1362_REG(HCINTLDONE, 0x17, REG_WIDTH_32, REG_ACCESS_R); | |
228 | ISP1362_REG(HCINTLSKIP, 0x18, REG_WIDTH_32, REG_ACCESS_RW); | |
229 | ISP1362_REG(HCINTLLAST, 0x19, REG_WIDTH_32, REG_ACCESS_RW); | |
230 | ISP1362_REG(HCINTLCURR, 0x1a, REG_WIDTH_16, REG_ACCESS_R); | |
231 | ||
232 | ISP1362_REG(HCATLBUFSZ, 0x34, REG_WIDTH_16, REG_ACCESS_RW); | |
233 | ISP1362_REG(HCATLPORT, 0x44, REG_WIDTH_16, REG_ACCESS_RW); | |
234 | ISP1362_REG(HCATLBLKSZ, 0x54, REG_WIDTH_16, REG_ACCESS_RW); | |
235 | ISP1362_REG(HCATLDONE, 0x1b, REG_WIDTH_32, REG_ACCESS_R); | |
236 | ISP1362_REG(HCATLSKIP, 0x1c, REG_WIDTH_32, REG_ACCESS_RW); | |
237 | ISP1362_REG(HCATLLAST, 0x1d, REG_WIDTH_32, REG_ACCESS_RW); | |
238 | ISP1362_REG(HCATLCURR, 0x1e, REG_WIDTH_16, REG_ACCESS_R); | |
239 | ||
240 | ISP1362_REG(HCATLDTC, 0x51, REG_WIDTH_16, REG_ACCESS_RW); | |
241 | ISP1362_REG(HCATLDTCTO, 0x52, REG_WIDTH_16, REG_ACCESS_RW); | |
242 | ||
243 | ||
244 | ISP1362_REG(OTGCONTROL, 0x62, REG_WIDTH_16, REG_ACCESS_RW); | |
245 | ISP1362_REG(OTGSTATUS, 0x67, REG_WIDTH_16, REG_ACCESS_R); | |
246 | ISP1362_REG(OTGINT, 0x68, REG_WIDTH_16, REG_ACCESS_RW); | |
247 | ISP1362_REG(OTGINTENB, 0x69, REG_WIDTH_16, REG_ACCESS_RW); | |
248 | ISP1362_REG(OTGTIMER, 0x6A, REG_WIDTH_16, REG_ACCESS_RW); | |
249 | ISP1362_REG(OTGALTTMR, 0x6C, REG_WIDTH_16, REG_ACCESS_RW); | |
250 | ||
251 | /* Philips transfer descriptor, cpu-endian */ | |
252 | struct ptd { | |
253 | u16 count; | |
254 | #define PTD_COUNT_MSK (0x3ff << 0) | |
255 | #define PTD_TOGGLE_MSK (1 << 10) | |
256 | #define PTD_ACTIVE_MSK (1 << 11) | |
257 | #define PTD_CC_MSK (0xf << 12) | |
258 | u16 mps; | |
259 | #define PTD_MPS_MSK (0x3ff << 0) | |
260 | #define PTD_SPD_MSK (1 << 10) | |
261 | #define PTD_LAST_MSK (1 << 11) | |
262 | #define PTD_EP_MSK (0xf << 12) | |
263 | u16 len; | |
264 | #define PTD_LEN_MSK (0x3ff << 0) | |
265 | #define PTD_DIR_MSK (3 << 10) | |
266 | #define PTD_DIR_SETUP (0) | |
267 | #define PTD_DIR_OUT (1) | |
268 | #define PTD_DIR_IN (2) | |
269 | u16 faddr; | |
270 | #define PTD_FA_MSK (0x7f << 0) | |
271 | /* PTD Byte 7: [StartingFrame (if ISO PTD) | StartingFrame[0..4], PollingRate[0..2] (if INT PTD)] */ | |
272 | #define PTD_SF_ISO_MSK (0xff << 8) | |
273 | #define PTD_SF_INT_MSK (0x1f << 8) | |
274 | #define PTD_PR_MSK (0x07 << 13) | |
275 | } __attribute__ ((packed, aligned(2))); | |
276 | #define PTD_HEADER_SIZE sizeof(struct ptd) | |
277 | ||
278 | /* ------------------------------------------------------------------------- */ | |
279 | /* Copied from ohci.h: */ | |
280 | /* | |
281 | * Hardware transfer status codes -- CC from PTD | |
282 | */ | |
283 | #define PTD_CC_NOERROR 0x00 | |
284 | #define PTD_CC_CRC 0x01 | |
285 | #define PTD_CC_BITSTUFFING 0x02 | |
286 | #define PTD_CC_DATATOGGLEM 0x03 | |
287 | #define PTD_CC_STALL 0x04 | |
288 | #define PTD_DEVNOTRESP 0x05 | |
289 | #define PTD_PIDCHECKFAIL 0x06 | |
290 | #define PTD_UNEXPECTEDPID 0x07 | |
291 | #define PTD_DATAOVERRUN 0x08 | |
292 | #define PTD_DATAUNDERRUN 0x09 | |
293 | /* 0x0A, 0x0B reserved for hardware */ | |
294 | #define PTD_BUFFEROVERRUN 0x0C | |
295 | #define PTD_BUFFERUNDERRUN 0x0D | |
296 | /* 0x0E, 0x0F reserved for HCD */ | |
297 | #define PTD_NOTACCESSED 0x0F | |
298 | ||
299 | ||
300 | /* map OHCI TD status codes (CC) to errno values */ | |
301 | static const int cc_to_error[16] = { | |
302 | /* No Error */ 0, | |
303 | /* CRC Error */ -EILSEQ, | |
304 | /* Bit Stuff */ -EPROTO, | |
305 | /* Data Togg */ -EILSEQ, | |
306 | /* Stall */ -EPIPE, | |
307 | /* DevNotResp */ -ETIMEDOUT, | |
308 | /* PIDCheck */ -EPROTO, | |
309 | /* UnExpPID */ -EPROTO, | |
310 | /* DataOver */ -EOVERFLOW, | |
311 | /* DataUnder */ -EREMOTEIO, | |
312 | /* (for hw) */ -EIO, | |
313 | /* (for hw) */ -EIO, | |
314 | /* BufferOver */ -ECOMM, | |
315 | /* BuffUnder */ -ENOSR, | |
316 | /* (for HCD) */ -EALREADY, | |
317 | /* (for HCD) */ -EALREADY | |
318 | }; | |
319 | ||
320 | ||
321 | /* | |
322 | * HcControl (control) register masks | |
323 | */ | |
324 | #define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */ | |
325 | #define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */ | |
326 | #define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */ | |
327 | ||
328 | /* pre-shifted values for HCFS */ | |
329 | # define OHCI_USB_RESET (0 << 6) | |
330 | # define OHCI_USB_RESUME (1 << 6) | |
331 | # define OHCI_USB_OPER (2 << 6) | |
332 | # define OHCI_USB_SUSPEND (3 << 6) | |
333 | ||
334 | /* | |
335 | * HcCommandStatus (cmdstatus) register masks | |
336 | */ | |
337 | #define OHCI_HCR (1 << 0) /* host controller reset */ | |
338 | #define OHCI_SOC (3 << 16) /* scheduling overrun count */ | |
339 | ||
340 | /* | |
341 | * masks used with interrupt registers: | |
342 | * HcInterruptStatus (intrstatus) | |
343 | * HcInterruptEnable (intrenable) | |
344 | * HcInterruptDisable (intrdisable) | |
345 | */ | |
346 | #define OHCI_INTR_SO (1 << 0) /* scheduling overrun */ | |
347 | #define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */ | |
348 | #define OHCI_INTR_SF (1 << 2) /* start frame */ | |
349 | #define OHCI_INTR_RD (1 << 3) /* resume detect */ | |
350 | #define OHCI_INTR_UE (1 << 4) /* unrecoverable error */ | |
351 | #define OHCI_INTR_FNO (1 << 5) /* frame number overflow */ | |
352 | #define OHCI_INTR_RHSC (1 << 6) /* root hub status change */ | |
353 | #define OHCI_INTR_OC (1 << 30) /* ownership change */ | |
354 | #define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */ | |
355 | ||
356 | /* roothub.portstatus [i] bits */ | |
357 | #define RH_PS_CCS 0x00000001 /* current connect status */ | |
358 | #define RH_PS_PES 0x00000002 /* port enable status*/ | |
359 | #define RH_PS_PSS 0x00000004 /* port suspend status */ | |
360 | #define RH_PS_POCI 0x00000008 /* port over current indicator */ | |
361 | #define RH_PS_PRS 0x00000010 /* port reset status */ | |
362 | #define RH_PS_PPS 0x00000100 /* port power status */ | |
363 | #define RH_PS_LSDA 0x00000200 /* low speed device attached */ | |
364 | #define RH_PS_CSC 0x00010000 /* connect status change */ | |
365 | #define RH_PS_PESC 0x00020000 /* port enable status change */ | |
366 | #define RH_PS_PSSC 0x00040000 /* port suspend status change */ | |
367 | #define RH_PS_OCIC 0x00080000 /* over current indicator change */ | |
368 | #define RH_PS_PRSC 0x00100000 /* port reset status change */ | |
369 | ||
370 | /* roothub.status bits */ | |
371 | #define RH_HS_LPS 0x00000001 /* local power status */ | |
372 | #define RH_HS_OCI 0x00000002 /* over current indicator */ | |
373 | #define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */ | |
374 | #define RH_HS_LPSC 0x00010000 /* local power status change */ | |
375 | #define RH_HS_OCIC 0x00020000 /* over current indicator change */ | |
376 | #define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */ | |
377 | ||
378 | /* roothub.b masks */ | |
379 | #define RH_B_DR 0x0000ffff /* device removable flags */ | |
380 | #define RH_B_PPCM 0xffff0000 /* port power control mask */ | |
381 | ||
382 | /* roothub.a masks */ | |
383 | #define RH_A_NDP (0xff << 0) /* number of downstream ports */ | |
384 | #define RH_A_PSM (1 << 8) /* power switching mode */ | |
385 | #define RH_A_NPS (1 << 9) /* no power switching */ | |
386 | #define RH_A_DT (1 << 10) /* device type (mbz) */ | |
387 | #define RH_A_OCPM (1 << 11) /* over current protection mode */ | |
388 | #define RH_A_NOCP (1 << 12) /* no over current protection */ | |
389 | #define RH_A_POTPGT (0xff << 24) /* power on to power good time */ | |
390 | ||
391 | #define FI 0x2edf /* 12000 bits per frame (-1) */ | |
392 | #define FSMP(fi) (0x7fff & ((6 * ((fi) - 210)) / 7)) | |
393 | #define LSTHRESH 0x628 /* lowspeed bit threshold */ | |
394 | ||
395 | /* ------------------------------------------------------------------------- */ | |
396 | ||
397 | /* PTD accessor macros. */ | |
398 | #define PTD_GET_COUNT(p) (((p)->count & PTD_COUNT_MSK) >> 0) | |
399 | #define PTD_COUNT(v) (((v) << 0) & PTD_COUNT_MSK) | |
400 | #define PTD_GET_TOGGLE(p) (((p)->count & PTD_TOGGLE_MSK) >> 10) | |
401 | #define PTD_TOGGLE(v) (((v) << 10) & PTD_TOGGLE_MSK) | |
402 | #define PTD_GET_ACTIVE(p) (((p)->count & PTD_ACTIVE_MSK) >> 11) | |
403 | #define PTD_ACTIVE(v) (((v) << 11) & PTD_ACTIVE_MSK) | |
404 | #define PTD_GET_CC(p) (((p)->count & PTD_CC_MSK) >> 12) | |
405 | #define PTD_CC(v) (((v) << 12) & PTD_CC_MSK) | |
406 | #define PTD_GET_MPS(p) (((p)->mps & PTD_MPS_MSK) >> 0) | |
407 | #define PTD_MPS(v) (((v) << 0) & PTD_MPS_MSK) | |
408 | #define PTD_GET_SPD(p) (((p)->mps & PTD_SPD_MSK) >> 10) | |
409 | #define PTD_SPD(v) (((v) << 10) & PTD_SPD_MSK) | |
410 | #define PTD_GET_LAST(p) (((p)->mps & PTD_LAST_MSK) >> 11) | |
411 | #define PTD_LAST(v) (((v) << 11) & PTD_LAST_MSK) | |
412 | #define PTD_GET_EP(p) (((p)->mps & PTD_EP_MSK) >> 12) | |
413 | #define PTD_EP(v) (((v) << 12) & PTD_EP_MSK) | |
414 | #define PTD_GET_LEN(p) (((p)->len & PTD_LEN_MSK) >> 0) | |
415 | #define PTD_LEN(v) (((v) << 0) & PTD_LEN_MSK) | |
416 | #define PTD_GET_DIR(p) (((p)->len & PTD_DIR_MSK) >> 10) | |
417 | #define PTD_DIR(v) (((v) << 10) & PTD_DIR_MSK) | |
418 | #define PTD_GET_FA(p) (((p)->faddr & PTD_FA_MSK) >> 0) | |
419 | #define PTD_FA(v) (((v) << 0) & PTD_FA_MSK) | |
420 | #define PTD_GET_SF_INT(p) (((p)->faddr & PTD_SF_INT_MSK) >> 8) | |
421 | #define PTD_SF_INT(v) (((v) << 8) & PTD_SF_INT_MSK) | |
422 | #define PTD_GET_SF_ISO(p) (((p)->faddr & PTD_SF_ISO_MSK) >> 8) | |
423 | #define PTD_SF_ISO(v) (((v) << 8) & PTD_SF_ISO_MSK) | |
424 | #define PTD_GET_PR(p) (((p)->faddr & PTD_PR_MSK) >> 13) | |
425 | #define PTD_PR(v) (((v) << 13) & PTD_PR_MSK) | |
426 | ||
427 | #define LOG2_PERIODIC_SIZE 5 /* arbitrary; this matches OHCI */ | |
428 | #define PERIODIC_SIZE (1 << LOG2_PERIODIC_SIZE) | |
429 | ||
430 | struct isp1362_ep { | |
431 | struct usb_host_endpoint *hep; | |
432 | struct usb_device *udev; | |
433 | ||
434 | /* philips transfer descriptor */ | |
435 | struct ptd ptd; | |
436 | ||
437 | u8 maxpacket; | |
438 | u8 epnum; | |
439 | u8 nextpid; | |
440 | u16 error_count; | |
441 | u16 length; /* of current packet */ | |
442 | s16 ptd_offset; /* buffer offset in ISP1362 where | |
443 | PTD has been stored | |
444 | (for access thru HCDIRDATA) */ | |
445 | int ptd_index; | |
446 | int num_ptds; | |
447 | void *data; /* to databuf */ | |
448 | /* queue of active EPs (the ones transmitted to the chip) */ | |
449 | struct list_head active; | |
450 | ||
451 | /* periodic schedule */ | |
452 | u8 branch; | |
453 | u16 interval; | |
454 | u16 load; | |
455 | u16 last_iso; | |
456 | ||
457 | /* async schedule */ | |
458 | struct list_head schedule; /* list of all EPs that need processing */ | |
459 | struct list_head remove_list; | |
460 | int num_req; | |
461 | }; | |
462 | ||
463 | struct isp1362_ep_queue { | |
464 | struct list_head active; /* list of PTDs currently processed by HC */ | |
465 | atomic_t finishing; | |
466 | unsigned long buf_map; | |
467 | unsigned long skip_map; | |
468 | int free_ptd; | |
469 | u16 buf_start; | |
470 | u16 buf_size; | |
471 | u16 blk_size; /* PTD buffer block size for ATL and INTL */ | |
472 | u8 buf_count; | |
473 | u8 buf_avail; | |
474 | char name[16]; | |
475 | ||
476 | /* for statistical tracking */ | |
477 | u8 stat_maxptds; /* Max # of ptds seen simultaneously in fifo */ | |
478 | u8 ptd_count; /* number of ptds submitted to this queue */ | |
479 | }; | |
480 | ||
481 | struct isp1362_hcd { | |
482 | spinlock_t lock; | |
483 | void __iomem *addr_reg; | |
484 | void __iomem *data_reg; | |
485 | ||
486 | struct isp1362_platform_data *board; | |
487 | ||
488 | struct proc_dir_entry *pde; | |
489 | unsigned long stat1, stat2, stat4, stat8, stat16; | |
490 | ||
491 | /* HC registers */ | |
492 | u32 intenb; /* "OHCI" interrupts */ | |
493 | u16 irqenb; /* uP interrupts */ | |
494 | ||
495 | /* Root hub registers */ | |
496 | u32 rhdesca; | |
497 | u32 rhdescb; | |
498 | u32 rhstatus; | |
499 | u32 rhport[MAX_ROOT_PORTS]; | |
500 | unsigned long next_statechange; | |
501 | ||
502 | /* HC control reg shadow copy */ | |
503 | u32 hc_control; | |
504 | ||
505 | /* async schedule: control, bulk */ | |
506 | struct list_head async; | |
507 | ||
508 | /* periodic schedule: int */ | |
509 | u16 load[PERIODIC_SIZE]; | |
510 | struct list_head periodic; | |
511 | u16 fmindex; | |
512 | ||
513 | /* periodic schedule: isochronous */ | |
514 | struct list_head isoc; | |
22a627ba RK |
515 | unsigned int istl_flip:1; |
516 | unsigned int irq_active:1; | |
a9d43091 LW |
517 | |
518 | /* Schedules for the current frame */ | |
519 | struct isp1362_ep_queue atl_queue; | |
520 | struct isp1362_ep_queue intl_queue; | |
521 | struct isp1362_ep_queue istl_queue[2]; | |
522 | ||
523 | /* list of PTDs retrieved from HC */ | |
524 | struct list_head remove_list; | |
525 | enum { | |
526 | ISP1362_INT_SOF, | |
527 | ISP1362_INT_ISTL0, | |
528 | ISP1362_INT_ISTL1, | |
529 | ISP1362_INT_EOT, | |
530 | ISP1362_INT_OPR, | |
531 | ISP1362_INT_SUSP, | |
532 | ISP1362_INT_CLKRDY, | |
533 | ISP1362_INT_INTL, | |
534 | ISP1362_INT_ATL, | |
535 | ISP1362_INT_OTG, | |
536 | NUM_ISP1362_IRQS | |
537 | } IRQ_NAMES; | |
538 | unsigned int irq_stat[NUM_ISP1362_IRQS]; | |
539 | int req_serial; | |
540 | }; | |
541 | ||
542 | static inline const char *ISP1362_INT_NAME(int n) | |
543 | { | |
544 | switch (n) { | |
545 | case ISP1362_INT_SOF: return "SOF"; | |
546 | case ISP1362_INT_ISTL0: return "ISTL0"; | |
547 | case ISP1362_INT_ISTL1: return "ISTL1"; | |
548 | case ISP1362_INT_EOT: return "EOT"; | |
549 | case ISP1362_INT_OPR: return "OPR"; | |
550 | case ISP1362_INT_SUSP: return "SUSP"; | |
551 | case ISP1362_INT_CLKRDY: return "CLKRDY"; | |
552 | case ISP1362_INT_INTL: return "INTL"; | |
553 | case ISP1362_INT_ATL: return "ATL"; | |
554 | case ISP1362_INT_OTG: return "OTG"; | |
555 | default: return "unknown"; | |
556 | } | |
557 | } | |
558 | ||
559 | static inline void ALIGNSTAT(struct isp1362_hcd *isp1362_hcd, void *ptr) | |
560 | { | |
b0a9cf29 | 561 | unsigned long p = (unsigned long)ptr; |
a9d43091 LW |
562 | if (!(p & 0xf)) |
563 | isp1362_hcd->stat16++; | |
564 | else if (!(p & 0x7)) | |
565 | isp1362_hcd->stat8++; | |
566 | else if (!(p & 0x3)) | |
567 | isp1362_hcd->stat4++; | |
568 | else if (!(p & 0x1)) | |
569 | isp1362_hcd->stat2++; | |
570 | else | |
571 | isp1362_hcd->stat1++; | |
572 | } | |
573 | ||
574 | static inline struct isp1362_hcd *hcd_to_isp1362_hcd(struct usb_hcd *hcd) | |
575 | { | |
576 | return (struct isp1362_hcd *) (hcd->hcd_priv); | |
577 | } | |
578 | ||
579 | static inline struct usb_hcd *isp1362_hcd_to_hcd(struct isp1362_hcd *isp1362_hcd) | |
580 | { | |
581 | return container_of((void *)isp1362_hcd, struct usb_hcd, hcd_priv); | |
582 | } | |
583 | ||
584 | #define frame_before(f1, f2) ((s16)((u16)f1 - (u16)f2) < 0) | |
585 | ||
586 | /* | |
587 | * ISP1362 HW Interface | |
588 | */ | |
589 | ||
590 | #ifdef ISP1362_DEBUG | |
591 | #define DBG(level, fmt...) \ | |
592 | do { \ | |
593 | if (dbg_level > level) \ | |
594 | pr_debug(fmt); \ | |
595 | } while (0) | |
596 | #define _DBG(level, fmt...) \ | |
597 | do { \ | |
598 | if (dbg_level > level) \ | |
599 | printk(fmt); \ | |
600 | } while (0) | |
601 | #else | |
602 | #define DBG(fmt...) do {} while (0) | |
603 | #define _DBG DBG | |
604 | #endif | |
605 | ||
606 | #ifdef VERBOSE | |
607 | # define VDBG(fmt...) DBG(3, fmt) | |
608 | #else | |
609 | # define VDBG(fmt...) do {} while (0) | |
610 | #endif | |
611 | ||
612 | #ifdef REGISTERS | |
613 | # define RDBG(fmt...) DBG(1, fmt) | |
614 | #else | |
615 | # define RDBG(fmt...) do {} while (0) | |
616 | #endif | |
617 | ||
618 | #ifdef URB_TRACE | |
619 | #define URB_DBG(fmt...) DBG(0, fmt) | |
620 | #else | |
621 | #define URB_DBG(fmt...) do {} while (0) | |
622 | #endif | |
623 | ||
624 | ||
625 | #if USE_PLATFORM_DELAY | |
626 | #if USE_NDELAY | |
627 | #error USE_PLATFORM_DELAY and USE_NDELAY defined simultaneously. | |
628 | #endif | |
629 | #define isp1362_delay(h, d) (h)->board->delay(isp1362_hcd_to_hcd(h)->self.controller, d) | |
630 | #elif USE_NDELAY | |
631 | #define isp1362_delay(h, d) ndelay(d) | |
632 | #else | |
633 | #define isp1362_delay(h, d) do {} while (0) | |
634 | #endif | |
635 | ||
636 | #define get_urb(ep) ({ \ | |
637 | BUG_ON(list_empty(&ep->hep->urb_list)); \ | |
638 | container_of(ep->hep->urb_list.next, struct urb, urb_list); \ | |
639 | }) | |
640 | ||
641 | /* basic access functions for ISP1362 chip registers */ | |
642 | /* NOTE: The contents of the address pointer register cannot be read back! The driver must ensure, | |
643 | * that all register accesses are performed with interrupts disabled, since the interrupt | |
644 | * handler has no way of restoring the previous state. | |
645 | */ | |
646 | static void isp1362_write_addr(struct isp1362_hcd *isp1362_hcd, isp1362_reg_t reg) | |
647 | { | |
648 | /*_BUG_ON((reg & ISP1362_REG_WRITE_OFFSET) && !(reg & REG_ACCESS_W));*/ | |
649 | REG_ACCESS_TEST(reg); | |
650 | _BUG_ON(!irqs_disabled()); | |
651 | DUMMY_DELAY_ACCESS; | |
652 | writew(ISP1362_REG_NO(reg), isp1362_hcd->addr_reg); | |
653 | DUMMY_DELAY_ACCESS; | |
654 | isp1362_delay(isp1362_hcd, 1); | |
655 | } | |
656 | ||
657 | static void isp1362_write_data16(struct isp1362_hcd *isp1362_hcd, u16 val) | |
658 | { | |
659 | _BUG_ON(!irqs_disabled()); | |
660 | DUMMY_DELAY_ACCESS; | |
661 | writew(val, isp1362_hcd->data_reg); | |
662 | } | |
663 | ||
664 | static u16 isp1362_read_data16(struct isp1362_hcd *isp1362_hcd) | |
665 | { | |
666 | u16 val; | |
667 | ||
668 | _BUG_ON(!irqs_disabled()); | |
669 | DUMMY_DELAY_ACCESS; | |
670 | val = readw(isp1362_hcd->data_reg); | |
671 | ||
672 | return val; | |
673 | } | |
674 | ||
675 | static void isp1362_write_data32(struct isp1362_hcd *isp1362_hcd, u32 val) | |
676 | { | |
677 | _BUG_ON(!irqs_disabled()); | |
678 | #if USE_32BIT | |
679 | DUMMY_DELAY_ACCESS; | |
680 | writel(val, isp1362_hcd->data_reg); | |
681 | #else | |
682 | DUMMY_DELAY_ACCESS; | |
683 | writew((u16)val, isp1362_hcd->data_reg); | |
684 | DUMMY_DELAY_ACCESS; | |
685 | writew(val >> 16, isp1362_hcd->data_reg); | |
686 | #endif | |
687 | } | |
688 | ||
689 | static u32 isp1362_read_data32(struct isp1362_hcd *isp1362_hcd) | |
690 | { | |
691 | u32 val; | |
692 | ||
693 | _BUG_ON(!irqs_disabled()); | |
694 | #if USE_32BIT | |
695 | DUMMY_DELAY_ACCESS; | |
696 | val = readl(isp1362_hcd->data_reg); | |
697 | #else | |
698 | DUMMY_DELAY_ACCESS; | |
699 | val = (u32)readw(isp1362_hcd->data_reg); | |
700 | DUMMY_DELAY_ACCESS; | |
701 | val |= (u32)readw(isp1362_hcd->data_reg) << 16; | |
702 | #endif | |
703 | return val; | |
704 | } | |
705 | ||
706 | /* use readsw/writesw to access the fifo whenever possible */ | |
707 | /* assume HCDIRDATA or XFERCTR & addr_reg have been set up */ | |
708 | static void isp1362_read_fifo(struct isp1362_hcd *isp1362_hcd, void *buf, u16 len) | |
709 | { | |
710 | u8 *dp = buf; | |
711 | u16 data; | |
712 | ||
713 | if (!len) | |
714 | return; | |
715 | ||
716 | _BUG_ON(!irqs_disabled()); | |
717 | ||
718 | RDBG("%s: Reading %d byte from fifo to mem @ %p\n", __func__, len, buf); | |
719 | #if USE_32BIT | |
720 | if (len >= 4) { | |
721 | RDBG("%s: Using readsl for %d dwords\n", __func__, len >> 2); | |
722 | readsl(isp1362_hcd->data_reg, dp, len >> 2); | |
723 | dp += len & ~3; | |
724 | len &= 3; | |
725 | } | |
726 | #endif | |
727 | if (len >= 2) { | |
728 | RDBG("%s: Using readsw for %d words\n", __func__, len >> 1); | |
729 | insw((unsigned long)isp1362_hcd->data_reg, dp, len >> 1); | |
730 | dp += len & ~1; | |
731 | len &= 1; | |
732 | } | |
733 | ||
734 | BUG_ON(len & ~1); | |
735 | if (len > 0) { | |
736 | data = isp1362_read_data16(isp1362_hcd); | |
737 | RDBG("%s: Reading trailing byte %02x to mem @ %08x\n", __func__, | |
738 | (u8)data, (u32)dp); | |
739 | *dp = (u8)data; | |
740 | } | |
741 | } | |
742 | ||
743 | static void isp1362_write_fifo(struct isp1362_hcd *isp1362_hcd, void *buf, u16 len) | |
744 | { | |
745 | u8 *dp = buf; | |
746 | u16 data; | |
747 | ||
748 | if (!len) | |
749 | return; | |
750 | ||
b0a9cf29 | 751 | if ((unsigned long)dp & 0x1) { |
a9d43091 LW |
752 | /* not aligned */ |
753 | for (; len > 1; len -= 2) { | |
754 | data = *dp++; | |
755 | data |= *dp++ << 8; | |
756 | isp1362_write_data16(isp1362_hcd, data); | |
757 | } | |
758 | if (len) | |
759 | isp1362_write_data16(isp1362_hcd, *dp); | |
760 | return; | |
761 | } | |
762 | ||
763 | _BUG_ON(!irqs_disabled()); | |
764 | ||
765 | RDBG("%s: Writing %d byte to fifo from memory @%p\n", __func__, len, buf); | |
766 | #if USE_32BIT | |
767 | if (len >= 4) { | |
768 | RDBG("%s: Using writesl for %d dwords\n", __func__, len >> 2); | |
769 | writesl(isp1362_hcd->data_reg, dp, len >> 2); | |
770 | dp += len & ~3; | |
771 | len &= 3; | |
772 | } | |
773 | #endif | |
774 | if (len >= 2) { | |
775 | RDBG("%s: Using writesw for %d words\n", __func__, len >> 1); | |
776 | outsw((unsigned long)isp1362_hcd->data_reg, dp, len >> 1); | |
777 | dp += len & ~1; | |
778 | len &= 1; | |
779 | } | |
780 | ||
781 | BUG_ON(len & ~1); | |
782 | if (len > 0) { | |
783 | /* finally write any trailing byte; we don't need to care | |
784 | * about the high byte of the last word written | |
785 | */ | |
786 | data = (u16)*dp; | |
787 | RDBG("%s: Sending trailing byte %02x from mem @ %08x\n", __func__, | |
788 | data, (u32)dp); | |
789 | isp1362_write_data16(isp1362_hcd, data); | |
790 | } | |
791 | } | |
792 | ||
793 | #define isp1362_read_reg16(d, r) ({ \ | |
794 | u16 __v; \ | |
795 | REG_WIDTH_TEST(ISP1362_REG_##r, REG_WIDTH_16); \ | |
796 | isp1362_write_addr(d, ISP1362_REG_##r); \ | |
797 | __v = isp1362_read_data16(d); \ | |
798 | RDBG("%s: Read %04x from %s[%02x]\n", __func__, __v, #r, \ | |
799 | ISP1362_REG_NO(ISP1362_REG_##r)); \ | |
800 | __v; \ | |
801 | }) | |
802 | ||
803 | #define isp1362_read_reg32(d, r) ({ \ | |
804 | u32 __v; \ | |
805 | REG_WIDTH_TEST(ISP1362_REG_##r, REG_WIDTH_32); \ | |
806 | isp1362_write_addr(d, ISP1362_REG_##r); \ | |
807 | __v = isp1362_read_data32(d); \ | |
808 | RDBG("%s: Read %08x from %s[%02x]\n", __func__, __v, #r, \ | |
809 | ISP1362_REG_NO(ISP1362_REG_##r)); \ | |
810 | __v; \ | |
811 | }) | |
812 | ||
813 | #define isp1362_write_reg16(d, r, v) { \ | |
814 | REG_WIDTH_TEST(ISP1362_REG_##r, REG_WIDTH_16); \ | |
815 | isp1362_write_addr(d, (ISP1362_REG_##r) | ISP1362_REG_WRITE_OFFSET); \ | |
816 | isp1362_write_data16(d, (u16)(v)); \ | |
817 | RDBG("%s: Wrote %04x to %s[%02x]\n", __func__, (u16)(v), #r, \ | |
818 | ISP1362_REG_NO(ISP1362_REG_##r)); \ | |
819 | } | |
820 | ||
821 | #define isp1362_write_reg32(d, r, v) { \ | |
822 | REG_WIDTH_TEST(ISP1362_REG_##r, REG_WIDTH_32); \ | |
823 | isp1362_write_addr(d, (ISP1362_REG_##r) | ISP1362_REG_WRITE_OFFSET); \ | |
824 | isp1362_write_data32(d, (u32)(v)); \ | |
825 | RDBG("%s: Wrote %08x to %s[%02x]\n", __func__, (u32)(v), #r, \ | |
826 | ISP1362_REG_NO(ISP1362_REG_##r)); \ | |
827 | } | |
828 | ||
829 | #define isp1362_set_mask16(d, r, m) { \ | |
830 | u16 __v; \ | |
831 | __v = isp1362_read_reg16(d, r); \ | |
832 | if ((__v | m) != __v) \ | |
833 | isp1362_write_reg16(d, r, __v | m); \ | |
834 | } | |
835 | ||
836 | #define isp1362_clr_mask16(d, r, m) { \ | |
837 | u16 __v; \ | |
838 | __v = isp1362_read_reg16(d, r); \ | |
839 | if ((__v & ~m) != __v) \ | |
840 | isp1362_write_reg16(d, r, __v & ~m); \ | |
841 | } | |
842 | ||
843 | #define isp1362_set_mask32(d, r, m) { \ | |
844 | u32 __v; \ | |
845 | __v = isp1362_read_reg32(d, r); \ | |
846 | if ((__v | m) != __v) \ | |
847 | isp1362_write_reg32(d, r, __v | m); \ | |
848 | } | |
849 | ||
850 | #define isp1362_clr_mask32(d, r, m) { \ | |
851 | u32 __v; \ | |
852 | __v = isp1362_read_reg32(d, r); \ | |
853 | if ((__v & ~m) != __v) \ | |
854 | isp1362_write_reg32(d, r, __v & ~m); \ | |
855 | } | |
856 | ||
857 | #ifdef ISP1362_DEBUG | |
858 | #define isp1362_show_reg(d, r) { \ | |
859 | if ((ISP1362_REG_##r & REG_WIDTH_MASK) == REG_WIDTH_32) \ | |
860 | DBG(0, "%-12s[%02x]: %08x\n", #r, \ | |
861 | ISP1362_REG_NO(ISP1362_REG_##r), isp1362_read_reg32(d, r)); \ | |
862 | else \ | |
863 | DBG(0, "%-12s[%02x]: %04x\n", #r, \ | |
864 | ISP1362_REG_NO(ISP1362_REG_##r), isp1362_read_reg16(d, r)); \ | |
865 | } | |
866 | #else | |
867 | #define isp1362_show_reg(d, r) do {} while (0) | |
868 | #endif | |
869 | ||
870 | static void __attribute__((__unused__)) isp1362_show_regs(struct isp1362_hcd *isp1362_hcd) | |
871 | { | |
872 | isp1362_show_reg(isp1362_hcd, HCREVISION); | |
873 | isp1362_show_reg(isp1362_hcd, HCCONTROL); | |
874 | isp1362_show_reg(isp1362_hcd, HCCMDSTAT); | |
875 | isp1362_show_reg(isp1362_hcd, HCINTSTAT); | |
876 | isp1362_show_reg(isp1362_hcd, HCINTENB); | |
877 | isp1362_show_reg(isp1362_hcd, HCFMINTVL); | |
878 | isp1362_show_reg(isp1362_hcd, HCFMREM); | |
879 | isp1362_show_reg(isp1362_hcd, HCFMNUM); | |
880 | isp1362_show_reg(isp1362_hcd, HCLSTHRESH); | |
881 | isp1362_show_reg(isp1362_hcd, HCRHDESCA); | |
882 | isp1362_show_reg(isp1362_hcd, HCRHDESCB); | |
883 | isp1362_show_reg(isp1362_hcd, HCRHSTATUS); | |
884 | isp1362_show_reg(isp1362_hcd, HCRHPORT1); | |
885 | isp1362_show_reg(isp1362_hcd, HCRHPORT2); | |
886 | ||
887 | isp1362_show_reg(isp1362_hcd, HCHWCFG); | |
888 | isp1362_show_reg(isp1362_hcd, HCDMACFG); | |
889 | isp1362_show_reg(isp1362_hcd, HCXFERCTR); | |
890 | isp1362_show_reg(isp1362_hcd, HCuPINT); | |
891 | ||
892 | if (in_interrupt()) | |
893 | DBG(0, "%-12s[%02x]: %04x\n", "HCuPINTENB", | |
894 | ISP1362_REG_NO(ISP1362_REG_HCuPINTENB), isp1362_hcd->irqenb); | |
895 | else | |
896 | isp1362_show_reg(isp1362_hcd, HCuPINTENB); | |
897 | isp1362_show_reg(isp1362_hcd, HCCHIPID); | |
898 | isp1362_show_reg(isp1362_hcd, HCSCRATCH); | |
899 | isp1362_show_reg(isp1362_hcd, HCBUFSTAT); | |
900 | isp1362_show_reg(isp1362_hcd, HCDIRADDR); | |
901 | /* Access would advance fifo | |
902 | * isp1362_show_reg(isp1362_hcd, HCDIRDATA); | |
903 | */ | |
904 | isp1362_show_reg(isp1362_hcd, HCISTLBUFSZ); | |
905 | isp1362_show_reg(isp1362_hcd, HCISTLRATE); | |
906 | isp1362_show_reg(isp1362_hcd, HCINTLBUFSZ); | |
907 | isp1362_show_reg(isp1362_hcd, HCINTLBLKSZ); | |
908 | isp1362_show_reg(isp1362_hcd, HCINTLDONE); | |
909 | isp1362_show_reg(isp1362_hcd, HCINTLSKIP); | |
910 | isp1362_show_reg(isp1362_hcd, HCINTLLAST); | |
911 | isp1362_show_reg(isp1362_hcd, HCINTLCURR); | |
912 | isp1362_show_reg(isp1362_hcd, HCATLBUFSZ); | |
913 | isp1362_show_reg(isp1362_hcd, HCATLBLKSZ); | |
914 | /* only valid after ATL_DONE interrupt | |
915 | * isp1362_show_reg(isp1362_hcd, HCATLDONE); | |
916 | */ | |
917 | isp1362_show_reg(isp1362_hcd, HCATLSKIP); | |
918 | isp1362_show_reg(isp1362_hcd, HCATLLAST); | |
919 | isp1362_show_reg(isp1362_hcd, HCATLCURR); | |
920 | isp1362_show_reg(isp1362_hcd, HCATLDTC); | |
921 | isp1362_show_reg(isp1362_hcd, HCATLDTCTO); | |
922 | } | |
923 | ||
924 | static void isp1362_write_diraddr(struct isp1362_hcd *isp1362_hcd, u16 offset, u16 len) | |
925 | { | |
926 | _BUG_ON(offset & 1); | |
927 | _BUG_ON(offset >= ISP1362_BUF_SIZE); | |
928 | _BUG_ON(len > ISP1362_BUF_SIZE); | |
929 | _BUG_ON(offset + len > ISP1362_BUF_SIZE); | |
930 | len = (len + 1) & ~1; | |
931 | ||
932 | isp1362_clr_mask16(isp1362_hcd, HCDMACFG, HCDMACFG_CTR_ENABLE); | |
933 | isp1362_write_reg32(isp1362_hcd, HCDIRADDR, | |
934 | HCDIRADDR_ADDR(offset) | HCDIRADDR_COUNT(len)); | |
935 | } | |
936 | ||
937 | static void isp1362_read_buffer(struct isp1362_hcd *isp1362_hcd, void *buf, u16 offset, int len) | |
938 | { | |
939 | _BUG_ON(offset & 1); | |
940 | ||
941 | isp1362_write_diraddr(isp1362_hcd, offset, len); | |
942 | ||
b0a9cf29 MF |
943 | DBG(3, "%s: Reading %d byte from buffer @%04x to memory @ %p\n", |
944 | __func__, len, offset, buf); | |
a9d43091 LW |
945 | |
946 | isp1362_write_reg16(isp1362_hcd, HCuPINT, HCuPINT_EOT); | |
947 | _WARN_ON((isp1362_read_reg16(isp1362_hcd, HCuPINT) & HCuPINT_EOT)); | |
948 | ||
949 | isp1362_write_addr(isp1362_hcd, ISP1362_REG_HCDIRDATA); | |
950 | ||
951 | isp1362_read_fifo(isp1362_hcd, buf, len); | |
952 | _WARN_ON(!(isp1362_read_reg16(isp1362_hcd, HCuPINT) & HCuPINT_EOT)); | |
953 | isp1362_write_reg16(isp1362_hcd, HCuPINT, HCuPINT_EOT); | |
954 | _WARN_ON((isp1362_read_reg16(isp1362_hcd, HCuPINT) & HCuPINT_EOT)); | |
955 | } | |
956 | ||
957 | static void isp1362_write_buffer(struct isp1362_hcd *isp1362_hcd, void *buf, u16 offset, int len) | |
958 | { | |
959 | _BUG_ON(offset & 1); | |
960 | ||
961 | isp1362_write_diraddr(isp1362_hcd, offset, len); | |
962 | ||
b0a9cf29 MF |
963 | DBG(3, "%s: Writing %d byte to buffer @%04x from memory @ %p\n", |
964 | __func__, len, offset, buf); | |
a9d43091 LW |
965 | |
966 | isp1362_write_reg16(isp1362_hcd, HCuPINT, HCuPINT_EOT); | |
967 | _WARN_ON((isp1362_read_reg16(isp1362_hcd, HCuPINT) & HCuPINT_EOT)); | |
968 | ||
969 | isp1362_write_addr(isp1362_hcd, ISP1362_REG_HCDIRDATA | ISP1362_REG_WRITE_OFFSET); | |
970 | isp1362_write_fifo(isp1362_hcd, buf, len); | |
971 | ||
972 | _WARN_ON(!(isp1362_read_reg16(isp1362_hcd, HCuPINT) & HCuPINT_EOT)); | |
973 | isp1362_write_reg16(isp1362_hcd, HCuPINT, HCuPINT_EOT); | |
974 | _WARN_ON((isp1362_read_reg16(isp1362_hcd, HCuPINT) & HCuPINT_EOT)); | |
975 | } | |
976 | ||
977 | static void __attribute__((unused)) dump_data(char *buf, int len) | |
978 | { | |
979 | if (dbg_level > 0) { | |
980 | int k; | |
981 | int lf = 0; | |
982 | ||
983 | for (k = 0; k < len; ++k) { | |
984 | if (!lf) | |
985 | DBG(0, "%04x:", k); | |
986 | printk(" %02x", ((u8 *) buf)[k]); | |
987 | lf = 1; | |
988 | if (!k) | |
989 | continue; | |
990 | if (k % 16 == 15) { | |
991 | printk("\n"); | |
992 | lf = 0; | |
993 | continue; | |
994 | } | |
995 | if (k % 8 == 7) | |
996 | printk(" "); | |
997 | if (k % 4 == 3) | |
998 | printk(" "); | |
999 | } | |
1000 | if (lf) | |
1001 | printk("\n"); | |
1002 | } | |
1003 | } | |
1004 | ||
1005 | #if defined(ISP1362_DEBUG) && defined(PTD_TRACE) | |
1006 | ||
1007 | static void dump_ptd(struct ptd *ptd) | |
1008 | { | |
1009 | DBG(0, "EP %p: CC=%x EP=%d DIR=%x CNT=%d LEN=%d MPS=%d TGL=%x ACT=%x FA=%d SPD=%x SF=%x PR=%x LST=%x\n", | |
1010 | container_of(ptd, struct isp1362_ep, ptd), | |
1011 | PTD_GET_CC(ptd), PTD_GET_EP(ptd), PTD_GET_DIR(ptd), | |
1012 | PTD_GET_COUNT(ptd), PTD_GET_LEN(ptd), PTD_GET_MPS(ptd), | |
1013 | PTD_GET_TOGGLE(ptd), PTD_GET_ACTIVE(ptd), PTD_GET_FA(ptd), | |
1014 | PTD_GET_SPD(ptd), PTD_GET_SF_INT(ptd), PTD_GET_PR(ptd), PTD_GET_LAST(ptd)); | |
1015 | DBG(0, " %04x %04x %04x %04x\n", ptd->count, ptd->mps, ptd->len, ptd->faddr); | |
1016 | } | |
1017 | ||
1018 | static void dump_ptd_out_data(struct ptd *ptd, u8 *buf) | |
1019 | { | |
1020 | if (dbg_level > 0) { | |
1021 | if (PTD_GET_DIR(ptd) != PTD_DIR_IN && PTD_GET_LEN(ptd)) { | |
1022 | DBG(0, "--out->\n"); | |
1023 | dump_data(buf, PTD_GET_LEN(ptd)); | |
1024 | } | |
1025 | } | |
1026 | } | |
1027 | ||
1028 | static void dump_ptd_in_data(struct ptd *ptd, u8 *buf) | |
1029 | { | |
1030 | if (dbg_level > 0) { | |
1031 | if (PTD_GET_DIR(ptd) == PTD_DIR_IN && PTD_GET_COUNT(ptd)) { | |
1032 | DBG(0, "<--in--\n"); | |
1033 | dump_data(buf, PTD_GET_COUNT(ptd)); | |
1034 | } | |
1035 | DBG(0, "-----\n"); | |
1036 | } | |
1037 | } | |
1038 | ||
1039 | static void dump_ptd_queue(struct isp1362_ep_queue *epq) | |
1040 | { | |
1041 | struct isp1362_ep *ep; | |
1042 | int dbg = dbg_level; | |
1043 | ||
1044 | dbg_level = 1; | |
1045 | list_for_each_entry(ep, &epq->active, active) { | |
1046 | dump_ptd(&ep->ptd); | |
1047 | dump_data(ep->data, ep->length); | |
1048 | } | |
1049 | dbg_level = dbg; | |
1050 | } | |
1051 | #else | |
1052 | #define dump_ptd(ptd) do {} while (0) | |
1053 | #define dump_ptd_in_data(ptd, buf) do {} while (0) | |
1054 | #define dump_ptd_out_data(ptd, buf) do {} while (0) | |
1055 | #define dump_ptd_data(ptd, buf) do {} while (0) | |
1056 | #define dump_ptd_queue(epq) do {} while (0) | |
1057 | #endif |