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Commit | Line | Data |
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db11e47d SS |
1 | /* |
2 | * Driver for the NXP ISP1760 chip | |
3 | * | |
4 | * However, the code might contain some bugs. What doesn't work for sure is: | |
5 | * - ISO | |
6 | * - OTG | |
7 | e The interrupt line is configured as active low, level. | |
8 | * | |
9 | * (c) 2007 Sebastian Siewior <bigeasy@linutronix.de> | |
10 | * | |
71a9f9d2 AB |
11 | * (c) 2011 Arvid Brodin <arvid.brodin@enea.com> |
12 | * | |
db11e47d SS |
13 | */ |
14 | #include <linux/module.h> | |
15 | #include <linux/kernel.h> | |
16 | #include <linux/slab.h> | |
17 | #include <linux/list.h> | |
18 | #include <linux/usb.h> | |
27729aad | 19 | #include <linux/usb/hcd.h> |
db11e47d SS |
20 | #include <linux/debugfs.h> |
21 | #include <linux/uaccess.h> | |
22 | #include <linux/io.h> | |
db8516f6 | 23 | #include <linux/mm.h> |
6d50c60e | 24 | #include <linux/timer.h> |
db11e47d | 25 | #include <asm/unaligned.h> |
db8516f6 | 26 | #include <asm/cacheflush.h> |
db11e47d | 27 | |
db11e47d SS |
28 | #include "isp1760-hcd.h" |
29 | ||
30 | static struct kmem_cache *qtd_cachep; | |
31 | static struct kmem_cache *qh_cachep; | |
71a9f9d2 | 32 | static struct kmem_cache *urb_listitem_cachep; |
db11e47d SS |
33 | |
34 | struct isp1760_hcd { | |
35 | u32 hcs_params; | |
36 | spinlock_t lock; | |
71a9f9d2 | 37 | struct slotinfo atl_slots[32]; |
d05b6ec0 | 38 | int atl_done_map; |
71a9f9d2 | 39 | struct slotinfo int_slots[32]; |
d05b6ec0 | 40 | int int_done_map; |
db11e47d | 41 | struct memory_chunk memory_pool[BLOCKS]; |
71a9f9d2 | 42 | struct list_head controlqhs, bulkqhs, interruptqhs; |
db11e47d SS |
43 | |
44 | /* periodic schedule support */ | |
45 | #define DEFAULT_I_TDPS 1024 | |
46 | unsigned periodic_size; | |
47 | unsigned i_thresh; | |
48 | unsigned long reset_done; | |
49 | unsigned long next_statechange; | |
3faefc88 | 50 | unsigned int devflags; |
db11e47d SS |
51 | }; |
52 | ||
53 | static inline struct isp1760_hcd *hcd_to_priv(struct usb_hcd *hcd) | |
54 | { | |
55 | return (struct isp1760_hcd *) (hcd->hcd_priv); | |
56 | } | |
db11e47d SS |
57 | |
58 | /* Section 2.2 Host Controller Capability Registers */ | |
59 | #define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */ | |
60 | #define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */ | |
61 | #define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */ | |
62 | #define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */ | |
63 | #define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */ | |
64 | #define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */ | |
65 | #define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */ | |
66 | ||
67 | /* Section 2.3 Host Controller Operational Registers */ | |
68 | #define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */ | |
69 | #define CMD_RESET (1<<1) /* reset HC not bus */ | |
70 | #define CMD_RUN (1<<0) /* start/stop HC */ | |
71 | #define STS_PCD (1<<2) /* port change detect */ | |
72 | #define FLAG_CF (1<<0) /* true: we'll support "high speed" */ | |
73 | ||
74 | #define PORT_OWNER (1<<13) /* true: companion hc owns this port */ | |
75 | #define PORT_POWER (1<<12) /* true: has power (see PPC) */ | |
76 | #define PORT_USB11(x) (((x) & (3 << 10)) == (1 << 10)) /* USB 1.1 device */ | |
77 | #define PORT_RESET (1<<8) /* reset port */ | |
78 | #define PORT_SUSPEND (1<<7) /* suspend port */ | |
79 | #define PORT_RESUME (1<<6) /* resume it */ | |
80 | #define PORT_PE (1<<2) /* port enable */ | |
81 | #define PORT_CSC (1<<1) /* connect status change */ | |
82 | #define PORT_CONNECT (1<<0) /* device connected */ | |
83 | #define PORT_RWC_BITS (PORT_CSC) | |
84 | ||
85 | struct isp1760_qtd { | |
db11e47d | 86 | u8 packet_type; |
db11e47d | 87 | void *data_buffer; |
a041d8e4 AB |
88 | u32 payload_addr; |
89 | ||
db11e47d SS |
90 | /* the rest is HCD-private */ |
91 | struct list_head qtd_list; | |
92 | struct urb *urb; | |
93 | size_t length; | |
71a9f9d2 AB |
94 | size_t actual_length; |
95 | ||
96 | /* QTD_ENQUEUED: waiting for transfer (inactive) */ | |
97 | /* QTD_PAYLOAD_ALLOC: chip mem has been allocated for payload */ | |
98 | /* QTD_XFER_STARTED: valid ptd has been written to isp176x - only | |
99 | interrupt handler may touch this qtd! */ | |
100 | /* QTD_XFER_COMPLETE: payload has been transferred successfully */ | |
101 | /* QTD_RETIRE: transfer error/abort qtd */ | |
102 | #define QTD_ENQUEUED 0 | |
103 | #define QTD_PAYLOAD_ALLOC 1 | |
104 | #define QTD_XFER_STARTED 2 | |
105 | #define QTD_XFER_COMPLETE 3 | |
106 | #define QTD_RETIRE 4 | |
db11e47d | 107 | u32 status; |
db11e47d SS |
108 | }; |
109 | ||
71a9f9d2 | 110 | /* Queue head, one for each active endpoint */ |
db11e47d | 111 | struct isp1760_qh { |
71a9f9d2 | 112 | struct list_head qh_list; |
db11e47d | 113 | struct list_head qtd_list; |
db11e47d SS |
114 | u32 toggle; |
115 | u32 ping; | |
71a9f9d2 AB |
116 | int slot; |
117 | }; | |
118 | ||
119 | struct urb_listitem { | |
120 | struct list_head urb_list; | |
121 | struct urb *urb; | |
db11e47d SS |
122 | }; |
123 | ||
bedc0c31 AB |
124 | /* |
125 | * Access functions for isp176x registers (addresses 0..0x03FF). | |
126 | */ | |
127 | static u32 reg_read32(void __iomem *base, u32 reg) | |
db11e47d | 128 | { |
bedc0c31 | 129 | return readl(base + reg); |
db11e47d SS |
130 | } |
131 | ||
bedc0c31 | 132 | static void reg_write32(void __iomem *base, u32 reg, u32 val) |
db11e47d | 133 | { |
bedc0c31 | 134 | writel(val, base + reg); |
db11e47d SS |
135 | } |
136 | ||
137 | /* | |
bedc0c31 AB |
138 | * Access functions for isp176x memory (offset >= 0x0400). |
139 | * | |
140 | * bank_reads8() reads memory locations prefetched by an earlier write to | |
141 | * HC_MEMORY_REG (see isp176x datasheet). Unless you want to do fancy multi- | |
142 | * bank optimizations, you should use the more generic mem_reads8() below. | |
143 | * | |
144 | * For access to ptd memory, use the specialized ptd_read() and ptd_write() | |
145 | * below. | |
146 | * | |
147 | * These functions copy via MMIO data to/from the device. memcpy_{to|from}io() | |
db11e47d SS |
148 | * doesn't quite work because some people have to enforce 32-bit access |
149 | */ | |
bedc0c31 AB |
150 | static void bank_reads8(void __iomem *src_base, u32 src_offset, u32 bank_addr, |
151 | __u32 *dst, u32 bytes) | |
db11e47d | 152 | { |
bedc0c31 | 153 | __u32 __iomem *src; |
db11e47d | 154 | u32 val; |
bedc0c31 AB |
155 | __u8 *src_byteptr; |
156 | __u8 *dst_byteptr; | |
db11e47d | 157 | |
bedc0c31 | 158 | src = src_base + (bank_addr | src_offset); |
db11e47d | 159 | |
bedc0c31 AB |
160 | if (src_offset < PAYLOAD_OFFSET) { |
161 | while (bytes >= 4) { | |
162 | *dst = le32_to_cpu(__raw_readl(src)); | |
163 | bytes -= 4; | |
164 | src++; | |
165 | dst++; | |
166 | } | |
167 | } else { | |
168 | while (bytes >= 4) { | |
169 | *dst = __raw_readl(src); | |
170 | bytes -= 4; | |
171 | src++; | |
172 | dst++; | |
173 | } | |
db11e47d SS |
174 | } |
175 | ||
bedc0c31 | 176 | if (!bytes) |
db11e47d SS |
177 | return; |
178 | ||
179 | /* in case we have 3, 2 or 1 by left. The dst buffer may not be fully | |
180 | * allocated. | |
181 | */ | |
bedc0c31 AB |
182 | if (src_offset < PAYLOAD_OFFSET) |
183 | val = le32_to_cpu(__raw_readl(src)); | |
184 | else | |
185 | val = __raw_readl(src); | |
186 | ||
187 | dst_byteptr = (void *) dst; | |
188 | src_byteptr = (void *) &val; | |
189 | while (bytes > 0) { | |
190 | *dst_byteptr = *src_byteptr; | |
191 | dst_byteptr++; | |
192 | src_byteptr++; | |
193 | bytes--; | |
db11e47d SS |
194 | } |
195 | } | |
196 | ||
bedc0c31 AB |
197 | static void mem_reads8(void __iomem *src_base, u32 src_offset, void *dst, |
198 | u32 bytes) | |
db11e47d | 199 | { |
bedc0c31 AB |
200 | reg_write32(src_base, HC_MEMORY_REG, src_offset + ISP_BANK(0)); |
201 | ndelay(90); | |
202 | bank_reads8(src_base, src_offset, ISP_BANK(0), dst, bytes); | |
203 | } | |
204 | ||
205 | static void mem_writes8(void __iomem *dst_base, u32 dst_offset, | |
206 | __u32 const *src, u32 bytes) | |
207 | { | |
208 | __u32 __iomem *dst; | |
209 | ||
210 | dst = dst_base + dst_offset; | |
211 | ||
212 | if (dst_offset < PAYLOAD_OFFSET) { | |
213 | while (bytes >= 4) { | |
214 | __raw_writel(cpu_to_le32(*src), dst); | |
215 | bytes -= 4; | |
216 | src++; | |
217 | dst++; | |
218 | } | |
219 | } else { | |
220 | while (bytes >= 4) { | |
221 | __raw_writel(*src, dst); | |
222 | bytes -= 4; | |
223 | src++; | |
224 | dst++; | |
225 | } | |
db11e47d SS |
226 | } |
227 | ||
bedc0c31 | 228 | if (!bytes) |
db11e47d | 229 | return; |
bedc0c31 AB |
230 | /* in case we have 3, 2 or 1 bytes left. The buffer is allocated and the |
231 | * extra bytes should not be read by the HW. | |
db11e47d SS |
232 | */ |
233 | ||
bedc0c31 AB |
234 | if (dst_offset < PAYLOAD_OFFSET) |
235 | __raw_writel(cpu_to_le32(*src), dst); | |
236 | else | |
237 | __raw_writel(*src, dst); | |
db11e47d SS |
238 | } |
239 | ||
bedc0c31 AB |
240 | /* |
241 | * Read and write ptds. 'ptd_offset' should be one of ISO_PTD_OFFSET, | |
242 | * INT_PTD_OFFSET, and ATL_PTD_OFFSET. 'slot' should be less than 32. | |
243 | */ | |
244 | static void ptd_read(void __iomem *base, u32 ptd_offset, u32 slot, | |
245 | struct ptd *ptd) | |
246 | { | |
247 | reg_write32(base, HC_MEMORY_REG, | |
248 | ISP_BANK(0) + ptd_offset + slot*sizeof(*ptd)); | |
249 | ndelay(90); | |
250 | bank_reads8(base, ptd_offset + slot*sizeof(*ptd), ISP_BANK(0), | |
251 | (void *) ptd, sizeof(*ptd)); | |
252 | } | |
253 | ||
254 | static void ptd_write(void __iomem *base, u32 ptd_offset, u32 slot, | |
255 | struct ptd *ptd) | |
256 | { | |
257 | mem_writes8(base, ptd_offset + slot*sizeof(*ptd) + sizeof(ptd->dw0), | |
258 | &ptd->dw1, 7*sizeof(ptd->dw1)); | |
259 | /* Make sure dw0 gets written last (after other dw's and after payload) | |
260 | since it contains the enable bit */ | |
261 | wmb(); | |
262 | mem_writes8(base, ptd_offset + slot*sizeof(*ptd), &ptd->dw0, | |
263 | sizeof(ptd->dw0)); | |
264 | } | |
265 | ||
266 | ||
db11e47d SS |
267 | /* memory management of the 60kb on the chip from 0x1000 to 0xffff */ |
268 | static void init_memory(struct isp1760_hcd *priv) | |
269 | { | |
a041d8e4 AB |
270 | int i, curr; |
271 | u32 payload_addr; | |
db11e47d | 272 | |
a041d8e4 | 273 | payload_addr = PAYLOAD_OFFSET; |
db11e47d | 274 | for (i = 0; i < BLOCK_1_NUM; i++) { |
a041d8e4 | 275 | priv->memory_pool[i].start = payload_addr; |
db11e47d SS |
276 | priv->memory_pool[i].size = BLOCK_1_SIZE; |
277 | priv->memory_pool[i].free = 1; | |
a041d8e4 | 278 | payload_addr += priv->memory_pool[i].size; |
db11e47d SS |
279 | } |
280 | ||
a041d8e4 AB |
281 | curr = i; |
282 | for (i = 0; i < BLOCK_2_NUM; i++) { | |
283 | priv->memory_pool[curr + i].start = payload_addr; | |
284 | priv->memory_pool[curr + i].size = BLOCK_2_SIZE; | |
285 | priv->memory_pool[curr + i].free = 1; | |
286 | payload_addr += priv->memory_pool[curr + i].size; | |
db11e47d SS |
287 | } |
288 | ||
a041d8e4 AB |
289 | curr = i; |
290 | for (i = 0; i < BLOCK_3_NUM; i++) { | |
291 | priv->memory_pool[curr + i].start = payload_addr; | |
292 | priv->memory_pool[curr + i].size = BLOCK_3_SIZE; | |
293 | priv->memory_pool[curr + i].free = 1; | |
294 | payload_addr += priv->memory_pool[curr + i].size; | |
db11e47d SS |
295 | } |
296 | ||
34537731 | 297 | WARN_ON(payload_addr - priv->memory_pool[0].start > PAYLOAD_AREA_SIZE); |
db11e47d SS |
298 | } |
299 | ||
6bda21bc | 300 | static void alloc_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd) |
db11e47d | 301 | { |
6bda21bc | 302 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
db11e47d SS |
303 | int i; |
304 | ||
34537731 | 305 | WARN_ON(qtd->payload_addr); |
a041d8e4 AB |
306 | |
307 | if (!qtd->length) | |
308 | return; | |
db11e47d SS |
309 | |
310 | for (i = 0; i < BLOCKS; i++) { | |
a041d8e4 | 311 | if (priv->memory_pool[i].size >= qtd->length && |
db11e47d | 312 | priv->memory_pool[i].free) { |
db11e47d | 313 | priv->memory_pool[i].free = 0; |
a041d8e4 AB |
314 | qtd->payload_addr = priv->memory_pool[i].start; |
315 | return; | |
db11e47d SS |
316 | } |
317 | } | |
db11e47d SS |
318 | } |
319 | ||
6bda21bc | 320 | static void free_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd) |
db11e47d | 321 | { |
6bda21bc | 322 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
db11e47d SS |
323 | int i; |
324 | ||
a041d8e4 | 325 | if (!qtd->payload_addr) |
db11e47d SS |
326 | return; |
327 | ||
328 | for (i = 0; i < BLOCKS; i++) { | |
a041d8e4 | 329 | if (priv->memory_pool[i].start == qtd->payload_addr) { |
34537731 | 330 | WARN_ON(priv->memory_pool[i].free); |
db11e47d | 331 | priv->memory_pool[i].free = 1; |
a041d8e4 AB |
332 | qtd->payload_addr = 0; |
333 | return; | |
db11e47d SS |
334 | } |
335 | } | |
336 | ||
6bda21bc AB |
337 | dev_err(hcd->self.controller, "%s: Invalid pointer: %08x\n", |
338 | __func__, qtd->payload_addr); | |
71a9f9d2 AB |
339 | WARN_ON(1); |
340 | qtd->payload_addr = 0; | |
db11e47d SS |
341 | } |
342 | ||
bedc0c31 | 343 | static int handshake(struct usb_hcd *hcd, u32 reg, |
db11e47d SS |
344 | u32 mask, u32 done, int usec) |
345 | { | |
346 | u32 result; | |
347 | ||
348 | do { | |
bedc0c31 | 349 | result = reg_read32(hcd->regs, reg); |
db11e47d SS |
350 | if (result == ~0) |
351 | return -ENODEV; | |
352 | result &= mask; | |
353 | if (result == done) | |
354 | return 0; | |
355 | udelay(1); | |
356 | usec--; | |
357 | } while (usec > 0); | |
358 | return -ETIMEDOUT; | |
359 | } | |
360 | ||
361 | /* reset a non-running (STS_HALT == 1) controller */ | |
6bda21bc | 362 | static int ehci_reset(struct usb_hcd *hcd) |
db11e47d SS |
363 | { |
364 | int retval; | |
6bda21bc AB |
365 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
366 | ||
bedc0c31 | 367 | u32 command = reg_read32(hcd->regs, HC_USBCMD); |
db11e47d SS |
368 | |
369 | command |= CMD_RESET; | |
bedc0c31 | 370 | reg_write32(hcd->regs, HC_USBCMD, command); |
db11e47d SS |
371 | hcd->state = HC_STATE_HALT; |
372 | priv->next_statechange = jiffies; | |
bedc0c31 | 373 | retval = handshake(hcd, HC_USBCMD, |
db11e47d SS |
374 | CMD_RESET, 0, 250 * 1000); |
375 | return retval; | |
376 | } | |
377 | ||
71a9f9d2 | 378 | static struct isp1760_qh *qh_alloc(gfp_t flags) |
db11e47d SS |
379 | { |
380 | struct isp1760_qh *qh; | |
381 | ||
382 | qh = kmem_cache_zalloc(qh_cachep, flags); | |
383 | if (!qh) | |
71a9f9d2 | 384 | return NULL; |
db11e47d | 385 | |
71a9f9d2 | 386 | INIT_LIST_HEAD(&qh->qh_list); |
db11e47d | 387 | INIT_LIST_HEAD(&qh->qtd_list); |
71a9f9d2 AB |
388 | qh->slot = -1; |
389 | ||
db11e47d SS |
390 | return qh; |
391 | } | |
392 | ||
71a9f9d2 AB |
393 | static void qh_free(struct isp1760_qh *qh) |
394 | { | |
395 | WARN_ON(!list_empty(&qh->qtd_list)); | |
396 | WARN_ON(qh->slot > -1); | |
397 | kmem_cache_free(qh_cachep, qh); | |
398 | } | |
db11e47d SS |
399 | |
400 | /* one-time init, only for memory state */ | |
401 | static int priv_init(struct usb_hcd *hcd) | |
402 | { | |
403 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | |
404 | u32 hcc_params; | |
405 | ||
406 | spin_lock_init(&priv->lock); | |
407 | ||
71a9f9d2 AB |
408 | INIT_LIST_HEAD(&priv->interruptqhs); |
409 | INIT_LIST_HEAD(&priv->controlqhs); | |
410 | INIT_LIST_HEAD(&priv->bulkqhs); | |
411 | ||
db11e47d SS |
412 | /* |
413 | * hw default: 1K periodic list heads, one per frame. | |
414 | * periodic_size can shrink by USBCMD update if hcc_params allows. | |
415 | */ | |
416 | priv->periodic_size = DEFAULT_I_TDPS; | |
417 | ||
418 | /* controllers may cache some of the periodic schedule ... */ | |
bedc0c31 | 419 | hcc_params = reg_read32(hcd->regs, HC_HCCPARAMS); |
db11e47d SS |
420 | /* full frame cache */ |
421 | if (HCC_ISOC_CACHE(hcc_params)) | |
422 | priv->i_thresh = 8; | |
423 | else /* N microframes cached */ | |
424 | priv->i_thresh = 2 + HCC_ISOC_THRES(hcc_params); | |
425 | ||
426 | return 0; | |
427 | } | |
428 | ||
429 | static int isp1760_hc_setup(struct usb_hcd *hcd) | |
430 | { | |
431 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | |
432 | int result; | |
3faefc88 NC |
433 | u32 scratch, hwmode; |
434 | ||
435 | /* Setup HW Mode Control: This assumes a level active-low interrupt */ | |
436 | hwmode = HW_DATA_BUS_32BIT; | |
437 | ||
438 | if (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16) | |
439 | hwmode &= ~HW_DATA_BUS_32BIT; | |
440 | if (priv->devflags & ISP1760_FLAG_ANALOG_OC) | |
441 | hwmode |= HW_ANA_DIGI_OC; | |
442 | if (priv->devflags & ISP1760_FLAG_DACK_POL_HIGH) | |
443 | hwmode |= HW_DACK_POL_HIGH; | |
444 | if (priv->devflags & ISP1760_FLAG_DREQ_POL_HIGH) | |
445 | hwmode |= HW_DREQ_POL_HIGH; | |
9da69c60 MH |
446 | if (priv->devflags & ISP1760_FLAG_INTR_POL_HIGH) |
447 | hwmode |= HW_INTR_HIGH_ACT; | |
448 | if (priv->devflags & ISP1760_FLAG_INTR_EDGE_TRIG) | |
449 | hwmode |= HW_INTR_EDGE_TRIG; | |
3faefc88 NC |
450 | |
451 | /* | |
452 | * We have to set this first in case we're in 16-bit mode. | |
453 | * Write it twice to ensure correct upper bits if switching | |
454 | * to 16-bit mode. | |
455 | */ | |
bedc0c31 AB |
456 | reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode); |
457 | reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode); | |
db11e47d | 458 | |
bedc0c31 | 459 | reg_write32(hcd->regs, HC_SCRATCH_REG, 0xdeadbabe); |
3faefc88 | 460 | /* Change bus pattern */ |
bedc0c31 AB |
461 | scratch = reg_read32(hcd->regs, HC_CHIP_ID_REG); |
462 | scratch = reg_read32(hcd->regs, HC_SCRATCH_REG); | |
db11e47d | 463 | if (scratch != 0xdeadbabe) { |
6bda21bc | 464 | dev_err(hcd->self.controller, "Scratch test failed.\n"); |
db11e47d SS |
465 | return -ENODEV; |
466 | } | |
467 | ||
468 | /* pre reset */ | |
71a9f9d2 AB |
469 | reg_write32(hcd->regs, HC_BUFFER_STATUS_REG, 0); |
470 | reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE); | |
471 | reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE); | |
472 | reg_write32(hcd->regs, HC_ISO_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE); | |
db11e47d SS |
473 | |
474 | /* reset */ | |
bedc0c31 | 475 | reg_write32(hcd->regs, HC_RESET_REG, SW_RESET_RESET_ALL); |
db11e47d SS |
476 | mdelay(100); |
477 | ||
bedc0c31 | 478 | reg_write32(hcd->regs, HC_RESET_REG, SW_RESET_RESET_HC); |
db11e47d SS |
479 | mdelay(100); |
480 | ||
6bda21bc | 481 | result = ehci_reset(hcd); |
db11e47d SS |
482 | if (result) |
483 | return result; | |
484 | ||
485 | /* Step 11 passed */ | |
486 | ||
6bda21bc | 487 | dev_info(hcd->self.controller, "bus width: %d, oc: %s\n", |
3faefc88 NC |
488 | (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16) ? |
489 | 16 : 32, (priv->devflags & ISP1760_FLAG_ANALOG_OC) ? | |
490 | "analog" : "digital"); | |
db11e47d SS |
491 | |
492 | /* ATL reset */ | |
bedc0c31 | 493 | reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode | ALL_ATX_RESET); |
db11e47d | 494 | mdelay(10); |
bedc0c31 | 495 | reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode); |
db11e47d | 496 | |
bedc0c31 | 497 | reg_write32(hcd->regs, HC_INTERRUPT_ENABLE, INTERRUPT_ENABLE_MASK); |
3faefc88 NC |
498 | |
499 | /* | |
500 | * PORT 1 Control register of the ISP1760 is the OTG control | |
42c65396 TH |
501 | * register on ISP1761. Since there is no OTG or device controller |
502 | * support in this driver, we use port 1 as a "normal" USB host port on | |
503 | * both chips. | |
3faefc88 | 504 | */ |
bedc0c31 | 505 | reg_write32(hcd->regs, HC_PORT1_CTRL, PORT1_POWER | PORT1_INIT2); |
42c65396 | 506 | mdelay(10); |
db11e47d | 507 | |
bedc0c31 | 508 | priv->hcs_params = reg_read32(hcd->regs, HC_HCSPARAMS); |
db11e47d SS |
509 | |
510 | return priv_init(hcd); | |
511 | } | |
512 | ||
db11e47d SS |
513 | static u32 base_to_chip(u32 base) |
514 | { | |
515 | return ((base - 0x400) >> 3); | |
516 | } | |
517 | ||
7adc14b1 AB |
518 | static int last_qtd_of_urb(struct isp1760_qtd *qtd, struct isp1760_qh *qh) |
519 | { | |
520 | struct urb *urb; | |
521 | ||
522 | if (list_is_last(&qtd->qtd_list, &qh->qtd_list)) | |
523 | return 1; | |
524 | ||
525 | urb = qtd->urb; | |
526 | qtd = list_entry(qtd->qtd_list.next, typeof(*qtd), qtd_list); | |
527 | return (qtd->urb != urb); | |
528 | } | |
529 | ||
71a9f9d2 AB |
530 | /* magic numbers that can affect system performance */ |
531 | #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */ | |
532 | #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */ | |
533 | #define EHCI_TUNE_RL_TT 0 | |
534 | #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */ | |
535 | #define EHCI_TUNE_MULT_TT 1 | |
536 | #define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */ | |
537 | ||
538 | static void create_ptd_atl(struct isp1760_qh *qh, | |
a041d8e4 | 539 | struct isp1760_qtd *qtd, struct ptd *ptd) |
db11e47d | 540 | { |
db11e47d SS |
541 | u32 maxpacket; |
542 | u32 multi; | |
db11e47d SS |
543 | u32 rl = RL_COUNTER; |
544 | u32 nak = NAK_COUNTER; | |
545 | ||
bedc0c31 AB |
546 | memset(ptd, 0, sizeof(*ptd)); |
547 | ||
db11e47d | 548 | /* according to 3.6.2, max packet len can not be > 0x400 */ |
a041d8e4 AB |
549 | maxpacket = usb_maxpacket(qtd->urb->dev, qtd->urb->pipe, |
550 | usb_pipeout(qtd->urb->pipe)); | |
db11e47d SS |
551 | multi = 1 + ((maxpacket >> 11) & 0x3); |
552 | maxpacket &= 0x7ff; | |
553 | ||
554 | /* DW0 */ | |
71a9f9d2 AB |
555 | ptd->dw0 = DW0_VALID_BIT; |
556 | ptd->dw0 |= TO_DW0_LENGTH(qtd->length); | |
557 | ptd->dw0 |= TO_DW0_MAXPACKET(maxpacket); | |
558 | ptd->dw0 |= TO_DW0_ENDPOINT(usb_pipeendpoint(qtd->urb->pipe)); | |
db11e47d SS |
559 | |
560 | /* DW1 */ | |
a041d8e4 | 561 | ptd->dw1 = usb_pipeendpoint(qtd->urb->pipe) >> 1; |
71a9f9d2 AB |
562 | ptd->dw1 |= TO_DW1_DEVICE_ADDR(usb_pipedevice(qtd->urb->pipe)); |
563 | ptd->dw1 |= TO_DW1_PID_TOKEN(qtd->packet_type); | |
db11e47d | 564 | |
a041d8e4 | 565 | if (usb_pipebulk(qtd->urb->pipe)) |
71a9f9d2 | 566 | ptd->dw1 |= DW1_TRANS_BULK; |
a041d8e4 | 567 | else if (usb_pipeint(qtd->urb->pipe)) |
71a9f9d2 | 568 | ptd->dw1 |= DW1_TRANS_INT; |
db11e47d | 569 | |
a041d8e4 | 570 | if (qtd->urb->dev->speed != USB_SPEED_HIGH) { |
db11e47d SS |
571 | /* split transaction */ |
572 | ||
71a9f9d2 | 573 | ptd->dw1 |= DW1_TRANS_SPLIT; |
a041d8e4 | 574 | if (qtd->urb->dev->speed == USB_SPEED_LOW) |
71a9f9d2 | 575 | ptd->dw1 |= DW1_SE_USB_LOSPEED; |
db11e47d | 576 | |
71a9f9d2 AB |
577 | ptd->dw1 |= TO_DW1_PORT_NUM(qtd->urb->dev->ttport); |
578 | ptd->dw1 |= TO_DW1_HUB_NUM(qtd->urb->dev->tt->hub->devnum); | |
db11e47d SS |
579 | |
580 | /* SE bit for Split INT transfers */ | |
a041d8e4 AB |
581 | if (usb_pipeint(qtd->urb->pipe) && |
582 | (qtd->urb->dev->speed == USB_SPEED_LOW)) | |
bedc0c31 | 583 | ptd->dw1 |= 2 << 16; |
db11e47d | 584 | |
db11e47d SS |
585 | rl = 0; |
586 | nak = 0; | |
587 | } else { | |
71a9f9d2 | 588 | ptd->dw0 |= TO_DW0_MULTI(multi); |
a041d8e4 AB |
589 | if (usb_pipecontrol(qtd->urb->pipe) || |
590 | usb_pipebulk(qtd->urb->pipe)) | |
71a9f9d2 | 591 | ptd->dw3 |= TO_DW3_PING(qh->ping); |
db11e47d SS |
592 | } |
593 | /* DW2 */ | |
bedc0c31 | 594 | ptd->dw2 = 0; |
71a9f9d2 AB |
595 | ptd->dw2 |= TO_DW2_DATA_START_ADDR(base_to_chip(qtd->payload_addr)); |
596 | ptd->dw2 |= TO_DW2_RL(rl); | |
db11e47d SS |
597 | |
598 | /* DW3 */ | |
71a9f9d2 AB |
599 | ptd->dw3 |= TO_DW3_NAKCOUNT(nak); |
600 | ptd->dw3 |= TO_DW3_DATA_TOGGLE(qh->toggle); | |
7adc14b1 AB |
601 | if (usb_pipecontrol(qtd->urb->pipe)) { |
602 | if (qtd->data_buffer == qtd->urb->setup_packet) | |
71a9f9d2 | 603 | ptd->dw3 &= ~TO_DW3_DATA_TOGGLE(1); |
7adc14b1 | 604 | else if (last_qtd_of_urb(qtd, qh)) |
71a9f9d2 | 605 | ptd->dw3 |= TO_DW3_DATA_TOGGLE(1); |
7adc14b1 | 606 | } |
db11e47d | 607 | |
71a9f9d2 | 608 | ptd->dw3 |= DW3_ACTIVE_BIT; |
db11e47d | 609 | /* Cerr */ |
71a9f9d2 | 610 | ptd->dw3 |= TO_DW3_CERR(ERR_COUNTER); |
db11e47d SS |
611 | } |
612 | ||
6bda21bc | 613 | static void transform_add_int(struct isp1760_qh *qh, |
a041d8e4 | 614 | struct isp1760_qtd *qtd, struct ptd *ptd) |
db11e47d | 615 | { |
65f1b525 | 616 | u32 usof; |
db11e47d SS |
617 | u32 period; |
618 | ||
65f1b525 AB |
619 | /* |
620 | * Most of this is guessing. ISP1761 datasheet is quite unclear, and | |
621 | * the algorithm from the original Philips driver code, which was | |
622 | * pretty much used in this driver before as well, is quite horrendous | |
623 | * and, i believe, incorrect. The code below follows the datasheet and | |
624 | * USB2.0 spec as far as I can tell, and plug/unplug seems to be much | |
625 | * more reliable this way (fingers crossed...). | |
626 | */ | |
db11e47d | 627 | |
65f1b525 AB |
628 | if (qtd->urb->dev->speed == USB_SPEED_HIGH) { |
629 | /* urb->interval is in units of microframes (1/8 ms) */ | |
630 | period = qtd->urb->interval >> 3; | |
631 | ||
632 | if (qtd->urb->interval > 4) | |
633 | usof = 0x01; /* One bit set => | |
634 | interval 1 ms * uFrame-match */ | |
635 | else if (qtd->urb->interval > 2) | |
636 | usof = 0x22; /* Two bits set => interval 1/2 ms */ | |
637 | else if (qtd->urb->interval > 1) | |
638 | usof = 0x55; /* Four bits set => interval 1/4 ms */ | |
db11e47d | 639 | else |
65f1b525 | 640 | usof = 0xff; /* All bits set => interval 1/8 ms */ |
db11e47d | 641 | } else { |
65f1b525 AB |
642 | /* urb->interval is in units of frames (1 ms) */ |
643 | period = qtd->urb->interval; | |
644 | usof = 0x0f; /* Execute Start Split on any of the | |
645 | four first uFrames */ | |
646 | ||
647 | /* | |
648 | * First 8 bits in dw5 is uSCS and "specifies which uSOF the | |
649 | * complete split needs to be sent. Valid only for IN." Also, | |
650 | * "All bits can be set to one for every transfer." (p 82, | |
651 | * ISP1761 data sheet.) 0x1c is from Philips driver. Where did | |
652 | * that number come from? 0xff seems to work fine... | |
653 | */ | |
654 | /* ptd->dw5 = 0x1c; */ | |
655 | ptd->dw5 = 0xff; /* Execute Complete Split on any uFrame */ | |
db11e47d SS |
656 | } |
657 | ||
65f1b525 AB |
658 | period = period >> 1;/* Ensure equal or shorter period than requested */ |
659 | period &= 0xf8; /* Mask off too large values and lowest unused 3 bits */ | |
660 | ||
bedc0c31 AB |
661 | ptd->dw2 |= period; |
662 | ptd->dw4 = usof; | |
db11e47d SS |
663 | } |
664 | ||
71a9f9d2 | 665 | static void create_ptd_int(struct isp1760_qh *qh, |
a041d8e4 | 666 | struct isp1760_qtd *qtd, struct ptd *ptd) |
db11e47d | 667 | { |
71a9f9d2 | 668 | create_ptd_atl(qh, qtd, ptd); |
6bda21bc | 669 | transform_add_int(qh, qtd, ptd); |
db11e47d SS |
670 | } |
671 | ||
6bda21bc | 672 | static void isp1760_urb_done(struct usb_hcd *hcd, struct urb *urb) |
db11e47d SS |
673 | __releases(priv->lock) |
674 | __acquires(priv->lock) | |
675 | { | |
6bda21bc AB |
676 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
677 | ||
db11e47d | 678 | if (!urb->unlinked) { |
6bda21bc AB |
679 | if (urb->status == -EINPROGRESS) |
680 | urb->status = 0; | |
db11e47d SS |
681 | } |
682 | ||
db8516f6 CM |
683 | if (usb_pipein(urb->pipe) && usb_pipetype(urb->pipe) != PIPE_CONTROL) { |
684 | void *ptr; | |
685 | for (ptr = urb->transfer_buffer; | |
686 | ptr < urb->transfer_buffer + urb->transfer_buffer_length; | |
687 | ptr += PAGE_SIZE) | |
688 | flush_dcache_page(virt_to_page(ptr)); | |
689 | } | |
690 | ||
db11e47d | 691 | /* complete() can reenter this HCD */ |
6bda21bc | 692 | usb_hcd_unlink_urb_from_ep(hcd, urb); |
db11e47d | 693 | spin_unlock(&priv->lock); |
6bda21bc | 694 | usb_hcd_giveback_urb(hcd, urb, urb->status); |
db11e47d SS |
695 | spin_lock(&priv->lock); |
696 | } | |
697 | ||
34537731 AB |
698 | static struct isp1760_qtd *qtd_alloc(gfp_t flags, struct urb *urb, |
699 | u8 packet_type) | |
db11e47d | 700 | { |
34537731 AB |
701 | struct isp1760_qtd *qtd; |
702 | ||
703 | qtd = kmem_cache_zalloc(qtd_cachep, flags); | |
704 | if (!qtd) | |
705 | return NULL; | |
706 | ||
707 | INIT_LIST_HEAD(&qtd->qtd_list); | |
708 | qtd->urb = urb; | |
709 | qtd->packet_type = packet_type; | |
71a9f9d2 AB |
710 | qtd->status = QTD_ENQUEUED; |
711 | qtd->actual_length = 0; | |
34537731 AB |
712 | |
713 | return qtd; | |
714 | } | |
715 | ||
716 | static void qtd_free(struct isp1760_qtd *qtd) | |
717 | { | |
718 | WARN_ON(qtd->payload_addr); | |
db11e47d SS |
719 | kmem_cache_free(qtd_cachep, qtd); |
720 | } | |
721 | ||
71a9f9d2 AB |
722 | static void start_bus_transfer(struct usb_hcd *hcd, u32 ptd_offset, int slot, |
723 | struct slotinfo *slots, struct isp1760_qtd *qtd, | |
724 | struct isp1760_qh *qh, struct ptd *ptd) | |
db11e47d | 725 | { |
71a9f9d2 | 726 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
d05b6ec0 AB |
727 | int skip_map; |
728 | ||
71a9f9d2 AB |
729 | WARN_ON((slot < 0) || (slot > 31)); |
730 | WARN_ON(qtd->length && !qtd->payload_addr); | |
731 | WARN_ON(slots[slot].qtd); | |
732 | WARN_ON(slots[slot].qh); | |
733 | WARN_ON(qtd->status != QTD_PAYLOAD_ALLOC); | |
734 | ||
735 | slots[slot].qtd = qtd; | |
736 | slots[slot].qh = qh; | |
737 | qh->slot = slot; | |
738 | qtd->status = QTD_XFER_STARTED; /* Set this before writing ptd, since | |
739 | interrupt routine may preempt and expects this value. */ | |
6d50c60e | 740 | slots[slot].timestamp = jiffies; |
71a9f9d2 | 741 | ptd_write(hcd->regs, ptd_offset, slot, ptd); |
d05b6ec0 AB |
742 | |
743 | /* Make sure done map has not triggered from some unlinked transfer */ | |
744 | if (ptd_offset == ATL_PTD_OFFSET) { | |
745 | priv->atl_done_map |= reg_read32(hcd->regs, | |
746 | HC_ATL_PTD_DONEMAP_REG); | |
747 | priv->atl_done_map &= ~(1 << qh->slot); | |
748 | ||
749 | skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG); | |
750 | skip_map &= ~(1 << qh->slot); | |
751 | reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, skip_map); | |
752 | } else { | |
753 | priv->int_done_map |= reg_read32(hcd->regs, | |
754 | HC_INT_PTD_DONEMAP_REG); | |
755 | priv->int_done_map &= ~(1 << qh->slot); | |
756 | ||
757 | skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG); | |
758 | skip_map &= ~(1 << qh->slot); | |
759 | reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, skip_map); | |
760 | } | |
db11e47d SS |
761 | } |
762 | ||
71a9f9d2 | 763 | static int is_short_bulk(struct isp1760_qtd *qtd) |
db11e47d | 764 | { |
71a9f9d2 AB |
765 | return (usb_pipebulk(qtd->urb->pipe) && |
766 | (qtd->actual_length < qtd->length)); | |
db11e47d SS |
767 | } |
768 | ||
71a9f9d2 AB |
769 | static void collect_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh, |
770 | struct list_head *urb_list) | |
db11e47d | 771 | { |
71a9f9d2 AB |
772 | int last_qtd; |
773 | struct isp1760_qtd *qtd, *qtd_next; | |
774 | struct urb_listitem *urb_listitem; | |
db11e47d | 775 | |
71a9f9d2 AB |
776 | list_for_each_entry_safe(qtd, qtd_next, &qh->qtd_list, qtd_list) { |
777 | if (qtd->status < QTD_XFER_COMPLETE) | |
778 | break; | |
db11e47d | 779 | |
38679b72 | 780 | last_qtd = last_qtd_of_urb(qtd, qh); |
71a9f9d2 AB |
781 | |
782 | if ((!last_qtd) && (qtd->status == QTD_RETIRE)) | |
783 | qtd_next->status = QTD_RETIRE; | |
784 | ||
785 | if (qtd->status == QTD_XFER_COMPLETE) { | |
786 | if (qtd->actual_length) { | |
787 | switch (qtd->packet_type) { | |
788 | case IN_PID: | |
789 | mem_reads8(hcd->regs, qtd->payload_addr, | |
790 | qtd->data_buffer, | |
791 | qtd->actual_length); | |
792 | /* Fall through (?) */ | |
793 | case OUT_PID: | |
794 | qtd->urb->actual_length += | |
795 | qtd->actual_length; | |
796 | /* Fall through ... */ | |
797 | case SETUP_PID: | |
798 | break; | |
799 | } | |
800 | } | |
db11e47d | 801 | |
71a9f9d2 AB |
802 | if (is_short_bulk(qtd)) { |
803 | if (qtd->urb->transfer_flags & URB_SHORT_NOT_OK) | |
804 | qtd->urb->status = -EREMOTEIO; | |
805 | if (!last_qtd) | |
806 | qtd_next->status = QTD_RETIRE; | |
807 | } | |
808 | } | |
db11e47d | 809 | |
71a9f9d2 AB |
810 | if (qtd->payload_addr) |
811 | free_mem(hcd, qtd); | |
db11e47d | 812 | |
71a9f9d2 AB |
813 | if (last_qtd) { |
814 | if ((qtd->status == QTD_RETIRE) && | |
815 | (qtd->urb->status == -EINPROGRESS)) | |
816 | qtd->urb->status = -EPIPE; | |
817 | /* Defer calling of urb_done() since it releases lock */ | |
818 | urb_listitem = kmem_cache_zalloc(urb_listitem_cachep, | |
819 | GFP_ATOMIC); | |
820 | if (unlikely(!urb_listitem)) | |
38679b72 | 821 | break; /* Try again on next call */ |
71a9f9d2 AB |
822 | urb_listitem->urb = qtd->urb; |
823 | list_add_tail(&urb_listitem->urb_list, urb_list); | |
824 | } | |
847ed3e8 | 825 | |
71a9f9d2 AB |
826 | list_del(&qtd->qtd_list); |
827 | qtd_free(qtd); | |
828 | } | |
829 | } | |
3f02a957 | 830 | |
71a9f9d2 AB |
831 | #define ENQUEUE_DEPTH 2 |
832 | static void enqueue_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh) | |
833 | { | |
834 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | |
835 | int ptd_offset; | |
836 | struct slotinfo *slots; | |
837 | int curr_slot, free_slot; | |
838 | int n; | |
839 | struct ptd ptd; | |
840 | struct isp1760_qtd *qtd; | |
db11e47d | 841 | |
71a9f9d2 AB |
842 | if (unlikely(list_empty(&qh->qtd_list))) { |
843 | WARN_ON(1); | |
844 | return; | |
845 | } | |
db11e47d | 846 | |
71a9f9d2 AB |
847 | if (usb_pipeint(list_entry(qh->qtd_list.next, struct isp1760_qtd, |
848 | qtd_list)->urb->pipe)) { | |
849 | ptd_offset = INT_PTD_OFFSET; | |
850 | slots = priv->int_slots; | |
851 | } else { | |
852 | ptd_offset = ATL_PTD_OFFSET; | |
853 | slots = priv->atl_slots; | |
854 | } | |
db11e47d | 855 | |
71a9f9d2 AB |
856 | free_slot = -1; |
857 | for (curr_slot = 0; curr_slot < 32; curr_slot++) { | |
858 | if ((free_slot == -1) && (slots[curr_slot].qtd == NULL)) | |
859 | free_slot = curr_slot; | |
860 | if (slots[curr_slot].qh == qh) | |
861 | break; | |
862 | } | |
db11e47d | 863 | |
71a9f9d2 AB |
864 | n = 0; |
865 | list_for_each_entry(qtd, &qh->qtd_list, qtd_list) { | |
866 | if (qtd->status == QTD_ENQUEUED) { | |
867 | WARN_ON(qtd->payload_addr); | |
868 | alloc_mem(hcd, qtd); | |
869 | if ((qtd->length) && (!qtd->payload_addr)) | |
870 | break; | |
db11e47d | 871 | |
71a9f9d2 AB |
872 | if ((qtd->length) && |
873 | ((qtd->packet_type == SETUP_PID) || | |
874 | (qtd->packet_type == OUT_PID))) { | |
875 | mem_writes8(hcd->regs, qtd->payload_addr, | |
876 | qtd->data_buffer, qtd->length); | |
877 | } | |
db11e47d | 878 | |
71a9f9d2 | 879 | qtd->status = QTD_PAYLOAD_ALLOC; |
db11e47d SS |
880 | } |
881 | ||
71a9f9d2 AB |
882 | if (qtd->status == QTD_PAYLOAD_ALLOC) { |
883 | /* | |
884 | if ((curr_slot > 31) && (free_slot == -1)) | |
885 | dev_dbg(hcd->self.controller, "%s: No slot " | |
886 | "available for transfer\n", __func__); | |
887 | */ | |
888 | /* Start xfer for this endpoint if not already done */ | |
889 | if ((curr_slot > 31) && (free_slot > -1)) { | |
890 | if (usb_pipeint(qtd->urb->pipe)) | |
891 | create_ptd_int(qh, qtd, &ptd); | |
892 | else | |
893 | create_ptd_atl(qh, qtd, &ptd); | |
894 | ||
895 | start_bus_transfer(hcd, ptd_offset, free_slot, | |
896 | slots, qtd, qh, &ptd); | |
897 | curr_slot = free_slot; | |
898 | } | |
db11e47d | 899 | |
71a9f9d2 AB |
900 | n++; |
901 | if (n >= ENQUEUE_DEPTH) | |
902 | break; | |
903 | } | |
904 | } | |
905 | } | |
db11e47d | 906 | |
71a9f9d2 AB |
907 | void schedule_ptds(struct usb_hcd *hcd) |
908 | { | |
909 | struct isp1760_hcd *priv; | |
910 | struct isp1760_qh *qh, *qh_next; | |
911 | struct list_head *ep_queue; | |
912 | struct usb_host_endpoint *ep; | |
913 | LIST_HEAD(urb_list); | |
914 | struct urb_listitem *urb_listitem, *urb_listitem_next; | |
915 | ||
916 | if (!hcd) { | |
917 | WARN_ON(1); | |
918 | return; | |
919 | } | |
db11e47d | 920 | |
71a9f9d2 | 921 | priv = hcd_to_priv(hcd); |
db11e47d | 922 | |
71a9f9d2 AB |
923 | /* |
924 | * check finished/retired xfers, transfer payloads, call urb_done() | |
925 | */ | |
926 | ep_queue = &priv->interruptqhs; | |
927 | while (ep_queue) { | |
928 | list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list) { | |
929 | ep = list_entry(qh->qtd_list.next, struct isp1760_qtd, | |
930 | qtd_list)->urb->ep; | |
931 | collect_qtds(hcd, qh, &urb_list); | |
932 | if (list_empty(&qh->qtd_list)) { | |
933 | list_del(&qh->qh_list); | |
934 | if (ep->hcpriv == NULL) { | |
935 | /* Endpoint has been disabled, so we | |
936 | can free the associated queue head. */ | |
937 | qh_free(qh); | |
938 | } | |
db11e47d SS |
939 | } |
940 | } | |
941 | ||
71a9f9d2 AB |
942 | if (ep_queue == &priv->interruptqhs) |
943 | ep_queue = &priv->controlqhs; | |
944 | else if (ep_queue == &priv->controlqhs) | |
945 | ep_queue = &priv->bulkqhs; | |
946 | else | |
947 | ep_queue = NULL; | |
948 | } | |
db11e47d | 949 | |
71a9f9d2 AB |
950 | list_for_each_entry_safe(urb_listitem, urb_listitem_next, &urb_list, |
951 | urb_list) { | |
952 | isp1760_urb_done(hcd, urb_listitem->urb); | |
953 | kmem_cache_free(urb_listitem_cachep, urb_listitem); | |
954 | } | |
db11e47d | 955 | |
71a9f9d2 AB |
956 | /* |
957 | * Schedule packets for transfer. | |
958 | * | |
959 | * According to USB2.0 specification: | |
960 | * | |
961 | * 1st prio: interrupt xfers, up to 80 % of bandwidth | |
962 | * 2nd prio: control xfers | |
963 | * 3rd prio: bulk xfers | |
964 | * | |
965 | * ... but let's use a simpler scheme here (mostly because ISP1761 doc | |
966 | * is very unclear on how to prioritize traffic): | |
967 | * | |
968 | * 1) Enqueue any queued control transfers, as long as payload chip mem | |
969 | * and PTD ATL slots are available. | |
970 | * 2) Enqueue any queued INT transfers, as long as payload chip mem | |
971 | * and PTD INT slots are available. | |
972 | * 3) Enqueue any queued bulk transfers, as long as payload chip mem | |
973 | * and PTD ATL slots are available. | |
974 | * | |
975 | * Use double buffering (ENQUEUE_DEPTH==2) as a compromise between | |
976 | * conservation of chip mem and performance. | |
977 | * | |
978 | * I'm sure this scheme could be improved upon! | |
979 | */ | |
980 | ep_queue = &priv->controlqhs; | |
981 | while (ep_queue) { | |
982 | list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list) | |
983 | enqueue_qtds(hcd, qh); | |
984 | ||
985 | if (ep_queue == &priv->controlqhs) | |
986 | ep_queue = &priv->interruptqhs; | |
987 | else if (ep_queue == &priv->interruptqhs) | |
988 | ep_queue = &priv->bulkqhs; | |
989 | else | |
990 | ep_queue = NULL; | |
991 | } | |
992 | } | |
db11e47d | 993 | |
71a9f9d2 AB |
994 | #define PTD_STATE_QTD_DONE 1 |
995 | #define PTD_STATE_QTD_RELOAD 2 | |
996 | #define PTD_STATE_URB_RETIRE 3 | |
db11e47d | 997 | |
71a9f9d2 AB |
998 | static int check_int_transfer(struct usb_hcd *hcd, struct ptd *ptd, |
999 | struct urb *urb) | |
1000 | { | |
1001 | __dw dw4; | |
1002 | int i; | |
db11e47d | 1003 | |
71a9f9d2 AB |
1004 | dw4 = ptd->dw4; |
1005 | dw4 >>= 8; | |
db11e47d | 1006 | |
71a9f9d2 AB |
1007 | /* FIXME: ISP1761 datasheet does not say what to do with these. Do we |
1008 | need to handle these errors? Is it done in hardware? */ | |
db11e47d | 1009 | |
71a9f9d2 | 1010 | if (ptd->dw3 & DW3_HALT_BIT) { |
db11e47d | 1011 | |
71a9f9d2 | 1012 | urb->status = -EPROTO; /* Default unknown error */ |
db11e47d | 1013 | |
71a9f9d2 AB |
1014 | for (i = 0; i < 8; i++) { |
1015 | switch (dw4 & 0x7) { | |
1016 | case INT_UNDERRUN: | |
1017 | dev_dbg(hcd->self.controller, "%s: underrun " | |
1018 | "during uFrame %d\n", | |
1019 | __func__, i); | |
1020 | urb->status = -ECOMM; /* Could not write data */ | |
1021 | break; | |
1022 | case INT_EXACT: | |
1023 | dev_dbg(hcd->self.controller, "%s: transaction " | |
1024 | "error during uFrame %d\n", | |
1025 | __func__, i); | |
1026 | urb->status = -EPROTO; /* timeout, bad CRC, PID | |
1027 | error etc. */ | |
1028 | break; | |
1029 | case INT_BABBLE: | |
1030 | dev_dbg(hcd->self.controller, "%s: babble " | |
1031 | "error during uFrame %d\n", | |
1032 | __func__, i); | |
1033 | urb->status = -EOVERFLOW; | |
1034 | break; | |
1035 | } | |
1036 | dw4 >>= 3; | |
1037 | } | |
db11e47d | 1038 | |
71a9f9d2 AB |
1039 | return PTD_STATE_URB_RETIRE; |
1040 | } | |
db11e47d | 1041 | |
71a9f9d2 AB |
1042 | return PTD_STATE_QTD_DONE; |
1043 | } | |
db11e47d | 1044 | |
71a9f9d2 AB |
1045 | static int check_atl_transfer(struct usb_hcd *hcd, struct ptd *ptd, |
1046 | struct urb *urb) | |
1047 | { | |
1048 | WARN_ON(!ptd); | |
1049 | if (ptd->dw3 & DW3_HALT_BIT) { | |
1050 | if (ptd->dw3 & DW3_BABBLE_BIT) | |
1051 | urb->status = -EOVERFLOW; | |
1052 | else if (FROM_DW3_CERR(ptd->dw3)) | |
1053 | urb->status = -EPIPE; /* Stall */ | |
1054 | else if (ptd->dw3 & DW3_ERROR_BIT) | |
1055 | urb->status = -EPROTO; /* XactErr */ | |
1056 | else | |
1057 | urb->status = -EPROTO; /* Unknown */ | |
1058 | /* | |
1059 | dev_dbg(hcd->self.controller, "%s: ptd error:\n" | |
1060 | " dw0: %08x dw1: %08x dw2: %08x dw3: %08x\n" | |
1061 | " dw4: %08x dw5: %08x dw6: %08x dw7: %08x\n", | |
1062 | __func__, | |
1063 | ptd->dw0, ptd->dw1, ptd->dw2, ptd->dw3, | |
1064 | ptd->dw4, ptd->dw5, ptd->dw6, ptd->dw7); | |
1065 | */ | |
1066 | return PTD_STATE_URB_RETIRE; | |
1067 | } | |
db11e47d | 1068 | |
71a9f9d2 AB |
1069 | if ((ptd->dw3 & DW3_ERROR_BIT) && (ptd->dw3 & DW3_ACTIVE_BIT)) { |
1070 | /* Transfer Error, *but* active and no HALT -> reload */ | |
1071 | dev_dbg(hcd->self.controller, "PID error; reloading ptd\n"); | |
1072 | return PTD_STATE_QTD_RELOAD; | |
1073 | } | |
db11e47d | 1074 | |
71a9f9d2 AB |
1075 | if (!FROM_DW3_NAKCOUNT(ptd->dw3) && (ptd->dw3 & DW3_ACTIVE_BIT)) { |
1076 | /* | |
1077 | * NAKs are handled in HW by the chip. Usually if the | |
1078 | * device is not able to send data fast enough. | |
1079 | * This happens mostly on slower hardware. | |
1080 | */ | |
1081 | return PTD_STATE_QTD_RELOAD; | |
db11e47d | 1082 | } |
71a9f9d2 AB |
1083 | |
1084 | return PTD_STATE_QTD_DONE; | |
db11e47d SS |
1085 | } |
1086 | ||
6d50c60e | 1087 | static void handle_done_ptds(struct usb_hcd *hcd) |
db11e47d | 1088 | { |
bedc0c31 | 1089 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
db11e47d | 1090 | struct ptd ptd; |
db11e47d | 1091 | struct isp1760_qh *qh; |
71a9f9d2 AB |
1092 | int slot; |
1093 | int state; | |
1094 | struct slotinfo *slots; | |
1095 | u32 ptd_offset; | |
1096 | struct isp1760_qtd *qtd; | |
1097 | int modified; | |
6d50c60e | 1098 | int skip_map; |
71a9f9d2 | 1099 | |
6d50c60e AB |
1100 | skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG); |
1101 | priv->int_done_map &= ~skip_map; | |
1102 | skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG); | |
1103 | priv->atl_done_map &= ~skip_map; | |
71a9f9d2 | 1104 | |
6d50c60e | 1105 | modified = priv->int_done_map || priv->atl_done_map; |
d05b6ec0 AB |
1106 | |
1107 | while (priv->int_done_map || priv->atl_done_map) { | |
1108 | if (priv->int_done_map) { | |
71a9f9d2 | 1109 | /* INT ptd */ |
d05b6ec0 AB |
1110 | slot = __ffs(priv->int_done_map); |
1111 | priv->int_done_map &= ~(1 << slot); | |
71a9f9d2 | 1112 | slots = priv->int_slots; |
d05b6ec0 AB |
1113 | /* This should not trigger, and could be removed if |
1114 | noone have any problems with it triggering: */ | |
1115 | if (!slots[slot].qh) { | |
1116 | WARN_ON(1); | |
71a9f9d2 | 1117 | continue; |
d05b6ec0 | 1118 | } |
71a9f9d2 AB |
1119 | ptd_offset = INT_PTD_OFFSET; |
1120 | ptd_read(hcd->regs, INT_PTD_OFFSET, slot, &ptd); | |
1121 | state = check_int_transfer(hcd, &ptd, | |
1122 | slots[slot].qtd->urb); | |
db11e47d | 1123 | } else { |
71a9f9d2 | 1124 | /* ATL ptd */ |
d05b6ec0 AB |
1125 | slot = __ffs(priv->atl_done_map); |
1126 | priv->atl_done_map &= ~(1 << slot); | |
71a9f9d2 | 1127 | slots = priv->atl_slots; |
d05b6ec0 AB |
1128 | /* This should not trigger, and could be removed if |
1129 | noone have any problems with it triggering: */ | |
1130 | if (!slots[slot].qh) { | |
1131 | WARN_ON(1); | |
71a9f9d2 | 1132 | continue; |
d05b6ec0 | 1133 | } |
71a9f9d2 AB |
1134 | ptd_offset = ATL_PTD_OFFSET; |
1135 | ptd_read(hcd->regs, ATL_PTD_OFFSET, slot, &ptd); | |
1136 | state = check_atl_transfer(hcd, &ptd, | |
1137 | slots[slot].qtd->urb); | |
db11e47d SS |
1138 | } |
1139 | ||
71a9f9d2 AB |
1140 | qtd = slots[slot].qtd; |
1141 | slots[slot].qtd = NULL; | |
1142 | qh = slots[slot].qh; | |
1143 | slots[slot].qh = NULL; | |
71a9f9d2 AB |
1144 | qh->slot = -1; |
1145 | ||
1146 | WARN_ON(qtd->status != QTD_XFER_STARTED); | |
1147 | ||
1148 | switch (state) { | |
1149 | case PTD_STATE_QTD_DONE: | |
1150 | if ((usb_pipeint(qtd->urb->pipe)) && | |
1151 | (qtd->urb->dev->speed != USB_SPEED_HIGH)) | |
1152 | qtd->actual_length = | |
1153 | FROM_DW3_SCS_NRBYTESTRANSFERRED(ptd.dw3); | |
1154 | else | |
1155 | qtd->actual_length = | |
1156 | FROM_DW3_NRBYTESTRANSFERRED(ptd.dw3); | |
db11e47d | 1157 | |
71a9f9d2 AB |
1158 | qtd->status = QTD_XFER_COMPLETE; |
1159 | if (list_is_last(&qtd->qtd_list, &qh->qtd_list) || | |
1160 | is_short_bulk(qtd)) | |
1161 | qtd = NULL; | |
1162 | else | |
1163 | qtd = list_entry(qtd->qtd_list.next, | |
1164 | typeof(*qtd), qtd_list); | |
db11e47d | 1165 | |
71a9f9d2 AB |
1166 | qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3); |
1167 | qh->ping = FROM_DW3_PING(ptd.dw3); | |
1168 | break; | |
db11e47d | 1169 | |
71a9f9d2 AB |
1170 | case PTD_STATE_QTD_RELOAD: /* QTD_RETRY, for atls only */ |
1171 | qtd->status = QTD_PAYLOAD_ALLOC; | |
1172 | ptd.dw0 |= DW0_VALID_BIT; | |
1173 | /* RL counter = ERR counter */ | |
1174 | ptd.dw3 &= ~TO_DW3_NAKCOUNT(0xf); | |
1175 | ptd.dw3 |= TO_DW3_NAKCOUNT(FROM_DW2_RL(ptd.dw2)); | |
1176 | ptd.dw3 &= ~TO_DW3_CERR(3); | |
1177 | ptd.dw3 |= TO_DW3_CERR(ERR_COUNTER); | |
1178 | qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3); | |
1179 | qh->ping = FROM_DW3_PING(ptd.dw3); | |
1180 | break; | |
db11e47d | 1181 | |
71a9f9d2 AB |
1182 | case PTD_STATE_URB_RETIRE: |
1183 | qtd->status = QTD_RETIRE; | |
1184 | qtd = NULL; | |
1185 | qh->toggle = 0; | |
1186 | qh->ping = 0; | |
1187 | break; | |
db11e47d | 1188 | |
71a9f9d2 AB |
1189 | default: |
1190 | WARN_ON(1); | |
1191 | continue; | |
1192 | } | |
db11e47d | 1193 | |
71a9f9d2 AB |
1194 | if (qtd && (qtd->status == QTD_PAYLOAD_ALLOC)) { |
1195 | if (slots == priv->int_slots) { | |
1196 | if (state == PTD_STATE_QTD_RELOAD) | |
1197 | dev_err(hcd->self.controller, | |
1198 | "%s: PTD_STATE_QTD_RELOAD on " | |
1199 | "interrupt packet\n", __func__); | |
1200 | if (state != PTD_STATE_QTD_RELOAD) | |
1201 | create_ptd_int(qh, qtd, &ptd); | |
1202 | } else { | |
1203 | if (state != PTD_STATE_QTD_RELOAD) | |
1204 | create_ptd_atl(qh, qtd, &ptd); | |
1205 | } | |
db11e47d | 1206 | |
71a9f9d2 AB |
1207 | start_bus_transfer(hcd, ptd_offset, slot, slots, qtd, |
1208 | qh, &ptd); | |
1209 | } | |
1210 | } | |
db11e47d | 1211 | |
71a9f9d2 AB |
1212 | if (modified) |
1213 | schedule_ptds(hcd); | |
6d50c60e | 1214 | } |
db11e47d | 1215 | |
6d50c60e AB |
1216 | static irqreturn_t isp1760_irq(struct usb_hcd *hcd) |
1217 | { | |
1218 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | |
1219 | u32 imask; | |
1220 | irqreturn_t irqret = IRQ_NONE; | |
db11e47d | 1221 | |
6d50c60e AB |
1222 | spin_lock(&priv->lock); |
1223 | ||
1224 | if (!(hcd->state & HC_STATE_RUNNING)) | |
1225 | goto leave; | |
1226 | ||
1227 | imask = reg_read32(hcd->regs, HC_INTERRUPT_REG); | |
1228 | if (unlikely(!imask)) | |
1229 | goto leave; | |
1230 | reg_write32(hcd->regs, HC_INTERRUPT_REG, imask); /* Clear */ | |
1231 | ||
1232 | priv->int_done_map |= reg_read32(hcd->regs, HC_INT_PTD_DONEMAP_REG); | |
1233 | priv->atl_done_map |= reg_read32(hcd->regs, HC_ATL_PTD_DONEMAP_REG); | |
1234 | ||
1235 | handle_done_ptds(hcd); | |
db11e47d | 1236 | |
71a9f9d2 AB |
1237 | irqret = IRQ_HANDLED; |
1238 | leave: | |
1239 | spin_unlock(&priv->lock); | |
db11e47d | 1240 | |
71a9f9d2 | 1241 | return irqret; |
db11e47d SS |
1242 | } |
1243 | ||
6d50c60e AB |
1244 | /* |
1245 | * Workaround for problem described in chip errata 2: | |
1246 | * | |
1247 | * Sometimes interrupts are not generated when ATL (not INT?) completion occurs. | |
1248 | * One solution suggested in the errata is to use SOF interrupts _instead_of_ | |
1249 | * ATL done interrupts (the "instead of" might be important since it seems | |
1250 | * enabling ATL interrupts also causes the chip to sometimes - rarely - "forget" | |
1251 | * to set the PTD's done bit in addition to not generating an interrupt!). | |
1252 | * | |
1253 | * So if we use SOF + ATL interrupts, we sometimes get stale PTDs since their | |
1254 | * done bit is not being set. This is bad - it blocks the endpoint until reboot. | |
1255 | * | |
1256 | * If we use SOF interrupts only, we get latency between ptd completion and the | |
1257 | * actual handling. This is very noticeable in testusb runs which takes several | |
1258 | * minutes longer without ATL interrupts. | |
1259 | * | |
1260 | * A better solution is to run the code below every SLOT_CHECK_PERIOD ms. If it | |
1261 | * finds active ATL slots which are older than SLOT_TIMEOUT ms, it checks the | |
1262 | * slot's ACTIVE and VALID bits. If these are not set, the ptd is considered | |
1263 | * completed and its done map bit is set. | |
1264 | * | |
1265 | * The values of SLOT_TIMEOUT and SLOT_CHECK_PERIOD have been arbitrarily chosen | |
1266 | * not to cause too much lag when this HW bug occurs, while still hopefully | |
1267 | * ensuring that the check does not falsely trigger. | |
1268 | */ | |
1269 | #define SLOT_TIMEOUT 180 | |
1270 | #define SLOT_CHECK_PERIOD 200 | |
1271 | static struct timer_list errata2_timer; | |
1272 | ||
1273 | void errata2_function(unsigned long data) | |
1274 | { | |
1275 | struct usb_hcd *hcd = (struct usb_hcd *) data; | |
1276 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | |
1277 | int slot; | |
1278 | struct ptd ptd; | |
1279 | unsigned long spinflags; | |
1280 | ||
1281 | spin_lock_irqsave(&priv->lock, spinflags); | |
1282 | ||
1283 | for (slot = 0; slot < 32; slot++) | |
1284 | if ((priv->atl_slots[slot].qh || priv->atl_slots[slot].qtd) && | |
1285 | time_after(jiffies + SLOT_TIMEOUT * HZ / 1000, | |
1286 | priv->atl_slots[slot].timestamp)) { | |
1287 | ptd_read(hcd->regs, ATL_PTD_OFFSET, slot, &ptd); | |
1288 | if (!FROM_DW0_VALID(ptd.dw0) && | |
1289 | !FROM_DW3_ACTIVE(ptd.dw3)) | |
1290 | priv->atl_done_map |= 1 << slot; | |
1291 | } | |
1292 | ||
1293 | handle_done_ptds(hcd); | |
1294 | ||
1295 | spin_unlock_irqrestore(&priv->lock, spinflags); | |
1296 | ||
1297 | errata2_timer.expires = jiffies + SLOT_CHECK_PERIOD * HZ / 1000; | |
1298 | add_timer(&errata2_timer); | |
1299 | } | |
1300 | ||
0ba7905e AB |
1301 | static int isp1760_run(struct usb_hcd *hcd) |
1302 | { | |
1303 | int retval; | |
1304 | u32 temp; | |
1305 | u32 command; | |
1306 | u32 chipid; | |
1307 | ||
1308 | hcd->uses_new_polling = 1; | |
1309 | ||
1310 | hcd->state = HC_STATE_RUNNING; | |
1311 | ||
1312 | /* Set PTD interrupt AND & OR maps */ | |
1313 | reg_write32(hcd->regs, HC_ATL_IRQ_MASK_AND_REG, 0); | |
1314 | reg_write32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG, 0xffffffff); | |
1315 | reg_write32(hcd->regs, HC_INT_IRQ_MASK_AND_REG, 0); | |
1316 | reg_write32(hcd->regs, HC_INT_IRQ_MASK_OR_REG, 0xffffffff); | |
1317 | reg_write32(hcd->regs, HC_ISO_IRQ_MASK_AND_REG, 0); | |
1318 | reg_write32(hcd->regs, HC_ISO_IRQ_MASK_OR_REG, 0xffffffff); | |
1319 | /* step 23 passed */ | |
1320 | ||
1321 | temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL); | |
1322 | reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp | HW_GLOBAL_INTR_EN); | |
1323 | ||
1324 | command = reg_read32(hcd->regs, HC_USBCMD); | |
1325 | command &= ~(CMD_LRESET|CMD_RESET); | |
1326 | command |= CMD_RUN; | |
1327 | reg_write32(hcd->regs, HC_USBCMD, command); | |
1328 | ||
1329 | retval = handshake(hcd, HC_USBCMD, CMD_RUN, CMD_RUN, 250 * 1000); | |
1330 | if (retval) | |
1331 | return retval; | |
1332 | ||
1333 | /* | |
1334 | * XXX | |
1335 | * Spec says to write FLAG_CF as last config action, priv code grabs | |
1336 | * the semaphore while doing so. | |
1337 | */ | |
1338 | down_write(&ehci_cf_port_reset_rwsem); | |
1339 | reg_write32(hcd->regs, HC_CONFIGFLAG, FLAG_CF); | |
1340 | ||
1341 | retval = handshake(hcd, HC_CONFIGFLAG, FLAG_CF, FLAG_CF, 250 * 1000); | |
1342 | up_write(&ehci_cf_port_reset_rwsem); | |
1343 | if (retval) | |
1344 | return retval; | |
1345 | ||
6d50c60e AB |
1346 | init_timer(&errata2_timer); |
1347 | errata2_timer.function = errata2_function; | |
1348 | errata2_timer.data = (unsigned long) hcd; | |
1349 | errata2_timer.expires = jiffies + SLOT_CHECK_PERIOD * HZ / 1000; | |
1350 | add_timer(&errata2_timer); | |
1351 | ||
0ba7905e AB |
1352 | chipid = reg_read32(hcd->regs, HC_CHIP_ID_REG); |
1353 | dev_info(hcd->self.controller, "USB ISP %04x HW rev. %d started\n", | |
1354 | chipid & 0xffff, chipid >> 16); | |
1355 | ||
1356 | /* PTD Register Init Part 2, Step 28 */ | |
1357 | ||
1358 | /* Setup registers controlling PTD checking */ | |
1359 | reg_write32(hcd->regs, HC_ATL_PTD_LASTPTD_REG, 0x80000000); | |
1360 | reg_write32(hcd->regs, HC_INT_PTD_LASTPTD_REG, 0x80000000); | |
1361 | reg_write32(hcd->regs, HC_ISO_PTD_LASTPTD_REG, 0x00000001); | |
1362 | reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, 0xffffffff); | |
1363 | reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, 0xffffffff); | |
1364 | reg_write32(hcd->regs, HC_ISO_PTD_SKIPMAP_REG, 0xffffffff); | |
1365 | reg_write32(hcd->regs, HC_BUFFER_STATUS_REG, | |
1366 | ATL_BUF_FILL | INT_BUF_FILL); | |
1367 | ||
1368 | /* GRR this is run-once init(), being done every time the HC starts. | |
1369 | * So long as they're part of class devices, we can't do it init() | |
1370 | * since the class device isn't created that early. | |
1371 | */ | |
1372 | return 0; | |
1373 | } | |
1374 | ||
34537731 | 1375 | static int qtd_fill(struct isp1760_qtd *qtd, void *databuffer, size_t len) |
db11e47d | 1376 | { |
34537731 | 1377 | qtd->data_buffer = databuffer; |
db11e47d | 1378 | |
34537731 AB |
1379 | if (len > MAX_PAYLOAD_SIZE) |
1380 | len = MAX_PAYLOAD_SIZE; | |
1381 | qtd->length = len; | |
db11e47d | 1382 | |
34537731 | 1383 | return qtd->length; |
db11e47d SS |
1384 | } |
1385 | ||
34537731 | 1386 | static void qtd_list_free(struct list_head *qtd_list) |
db11e47d | 1387 | { |
34537731 | 1388 | struct isp1760_qtd *qtd, *qtd_next; |
db11e47d | 1389 | |
34537731 | 1390 | list_for_each_entry_safe(qtd, qtd_next, qtd_list, qtd_list) { |
db11e47d | 1391 | list_del(&qtd->qtd_list); |
34537731 | 1392 | qtd_free(qtd); |
db11e47d SS |
1393 | } |
1394 | } | |
1395 | ||
db11e47d | 1396 | /* |
34537731 AB |
1397 | * Packetize urb->transfer_buffer into list of packets of size wMaxPacketSize. |
1398 | * Also calculate the PID type (SETUP/IN/OUT) for each packet. | |
db11e47d | 1399 | */ |
6bda21bc | 1400 | #define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff) |
34537731 | 1401 | static void packetize_urb(struct usb_hcd *hcd, |
db11e47d SS |
1402 | struct urb *urb, struct list_head *head, gfp_t flags) |
1403 | { | |
fd436aee | 1404 | struct isp1760_qtd *qtd; |
db11e47d | 1405 | void *buf; |
34537731 AB |
1406 | int len, maxpacketsize; |
1407 | u8 packet_type; | |
db11e47d SS |
1408 | |
1409 | /* | |
1410 | * URBs map to sequences of QTDs: one logical transaction | |
1411 | */ | |
db11e47d | 1412 | |
34537731 AB |
1413 | if (!urb->transfer_buffer && urb->transfer_buffer_length) { |
1414 | /* XXX This looks like usb storage / SCSI bug */ | |
1415 | dev_err(hcd->self.controller, | |
1416 | "buf is null, dma is %08lx len is %d\n", | |
1417 | (long unsigned)urb->transfer_dma, | |
1418 | urb->transfer_buffer_length); | |
1419 | WARN_ON(1); | |
1420 | } | |
db11e47d | 1421 | |
34537731 AB |
1422 | if (usb_pipein(urb->pipe)) |
1423 | packet_type = IN_PID; | |
1424 | else | |
1425 | packet_type = OUT_PID; | |
db11e47d | 1426 | |
db11e47d | 1427 | if (usb_pipecontrol(urb->pipe)) { |
34537731 | 1428 | qtd = qtd_alloc(flags, urb, SETUP_PID); |
db11e47d SS |
1429 | if (!qtd) |
1430 | goto cleanup; | |
34537731 | 1431 | qtd_fill(qtd, urb->setup_packet, sizeof(struct usb_ctrlrequest)); |
db11e47d SS |
1432 | list_add_tail(&qtd->qtd_list, head); |
1433 | ||
1434 | /* for zero length DATA stages, STATUS is always IN */ | |
34537731 AB |
1435 | if (urb->transfer_buffer_length == 0) |
1436 | packet_type = IN_PID; | |
db11e47d SS |
1437 | } |
1438 | ||
34537731 AB |
1439 | maxpacketsize = max_packet(usb_maxpacket(urb->dev, urb->pipe, |
1440 | usb_pipeout(urb->pipe))); | |
db11e47d SS |
1441 | |
1442 | /* | |
1443 | * buffer gets wrapped in one or more qtds; | |
1444 | * last one may be "short" (including zero len) | |
1445 | * and may serve as a control status ack | |
1446 | */ | |
34537731 AB |
1447 | buf = urb->transfer_buffer; |
1448 | len = urb->transfer_buffer_length; | |
1449 | ||
db11e47d SS |
1450 | for (;;) { |
1451 | int this_qtd_len; | |
1452 | ||
34537731 AB |
1453 | qtd = qtd_alloc(flags, urb, packet_type); |
1454 | if (!qtd) | |
1455 | goto cleanup; | |
1456 | this_qtd_len = qtd_fill(qtd, buf, len); | |
1457 | list_add_tail(&qtd->qtd_list, head); | |
db11e47d | 1458 | |
db11e47d SS |
1459 | len -= this_qtd_len; |
1460 | buf += this_qtd_len; | |
1461 | ||
db11e47d SS |
1462 | if (len <= 0) |
1463 | break; | |
db11e47d SS |
1464 | } |
1465 | ||
1466 | /* | |
1467 | * control requests may need a terminating data "status" ack; | |
1468 | * bulk ones may need a terminating short packet (zero length). | |
1469 | */ | |
1470 | if (urb->transfer_buffer_length != 0) { | |
1471 | int one_more = 0; | |
1472 | ||
1473 | if (usb_pipecontrol(urb->pipe)) { | |
1474 | one_more = 1; | |
34537731 AB |
1475 | if (packet_type == IN_PID) |
1476 | packet_type = OUT_PID; | |
1477 | else | |
1478 | packet_type = IN_PID; | |
db11e47d SS |
1479 | } else if (usb_pipebulk(urb->pipe) |
1480 | && (urb->transfer_flags & URB_ZERO_PACKET) | |
34537731 AB |
1481 | && !(urb->transfer_buffer_length % |
1482 | maxpacketsize)) { | |
db11e47d SS |
1483 | one_more = 1; |
1484 | } | |
1485 | if (one_more) { | |
34537731 | 1486 | qtd = qtd_alloc(flags, urb, packet_type); |
db11e47d SS |
1487 | if (!qtd) |
1488 | goto cleanup; | |
db11e47d SS |
1489 | |
1490 | /* never any data in such packets */ | |
34537731 AB |
1491 | qtd_fill(qtd, NULL, 0); |
1492 | list_add_tail(&qtd->qtd_list, head); | |
db11e47d SS |
1493 | } |
1494 | } | |
1495 | ||
34537731 | 1496 | return; |
db11e47d SS |
1497 | |
1498 | cleanup: | |
34537731 AB |
1499 | qtd_list_free(head); |
1500 | } | |
1501 | ||
db11e47d SS |
1502 | static int isp1760_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, |
1503 | gfp_t mem_flags) | |
1504 | { | |
71a9f9d2 AB |
1505 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
1506 | struct list_head *ep_queue; | |
1507 | struct isp1760_qh *qh, *qhit; | |
1508 | unsigned long spinflags; | |
1509 | LIST_HEAD(new_qtds); | |
1510 | int retval; | |
1511 | int qh_in_queue; | |
db11e47d SS |
1512 | |
1513 | switch (usb_pipetype(urb->pipe)) { | |
1514 | case PIPE_CONTROL: | |
71a9f9d2 AB |
1515 | ep_queue = &priv->controlqhs; |
1516 | break; | |
db11e47d | 1517 | case PIPE_BULK: |
71a9f9d2 | 1518 | ep_queue = &priv->bulkqhs; |
db11e47d | 1519 | break; |
db11e47d | 1520 | case PIPE_INTERRUPT: |
71a9f9d2 AB |
1521 | if (urb->interval < 0) |
1522 | return -EINVAL; | |
1523 | /* FIXME: Check bandwidth */ | |
1524 | ep_queue = &priv->interruptqhs; | |
db11e47d | 1525 | break; |
db11e47d | 1526 | case PIPE_ISOCHRONOUS: |
71a9f9d2 AB |
1527 | dev_err(hcd->self.controller, "%s: isochronous USB packets " |
1528 | "not yet supported\n", | |
1529 | __func__); | |
1530 | return -EPIPE; | |
db11e47d | 1531 | default: |
71a9f9d2 AB |
1532 | dev_err(hcd->self.controller, "%s: unknown pipe type\n", |
1533 | __func__); | |
db11e47d SS |
1534 | return -EPIPE; |
1535 | } | |
1536 | ||
71a9f9d2 AB |
1537 | if (usb_pipein(urb->pipe)) |
1538 | urb->actual_length = 0; | |
db11e47d | 1539 | |
71a9f9d2 AB |
1540 | packetize_urb(hcd, urb, &new_qtds, mem_flags); |
1541 | if (list_empty(&new_qtds)) | |
1542 | return -ENOMEM; | |
db11e47d | 1543 | |
71a9f9d2 AB |
1544 | retval = 0; |
1545 | spin_lock_irqsave(&priv->lock, spinflags); | |
db11e47d | 1546 | |
71a9f9d2 AB |
1547 | if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) { |
1548 | retval = -ESHUTDOWN; | |
1549 | goto out; | |
db11e47d | 1550 | } |
71a9f9d2 AB |
1551 | retval = usb_hcd_link_urb_to_ep(hcd, urb); |
1552 | if (retval) | |
1553 | goto out; | |
db11e47d | 1554 | |
71a9f9d2 AB |
1555 | qh = urb->ep->hcpriv; |
1556 | if (qh) { | |
1557 | qh_in_queue = 0; | |
1558 | list_for_each_entry(qhit, ep_queue, qh_list) { | |
1559 | if (qhit == qh) { | |
1560 | qh_in_queue = 1; | |
0afb20e0 | 1561 | break; |
71a9f9d2 AB |
1562 | } |
1563 | } | |
1564 | if (!qh_in_queue) | |
1565 | list_add_tail(&qh->qh_list, ep_queue); | |
1566 | } else { | |
1567 | qh = qh_alloc(GFP_ATOMIC); | |
1568 | if (!qh) { | |
1569 | retval = -ENOMEM; | |
38679b72 | 1570 | usb_hcd_unlink_urb_from_ep(hcd, urb); |
71a9f9d2 | 1571 | goto out; |
db11e47d | 1572 | } |
71a9f9d2 AB |
1573 | list_add_tail(&qh->qh_list, ep_queue); |
1574 | urb->ep->hcpriv = qh; | |
db11e47d SS |
1575 | } |
1576 | ||
71a9f9d2 AB |
1577 | list_splice_tail(&new_qtds, &qh->qtd_list); |
1578 | schedule_ptds(hcd); | |
1579 | ||
1580 | out: | |
1581 | spin_unlock_irqrestore(&priv->lock, spinflags); | |
1582 | return retval; | |
db11e47d SS |
1583 | } |
1584 | ||
d05b6ec0 AB |
1585 | static void kill_transfer(struct usb_hcd *hcd, struct urb *urb, |
1586 | struct isp1760_qh *qh) | |
1587 | { | |
1588 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | |
1589 | int skip_map; | |
1590 | ||
1591 | WARN_ON(qh->slot == -1); | |
1592 | ||
1593 | /* We need to forcefully reclaim the slot since some transfers never | |
1594 | return, e.g. interrupt transfers and NAKed bulk transfers. */ | |
8b1ab60c | 1595 | if (usb_pipecontrol(urb->pipe) || usb_pipebulk(urb->pipe)) { |
d05b6ec0 AB |
1596 | skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG); |
1597 | skip_map |= (1 << qh->slot); | |
1598 | reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, skip_map); | |
1599 | priv->atl_slots[qh->slot].qh = NULL; | |
1600 | priv->atl_slots[qh->slot].qtd = NULL; | |
1601 | } else { | |
1602 | skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG); | |
1603 | skip_map |= (1 << qh->slot); | |
1604 | reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, skip_map); | |
1605 | priv->int_slots[qh->slot].qh = NULL; | |
1606 | priv->int_slots[qh->slot].qtd = NULL; | |
1607 | } | |
1608 | ||
1609 | qh->slot = -1; | |
d05b6ec0 AB |
1610 | } |
1611 | ||
71a9f9d2 AB |
1612 | static int isp1760_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, |
1613 | int status) | |
db11e47d | 1614 | { |
6bda21bc | 1615 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
d05b6ec0 | 1616 | unsigned long spinflags; |
71a9f9d2 AB |
1617 | struct isp1760_qh *qh; |
1618 | struct isp1760_qtd *qtd; | |
71a9f9d2 | 1619 | int retval = 0; |
db11e47d | 1620 | |
71a9f9d2 | 1621 | spin_lock_irqsave(&priv->lock, spinflags); |
17d3e145 AB |
1622 | retval = usb_hcd_check_unlink_urb(hcd, urb, status); |
1623 | if (retval) | |
1624 | goto out; | |
db11e47d | 1625 | |
71a9f9d2 AB |
1626 | qh = urb->ep->hcpriv; |
1627 | if (!qh) { | |
1628 | retval = -EINVAL; | |
1629 | goto out; | |
1630 | } | |
db11e47d | 1631 | |
d05b6ec0 AB |
1632 | list_for_each_entry(qtd, &qh->qtd_list, qtd_list) |
1633 | if (qtd->urb == urb) { | |
1634 | if (qtd->status == QTD_XFER_STARTED) | |
1635 | kill_transfer(hcd, urb, qh); | |
71a9f9d2 | 1636 | qtd->status = QTD_RETIRE; |
d05b6ec0 | 1637 | } |
db11e47d | 1638 | |
71a9f9d2 AB |
1639 | urb->status = status; |
1640 | schedule_ptds(hcd); | |
db11e47d | 1641 | |
71a9f9d2 AB |
1642 | out: |
1643 | spin_unlock_irqrestore(&priv->lock, spinflags); | |
71a9f9d2 | 1644 | return retval; |
db11e47d SS |
1645 | } |
1646 | ||
079cdb09 AB |
1647 | static void isp1760_endpoint_disable(struct usb_hcd *hcd, |
1648 | struct usb_host_endpoint *ep) | |
1649 | { | |
1650 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | |
d05b6ec0 | 1651 | unsigned long spinflags; |
079cdb09 AB |
1652 | struct isp1760_qh *qh; |
1653 | struct isp1760_qtd *qtd; | |
079cdb09 AB |
1654 | |
1655 | spin_lock_irqsave(&priv->lock, spinflags); | |
d05b6ec0 | 1656 | |
079cdb09 AB |
1657 | qh = ep->hcpriv; |
1658 | if (!qh) | |
1659 | goto out; | |
1660 | ||
d05b6ec0 AB |
1661 | list_for_each_entry(qtd, &qh->qtd_list, qtd_list) { |
1662 | if (qtd->status == QTD_XFER_STARTED) | |
1663 | kill_transfer(hcd, qtd->urb, qh); | |
1664 | qtd->status = QTD_RETIRE; | |
1665 | qtd->urb->status = -ECONNRESET; | |
079cdb09 | 1666 | } |
d05b6ec0 | 1667 | |
079cdb09 AB |
1668 | ep->hcpriv = NULL; |
1669 | /* Cannot free qh here since it will be parsed by schedule_ptds() */ | |
1670 | ||
d05b6ec0 AB |
1671 | schedule_ptds(hcd); |
1672 | ||
079cdb09 AB |
1673 | out: |
1674 | spin_unlock_irqrestore(&priv->lock, spinflags); | |
1675 | } | |
1676 | ||
db11e47d SS |
1677 | static int isp1760_hub_status_data(struct usb_hcd *hcd, char *buf) |
1678 | { | |
1679 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | |
1680 | u32 temp, status = 0; | |
1681 | u32 mask; | |
1682 | int retval = 1; | |
1683 | unsigned long flags; | |
1684 | ||
1685 | /* if !USB_SUSPEND, root hub timers won't get shut down ... */ | |
1686 | if (!HC_IS_RUNNING(hcd->state)) | |
1687 | return 0; | |
1688 | ||
1689 | /* init status to no-changes */ | |
1690 | buf[0] = 0; | |
1691 | mask = PORT_CSC; | |
1692 | ||
1693 | spin_lock_irqsave(&priv->lock, flags); | |
bedc0c31 | 1694 | temp = reg_read32(hcd->regs, HC_PORTSC1); |
db11e47d SS |
1695 | |
1696 | if (temp & PORT_OWNER) { | |
1697 | if (temp & PORT_CSC) { | |
1698 | temp &= ~PORT_CSC; | |
bedc0c31 | 1699 | reg_write32(hcd->regs, HC_PORTSC1, temp); |
db11e47d SS |
1700 | goto done; |
1701 | } | |
1702 | } | |
1703 | ||
1704 | /* | |
1705 | * Return status information even for ports with OWNER set. | |
1706 | * Otherwise khubd wouldn't see the disconnect event when a | |
1707 | * high-speed device is switched over to the companion | |
1708 | * controller by the user. | |
1709 | */ | |
1710 | ||
1711 | if ((temp & mask) != 0 | |
1712 | || ((temp & PORT_RESUME) != 0 | |
1713 | && time_after_eq(jiffies, | |
1714 | priv->reset_done))) { | |
1715 | buf [0] |= 1 << (0 + 1); | |
1716 | status = STS_PCD; | |
1717 | } | |
1718 | /* FIXME autosuspend idle root hubs */ | |
1719 | done: | |
1720 | spin_unlock_irqrestore(&priv->lock, flags); | |
1721 | return status ? retval : 0; | |
1722 | } | |
1723 | ||
1724 | static void isp1760_hub_descriptor(struct isp1760_hcd *priv, | |
1725 | struct usb_hub_descriptor *desc) | |
1726 | { | |
1727 | int ports = HCS_N_PORTS(priv->hcs_params); | |
1728 | u16 temp; | |
1729 | ||
1730 | desc->bDescriptorType = 0x29; | |
1731 | /* priv 1.0, 2.3.9 says 20ms max */ | |
1732 | desc->bPwrOn2PwrGood = 10; | |
1733 | desc->bHubContrCurrent = 0; | |
1734 | ||
1735 | desc->bNbrPorts = ports; | |
1736 | temp = 1 + (ports / 8); | |
1737 | desc->bDescLength = 7 + 2 * temp; | |
1738 | ||
da13051c | 1739 | /* ports removable, and usb 1.0 legacy PortPwrCtrlMask */ |
dbe79bbe JY |
1740 | memset(&desc->u.hs.DeviceRemovable[0], 0, temp); |
1741 | memset(&desc->u.hs.DeviceRemovable[temp], 0xff, temp); | |
db11e47d SS |
1742 | |
1743 | /* per-port overcurrent reporting */ | |
1744 | temp = 0x0008; | |
1745 | if (HCS_PPC(priv->hcs_params)) | |
1746 | /* per-port power control */ | |
1747 | temp |= 0x0001; | |
1748 | else | |
1749 | /* no power switching */ | |
1750 | temp |= 0x0002; | |
1751 | desc->wHubCharacteristics = cpu_to_le16(temp); | |
1752 | } | |
1753 | ||
1754 | #define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E) | |
1755 | ||
bedc0c31 AB |
1756 | static int check_reset_complete(struct usb_hcd *hcd, int index, |
1757 | int port_status) | |
db11e47d SS |
1758 | { |
1759 | if (!(port_status & PORT_CONNECT)) | |
1760 | return port_status; | |
1761 | ||
1762 | /* if reset finished and it's still not enabled -- handoff */ | |
1763 | if (!(port_status & PORT_PE)) { | |
1764 | ||
71a9f9d2 | 1765 | dev_info(hcd->self.controller, |
6bda21bc AB |
1766 | "port %d full speed --> companion\n", |
1767 | index + 1); | |
db11e47d SS |
1768 | |
1769 | port_status |= PORT_OWNER; | |
1770 | port_status &= ~PORT_RWC_BITS; | |
bedc0c31 | 1771 | reg_write32(hcd->regs, HC_PORTSC1, port_status); |
db11e47d SS |
1772 | |
1773 | } else | |
71a9f9d2 | 1774 | dev_info(hcd->self.controller, "port %d high speed\n", |
6bda21bc | 1775 | index + 1); |
db11e47d SS |
1776 | |
1777 | return port_status; | |
1778 | } | |
1779 | ||
1780 | static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq, | |
1781 | u16 wValue, u16 wIndex, char *buf, u16 wLength) | |
1782 | { | |
1783 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | |
1784 | int ports = HCS_N_PORTS(priv->hcs_params); | |
db11e47d SS |
1785 | u32 temp, status; |
1786 | unsigned long flags; | |
1787 | int retval = 0; | |
1788 | unsigned selector; | |
1789 | ||
1790 | /* | |
1791 | * FIXME: support SetPortFeatures USB_PORT_FEAT_INDICATOR. | |
1792 | * HCS_INDICATOR may say we can change LEDs to off/amber/green. | |
1793 | * (track current state ourselves) ... blink for diagnostics, | |
1794 | * power, "this is the one", etc. EHCI spec supports this. | |
1795 | */ | |
1796 | ||
1797 | spin_lock_irqsave(&priv->lock, flags); | |
1798 | switch (typeReq) { | |
1799 | case ClearHubFeature: | |
1800 | switch (wValue) { | |
1801 | case C_HUB_LOCAL_POWER: | |
1802 | case C_HUB_OVER_CURRENT: | |
1803 | /* no hub-wide feature/status flags */ | |
1804 | break; | |
1805 | default: | |
1806 | goto error; | |
1807 | } | |
1808 | break; | |
1809 | case ClearPortFeature: | |
1810 | if (!wIndex || wIndex > ports) | |
1811 | goto error; | |
1812 | wIndex--; | |
bedc0c31 | 1813 | temp = reg_read32(hcd->regs, HC_PORTSC1); |
db11e47d SS |
1814 | |
1815 | /* | |
1816 | * Even if OWNER is set, so the port is owned by the | |
1817 | * companion controller, khubd needs to be able to clear | |
1818 | * the port-change status bits (especially | |
749da5f8 | 1819 | * USB_PORT_STAT_C_CONNECTION). |
db11e47d SS |
1820 | */ |
1821 | ||
1822 | switch (wValue) { | |
1823 | case USB_PORT_FEAT_ENABLE: | |
bedc0c31 | 1824 | reg_write32(hcd->regs, HC_PORTSC1, temp & ~PORT_PE); |
db11e47d SS |
1825 | break; |
1826 | case USB_PORT_FEAT_C_ENABLE: | |
1827 | /* XXX error? */ | |
1828 | break; | |
1829 | case USB_PORT_FEAT_SUSPEND: | |
1830 | if (temp & PORT_RESET) | |
1831 | goto error; | |
1832 | ||
1833 | if (temp & PORT_SUSPEND) { | |
1834 | if ((temp & PORT_PE) == 0) | |
1835 | goto error; | |
1836 | /* resume signaling for 20 msec */ | |
1837 | temp &= ~(PORT_RWC_BITS); | |
bedc0c31 AB |
1838 | reg_write32(hcd->regs, HC_PORTSC1, |
1839 | temp | PORT_RESUME); | |
db11e47d SS |
1840 | priv->reset_done = jiffies + |
1841 | msecs_to_jiffies(20); | |
1842 | } | |
1843 | break; | |
1844 | case USB_PORT_FEAT_C_SUSPEND: | |
1845 | /* we auto-clear this feature */ | |
1846 | break; | |
1847 | case USB_PORT_FEAT_POWER: | |
1848 | if (HCS_PPC(priv->hcs_params)) | |
bedc0c31 AB |
1849 | reg_write32(hcd->regs, HC_PORTSC1, |
1850 | temp & ~PORT_POWER); | |
db11e47d SS |
1851 | break; |
1852 | case USB_PORT_FEAT_C_CONNECTION: | |
bedc0c31 | 1853 | reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_CSC); |
db11e47d SS |
1854 | break; |
1855 | case USB_PORT_FEAT_C_OVER_CURRENT: | |
1856 | /* XXX error ?*/ | |
1857 | break; | |
1858 | case USB_PORT_FEAT_C_RESET: | |
1859 | /* GetPortStatus clears reset */ | |
1860 | break; | |
1861 | default: | |
1862 | goto error; | |
1863 | } | |
bedc0c31 | 1864 | reg_read32(hcd->regs, HC_USBCMD); |
db11e47d SS |
1865 | break; |
1866 | case GetHubDescriptor: | |
1867 | isp1760_hub_descriptor(priv, (struct usb_hub_descriptor *) | |
1868 | buf); | |
1869 | break; | |
1870 | case GetHubStatus: | |
1871 | /* no hub-wide feature/status flags */ | |
1872 | memset(buf, 0, 4); | |
1873 | break; | |
1874 | case GetPortStatus: | |
1875 | if (!wIndex || wIndex > ports) | |
1876 | goto error; | |
1877 | wIndex--; | |
1878 | status = 0; | |
bedc0c31 | 1879 | temp = reg_read32(hcd->regs, HC_PORTSC1); |
db11e47d SS |
1880 | |
1881 | /* wPortChange bits */ | |
1882 | if (temp & PORT_CSC) | |
749da5f8 | 1883 | status |= USB_PORT_STAT_C_CONNECTION << 16; |
db11e47d SS |
1884 | |
1885 | ||
1886 | /* whoever resumes must GetPortStatus to complete it!! */ | |
1887 | if (temp & PORT_RESUME) { | |
6bda21bc | 1888 | dev_err(hcd->self.controller, "Port resume should be skipped.\n"); |
db11e47d SS |
1889 | |
1890 | /* Remote Wakeup received? */ | |
1891 | if (!priv->reset_done) { | |
1892 | /* resume signaling for 20 msec */ | |
1893 | priv->reset_done = jiffies | |
1894 | + msecs_to_jiffies(20); | |
1895 | /* check the port again */ | |
6bda21bc | 1896 | mod_timer(&hcd->rh_timer, priv->reset_done); |
db11e47d SS |
1897 | } |
1898 | ||
1899 | /* resume completed? */ | |
1900 | else if (time_after_eq(jiffies, | |
1901 | priv->reset_done)) { | |
749da5f8 | 1902 | status |= USB_PORT_STAT_C_SUSPEND << 16; |
db11e47d SS |
1903 | priv->reset_done = 0; |
1904 | ||
1905 | /* stop resume signaling */ | |
bedc0c31 AB |
1906 | temp = reg_read32(hcd->regs, HC_PORTSC1); |
1907 | reg_write32(hcd->regs, HC_PORTSC1, | |
1908 | temp & ~(PORT_RWC_BITS | PORT_RESUME)); | |
1909 | retval = handshake(hcd, HC_PORTSC1, | |
db11e47d SS |
1910 | PORT_RESUME, 0, 2000 /* 2msec */); |
1911 | if (retval != 0) { | |
6bda21bc | 1912 | dev_err(hcd->self.controller, |
db11e47d SS |
1913 | "port %d resume error %d\n", |
1914 | wIndex + 1, retval); | |
1915 | goto error; | |
1916 | } | |
1917 | temp &= ~(PORT_SUSPEND|PORT_RESUME|(3<<10)); | |
1918 | } | |
1919 | } | |
1920 | ||
1921 | /* whoever resets must GetPortStatus to complete it!! */ | |
1922 | if ((temp & PORT_RESET) | |
1923 | && time_after_eq(jiffies, | |
1924 | priv->reset_done)) { | |
749da5f8 | 1925 | status |= USB_PORT_STAT_C_RESET << 16; |
db11e47d SS |
1926 | priv->reset_done = 0; |
1927 | ||
1928 | /* force reset to complete */ | |
bedc0c31 | 1929 | reg_write32(hcd->regs, HC_PORTSC1, temp & ~PORT_RESET); |
db11e47d SS |
1930 | /* REVISIT: some hardware needs 550+ usec to clear |
1931 | * this bit; seems too long to spin routinely... | |
1932 | */ | |
bedc0c31 | 1933 | retval = handshake(hcd, HC_PORTSC1, |
db11e47d SS |
1934 | PORT_RESET, 0, 750); |
1935 | if (retval != 0) { | |
6bda21bc | 1936 | dev_err(hcd->self.controller, "port %d reset error %d\n", |
db11e47d SS |
1937 | wIndex + 1, retval); |
1938 | goto error; | |
1939 | } | |
1940 | ||
1941 | /* see what we found out */ | |
bedc0c31 AB |
1942 | temp = check_reset_complete(hcd, wIndex, |
1943 | reg_read32(hcd->regs, HC_PORTSC1)); | |
db11e47d SS |
1944 | } |
1945 | /* | |
1946 | * Even if OWNER is set, there's no harm letting khubd | |
1947 | * see the wPortStatus values (they should all be 0 except | |
1948 | * for PORT_POWER anyway). | |
1949 | */ | |
1950 | ||
1951 | if (temp & PORT_OWNER) | |
6bda21bc | 1952 | dev_err(hcd->self.controller, "PORT_OWNER is set\n"); |
db11e47d SS |
1953 | |
1954 | if (temp & PORT_CONNECT) { | |
749da5f8 | 1955 | status |= USB_PORT_STAT_CONNECTION; |
db11e47d | 1956 | /* status may be from integrated TT */ |
6bda21bc | 1957 | status |= USB_PORT_STAT_HIGH_SPEED; |
db11e47d SS |
1958 | } |
1959 | if (temp & PORT_PE) | |
749da5f8 | 1960 | status |= USB_PORT_STAT_ENABLE; |
db11e47d | 1961 | if (temp & (PORT_SUSPEND|PORT_RESUME)) |
749da5f8 | 1962 | status |= USB_PORT_STAT_SUSPEND; |
db11e47d | 1963 | if (temp & PORT_RESET) |
749da5f8 | 1964 | status |= USB_PORT_STAT_RESET; |
db11e47d | 1965 | if (temp & PORT_POWER) |
749da5f8 | 1966 | status |= USB_PORT_STAT_POWER; |
db11e47d SS |
1967 | |
1968 | put_unaligned(cpu_to_le32(status), (__le32 *) buf); | |
1969 | break; | |
1970 | case SetHubFeature: | |
1971 | switch (wValue) { | |
1972 | case C_HUB_LOCAL_POWER: | |
1973 | case C_HUB_OVER_CURRENT: | |
1974 | /* no hub-wide feature/status flags */ | |
1975 | break; | |
1976 | default: | |
1977 | goto error; | |
1978 | } | |
1979 | break; | |
1980 | case SetPortFeature: | |
1981 | selector = wIndex >> 8; | |
1982 | wIndex &= 0xff; | |
1983 | if (!wIndex || wIndex > ports) | |
1984 | goto error; | |
1985 | wIndex--; | |
bedc0c31 | 1986 | temp = reg_read32(hcd->regs, HC_PORTSC1); |
db11e47d SS |
1987 | if (temp & PORT_OWNER) |
1988 | break; | |
1989 | ||
1990 | /* temp &= ~PORT_RWC_BITS; */ | |
1991 | switch (wValue) { | |
1992 | case USB_PORT_FEAT_ENABLE: | |
bedc0c31 | 1993 | reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_PE); |
db11e47d SS |
1994 | break; |
1995 | ||
1996 | case USB_PORT_FEAT_SUSPEND: | |
1997 | if ((temp & PORT_PE) == 0 | |
1998 | || (temp & PORT_RESET) != 0) | |
1999 | goto error; | |
2000 | ||
bedc0c31 | 2001 | reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_SUSPEND); |
db11e47d SS |
2002 | break; |
2003 | case USB_PORT_FEAT_POWER: | |
2004 | if (HCS_PPC(priv->hcs_params)) | |
bedc0c31 AB |
2005 | reg_write32(hcd->regs, HC_PORTSC1, |
2006 | temp | PORT_POWER); | |
db11e47d SS |
2007 | break; |
2008 | case USB_PORT_FEAT_RESET: | |
2009 | if (temp & PORT_RESUME) | |
2010 | goto error; | |
2011 | /* line status bits may report this as low speed, | |
2012 | * which can be fine if this root hub has a | |
2013 | * transaction translator built in. | |
2014 | */ | |
2015 | if ((temp & (PORT_PE|PORT_CONNECT)) == PORT_CONNECT | |
2016 | && PORT_USB11(temp)) { | |
2017 | temp |= PORT_OWNER; | |
2018 | } else { | |
2019 | temp |= PORT_RESET; | |
2020 | temp &= ~PORT_PE; | |
2021 | ||
2022 | /* | |
2023 | * caller must wait, then call GetPortStatus | |
2024 | * usb 2.0 spec says 50 ms resets on root | |
2025 | */ | |
2026 | priv->reset_done = jiffies + | |
2027 | msecs_to_jiffies(50); | |
2028 | } | |
bedc0c31 | 2029 | reg_write32(hcd->regs, HC_PORTSC1, temp); |
db11e47d SS |
2030 | break; |
2031 | default: | |
2032 | goto error; | |
2033 | } | |
bedc0c31 | 2034 | reg_read32(hcd->regs, HC_USBCMD); |
db11e47d SS |
2035 | break; |
2036 | ||
2037 | default: | |
2038 | error: | |
2039 | /* "stall" on error */ | |
2040 | retval = -EPIPE; | |
2041 | } | |
2042 | spin_unlock_irqrestore(&priv->lock, flags); | |
2043 | return retval; | |
2044 | } | |
2045 | ||
db11e47d SS |
2046 | static int isp1760_get_frame(struct usb_hcd *hcd) |
2047 | { | |
2048 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | |
2049 | u32 fr; | |
2050 | ||
bedc0c31 | 2051 | fr = reg_read32(hcd->regs, HC_FRINDEX); |
db11e47d SS |
2052 | return (fr >> 3) % priv->periodic_size; |
2053 | } | |
2054 | ||
2055 | static void isp1760_stop(struct usb_hcd *hcd) | |
2056 | { | |
2057 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | |
3faefc88 | 2058 | u32 temp; |
db11e47d | 2059 | |
6d50c60e AB |
2060 | del_timer(&errata2_timer); |
2061 | ||
db11e47d SS |
2062 | isp1760_hub_control(hcd, ClearPortFeature, USB_PORT_FEAT_POWER, 1, |
2063 | NULL, 0); | |
2064 | mdelay(20); | |
2065 | ||
2066 | spin_lock_irq(&priv->lock); | |
6bda21bc | 2067 | ehci_reset(hcd); |
db11e47d | 2068 | /* Disable IRQ */ |
bedc0c31 AB |
2069 | temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL); |
2070 | reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp &= ~HW_GLOBAL_INTR_EN); | |
db11e47d SS |
2071 | spin_unlock_irq(&priv->lock); |
2072 | ||
bedc0c31 | 2073 | reg_write32(hcd->regs, HC_CONFIGFLAG, 0); |
db11e47d SS |
2074 | } |
2075 | ||
2076 | static void isp1760_shutdown(struct usb_hcd *hcd) | |
2077 | { | |
3faefc88 | 2078 | u32 command, temp; |
db11e47d SS |
2079 | |
2080 | isp1760_stop(hcd); | |
bedc0c31 AB |
2081 | temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL); |
2082 | reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp &= ~HW_GLOBAL_INTR_EN); | |
db11e47d | 2083 | |
bedc0c31 | 2084 | command = reg_read32(hcd->regs, HC_USBCMD); |
db11e47d | 2085 | command &= ~CMD_RUN; |
bedc0c31 | 2086 | reg_write32(hcd->regs, HC_USBCMD, command); |
db11e47d SS |
2087 | } |
2088 | ||
2089 | static const struct hc_driver isp1760_hc_driver = { | |
2090 | .description = "isp1760-hcd", | |
2091 | .product_desc = "NXP ISP1760 USB Host Controller", | |
2092 | .hcd_priv_size = sizeof(struct isp1760_hcd), | |
2093 | .irq = isp1760_irq, | |
2094 | .flags = HCD_MEMORY | HCD_USB2, | |
2095 | .reset = isp1760_hc_setup, | |
2096 | .start = isp1760_run, | |
2097 | .stop = isp1760_stop, | |
2098 | .shutdown = isp1760_shutdown, | |
2099 | .urb_enqueue = isp1760_urb_enqueue, | |
2100 | .urb_dequeue = isp1760_urb_dequeue, | |
2101 | .endpoint_disable = isp1760_endpoint_disable, | |
2102 | .get_frame_number = isp1760_get_frame, | |
2103 | .hub_status_data = isp1760_hub_status_data, | |
2104 | .hub_control = isp1760_hub_control, | |
2105 | }; | |
2106 | ||
2107 | int __init init_kmem_once(void) | |
2108 | { | |
71a9f9d2 AB |
2109 | urb_listitem_cachep = kmem_cache_create("isp1760 urb_listitem", |
2110 | sizeof(struct urb_listitem), 0, SLAB_TEMPORARY | | |
2111 | SLAB_MEM_SPREAD, NULL); | |
2112 | ||
2113 | if (!urb_listitem_cachep) | |
2114 | return -ENOMEM; | |
2115 | ||
db11e47d SS |
2116 | qtd_cachep = kmem_cache_create("isp1760_qtd", |
2117 | sizeof(struct isp1760_qtd), 0, SLAB_TEMPORARY | | |
2118 | SLAB_MEM_SPREAD, NULL); | |
2119 | ||
2120 | if (!qtd_cachep) | |
2121 | return -ENOMEM; | |
2122 | ||
2123 | qh_cachep = kmem_cache_create("isp1760_qh", sizeof(struct isp1760_qh), | |
2124 | 0, SLAB_TEMPORARY | SLAB_MEM_SPREAD, NULL); | |
2125 | ||
2126 | if (!qh_cachep) { | |
2127 | kmem_cache_destroy(qtd_cachep); | |
2128 | return -ENOMEM; | |
2129 | } | |
2130 | ||
2131 | return 0; | |
2132 | } | |
2133 | ||
2134 | void deinit_kmem_cache(void) | |
2135 | { | |
2136 | kmem_cache_destroy(qtd_cachep); | |
2137 | kmem_cache_destroy(qh_cachep); | |
71a9f9d2 | 2138 | kmem_cache_destroy(urb_listitem_cachep); |
db11e47d SS |
2139 | } |
2140 | ||
f9031f2c CM |
2141 | struct usb_hcd *isp1760_register(phys_addr_t res_start, resource_size_t res_len, |
2142 | int irq, unsigned long irqflags, | |
2143 | struct device *dev, const char *busname, | |
2144 | unsigned int devflags) | |
db11e47d SS |
2145 | { |
2146 | struct usb_hcd *hcd; | |
2147 | struct isp1760_hcd *priv; | |
2148 | int ret; | |
2149 | ||
2150 | if (usb_disabled()) | |
2151 | return ERR_PTR(-ENODEV); | |
2152 | ||
2153 | /* prevent usb-core allocating DMA pages */ | |
2154 | dev->dma_mask = NULL; | |
2155 | ||
0031a06e | 2156 | hcd = usb_create_hcd(&isp1760_hc_driver, dev, dev_name(dev)); |
db11e47d SS |
2157 | if (!hcd) |
2158 | return ERR_PTR(-ENOMEM); | |
2159 | ||
2160 | priv = hcd_to_priv(hcd); | |
3faefc88 | 2161 | priv->devflags = devflags; |
db11e47d SS |
2162 | init_memory(priv); |
2163 | hcd->regs = ioremap(res_start, res_len); | |
2164 | if (!hcd->regs) { | |
2165 | ret = -EIO; | |
2166 | goto err_put; | |
2167 | } | |
2168 | ||
db11e47d SS |
2169 | hcd->irq = irq; |
2170 | hcd->rsrc_start = res_start; | |
2171 | hcd->rsrc_len = res_len; | |
2172 | ||
e6942d63 NC |
2173 | ret = usb_add_hcd(hcd, irq, irqflags); |
2174 | if (ret) | |
2175 | goto err_unmap; | |
2176 | ||
db11e47d SS |
2177 | return hcd; |
2178 | ||
2179 | err_unmap: | |
2180 | iounmap(hcd->regs); | |
2181 | ||
2182 | err_put: | |
2183 | usb_put_hcd(hcd); | |
2184 | ||
2185 | return ERR_PTR(ret); | |
2186 | } | |
2187 | ||
2188 | MODULE_DESCRIPTION("Driver for the ISP1760 USB-controller from NXP"); | |
2189 | MODULE_AUTHOR("Sebastian Siewior <bigeasy@linuxtronix.de>"); | |
2190 | MODULE_LICENSE("GPL v2"); |