]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * OHCI HCD (Host Controller Driver) for USB. | |
3 | * | |
4 | * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at> | |
5 | * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net> | |
dd9048af | 6 | * |
1da177e4 LT |
7 | * [ Initialisation is based on Linus' ] |
8 | * [ uhci code and gregs ohci fragments ] | |
9 | * [ (C) Copyright 1999 Linus Torvalds ] | |
10 | * [ (C) Copyright 1999 Gregory P. Smith] | |
dd9048af DB |
11 | * |
12 | * | |
1da177e4 LT |
13 | * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller |
14 | * interfaces (though some non-x86 Intel chips use it). It supports | |
15 | * smarter hardware than UHCI. A download link for the spec available | |
16 | * through the http://www.usb.org website. | |
17 | * | |
1da177e4 LT |
18 | * This file is licenced under the GPL. |
19 | */ | |
dd9048af | 20 | |
1da177e4 LT |
21 | #include <linux/module.h> |
22 | #include <linux/moduleparam.h> | |
23 | #include <linux/pci.h> | |
24 | #include <linux/kernel.h> | |
25 | #include <linux/delay.h> | |
26 | #include <linux/ioport.h> | |
27 | #include <linux/sched.h> | |
28 | #include <linux/slab.h> | |
1da177e4 LT |
29 | #include <linux/errno.h> |
30 | #include <linux/init.h> | |
31 | #include <linux/timer.h> | |
32 | #include <linux/list.h> | |
1da177e4 | 33 | #include <linux/usb.h> |
3a16f7b4 | 34 | #include <linux/usb/otg.h> |
dd9048af | 35 | #include <linux/dma-mapping.h> |
f4df0e33 DB |
36 | #include <linux/dmapool.h> |
37 | #include <linux/reboot.h> | |
1da177e4 LT |
38 | |
39 | #include <asm/io.h> | |
40 | #include <asm/irq.h> | |
41 | #include <asm/system.h> | |
42 | #include <asm/unaligned.h> | |
43 | #include <asm/byteorder.h> | |
48fda451 IK |
44 | #ifdef CONFIG_PPC_PS3 |
45 | #include <asm/firmware.h> | |
46 | #endif | |
1da177e4 | 47 | |
f4df0e33 | 48 | #include "../core/hcd.h" |
1da177e4 | 49 | |
d413984a | 50 | #define DRIVER_VERSION "2006 August 04" |
1da177e4 LT |
51 | #define DRIVER_AUTHOR "Roman Weissgaerber, David Brownell" |
52 | #define DRIVER_DESC "USB 1.1 'Open' Host Controller (OHCI) Driver" | |
53 | ||
54 | /*-------------------------------------------------------------------------*/ | |
55 | ||
8de98402 | 56 | #undef OHCI_VERBOSE_DEBUG /* not always helpful */ |
1da177e4 LT |
57 | |
58 | /* For initializing controller (mask in an HCFS mode too) */ | |
d413984a | 59 | #define OHCI_CONTROL_INIT OHCI_CTRL_CBSR |
1da177e4 | 60 | #define OHCI_INTR_INIT \ |
d413984a DB |
61 | (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE \ |
62 | | OHCI_INTR_RD | OHCI_INTR_WDH) | |
1da177e4 LT |
63 | |
64 | #ifdef __hppa__ | |
65 | /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */ | |
66 | #define IR_DISABLE | |
67 | #endif | |
68 | ||
69 | #ifdef CONFIG_ARCH_OMAP | |
70 | /* OMAP doesn't support IR (no SMM; not needed) */ | |
71 | #define IR_DISABLE | |
72 | #endif | |
73 | ||
74 | /*-------------------------------------------------------------------------*/ | |
75 | ||
76 | static const char hcd_name [] = "ohci_hcd"; | |
77 | ||
d413984a DB |
78 | #define STATECHANGE_DELAY msecs_to_jiffies(300) |
79 | ||
1da177e4 LT |
80 | #include "ohci.h" |
81 | ||
82 | static void ohci_dump (struct ohci_hcd *ohci, int verbose); | |
83 | static int ohci_init (struct ohci_hcd *ohci); | |
84 | static void ohci_stop (struct usb_hcd *hcd); | |
85 | ||
86 | #include "ohci-hub.c" | |
87 | #include "ohci-dbg.c" | |
88 | #include "ohci-mem.c" | |
89 | #include "ohci-q.c" | |
90 | ||
91 | ||
92 | /* | |
93 | * On architectures with edge-triggered interrupts we must never return | |
94 | * IRQ_NONE. | |
95 | */ | |
96 | #if defined(CONFIG_SA1111) /* ... or other edge-triggered systems */ | |
97 | #define IRQ_NOTMINE IRQ_HANDLED | |
98 | #else | |
99 | #define IRQ_NOTMINE IRQ_NONE | |
100 | #endif | |
101 | ||
102 | ||
103 | /* Some boards misreport power switching/overcurrent */ | |
104 | static int distrust_firmware = 1; | |
105 | module_param (distrust_firmware, bool, 0); | |
106 | MODULE_PARM_DESC (distrust_firmware, | |
107 | "true to distrust firmware power/overcurrent setup"); | |
108 | ||
109 | /* Some boards leave IR set wrongly, since they fail BIOS/SMM handshakes */ | |
110 | static int no_handshake = 0; | |
111 | module_param (no_handshake, bool, 0); | |
112 | MODULE_PARM_DESC (no_handshake, "true (not default) disables BIOS handshake"); | |
113 | ||
114 | /*-------------------------------------------------------------------------*/ | |
115 | ||
116 | /* | |
117 | * queue up an urb for anything except the root hub | |
118 | */ | |
119 | static int ohci_urb_enqueue ( | |
120 | struct usb_hcd *hcd, | |
121 | struct usb_host_endpoint *ep, | |
122 | struct urb *urb, | |
55016f10 | 123 | gfp_t mem_flags |
1da177e4 LT |
124 | ) { |
125 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); | |
126 | struct ed *ed; | |
127 | urb_priv_t *urb_priv; | |
128 | unsigned int pipe = urb->pipe; | |
129 | int i, size = 0; | |
130 | unsigned long flags; | |
131 | int retval = 0; | |
dd9048af | 132 | |
1da177e4 LT |
133 | #ifdef OHCI_VERBOSE_DEBUG |
134 | urb_print (urb, "SUB", usb_pipein (pipe)); | |
135 | #endif | |
dd9048af | 136 | |
1da177e4 LT |
137 | /* every endpoint has a ed, locate and maybe (re)initialize it */ |
138 | if (! (ed = ed_get (ohci, ep, urb->dev, pipe, urb->interval))) | |
139 | return -ENOMEM; | |
140 | ||
141 | /* for the private part of the URB we need the number of TDs (size) */ | |
142 | switch (ed->type) { | |
143 | case PIPE_CONTROL: | |
144 | /* td_submit_urb() doesn't yet handle these */ | |
145 | if (urb->transfer_buffer_length > 4096) | |
146 | return -EMSGSIZE; | |
147 | ||
148 | /* 1 TD for setup, 1 for ACK, plus ... */ | |
149 | size = 2; | |
150 | /* FALLTHROUGH */ | |
151 | // case PIPE_INTERRUPT: | |
152 | // case PIPE_BULK: | |
153 | default: | |
154 | /* one TD for every 4096 Bytes (can be upto 8K) */ | |
155 | size += urb->transfer_buffer_length / 4096; | |
156 | /* ... and for any remaining bytes ... */ | |
157 | if ((urb->transfer_buffer_length % 4096) != 0) | |
158 | size++; | |
159 | /* ... and maybe a zero length packet to wrap it up */ | |
160 | if (size == 0) | |
161 | size++; | |
162 | else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0 | |
163 | && (urb->transfer_buffer_length | |
164 | % usb_maxpacket (urb->dev, pipe, | |
165 | usb_pipeout (pipe))) == 0) | |
166 | size++; | |
167 | break; | |
168 | case PIPE_ISOCHRONOUS: /* number of packets from URB */ | |
169 | size = urb->number_of_packets; | |
170 | break; | |
171 | } | |
172 | ||
173 | /* allocate the private part of the URB */ | |
174 | urb_priv = kmalloc (sizeof (urb_priv_t) + size * sizeof (struct td *), | |
175 | mem_flags); | |
176 | if (!urb_priv) | |
177 | return -ENOMEM; | |
178 | memset (urb_priv, 0, sizeof (urb_priv_t) + size * sizeof (struct td *)); | |
179 | INIT_LIST_HEAD (&urb_priv->pending); | |
180 | urb_priv->length = size; | |
dd9048af | 181 | urb_priv->ed = ed; |
1da177e4 LT |
182 | |
183 | /* allocate the TDs (deferring hash chain updates) */ | |
184 | for (i = 0; i < size; i++) { | |
185 | urb_priv->td [i] = td_alloc (ohci, mem_flags); | |
186 | if (!urb_priv->td [i]) { | |
187 | urb_priv->length = i; | |
188 | urb_free_priv (ohci, urb_priv); | |
189 | return -ENOMEM; | |
190 | } | |
dd9048af | 191 | } |
1da177e4 LT |
192 | |
193 | spin_lock_irqsave (&ohci->lock, flags); | |
194 | ||
195 | /* don't submit to a dead HC */ | |
8de98402 BH |
196 | if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) { |
197 | retval = -ENODEV; | |
198 | goto fail; | |
199 | } | |
1da177e4 LT |
200 | if (!HC_IS_RUNNING(hcd->state)) { |
201 | retval = -ENODEV; | |
202 | goto fail; | |
203 | } | |
204 | ||
205 | /* in case of unlink-during-submit */ | |
206 | spin_lock (&urb->lock); | |
207 | if (urb->status != -EINPROGRESS) { | |
208 | spin_unlock (&urb->lock); | |
209 | urb->hcpriv = urb_priv; | |
7d12e780 | 210 | finish_urb (ohci, urb); |
1da177e4 LT |
211 | retval = 0; |
212 | goto fail; | |
213 | } | |
214 | ||
215 | /* schedule the ed if needed */ | |
216 | if (ed->state == ED_IDLE) { | |
217 | retval = ed_schedule (ohci, ed); | |
218 | if (retval < 0) | |
219 | goto fail0; | |
220 | if (ed->type == PIPE_ISOCHRONOUS) { | |
221 | u16 frame = ohci_frame_no(ohci); | |
222 | ||
223 | /* delay a few frames before the first TD */ | |
224 | frame += max_t (u16, 8, ed->interval); | |
225 | frame &= ~(ed->interval - 1); | |
226 | frame |= ed->branch; | |
227 | urb->start_frame = frame; | |
228 | ||
229 | /* yes, only URB_ISO_ASAP is supported, and | |
230 | * urb->start_frame is never used as input. | |
231 | */ | |
232 | } | |
233 | } else if (ed->type == PIPE_ISOCHRONOUS) | |
234 | urb->start_frame = ed->last_iso + ed->interval; | |
235 | ||
236 | /* fill the TDs and link them to the ed; and | |
237 | * enable that part of the schedule, if needed | |
238 | * and update count of queued periodic urbs | |
239 | */ | |
240 | urb->hcpriv = urb_priv; | |
241 | td_submit_urb (ohci, urb); | |
242 | ||
243 | fail0: | |
244 | spin_unlock (&urb->lock); | |
245 | fail: | |
246 | if (retval) | |
247 | urb_free_priv (ohci, urb_priv); | |
248 | spin_unlock_irqrestore (&ohci->lock, flags); | |
249 | return retval; | |
250 | } | |
251 | ||
252 | /* | |
253 | * decouple the URB from the HC queues (TDs, urb_priv); it's | |
254 | * already marked using urb->status. reporting is always done | |
255 | * asynchronously, and we might be dealing with an urb that's | |
256 | * partially transferred, or an ED with other urbs being unlinked. | |
257 | */ | |
258 | static int ohci_urb_dequeue (struct usb_hcd *hcd, struct urb *urb) | |
259 | { | |
260 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); | |
261 | unsigned long flags; | |
dd9048af | 262 | |
1da177e4 LT |
263 | #ifdef OHCI_VERBOSE_DEBUG |
264 | urb_print (urb, "UNLINK", 1); | |
dd9048af | 265 | #endif |
1da177e4 LT |
266 | |
267 | spin_lock_irqsave (&ohci->lock, flags); | |
dd9048af | 268 | if (HC_IS_RUNNING(hcd->state)) { |
1da177e4 LT |
269 | urb_priv_t *urb_priv; |
270 | ||
271 | /* Unless an IRQ completed the unlink while it was being | |
272 | * handed to us, flag it for unlink and giveback, and force | |
273 | * some upcoming INTR_SF to call finish_unlinks() | |
274 | */ | |
275 | urb_priv = urb->hcpriv; | |
276 | if (urb_priv) { | |
277 | if (urb_priv->ed->state == ED_OPER) | |
278 | start_ed_unlink (ohci, urb_priv->ed); | |
279 | } | |
280 | } else { | |
281 | /* | |
282 | * with HC dead, we won't respect hc queue pointers | |
283 | * any more ... just clean up every urb's memory. | |
284 | */ | |
285 | if (urb->hcpriv) | |
7d12e780 | 286 | finish_urb (ohci, urb); |
1da177e4 LT |
287 | } |
288 | spin_unlock_irqrestore (&ohci->lock, flags); | |
289 | return 0; | |
290 | } | |
291 | ||
292 | /*-------------------------------------------------------------------------*/ | |
293 | ||
294 | /* frees config/altsetting state for endpoints, | |
295 | * including ED memory, dummy TD, and bulk/intr data toggle | |
296 | */ | |
297 | ||
298 | static void | |
299 | ohci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep) | |
300 | { | |
301 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); | |
302 | unsigned long flags; | |
303 | struct ed *ed = ep->hcpriv; | |
304 | unsigned limit = 1000; | |
305 | ||
306 | /* ASSERT: any requests/urbs are being unlinked */ | |
307 | /* ASSERT: nobody can be submitting urbs for this any more */ | |
308 | ||
309 | if (!ed) | |
310 | return; | |
311 | ||
312 | rescan: | |
313 | spin_lock_irqsave (&ohci->lock, flags); | |
314 | ||
315 | if (!HC_IS_RUNNING (hcd->state)) { | |
316 | sanitize: | |
317 | ed->state = ED_IDLE; | |
7d12e780 | 318 | finish_unlinks (ohci, 0); |
1da177e4 LT |
319 | } |
320 | ||
321 | switch (ed->state) { | |
322 | case ED_UNLINK: /* wait for hw to finish? */ | |
323 | /* major IRQ delivery trouble loses INTR_SF too... */ | |
324 | if (limit-- == 0) { | |
325 | ohci_warn (ohci, "IRQ INTR_SF lossage\n"); | |
326 | goto sanitize; | |
327 | } | |
328 | spin_unlock_irqrestore (&ohci->lock, flags); | |
22c43863 | 329 | schedule_timeout_uninterruptible(1); |
1da177e4 LT |
330 | goto rescan; |
331 | case ED_IDLE: /* fully unlinked */ | |
332 | if (list_empty (&ed->td_list)) { | |
333 | td_free (ohci, ed->dummy); | |
334 | ed_free (ohci, ed); | |
335 | break; | |
336 | } | |
337 | /* else FALL THROUGH */ | |
338 | default: | |
339 | /* caller was supposed to have unlinked any requests; | |
340 | * that's not our job. can't recover; must leak ed. | |
341 | */ | |
342 | ohci_err (ohci, "leak ed %p (#%02x) state %d%s\n", | |
343 | ed, ep->desc.bEndpointAddress, ed->state, | |
344 | list_empty (&ed->td_list) ? "" : " (has tds)"); | |
345 | td_free (ohci, ed->dummy); | |
346 | break; | |
347 | } | |
348 | ep->hcpriv = NULL; | |
349 | spin_unlock_irqrestore (&ohci->lock, flags); | |
350 | return; | |
351 | } | |
352 | ||
353 | static int ohci_get_frame (struct usb_hcd *hcd) | |
354 | { | |
355 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); | |
356 | ||
357 | return ohci_frame_no(ohci); | |
358 | } | |
359 | ||
360 | static void ohci_usb_reset (struct ohci_hcd *ohci) | |
361 | { | |
362 | ohci->hc_control = ohci_readl (ohci, &ohci->regs->control); | |
363 | ohci->hc_control &= OHCI_CTRL_RWC; | |
364 | ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); | |
365 | } | |
366 | ||
64a21d02 | 367 | /* ohci_shutdown forcibly disables IRQs and DMA, helping kexec and |
f4df0e33 DB |
368 | * other cases where the next software may expect clean state from the |
369 | * "firmware". this is bus-neutral, unlike shutdown() methods. | |
370 | */ | |
64a21d02 AG |
371 | static void |
372 | ohci_shutdown (struct usb_hcd *hcd) | |
f4df0e33 DB |
373 | { |
374 | struct ohci_hcd *ohci; | |
375 | ||
64a21d02 | 376 | ohci = hcd_to_ohci (hcd); |
f4df0e33 DB |
377 | ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable); |
378 | ohci_usb_reset (ohci); | |
379 | /* flush the writes */ | |
380 | (void) ohci_readl (ohci, &ohci->regs->control); | |
f4df0e33 DB |
381 | } |
382 | ||
1da177e4 LT |
383 | /*-------------------------------------------------------------------------* |
384 | * HC functions | |
385 | *-------------------------------------------------------------------------*/ | |
386 | ||
387 | /* init memory, and kick BIOS/SMM off */ | |
388 | ||
389 | static int ohci_init (struct ohci_hcd *ohci) | |
390 | { | |
391 | int ret; | |
6a9062f3 | 392 | struct usb_hcd *hcd = ohci_to_hcd(ohci); |
1da177e4 LT |
393 | |
394 | disable (ohci); | |
6a9062f3 | 395 | ohci->regs = hcd->regs; |
1da177e4 | 396 | |
6a9062f3 DB |
397 | /* REVISIT this BIOS handshake is now moved into PCI "quirks", and |
398 | * was never needed for most non-PCI systems ... remove the code? | |
399 | */ | |
400 | ||
1da177e4 LT |
401 | #ifndef IR_DISABLE |
402 | /* SMM owns the HC? not for long! */ | |
403 | if (!no_handshake && ohci_readl (ohci, | |
404 | &ohci->regs->control) & OHCI_CTRL_IR) { | |
405 | u32 temp; | |
406 | ||
407 | ohci_dbg (ohci, "USB HC TakeOver from BIOS/SMM\n"); | |
408 | ||
409 | /* this timeout is arbitrary. we make it long, so systems | |
410 | * depending on usb keyboards may be usable even if the | |
411 | * BIOS/SMM code seems pretty broken. | |
412 | */ | |
413 | temp = 500; /* arbitrary: five seconds */ | |
414 | ||
415 | ohci_writel (ohci, OHCI_INTR_OC, &ohci->regs->intrenable); | |
416 | ohci_writel (ohci, OHCI_OCR, &ohci->regs->cmdstatus); | |
417 | while (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_IR) { | |
418 | msleep (10); | |
419 | if (--temp == 0) { | |
420 | ohci_err (ohci, "USB HC takeover failed!" | |
421 | " (BIOS/SMM bug)\n"); | |
422 | return -EBUSY; | |
423 | } | |
424 | } | |
425 | ohci_usb_reset (ohci); | |
426 | } | |
427 | #endif | |
428 | ||
429 | /* Disable HC interrupts */ | |
430 | ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable); | |
6a9062f3 DB |
431 | |
432 | /* flush the writes, and save key bits like RWC */ | |
433 | if (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_RWC) | |
434 | ohci->hc_control |= OHCI_CTRL_RWC; | |
1da177e4 | 435 | |
fdd13b36 DB |
436 | /* Read the number of ports unless overridden */ |
437 | if (ohci->num_ports == 0) | |
438 | ohci->num_ports = roothub_a(ohci) & RH_A_NDP; | |
439 | ||
1da177e4 LT |
440 | if (ohci->hcca) |
441 | return 0; | |
442 | ||
6a9062f3 | 443 | ohci->hcca = dma_alloc_coherent (hcd->self.controller, |
1da177e4 LT |
444 | sizeof *ohci->hcca, &ohci->hcca_dma, 0); |
445 | if (!ohci->hcca) | |
446 | return -ENOMEM; | |
447 | ||
448 | if ((ret = ohci_mem_init (ohci)) < 0) | |
6a9062f3 DB |
449 | ohci_stop (hcd); |
450 | else { | |
6a9062f3 DB |
451 | create_debug_files (ohci); |
452 | } | |
1da177e4 LT |
453 | |
454 | return ret; | |
1da177e4 LT |
455 | } |
456 | ||
457 | /*-------------------------------------------------------------------------*/ | |
458 | ||
459 | /* Start an OHCI controller, set the BUS operational | |
460 | * resets USB and controller | |
dd9048af | 461 | * enable interrupts |
1da177e4 LT |
462 | */ |
463 | static int ohci_run (struct ohci_hcd *ohci) | |
464 | { | |
dd9048af | 465 | u32 mask, temp; |
1da177e4 | 466 | int first = ohci->fminterval == 0; |
6a9062f3 | 467 | struct usb_hcd *hcd = ohci_to_hcd(ohci); |
1da177e4 LT |
468 | |
469 | disable (ohci); | |
470 | ||
471 | /* boot firmware should have set this up (5.1.1.3.1) */ | |
472 | if (first) { | |
473 | ||
474 | temp = ohci_readl (ohci, &ohci->regs->fminterval); | |
475 | ohci->fminterval = temp & 0x3fff; | |
476 | if (ohci->fminterval != FI) | |
477 | ohci_dbg (ohci, "fminterval delta %d\n", | |
478 | ohci->fminterval - FI); | |
479 | ohci->fminterval |= FSMP (ohci->fminterval) << 16; | |
480 | /* also: power/overcurrent flags in roothub.a */ | |
481 | } | |
482 | ||
dd9048af | 483 | /* Reset USB nearly "by the book". RemoteWakeupConnected was |
6a9062f3 DB |
484 | * saved if boot firmware (BIOS/SMM/...) told us it's connected, |
485 | * or if bus glue did the same (e.g. for PCI add-in cards with | |
486 | * PCI PM support). | |
1da177e4 | 487 | */ |
6a9062f3 DB |
488 | if ((ohci->hc_control & OHCI_CTRL_RWC) != 0 |
489 | && !device_may_wakeup(hcd->self.controller)) | |
490 | device_init_wakeup(hcd->self.controller, 1); | |
1da177e4 LT |
491 | |
492 | switch (ohci->hc_control & OHCI_CTRL_HCFS) { | |
493 | case OHCI_USB_OPER: | |
494 | temp = 0; | |
495 | break; | |
496 | case OHCI_USB_SUSPEND: | |
497 | case OHCI_USB_RESUME: | |
498 | ohci->hc_control &= OHCI_CTRL_RWC; | |
499 | ohci->hc_control |= OHCI_USB_RESUME; | |
500 | temp = 10 /* msec wait */; | |
501 | break; | |
502 | // case OHCI_USB_RESET: | |
503 | default: | |
504 | ohci->hc_control &= OHCI_CTRL_RWC; | |
505 | ohci->hc_control |= OHCI_USB_RESET; | |
506 | temp = 50 /* msec wait */; | |
507 | break; | |
508 | } | |
509 | ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); | |
510 | // flush the writes | |
511 | (void) ohci_readl (ohci, &ohci->regs->control); | |
512 | msleep(temp); | |
513 | temp = roothub_a (ohci); | |
514 | if (!(temp & RH_A_NPS)) { | |
1da177e4 | 515 | /* power down each port */ |
fdd13b36 | 516 | for (temp = 0; temp < ohci->num_ports; temp++) |
1da177e4 LT |
517 | ohci_writel (ohci, RH_PS_LSDA, |
518 | &ohci->regs->roothub.portstatus [temp]); | |
519 | } | |
520 | // flush those writes | |
521 | (void) ohci_readl (ohci, &ohci->regs->control); | |
522 | memset (ohci->hcca, 0, sizeof (struct ohci_hcca)); | |
523 | ||
524 | /* 2msec timelimit here means no irqs/preempt */ | |
525 | spin_lock_irq (&ohci->lock); | |
526 | ||
527 | retry: | |
528 | /* HC Reset requires max 10 us delay */ | |
529 | ohci_writel (ohci, OHCI_HCR, &ohci->regs->cmdstatus); | |
530 | temp = 30; /* ... allow extra time */ | |
531 | while ((ohci_readl (ohci, &ohci->regs->cmdstatus) & OHCI_HCR) != 0) { | |
532 | if (--temp == 0) { | |
533 | spin_unlock_irq (&ohci->lock); | |
534 | ohci_err (ohci, "USB HC reset timed out!\n"); | |
535 | return -1; | |
536 | } | |
537 | udelay (1); | |
538 | } | |
539 | ||
540 | /* now we're in the SUSPEND state ... must go OPERATIONAL | |
541 | * within 2msec else HC enters RESUME | |
542 | * | |
543 | * ... but some hardware won't init fmInterval "by the book" | |
544 | * (SiS, OPTi ...), so reset again instead. SiS doesn't need | |
545 | * this if we write fmInterval after we're OPERATIONAL. | |
546 | * Unclear about ALi, ServerWorks, and others ... this could | |
547 | * easily be a longstanding bug in chip init on Linux. | |
548 | */ | |
549 | if (ohci->flags & OHCI_QUIRK_INITRESET) { | |
550 | ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); | |
551 | // flush those writes | |
552 | (void) ohci_readl (ohci, &ohci->regs->control); | |
553 | } | |
554 | ||
555 | /* Tell the controller where the control and bulk lists are | |
556 | * The lists are empty now. */ | |
557 | ohci_writel (ohci, 0, &ohci->regs->ed_controlhead); | |
558 | ohci_writel (ohci, 0, &ohci->regs->ed_bulkhead); | |
559 | ||
560 | /* a reset clears this */ | |
561 | ohci_writel (ohci, (u32) ohci->hcca_dma, &ohci->regs->hcca); | |
562 | ||
563 | periodic_reinit (ohci); | |
564 | ||
565 | /* some OHCI implementations are finicky about how they init. | |
566 | * bogus values here mean not even enumeration could work. | |
567 | */ | |
568 | if ((ohci_readl (ohci, &ohci->regs->fminterval) & 0x3fff0000) == 0 | |
569 | || !ohci_readl (ohci, &ohci->regs->periodicstart)) { | |
570 | if (!(ohci->flags & OHCI_QUIRK_INITRESET)) { | |
571 | ohci->flags |= OHCI_QUIRK_INITRESET; | |
572 | ohci_dbg (ohci, "enabling initreset quirk\n"); | |
573 | goto retry; | |
574 | } | |
575 | spin_unlock_irq (&ohci->lock); | |
576 | ohci_err (ohci, "init err (%08x %04x)\n", | |
577 | ohci_readl (ohci, &ohci->regs->fminterval), | |
578 | ohci_readl (ohci, &ohci->regs->periodicstart)); | |
579 | return -EOVERFLOW; | |
580 | } | |
581 | ||
d413984a DB |
582 | /* use rhsc irqs after khubd is fully initialized */ |
583 | hcd->poll_rh = 1; | |
584 | hcd->uses_new_polling = 1; | |
585 | ||
586 | /* start controller operations */ | |
1da177e4 | 587 | ohci->hc_control &= OHCI_CTRL_RWC; |
d413984a DB |
588 | ohci->hc_control |= OHCI_CONTROL_INIT | OHCI_USB_OPER; |
589 | ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); | |
6a9062f3 | 590 | hcd->state = HC_STATE_RUNNING; |
1da177e4 LT |
591 | |
592 | /* wake on ConnectStatusChange, matching external hubs */ | |
593 | ohci_writel (ohci, RH_HS_DRWE, &ohci->regs->roothub.status); | |
594 | ||
595 | /* Choose the interrupts we care about now, others later on demand */ | |
596 | mask = OHCI_INTR_INIT; | |
d413984a | 597 | ohci_writel (ohci, ~0, &ohci->regs->intrstatus); |
1da177e4 LT |
598 | ohci_writel (ohci, mask, &ohci->regs->intrenable); |
599 | ||
600 | /* handle root hub init quirks ... */ | |
601 | temp = roothub_a (ohci); | |
602 | temp &= ~(RH_A_PSM | RH_A_OCPM); | |
603 | if (ohci->flags & OHCI_QUIRK_SUPERIO) { | |
604 | /* NSC 87560 and maybe others */ | |
605 | temp |= RH_A_NOCP; | |
606 | temp &= ~(RH_A_POTPGT | RH_A_NPS); | |
607 | ohci_writel (ohci, temp, &ohci->regs->roothub.a); | |
608 | } else if ((ohci->flags & OHCI_QUIRK_AMD756) || distrust_firmware) { | |
609 | /* hub power always on; required for AMD-756 and some | |
610 | * Mac platforms. ganged overcurrent reporting, if any. | |
611 | */ | |
612 | temp |= RH_A_NPS; | |
613 | ohci_writel (ohci, temp, &ohci->regs->roothub.a); | |
614 | } | |
615 | ohci_writel (ohci, RH_HS_LPSC, &ohci->regs->roothub.status); | |
616 | ohci_writel (ohci, (temp & RH_A_NPS) ? 0 : RH_B_PPCM, | |
617 | &ohci->regs->roothub.b); | |
618 | // flush those writes | |
619 | (void) ohci_readl (ohci, &ohci->regs->control); | |
620 | ||
d413984a | 621 | ohci->next_statechange = jiffies + STATECHANGE_DELAY; |
1da177e4 LT |
622 | spin_unlock_irq (&ohci->lock); |
623 | ||
624 | // POTPGT delay is bits 24-31, in 2 ms units. | |
625 | mdelay ((temp >> 23) & 0x1fe); | |
6a9062f3 | 626 | hcd->state = HC_STATE_RUNNING; |
1da177e4 LT |
627 | |
628 | ohci_dump (ohci, 1); | |
629 | ||
1da177e4 LT |
630 | return 0; |
631 | } | |
632 | ||
633 | /*-------------------------------------------------------------------------*/ | |
634 | ||
635 | /* an interrupt happens */ | |
636 | ||
7d12e780 | 637 | static irqreturn_t ohci_irq (struct usb_hcd *hcd) |
1da177e4 LT |
638 | { |
639 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); | |
640 | struct ohci_regs __iomem *regs = ohci->regs; | |
641 | int ints; | |
642 | ||
643 | /* we can eliminate a (slow) ohci_readl() | |
644 | if _only_ WDH caused this irq */ | |
645 | if ((ohci->hcca->done_head != 0) | |
646 | && ! (hc32_to_cpup (ohci, &ohci->hcca->done_head) | |
647 | & 0x01)) { | |
648 | ints = OHCI_INTR_WDH; | |
649 | ||
650 | /* cardbus/... hardware gone before remove() */ | |
651 | } else if ((ints = ohci_readl (ohci, ®s->intrstatus)) == ~(u32)0) { | |
652 | disable (ohci); | |
653 | ohci_dbg (ohci, "device removed!\n"); | |
654 | return IRQ_HANDLED; | |
655 | ||
656 | /* interrupt for some other device? */ | |
657 | } else if ((ints &= ohci_readl (ohci, ®s->intrenable)) == 0) { | |
658 | return IRQ_NOTMINE; | |
d413984a DB |
659 | } |
660 | ||
1da177e4 LT |
661 | if (ints & OHCI_INTR_UE) { |
662 | disable (ohci); | |
663 | ohci_err (ohci, "OHCI Unrecoverable Error, disabled\n"); | |
664 | // e.g. due to PCI Master/Target Abort | |
665 | ||
666 | ohci_dump (ohci, 1); | |
667 | ohci_usb_reset (ohci); | |
668 | } | |
669 | ||
583ceada AS |
670 | if (ints & OHCI_INTR_RHSC) { |
671 | ohci_vdbg(ohci, "rhsc\n"); | |
672 | ohci->next_statechange = jiffies + STATECHANGE_DELAY; | |
673 | ohci_writel(ohci, OHCI_INTR_RD | OHCI_INTR_RHSC, | |
674 | ®s->intrstatus); | |
052ac01a AS |
675 | |
676 | /* NOTE: Vendors didn't always make the same implementation | |
677 | * choices for RHSC. Many followed the spec; RHSC triggers | |
678 | * on an edge, like setting and maybe clearing a port status | |
679 | * change bit. With others it's level-triggered, active | |
680 | * until khubd clears all the port status change bits. We'll | |
681 | * always disable it here and rely on polling until khubd | |
682 | * re-enables it. | |
683 | */ | |
684 | ohci_writel(ohci, OHCI_INTR_RHSC, ®s->intrdisable); | |
583ceada AS |
685 | usb_hcd_poll_rh_status(hcd); |
686 | } | |
687 | ||
688 | /* For connect and disconnect events, we expect the controller | |
689 | * to turn on RHSC along with RD. But for remote wakeup events | |
690 | * this might not happen. | |
691 | */ | |
692 | else if (ints & OHCI_INTR_RD) { | |
693 | ohci_vdbg(ohci, "resume detect\n"); | |
694 | ohci_writel(ohci, OHCI_INTR_RD, ®s->intrstatus); | |
8d1a243b AS |
695 | hcd->poll_rh = 1; |
696 | if (ohci->autostop) { | |
697 | spin_lock (&ohci->lock); | |
698 | ohci_rh_resume (ohci); | |
699 | spin_unlock (&ohci->lock); | |
700 | } else | |
f197b2c5 | 701 | usb_hcd_resume_root_hub(hcd); |
1da177e4 LT |
702 | } |
703 | ||
704 | if (ints & OHCI_INTR_WDH) { | |
705 | if (HC_IS_RUNNING(hcd->state)) | |
8d1a243b | 706 | ohci_writel (ohci, OHCI_INTR_WDH, ®s->intrdisable); |
1da177e4 | 707 | spin_lock (&ohci->lock); |
7d12e780 | 708 | dl_done_list (ohci); |
1da177e4 LT |
709 | spin_unlock (&ohci->lock); |
710 | if (HC_IS_RUNNING(hcd->state)) | |
dd9048af | 711 | ohci_writel (ohci, OHCI_INTR_WDH, ®s->intrenable); |
1da177e4 | 712 | } |
dd9048af | 713 | |
1da177e4 LT |
714 | /* could track INTR_SO to reduce available PCI/... bandwidth */ |
715 | ||
716 | /* handle any pending URB/ED unlinks, leaving INTR_SF enabled | |
717 | * when there's still unlinking to be done (next frame). | |
718 | */ | |
719 | spin_lock (&ohci->lock); | |
720 | if (ohci->ed_rm_list) | |
7d12e780 | 721 | finish_unlinks (ohci, ohci_frame_no(ohci)); |
1da177e4 LT |
722 | if ((ints & OHCI_INTR_SF) != 0 && !ohci->ed_rm_list |
723 | && HC_IS_RUNNING(hcd->state)) | |
dd9048af | 724 | ohci_writel (ohci, OHCI_INTR_SF, ®s->intrdisable); |
1da177e4 LT |
725 | spin_unlock (&ohci->lock); |
726 | ||
727 | if (HC_IS_RUNNING(hcd->state)) { | |
728 | ohci_writel (ohci, ints, ®s->intrstatus); | |
dd9048af | 729 | ohci_writel (ohci, OHCI_INTR_MIE, ®s->intrenable); |
1da177e4 LT |
730 | // flush those writes |
731 | (void) ohci_readl (ohci, &ohci->regs->control); | |
732 | } | |
733 | ||
734 | return IRQ_HANDLED; | |
735 | } | |
736 | ||
737 | /*-------------------------------------------------------------------------*/ | |
738 | ||
739 | static void ohci_stop (struct usb_hcd *hcd) | |
dd9048af | 740 | { |
1da177e4 LT |
741 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); |
742 | ||
1da177e4 LT |
743 | ohci_dump (ohci, 1); |
744 | ||
745 | flush_scheduled_work(); | |
746 | ||
747 | ohci_usb_reset (ohci); | |
748 | ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable); | |
71795c1d PZ |
749 | free_irq(hcd->irq, hcd); |
750 | hcd->irq = -1; | |
751 | ||
1da177e4 LT |
752 | remove_debug_files (ohci); |
753 | ohci_mem_cleanup (ohci); | |
754 | if (ohci->hcca) { | |
dd9048af DB |
755 | dma_free_coherent (hcd->self.controller, |
756 | sizeof *ohci->hcca, | |
1da177e4 LT |
757 | ohci->hcca, ohci->hcca_dma); |
758 | ohci->hcca = NULL; | |
759 | ohci->hcca_dma = 0; | |
760 | } | |
761 | } | |
762 | ||
763 | /*-------------------------------------------------------------------------*/ | |
764 | ||
765 | /* must not be called from interrupt context */ | |
766 | ||
8ad7fe16 | 767 | #ifdef CONFIG_PM |
1da177e4 LT |
768 | |
769 | static int ohci_restart (struct ohci_hcd *ohci) | |
770 | { | |
771 | int temp; | |
772 | int i; | |
773 | struct urb_priv *priv; | |
1da177e4 LT |
774 | |
775 | /* mark any devices gone, so they do nothing till khubd disconnects. | |
776 | * recycle any "live" eds/tds (and urbs) right away. | |
777 | * later, khubd disconnect processing will recycle the other state, | |
778 | * (either as disconnect/reconnect, or maybe someday as a reset). | |
dd9048af | 779 | */ |
1da177e4 LT |
780 | spin_lock_irq(&ohci->lock); |
781 | disable (ohci); | |
1c50c317 | 782 | usb_root_hub_lost_power(ohci_to_hcd(ohci)->self.root_hub); |
1da177e4 LT |
783 | if (!list_empty (&ohci->pending)) |
784 | ohci_dbg(ohci, "abort schedule...\n"); | |
785 | list_for_each_entry (priv, &ohci->pending, pending) { | |
786 | struct urb *urb = priv->td[0]->urb; | |
787 | struct ed *ed = priv->ed; | |
788 | ||
789 | switch (ed->state) { | |
790 | case ED_OPER: | |
791 | ed->state = ED_UNLINK; | |
792 | ed->hwINFO |= cpu_to_hc32(ohci, ED_DEQUEUE); | |
793 | ed_deschedule (ohci, ed); | |
794 | ||
795 | ed->ed_next = ohci->ed_rm_list; | |
796 | ed->ed_prev = NULL; | |
797 | ohci->ed_rm_list = ed; | |
798 | /* FALLTHROUGH */ | |
799 | case ED_UNLINK: | |
800 | break; | |
801 | default: | |
802 | ohci_dbg(ohci, "bogus ed %p state %d\n", | |
803 | ed, ed->state); | |
804 | } | |
805 | ||
806 | spin_lock (&urb->lock); | |
807 | urb->status = -ESHUTDOWN; | |
808 | spin_unlock (&urb->lock); | |
809 | } | |
7d12e780 | 810 | finish_unlinks (ohci, 0); |
1da177e4 LT |
811 | spin_unlock_irq(&ohci->lock); |
812 | ||
813 | /* paranoia, in case that didn't work: */ | |
814 | ||
815 | /* empty the interrupt branches */ | |
816 | for (i = 0; i < NUM_INTS; i++) ohci->load [i] = 0; | |
817 | for (i = 0; i < NUM_INTS; i++) ohci->hcca->int_table [i] = 0; | |
dd9048af | 818 | |
1da177e4 LT |
819 | /* no EDs to remove */ |
820 | ohci->ed_rm_list = NULL; | |
821 | ||
dd9048af | 822 | /* empty control and bulk lists */ |
1da177e4 LT |
823 | ohci->ed_controltail = NULL; |
824 | ohci->ed_bulktail = NULL; | |
825 | ||
826 | if ((temp = ohci_run (ohci)) < 0) { | |
827 | ohci_err (ohci, "can't restart, %d\n", temp); | |
828 | return temp; | |
829 | } else { | |
830 | /* here we "know" root ports should always stay powered, | |
831 | * and that if we try to turn them back on the root hub | |
832 | * will respond to CSC processing. | |
833 | */ | |
fdd13b36 | 834 | i = ohci->num_ports; |
1da177e4 LT |
835 | while (i--) |
836 | ohci_writel (ohci, RH_PS_PSS, | |
839ab1d4 | 837 | &ohci->regs->roothub.portstatus [i]); |
1da177e4 LT |
838 | ohci_dbg (ohci, "restart complete\n"); |
839 | } | |
840 | return 0; | |
841 | } | |
842 | #endif | |
843 | ||
844 | /*-------------------------------------------------------------------------*/ | |
845 | ||
846 | #define DRIVER_INFO DRIVER_VERSION " " DRIVER_DESC | |
847 | ||
848 | MODULE_AUTHOR (DRIVER_AUTHOR); | |
849 | MODULE_DESCRIPTION (DRIVER_INFO); | |
850 | MODULE_LICENSE ("GPL"); | |
851 | ||
852 | #ifdef CONFIG_PCI | |
853 | #include "ohci-pci.c" | |
5e16fabe | 854 | #define PCI_DRIVER ohci_pci_driver |
1da177e4 LT |
855 | #endif |
856 | ||
857 | #ifdef CONFIG_SA1111 | |
858 | #include "ohci-sa1111.c" | |
5e16fabe | 859 | #define SA1111_DRIVER ohci_hcd_sa1111_driver |
1da177e4 LT |
860 | #endif |
861 | ||
3eb0c5f4 BD |
862 | #ifdef CONFIG_ARCH_S3C2410 |
863 | #include "ohci-s3c2410.c" | |
5e16fabe | 864 | #define PLATFORM_DRIVER ohci_hcd_s3c2410_driver |
3eb0c5f4 BD |
865 | #endif |
866 | ||
1da177e4 LT |
867 | #ifdef CONFIG_ARCH_OMAP |
868 | #include "ohci-omap.c" | |
5e16fabe | 869 | #define PLATFORM_DRIVER ohci_hcd_omap_driver |
1da177e4 LT |
870 | #endif |
871 | ||
872 | #ifdef CONFIG_ARCH_LH7A404 | |
873 | #include "ohci-lh7a404.c" | |
5e16fabe | 874 | #define PLATFORM_DRIVER ohci_hcd_lh7a404_driver |
1da177e4 LT |
875 | #endif |
876 | ||
877 | #ifdef CONFIG_PXA27x | |
878 | #include "ohci-pxa27x.c" | |
5e16fabe | 879 | #define PLATFORM_DRIVER ohci_hcd_pxa27x_driver |
1da177e4 LT |
880 | #endif |
881 | ||
a5b7474a LB |
882 | #ifdef CONFIG_ARCH_EP93XX |
883 | #include "ohci-ep93xx.c" | |
5e16fabe | 884 | #define PLATFORM_DRIVER ohci_hcd_ep93xx_driver |
a5b7474a LB |
885 | #endif |
886 | ||
1da177e4 LT |
887 | #ifdef CONFIG_SOC_AU1X00 |
888 | #include "ohci-au1xxx.c" | |
5e16fabe | 889 | #define PLATFORM_DRIVER ohci_hcd_au1xxx_driver |
1da177e4 LT |
890 | #endif |
891 | ||
5151d040 VW |
892 | #ifdef CONFIG_PNX8550 |
893 | #include "ohci-pnx8550.c" | |
5e16fabe | 894 | #define PLATFORM_DRIVER ohci_hcd_pnx8550_driver |
5151d040 VW |
895 | #endif |
896 | ||
1da177e4 LT |
897 | #ifdef CONFIG_USB_OHCI_HCD_PPC_SOC |
898 | #include "ohci-ppc-soc.c" | |
5e16fabe | 899 | #define PLATFORM_DRIVER ohci_hcd_ppc_soc_driver |
1da177e4 LT |
900 | #endif |
901 | ||
58a0cd78 | 902 | #ifdef CONFIG_ARCH_AT91 |
39a269c0 | 903 | #include "ohci-at91.c" |
5e16fabe | 904 | #define PLATFORM_DRIVER ohci_hcd_at91_driver |
39a269c0 AV |
905 | #endif |
906 | ||
60bbfc84 VW |
907 | #ifdef CONFIG_ARCH_PNX4008 |
908 | #include "ohci-pnx4008.c" | |
5e16fabe | 909 | #define PLATFORM_DRIVER usb_hcd_pnx4008_driver |
60bbfc84 VW |
910 | #endif |
911 | ||
5e16fabe | 912 | |
495a678f SM |
913 | #ifdef CONFIG_USB_OHCI_HCD_PPC_OF |
914 | #include "ohci-ppc-of.c" | |
915 | #define OF_PLATFORM_DRIVER ohci_hcd_ppc_of_driver | |
916 | #endif | |
917 | ||
6a6c957e GL |
918 | #ifdef CONFIG_PPC_PS3 |
919 | #include "ohci-ps3.c" | |
920 | #define PS3_SYSTEM_BUS_DRIVER ps3_ohci_sb_driver | |
921 | #endif | |
922 | ||
5e16fabe SM |
923 | #if !defined(PCI_DRIVER) && \ |
924 | !defined(PLATFORM_DRIVER) && \ | |
495a678f | 925 | !defined(OF_PLATFORM_DRIVER) && \ |
6a6c957e GL |
926 | !defined(SA1111_DRIVER) && \ |
927 | !defined(PS3_SYSTEM_BUS_DRIVER) | |
1da177e4 LT |
928 | #error "missing bus glue for ohci-hcd" |
929 | #endif | |
5e16fabe SM |
930 | |
931 | static int __init ohci_hcd_mod_init(void) | |
932 | { | |
933 | int retval = 0; | |
5e16fabe SM |
934 | |
935 | if (usb_disabled()) | |
936 | return -ENODEV; | |
937 | ||
938 | printk (KERN_DEBUG "%s: " DRIVER_INFO "\n", hcd_name); | |
939 | pr_debug ("%s: block sizes: ed %Zd td %Zd\n", hcd_name, | |
940 | sizeof (struct ed), sizeof (struct td)); | |
941 | ||
6a6c957e | 942 | #ifdef PS3_SYSTEM_BUS_DRIVER |
48fda451 IK |
943 | if (firmware_has_feature(FW_FEATURE_PS3_LV1)) { |
944 | retval = ps3_system_bus_driver_register( | |
945 | &PS3_SYSTEM_BUS_DRIVER); | |
946 | if (retval < 0) | |
947 | goto error_ps3; | |
948 | } | |
6a6c957e GL |
949 | #endif |
950 | ||
5e16fabe SM |
951 | #ifdef PLATFORM_DRIVER |
952 | retval = platform_driver_register(&PLATFORM_DRIVER); | |
953 | if (retval < 0) | |
de44743b | 954 | goto error_platform; |
5e16fabe SM |
955 | #endif |
956 | ||
495a678f SM |
957 | #ifdef OF_PLATFORM_DRIVER |
958 | retval = of_register_platform_driver(&OF_PLATFORM_DRIVER); | |
959 | if (retval < 0) | |
de44743b | 960 | goto error_of_platform; |
495a678f SM |
961 | #endif |
962 | ||
5e16fabe SM |
963 | #ifdef SA1111_DRIVER |
964 | retval = sa1111_driver_register(&SA1111_DRIVER); | |
965 | if (retval < 0) | |
de44743b | 966 | goto error_sa1111; |
5e16fabe SM |
967 | #endif |
968 | ||
969 | #ifdef PCI_DRIVER | |
970 | retval = pci_register_driver(&PCI_DRIVER); | |
971 | if (retval < 0) | |
de44743b | 972 | goto error_pci; |
5e16fabe SM |
973 | #endif |
974 | ||
975 | return retval; | |
976 | ||
977 | /* Error path */ | |
de44743b BH |
978 | #ifdef PCI_DRIVER |
979 | error_pci: | |
980 | #endif | |
981 | #ifdef SA1111_DRIVER | |
982 | sa1111_driver_unregister(&SA1111_DRIVER); | |
983 | error_sa1111: | |
5e16fabe | 984 | #endif |
495a678f | 985 | #ifdef OF_PLATFORM_DRIVER |
de44743b BH |
986 | of_unregister_platform_driver(&OF_PLATFORM_DRIVER); |
987 | error_of_platform: | |
495a678f | 988 | #endif |
de44743b BH |
989 | #ifdef PLATFORM_DRIVER |
990 | platform_driver_unregister(&PLATFORM_DRIVER); | |
991 | error_platform: | |
6a6c957e GL |
992 | #endif |
993 | #ifdef PS3_SYSTEM_BUS_DRIVER | |
48fda451 IK |
994 | if (firmware_has_feature(FW_FEATURE_PS3_LV1)) |
995 | ps3_system_bus_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); | |
6a6c957e | 996 | error_ps3: |
5e16fabe SM |
997 | #endif |
998 | return retval; | |
999 | } | |
1000 | module_init(ohci_hcd_mod_init); | |
1001 | ||
1002 | static void __exit ohci_hcd_mod_exit(void) | |
1003 | { | |
1004 | #ifdef PCI_DRIVER | |
1005 | pci_unregister_driver(&PCI_DRIVER); | |
1006 | #endif | |
1007 | #ifdef SA1111_DRIVER | |
1008 | sa1111_driver_unregister(&SA1111_DRIVER); | |
1009 | #endif | |
495a678f SM |
1010 | #ifdef OF_PLATFORM_DRIVER |
1011 | of_unregister_platform_driver(&OF_PLATFORM_DRIVER); | |
1012 | #endif | |
5e16fabe SM |
1013 | #ifdef PLATFORM_DRIVER |
1014 | platform_driver_unregister(&PLATFORM_DRIVER); | |
1015 | #endif | |
6a6c957e | 1016 | #ifdef PS3_SYSTEM_BUS_DRIVER |
48fda451 IK |
1017 | if (firmware_has_feature(FW_FEATURE_PS3_LV1)) |
1018 | ps3_system_bus_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); | |
6a6c957e | 1019 | #endif |
5e16fabe SM |
1020 | } |
1021 | module_exit(ohci_hcd_mod_exit); | |
1022 |