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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * OHCI HCD (Host Controller Driver) for USB. | |
3 | * | |
4 | * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at> | |
5 | * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net> | |
dd9048af | 6 | * |
1da177e4 LT |
7 | * [ Initialisation is based on Linus' ] |
8 | * [ uhci code and gregs ohci fragments ] | |
9 | * [ (C) Copyright 1999 Linus Torvalds ] | |
10 | * [ (C) Copyright 1999 Gregory P. Smith] | |
dd9048af DB |
11 | * |
12 | * | |
1da177e4 LT |
13 | * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller |
14 | * interfaces (though some non-x86 Intel chips use it). It supports | |
15 | * smarter hardware than UHCI. A download link for the spec available | |
16 | * through the http://www.usb.org website. | |
17 | * | |
1da177e4 LT |
18 | * This file is licenced under the GPL. |
19 | */ | |
dd9048af | 20 | |
1da177e4 LT |
21 | #include <linux/module.h> |
22 | #include <linux/moduleparam.h> | |
23 | #include <linux/pci.h> | |
24 | #include <linux/kernel.h> | |
25 | #include <linux/delay.h> | |
26 | #include <linux/ioport.h> | |
27 | #include <linux/sched.h> | |
28 | #include <linux/slab.h> | |
1da177e4 LT |
29 | #include <linux/errno.h> |
30 | #include <linux/init.h> | |
31 | #include <linux/timer.h> | |
32 | #include <linux/list.h> | |
1da177e4 | 33 | #include <linux/usb.h> |
3a16f7b4 | 34 | #include <linux/usb/otg.h> |
27729aad | 35 | #include <linux/usb/hcd.h> |
dd9048af | 36 | #include <linux/dma-mapping.h> |
f4df0e33 | 37 | #include <linux/dmapool.h> |
d576bb9f | 38 | #include <linux/workqueue.h> |
684c19e0 | 39 | #include <linux/debugfs.h> |
1da177e4 LT |
40 | |
41 | #include <asm/io.h> | |
42 | #include <asm/irq.h> | |
43 | #include <asm/system.h> | |
44 | #include <asm/unaligned.h> | |
45 | #include <asm/byteorder.h> | |
46 | ||
47 | ||
1da177e4 LT |
48 | #define DRIVER_AUTHOR "Roman Weissgaerber, David Brownell" |
49 | #define DRIVER_DESC "USB 1.1 'Open' Host Controller (OHCI) Driver" | |
50 | ||
51 | /*-------------------------------------------------------------------------*/ | |
52 | ||
8de98402 | 53 | #undef OHCI_VERBOSE_DEBUG /* not always helpful */ |
1da177e4 LT |
54 | |
55 | /* For initializing controller (mask in an HCFS mode too) */ | |
d413984a | 56 | #define OHCI_CONTROL_INIT OHCI_CTRL_CBSR |
1da177e4 | 57 | #define OHCI_INTR_INIT \ |
d413984a DB |
58 | (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE \ |
59 | | OHCI_INTR_RD | OHCI_INTR_WDH) | |
1da177e4 LT |
60 | |
61 | #ifdef __hppa__ | |
62 | /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */ | |
63 | #define IR_DISABLE | |
64 | #endif | |
65 | ||
66 | #ifdef CONFIG_ARCH_OMAP | |
67 | /* OMAP doesn't support IR (no SMM; not needed) */ | |
68 | #define IR_DISABLE | |
69 | #endif | |
70 | ||
71 | /*-------------------------------------------------------------------------*/ | |
72 | ||
73 | static const char hcd_name [] = "ohci_hcd"; | |
74 | ||
d413984a DB |
75 | #define STATECHANGE_DELAY msecs_to_jiffies(300) |
76 | ||
1da177e4 LT |
77 | #include "ohci.h" |
78 | ||
79 | static void ohci_dump (struct ohci_hcd *ohci, int verbose); | |
80 | static int ohci_init (struct ohci_hcd *ohci); | |
81 | static void ohci_stop (struct usb_hcd *hcd); | |
da6fb570 DB |
82 | |
83 | #if defined(CONFIG_PM) || defined(CONFIG_PCI) | |
d576bb9f | 84 | static int ohci_restart (struct ohci_hcd *ohci); |
da6fb570 | 85 | #endif |
1da177e4 | 86 | |
ab1666c1 LY |
87 | #ifdef CONFIG_PCI |
88 | static void quirk_amd_pll(int state); | |
89 | static void amd_iso_dev_put(void); | |
a1f17a87 | 90 | static void sb800_prefetch(struct ohci_hcd *ohci, int on); |
ab1666c1 LY |
91 | #else |
92 | static inline void quirk_amd_pll(int state) | |
93 | { | |
94 | return; | |
95 | } | |
96 | static inline void amd_iso_dev_put(void) | |
97 | { | |
98 | return; | |
99 | } | |
a1f17a87 LY |
100 | static inline void sb800_prefetch(struct ohci_hcd *ohci, int on) |
101 | { | |
102 | return; | |
103 | } | |
ab1666c1 LY |
104 | #endif |
105 | ||
106 | ||
1da177e4 LT |
107 | #include "ohci-hub.c" |
108 | #include "ohci-dbg.c" | |
109 | #include "ohci-mem.c" | |
110 | #include "ohci-q.c" | |
111 | ||
112 | ||
113 | /* | |
114 | * On architectures with edge-triggered interrupts we must never return | |
115 | * IRQ_NONE. | |
116 | */ | |
117 | #if defined(CONFIG_SA1111) /* ... or other edge-triggered systems */ | |
118 | #define IRQ_NOTMINE IRQ_HANDLED | |
119 | #else | |
120 | #define IRQ_NOTMINE IRQ_NONE | |
121 | #endif | |
122 | ||
123 | ||
124 | /* Some boards misreport power switching/overcurrent */ | |
125 | static int distrust_firmware = 1; | |
126 | module_param (distrust_firmware, bool, 0); | |
127 | MODULE_PARM_DESC (distrust_firmware, | |
128 | "true to distrust firmware power/overcurrent setup"); | |
129 | ||
130 | /* Some boards leave IR set wrongly, since they fail BIOS/SMM handshakes */ | |
131 | static int no_handshake = 0; | |
132 | module_param (no_handshake, bool, 0); | |
133 | MODULE_PARM_DESC (no_handshake, "true (not default) disables BIOS handshake"); | |
134 | ||
135 | /*-------------------------------------------------------------------------*/ | |
136 | ||
137 | /* | |
138 | * queue up an urb for anything except the root hub | |
139 | */ | |
140 | static int ohci_urb_enqueue ( | |
141 | struct usb_hcd *hcd, | |
1da177e4 | 142 | struct urb *urb, |
55016f10 | 143 | gfp_t mem_flags |
1da177e4 LT |
144 | ) { |
145 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); | |
146 | struct ed *ed; | |
147 | urb_priv_t *urb_priv; | |
148 | unsigned int pipe = urb->pipe; | |
149 | int i, size = 0; | |
150 | unsigned long flags; | |
151 | int retval = 0; | |
dd9048af | 152 | |
1da177e4 | 153 | #ifdef OHCI_VERBOSE_DEBUG |
55d84968 | 154 | urb_print(urb, "SUB", usb_pipein(pipe), -EINPROGRESS); |
1da177e4 | 155 | #endif |
dd9048af | 156 | |
1da177e4 | 157 | /* every endpoint has a ed, locate and maybe (re)initialize it */ |
e9df41c5 | 158 | if (! (ed = ed_get (ohci, urb->ep, urb->dev, pipe, urb->interval))) |
1da177e4 LT |
159 | return -ENOMEM; |
160 | ||
161 | /* for the private part of the URB we need the number of TDs (size) */ | |
162 | switch (ed->type) { | |
163 | case PIPE_CONTROL: | |
164 | /* td_submit_urb() doesn't yet handle these */ | |
165 | if (urb->transfer_buffer_length > 4096) | |
166 | return -EMSGSIZE; | |
167 | ||
168 | /* 1 TD for setup, 1 for ACK, plus ... */ | |
169 | size = 2; | |
170 | /* FALLTHROUGH */ | |
171 | // case PIPE_INTERRUPT: | |
172 | // case PIPE_BULK: | |
173 | default: | |
174 | /* one TD for every 4096 Bytes (can be upto 8K) */ | |
175 | size += urb->transfer_buffer_length / 4096; | |
176 | /* ... and for any remaining bytes ... */ | |
177 | if ((urb->transfer_buffer_length % 4096) != 0) | |
178 | size++; | |
179 | /* ... and maybe a zero length packet to wrap it up */ | |
180 | if (size == 0) | |
181 | size++; | |
182 | else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0 | |
183 | && (urb->transfer_buffer_length | |
184 | % usb_maxpacket (urb->dev, pipe, | |
185 | usb_pipeout (pipe))) == 0) | |
186 | size++; | |
187 | break; | |
188 | case PIPE_ISOCHRONOUS: /* number of packets from URB */ | |
189 | size = urb->number_of_packets; | |
190 | break; | |
191 | } | |
192 | ||
193 | /* allocate the private part of the URB */ | |
dd00cc48 | 194 | urb_priv = kzalloc (sizeof (urb_priv_t) + size * sizeof (struct td *), |
1da177e4 LT |
195 | mem_flags); |
196 | if (!urb_priv) | |
197 | return -ENOMEM; | |
1da177e4 LT |
198 | INIT_LIST_HEAD (&urb_priv->pending); |
199 | urb_priv->length = size; | |
dd9048af | 200 | urb_priv->ed = ed; |
1da177e4 LT |
201 | |
202 | /* allocate the TDs (deferring hash chain updates) */ | |
203 | for (i = 0; i < size; i++) { | |
204 | urb_priv->td [i] = td_alloc (ohci, mem_flags); | |
205 | if (!urb_priv->td [i]) { | |
206 | urb_priv->length = i; | |
207 | urb_free_priv (ohci, urb_priv); | |
208 | return -ENOMEM; | |
209 | } | |
dd9048af | 210 | } |
1da177e4 LT |
211 | |
212 | spin_lock_irqsave (&ohci->lock, flags); | |
213 | ||
214 | /* don't submit to a dead HC */ | |
541c7d43 | 215 | if (!HCD_HW_ACCESSIBLE(hcd)) { |
8de98402 BH |
216 | retval = -ENODEV; |
217 | goto fail; | |
218 | } | |
1da177e4 LT |
219 | if (!HC_IS_RUNNING(hcd->state)) { |
220 | retval = -ENODEV; | |
221 | goto fail; | |
222 | } | |
e9df41c5 AS |
223 | retval = usb_hcd_link_urb_to_ep(hcd, urb); |
224 | if (retval) | |
1da177e4 | 225 | goto fail; |
1da177e4 LT |
226 | |
227 | /* schedule the ed if needed */ | |
228 | if (ed->state == ED_IDLE) { | |
229 | retval = ed_schedule (ohci, ed); | |
e9df41c5 AS |
230 | if (retval < 0) { |
231 | usb_hcd_unlink_urb_from_ep(hcd, urb); | |
232 | goto fail; | |
233 | } | |
1da177e4 LT |
234 | if (ed->type == PIPE_ISOCHRONOUS) { |
235 | u16 frame = ohci_frame_no(ohci); | |
236 | ||
237 | /* delay a few frames before the first TD */ | |
238 | frame += max_t (u16, 8, ed->interval); | |
239 | frame &= ~(ed->interval - 1); | |
240 | frame |= ed->branch; | |
241 | urb->start_frame = frame; | |
242 | ||
243 | /* yes, only URB_ISO_ASAP is supported, and | |
244 | * urb->start_frame is never used as input. | |
245 | */ | |
246 | } | |
247 | } else if (ed->type == PIPE_ISOCHRONOUS) | |
248 | urb->start_frame = ed->last_iso + ed->interval; | |
249 | ||
250 | /* fill the TDs and link them to the ed; and | |
251 | * enable that part of the schedule, if needed | |
252 | * and update count of queued periodic urbs | |
253 | */ | |
254 | urb->hcpriv = urb_priv; | |
255 | td_submit_urb (ohci, urb); | |
256 | ||
1da177e4 LT |
257 | fail: |
258 | if (retval) | |
259 | urb_free_priv (ohci, urb_priv); | |
260 | spin_unlock_irqrestore (&ohci->lock, flags); | |
261 | return retval; | |
262 | } | |
263 | ||
264 | /* | |
55d84968 AS |
265 | * decouple the URB from the HC queues (TDs, urb_priv). |
266 | * reporting is always done | |
1da177e4 LT |
267 | * asynchronously, and we might be dealing with an urb that's |
268 | * partially transferred, or an ED with other urbs being unlinked. | |
269 | */ | |
e9df41c5 | 270 | static int ohci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) |
1da177e4 LT |
271 | { |
272 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); | |
273 | unsigned long flags; | |
e9df41c5 | 274 | int rc; |
dd9048af | 275 | |
1da177e4 | 276 | #ifdef OHCI_VERBOSE_DEBUG |
55d84968 | 277 | urb_print(urb, "UNLINK", 1, status); |
dd9048af | 278 | #endif |
1da177e4 LT |
279 | |
280 | spin_lock_irqsave (&ohci->lock, flags); | |
e9df41c5 AS |
281 | rc = usb_hcd_check_unlink_urb(hcd, urb, status); |
282 | if (rc) { | |
283 | ; /* Do nothing */ | |
284 | } else if (HC_IS_RUNNING(hcd->state)) { | |
1da177e4 LT |
285 | urb_priv_t *urb_priv; |
286 | ||
287 | /* Unless an IRQ completed the unlink while it was being | |
288 | * handed to us, flag it for unlink and giveback, and force | |
289 | * some upcoming INTR_SF to call finish_unlinks() | |
290 | */ | |
291 | urb_priv = urb->hcpriv; | |
292 | if (urb_priv) { | |
293 | if (urb_priv->ed->state == ED_OPER) | |
294 | start_ed_unlink (ohci, urb_priv->ed); | |
295 | } | |
296 | } else { | |
297 | /* | |
298 | * with HC dead, we won't respect hc queue pointers | |
299 | * any more ... just clean up every urb's memory. | |
300 | */ | |
301 | if (urb->hcpriv) | |
55d84968 | 302 | finish_urb(ohci, urb, status); |
1da177e4 LT |
303 | } |
304 | spin_unlock_irqrestore (&ohci->lock, flags); | |
e9df41c5 | 305 | return rc; |
1da177e4 LT |
306 | } |
307 | ||
308 | /*-------------------------------------------------------------------------*/ | |
309 | ||
310 | /* frees config/altsetting state for endpoints, | |
311 | * including ED memory, dummy TD, and bulk/intr data toggle | |
312 | */ | |
313 | ||
314 | static void | |
315 | ohci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep) | |
316 | { | |
317 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); | |
318 | unsigned long flags; | |
319 | struct ed *ed = ep->hcpriv; | |
320 | unsigned limit = 1000; | |
321 | ||
322 | /* ASSERT: any requests/urbs are being unlinked */ | |
323 | /* ASSERT: nobody can be submitting urbs for this any more */ | |
324 | ||
325 | if (!ed) | |
326 | return; | |
327 | ||
328 | rescan: | |
329 | spin_lock_irqsave (&ohci->lock, flags); | |
330 | ||
331 | if (!HC_IS_RUNNING (hcd->state)) { | |
332 | sanitize: | |
333 | ed->state = ED_IDLE; | |
89a0fd18 MN |
334 | if (quirk_zfmicro(ohci) && ed->type == PIPE_INTERRUPT) |
335 | ohci->eds_scheduled--; | |
7d12e780 | 336 | finish_unlinks (ohci, 0); |
1da177e4 LT |
337 | } |
338 | ||
339 | switch (ed->state) { | |
340 | case ED_UNLINK: /* wait for hw to finish? */ | |
341 | /* major IRQ delivery trouble loses INTR_SF too... */ | |
342 | if (limit-- == 0) { | |
89a0fd18 MN |
343 | ohci_warn(ohci, "ED unlink timeout\n"); |
344 | if (quirk_zfmicro(ohci)) { | |
345 | ohci_warn(ohci, "Attempting ZF TD recovery\n"); | |
346 | ohci->ed_to_check = ed; | |
347 | ohci->zf_delay = 2; | |
348 | } | |
1da177e4 LT |
349 | goto sanitize; |
350 | } | |
351 | spin_unlock_irqrestore (&ohci->lock, flags); | |
22c43863 | 352 | schedule_timeout_uninterruptible(1); |
1da177e4 LT |
353 | goto rescan; |
354 | case ED_IDLE: /* fully unlinked */ | |
355 | if (list_empty (&ed->td_list)) { | |
356 | td_free (ohci, ed->dummy); | |
357 | ed_free (ohci, ed); | |
358 | break; | |
359 | } | |
360 | /* else FALL THROUGH */ | |
361 | default: | |
362 | /* caller was supposed to have unlinked any requests; | |
363 | * that's not our job. can't recover; must leak ed. | |
364 | */ | |
365 | ohci_err (ohci, "leak ed %p (#%02x) state %d%s\n", | |
366 | ed, ep->desc.bEndpointAddress, ed->state, | |
367 | list_empty (&ed->td_list) ? "" : " (has tds)"); | |
368 | td_free (ohci, ed->dummy); | |
369 | break; | |
370 | } | |
371 | ep->hcpriv = NULL; | |
372 | spin_unlock_irqrestore (&ohci->lock, flags); | |
1da177e4 LT |
373 | } |
374 | ||
375 | static int ohci_get_frame (struct usb_hcd *hcd) | |
376 | { | |
377 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); | |
378 | ||
379 | return ohci_frame_no(ohci); | |
380 | } | |
381 | ||
382 | static void ohci_usb_reset (struct ohci_hcd *ohci) | |
383 | { | |
384 | ohci->hc_control = ohci_readl (ohci, &ohci->regs->control); | |
385 | ohci->hc_control &= OHCI_CTRL_RWC; | |
386 | ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); | |
387 | } | |
388 | ||
64a21d02 | 389 | /* ohci_shutdown forcibly disables IRQs and DMA, helping kexec and |
f4df0e33 DB |
390 | * other cases where the next software may expect clean state from the |
391 | * "firmware". this is bus-neutral, unlike shutdown() methods. | |
392 | */ | |
64a21d02 AG |
393 | static void |
394 | ohci_shutdown (struct usb_hcd *hcd) | |
f4df0e33 DB |
395 | { |
396 | struct ohci_hcd *ohci; | |
397 | ||
64a21d02 | 398 | ohci = hcd_to_ohci (hcd); |
f4df0e33 | 399 | ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable); |
3df7169e AS |
400 | ohci->hc_control = ohci_readl(ohci, &ohci->regs->control); |
401 | ||
402 | /* If the SHUTDOWN quirk is set, don't put the controller in RESET */ | |
403 | ohci->hc_control &= (ohci->flags & OHCI_QUIRK_SHUTDOWN ? | |
404 | OHCI_CTRL_RWC | OHCI_CTRL_HCFS : | |
405 | OHCI_CTRL_RWC); | |
406 | ohci_writel(ohci, ohci->hc_control, &ohci->regs->control); | |
407 | ||
f4df0e33 DB |
408 | /* flush the writes */ |
409 | (void) ohci_readl (ohci, &ohci->regs->control); | |
f4df0e33 DB |
410 | } |
411 | ||
89a0fd18 MN |
412 | static int check_ed(struct ohci_hcd *ohci, struct ed *ed) |
413 | { | |
414 | return (hc32_to_cpu(ohci, ed->hwINFO) & ED_IN) != 0 | |
415 | && (hc32_to_cpu(ohci, ed->hwHeadP) & TD_MASK) | |
416 | == (hc32_to_cpu(ohci, ed->hwTailP) & TD_MASK) | |
417 | && !list_empty(&ed->td_list); | |
418 | } | |
419 | ||
420 | /* ZF Micro watchdog timer callback. The ZF Micro chipset sometimes completes | |
421 | * an interrupt TD but neglects to add it to the donelist. On systems with | |
422 | * this chipset, we need to periodically check the state of the queues to look | |
423 | * for such "lost" TDs. | |
424 | */ | |
425 | static void unlink_watchdog_func(unsigned long _ohci) | |
426 | { | |
da6fb570 | 427 | unsigned long flags; |
89a0fd18 MN |
428 | unsigned max; |
429 | unsigned seen_count = 0; | |
430 | unsigned i; | |
431 | struct ed **seen = NULL; | |
432 | struct ohci_hcd *ohci = (struct ohci_hcd *) _ohci; | |
433 | ||
434 | spin_lock_irqsave(&ohci->lock, flags); | |
435 | max = ohci->eds_scheduled; | |
436 | if (!max) | |
437 | goto done; | |
438 | ||
439 | if (ohci->ed_to_check) | |
440 | goto out; | |
441 | ||
442 | seen = kcalloc(max, sizeof *seen, GFP_ATOMIC); | |
443 | if (!seen) | |
444 | goto out; | |
445 | ||
446 | for (i = 0; i < NUM_INTS; i++) { | |
447 | struct ed *ed = ohci->periodic[i]; | |
448 | ||
449 | while (ed) { | |
450 | unsigned temp; | |
451 | ||
452 | /* scan this branch of the periodic schedule tree */ | |
453 | for (temp = 0; temp < seen_count; temp++) { | |
454 | if (seen[temp] == ed) { | |
455 | /* we've checked it and what's after */ | |
456 | ed = NULL; | |
457 | break; | |
458 | } | |
459 | } | |
460 | if (!ed) | |
461 | break; | |
462 | seen[seen_count++] = ed; | |
463 | if (!check_ed(ohci, ed)) { | |
464 | ed = ed->ed_next; | |
465 | continue; | |
466 | } | |
467 | ||
468 | /* HC's TD list is empty, but HCD sees at least one | |
469 | * TD that's not been sent through the donelist. | |
470 | */ | |
471 | ohci->ed_to_check = ed; | |
472 | ohci->zf_delay = 2; | |
473 | ||
474 | /* The HC may wait until the next frame to report the | |
475 | * TD as done through the donelist and INTR_WDH. (We | |
476 | * just *assume* it's not a multi-TD interrupt URB; | |
477 | * those could defer the IRQ more than one frame, using | |
478 | * DI...) Check again after the next INTR_SF. | |
479 | */ | |
480 | ohci_writel(ohci, OHCI_INTR_SF, | |
481 | &ohci->regs->intrstatus); | |
482 | ohci_writel(ohci, OHCI_INTR_SF, | |
483 | &ohci->regs->intrenable); | |
484 | ||
485 | /* flush those writes */ | |
486 | (void) ohci_readl(ohci, &ohci->regs->control); | |
487 | ||
488 | goto out; | |
489 | } | |
490 | } | |
491 | out: | |
492 | kfree(seen); | |
493 | if (ohci->eds_scheduled) | |
9cebcdc7 | 494 | mod_timer(&ohci->unlink_watchdog, round_jiffies(jiffies + HZ)); |
89a0fd18 MN |
495 | done: |
496 | spin_unlock_irqrestore(&ohci->lock, flags); | |
497 | } | |
498 | ||
1da177e4 LT |
499 | /*-------------------------------------------------------------------------* |
500 | * HC functions | |
501 | *-------------------------------------------------------------------------*/ | |
502 | ||
503 | /* init memory, and kick BIOS/SMM off */ | |
504 | ||
505 | static int ohci_init (struct ohci_hcd *ohci) | |
506 | { | |
507 | int ret; | |
6a9062f3 | 508 | struct usb_hcd *hcd = ohci_to_hcd(ohci); |
1da177e4 | 509 | |
1133cd8a DES |
510 | if (distrust_firmware) |
511 | ohci->flags |= OHCI_QUIRK_HUB_POWER; | |
512 | ||
1da177e4 | 513 | disable (ohci); |
6a9062f3 | 514 | ohci->regs = hcd->regs; |
1da177e4 | 515 | |
6a9062f3 DB |
516 | /* REVISIT this BIOS handshake is now moved into PCI "quirks", and |
517 | * was never needed for most non-PCI systems ... remove the code? | |
518 | */ | |
519 | ||
1da177e4 LT |
520 | #ifndef IR_DISABLE |
521 | /* SMM owns the HC? not for long! */ | |
522 | if (!no_handshake && ohci_readl (ohci, | |
523 | &ohci->regs->control) & OHCI_CTRL_IR) { | |
524 | u32 temp; | |
525 | ||
526 | ohci_dbg (ohci, "USB HC TakeOver from BIOS/SMM\n"); | |
527 | ||
528 | /* this timeout is arbitrary. we make it long, so systems | |
529 | * depending on usb keyboards may be usable even if the | |
530 | * BIOS/SMM code seems pretty broken. | |
531 | */ | |
532 | temp = 500; /* arbitrary: five seconds */ | |
533 | ||
534 | ohci_writel (ohci, OHCI_INTR_OC, &ohci->regs->intrenable); | |
535 | ohci_writel (ohci, OHCI_OCR, &ohci->regs->cmdstatus); | |
536 | while (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_IR) { | |
537 | msleep (10); | |
538 | if (--temp == 0) { | |
539 | ohci_err (ohci, "USB HC takeover failed!" | |
540 | " (BIOS/SMM bug)\n"); | |
541 | return -EBUSY; | |
542 | } | |
543 | } | |
544 | ohci_usb_reset (ohci); | |
545 | } | |
546 | #endif | |
547 | ||
548 | /* Disable HC interrupts */ | |
549 | ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable); | |
6a9062f3 DB |
550 | |
551 | /* flush the writes, and save key bits like RWC */ | |
552 | if (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_RWC) | |
553 | ohci->hc_control |= OHCI_CTRL_RWC; | |
1da177e4 | 554 | |
fdd13b36 DB |
555 | /* Read the number of ports unless overridden */ |
556 | if (ohci->num_ports == 0) | |
557 | ohci->num_ports = roothub_a(ohci) & RH_A_NDP; | |
558 | ||
1da177e4 LT |
559 | if (ohci->hcca) |
560 | return 0; | |
561 | ||
6a9062f3 | 562 | ohci->hcca = dma_alloc_coherent (hcd->self.controller, |
1da177e4 LT |
563 | sizeof *ohci->hcca, &ohci->hcca_dma, 0); |
564 | if (!ohci->hcca) | |
565 | return -ENOMEM; | |
566 | ||
567 | if ((ret = ohci_mem_init (ohci)) < 0) | |
6a9062f3 DB |
568 | ohci_stop (hcd); |
569 | else { | |
6a9062f3 DB |
570 | create_debug_files (ohci); |
571 | } | |
1da177e4 LT |
572 | |
573 | return ret; | |
1da177e4 LT |
574 | } |
575 | ||
576 | /*-------------------------------------------------------------------------*/ | |
577 | ||
578 | /* Start an OHCI controller, set the BUS operational | |
579 | * resets USB and controller | |
dd9048af | 580 | * enable interrupts |
1da177e4 LT |
581 | */ |
582 | static int ohci_run (struct ohci_hcd *ohci) | |
583 | { | |
96f90a8b | 584 | u32 mask, val; |
1da177e4 | 585 | int first = ohci->fminterval == 0; |
6a9062f3 | 586 | struct usb_hcd *hcd = ohci_to_hcd(ohci); |
1da177e4 LT |
587 | |
588 | disable (ohci); | |
589 | ||
590 | /* boot firmware should have set this up (5.1.1.3.1) */ | |
591 | if (first) { | |
592 | ||
96f90a8b HS |
593 | val = ohci_readl (ohci, &ohci->regs->fminterval); |
594 | ohci->fminterval = val & 0x3fff; | |
1da177e4 LT |
595 | if (ohci->fminterval != FI) |
596 | ohci_dbg (ohci, "fminterval delta %d\n", | |
597 | ohci->fminterval - FI); | |
598 | ohci->fminterval |= FSMP (ohci->fminterval) << 16; | |
599 | /* also: power/overcurrent flags in roothub.a */ | |
600 | } | |
601 | ||
6fd9086a AS |
602 | /* Reset USB nearly "by the book". RemoteWakeupConnected has |
603 | * to be checked in case boot firmware (BIOS/SMM/...) has set up | |
604 | * wakeup in a way the bus isn't aware of (e.g., legacy PCI PM). | |
605 | * If the bus glue detected wakeup capability then it should | |
bcca06ef | 606 | * already be enabled; if so we'll just enable it again. |
1da177e4 | 607 | */ |
bcca06ef AS |
608 | if ((ohci->hc_control & OHCI_CTRL_RWC) != 0) |
609 | device_set_wakeup_capable(hcd->self.controller, 1); | |
1da177e4 LT |
610 | |
611 | switch (ohci->hc_control & OHCI_CTRL_HCFS) { | |
612 | case OHCI_USB_OPER: | |
96f90a8b | 613 | val = 0; |
1da177e4 LT |
614 | break; |
615 | case OHCI_USB_SUSPEND: | |
616 | case OHCI_USB_RESUME: | |
617 | ohci->hc_control &= OHCI_CTRL_RWC; | |
618 | ohci->hc_control |= OHCI_USB_RESUME; | |
96f90a8b | 619 | val = 10 /* msec wait */; |
1da177e4 LT |
620 | break; |
621 | // case OHCI_USB_RESET: | |
622 | default: | |
623 | ohci->hc_control &= OHCI_CTRL_RWC; | |
624 | ohci->hc_control |= OHCI_USB_RESET; | |
96f90a8b | 625 | val = 50 /* msec wait */; |
1da177e4 LT |
626 | break; |
627 | } | |
628 | ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); | |
629 | // flush the writes | |
630 | (void) ohci_readl (ohci, &ohci->regs->control); | |
96f90a8b | 631 | msleep(val); |
383975d7 | 632 | |
1da177e4 LT |
633 | memset (ohci->hcca, 0, sizeof (struct ohci_hcca)); |
634 | ||
635 | /* 2msec timelimit here means no irqs/preempt */ | |
636 | spin_lock_irq (&ohci->lock); | |
637 | ||
638 | retry: | |
639 | /* HC Reset requires max 10 us delay */ | |
640 | ohci_writel (ohci, OHCI_HCR, &ohci->regs->cmdstatus); | |
96f90a8b | 641 | val = 30; /* ... allow extra time */ |
1da177e4 | 642 | while ((ohci_readl (ohci, &ohci->regs->cmdstatus) & OHCI_HCR) != 0) { |
96f90a8b | 643 | if (--val == 0) { |
1da177e4 LT |
644 | spin_unlock_irq (&ohci->lock); |
645 | ohci_err (ohci, "USB HC reset timed out!\n"); | |
646 | return -1; | |
647 | } | |
648 | udelay (1); | |
649 | } | |
650 | ||
651 | /* now we're in the SUSPEND state ... must go OPERATIONAL | |
652 | * within 2msec else HC enters RESUME | |
653 | * | |
654 | * ... but some hardware won't init fmInterval "by the book" | |
655 | * (SiS, OPTi ...), so reset again instead. SiS doesn't need | |
656 | * this if we write fmInterval after we're OPERATIONAL. | |
657 | * Unclear about ALi, ServerWorks, and others ... this could | |
658 | * easily be a longstanding bug in chip init on Linux. | |
659 | */ | |
660 | if (ohci->flags & OHCI_QUIRK_INITRESET) { | |
661 | ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); | |
662 | // flush those writes | |
663 | (void) ohci_readl (ohci, &ohci->regs->control); | |
664 | } | |
665 | ||
666 | /* Tell the controller where the control and bulk lists are | |
667 | * The lists are empty now. */ | |
668 | ohci_writel (ohci, 0, &ohci->regs->ed_controlhead); | |
669 | ohci_writel (ohci, 0, &ohci->regs->ed_bulkhead); | |
670 | ||
671 | /* a reset clears this */ | |
672 | ohci_writel (ohci, (u32) ohci->hcca_dma, &ohci->regs->hcca); | |
673 | ||
674 | periodic_reinit (ohci); | |
675 | ||
676 | /* some OHCI implementations are finicky about how they init. | |
677 | * bogus values here mean not even enumeration could work. | |
678 | */ | |
679 | if ((ohci_readl (ohci, &ohci->regs->fminterval) & 0x3fff0000) == 0 | |
680 | || !ohci_readl (ohci, &ohci->regs->periodicstart)) { | |
681 | if (!(ohci->flags & OHCI_QUIRK_INITRESET)) { | |
682 | ohci->flags |= OHCI_QUIRK_INITRESET; | |
683 | ohci_dbg (ohci, "enabling initreset quirk\n"); | |
684 | goto retry; | |
685 | } | |
686 | spin_unlock_irq (&ohci->lock); | |
687 | ohci_err (ohci, "init err (%08x %04x)\n", | |
688 | ohci_readl (ohci, &ohci->regs->fminterval), | |
689 | ohci_readl (ohci, &ohci->regs->periodicstart)); | |
690 | return -EOVERFLOW; | |
691 | } | |
692 | ||
d413984a | 693 | /* use rhsc irqs after khubd is fully initialized */ |
541c7d43 | 694 | set_bit(HCD_FLAG_POLL_RH, &hcd->flags); |
d413984a DB |
695 | hcd->uses_new_polling = 1; |
696 | ||
697 | /* start controller operations */ | |
1da177e4 | 698 | ohci->hc_control &= OHCI_CTRL_RWC; |
d413984a DB |
699 | ohci->hc_control |= OHCI_CONTROL_INIT | OHCI_USB_OPER; |
700 | ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); | |
6a9062f3 | 701 | hcd->state = HC_STATE_RUNNING; |
1da177e4 LT |
702 | |
703 | /* wake on ConnectStatusChange, matching external hubs */ | |
704 | ohci_writel (ohci, RH_HS_DRWE, &ohci->regs->roothub.status); | |
705 | ||
706 | /* Choose the interrupts we care about now, others later on demand */ | |
707 | mask = OHCI_INTR_INIT; | |
d413984a | 708 | ohci_writel (ohci, ~0, &ohci->regs->intrstatus); |
1da177e4 LT |
709 | ohci_writel (ohci, mask, &ohci->regs->intrenable); |
710 | ||
711 | /* handle root hub init quirks ... */ | |
96f90a8b HS |
712 | val = roothub_a (ohci); |
713 | val &= ~(RH_A_PSM | RH_A_OCPM); | |
1da177e4 LT |
714 | if (ohci->flags & OHCI_QUIRK_SUPERIO) { |
715 | /* NSC 87560 and maybe others */ | |
96f90a8b HS |
716 | val |= RH_A_NOCP; |
717 | val &= ~(RH_A_POTPGT | RH_A_NPS); | |
718 | ohci_writel (ohci, val, &ohci->regs->roothub.a); | |
1133cd8a DES |
719 | } else if ((ohci->flags & OHCI_QUIRK_AMD756) || |
720 | (ohci->flags & OHCI_QUIRK_HUB_POWER)) { | |
1da177e4 LT |
721 | /* hub power always on; required for AMD-756 and some |
722 | * Mac platforms. ganged overcurrent reporting, if any. | |
723 | */ | |
96f90a8b HS |
724 | val |= RH_A_NPS; |
725 | ohci_writel (ohci, val, &ohci->regs->roothub.a); | |
1da177e4 LT |
726 | } |
727 | ohci_writel (ohci, RH_HS_LPSC, &ohci->regs->roothub.status); | |
96f90a8b | 728 | ohci_writel (ohci, (val & RH_A_NPS) ? 0 : RH_B_PPCM, |
1da177e4 LT |
729 | &ohci->regs->roothub.b); |
730 | // flush those writes | |
731 | (void) ohci_readl (ohci, &ohci->regs->control); | |
732 | ||
d413984a | 733 | ohci->next_statechange = jiffies + STATECHANGE_DELAY; |
1da177e4 LT |
734 | spin_unlock_irq (&ohci->lock); |
735 | ||
736 | // POTPGT delay is bits 24-31, in 2 ms units. | |
96f90a8b | 737 | mdelay ((val >> 23) & 0x1fe); |
6a9062f3 | 738 | hcd->state = HC_STATE_RUNNING; |
1da177e4 | 739 | |
89a0fd18 MN |
740 | if (quirk_zfmicro(ohci)) { |
741 | /* Create timer to watch for bad queue state on ZF Micro */ | |
742 | setup_timer(&ohci->unlink_watchdog, unlink_watchdog_func, | |
743 | (unsigned long) ohci); | |
744 | ||
745 | ohci->eds_scheduled = 0; | |
746 | ohci->ed_to_check = NULL; | |
747 | } | |
748 | ||
1da177e4 LT |
749 | ohci_dump (ohci, 1); |
750 | ||
1da177e4 LT |
751 | return 0; |
752 | } | |
753 | ||
754 | /*-------------------------------------------------------------------------*/ | |
755 | ||
756 | /* an interrupt happens */ | |
757 | ||
7d12e780 | 758 | static irqreturn_t ohci_irq (struct usb_hcd *hcd) |
1da177e4 LT |
759 | { |
760 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); | |
761 | struct ohci_regs __iomem *regs = ohci->regs; | |
89a0fd18 | 762 | int ints; |
1da177e4 | 763 | |
565227c0 BH |
764 | /* Read interrupt status (and flush pending writes). We ignore the |
765 | * optimization of checking the LSB of hcca->done_head; it doesn't | |
766 | * work on all systems (edge triggering for OHCI can be a factor). | |
89a0fd18 | 767 | */ |
565227c0 | 768 | ints = ohci_readl(ohci, ®s->intrstatus); |
1da177e4 | 769 | |
565227c0 BH |
770 | /* Check for an all 1's result which is a typical consequence |
771 | * of dead, unclocked, or unplugged (CardBus...) devices | |
772 | */ | |
773 | if (ints == ~(u32)0) { | |
1da177e4 LT |
774 | disable (ohci); |
775 | ohci_dbg (ohci, "device removed!\n"); | |
776 | return IRQ_HANDLED; | |
565227c0 BH |
777 | } |
778 | ||
779 | /* We only care about interrupts that are enabled */ | |
780 | ints &= ohci_readl(ohci, ®s->intrenable); | |
1da177e4 LT |
781 | |
782 | /* interrupt for some other device? */ | |
565227c0 | 783 | if (ints == 0) |
1da177e4 | 784 | return IRQ_NOTMINE; |
d413984a | 785 | |
1da177e4 | 786 | if (ints & OHCI_INTR_UE) { |
1da177e4 | 787 | // e.g. due to PCI Master/Target Abort |
89a0fd18 | 788 | if (quirk_nec(ohci)) { |
d576bb9f MH |
789 | /* Workaround for a silicon bug in some NEC chips used |
790 | * in Apple's PowerBooks. Adapted from Darwin code. | |
791 | */ | |
792 | ohci_err (ohci, "OHCI Unrecoverable Error, scheduling NEC chip restart\n"); | |
793 | ||
794 | ohci_writel (ohci, OHCI_INTR_UE, ®s->intrdisable); | |
795 | ||
796 | schedule_work (&ohci->nec_work); | |
797 | } else { | |
798 | disable (ohci); | |
799 | ohci_err (ohci, "OHCI Unrecoverable Error, disabled\n"); | |
800 | } | |
1da177e4 LT |
801 | |
802 | ohci_dump (ohci, 1); | |
803 | ohci_usb_reset (ohci); | |
804 | } | |
805 | ||
583ceada AS |
806 | if (ints & OHCI_INTR_RHSC) { |
807 | ohci_vdbg(ohci, "rhsc\n"); | |
808 | ohci->next_statechange = jiffies + STATECHANGE_DELAY; | |
809 | ohci_writel(ohci, OHCI_INTR_RD | OHCI_INTR_RHSC, | |
810 | ®s->intrstatus); | |
052ac01a AS |
811 | |
812 | /* NOTE: Vendors didn't always make the same implementation | |
813 | * choices for RHSC. Many followed the spec; RHSC triggers | |
814 | * on an edge, like setting and maybe clearing a port status | |
815 | * change bit. With others it's level-triggered, active | |
816 | * until khubd clears all the port status change bits. We'll | |
817 | * always disable it here and rely on polling until khubd | |
818 | * re-enables it. | |
819 | */ | |
820 | ohci_writel(ohci, OHCI_INTR_RHSC, ®s->intrdisable); | |
583ceada AS |
821 | usb_hcd_poll_rh_status(hcd); |
822 | } | |
823 | ||
824 | /* For connect and disconnect events, we expect the controller | |
825 | * to turn on RHSC along with RD. But for remote wakeup events | |
826 | * this might not happen. | |
827 | */ | |
828 | else if (ints & OHCI_INTR_RD) { | |
829 | ohci_vdbg(ohci, "resume detect\n"); | |
830 | ohci_writel(ohci, OHCI_INTR_RD, ®s->intrstatus); | |
541c7d43 | 831 | set_bit(HCD_FLAG_POLL_RH, &hcd->flags); |
8d1a243b AS |
832 | if (ohci->autostop) { |
833 | spin_lock (&ohci->lock); | |
834 | ohci_rh_resume (ohci); | |
835 | spin_unlock (&ohci->lock); | |
836 | } else | |
f197b2c5 | 837 | usb_hcd_resume_root_hub(hcd); |
1da177e4 LT |
838 | } |
839 | ||
840 | if (ints & OHCI_INTR_WDH) { | |
1da177e4 | 841 | spin_lock (&ohci->lock); |
7d12e780 | 842 | dl_done_list (ohci); |
1da177e4 | 843 | spin_unlock (&ohci->lock); |
1da177e4 | 844 | } |
dd9048af | 845 | |
89a0fd18 MN |
846 | if (quirk_zfmicro(ohci) && (ints & OHCI_INTR_SF)) { |
847 | spin_lock(&ohci->lock); | |
848 | if (ohci->ed_to_check) { | |
849 | struct ed *ed = ohci->ed_to_check; | |
850 | ||
851 | if (check_ed(ohci, ed)) { | |
852 | /* HC thinks the TD list is empty; HCD knows | |
853 | * at least one TD is outstanding | |
854 | */ | |
855 | if (--ohci->zf_delay == 0) { | |
856 | struct td *td = list_entry( | |
857 | ed->td_list.next, | |
858 | struct td, td_list); | |
859 | ohci_warn(ohci, | |
860 | "Reclaiming orphan TD %p\n", | |
861 | td); | |
862 | takeback_td(ohci, td); | |
863 | ohci->ed_to_check = NULL; | |
864 | } | |
865 | } else | |
866 | ohci->ed_to_check = NULL; | |
867 | } | |
868 | spin_unlock(&ohci->lock); | |
869 | } | |
870 | ||
1da177e4 LT |
871 | /* could track INTR_SO to reduce available PCI/... bandwidth */ |
872 | ||
873 | /* handle any pending URB/ED unlinks, leaving INTR_SF enabled | |
874 | * when there's still unlinking to be done (next frame). | |
875 | */ | |
876 | spin_lock (&ohci->lock); | |
877 | if (ohci->ed_rm_list) | |
7d12e780 | 878 | finish_unlinks (ohci, ohci_frame_no(ohci)); |
89a0fd18 MN |
879 | if ((ints & OHCI_INTR_SF) != 0 |
880 | && !ohci->ed_rm_list | |
881 | && !ohci->ed_to_check | |
1da177e4 | 882 | && HC_IS_RUNNING(hcd->state)) |
dd9048af | 883 | ohci_writel (ohci, OHCI_INTR_SF, ®s->intrdisable); |
1da177e4 LT |
884 | spin_unlock (&ohci->lock); |
885 | ||
886 | if (HC_IS_RUNNING(hcd->state)) { | |
887 | ohci_writel (ohci, ints, ®s->intrstatus); | |
dd9048af | 888 | ohci_writel (ohci, OHCI_INTR_MIE, ®s->intrenable); |
1da177e4 LT |
889 | // flush those writes |
890 | (void) ohci_readl (ohci, &ohci->regs->control); | |
891 | } | |
892 | ||
893 | return IRQ_HANDLED; | |
894 | } | |
895 | ||
896 | /*-------------------------------------------------------------------------*/ | |
897 | ||
898 | static void ohci_stop (struct usb_hcd *hcd) | |
dd9048af | 899 | { |
1da177e4 LT |
900 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); |
901 | ||
1da177e4 LT |
902 | ohci_dump (ohci, 1); |
903 | ||
904 | flush_scheduled_work(); | |
905 | ||
906 | ohci_usb_reset (ohci); | |
907 | ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable); | |
71795c1d PZ |
908 | free_irq(hcd->irq, hcd); |
909 | hcd->irq = -1; | |
910 | ||
89a0fd18 MN |
911 | if (quirk_zfmicro(ohci)) |
912 | del_timer(&ohci->unlink_watchdog); | |
ab1666c1 LY |
913 | if (quirk_amdiso(ohci)) |
914 | amd_iso_dev_put(); | |
89a0fd18 | 915 | |
1da177e4 LT |
916 | remove_debug_files (ohci); |
917 | ohci_mem_cleanup (ohci); | |
918 | if (ohci->hcca) { | |
dd9048af DB |
919 | dma_free_coherent (hcd->self.controller, |
920 | sizeof *ohci->hcca, | |
1da177e4 LT |
921 | ohci->hcca, ohci->hcca_dma); |
922 | ohci->hcca = NULL; | |
923 | ohci->hcca_dma = 0; | |
924 | } | |
925 | } | |
926 | ||
927 | /*-------------------------------------------------------------------------*/ | |
928 | ||
da6fb570 DB |
929 | #if defined(CONFIG_PM) || defined(CONFIG_PCI) |
930 | ||
1da177e4 | 931 | /* must not be called from interrupt context */ |
1da177e4 LT |
932 | static int ohci_restart (struct ohci_hcd *ohci) |
933 | { | |
934 | int temp; | |
935 | int i; | |
936 | struct urb_priv *priv; | |
1da177e4 | 937 | |
1da177e4 LT |
938 | spin_lock_irq(&ohci->lock); |
939 | disable (ohci); | |
d576bb9f MH |
940 | |
941 | /* Recycle any "live" eds/tds (and urbs). */ | |
1da177e4 LT |
942 | if (!list_empty (&ohci->pending)) |
943 | ohci_dbg(ohci, "abort schedule...\n"); | |
944 | list_for_each_entry (priv, &ohci->pending, pending) { | |
945 | struct urb *urb = priv->td[0]->urb; | |
946 | struct ed *ed = priv->ed; | |
947 | ||
948 | switch (ed->state) { | |
949 | case ED_OPER: | |
950 | ed->state = ED_UNLINK; | |
951 | ed->hwINFO |= cpu_to_hc32(ohci, ED_DEQUEUE); | |
952 | ed_deschedule (ohci, ed); | |
953 | ||
954 | ed->ed_next = ohci->ed_rm_list; | |
955 | ed->ed_prev = NULL; | |
956 | ohci->ed_rm_list = ed; | |
957 | /* FALLTHROUGH */ | |
958 | case ED_UNLINK: | |
959 | break; | |
960 | default: | |
961 | ohci_dbg(ohci, "bogus ed %p state %d\n", | |
962 | ed, ed->state); | |
963 | } | |
964 | ||
55d84968 AS |
965 | if (!urb->unlinked) |
966 | urb->unlinked = -ESHUTDOWN; | |
1da177e4 | 967 | } |
7d12e780 | 968 | finish_unlinks (ohci, 0); |
1da177e4 LT |
969 | spin_unlock_irq(&ohci->lock); |
970 | ||
971 | /* paranoia, in case that didn't work: */ | |
972 | ||
973 | /* empty the interrupt branches */ | |
974 | for (i = 0; i < NUM_INTS; i++) ohci->load [i] = 0; | |
975 | for (i = 0; i < NUM_INTS; i++) ohci->hcca->int_table [i] = 0; | |
dd9048af | 976 | |
1da177e4 LT |
977 | /* no EDs to remove */ |
978 | ohci->ed_rm_list = NULL; | |
979 | ||
dd9048af | 980 | /* empty control and bulk lists */ |
1da177e4 LT |
981 | ohci->ed_controltail = NULL; |
982 | ohci->ed_bulktail = NULL; | |
983 | ||
984 | if ((temp = ohci_run (ohci)) < 0) { | |
985 | ohci_err (ohci, "can't restart, %d\n", temp); | |
986 | return temp; | |
1da177e4 | 987 | } |
383975d7 | 988 | ohci_dbg(ohci, "restart complete\n"); |
1da177e4 LT |
989 | return 0; |
990 | } | |
d576bb9f | 991 | |
da6fb570 DB |
992 | #endif |
993 | ||
d576bb9f MH |
994 | /*-------------------------------------------------------------------------*/ |
995 | ||
1da177e4 | 996 | MODULE_AUTHOR (DRIVER_AUTHOR); |
2b70f073 | 997 | MODULE_DESCRIPTION(DRIVER_DESC); |
1da177e4 LT |
998 | MODULE_LICENSE ("GPL"); |
999 | ||
1000 | #ifdef CONFIG_PCI | |
1001 | #include "ohci-pci.c" | |
5e16fabe | 1002 | #define PCI_DRIVER ohci_pci_driver |
1da177e4 LT |
1003 | #endif |
1004 | ||
6381fad7 | 1005 | #if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_SA1111) |
1da177e4 | 1006 | #include "ohci-sa1111.c" |
5e16fabe | 1007 | #define SA1111_DRIVER ohci_hcd_sa1111_driver |
1da177e4 LT |
1008 | #endif |
1009 | ||
3ba5f38f | 1010 | #if defined(CONFIG_ARCH_S3C2410) || defined(CONFIG_ARCH_S3C64XX) |
3eb0c5f4 | 1011 | #include "ohci-s3c2410.c" |
5e16fabe | 1012 | #define PLATFORM_DRIVER ohci_hcd_s3c2410_driver |
3eb0c5f4 BD |
1013 | #endif |
1014 | ||
968b448b | 1015 | #ifdef CONFIG_USB_OHCI_HCD_OMAP1 |
1da177e4 | 1016 | #include "ohci-omap.c" |
968b448b AG |
1017 | #define OMAP1_PLATFORM_DRIVER ohci_hcd_omap_driver |
1018 | #endif | |
1019 | ||
1020 | #ifdef CONFIG_USB_OHCI_HCD_OMAP3 | |
1021 | #include "ohci-omap3.c" | |
1022 | #define OMAP3_PLATFORM_DRIVER ohci_hcd_omap3_driver | |
1da177e4 LT |
1023 | #endif |
1024 | ||
1025 | #ifdef CONFIG_ARCH_LH7A404 | |
1026 | #include "ohci-lh7a404.c" | |
5e16fabe | 1027 | #define PLATFORM_DRIVER ohci_hcd_lh7a404_driver |
1da177e4 LT |
1028 | #endif |
1029 | ||
e77ec189 | 1030 | #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) |
1da177e4 | 1031 | #include "ohci-pxa27x.c" |
5e16fabe | 1032 | #define PLATFORM_DRIVER ohci_hcd_pxa27x_driver |
1da177e4 LT |
1033 | #endif |
1034 | ||
a5b7474a LB |
1035 | #ifdef CONFIG_ARCH_EP93XX |
1036 | #include "ohci-ep93xx.c" | |
5e16fabe | 1037 | #define PLATFORM_DRIVER ohci_hcd_ep93xx_driver |
a5b7474a LB |
1038 | #endif |
1039 | ||
42a4f17d | 1040 | #ifdef CONFIG_MIPS_ALCHEMY |
1da177e4 | 1041 | #include "ohci-au1xxx.c" |
5e16fabe | 1042 | #define PLATFORM_DRIVER ohci_hcd_au1xxx_driver |
1da177e4 LT |
1043 | #endif |
1044 | ||
5151d040 VW |
1045 | #ifdef CONFIG_PNX8550 |
1046 | #include "ohci-pnx8550.c" | |
5e16fabe | 1047 | #define PLATFORM_DRIVER ohci_hcd_pnx8550_driver |
5151d040 VW |
1048 | #endif |
1049 | ||
1da177e4 LT |
1050 | #ifdef CONFIG_USB_OHCI_HCD_PPC_SOC |
1051 | #include "ohci-ppc-soc.c" | |
5e16fabe | 1052 | #define PLATFORM_DRIVER ohci_hcd_ppc_soc_driver |
1da177e4 LT |
1053 | #endif |
1054 | ||
58a0cd78 | 1055 | #ifdef CONFIG_ARCH_AT91 |
39a269c0 | 1056 | #include "ohci-at91.c" |
5e16fabe | 1057 | #define PLATFORM_DRIVER ohci_hcd_at91_driver |
39a269c0 AV |
1058 | #endif |
1059 | ||
60bbfc84 VW |
1060 | #ifdef CONFIG_ARCH_PNX4008 |
1061 | #include "ohci-pnx4008.c" | |
5e16fabe | 1062 | #define PLATFORM_DRIVER usb_hcd_pnx4008_driver |
60bbfc84 VW |
1063 | #endif |
1064 | ||
efe7daf2 SS |
1065 | #ifdef CONFIG_ARCH_DAVINCI_DA8XX |
1066 | #include "ohci-da8xx.c" | |
1067 | #define PLATFORM_DRIVER ohci_hcd_da8xx_driver | |
1068 | #endif | |
1069 | ||
828d55c5 YS |
1070 | #if defined(CONFIG_CPU_SUBTYPE_SH7720) || \ |
1071 | defined(CONFIG_CPU_SUBTYPE_SH7721) || \ | |
4c3f450b KM |
1072 | defined(CONFIG_CPU_SUBTYPE_SH7763) || \ |
1073 | defined(CONFIG_CPU_SUBTYPE_SH7786) | |
828d55c5 YS |
1074 | #include "ohci-sh.c" |
1075 | #define PLATFORM_DRIVER ohci_hcd_sh_driver | |
1076 | #endif | |
1077 | ||
5e16fabe | 1078 | |
495a678f SM |
1079 | #ifdef CONFIG_USB_OHCI_HCD_PPC_OF |
1080 | #include "ohci-ppc-of.c" | |
1081 | #define OF_PLATFORM_DRIVER ohci_hcd_ppc_of_driver | |
1082 | #endif | |
1083 | ||
6a6c957e GL |
1084 | #ifdef CONFIG_PPC_PS3 |
1085 | #include "ohci-ps3.c" | |
7a4eb7fd | 1086 | #define PS3_SYSTEM_BUS_DRIVER ps3_ohci_driver |
6a6c957e GL |
1087 | #endif |
1088 | ||
c604e851 MB |
1089 | #ifdef CONFIG_USB_OHCI_HCD_SSB |
1090 | #include "ohci-ssb.c" | |
1091 | #define SSB_OHCI_DRIVER ssb_ohci_driver | |
1092 | #endif | |
1093 | ||
f54aab6e MD |
1094 | #ifdef CONFIG_MFD_SM501 |
1095 | #include "ohci-sm501.c" | |
3ee38d8b | 1096 | #define SM501_OHCI_DRIVER ohci_hcd_sm501_driver |
f54aab6e MD |
1097 | #endif |
1098 | ||
78c73414 DES |
1099 | #ifdef CONFIG_MFD_TC6393XB |
1100 | #include "ohci-tmio.c" | |
1101 | #define TMIO_OHCI_DRIVER ohci_hcd_tmio_driver | |
2249071b LPC |
1102 | #endif |
1103 | ||
1104 | #ifdef CONFIG_MACH_JZ4740 | |
1105 | #include "ohci-jz4740.c" | |
1106 | #define PLATFORM_DRIVER ohci_hcd_jz4740_driver | |
78c73414 DES |
1107 | #endif |
1108 | ||
1643accd DD |
1109 | #ifdef CONFIG_USB_OCTEON_OHCI |
1110 | #include "ohci-octeon.c" | |
1111 | #define PLATFORM_DRIVER ohci_octeon_driver | |
1112 | #endif | |
1113 | ||
5e16fabe SM |
1114 | #if !defined(PCI_DRIVER) && \ |
1115 | !defined(PLATFORM_DRIVER) && \ | |
968b448b AG |
1116 | !defined(OMAP1_PLATFORM_DRIVER) && \ |
1117 | !defined(OMAP3_PLATFORM_DRIVER) && \ | |
495a678f | 1118 | !defined(OF_PLATFORM_DRIVER) && \ |
6a6c957e | 1119 | !defined(SA1111_DRIVER) && \ |
c604e851 | 1120 | !defined(PS3_SYSTEM_BUS_DRIVER) && \ |
3ee38d8b | 1121 | !defined(SM501_OHCI_DRIVER) && \ |
78c73414 | 1122 | !defined(TMIO_OHCI_DRIVER) && \ |
c604e851 | 1123 | !defined(SSB_OHCI_DRIVER) |
1da177e4 LT |
1124 | #error "missing bus glue for ohci-hcd" |
1125 | #endif | |
5e16fabe SM |
1126 | |
1127 | static int __init ohci_hcd_mod_init(void) | |
1128 | { | |
1129 | int retval = 0; | |
5e16fabe SM |
1130 | |
1131 | if (usb_disabled()) | |
1132 | return -ENODEV; | |
1133 | ||
2b70f073 | 1134 | printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name); |
5e16fabe SM |
1135 | pr_debug ("%s: block sizes: ed %Zd td %Zd\n", hcd_name, |
1136 | sizeof (struct ed), sizeof (struct td)); | |
9beeee65 | 1137 | set_bit(USB_OHCI_LOADED, &usb_hcds_loaded); |
5e16fabe | 1138 | |
684c19e0 | 1139 | #ifdef DEBUG |
485f4f39 | 1140 | ohci_debug_root = debugfs_create_dir("ohci", usb_debug_root); |
684c19e0 TJ |
1141 | if (!ohci_debug_root) { |
1142 | retval = -ENOENT; | |
1143 | goto error_debug; | |
1144 | } | |
1145 | #endif | |
1146 | ||
6a6c957e | 1147 | #ifdef PS3_SYSTEM_BUS_DRIVER |
7a4eb7fd GL |
1148 | retval = ps3_ohci_driver_register(&PS3_SYSTEM_BUS_DRIVER); |
1149 | if (retval < 0) | |
1150 | goto error_ps3; | |
6a6c957e GL |
1151 | #endif |
1152 | ||
5e16fabe SM |
1153 | #ifdef PLATFORM_DRIVER |
1154 | retval = platform_driver_register(&PLATFORM_DRIVER); | |
1155 | if (retval < 0) | |
de44743b | 1156 | goto error_platform; |
5e16fabe SM |
1157 | #endif |
1158 | ||
968b448b AG |
1159 | #ifdef OMAP1_PLATFORM_DRIVER |
1160 | retval = platform_driver_register(&OMAP1_PLATFORM_DRIVER); | |
1161 | if (retval < 0) | |
1162 | goto error_omap1_platform; | |
1163 | #endif | |
1164 | ||
1165 | #ifdef OMAP3_PLATFORM_DRIVER | |
1166 | retval = platform_driver_register(&OMAP3_PLATFORM_DRIVER); | |
1167 | if (retval < 0) | |
1168 | goto error_omap3_platform; | |
1169 | #endif | |
1170 | ||
495a678f SM |
1171 | #ifdef OF_PLATFORM_DRIVER |
1172 | retval = of_register_platform_driver(&OF_PLATFORM_DRIVER); | |
1173 | if (retval < 0) | |
de44743b | 1174 | goto error_of_platform; |
495a678f SM |
1175 | #endif |
1176 | ||
5e16fabe SM |
1177 | #ifdef SA1111_DRIVER |
1178 | retval = sa1111_driver_register(&SA1111_DRIVER); | |
1179 | if (retval < 0) | |
de44743b | 1180 | goto error_sa1111; |
5e16fabe SM |
1181 | #endif |
1182 | ||
1183 | #ifdef PCI_DRIVER | |
1184 | retval = pci_register_driver(&PCI_DRIVER); | |
1185 | if (retval < 0) | |
de44743b | 1186 | goto error_pci; |
5e16fabe SM |
1187 | #endif |
1188 | ||
c604e851 MB |
1189 | #ifdef SSB_OHCI_DRIVER |
1190 | retval = ssb_driver_register(&SSB_OHCI_DRIVER); | |
1191 | if (retval) | |
1192 | goto error_ssb; | |
1193 | #endif | |
1194 | ||
3ee38d8b BD |
1195 | #ifdef SM501_OHCI_DRIVER |
1196 | retval = platform_driver_register(&SM501_OHCI_DRIVER); | |
1197 | if (retval < 0) | |
1198 | goto error_sm501; | |
1199 | #endif | |
1200 | ||
78c73414 DES |
1201 | #ifdef TMIO_OHCI_DRIVER |
1202 | retval = platform_driver_register(&TMIO_OHCI_DRIVER); | |
1203 | if (retval < 0) | |
1204 | goto error_tmio; | |
1205 | #endif | |
1206 | ||
5e16fabe SM |
1207 | return retval; |
1208 | ||
1209 | /* Error path */ | |
78c73414 DES |
1210 | #ifdef TMIO_OHCI_DRIVER |
1211 | platform_driver_unregister(&TMIO_OHCI_DRIVER); | |
1212 | error_tmio: | |
1213 | #endif | |
3ee38d8b | 1214 | #ifdef SM501_OHCI_DRIVER |
78c73414 | 1215 | platform_driver_unregister(&SM501_OHCI_DRIVER); |
3ee38d8b BD |
1216 | error_sm501: |
1217 | #endif | |
c604e851 | 1218 | #ifdef SSB_OHCI_DRIVER |
78c73414 | 1219 | ssb_driver_unregister(&SSB_OHCI_DRIVER); |
c604e851 MB |
1220 | error_ssb: |
1221 | #endif | |
de44743b | 1222 | #ifdef PCI_DRIVER |
c604e851 | 1223 | pci_unregister_driver(&PCI_DRIVER); |
de44743b BH |
1224 | error_pci: |
1225 | #endif | |
1226 | #ifdef SA1111_DRIVER | |
1227 | sa1111_driver_unregister(&SA1111_DRIVER); | |
1228 | error_sa1111: | |
5e16fabe | 1229 | #endif |
495a678f | 1230 | #ifdef OF_PLATFORM_DRIVER |
de44743b BH |
1231 | of_unregister_platform_driver(&OF_PLATFORM_DRIVER); |
1232 | error_of_platform: | |
495a678f | 1233 | #endif |
de44743b BH |
1234 | #ifdef PLATFORM_DRIVER |
1235 | platform_driver_unregister(&PLATFORM_DRIVER); | |
1236 | error_platform: | |
6a6c957e | 1237 | #endif |
968b448b AG |
1238 | #ifdef OMAP1_PLATFORM_DRIVER |
1239 | platform_driver_unregister(&OMAP1_PLATFORM_DRIVER); | |
1240 | error_omap1_platform: | |
1241 | #endif | |
1242 | #ifdef OMAP3_PLATFORM_DRIVER | |
1243 | platform_driver_unregister(&OMAP3_PLATFORM_DRIVER); | |
1244 | error_omap3_platform: | |
1245 | #endif | |
6a6c957e | 1246 | #ifdef PS3_SYSTEM_BUS_DRIVER |
7a4eb7fd | 1247 | ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); |
6a6c957e | 1248 | error_ps3: |
5e16fabe | 1249 | #endif |
684c19e0 TJ |
1250 | #ifdef DEBUG |
1251 | debugfs_remove(ohci_debug_root); | |
1252 | ohci_debug_root = NULL; | |
1253 | error_debug: | |
1254 | #endif | |
1255 | ||
9beeee65 | 1256 | clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded); |
5e16fabe SM |
1257 | return retval; |
1258 | } | |
1259 | module_init(ohci_hcd_mod_init); | |
1260 | ||
1261 | static void __exit ohci_hcd_mod_exit(void) | |
1262 | { | |
78c73414 DES |
1263 | #ifdef TMIO_OHCI_DRIVER |
1264 | platform_driver_unregister(&TMIO_OHCI_DRIVER); | |
1265 | #endif | |
3ee38d8b BD |
1266 | #ifdef SM501_OHCI_DRIVER |
1267 | platform_driver_unregister(&SM501_OHCI_DRIVER); | |
1268 | #endif | |
c604e851 MB |
1269 | #ifdef SSB_OHCI_DRIVER |
1270 | ssb_driver_unregister(&SSB_OHCI_DRIVER); | |
1271 | #endif | |
5e16fabe SM |
1272 | #ifdef PCI_DRIVER |
1273 | pci_unregister_driver(&PCI_DRIVER); | |
1274 | #endif | |
1275 | #ifdef SA1111_DRIVER | |
1276 | sa1111_driver_unregister(&SA1111_DRIVER); | |
1277 | #endif | |
495a678f SM |
1278 | #ifdef OF_PLATFORM_DRIVER |
1279 | of_unregister_platform_driver(&OF_PLATFORM_DRIVER); | |
1280 | #endif | |
5e16fabe SM |
1281 | #ifdef PLATFORM_DRIVER |
1282 | platform_driver_unregister(&PLATFORM_DRIVER); | |
1283 | #endif | |
ffb6748f KM |
1284 | #ifdef OMAP3_PLATFORM_DRIVER |
1285 | platform_driver_unregister(&OMAP3_PLATFORM_DRIVER); | |
1286 | #endif | |
6a6c957e | 1287 | #ifdef PS3_SYSTEM_BUS_DRIVER |
7a4eb7fd | 1288 | ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); |
6a6c957e | 1289 | #endif |
684c19e0 TJ |
1290 | #ifdef DEBUG |
1291 | debugfs_remove(ohci_debug_root); | |
1292 | #endif | |
9beeee65 | 1293 | clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded); |
5e16fabe SM |
1294 | } |
1295 | module_exit(ohci_hcd_mod_exit); | |
1296 |