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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * OHCI HCD (Host Controller Driver) for USB. | |
3 | * | |
4 | * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at> | |
5 | * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net> | |
dd9048af | 6 | * |
1da177e4 LT |
7 | * [ Initialisation is based on Linus' ] |
8 | * [ uhci code and gregs ohci fragments ] | |
9 | * [ (C) Copyright 1999 Linus Torvalds ] | |
10 | * [ (C) Copyright 1999 Gregory P. Smith] | |
dd9048af DB |
11 | * |
12 | * | |
1da177e4 LT |
13 | * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller |
14 | * interfaces (though some non-x86 Intel chips use it). It supports | |
15 | * smarter hardware than UHCI. A download link for the spec available | |
16 | * through the http://www.usb.org website. | |
17 | * | |
1da177e4 LT |
18 | * This file is licenced under the GPL. |
19 | */ | |
dd9048af | 20 | |
1da177e4 LT |
21 | #include <linux/module.h> |
22 | #include <linux/moduleparam.h> | |
23 | #include <linux/pci.h> | |
24 | #include <linux/kernel.h> | |
25 | #include <linux/delay.h> | |
26 | #include <linux/ioport.h> | |
27 | #include <linux/sched.h> | |
28 | #include <linux/slab.h> | |
29 | #include <linux/smp_lock.h> | |
30 | #include <linux/errno.h> | |
31 | #include <linux/init.h> | |
32 | #include <linux/timer.h> | |
33 | #include <linux/list.h> | |
1da177e4 | 34 | #include <linux/usb.h> |
3a16f7b4 | 35 | #include <linux/usb/otg.h> |
dd9048af | 36 | #include <linux/dma-mapping.h> |
f4df0e33 DB |
37 | #include <linux/dmapool.h> |
38 | #include <linux/reboot.h> | |
1da177e4 LT |
39 | |
40 | #include <asm/io.h> | |
41 | #include <asm/irq.h> | |
42 | #include <asm/system.h> | |
43 | #include <asm/unaligned.h> | |
44 | #include <asm/byteorder.h> | |
45 | ||
f4df0e33 | 46 | #include "../core/hcd.h" |
1da177e4 | 47 | |
d413984a | 48 | #define DRIVER_VERSION "2006 August 04" |
1da177e4 LT |
49 | #define DRIVER_AUTHOR "Roman Weissgaerber, David Brownell" |
50 | #define DRIVER_DESC "USB 1.1 'Open' Host Controller (OHCI) Driver" | |
51 | ||
52 | /*-------------------------------------------------------------------------*/ | |
53 | ||
8de98402 | 54 | #undef OHCI_VERBOSE_DEBUG /* not always helpful */ |
1da177e4 LT |
55 | |
56 | /* For initializing controller (mask in an HCFS mode too) */ | |
d413984a | 57 | #define OHCI_CONTROL_INIT OHCI_CTRL_CBSR |
1da177e4 | 58 | #define OHCI_INTR_INIT \ |
d413984a DB |
59 | (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE \ |
60 | | OHCI_INTR_RD | OHCI_INTR_WDH) | |
1da177e4 LT |
61 | |
62 | #ifdef __hppa__ | |
63 | /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */ | |
64 | #define IR_DISABLE | |
65 | #endif | |
66 | ||
67 | #ifdef CONFIG_ARCH_OMAP | |
68 | /* OMAP doesn't support IR (no SMM; not needed) */ | |
69 | #define IR_DISABLE | |
70 | #endif | |
71 | ||
72 | /*-------------------------------------------------------------------------*/ | |
73 | ||
74 | static const char hcd_name [] = "ohci_hcd"; | |
75 | ||
d413984a DB |
76 | #define STATECHANGE_DELAY msecs_to_jiffies(300) |
77 | ||
1da177e4 LT |
78 | #include "ohci.h" |
79 | ||
80 | static void ohci_dump (struct ohci_hcd *ohci, int verbose); | |
81 | static int ohci_init (struct ohci_hcd *ohci); | |
82 | static void ohci_stop (struct usb_hcd *hcd); | |
83 | ||
84 | #include "ohci-hub.c" | |
85 | #include "ohci-dbg.c" | |
86 | #include "ohci-mem.c" | |
87 | #include "ohci-q.c" | |
88 | ||
89 | ||
90 | /* | |
91 | * On architectures with edge-triggered interrupts we must never return | |
92 | * IRQ_NONE. | |
93 | */ | |
94 | #if defined(CONFIG_SA1111) /* ... or other edge-triggered systems */ | |
95 | #define IRQ_NOTMINE IRQ_HANDLED | |
96 | #else | |
97 | #define IRQ_NOTMINE IRQ_NONE | |
98 | #endif | |
99 | ||
100 | ||
101 | /* Some boards misreport power switching/overcurrent */ | |
102 | static int distrust_firmware = 1; | |
103 | module_param (distrust_firmware, bool, 0); | |
104 | MODULE_PARM_DESC (distrust_firmware, | |
105 | "true to distrust firmware power/overcurrent setup"); | |
106 | ||
107 | /* Some boards leave IR set wrongly, since they fail BIOS/SMM handshakes */ | |
108 | static int no_handshake = 0; | |
109 | module_param (no_handshake, bool, 0); | |
110 | MODULE_PARM_DESC (no_handshake, "true (not default) disables BIOS handshake"); | |
111 | ||
112 | /*-------------------------------------------------------------------------*/ | |
113 | ||
114 | /* | |
115 | * queue up an urb for anything except the root hub | |
116 | */ | |
117 | static int ohci_urb_enqueue ( | |
118 | struct usb_hcd *hcd, | |
119 | struct usb_host_endpoint *ep, | |
120 | struct urb *urb, | |
55016f10 | 121 | gfp_t mem_flags |
1da177e4 LT |
122 | ) { |
123 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); | |
124 | struct ed *ed; | |
125 | urb_priv_t *urb_priv; | |
126 | unsigned int pipe = urb->pipe; | |
127 | int i, size = 0; | |
128 | unsigned long flags; | |
129 | int retval = 0; | |
dd9048af | 130 | |
1da177e4 LT |
131 | #ifdef OHCI_VERBOSE_DEBUG |
132 | urb_print (urb, "SUB", usb_pipein (pipe)); | |
133 | #endif | |
dd9048af | 134 | |
1da177e4 LT |
135 | /* every endpoint has a ed, locate and maybe (re)initialize it */ |
136 | if (! (ed = ed_get (ohci, ep, urb->dev, pipe, urb->interval))) | |
137 | return -ENOMEM; | |
138 | ||
139 | /* for the private part of the URB we need the number of TDs (size) */ | |
140 | switch (ed->type) { | |
141 | case PIPE_CONTROL: | |
142 | /* td_submit_urb() doesn't yet handle these */ | |
143 | if (urb->transfer_buffer_length > 4096) | |
144 | return -EMSGSIZE; | |
145 | ||
146 | /* 1 TD for setup, 1 for ACK, plus ... */ | |
147 | size = 2; | |
148 | /* FALLTHROUGH */ | |
149 | // case PIPE_INTERRUPT: | |
150 | // case PIPE_BULK: | |
151 | default: | |
152 | /* one TD for every 4096 Bytes (can be upto 8K) */ | |
153 | size += urb->transfer_buffer_length / 4096; | |
154 | /* ... and for any remaining bytes ... */ | |
155 | if ((urb->transfer_buffer_length % 4096) != 0) | |
156 | size++; | |
157 | /* ... and maybe a zero length packet to wrap it up */ | |
158 | if (size == 0) | |
159 | size++; | |
160 | else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0 | |
161 | && (urb->transfer_buffer_length | |
162 | % usb_maxpacket (urb->dev, pipe, | |
163 | usb_pipeout (pipe))) == 0) | |
164 | size++; | |
165 | break; | |
166 | case PIPE_ISOCHRONOUS: /* number of packets from URB */ | |
167 | size = urb->number_of_packets; | |
168 | break; | |
169 | } | |
170 | ||
171 | /* allocate the private part of the URB */ | |
172 | urb_priv = kmalloc (sizeof (urb_priv_t) + size * sizeof (struct td *), | |
173 | mem_flags); | |
174 | if (!urb_priv) | |
175 | return -ENOMEM; | |
176 | memset (urb_priv, 0, sizeof (urb_priv_t) + size * sizeof (struct td *)); | |
177 | INIT_LIST_HEAD (&urb_priv->pending); | |
178 | urb_priv->length = size; | |
dd9048af | 179 | urb_priv->ed = ed; |
1da177e4 LT |
180 | |
181 | /* allocate the TDs (deferring hash chain updates) */ | |
182 | for (i = 0; i < size; i++) { | |
183 | urb_priv->td [i] = td_alloc (ohci, mem_flags); | |
184 | if (!urb_priv->td [i]) { | |
185 | urb_priv->length = i; | |
186 | urb_free_priv (ohci, urb_priv); | |
187 | return -ENOMEM; | |
188 | } | |
dd9048af | 189 | } |
1da177e4 LT |
190 | |
191 | spin_lock_irqsave (&ohci->lock, flags); | |
192 | ||
193 | /* don't submit to a dead HC */ | |
8de98402 BH |
194 | if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) { |
195 | retval = -ENODEV; | |
196 | goto fail; | |
197 | } | |
1da177e4 LT |
198 | if (!HC_IS_RUNNING(hcd->state)) { |
199 | retval = -ENODEV; | |
200 | goto fail; | |
201 | } | |
202 | ||
203 | /* in case of unlink-during-submit */ | |
204 | spin_lock (&urb->lock); | |
205 | if (urb->status != -EINPROGRESS) { | |
206 | spin_unlock (&urb->lock); | |
207 | urb->hcpriv = urb_priv; | |
7d12e780 | 208 | finish_urb (ohci, urb); |
1da177e4 LT |
209 | retval = 0; |
210 | goto fail; | |
211 | } | |
212 | ||
213 | /* schedule the ed if needed */ | |
214 | if (ed->state == ED_IDLE) { | |
215 | retval = ed_schedule (ohci, ed); | |
216 | if (retval < 0) | |
217 | goto fail0; | |
218 | if (ed->type == PIPE_ISOCHRONOUS) { | |
219 | u16 frame = ohci_frame_no(ohci); | |
220 | ||
221 | /* delay a few frames before the first TD */ | |
222 | frame += max_t (u16, 8, ed->interval); | |
223 | frame &= ~(ed->interval - 1); | |
224 | frame |= ed->branch; | |
225 | urb->start_frame = frame; | |
226 | ||
227 | /* yes, only URB_ISO_ASAP is supported, and | |
228 | * urb->start_frame is never used as input. | |
229 | */ | |
230 | } | |
231 | } else if (ed->type == PIPE_ISOCHRONOUS) | |
232 | urb->start_frame = ed->last_iso + ed->interval; | |
233 | ||
234 | /* fill the TDs and link them to the ed; and | |
235 | * enable that part of the schedule, if needed | |
236 | * and update count of queued periodic urbs | |
237 | */ | |
238 | urb->hcpriv = urb_priv; | |
239 | td_submit_urb (ohci, urb); | |
240 | ||
241 | fail0: | |
242 | spin_unlock (&urb->lock); | |
243 | fail: | |
244 | if (retval) | |
245 | urb_free_priv (ohci, urb_priv); | |
246 | spin_unlock_irqrestore (&ohci->lock, flags); | |
247 | return retval; | |
248 | } | |
249 | ||
250 | /* | |
251 | * decouple the URB from the HC queues (TDs, urb_priv); it's | |
252 | * already marked using urb->status. reporting is always done | |
253 | * asynchronously, and we might be dealing with an urb that's | |
254 | * partially transferred, or an ED with other urbs being unlinked. | |
255 | */ | |
256 | static int ohci_urb_dequeue (struct usb_hcd *hcd, struct urb *urb) | |
257 | { | |
258 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); | |
259 | unsigned long flags; | |
dd9048af | 260 | |
1da177e4 LT |
261 | #ifdef OHCI_VERBOSE_DEBUG |
262 | urb_print (urb, "UNLINK", 1); | |
dd9048af | 263 | #endif |
1da177e4 LT |
264 | |
265 | spin_lock_irqsave (&ohci->lock, flags); | |
dd9048af | 266 | if (HC_IS_RUNNING(hcd->state)) { |
1da177e4 LT |
267 | urb_priv_t *urb_priv; |
268 | ||
269 | /* Unless an IRQ completed the unlink while it was being | |
270 | * handed to us, flag it for unlink and giveback, and force | |
271 | * some upcoming INTR_SF to call finish_unlinks() | |
272 | */ | |
273 | urb_priv = urb->hcpriv; | |
274 | if (urb_priv) { | |
275 | if (urb_priv->ed->state == ED_OPER) | |
276 | start_ed_unlink (ohci, urb_priv->ed); | |
277 | } | |
278 | } else { | |
279 | /* | |
280 | * with HC dead, we won't respect hc queue pointers | |
281 | * any more ... just clean up every urb's memory. | |
282 | */ | |
283 | if (urb->hcpriv) | |
7d12e780 | 284 | finish_urb (ohci, urb); |
1da177e4 LT |
285 | } |
286 | spin_unlock_irqrestore (&ohci->lock, flags); | |
287 | return 0; | |
288 | } | |
289 | ||
290 | /*-------------------------------------------------------------------------*/ | |
291 | ||
292 | /* frees config/altsetting state for endpoints, | |
293 | * including ED memory, dummy TD, and bulk/intr data toggle | |
294 | */ | |
295 | ||
296 | static void | |
297 | ohci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep) | |
298 | { | |
299 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); | |
300 | unsigned long flags; | |
301 | struct ed *ed = ep->hcpriv; | |
302 | unsigned limit = 1000; | |
303 | ||
304 | /* ASSERT: any requests/urbs are being unlinked */ | |
305 | /* ASSERT: nobody can be submitting urbs for this any more */ | |
306 | ||
307 | if (!ed) | |
308 | return; | |
309 | ||
310 | rescan: | |
311 | spin_lock_irqsave (&ohci->lock, flags); | |
312 | ||
313 | if (!HC_IS_RUNNING (hcd->state)) { | |
314 | sanitize: | |
315 | ed->state = ED_IDLE; | |
7d12e780 | 316 | finish_unlinks (ohci, 0); |
1da177e4 LT |
317 | } |
318 | ||
319 | switch (ed->state) { | |
320 | case ED_UNLINK: /* wait for hw to finish? */ | |
321 | /* major IRQ delivery trouble loses INTR_SF too... */ | |
322 | if (limit-- == 0) { | |
323 | ohci_warn (ohci, "IRQ INTR_SF lossage\n"); | |
324 | goto sanitize; | |
325 | } | |
326 | spin_unlock_irqrestore (&ohci->lock, flags); | |
22c43863 | 327 | schedule_timeout_uninterruptible(1); |
1da177e4 LT |
328 | goto rescan; |
329 | case ED_IDLE: /* fully unlinked */ | |
330 | if (list_empty (&ed->td_list)) { | |
331 | td_free (ohci, ed->dummy); | |
332 | ed_free (ohci, ed); | |
333 | break; | |
334 | } | |
335 | /* else FALL THROUGH */ | |
336 | default: | |
337 | /* caller was supposed to have unlinked any requests; | |
338 | * that's not our job. can't recover; must leak ed. | |
339 | */ | |
340 | ohci_err (ohci, "leak ed %p (#%02x) state %d%s\n", | |
341 | ed, ep->desc.bEndpointAddress, ed->state, | |
342 | list_empty (&ed->td_list) ? "" : " (has tds)"); | |
343 | td_free (ohci, ed->dummy); | |
344 | break; | |
345 | } | |
346 | ep->hcpriv = NULL; | |
347 | spin_unlock_irqrestore (&ohci->lock, flags); | |
348 | return; | |
349 | } | |
350 | ||
351 | static int ohci_get_frame (struct usb_hcd *hcd) | |
352 | { | |
353 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); | |
354 | ||
355 | return ohci_frame_no(ohci); | |
356 | } | |
357 | ||
358 | static void ohci_usb_reset (struct ohci_hcd *ohci) | |
359 | { | |
360 | ohci->hc_control = ohci_readl (ohci, &ohci->regs->control); | |
361 | ohci->hc_control &= OHCI_CTRL_RWC; | |
362 | ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); | |
363 | } | |
364 | ||
64a21d02 | 365 | /* ohci_shutdown forcibly disables IRQs and DMA, helping kexec and |
f4df0e33 DB |
366 | * other cases where the next software may expect clean state from the |
367 | * "firmware". this is bus-neutral, unlike shutdown() methods. | |
368 | */ | |
64a21d02 AG |
369 | static void |
370 | ohci_shutdown (struct usb_hcd *hcd) | |
f4df0e33 DB |
371 | { |
372 | struct ohci_hcd *ohci; | |
373 | ||
64a21d02 | 374 | ohci = hcd_to_ohci (hcd); |
f4df0e33 DB |
375 | ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable); |
376 | ohci_usb_reset (ohci); | |
377 | /* flush the writes */ | |
378 | (void) ohci_readl (ohci, &ohci->regs->control); | |
f4df0e33 DB |
379 | } |
380 | ||
1da177e4 LT |
381 | /*-------------------------------------------------------------------------* |
382 | * HC functions | |
383 | *-------------------------------------------------------------------------*/ | |
384 | ||
385 | /* init memory, and kick BIOS/SMM off */ | |
386 | ||
387 | static int ohci_init (struct ohci_hcd *ohci) | |
388 | { | |
389 | int ret; | |
6a9062f3 | 390 | struct usb_hcd *hcd = ohci_to_hcd(ohci); |
1da177e4 LT |
391 | |
392 | disable (ohci); | |
6a9062f3 | 393 | ohci->regs = hcd->regs; |
1da177e4 | 394 | |
6a9062f3 DB |
395 | /* REVISIT this BIOS handshake is now moved into PCI "quirks", and |
396 | * was never needed for most non-PCI systems ... remove the code? | |
397 | */ | |
398 | ||
1da177e4 LT |
399 | #ifndef IR_DISABLE |
400 | /* SMM owns the HC? not for long! */ | |
401 | if (!no_handshake && ohci_readl (ohci, | |
402 | &ohci->regs->control) & OHCI_CTRL_IR) { | |
403 | u32 temp; | |
404 | ||
405 | ohci_dbg (ohci, "USB HC TakeOver from BIOS/SMM\n"); | |
406 | ||
407 | /* this timeout is arbitrary. we make it long, so systems | |
408 | * depending on usb keyboards may be usable even if the | |
409 | * BIOS/SMM code seems pretty broken. | |
410 | */ | |
411 | temp = 500; /* arbitrary: five seconds */ | |
412 | ||
413 | ohci_writel (ohci, OHCI_INTR_OC, &ohci->regs->intrenable); | |
414 | ohci_writel (ohci, OHCI_OCR, &ohci->regs->cmdstatus); | |
415 | while (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_IR) { | |
416 | msleep (10); | |
417 | if (--temp == 0) { | |
418 | ohci_err (ohci, "USB HC takeover failed!" | |
419 | " (BIOS/SMM bug)\n"); | |
420 | return -EBUSY; | |
421 | } | |
422 | } | |
423 | ohci_usb_reset (ohci); | |
424 | } | |
425 | #endif | |
426 | ||
427 | /* Disable HC interrupts */ | |
428 | ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable); | |
6a9062f3 DB |
429 | |
430 | /* flush the writes, and save key bits like RWC */ | |
431 | if (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_RWC) | |
432 | ohci->hc_control |= OHCI_CTRL_RWC; | |
1da177e4 | 433 | |
fdd13b36 DB |
434 | /* Read the number of ports unless overridden */ |
435 | if (ohci->num_ports == 0) | |
436 | ohci->num_ports = roothub_a(ohci) & RH_A_NDP; | |
437 | ||
1da177e4 LT |
438 | if (ohci->hcca) |
439 | return 0; | |
440 | ||
6a9062f3 | 441 | ohci->hcca = dma_alloc_coherent (hcd->self.controller, |
1da177e4 LT |
442 | sizeof *ohci->hcca, &ohci->hcca_dma, 0); |
443 | if (!ohci->hcca) | |
444 | return -ENOMEM; | |
445 | ||
446 | if ((ret = ohci_mem_init (ohci)) < 0) | |
6a9062f3 DB |
447 | ohci_stop (hcd); |
448 | else { | |
6a9062f3 DB |
449 | create_debug_files (ohci); |
450 | } | |
1da177e4 LT |
451 | |
452 | return ret; | |
1da177e4 LT |
453 | } |
454 | ||
455 | /*-------------------------------------------------------------------------*/ | |
456 | ||
457 | /* Start an OHCI controller, set the BUS operational | |
458 | * resets USB and controller | |
dd9048af | 459 | * enable interrupts |
1da177e4 LT |
460 | */ |
461 | static int ohci_run (struct ohci_hcd *ohci) | |
462 | { | |
dd9048af | 463 | u32 mask, temp; |
1da177e4 | 464 | int first = ohci->fminterval == 0; |
6a9062f3 | 465 | struct usb_hcd *hcd = ohci_to_hcd(ohci); |
1da177e4 LT |
466 | |
467 | disable (ohci); | |
468 | ||
469 | /* boot firmware should have set this up (5.1.1.3.1) */ | |
470 | if (first) { | |
471 | ||
472 | temp = ohci_readl (ohci, &ohci->regs->fminterval); | |
473 | ohci->fminterval = temp & 0x3fff; | |
474 | if (ohci->fminterval != FI) | |
475 | ohci_dbg (ohci, "fminterval delta %d\n", | |
476 | ohci->fminterval - FI); | |
477 | ohci->fminterval |= FSMP (ohci->fminterval) << 16; | |
478 | /* also: power/overcurrent flags in roothub.a */ | |
479 | } | |
480 | ||
dd9048af | 481 | /* Reset USB nearly "by the book". RemoteWakeupConnected was |
6a9062f3 DB |
482 | * saved if boot firmware (BIOS/SMM/...) told us it's connected, |
483 | * or if bus glue did the same (e.g. for PCI add-in cards with | |
484 | * PCI PM support). | |
1da177e4 | 485 | */ |
1da177e4 LT |
486 | ohci_dbg (ohci, "resetting from state '%s', control = 0x%x\n", |
487 | hcfs2string (ohci->hc_control & OHCI_CTRL_HCFS), | |
6a9062f3 DB |
488 | ohci_readl (ohci, &ohci->regs->control)); |
489 | if ((ohci->hc_control & OHCI_CTRL_RWC) != 0 | |
490 | && !device_may_wakeup(hcd->self.controller)) | |
491 | device_init_wakeup(hcd->self.controller, 1); | |
1da177e4 LT |
492 | |
493 | switch (ohci->hc_control & OHCI_CTRL_HCFS) { | |
494 | case OHCI_USB_OPER: | |
495 | temp = 0; | |
496 | break; | |
497 | case OHCI_USB_SUSPEND: | |
498 | case OHCI_USB_RESUME: | |
499 | ohci->hc_control &= OHCI_CTRL_RWC; | |
500 | ohci->hc_control |= OHCI_USB_RESUME; | |
501 | temp = 10 /* msec wait */; | |
502 | break; | |
503 | // case OHCI_USB_RESET: | |
504 | default: | |
505 | ohci->hc_control &= OHCI_CTRL_RWC; | |
506 | ohci->hc_control |= OHCI_USB_RESET; | |
507 | temp = 50 /* msec wait */; | |
508 | break; | |
509 | } | |
510 | ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); | |
511 | // flush the writes | |
512 | (void) ohci_readl (ohci, &ohci->regs->control); | |
513 | msleep(temp); | |
514 | temp = roothub_a (ohci); | |
515 | if (!(temp & RH_A_NPS)) { | |
1da177e4 | 516 | /* power down each port */ |
fdd13b36 | 517 | for (temp = 0; temp < ohci->num_ports; temp++) |
1da177e4 LT |
518 | ohci_writel (ohci, RH_PS_LSDA, |
519 | &ohci->regs->roothub.portstatus [temp]); | |
520 | } | |
521 | // flush those writes | |
522 | (void) ohci_readl (ohci, &ohci->regs->control); | |
523 | memset (ohci->hcca, 0, sizeof (struct ohci_hcca)); | |
524 | ||
525 | /* 2msec timelimit here means no irqs/preempt */ | |
526 | spin_lock_irq (&ohci->lock); | |
527 | ||
528 | retry: | |
529 | /* HC Reset requires max 10 us delay */ | |
530 | ohci_writel (ohci, OHCI_HCR, &ohci->regs->cmdstatus); | |
531 | temp = 30; /* ... allow extra time */ | |
532 | while ((ohci_readl (ohci, &ohci->regs->cmdstatus) & OHCI_HCR) != 0) { | |
533 | if (--temp == 0) { | |
534 | spin_unlock_irq (&ohci->lock); | |
535 | ohci_err (ohci, "USB HC reset timed out!\n"); | |
536 | return -1; | |
537 | } | |
538 | udelay (1); | |
539 | } | |
540 | ||
541 | /* now we're in the SUSPEND state ... must go OPERATIONAL | |
542 | * within 2msec else HC enters RESUME | |
543 | * | |
544 | * ... but some hardware won't init fmInterval "by the book" | |
545 | * (SiS, OPTi ...), so reset again instead. SiS doesn't need | |
546 | * this if we write fmInterval after we're OPERATIONAL. | |
547 | * Unclear about ALi, ServerWorks, and others ... this could | |
548 | * easily be a longstanding bug in chip init on Linux. | |
549 | */ | |
550 | if (ohci->flags & OHCI_QUIRK_INITRESET) { | |
551 | ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); | |
552 | // flush those writes | |
553 | (void) ohci_readl (ohci, &ohci->regs->control); | |
554 | } | |
555 | ||
556 | /* Tell the controller where the control and bulk lists are | |
557 | * The lists are empty now. */ | |
558 | ohci_writel (ohci, 0, &ohci->regs->ed_controlhead); | |
559 | ohci_writel (ohci, 0, &ohci->regs->ed_bulkhead); | |
560 | ||
561 | /* a reset clears this */ | |
562 | ohci_writel (ohci, (u32) ohci->hcca_dma, &ohci->regs->hcca); | |
563 | ||
564 | periodic_reinit (ohci); | |
565 | ||
566 | /* some OHCI implementations are finicky about how they init. | |
567 | * bogus values here mean not even enumeration could work. | |
568 | */ | |
569 | if ((ohci_readl (ohci, &ohci->regs->fminterval) & 0x3fff0000) == 0 | |
570 | || !ohci_readl (ohci, &ohci->regs->periodicstart)) { | |
571 | if (!(ohci->flags & OHCI_QUIRK_INITRESET)) { | |
572 | ohci->flags |= OHCI_QUIRK_INITRESET; | |
573 | ohci_dbg (ohci, "enabling initreset quirk\n"); | |
574 | goto retry; | |
575 | } | |
576 | spin_unlock_irq (&ohci->lock); | |
577 | ohci_err (ohci, "init err (%08x %04x)\n", | |
578 | ohci_readl (ohci, &ohci->regs->fminterval), | |
579 | ohci_readl (ohci, &ohci->regs->periodicstart)); | |
580 | return -EOVERFLOW; | |
581 | } | |
582 | ||
d413984a DB |
583 | /* use rhsc irqs after khubd is fully initialized */ |
584 | hcd->poll_rh = 1; | |
585 | hcd->uses_new_polling = 1; | |
586 | ||
587 | /* start controller operations */ | |
1da177e4 | 588 | ohci->hc_control &= OHCI_CTRL_RWC; |
d413984a DB |
589 | ohci->hc_control |= OHCI_CONTROL_INIT | OHCI_USB_OPER; |
590 | ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); | |
6a9062f3 | 591 | hcd->state = HC_STATE_RUNNING; |
1da177e4 LT |
592 | |
593 | /* wake on ConnectStatusChange, matching external hubs */ | |
594 | ohci_writel (ohci, RH_HS_DRWE, &ohci->regs->roothub.status); | |
595 | ||
596 | /* Choose the interrupts we care about now, others later on demand */ | |
597 | mask = OHCI_INTR_INIT; | |
d413984a | 598 | ohci_writel (ohci, ~0, &ohci->regs->intrstatus); |
1da177e4 LT |
599 | ohci_writel (ohci, mask, &ohci->regs->intrenable); |
600 | ||
601 | /* handle root hub init quirks ... */ | |
602 | temp = roothub_a (ohci); | |
603 | temp &= ~(RH_A_PSM | RH_A_OCPM); | |
604 | if (ohci->flags & OHCI_QUIRK_SUPERIO) { | |
605 | /* NSC 87560 and maybe others */ | |
606 | temp |= RH_A_NOCP; | |
607 | temp &= ~(RH_A_POTPGT | RH_A_NPS); | |
608 | ohci_writel (ohci, temp, &ohci->regs->roothub.a); | |
609 | } else if ((ohci->flags & OHCI_QUIRK_AMD756) || distrust_firmware) { | |
610 | /* hub power always on; required for AMD-756 and some | |
611 | * Mac platforms. ganged overcurrent reporting, if any. | |
612 | */ | |
613 | temp |= RH_A_NPS; | |
614 | ohci_writel (ohci, temp, &ohci->regs->roothub.a); | |
615 | } | |
616 | ohci_writel (ohci, RH_HS_LPSC, &ohci->regs->roothub.status); | |
617 | ohci_writel (ohci, (temp & RH_A_NPS) ? 0 : RH_B_PPCM, | |
618 | &ohci->regs->roothub.b); | |
619 | // flush those writes | |
620 | (void) ohci_readl (ohci, &ohci->regs->control); | |
621 | ||
d413984a | 622 | ohci->next_statechange = jiffies + STATECHANGE_DELAY; |
1da177e4 LT |
623 | spin_unlock_irq (&ohci->lock); |
624 | ||
625 | // POTPGT delay is bits 24-31, in 2 ms units. | |
626 | mdelay ((temp >> 23) & 0x1fe); | |
6a9062f3 | 627 | hcd->state = HC_STATE_RUNNING; |
1da177e4 LT |
628 | |
629 | ohci_dump (ohci, 1); | |
630 | ||
1da177e4 LT |
631 | return 0; |
632 | } | |
633 | ||
634 | /*-------------------------------------------------------------------------*/ | |
635 | ||
636 | /* an interrupt happens */ | |
637 | ||
7d12e780 | 638 | static irqreturn_t ohci_irq (struct usb_hcd *hcd) |
1da177e4 LT |
639 | { |
640 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); | |
641 | struct ohci_regs __iomem *regs = ohci->regs; | |
642 | int ints; | |
643 | ||
644 | /* we can eliminate a (slow) ohci_readl() | |
645 | if _only_ WDH caused this irq */ | |
646 | if ((ohci->hcca->done_head != 0) | |
647 | && ! (hc32_to_cpup (ohci, &ohci->hcca->done_head) | |
648 | & 0x01)) { | |
649 | ints = OHCI_INTR_WDH; | |
650 | ||
651 | /* cardbus/... hardware gone before remove() */ | |
652 | } else if ((ints = ohci_readl (ohci, ®s->intrstatus)) == ~(u32)0) { | |
653 | disable (ohci); | |
654 | ohci_dbg (ohci, "device removed!\n"); | |
655 | return IRQ_HANDLED; | |
656 | ||
657 | /* interrupt for some other device? */ | |
658 | } else if ((ints &= ohci_readl (ohci, ®s->intrenable)) == 0) { | |
659 | return IRQ_NOTMINE; | |
d413984a DB |
660 | } |
661 | ||
1da177e4 LT |
662 | if (ints & OHCI_INTR_UE) { |
663 | disable (ohci); | |
664 | ohci_err (ohci, "OHCI Unrecoverable Error, disabled\n"); | |
665 | // e.g. due to PCI Master/Target Abort | |
666 | ||
667 | ohci_dump (ohci, 1); | |
668 | ohci_usb_reset (ohci); | |
669 | } | |
670 | ||
583ceada AS |
671 | if (ints & OHCI_INTR_RHSC) { |
672 | ohci_vdbg(ohci, "rhsc\n"); | |
673 | ohci->next_statechange = jiffies + STATECHANGE_DELAY; | |
674 | ohci_writel(ohci, OHCI_INTR_RD | OHCI_INTR_RHSC, | |
675 | ®s->intrstatus); | |
052ac01a AS |
676 | |
677 | /* NOTE: Vendors didn't always make the same implementation | |
678 | * choices for RHSC. Many followed the spec; RHSC triggers | |
679 | * on an edge, like setting and maybe clearing a port status | |
680 | * change bit. With others it's level-triggered, active | |
681 | * until khubd clears all the port status change bits. We'll | |
682 | * always disable it here and rely on polling until khubd | |
683 | * re-enables it. | |
684 | */ | |
685 | ohci_writel(ohci, OHCI_INTR_RHSC, ®s->intrdisable); | |
583ceada AS |
686 | usb_hcd_poll_rh_status(hcd); |
687 | } | |
688 | ||
689 | /* For connect and disconnect events, we expect the controller | |
690 | * to turn on RHSC along with RD. But for remote wakeup events | |
691 | * this might not happen. | |
692 | */ | |
693 | else if (ints & OHCI_INTR_RD) { | |
694 | ohci_vdbg(ohci, "resume detect\n"); | |
695 | ohci_writel(ohci, OHCI_INTR_RD, ®s->intrstatus); | |
8d1a243b AS |
696 | hcd->poll_rh = 1; |
697 | if (ohci->autostop) { | |
698 | spin_lock (&ohci->lock); | |
699 | ohci_rh_resume (ohci); | |
700 | spin_unlock (&ohci->lock); | |
701 | } else | |
f197b2c5 | 702 | usb_hcd_resume_root_hub(hcd); |
1da177e4 LT |
703 | } |
704 | ||
705 | if (ints & OHCI_INTR_WDH) { | |
706 | if (HC_IS_RUNNING(hcd->state)) | |
8d1a243b | 707 | ohci_writel (ohci, OHCI_INTR_WDH, ®s->intrdisable); |
1da177e4 | 708 | spin_lock (&ohci->lock); |
7d12e780 | 709 | dl_done_list (ohci); |
1da177e4 LT |
710 | spin_unlock (&ohci->lock); |
711 | if (HC_IS_RUNNING(hcd->state)) | |
dd9048af | 712 | ohci_writel (ohci, OHCI_INTR_WDH, ®s->intrenable); |
1da177e4 | 713 | } |
dd9048af | 714 | |
1da177e4 LT |
715 | /* could track INTR_SO to reduce available PCI/... bandwidth */ |
716 | ||
717 | /* handle any pending URB/ED unlinks, leaving INTR_SF enabled | |
718 | * when there's still unlinking to be done (next frame). | |
719 | */ | |
720 | spin_lock (&ohci->lock); | |
721 | if (ohci->ed_rm_list) | |
7d12e780 | 722 | finish_unlinks (ohci, ohci_frame_no(ohci)); |
1da177e4 LT |
723 | if ((ints & OHCI_INTR_SF) != 0 && !ohci->ed_rm_list |
724 | && HC_IS_RUNNING(hcd->state)) | |
dd9048af | 725 | ohci_writel (ohci, OHCI_INTR_SF, ®s->intrdisable); |
1da177e4 LT |
726 | spin_unlock (&ohci->lock); |
727 | ||
728 | if (HC_IS_RUNNING(hcd->state)) { | |
729 | ohci_writel (ohci, ints, ®s->intrstatus); | |
dd9048af | 730 | ohci_writel (ohci, OHCI_INTR_MIE, ®s->intrenable); |
1da177e4 LT |
731 | // flush those writes |
732 | (void) ohci_readl (ohci, &ohci->regs->control); | |
733 | } | |
734 | ||
735 | return IRQ_HANDLED; | |
736 | } | |
737 | ||
738 | /*-------------------------------------------------------------------------*/ | |
739 | ||
740 | static void ohci_stop (struct usb_hcd *hcd) | |
dd9048af | 741 | { |
1da177e4 LT |
742 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); |
743 | ||
744 | ohci_dbg (ohci, "stop %s controller (state 0x%02x)\n", | |
745 | hcfs2string (ohci->hc_control & OHCI_CTRL_HCFS), | |
746 | hcd->state); | |
747 | ohci_dump (ohci, 1); | |
748 | ||
749 | flush_scheduled_work(); | |
750 | ||
751 | ohci_usb_reset (ohci); | |
752 | ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable); | |
71795c1d PZ |
753 | free_irq(hcd->irq, hcd); |
754 | hcd->irq = -1; | |
755 | ||
1da177e4 LT |
756 | remove_debug_files (ohci); |
757 | ohci_mem_cleanup (ohci); | |
758 | if (ohci->hcca) { | |
dd9048af DB |
759 | dma_free_coherent (hcd->self.controller, |
760 | sizeof *ohci->hcca, | |
1da177e4 LT |
761 | ohci->hcca, ohci->hcca_dma); |
762 | ohci->hcca = NULL; | |
763 | ohci->hcca_dma = 0; | |
764 | } | |
765 | } | |
766 | ||
767 | /*-------------------------------------------------------------------------*/ | |
768 | ||
769 | /* must not be called from interrupt context */ | |
770 | ||
8ad7fe16 | 771 | #ifdef CONFIG_PM |
1da177e4 LT |
772 | |
773 | static int ohci_restart (struct ohci_hcd *ohci) | |
774 | { | |
775 | int temp; | |
776 | int i; | |
777 | struct urb_priv *priv; | |
1da177e4 LT |
778 | |
779 | /* mark any devices gone, so they do nothing till khubd disconnects. | |
780 | * recycle any "live" eds/tds (and urbs) right away. | |
781 | * later, khubd disconnect processing will recycle the other state, | |
782 | * (either as disconnect/reconnect, or maybe someday as a reset). | |
dd9048af | 783 | */ |
1da177e4 LT |
784 | spin_lock_irq(&ohci->lock); |
785 | disable (ohci); | |
1c50c317 | 786 | usb_root_hub_lost_power(ohci_to_hcd(ohci)->self.root_hub); |
1da177e4 LT |
787 | if (!list_empty (&ohci->pending)) |
788 | ohci_dbg(ohci, "abort schedule...\n"); | |
789 | list_for_each_entry (priv, &ohci->pending, pending) { | |
790 | struct urb *urb = priv->td[0]->urb; | |
791 | struct ed *ed = priv->ed; | |
792 | ||
793 | switch (ed->state) { | |
794 | case ED_OPER: | |
795 | ed->state = ED_UNLINK; | |
796 | ed->hwINFO |= cpu_to_hc32(ohci, ED_DEQUEUE); | |
797 | ed_deschedule (ohci, ed); | |
798 | ||
799 | ed->ed_next = ohci->ed_rm_list; | |
800 | ed->ed_prev = NULL; | |
801 | ohci->ed_rm_list = ed; | |
802 | /* FALLTHROUGH */ | |
803 | case ED_UNLINK: | |
804 | break; | |
805 | default: | |
806 | ohci_dbg(ohci, "bogus ed %p state %d\n", | |
807 | ed, ed->state); | |
808 | } | |
809 | ||
810 | spin_lock (&urb->lock); | |
811 | urb->status = -ESHUTDOWN; | |
812 | spin_unlock (&urb->lock); | |
813 | } | |
7d12e780 | 814 | finish_unlinks (ohci, 0); |
1da177e4 LT |
815 | spin_unlock_irq(&ohci->lock); |
816 | ||
817 | /* paranoia, in case that didn't work: */ | |
818 | ||
819 | /* empty the interrupt branches */ | |
820 | for (i = 0; i < NUM_INTS; i++) ohci->load [i] = 0; | |
821 | for (i = 0; i < NUM_INTS; i++) ohci->hcca->int_table [i] = 0; | |
dd9048af | 822 | |
1da177e4 LT |
823 | /* no EDs to remove */ |
824 | ohci->ed_rm_list = NULL; | |
825 | ||
dd9048af | 826 | /* empty control and bulk lists */ |
1da177e4 LT |
827 | ohci->ed_controltail = NULL; |
828 | ohci->ed_bulktail = NULL; | |
829 | ||
830 | if ((temp = ohci_run (ohci)) < 0) { | |
831 | ohci_err (ohci, "can't restart, %d\n", temp); | |
832 | return temp; | |
833 | } else { | |
834 | /* here we "know" root ports should always stay powered, | |
835 | * and that if we try to turn them back on the root hub | |
836 | * will respond to CSC processing. | |
837 | */ | |
fdd13b36 | 838 | i = ohci->num_ports; |
1da177e4 LT |
839 | while (i--) |
840 | ohci_writel (ohci, RH_PS_PSS, | |
839ab1d4 | 841 | &ohci->regs->roothub.portstatus [i]); |
1da177e4 LT |
842 | ohci_dbg (ohci, "restart complete\n"); |
843 | } | |
844 | return 0; | |
845 | } | |
846 | #endif | |
847 | ||
848 | /*-------------------------------------------------------------------------*/ | |
849 | ||
850 | #define DRIVER_INFO DRIVER_VERSION " " DRIVER_DESC | |
851 | ||
852 | MODULE_AUTHOR (DRIVER_AUTHOR); | |
853 | MODULE_DESCRIPTION (DRIVER_INFO); | |
854 | MODULE_LICENSE ("GPL"); | |
855 | ||
856 | #ifdef CONFIG_PCI | |
857 | #include "ohci-pci.c" | |
5e16fabe | 858 | #define PCI_DRIVER ohci_pci_driver |
1da177e4 LT |
859 | #endif |
860 | ||
861 | #ifdef CONFIG_SA1111 | |
862 | #include "ohci-sa1111.c" | |
5e16fabe | 863 | #define SA1111_DRIVER ohci_hcd_sa1111_driver |
1da177e4 LT |
864 | #endif |
865 | ||
3eb0c5f4 BD |
866 | #ifdef CONFIG_ARCH_S3C2410 |
867 | #include "ohci-s3c2410.c" | |
5e16fabe | 868 | #define PLATFORM_DRIVER ohci_hcd_s3c2410_driver |
3eb0c5f4 BD |
869 | #endif |
870 | ||
1da177e4 LT |
871 | #ifdef CONFIG_ARCH_OMAP |
872 | #include "ohci-omap.c" | |
5e16fabe | 873 | #define PLATFORM_DRIVER ohci_hcd_omap_driver |
1da177e4 LT |
874 | #endif |
875 | ||
876 | #ifdef CONFIG_ARCH_LH7A404 | |
877 | #include "ohci-lh7a404.c" | |
5e16fabe | 878 | #define PLATFORM_DRIVER ohci_hcd_lh7a404_driver |
1da177e4 LT |
879 | #endif |
880 | ||
881 | #ifdef CONFIG_PXA27x | |
882 | #include "ohci-pxa27x.c" | |
5e16fabe | 883 | #define PLATFORM_DRIVER ohci_hcd_pxa27x_driver |
1da177e4 LT |
884 | #endif |
885 | ||
a5b7474a LB |
886 | #ifdef CONFIG_ARCH_EP93XX |
887 | #include "ohci-ep93xx.c" | |
5e16fabe | 888 | #define PLATFORM_DRIVER ohci_hcd_ep93xx_driver |
a5b7474a LB |
889 | #endif |
890 | ||
1da177e4 LT |
891 | #ifdef CONFIG_SOC_AU1X00 |
892 | #include "ohci-au1xxx.c" | |
5e16fabe | 893 | #define PLATFORM_DRIVER ohci_hcd_au1xxx_driver |
1da177e4 LT |
894 | #endif |
895 | ||
5151d040 VW |
896 | #ifdef CONFIG_PNX8550 |
897 | #include "ohci-pnx8550.c" | |
5e16fabe | 898 | #define PLATFORM_DRIVER ohci_hcd_pnx8550_driver |
5151d040 VW |
899 | #endif |
900 | ||
1da177e4 LT |
901 | #ifdef CONFIG_USB_OHCI_HCD_PPC_SOC |
902 | #include "ohci-ppc-soc.c" | |
5e16fabe | 903 | #define PLATFORM_DRIVER ohci_hcd_ppc_soc_driver |
1da177e4 LT |
904 | #endif |
905 | ||
58a0cd78 | 906 | #ifdef CONFIG_ARCH_AT91 |
39a269c0 | 907 | #include "ohci-at91.c" |
5e16fabe | 908 | #define PLATFORM_DRIVER ohci_hcd_at91_driver |
39a269c0 AV |
909 | #endif |
910 | ||
60bbfc84 VW |
911 | #ifdef CONFIG_ARCH_PNX4008 |
912 | #include "ohci-pnx4008.c" | |
5e16fabe | 913 | #define PLATFORM_DRIVER usb_hcd_pnx4008_driver |
60bbfc84 VW |
914 | #endif |
915 | ||
5e16fabe | 916 | |
495a678f SM |
917 | #ifdef CONFIG_USB_OHCI_HCD_PPC_OF |
918 | #include "ohci-ppc-of.c" | |
919 | #define OF_PLATFORM_DRIVER ohci_hcd_ppc_of_driver | |
920 | #endif | |
921 | ||
5e16fabe SM |
922 | #if !defined(PCI_DRIVER) && \ |
923 | !defined(PLATFORM_DRIVER) && \ | |
495a678f | 924 | !defined(OF_PLATFORM_DRIVER) && \ |
5e16fabe | 925 | !defined(SA1111_DRIVER) |
1da177e4 LT |
926 | #error "missing bus glue for ohci-hcd" |
927 | #endif | |
5e16fabe SM |
928 | |
929 | static int __init ohci_hcd_mod_init(void) | |
930 | { | |
931 | int retval = 0; | |
5e16fabe SM |
932 | |
933 | if (usb_disabled()) | |
934 | return -ENODEV; | |
935 | ||
936 | printk (KERN_DEBUG "%s: " DRIVER_INFO "\n", hcd_name); | |
937 | pr_debug ("%s: block sizes: ed %Zd td %Zd\n", hcd_name, | |
938 | sizeof (struct ed), sizeof (struct td)); | |
939 | ||
940 | #ifdef PLATFORM_DRIVER | |
941 | retval = platform_driver_register(&PLATFORM_DRIVER); | |
942 | if (retval < 0) | |
de44743b | 943 | goto error_platform; |
5e16fabe SM |
944 | #endif |
945 | ||
495a678f SM |
946 | #ifdef OF_PLATFORM_DRIVER |
947 | retval = of_register_platform_driver(&OF_PLATFORM_DRIVER); | |
948 | if (retval < 0) | |
de44743b | 949 | goto error_of_platform; |
495a678f SM |
950 | #endif |
951 | ||
5e16fabe SM |
952 | #ifdef SA1111_DRIVER |
953 | retval = sa1111_driver_register(&SA1111_DRIVER); | |
954 | if (retval < 0) | |
de44743b | 955 | goto error_sa1111; |
5e16fabe SM |
956 | #endif |
957 | ||
958 | #ifdef PCI_DRIVER | |
959 | retval = pci_register_driver(&PCI_DRIVER); | |
960 | if (retval < 0) | |
de44743b | 961 | goto error_pci; |
5e16fabe SM |
962 | #endif |
963 | ||
964 | return retval; | |
965 | ||
966 | /* Error path */ | |
de44743b BH |
967 | #ifdef PCI_DRIVER |
968 | error_pci: | |
969 | #endif | |
970 | #ifdef SA1111_DRIVER | |
971 | sa1111_driver_unregister(&SA1111_DRIVER); | |
972 | error_sa1111: | |
5e16fabe | 973 | #endif |
495a678f | 974 | #ifdef OF_PLATFORM_DRIVER |
de44743b BH |
975 | of_unregister_platform_driver(&OF_PLATFORM_DRIVER); |
976 | error_of_platform: | |
495a678f | 977 | #endif |
de44743b BH |
978 | #ifdef PLATFORM_DRIVER |
979 | platform_driver_unregister(&PLATFORM_DRIVER); | |
980 | error_platform: | |
5e16fabe SM |
981 | #endif |
982 | return retval; | |
983 | } | |
984 | module_init(ohci_hcd_mod_init); | |
985 | ||
986 | static void __exit ohci_hcd_mod_exit(void) | |
987 | { | |
988 | #ifdef PCI_DRIVER | |
989 | pci_unregister_driver(&PCI_DRIVER); | |
990 | #endif | |
991 | #ifdef SA1111_DRIVER | |
992 | sa1111_driver_unregister(&SA1111_DRIVER); | |
993 | #endif | |
495a678f SM |
994 | #ifdef OF_PLATFORM_DRIVER |
995 | of_unregister_platform_driver(&OF_PLATFORM_DRIVER); | |
996 | #endif | |
5e16fabe SM |
997 | #ifdef PLATFORM_DRIVER |
998 | platform_driver_unregister(&PLATFORM_DRIVER); | |
999 | #endif | |
1000 | } | |
1001 | module_exit(ohci_hcd_mod_exit); | |
1002 |