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Commit | Line | Data |
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5fd54ace | 1 | // SPDX-License-Identifier: GPL-1.0+ |
1da177e4 | 2 | /* |
578333ab AS |
3 | * Open Host Controller Interface (OHCI) driver for USB. |
4 | * | |
5 | * Maintainer: Alan Stern <stern@rowland.harvard.edu> | |
1da177e4 LT |
6 | * |
7 | * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at> | |
8 | * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net> | |
dd9048af | 9 | * |
1da177e4 LT |
10 | * [ Initialisation is based on Linus' ] |
11 | * [ uhci code and gregs ohci fragments ] | |
12 | * [ (C) Copyright 1999 Linus Torvalds ] | |
13 | * [ (C) Copyright 1999 Gregory P. Smith] | |
dd9048af DB |
14 | * |
15 | * | |
1da177e4 LT |
16 | * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller |
17 | * interfaces (though some non-x86 Intel chips use it). It supports | |
18 | * smarter hardware than UHCI. A download link for the spec available | |
19 | * through the http://www.usb.org website. | |
20 | * | |
1da177e4 LT |
21 | * This file is licenced under the GPL. |
22 | */ | |
dd9048af | 23 | |
1da177e4 LT |
24 | #include <linux/module.h> |
25 | #include <linux/moduleparam.h> | |
26 | #include <linux/pci.h> | |
27 | #include <linux/kernel.h> | |
28 | #include <linux/delay.h> | |
29 | #include <linux/ioport.h> | |
30 | #include <linux/sched.h> | |
31 | #include <linux/slab.h> | |
1da177e4 LT |
32 | #include <linux/errno.h> |
33 | #include <linux/init.h> | |
34 | #include <linux/timer.h> | |
35 | #include <linux/list.h> | |
1da177e4 | 36 | #include <linux/usb.h> |
3a16f7b4 | 37 | #include <linux/usb/otg.h> |
27729aad | 38 | #include <linux/usb/hcd.h> |
dd9048af | 39 | #include <linux/dma-mapping.h> |
f4df0e33 | 40 | #include <linux/dmapool.h> |
d576bb9f | 41 | #include <linux/workqueue.h> |
684c19e0 | 42 | #include <linux/debugfs.h> |
1da177e4 LT |
43 | |
44 | #include <asm/io.h> | |
45 | #include <asm/irq.h> | |
1da177e4 LT |
46 | #include <asm/unaligned.h> |
47 | #include <asm/byteorder.h> | |
48 | ||
49 | ||
1da177e4 LT |
50 | #define DRIVER_AUTHOR "Roman Weissgaerber, David Brownell" |
51 | #define DRIVER_DESC "USB 1.1 'Open' Host Controller (OHCI) Driver" | |
52 | ||
53 | /*-------------------------------------------------------------------------*/ | |
54 | ||
1da177e4 | 55 | /* For initializing controller (mask in an HCFS mode too) */ |
d413984a | 56 | #define OHCI_CONTROL_INIT OHCI_CTRL_CBSR |
1da177e4 | 57 | #define OHCI_INTR_INIT \ |
d413984a DB |
58 | (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE \ |
59 | | OHCI_INTR_RD | OHCI_INTR_WDH) | |
1da177e4 LT |
60 | |
61 | #ifdef __hppa__ | |
62 | /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */ | |
63 | #define IR_DISABLE | |
64 | #endif | |
65 | ||
66 | #ifdef CONFIG_ARCH_OMAP | |
67 | /* OMAP doesn't support IR (no SMM; not needed) */ | |
68 | #define IR_DISABLE | |
69 | #endif | |
70 | ||
71 | /*-------------------------------------------------------------------------*/ | |
72 | ||
73 | static const char hcd_name [] = "ohci_hcd"; | |
74 | ||
d413984a | 75 | #define STATECHANGE_DELAY msecs_to_jiffies(300) |
ed6d6f8f | 76 | #define IO_WATCHDOG_DELAY msecs_to_jiffies(275) |
b2685bda | 77 | #define IO_WATCHDOG_OFF 0xffffff00 |
d413984a | 78 | |
1da177e4 | 79 | #include "ohci.h" |
ad93562b | 80 | #include "pci-quirks.h" |
1da177e4 | 81 | |
256dbcd8 AS |
82 | static void ohci_dump(struct ohci_hcd *ohci); |
83 | static void ohci_stop(struct usb_hcd *hcd); | |
e99e88a9 | 84 | static void io_watchdog_func(struct timer_list *t); |
ab1666c1 | 85 | |
1da177e4 LT |
86 | #include "ohci-hub.c" |
87 | #include "ohci-dbg.c" | |
88 | #include "ohci-mem.c" | |
89 | #include "ohci-q.c" | |
90 | ||
91 | ||
92 | /* | |
93 | * On architectures with edge-triggered interrupts we must never return | |
94 | * IRQ_NONE. | |
95 | */ | |
96 | #if defined(CONFIG_SA1111) /* ... or other edge-triggered systems */ | |
97 | #define IRQ_NOTMINE IRQ_HANDLED | |
98 | #else | |
99 | #define IRQ_NOTMINE IRQ_NONE | |
100 | #endif | |
101 | ||
102 | ||
103 | /* Some boards misreport power switching/overcurrent */ | |
900937c0 | 104 | static bool distrust_firmware = true; |
1da177e4 LT |
105 | module_param (distrust_firmware, bool, 0); |
106 | MODULE_PARM_DESC (distrust_firmware, | |
107 | "true to distrust firmware power/overcurrent setup"); | |
108 | ||
109 | /* Some boards leave IR set wrongly, since they fail BIOS/SMM handshakes */ | |
900937c0 | 110 | static bool no_handshake; |
1da177e4 LT |
111 | module_param (no_handshake, bool, 0); |
112 | MODULE_PARM_DESC (no_handshake, "true (not default) disables BIOS handshake"); | |
113 | ||
114 | /*-------------------------------------------------------------------------*/ | |
115 | ||
6f65126c AS |
116 | static int number_of_tds(struct urb *urb) |
117 | { | |
118 | int len, i, num, this_sg_len; | |
119 | struct scatterlist *sg; | |
120 | ||
121 | len = urb->transfer_buffer_length; | |
122 | i = urb->num_mapped_sgs; | |
123 | ||
124 | if (len > 0 && i > 0) { /* Scatter-gather transfer */ | |
125 | num = 0; | |
126 | sg = urb->sg; | |
127 | for (;;) { | |
128 | this_sg_len = min_t(int, sg_dma_len(sg), len); | |
129 | num += DIV_ROUND_UP(this_sg_len, 4096); | |
130 | len -= this_sg_len; | |
131 | if (--i <= 0 || len <= 0) | |
132 | break; | |
133 | sg = sg_next(sg); | |
134 | } | |
135 | ||
136 | } else { /* Non-SG transfer */ | |
137 | /* one TD for every 4096 Bytes (could be up to 8K) */ | |
138 | num = DIV_ROUND_UP(len, 4096); | |
139 | } | |
140 | return num; | |
141 | } | |
142 | ||
1da177e4 LT |
143 | /* |
144 | * queue up an urb for anything except the root hub | |
145 | */ | |
146 | static int ohci_urb_enqueue ( | |
147 | struct usb_hcd *hcd, | |
1da177e4 | 148 | struct urb *urb, |
55016f10 | 149 | gfp_t mem_flags |
1da177e4 LT |
150 | ) { |
151 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); | |
152 | struct ed *ed; | |
153 | urb_priv_t *urb_priv; | |
154 | unsigned int pipe = urb->pipe; | |
155 | int i, size = 0; | |
156 | unsigned long flags; | |
157 | int retval = 0; | |
dd9048af | 158 | |
1da177e4 | 159 | /* every endpoint has a ed, locate and maybe (re)initialize it */ |
71f46340 GKH |
160 | ed = ed_get(ohci, urb->ep, urb->dev, pipe, urb->interval); |
161 | if (! ed) | |
1da177e4 LT |
162 | return -ENOMEM; |
163 | ||
164 | /* for the private part of the URB we need the number of TDs (size) */ | |
165 | switch (ed->type) { | |
166 | case PIPE_CONTROL: | |
167 | /* td_submit_urb() doesn't yet handle these */ | |
168 | if (urb->transfer_buffer_length > 4096) | |
169 | return -EMSGSIZE; | |
170 | ||
171 | /* 1 TD for setup, 1 for ACK, plus ... */ | |
172 | size = 2; | |
173 | /* FALLTHROUGH */ | |
174 | // case PIPE_INTERRUPT: | |
175 | // case PIPE_BULK: | |
176 | default: | |
6f65126c AS |
177 | size += number_of_tds(urb); |
178 | /* maybe a zero-length packet to wrap it up */ | |
1da177e4 LT |
179 | if (size == 0) |
180 | size++; | |
181 | else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0 | |
182 | && (urb->transfer_buffer_length | |
183 | % usb_maxpacket (urb->dev, pipe, | |
184 | usb_pipeout (pipe))) == 0) | |
185 | size++; | |
186 | break; | |
187 | case PIPE_ISOCHRONOUS: /* number of packets from URB */ | |
188 | size = urb->number_of_packets; | |
189 | break; | |
190 | } | |
191 | ||
192 | /* allocate the private part of the URB */ | |
dd00cc48 | 193 | urb_priv = kzalloc (sizeof (urb_priv_t) + size * sizeof (struct td *), |
1da177e4 LT |
194 | mem_flags); |
195 | if (!urb_priv) | |
196 | return -ENOMEM; | |
1da177e4 LT |
197 | INIT_LIST_HEAD (&urb_priv->pending); |
198 | urb_priv->length = size; | |
dd9048af | 199 | urb_priv->ed = ed; |
1da177e4 LT |
200 | |
201 | /* allocate the TDs (deferring hash chain updates) */ | |
202 | for (i = 0; i < size; i++) { | |
203 | urb_priv->td [i] = td_alloc (ohci, mem_flags); | |
204 | if (!urb_priv->td [i]) { | |
205 | urb_priv->length = i; | |
206 | urb_free_priv (ohci, urb_priv); | |
207 | return -ENOMEM; | |
208 | } | |
dd9048af | 209 | } |
1da177e4 LT |
210 | |
211 | spin_lock_irqsave (&ohci->lock, flags); | |
212 | ||
213 | /* don't submit to a dead HC */ | |
541c7d43 | 214 | if (!HCD_HW_ACCESSIBLE(hcd)) { |
8de98402 BH |
215 | retval = -ENODEV; |
216 | goto fail; | |
217 | } | |
b7463c71 | 218 | if (ohci->rh_state != OHCI_RH_RUNNING) { |
1da177e4 LT |
219 | retval = -ENODEV; |
220 | goto fail; | |
221 | } | |
e9df41c5 AS |
222 | retval = usb_hcd_link_urb_to_ep(hcd, urb); |
223 | if (retval) | |
1da177e4 | 224 | goto fail; |
1da177e4 LT |
225 | |
226 | /* schedule the ed if needed */ | |
227 | if (ed->state == ED_IDLE) { | |
228 | retval = ed_schedule (ohci, ed); | |
e9df41c5 AS |
229 | if (retval < 0) { |
230 | usb_hcd_unlink_urb_from_ep(hcd, urb); | |
231 | goto fail; | |
232 | } | |
81e38333 AS |
233 | |
234 | /* Start up the I/O watchdog timer, if it's not running */ | |
b2685bda | 235 | if (ohci->prev_frame_no == IO_WATCHDOG_OFF && |
21a60f6e GH |
236 | list_empty(&ohci->eds_in_use) && |
237 | !(ohci->flags & OHCI_QUIRK_QEMU)) { | |
499b3803 | 238 | ohci->prev_frame_no = ohci_frame_no(ohci); |
81e38333 AS |
239 | mod_timer(&ohci->io_watchdog, |
240 | jiffies + IO_WATCHDOG_DELAY); | |
499b3803 | 241 | } |
81e38333 AS |
242 | list_add(&ed->in_use_list, &ohci->eds_in_use); |
243 | ||
1da177e4 LT |
244 | if (ed->type == PIPE_ISOCHRONOUS) { |
245 | u16 frame = ohci_frame_no(ohci); | |
246 | ||
247 | /* delay a few frames before the first TD */ | |
248 | frame += max_t (u16, 8, ed->interval); | |
249 | frame &= ~(ed->interval - 1); | |
250 | frame |= ed->branch; | |
251 | urb->start_frame = frame; | |
a8693424 | 252 | ed->last_iso = frame + ed->interval * (size - 1); |
6a41b4d3 AS |
253 | } |
254 | } else if (ed->type == PIPE_ISOCHRONOUS) { | |
e1944017 | 255 | u16 next = ohci_frame_no(ohci) + 1; |
6a41b4d3 | 256 | u16 frame = ed->last_iso + ed->interval; |
a8693424 | 257 | u16 length = ed->interval * (size - 1); |
6a41b4d3 AS |
258 | |
259 | /* Behind the scheduling threshold? */ | |
260 | if (unlikely(tick_before(frame, next))) { | |
261 | ||
a8693424 | 262 | /* URB_ISO_ASAP: Round up to the first available slot */ |
815fa7b9 | 263 | if (urb->transfer_flags & URB_ISO_ASAP) { |
6a41b4d3 AS |
264 | frame += (next - frame + ed->interval - 1) & |
265 | -ed->interval; | |
1da177e4 | 266 | |
6a41b4d3 | 267 | /* |
a8693424 AS |
268 | * Not ASAP: Use the next slot in the stream, |
269 | * no matter what. | |
1da177e4 | 270 | */ |
815fa7b9 | 271 | } else { |
815fa7b9 AS |
272 | /* |
273 | * Some OHCI hardware doesn't handle late TDs | |
274 | * correctly. After retiring them it proceeds | |
275 | * to the next ED instead of the next TD. | |
276 | * Therefore we have to omit the late TDs | |
277 | * entirely. | |
278 | */ | |
279 | urb_priv->td_cnt = DIV_ROUND_UP( | |
280 | (u16) (next - frame), | |
281 | ed->interval); | |
a8693424 AS |
282 | if (urb_priv->td_cnt >= urb_priv->length) { |
283 | ++urb_priv->td_cnt; /* Mark it */ | |
284 | ohci_dbg(ohci, "iso underrun %p (%u+%u < %u)\n", | |
285 | urb, frame, length, | |
286 | next); | |
287 | } | |
6a41b4d3 | 288 | } |
1da177e4 | 289 | } |
6a41b4d3 | 290 | urb->start_frame = frame; |
a8693424 | 291 | ed->last_iso = frame + length; |
6a41b4d3 | 292 | } |
1da177e4 LT |
293 | |
294 | /* fill the TDs and link them to the ed; and | |
295 | * enable that part of the schedule, if needed | |
296 | * and update count of queued periodic urbs | |
297 | */ | |
298 | urb->hcpriv = urb_priv; | |
299 | td_submit_urb (ohci, urb); | |
300 | ||
1da177e4 LT |
301 | fail: |
302 | if (retval) | |
303 | urb_free_priv (ohci, urb_priv); | |
304 | spin_unlock_irqrestore (&ohci->lock, flags); | |
305 | return retval; | |
306 | } | |
307 | ||
308 | /* | |
55d84968 AS |
309 | * decouple the URB from the HC queues (TDs, urb_priv). |
310 | * reporting is always done | |
1da177e4 LT |
311 | * asynchronously, and we might be dealing with an urb that's |
312 | * partially transferred, or an ED with other urbs being unlinked. | |
313 | */ | |
e9df41c5 | 314 | static int ohci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) |
1da177e4 LT |
315 | { |
316 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); | |
317 | unsigned long flags; | |
e9df41c5 | 318 | int rc; |
8b3ab0ed | 319 | urb_priv_t *urb_priv; |
dd9048af | 320 | |
1da177e4 | 321 | spin_lock_irqsave (&ohci->lock, flags); |
e9df41c5 | 322 | rc = usb_hcd_check_unlink_urb(hcd, urb, status); |
8b3ab0ed | 323 | if (rc == 0) { |
1da177e4 LT |
324 | |
325 | /* Unless an IRQ completed the unlink while it was being | |
326 | * handed to us, flag it for unlink and giveback, and force | |
327 | * some upcoming INTR_SF to call finish_unlinks() | |
328 | */ | |
329 | urb_priv = urb->hcpriv; | |
8b3ab0ed AS |
330 | if (urb_priv->ed->state == ED_OPER) |
331 | start_ed_unlink(ohci, urb_priv->ed); | |
332 | ||
333 | if (ohci->rh_state != OHCI_RH_RUNNING) { | |
334 | /* With HC dead, we can clean up right away */ | |
cdb4dd15 | 335 | ohci_work(ohci); |
1da177e4 | 336 | } |
1da177e4 LT |
337 | } |
338 | spin_unlock_irqrestore (&ohci->lock, flags); | |
e9df41c5 | 339 | return rc; |
1da177e4 LT |
340 | } |
341 | ||
342 | /*-------------------------------------------------------------------------*/ | |
343 | ||
344 | /* frees config/altsetting state for endpoints, | |
345 | * including ED memory, dummy TD, and bulk/intr data toggle | |
346 | */ | |
347 | ||
348 | static void | |
349 | ohci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep) | |
350 | { | |
351 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); | |
352 | unsigned long flags; | |
353 | struct ed *ed = ep->hcpriv; | |
354 | unsigned limit = 1000; | |
355 | ||
356 | /* ASSERT: any requests/urbs are being unlinked */ | |
357 | /* ASSERT: nobody can be submitting urbs for this any more */ | |
358 | ||
359 | if (!ed) | |
360 | return; | |
361 | ||
362 | rescan: | |
363 | spin_lock_irqsave (&ohci->lock, flags); | |
364 | ||
b7463c71 | 365 | if (ohci->rh_state != OHCI_RH_RUNNING) { |
1da177e4 LT |
366 | sanitize: |
367 | ed->state = ED_IDLE; | |
cdb4dd15 | 368 | ohci_work(ohci); |
1da177e4 LT |
369 | } |
370 | ||
371 | switch (ed->state) { | |
372 | case ED_UNLINK: /* wait for hw to finish? */ | |
373 | /* major IRQ delivery trouble loses INTR_SF too... */ | |
374 | if (limit-- == 0) { | |
89a0fd18 | 375 | ohci_warn(ohci, "ED unlink timeout\n"); |
1da177e4 LT |
376 | goto sanitize; |
377 | } | |
378 | spin_unlock_irqrestore (&ohci->lock, flags); | |
22c43863 | 379 | schedule_timeout_uninterruptible(1); |
1da177e4 LT |
380 | goto rescan; |
381 | case ED_IDLE: /* fully unlinked */ | |
382 | if (list_empty (&ed->td_list)) { | |
383 | td_free (ohci, ed->dummy); | |
384 | ed_free (ohci, ed); | |
385 | break; | |
386 | } | |
f5a3908e | 387 | /* fall through */ |
1da177e4 LT |
388 | default: |
389 | /* caller was supposed to have unlinked any requests; | |
390 | * that's not our job. can't recover; must leak ed. | |
391 | */ | |
392 | ohci_err (ohci, "leak ed %p (#%02x) state %d%s\n", | |
393 | ed, ep->desc.bEndpointAddress, ed->state, | |
394 | list_empty (&ed->td_list) ? "" : " (has tds)"); | |
395 | td_free (ohci, ed->dummy); | |
396 | break; | |
397 | } | |
398 | ep->hcpriv = NULL; | |
399 | spin_unlock_irqrestore (&ohci->lock, flags); | |
1da177e4 LT |
400 | } |
401 | ||
402 | static int ohci_get_frame (struct usb_hcd *hcd) | |
403 | { | |
404 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); | |
405 | ||
406 | return ohci_frame_no(ohci); | |
407 | } | |
408 | ||
409 | static void ohci_usb_reset (struct ohci_hcd *ohci) | |
410 | { | |
411 | ohci->hc_control = ohci_readl (ohci, &ohci->regs->control); | |
412 | ohci->hc_control &= OHCI_CTRL_RWC; | |
413 | ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); | |
b7463c71 | 414 | ohci->rh_state = OHCI_RH_HALTED; |
1da177e4 LT |
415 | } |
416 | ||
64a21d02 | 417 | /* ohci_shutdown forcibly disables IRQs and DMA, helping kexec and |
f4df0e33 DB |
418 | * other cases where the next software may expect clean state from the |
419 | * "firmware". this is bus-neutral, unlike shutdown() methods. | |
420 | */ | |
64a21d02 AG |
421 | static void |
422 | ohci_shutdown (struct usb_hcd *hcd) | |
f4df0e33 DB |
423 | { |
424 | struct ohci_hcd *ohci; | |
425 | ||
64a21d02 | 426 | ohci = hcd_to_ohci (hcd); |
c6187597 | 427 | ohci_writel(ohci, (u32) ~0, &ohci->regs->intrdisable); |
3df7169e | 428 | |
c6187597 AS |
429 | /* Software reset, after which the controller goes into SUSPEND */ |
430 | ohci_writel(ohci, OHCI_HCR, &ohci->regs->cmdstatus); | |
431 | ohci_readl(ohci, &ohci->regs->cmdstatus); /* flush the writes */ | |
432 | udelay(10); | |
3df7169e | 433 | |
c6187597 | 434 | ohci_writel(ohci, ohci->fminterval, &ohci->regs->fminterval); |
81e38333 | 435 | ohci->rh_state = OHCI_RH_HALTED; |
f4df0e33 DB |
436 | } |
437 | ||
1da177e4 LT |
438 | /*-------------------------------------------------------------------------* |
439 | * HC functions | |
440 | *-------------------------------------------------------------------------*/ | |
441 | ||
442 | /* init memory, and kick BIOS/SMM off */ | |
443 | ||
444 | static int ohci_init (struct ohci_hcd *ohci) | |
445 | { | |
446 | int ret; | |
6a9062f3 | 447 | struct usb_hcd *hcd = ohci_to_hcd(ohci); |
1da177e4 | 448 | |
6f65126c | 449 | /* Accept arbitrarily long scatter-gather lists */ |
d6c931ea FN |
450 | if (!(hcd->driver->flags & HCD_LOCAL_MEM)) |
451 | hcd->self.sg_tablesize = ~0; | |
6f65126c | 452 | |
1133cd8a DES |
453 | if (distrust_firmware) |
454 | ohci->flags |= OHCI_QUIRK_HUB_POWER; | |
455 | ||
b7463c71 | 456 | ohci->rh_state = OHCI_RH_HALTED; |
6a9062f3 | 457 | ohci->regs = hcd->regs; |
1da177e4 | 458 | |
6a9062f3 DB |
459 | /* REVISIT this BIOS handshake is now moved into PCI "quirks", and |
460 | * was never needed for most non-PCI systems ... remove the code? | |
461 | */ | |
462 | ||
1da177e4 LT |
463 | #ifndef IR_DISABLE |
464 | /* SMM owns the HC? not for long! */ | |
465 | if (!no_handshake && ohci_readl (ohci, | |
466 | &ohci->regs->control) & OHCI_CTRL_IR) { | |
467 | u32 temp; | |
468 | ||
469 | ohci_dbg (ohci, "USB HC TakeOver from BIOS/SMM\n"); | |
470 | ||
471 | /* this timeout is arbitrary. we make it long, so systems | |
472 | * depending on usb keyboards may be usable even if the | |
473 | * BIOS/SMM code seems pretty broken. | |
474 | */ | |
475 | temp = 500; /* arbitrary: five seconds */ | |
476 | ||
477 | ohci_writel (ohci, OHCI_INTR_OC, &ohci->regs->intrenable); | |
478 | ohci_writel (ohci, OHCI_OCR, &ohci->regs->cmdstatus); | |
479 | while (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_IR) { | |
480 | msleep (10); | |
481 | if (--temp == 0) { | |
482 | ohci_err (ohci, "USB HC takeover failed!" | |
483 | " (BIOS/SMM bug)\n"); | |
484 | return -EBUSY; | |
485 | } | |
486 | } | |
487 | ohci_usb_reset (ohci); | |
488 | } | |
489 | #endif | |
490 | ||
491 | /* Disable HC interrupts */ | |
492 | ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable); | |
6a9062f3 DB |
493 | |
494 | /* flush the writes, and save key bits like RWC */ | |
495 | if (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_RWC) | |
496 | ohci->hc_control |= OHCI_CTRL_RWC; | |
1da177e4 | 497 | |
fdd13b36 DB |
498 | /* Read the number of ports unless overridden */ |
499 | if (ohci->num_ports == 0) | |
500 | ohci->num_ports = roothub_a(ohci) & RH_A_NDP; | |
501 | ||
1da177e4 LT |
502 | if (ohci->hcca) |
503 | return 0; | |
504 | ||
e99e88a9 | 505 | timer_setup(&ohci->io_watchdog, io_watchdog_func, 0); |
b2685bda | 506 | ohci->prev_frame_no = IO_WATCHDOG_OFF; |
81e38333 | 507 | |
6a9062f3 | 508 | ohci->hcca = dma_alloc_coherent (hcd->self.controller, |
4428524d | 509 | sizeof(*ohci->hcca), &ohci->hcca_dma, GFP_KERNEL); |
1da177e4 LT |
510 | if (!ohci->hcca) |
511 | return -ENOMEM; | |
512 | ||
513 | if ((ret = ohci_mem_init (ohci)) < 0) | |
6a9062f3 DB |
514 | ohci_stop (hcd); |
515 | else { | |
6a9062f3 DB |
516 | create_debug_files (ohci); |
517 | } | |
1da177e4 LT |
518 | |
519 | return ret; | |
1da177e4 LT |
520 | } |
521 | ||
522 | /*-------------------------------------------------------------------------*/ | |
523 | ||
524 | /* Start an OHCI controller, set the BUS operational | |
525 | * resets USB and controller | |
dd9048af | 526 | * enable interrupts |
1da177e4 LT |
527 | */ |
528 | static int ohci_run (struct ohci_hcd *ohci) | |
529 | { | |
96f90a8b | 530 | u32 mask, val; |
1da177e4 | 531 | int first = ohci->fminterval == 0; |
6a9062f3 | 532 | struct usb_hcd *hcd = ohci_to_hcd(ohci); |
1da177e4 | 533 | |
b7463c71 | 534 | ohci->rh_state = OHCI_RH_HALTED; |
1da177e4 LT |
535 | |
536 | /* boot firmware should have set this up (5.1.1.3.1) */ | |
537 | if (first) { | |
538 | ||
96f90a8b HS |
539 | val = ohci_readl (ohci, &ohci->regs->fminterval); |
540 | ohci->fminterval = val & 0x3fff; | |
1da177e4 LT |
541 | if (ohci->fminterval != FI) |
542 | ohci_dbg (ohci, "fminterval delta %d\n", | |
543 | ohci->fminterval - FI); | |
544 | ohci->fminterval |= FSMP (ohci->fminterval) << 16; | |
545 | /* also: power/overcurrent flags in roothub.a */ | |
546 | } | |
547 | ||
6fd9086a AS |
548 | /* Reset USB nearly "by the book". RemoteWakeupConnected has |
549 | * to be checked in case boot firmware (BIOS/SMM/...) has set up | |
550 | * wakeup in a way the bus isn't aware of (e.g., legacy PCI PM). | |
551 | * If the bus glue detected wakeup capability then it should | |
bcca06ef | 552 | * already be enabled; if so we'll just enable it again. |
1da177e4 | 553 | */ |
bcca06ef AS |
554 | if ((ohci->hc_control & OHCI_CTRL_RWC) != 0) |
555 | device_set_wakeup_capable(hcd->self.controller, 1); | |
1da177e4 LT |
556 | |
557 | switch (ohci->hc_control & OHCI_CTRL_HCFS) { | |
558 | case OHCI_USB_OPER: | |
96f90a8b | 559 | val = 0; |
1da177e4 LT |
560 | break; |
561 | case OHCI_USB_SUSPEND: | |
562 | case OHCI_USB_RESUME: | |
563 | ohci->hc_control &= OHCI_CTRL_RWC; | |
564 | ohci->hc_control |= OHCI_USB_RESUME; | |
96f90a8b | 565 | val = 10 /* msec wait */; |
1da177e4 LT |
566 | break; |
567 | // case OHCI_USB_RESET: | |
568 | default: | |
569 | ohci->hc_control &= OHCI_CTRL_RWC; | |
570 | ohci->hc_control |= OHCI_USB_RESET; | |
96f90a8b | 571 | val = 50 /* msec wait */; |
1da177e4 LT |
572 | break; |
573 | } | |
574 | ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); | |
575 | // flush the writes | |
576 | (void) ohci_readl (ohci, &ohci->regs->control); | |
96f90a8b | 577 | msleep(val); |
383975d7 | 578 | |
1da177e4 LT |
579 | memset (ohci->hcca, 0, sizeof (struct ohci_hcca)); |
580 | ||
581 | /* 2msec timelimit here means no irqs/preempt */ | |
582 | spin_lock_irq (&ohci->lock); | |
583 | ||
584 | retry: | |
585 | /* HC Reset requires max 10 us delay */ | |
586 | ohci_writel (ohci, OHCI_HCR, &ohci->regs->cmdstatus); | |
96f90a8b | 587 | val = 30; /* ... allow extra time */ |
1da177e4 | 588 | while ((ohci_readl (ohci, &ohci->regs->cmdstatus) & OHCI_HCR) != 0) { |
96f90a8b | 589 | if (--val == 0) { |
1da177e4 LT |
590 | spin_unlock_irq (&ohci->lock); |
591 | ohci_err (ohci, "USB HC reset timed out!\n"); | |
592 | return -1; | |
593 | } | |
594 | udelay (1); | |
595 | } | |
596 | ||
597 | /* now we're in the SUSPEND state ... must go OPERATIONAL | |
598 | * within 2msec else HC enters RESUME | |
599 | * | |
600 | * ... but some hardware won't init fmInterval "by the book" | |
601 | * (SiS, OPTi ...), so reset again instead. SiS doesn't need | |
602 | * this if we write fmInterval after we're OPERATIONAL. | |
603 | * Unclear about ALi, ServerWorks, and others ... this could | |
604 | * easily be a longstanding bug in chip init on Linux. | |
605 | */ | |
606 | if (ohci->flags & OHCI_QUIRK_INITRESET) { | |
607 | ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); | |
608 | // flush those writes | |
609 | (void) ohci_readl (ohci, &ohci->regs->control); | |
610 | } | |
611 | ||
612 | /* Tell the controller where the control and bulk lists are | |
613 | * The lists are empty now. */ | |
614 | ohci_writel (ohci, 0, &ohci->regs->ed_controlhead); | |
615 | ohci_writel (ohci, 0, &ohci->regs->ed_bulkhead); | |
616 | ||
617 | /* a reset clears this */ | |
618 | ohci_writel (ohci, (u32) ohci->hcca_dma, &ohci->regs->hcca); | |
619 | ||
620 | periodic_reinit (ohci); | |
621 | ||
622 | /* some OHCI implementations are finicky about how they init. | |
623 | * bogus values here mean not even enumeration could work. | |
624 | */ | |
625 | if ((ohci_readl (ohci, &ohci->regs->fminterval) & 0x3fff0000) == 0 | |
626 | || !ohci_readl (ohci, &ohci->regs->periodicstart)) { | |
627 | if (!(ohci->flags & OHCI_QUIRK_INITRESET)) { | |
628 | ohci->flags |= OHCI_QUIRK_INITRESET; | |
629 | ohci_dbg (ohci, "enabling initreset quirk\n"); | |
630 | goto retry; | |
631 | } | |
632 | spin_unlock_irq (&ohci->lock); | |
633 | ohci_err (ohci, "init err (%08x %04x)\n", | |
634 | ohci_readl (ohci, &ohci->regs->fminterval), | |
635 | ohci_readl (ohci, &ohci->regs->periodicstart)); | |
636 | return -EOVERFLOW; | |
637 | } | |
638 | ||
37ebb549 | 639 | /* use rhsc irqs after hub_wq is allocated */ |
541c7d43 | 640 | set_bit(HCD_FLAG_POLL_RH, &hcd->flags); |
d413984a DB |
641 | hcd->uses_new_polling = 1; |
642 | ||
643 | /* start controller operations */ | |
1da177e4 | 644 | ohci->hc_control &= OHCI_CTRL_RWC; |
d413984a DB |
645 | ohci->hc_control |= OHCI_CONTROL_INIT | OHCI_USB_OPER; |
646 | ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); | |
b7463c71 | 647 | ohci->rh_state = OHCI_RH_RUNNING; |
1da177e4 LT |
648 | |
649 | /* wake on ConnectStatusChange, matching external hubs */ | |
650 | ohci_writel (ohci, RH_HS_DRWE, &ohci->regs->roothub.status); | |
651 | ||
652 | /* Choose the interrupts we care about now, others later on demand */ | |
653 | mask = OHCI_INTR_INIT; | |
d413984a | 654 | ohci_writel (ohci, ~0, &ohci->regs->intrstatus); |
1da177e4 LT |
655 | ohci_writel (ohci, mask, &ohci->regs->intrenable); |
656 | ||
657 | /* handle root hub init quirks ... */ | |
96f90a8b HS |
658 | val = roothub_a (ohci); |
659 | val &= ~(RH_A_PSM | RH_A_OCPM); | |
1da177e4 LT |
660 | if (ohci->flags & OHCI_QUIRK_SUPERIO) { |
661 | /* NSC 87560 and maybe others */ | |
96f90a8b HS |
662 | val |= RH_A_NOCP; |
663 | val &= ~(RH_A_POTPGT | RH_A_NPS); | |
664 | ohci_writel (ohci, val, &ohci->regs->roothub.a); | |
1133cd8a DES |
665 | } else if ((ohci->flags & OHCI_QUIRK_AMD756) || |
666 | (ohci->flags & OHCI_QUIRK_HUB_POWER)) { | |
1da177e4 LT |
667 | /* hub power always on; required for AMD-756 and some |
668 | * Mac platforms. ganged overcurrent reporting, if any. | |
669 | */ | |
96f90a8b HS |
670 | val |= RH_A_NPS; |
671 | ohci_writel (ohci, val, &ohci->regs->roothub.a); | |
1da177e4 LT |
672 | } |
673 | ohci_writel (ohci, RH_HS_LPSC, &ohci->regs->roothub.status); | |
96f90a8b | 674 | ohci_writel (ohci, (val & RH_A_NPS) ? 0 : RH_B_PPCM, |
1da177e4 LT |
675 | &ohci->regs->roothub.b); |
676 | // flush those writes | |
677 | (void) ohci_readl (ohci, &ohci->regs->control); | |
678 | ||
d413984a | 679 | ohci->next_statechange = jiffies + STATECHANGE_DELAY; |
1da177e4 LT |
680 | spin_unlock_irq (&ohci->lock); |
681 | ||
682 | // POTPGT delay is bits 24-31, in 2 ms units. | |
96f90a8b | 683 | mdelay ((val >> 23) & 0x1fe); |
1da177e4 | 684 | |
256dbcd8 | 685 | ohci_dump(ohci); |
1da177e4 | 686 | |
1da177e4 LT |
687 | return 0; |
688 | } | |
689 | ||
95e44d44 MG |
690 | /* ohci_setup routine for generic controller initialization */ |
691 | ||
692 | int ohci_setup(struct usb_hcd *hcd) | |
693 | { | |
694 | struct ohci_hcd *ohci = hcd_to_ohci(hcd); | |
695 | ||
696 | ohci_hcd_init(ohci); | |
697 | ||
698 | return ohci_init(ohci); | |
699 | } | |
700 | EXPORT_SYMBOL_GPL(ohci_setup); | |
701 | ||
702 | /* ohci_start routine for generic controller start of all OHCI bus glue */ | |
703 | static int ohci_start(struct usb_hcd *hcd) | |
704 | { | |
705 | struct ohci_hcd *ohci = hcd_to_ohci(hcd); | |
706 | int ret; | |
707 | ||
708 | ret = ohci_run(ohci); | |
709 | if (ret < 0) { | |
710 | ohci_err(ohci, "can't start\n"); | |
711 | ohci_stop(hcd); | |
712 | } | |
713 | return ret; | |
714 | } | |
715 | ||
1da177e4 LT |
716 | /*-------------------------------------------------------------------------*/ |
717 | ||
81e38333 AS |
718 | /* |
719 | * Some OHCI controllers are known to lose track of completed TDs. They | |
720 | * don't add the TDs to the hardware done queue, which means we never see | |
721 | * them as being completed. | |
722 | * | |
723 | * This watchdog routine checks for such problems. Without some way to | |
724 | * tell when those TDs have completed, we would never take their EDs off | |
725 | * the unlink list. As a result, URBs could never be dequeued and | |
726 | * endpoints could never be released. | |
727 | */ | |
e99e88a9 | 728 | static void io_watchdog_func(struct timer_list *t) |
81e38333 | 729 | { |
e99e88a9 | 730 | struct ohci_hcd *ohci = from_timer(ohci, t, io_watchdog); |
81e38333 AS |
731 | bool takeback_all_pending = false; |
732 | u32 status; | |
733 | u32 head; | |
734 | struct ed *ed; | |
735 | struct td *td, *td_start, *td_next; | |
b2685bda | 736 | unsigned frame_no, prev_frame_no = IO_WATCHDOG_OFF; |
81e38333 AS |
737 | unsigned long flags; |
738 | ||
739 | spin_lock_irqsave(&ohci->lock, flags); | |
740 | ||
741 | /* | |
742 | * One way to lose track of completed TDs is if the controller | |
743 | * never writes back the done queue head. If it hasn't been | |
744 | * written back since the last time this function ran and if it | |
745 | * was non-empty at that time, something is badly wrong with the | |
746 | * hardware. | |
747 | */ | |
748 | status = ohci_readl(ohci, &ohci->regs->intrstatus); | |
749 | if (!(status & OHCI_INTR_WDH) && ohci->wdh_cnt == ohci->prev_wdh_cnt) { | |
750 | if (ohci->prev_donehead) { | |
751 | ohci_err(ohci, "HcDoneHead not written back; disabled\n"); | |
499b3803 | 752 | died: |
81e38333 AS |
753 | usb_hc_died(ohci_to_hcd(ohci)); |
754 | ohci_dump(ohci); | |
755 | ohci_shutdown(ohci_to_hcd(ohci)); | |
756 | goto done; | |
757 | } else { | |
758 | /* No write back because the done queue was empty */ | |
759 | takeback_all_pending = true; | |
760 | } | |
761 | } | |
762 | ||
763 | /* Check every ED which might have pending TDs */ | |
764 | list_for_each_entry(ed, &ohci->eds_in_use, in_use_list) { | |
765 | if (ed->pending_td) { | |
766 | if (takeback_all_pending || | |
767 | OKAY_TO_TAKEBACK(ohci, ed)) { | |
768 | unsigned tmp = hc32_to_cpu(ohci, ed->hwINFO); | |
769 | ||
770 | ohci_dbg(ohci, "takeback pending TD for dev %d ep 0x%x\n", | |
771 | 0x007f & tmp, | |
772 | (0x000f & (tmp >> 7)) + | |
773 | ((tmp & ED_IN) >> 5)); | |
774 | add_to_done_list(ohci, ed->pending_td); | |
775 | } | |
776 | } | |
777 | ||
778 | /* Starting from the latest pending TD, */ | |
779 | td = ed->pending_td; | |
780 | ||
781 | /* or the last TD on the done list, */ | |
782 | if (!td) { | |
783 | list_for_each_entry(td_next, &ed->td_list, td_list) { | |
784 | if (!td_next->next_dl_td) | |
785 | break; | |
786 | td = td_next; | |
787 | } | |
788 | } | |
789 | ||
790 | /* find the last TD processed by the controller. */ | |
6aa7de05 | 791 | head = hc32_to_cpu(ohci, READ_ONCE(ed->hwHeadP)) & TD_MASK; |
81e38333 AS |
792 | td_start = td; |
793 | td_next = list_prepare_entry(td, &ed->td_list, td_list); | |
794 | list_for_each_entry_continue(td_next, &ed->td_list, td_list) { | |
795 | if (head == (u32) td_next->td_dma) | |
796 | break; | |
797 | td = td_next; /* head pointer has passed this TD */ | |
798 | } | |
799 | if (td != td_start) { | |
800 | /* | |
801 | * In case a WDH cycle is in progress, we will wait | |
802 | * for the next two cycles to complete before assuming | |
803 | * this TD will never get on the done queue. | |
804 | */ | |
805 | ed->takeback_wdh_cnt = ohci->wdh_cnt + 2; | |
806 | ed->pending_td = td; | |
807 | } | |
808 | } | |
809 | ||
810 | ohci_work(ohci); | |
811 | ||
812 | if (ohci->rh_state == OHCI_RH_RUNNING) { | |
499b3803 AS |
813 | |
814 | /* | |
815 | * Sometimes a controller just stops working. We can tell | |
816 | * by checking that the frame counter has advanced since | |
817 | * the last time we ran. | |
818 | * | |
819 | * But be careful: Some controllers violate the spec by | |
820 | * stopping their frame counter when no ports are active. | |
821 | */ | |
822 | frame_no = ohci_frame_no(ohci); | |
823 | if (frame_no == ohci->prev_frame_no) { | |
824 | int active_cnt = 0; | |
825 | int i; | |
826 | unsigned tmp; | |
827 | ||
828 | for (i = 0; i < ohci->num_ports; ++i) { | |
829 | tmp = roothub_portstatus(ohci, i); | |
830 | /* Enabled and not suspended? */ | |
831 | if ((tmp & RH_PS_PES) && !(tmp & RH_PS_PSS)) | |
832 | ++active_cnt; | |
833 | } | |
834 | ||
835 | if (active_cnt > 0) { | |
836 | ohci_err(ohci, "frame counter not updating; disabled\n"); | |
837 | goto died; | |
838 | } | |
839 | } | |
81e38333 | 840 | if (!list_empty(&ohci->eds_in_use)) { |
b2685bda | 841 | prev_frame_no = frame_no; |
81e38333 AS |
842 | ohci->prev_wdh_cnt = ohci->wdh_cnt; |
843 | ohci->prev_donehead = ohci_readl(ohci, | |
844 | &ohci->regs->donehead); | |
845 | mod_timer(&ohci->io_watchdog, | |
846 | jiffies + IO_WATCHDOG_DELAY); | |
847 | } | |
848 | } | |
849 | ||
850 | done: | |
b2685bda | 851 | ohci->prev_frame_no = prev_frame_no; |
81e38333 AS |
852 | spin_unlock_irqrestore(&ohci->lock, flags); |
853 | } | |
854 | ||
1da177e4 LT |
855 | /* an interrupt happens */ |
856 | ||
7d12e780 | 857 | static irqreturn_t ohci_irq (struct usb_hcd *hcd) |
1da177e4 LT |
858 | { |
859 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); | |
860 | struct ohci_regs __iomem *regs = ohci->regs; | |
89a0fd18 | 861 | int ints; |
1da177e4 | 862 | |
565227c0 BH |
863 | /* Read interrupt status (and flush pending writes). We ignore the |
864 | * optimization of checking the LSB of hcca->done_head; it doesn't | |
865 | * work on all systems (edge triggering for OHCI can be a factor). | |
89a0fd18 | 866 | */ |
565227c0 | 867 | ints = ohci_readl(ohci, ®s->intrstatus); |
1da177e4 | 868 | |
565227c0 BH |
869 | /* Check for an all 1's result which is a typical consequence |
870 | * of dead, unclocked, or unplugged (CardBus...) devices | |
871 | */ | |
872 | if (ints == ~(u32)0) { | |
b7463c71 | 873 | ohci->rh_state = OHCI_RH_HALTED; |
1da177e4 | 874 | ohci_dbg (ohci, "device removed!\n"); |
69fff59d | 875 | usb_hc_died(hcd); |
1da177e4 | 876 | return IRQ_HANDLED; |
565227c0 BH |
877 | } |
878 | ||
879 | /* We only care about interrupts that are enabled */ | |
880 | ints &= ohci_readl(ohci, ®s->intrenable); | |
1da177e4 LT |
881 | |
882 | /* interrupt for some other device? */ | |
b7463c71 | 883 | if (ints == 0 || unlikely(ohci->rh_state == OHCI_RH_HALTED)) |
1da177e4 | 884 | return IRQ_NOTMINE; |
d413984a | 885 | |
1da177e4 | 886 | if (ints & OHCI_INTR_UE) { |
1da177e4 | 887 | // e.g. due to PCI Master/Target Abort |
89a0fd18 | 888 | if (quirk_nec(ohci)) { |
d576bb9f MH |
889 | /* Workaround for a silicon bug in some NEC chips used |
890 | * in Apple's PowerBooks. Adapted from Darwin code. | |
891 | */ | |
892 | ohci_err (ohci, "OHCI Unrecoverable Error, scheduling NEC chip restart\n"); | |
893 | ||
894 | ohci_writel (ohci, OHCI_INTR_UE, ®s->intrdisable); | |
895 | ||
896 | schedule_work (&ohci->nec_work); | |
897 | } else { | |
d576bb9f | 898 | ohci_err (ohci, "OHCI Unrecoverable Error, disabled\n"); |
b7463c71 | 899 | ohci->rh_state = OHCI_RH_HALTED; |
69fff59d | 900 | usb_hc_died(hcd); |
d576bb9f | 901 | } |
1da177e4 | 902 | |
256dbcd8 | 903 | ohci_dump(ohci); |
1da177e4 LT |
904 | ohci_usb_reset (ohci); |
905 | } | |
906 | ||
583ceada | 907 | if (ints & OHCI_INTR_RHSC) { |
d2c4254f | 908 | ohci_dbg(ohci, "rhsc\n"); |
583ceada AS |
909 | ohci->next_statechange = jiffies + STATECHANGE_DELAY; |
910 | ohci_writel(ohci, OHCI_INTR_RD | OHCI_INTR_RHSC, | |
911 | ®s->intrstatus); | |
052ac01a AS |
912 | |
913 | /* NOTE: Vendors didn't always make the same implementation | |
914 | * choices for RHSC. Many followed the spec; RHSC triggers | |
915 | * on an edge, like setting and maybe clearing a port status | |
916 | * change bit. With others it's level-triggered, active | |
37ebb549 PM |
917 | * until hub_wq clears all the port status change bits. We'll |
918 | * always disable it here and rely on polling until hub_wq | |
052ac01a AS |
919 | * re-enables it. |
920 | */ | |
921 | ohci_writel(ohci, OHCI_INTR_RHSC, ®s->intrdisable); | |
583ceada AS |
922 | usb_hcd_poll_rh_status(hcd); |
923 | } | |
924 | ||
925 | /* For connect and disconnect events, we expect the controller | |
926 | * to turn on RHSC along with RD. But for remote wakeup events | |
927 | * this might not happen. | |
928 | */ | |
929 | else if (ints & OHCI_INTR_RD) { | |
d2c4254f | 930 | ohci_dbg(ohci, "resume detect\n"); |
583ceada | 931 | ohci_writel(ohci, OHCI_INTR_RD, ®s->intrstatus); |
541c7d43 | 932 | set_bit(HCD_FLAG_POLL_RH, &hcd->flags); |
8d1a243b AS |
933 | if (ohci->autostop) { |
934 | spin_lock (&ohci->lock); | |
935 | ohci_rh_resume (ohci); | |
936 | spin_unlock (&ohci->lock); | |
937 | } else | |
f197b2c5 | 938 | usb_hcd_resume_root_hub(hcd); |
1da177e4 LT |
939 | } |
940 | ||
c6fcb85e AS |
941 | spin_lock(&ohci->lock); |
942 | if (ints & OHCI_INTR_WDH) | |
943 | update_done_list(ohci); | |
dd9048af | 944 | |
1da177e4 LT |
945 | /* could track INTR_SO to reduce available PCI/... bandwidth */ |
946 | ||
947 | /* handle any pending URB/ED unlinks, leaving INTR_SF enabled | |
948 | * when there's still unlinking to be done (next frame). | |
949 | */ | |
cdb4dd15 | 950 | ohci_work(ohci); |
95d9a01d | 951 | if ((ints & OHCI_INTR_SF) != 0 && !ohci->ed_rm_list |
b7463c71 | 952 | && ohci->rh_state == OHCI_RH_RUNNING) |
dd9048af | 953 | ohci_writel (ohci, OHCI_INTR_SF, ®s->intrdisable); |
1da177e4 | 954 | |
b7463c71 | 955 | if (ohci->rh_state == OHCI_RH_RUNNING) { |
1da177e4 | 956 | ohci_writel (ohci, ints, ®s->intrstatus); |
81e38333 AS |
957 | if (ints & OHCI_INTR_WDH) |
958 | ++ohci->wdh_cnt; | |
959 | ||
dd9048af | 960 | ohci_writel (ohci, OHCI_INTR_MIE, ®s->intrenable); |
1da177e4 LT |
961 | // flush those writes |
962 | (void) ohci_readl (ohci, &ohci->regs->control); | |
963 | } | |
c6fcb85e | 964 | spin_unlock(&ohci->lock); |
1da177e4 LT |
965 | |
966 | return IRQ_HANDLED; | |
967 | } | |
968 | ||
969 | /*-------------------------------------------------------------------------*/ | |
970 | ||
971 | static void ohci_stop (struct usb_hcd *hcd) | |
dd9048af | 972 | { |
1da177e4 LT |
973 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); |
974 | ||
256dbcd8 | 975 | ohci_dump(ohci); |
1da177e4 | 976 | |
569ff2de | 977 | if (quirk_nec(ohci)) |
43829731 | 978 | flush_work(&ohci->nec_work); |
81e38333 | 979 | del_timer_sync(&ohci->io_watchdog); |
b2685bda | 980 | ohci->prev_frame_no = IO_WATCHDOG_OFF; |
1da177e4 | 981 | |
1da177e4 | 982 | ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable); |
435932f2 | 983 | ohci_usb_reset(ohci); |
71795c1d | 984 | free_irq(hcd->irq, hcd); |
cd70469d | 985 | hcd->irq = 0; |
71795c1d | 986 | |
ab1666c1 | 987 | if (quirk_amdiso(ohci)) |
ad93562b | 988 | usb_amd_dev_put(); |
89a0fd18 | 989 | |
1da177e4 LT |
990 | remove_debug_files (ohci); |
991 | ohci_mem_cleanup (ohci); | |
992 | if (ohci->hcca) { | |
dd9048af DB |
993 | dma_free_coherent (hcd->self.controller, |
994 | sizeof *ohci->hcca, | |
1da177e4 LT |
995 | ohci->hcca, ohci->hcca_dma); |
996 | ohci->hcca = NULL; | |
997 | ohci->hcca_dma = 0; | |
998 | } | |
999 | } | |
1000 | ||
1001 | /*-------------------------------------------------------------------------*/ | |
1002 | ||
2c93e790 | 1003 | #if defined(CONFIG_PM) || defined(CONFIG_USB_PCI) |
da6fb570 | 1004 | |
1da177e4 | 1005 | /* must not be called from interrupt context */ |
95e44d44 | 1006 | int ohci_restart(struct ohci_hcd *ohci) |
1da177e4 LT |
1007 | { |
1008 | int temp; | |
1009 | int i; | |
1010 | struct urb_priv *priv; | |
1da177e4 | 1011 | |
95e44d44 | 1012 | ohci_init(ohci); |
1da177e4 | 1013 | spin_lock_irq(&ohci->lock); |
b7463c71 | 1014 | ohci->rh_state = OHCI_RH_HALTED; |
d576bb9f MH |
1015 | |
1016 | /* Recycle any "live" eds/tds (and urbs). */ | |
1da177e4 LT |
1017 | if (!list_empty (&ohci->pending)) |
1018 | ohci_dbg(ohci, "abort schedule...\n"); | |
1019 | list_for_each_entry (priv, &ohci->pending, pending) { | |
1020 | struct urb *urb = priv->td[0]->urb; | |
1021 | struct ed *ed = priv->ed; | |
1022 | ||
1023 | switch (ed->state) { | |
1024 | case ED_OPER: | |
1025 | ed->state = ED_UNLINK; | |
1026 | ed->hwINFO |= cpu_to_hc32(ohci, ED_DEQUEUE); | |
1027 | ed_deschedule (ohci, ed); | |
1028 | ||
1029 | ed->ed_next = ohci->ed_rm_list; | |
1030 | ed->ed_prev = NULL; | |
1031 | ohci->ed_rm_list = ed; | |
1032 | /* FALLTHROUGH */ | |
1033 | case ED_UNLINK: | |
1034 | break; | |
1035 | default: | |
1036 | ohci_dbg(ohci, "bogus ed %p state %d\n", | |
1037 | ed, ed->state); | |
1038 | } | |
1039 | ||
55d84968 AS |
1040 | if (!urb->unlinked) |
1041 | urb->unlinked = -ESHUTDOWN; | |
1da177e4 | 1042 | } |
cdb4dd15 | 1043 | ohci_work(ohci); |
1da177e4 LT |
1044 | spin_unlock_irq(&ohci->lock); |
1045 | ||
1046 | /* paranoia, in case that didn't work: */ | |
1047 | ||
1048 | /* empty the interrupt branches */ | |
1049 | for (i = 0; i < NUM_INTS; i++) ohci->load [i] = 0; | |
1050 | for (i = 0; i < NUM_INTS; i++) ohci->hcca->int_table [i] = 0; | |
dd9048af | 1051 | |
1da177e4 LT |
1052 | /* no EDs to remove */ |
1053 | ohci->ed_rm_list = NULL; | |
1054 | ||
dd9048af | 1055 | /* empty control and bulk lists */ |
1da177e4 LT |
1056 | ohci->ed_controltail = NULL; |
1057 | ohci->ed_bulktail = NULL; | |
1058 | ||
1059 | if ((temp = ohci_run (ohci)) < 0) { | |
1060 | ohci_err (ohci, "can't restart, %d\n", temp); | |
1061 | return temp; | |
1da177e4 | 1062 | } |
383975d7 | 1063 | ohci_dbg(ohci, "restart complete\n"); |
1da177e4 LT |
1064 | return 0; |
1065 | } | |
95e44d44 | 1066 | EXPORT_SYMBOL_GPL(ohci_restart); |
d576bb9f | 1067 | |
da6fb570 DB |
1068 | #endif |
1069 | ||
cd1965db FF |
1070 | #ifdef CONFIG_PM |
1071 | ||
95e44d44 | 1072 | int ohci_suspend(struct usb_hcd *hcd, bool do_wakeup) |
cd1965db FF |
1073 | { |
1074 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); | |
1075 | unsigned long flags; | |
e1bffbf6 | 1076 | int rc = 0; |
cd1965db | 1077 | |
d4ae47dc | 1078 | /* Disable irq emission and mark HW unaccessible. Use |
cd1965db FF |
1079 | * the spinlock to properly synchronize with possible pending |
1080 | * RH suspend or resume activity. | |
1081 | */ | |
1082 | spin_lock_irqsave (&ohci->lock, flags); | |
cd1965db FF |
1083 | ohci_writel(ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable); |
1084 | (void)ohci_readl(ohci, &ohci->regs->intrdisable); | |
1085 | ||
1086 | clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); | |
cd1965db FF |
1087 | spin_unlock_irqrestore (&ohci->lock, flags); |
1088 | ||
e1bffbf6 MG |
1089 | synchronize_irq(hcd->irq); |
1090 | ||
1091 | if (do_wakeup && HCD_WAKEUP_PENDING(hcd)) { | |
1092 | ohci_resume(hcd, false); | |
1093 | rc = -EBUSY; | |
1094 | } | |
1095 | return rc; | |
cd1965db | 1096 | } |
95e44d44 | 1097 | EXPORT_SYMBOL_GPL(ohci_suspend); |
cd1965db FF |
1098 | |
1099 | ||
95e44d44 | 1100 | int ohci_resume(struct usb_hcd *hcd, bool hibernated) |
cd1965db | 1101 | { |
cfa49b4b FF |
1102 | struct ohci_hcd *ohci = hcd_to_ohci(hcd); |
1103 | int port; | |
1104 | bool need_reinit = false; | |
1105 | ||
cd1965db FF |
1106 | set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); |
1107 | ||
1108 | /* Make sure resume from hibernation re-enumerates everything */ | |
1109 | if (hibernated) | |
cfa49b4b FF |
1110 | ohci_usb_reset(ohci); |
1111 | ||
1112 | /* See if the controller is already running or has been reset */ | |
1113 | ohci->hc_control = ohci_readl(ohci, &ohci->regs->control); | |
1114 | if (ohci->hc_control & (OHCI_CTRL_IR | OHCI_SCHED_ENABLES)) { | |
1115 | need_reinit = true; | |
1116 | } else { | |
1117 | switch (ohci->hc_control & OHCI_CTRL_HCFS) { | |
1118 | case OHCI_USB_OPER: | |
1119 | case OHCI_USB_RESET: | |
1120 | need_reinit = true; | |
1121 | } | |
1122 | } | |
1123 | ||
1124 | /* If needed, reinitialize and suspend the root hub */ | |
1125 | if (need_reinit) { | |
1126 | spin_lock_irq(&ohci->lock); | |
1127 | ohci_rh_resume(ohci); | |
1128 | ohci_rh_suspend(ohci, 0); | |
1129 | spin_unlock_irq(&ohci->lock); | |
1130 | } | |
1131 | ||
1132 | /* Normally just turn on port power and enable interrupts */ | |
1133 | else { | |
1134 | ohci_dbg(ohci, "powerup ports\n"); | |
1135 | for (port = 0; port < ohci->num_ports; port++) | |
1136 | ohci_writel(ohci, RH_PS_PPS, | |
1137 | &ohci->regs->roothub.portstatus[port]); | |
1138 | ||
1139 | ohci_writel(ohci, OHCI_INTR_MIE, &ohci->regs->intrenable); | |
1140 | ohci_readl(ohci, &ohci->regs->intrenable); | |
1141 | msleep(20); | |
1142 | } | |
1143 | ||
1144 | usb_hcd_resume_root_hub(hcd); | |
cd1965db | 1145 | |
cd1965db FF |
1146 | return 0; |
1147 | } | |
95e44d44 MG |
1148 | EXPORT_SYMBOL_GPL(ohci_resume); |
1149 | ||
1150 | #endif | |
1151 | ||
1152 | /*-------------------------------------------------------------------------*/ | |
1153 | ||
1154 | /* | |
1155 | * Generic structure: This gets copied for platform drivers so that | |
1156 | * individual entries can be overridden as needed. | |
1157 | */ | |
cd1965db | 1158 | |
95e44d44 MG |
1159 | static const struct hc_driver ohci_hc_driver = { |
1160 | .description = hcd_name, | |
1161 | .product_desc = "OHCI Host Controller", | |
1162 | .hcd_priv_size = sizeof(struct ohci_hcd), | |
1163 | ||
1164 | /* | |
1165 | * generic hardware linkage | |
1166 | */ | |
1167 | .irq = ohci_irq, | |
1168 | .flags = HCD_MEMORY | HCD_USB11, | |
1169 | ||
1170 | /* | |
1171 | * basic lifecycle operations | |
1172 | */ | |
1173 | .reset = ohci_setup, | |
1174 | .start = ohci_start, | |
1175 | .stop = ohci_stop, | |
1176 | .shutdown = ohci_shutdown, | |
1177 | ||
1178 | /* | |
1179 | * managing i/o requests and associated device resources | |
1180 | */ | |
1181 | .urb_enqueue = ohci_urb_enqueue, | |
1182 | .urb_dequeue = ohci_urb_dequeue, | |
1183 | .endpoint_disable = ohci_endpoint_disable, | |
1184 | ||
1185 | /* | |
1186 | * scheduling support | |
1187 | */ | |
1188 | .get_frame_number = ohci_get_frame, | |
1189 | ||
1190 | /* | |
1191 | * root hub support | |
1192 | */ | |
1193 | .hub_status_data = ohci_hub_status_data, | |
1194 | .hub_control = ohci_hub_control, | |
1195 | #ifdef CONFIG_PM | |
1196 | .bus_suspend = ohci_bus_suspend, | |
1197 | .bus_resume = ohci_bus_resume, | |
cd1965db | 1198 | #endif |
95e44d44 MG |
1199 | .start_port_reset = ohci_start_port_reset, |
1200 | }; | |
1201 | ||
1202 | void ohci_init_driver(struct hc_driver *drv, | |
1203 | const struct ohci_driver_overrides *over) | |
1204 | { | |
1205 | /* Copy the generic table to drv and then apply the overrides */ | |
1206 | *drv = ohci_hc_driver; | |
1207 | ||
c80ad6d1 KH |
1208 | if (over) { |
1209 | drv->product_desc = over->product_desc; | |
1210 | drv->hcd_priv_size += over->extra_priv_size; | |
1211 | if (over->reset) | |
1212 | drv->reset = over->reset; | |
1213 | } | |
95e44d44 MG |
1214 | } |
1215 | EXPORT_SYMBOL_GPL(ohci_init_driver); | |
cd1965db | 1216 | |
d576bb9f MH |
1217 | /*-------------------------------------------------------------------------*/ |
1218 | ||
1da177e4 | 1219 | MODULE_AUTHOR (DRIVER_AUTHOR); |
2b70f073 | 1220 | MODULE_DESCRIPTION(DRIVER_DESC); |
1da177e4 LT |
1221 | MODULE_LICENSE ("GPL"); |
1222 | ||
6381fad7 | 1223 | #if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_SA1111) |
1da177e4 | 1224 | #include "ohci-sa1111.c" |
5e16fabe | 1225 | #define SA1111_DRIVER ohci_hcd_sa1111_driver |
1da177e4 LT |
1226 | #endif |
1227 | ||
495a678f SM |
1228 | #ifdef CONFIG_USB_OHCI_HCD_PPC_OF |
1229 | #include "ohci-ppc-of.c" | |
1230 | #define OF_PLATFORM_DRIVER ohci_hcd_ppc_of_driver | |
1231 | #endif | |
1232 | ||
6a6c957e GL |
1233 | #ifdef CONFIG_PPC_PS3 |
1234 | #include "ohci-ps3.c" | |
7a4eb7fd | 1235 | #define PS3_SYSTEM_BUS_DRIVER ps3_ohci_driver |
6a6c957e GL |
1236 | #endif |
1237 | ||
f54aab6e MD |
1238 | #ifdef CONFIG_MFD_SM501 |
1239 | #include "ohci-sm501.c" | |
3ee38d8b | 1240 | #define SM501_OHCI_DRIVER ohci_hcd_sm501_driver |
f54aab6e MD |
1241 | #endif |
1242 | ||
78c73414 DES |
1243 | #ifdef CONFIG_MFD_TC6393XB |
1244 | #include "ohci-tmio.c" | |
1245 | #define TMIO_OHCI_DRIVER ohci_hcd_tmio_driver | |
1643accd DD |
1246 | #endif |
1247 | ||
47fc28bf CM |
1248 | #ifdef CONFIG_TILE_USB |
1249 | #include "ohci-tilegx.c" | |
1250 | #define PLATFORM_DRIVER ohci_hcd_tilegx_driver | |
1251 | #endif | |
1252 | ||
5e16fabe SM |
1253 | static int __init ohci_hcd_mod_init(void) |
1254 | { | |
1255 | int retval = 0; | |
5e16fabe SM |
1256 | |
1257 | if (usb_disabled()) | |
1258 | return -ENODEV; | |
1259 | ||
2b70f073 | 1260 | printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name); |
5b5e0928 | 1261 | pr_debug ("%s: block sizes: ed %zd td %zd\n", hcd_name, |
5e16fabe | 1262 | sizeof (struct ed), sizeof (struct td)); |
9beeee65 | 1263 | set_bit(USB_OHCI_LOADED, &usb_hcds_loaded); |
5e16fabe | 1264 | |
485f4f39 | 1265 | ohci_debug_root = debugfs_create_dir("ohci", usb_debug_root); |
684c19e0 TJ |
1266 | if (!ohci_debug_root) { |
1267 | retval = -ENOENT; | |
1268 | goto error_debug; | |
1269 | } | |
684c19e0 | 1270 | |
6a6c957e | 1271 | #ifdef PS3_SYSTEM_BUS_DRIVER |
7a4eb7fd GL |
1272 | retval = ps3_ohci_driver_register(&PS3_SYSTEM_BUS_DRIVER); |
1273 | if (retval < 0) | |
1274 | goto error_ps3; | |
6a6c957e GL |
1275 | #endif |
1276 | ||
5e16fabe SM |
1277 | #ifdef PLATFORM_DRIVER |
1278 | retval = platform_driver_register(&PLATFORM_DRIVER); | |
1279 | if (retval < 0) | |
de44743b | 1280 | goto error_platform; |
5e16fabe SM |
1281 | #endif |
1282 | ||
495a678f | 1283 | #ifdef OF_PLATFORM_DRIVER |
d35fb641 | 1284 | retval = platform_driver_register(&OF_PLATFORM_DRIVER); |
495a678f | 1285 | if (retval < 0) |
de44743b | 1286 | goto error_of_platform; |
495a678f SM |
1287 | #endif |
1288 | ||
5e16fabe SM |
1289 | #ifdef SA1111_DRIVER |
1290 | retval = sa1111_driver_register(&SA1111_DRIVER); | |
1291 | if (retval < 0) | |
de44743b | 1292 | goto error_sa1111; |
5e16fabe SM |
1293 | #endif |
1294 | ||
3ee38d8b BD |
1295 | #ifdef SM501_OHCI_DRIVER |
1296 | retval = platform_driver_register(&SM501_OHCI_DRIVER); | |
1297 | if (retval < 0) | |
1298 | goto error_sm501; | |
1299 | #endif | |
1300 | ||
78c73414 DES |
1301 | #ifdef TMIO_OHCI_DRIVER |
1302 | retval = platform_driver_register(&TMIO_OHCI_DRIVER); | |
1303 | if (retval < 0) | |
1304 | goto error_tmio; | |
1305 | #endif | |
1306 | ||
5e16fabe SM |
1307 | return retval; |
1308 | ||
1309 | /* Error path */ | |
78c73414 DES |
1310 | #ifdef TMIO_OHCI_DRIVER |
1311 | platform_driver_unregister(&TMIO_OHCI_DRIVER); | |
1312 | error_tmio: | |
1313 | #endif | |
3ee38d8b | 1314 | #ifdef SM501_OHCI_DRIVER |
78c73414 | 1315 | platform_driver_unregister(&SM501_OHCI_DRIVER); |
3ee38d8b BD |
1316 | error_sm501: |
1317 | #endif | |
de44743b BH |
1318 | #ifdef SA1111_DRIVER |
1319 | sa1111_driver_unregister(&SA1111_DRIVER); | |
1320 | error_sa1111: | |
5e16fabe | 1321 | #endif |
495a678f | 1322 | #ifdef OF_PLATFORM_DRIVER |
d35fb641 | 1323 | platform_driver_unregister(&OF_PLATFORM_DRIVER); |
de44743b | 1324 | error_of_platform: |
495a678f | 1325 | #endif |
8097804e AB |
1326 | #ifdef PLATFORM_DRIVER |
1327 | platform_driver_unregister(&PLATFORM_DRIVER); | |
1328 | error_platform: | |
968b448b | 1329 | #endif |
6a6c957e | 1330 | #ifdef PS3_SYSTEM_BUS_DRIVER |
7a4eb7fd | 1331 | ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); |
6a6c957e | 1332 | error_ps3: |
5e16fabe | 1333 | #endif |
684c19e0 TJ |
1334 | debugfs_remove(ohci_debug_root); |
1335 | ohci_debug_root = NULL; | |
1336 | error_debug: | |
684c19e0 | 1337 | |
9beeee65 | 1338 | clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded); |
5e16fabe SM |
1339 | return retval; |
1340 | } | |
1341 | module_init(ohci_hcd_mod_init); | |
1342 | ||
1343 | static void __exit ohci_hcd_mod_exit(void) | |
1344 | { | |
78c73414 DES |
1345 | #ifdef TMIO_OHCI_DRIVER |
1346 | platform_driver_unregister(&TMIO_OHCI_DRIVER); | |
1347 | #endif | |
3ee38d8b BD |
1348 | #ifdef SM501_OHCI_DRIVER |
1349 | platform_driver_unregister(&SM501_OHCI_DRIVER); | |
1350 | #endif | |
5e16fabe SM |
1351 | #ifdef SA1111_DRIVER |
1352 | sa1111_driver_unregister(&SA1111_DRIVER); | |
1353 | #endif | |
495a678f | 1354 | #ifdef OF_PLATFORM_DRIVER |
d35fb641 | 1355 | platform_driver_unregister(&OF_PLATFORM_DRIVER); |
495a678f | 1356 | #endif |
8097804e AB |
1357 | #ifdef PLATFORM_DRIVER |
1358 | platform_driver_unregister(&PLATFORM_DRIVER); | |
1359 | #endif | |
6a6c957e | 1360 | #ifdef PS3_SYSTEM_BUS_DRIVER |
7a4eb7fd | 1361 | ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); |
6a6c957e | 1362 | #endif |
684c19e0 | 1363 | debugfs_remove(ohci_debug_root); |
9beeee65 | 1364 | clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded); |
5e16fabe SM |
1365 | } |
1366 | module_exit(ohci_hcd_mod_exit); | |
1367 |