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1da177e4 LT |
1 | /* |
2 | * OHCI HCD (Host Controller Driver) for USB. | |
3 | * | |
4 | * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at> | |
5 | * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net> | |
6 | * | |
7 | * This file is licenced under the GPL. | |
8 | */ | |
9 | ||
7d12e780 DH |
10 | #include <linux/irq.h> |
11 | ||
1da177e4 LT |
12 | static void urb_free_priv (struct ohci_hcd *hc, urb_priv_t *urb_priv) |
13 | { | |
14 | int last = urb_priv->length - 1; | |
15 | ||
16 | if (last >= 0) { | |
17 | int i; | |
18 | struct td *td; | |
19 | ||
20 | for (i = 0; i <= last; i++) { | |
21 | td = urb_priv->td [i]; | |
22 | if (td) | |
23 | td_free (hc, td); | |
24 | } | |
25 | } | |
26 | ||
27 | list_del (&urb_priv->pending); | |
28 | kfree (urb_priv); | |
29 | } | |
30 | ||
31 | /*-------------------------------------------------------------------------*/ | |
32 | ||
33 | /* | |
34 | * URB goes back to driver, and isn't reissued. | |
35 | * It's completely gone from HC data structures. | |
36 | * PRECONDITION: ohci lock held, irqs blocked. | |
37 | */ | |
38 | static void | |
7d12e780 | 39 | finish_urb (struct ohci_hcd *ohci, struct urb *urb) |
1da177e4 LT |
40 | __releases(ohci->lock) |
41 | __acquires(ohci->lock) | |
42 | { | |
43 | // ASSERT (urb->hcpriv != 0); | |
44 | ||
45 | urb_free_priv (ohci, urb->hcpriv); | |
46 | urb->hcpriv = NULL; | |
47 | ||
48 | spin_lock (&urb->lock); | |
49 | if (likely (urb->status == -EINPROGRESS)) | |
50 | urb->status = 0; | |
51 | /* report short control reads right even though the data TD always | |
52 | * has TD_R set. (much simpler, but creates the 1-td limit.) | |
53 | */ | |
54 | if (unlikely (urb->transfer_flags & URB_SHORT_NOT_OK) | |
55 | && unlikely (usb_pipecontrol (urb->pipe)) | |
56 | && urb->actual_length < urb->transfer_buffer_length | |
57 | && usb_pipein (urb->pipe) | |
58 | && urb->status == 0) { | |
59 | urb->status = -EREMOTEIO; | |
60 | } | |
61 | spin_unlock (&urb->lock); | |
62 | ||
63 | switch (usb_pipetype (urb->pipe)) { | |
64 | case PIPE_ISOCHRONOUS: | |
65 | ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs--; | |
66 | break; | |
67 | case PIPE_INTERRUPT: | |
68 | ohci_to_hcd(ohci)->self.bandwidth_int_reqs--; | |
69 | break; | |
70 | } | |
71 | ||
72 | #ifdef OHCI_VERBOSE_DEBUG | |
73 | urb_print (urb, "RET", usb_pipeout (urb->pipe)); | |
74 | #endif | |
75 | ||
76 | /* urb->complete() can reenter this HCD */ | |
77 | spin_unlock (&ohci->lock); | |
7d12e780 | 78 | usb_hcd_giveback_urb (ohci_to_hcd(ohci), urb); |
1da177e4 LT |
79 | spin_lock (&ohci->lock); |
80 | ||
81 | /* stop periodic dma if it's not needed */ | |
82 | if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0 | |
83 | && ohci_to_hcd(ohci)->self.bandwidth_int_reqs == 0) { | |
84 | ohci->hc_control &= ~(OHCI_CTRL_PLE|OHCI_CTRL_IE); | |
85 | ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); | |
86 | } | |
87 | } | |
88 | ||
89 | ||
90 | /*-------------------------------------------------------------------------* | |
91 | * ED handling functions | |
92 | *-------------------------------------------------------------------------*/ | |
93 | ||
94 | /* search for the right schedule branch to use for a periodic ed. | |
95 | * does some load balancing; returns the branch, or negative errno. | |
96 | */ | |
97 | static int balance (struct ohci_hcd *ohci, int interval, int load) | |
98 | { | |
99 | int i, branch = -ENOSPC; | |
100 | ||
101 | /* iso periods can be huge; iso tds specify frame numbers */ | |
102 | if (interval > NUM_INTS) | |
103 | interval = NUM_INTS; | |
104 | ||
105 | /* search for the least loaded schedule branch of that period | |
106 | * that has enough bandwidth left unreserved. | |
107 | */ | |
108 | for (i = 0; i < interval ; i++) { | |
109 | if (branch < 0 || ohci->load [branch] > ohci->load [i]) { | |
110 | #if 1 /* CONFIG_USB_BANDWIDTH */ | |
111 | int j; | |
112 | ||
113 | /* usb 1.1 says 90% of one frame */ | |
114 | for (j = i; j < NUM_INTS; j += interval) { | |
115 | if ((ohci->load [j] + load) > 900) | |
116 | break; | |
117 | } | |
118 | if (j < NUM_INTS) | |
119 | continue; | |
120 | #endif | |
121 | branch = i; | |
122 | } | |
123 | } | |
124 | return branch; | |
125 | } | |
126 | ||
127 | /*-------------------------------------------------------------------------*/ | |
128 | ||
129 | /* both iso and interrupt requests have periods; this routine puts them | |
130 | * into the schedule tree in the apppropriate place. most iso devices use | |
131 | * 1msec periods, but that's not required. | |
132 | */ | |
133 | static void periodic_link (struct ohci_hcd *ohci, struct ed *ed) | |
134 | { | |
135 | unsigned i; | |
136 | ||
137 | ohci_vdbg (ohci, "link %sed %p branch %d [%dus.], interval %d\n", | |
138 | (ed->hwINFO & cpu_to_hc32 (ohci, ED_ISO)) ? "iso " : "", | |
139 | ed, ed->branch, ed->load, ed->interval); | |
140 | ||
141 | for (i = ed->branch; i < NUM_INTS; i += ed->interval) { | |
142 | struct ed **prev = &ohci->periodic [i]; | |
143 | __hc32 *prev_p = &ohci->hcca->int_table [i]; | |
144 | struct ed *here = *prev; | |
145 | ||
146 | /* sorting each branch by period (slow before fast) | |
147 | * lets us share the faster parts of the tree. | |
148 | * (plus maybe: put interrupt eds before iso) | |
149 | */ | |
150 | while (here && ed != here) { | |
151 | if (ed->interval > here->interval) | |
152 | break; | |
153 | prev = &here->ed_next; | |
154 | prev_p = &here->hwNextED; | |
155 | here = *prev; | |
156 | } | |
157 | if (ed != here) { | |
158 | ed->ed_next = here; | |
159 | if (here) | |
160 | ed->hwNextED = *prev_p; | |
161 | wmb (); | |
162 | *prev = ed; | |
163 | *prev_p = cpu_to_hc32(ohci, ed->dma); | |
164 | wmb(); | |
165 | } | |
166 | ohci->load [i] += ed->load; | |
167 | } | |
168 | ohci_to_hcd(ohci)->self.bandwidth_allocated += ed->load / ed->interval; | |
169 | } | |
170 | ||
171 | /* link an ed into one of the HC chains */ | |
172 | ||
173 | static int ed_schedule (struct ohci_hcd *ohci, struct ed *ed) | |
174 | { | |
175 | int branch; | |
176 | ||
177 | if (ohci_to_hcd(ohci)->state == HC_STATE_QUIESCING) | |
178 | return -EAGAIN; | |
179 | ||
180 | ed->state = ED_OPER; | |
181 | ed->ed_prev = NULL; | |
182 | ed->ed_next = NULL; | |
183 | ed->hwNextED = 0; | |
184 | wmb (); | |
185 | ||
186 | /* we care about rm_list when setting CLE/BLE in case the HC was at | |
187 | * work on some TD when CLE/BLE was turned off, and isn't quiesced | |
188 | * yet. finish_unlinks() restarts as needed, some upcoming INTR_SF. | |
189 | * | |
190 | * control and bulk EDs are doubly linked (ed_next, ed_prev), but | |
191 | * periodic ones are singly linked (ed_next). that's because the | |
192 | * periodic schedule encodes a tree like figure 3-5 in the ohci | |
193 | * spec: each qh can have several "previous" nodes, and the tree | |
194 | * doesn't have unused/idle descriptors. | |
195 | */ | |
196 | switch (ed->type) { | |
197 | case PIPE_CONTROL: | |
198 | if (ohci->ed_controltail == NULL) { | |
199 | WARN_ON (ohci->hc_control & OHCI_CTRL_CLE); | |
200 | ohci_writel (ohci, ed->dma, | |
201 | &ohci->regs->ed_controlhead); | |
202 | } else { | |
203 | ohci->ed_controltail->ed_next = ed; | |
204 | ohci->ed_controltail->hwNextED = cpu_to_hc32 (ohci, | |
205 | ed->dma); | |
206 | } | |
207 | ed->ed_prev = ohci->ed_controltail; | |
208 | if (!ohci->ed_controltail && !ohci->ed_rm_list) { | |
209 | wmb(); | |
210 | ohci->hc_control |= OHCI_CTRL_CLE; | |
211 | ohci_writel (ohci, 0, &ohci->regs->ed_controlcurrent); | |
212 | ohci_writel (ohci, ohci->hc_control, | |
213 | &ohci->regs->control); | |
214 | } | |
215 | ohci->ed_controltail = ed; | |
216 | break; | |
217 | ||
218 | case PIPE_BULK: | |
219 | if (ohci->ed_bulktail == NULL) { | |
220 | WARN_ON (ohci->hc_control & OHCI_CTRL_BLE); | |
221 | ohci_writel (ohci, ed->dma, &ohci->regs->ed_bulkhead); | |
222 | } else { | |
223 | ohci->ed_bulktail->ed_next = ed; | |
224 | ohci->ed_bulktail->hwNextED = cpu_to_hc32 (ohci, | |
225 | ed->dma); | |
226 | } | |
227 | ed->ed_prev = ohci->ed_bulktail; | |
228 | if (!ohci->ed_bulktail && !ohci->ed_rm_list) { | |
229 | wmb(); | |
230 | ohci->hc_control |= OHCI_CTRL_BLE; | |
231 | ohci_writel (ohci, 0, &ohci->regs->ed_bulkcurrent); | |
232 | ohci_writel (ohci, ohci->hc_control, | |
233 | &ohci->regs->control); | |
234 | } | |
235 | ohci->ed_bulktail = ed; | |
236 | break; | |
237 | ||
238 | // case PIPE_INTERRUPT: | |
239 | // case PIPE_ISOCHRONOUS: | |
240 | default: | |
241 | branch = balance (ohci, ed->interval, ed->load); | |
242 | if (branch < 0) { | |
243 | ohci_dbg (ohci, | |
244 | "ERR %d, interval %d msecs, load %d\n", | |
245 | branch, ed->interval, ed->load); | |
246 | // FIXME if there are TDs queued, fail them! | |
247 | return branch; | |
248 | } | |
249 | ed->branch = branch; | |
250 | periodic_link (ohci, ed); | |
251 | } | |
252 | ||
253 | /* the HC may not see the schedule updates yet, but if it does | |
254 | * then they'll be properly ordered. | |
255 | */ | |
256 | return 0; | |
257 | } | |
258 | ||
259 | /*-------------------------------------------------------------------------*/ | |
260 | ||
261 | /* scan the periodic table to find and unlink this ED */ | |
262 | static void periodic_unlink (struct ohci_hcd *ohci, struct ed *ed) | |
263 | { | |
264 | int i; | |
265 | ||
266 | for (i = ed->branch; i < NUM_INTS; i += ed->interval) { | |
267 | struct ed *temp; | |
268 | struct ed **prev = &ohci->periodic [i]; | |
269 | __hc32 *prev_p = &ohci->hcca->int_table [i]; | |
270 | ||
271 | while (*prev && (temp = *prev) != ed) { | |
272 | prev_p = &temp->hwNextED; | |
273 | prev = &temp->ed_next; | |
274 | } | |
275 | if (*prev) { | |
276 | *prev_p = ed->hwNextED; | |
277 | *prev = ed->ed_next; | |
278 | } | |
279 | ohci->load [i] -= ed->load; | |
280 | } | |
281 | ohci_to_hcd(ohci)->self.bandwidth_allocated -= ed->load / ed->interval; | |
282 | ||
283 | ohci_vdbg (ohci, "unlink %sed %p branch %d [%dus.], interval %d\n", | |
284 | (ed->hwINFO & cpu_to_hc32 (ohci, ED_ISO)) ? "iso " : "", | |
285 | ed, ed->branch, ed->load, ed->interval); | |
286 | } | |
287 | ||
288 | /* unlink an ed from one of the HC chains. | |
289 | * just the link to the ed is unlinked. | |
290 | * the link from the ed still points to another operational ed or 0 | |
291 | * so the HC can eventually finish the processing of the unlinked ed | |
292 | * (assuming it already started that, which needn't be true). | |
293 | * | |
294 | * ED_UNLINK is a transient state: the HC may still see this ED, but soon | |
295 | * it won't. ED_SKIP means the HC will finish its current transaction, | |
296 | * but won't start anything new. The TD queue may still grow; device | |
297 | * drivers don't know about this HCD-internal state. | |
298 | * | |
299 | * When the HC can't see the ED, something changes ED_UNLINK to one of: | |
300 | * | |
301 | * - ED_OPER: when there's any request queued, the ED gets rescheduled | |
302 | * immediately. HC should be working on them. | |
303 | * | |
304 | * - ED_IDLE: when there's no TD queue. there's no reason for the HC | |
305 | * to care about this ED; safe to disable the endpoint. | |
306 | * | |
307 | * When finish_unlinks() runs later, after SOF interrupt, it will often | |
308 | * complete one or more URB unlinks before making that state change. | |
309 | */ | |
310 | static void ed_deschedule (struct ohci_hcd *ohci, struct ed *ed) | |
311 | { | |
312 | ed->hwINFO |= cpu_to_hc32 (ohci, ED_SKIP); | |
313 | wmb (); | |
314 | ed->state = ED_UNLINK; | |
315 | ||
316 | /* To deschedule something from the control or bulk list, just | |
317 | * clear CLE/BLE and wait. There's no safe way to scrub out list | |
318 | * head/current registers until later, and "later" isn't very | |
319 | * tightly specified. Figure 6-5 and Section 6.4.2.2 show how | |
320 | * the HC is reading the ED queues (while we modify them). | |
321 | * | |
322 | * For now, ed_schedule() is "later". It might be good paranoia | |
323 | * to scrub those registers in finish_unlinks(), in case of bugs | |
324 | * that make the HC try to use them. | |
325 | */ | |
326 | switch (ed->type) { | |
327 | case PIPE_CONTROL: | |
328 | /* remove ED from the HC's list: */ | |
329 | if (ed->ed_prev == NULL) { | |
330 | if (!ed->hwNextED) { | |
331 | ohci->hc_control &= ~OHCI_CTRL_CLE; | |
332 | ohci_writel (ohci, ohci->hc_control, | |
333 | &ohci->regs->control); | |
334 | // a ohci_readl() later syncs CLE with the HC | |
335 | } else | |
336 | ohci_writel (ohci, | |
337 | hc32_to_cpup (ohci, &ed->hwNextED), | |
338 | &ohci->regs->ed_controlhead); | |
339 | } else { | |
340 | ed->ed_prev->ed_next = ed->ed_next; | |
341 | ed->ed_prev->hwNextED = ed->hwNextED; | |
342 | } | |
343 | /* remove ED from the HCD's list: */ | |
344 | if (ohci->ed_controltail == ed) { | |
345 | ohci->ed_controltail = ed->ed_prev; | |
346 | if (ohci->ed_controltail) | |
347 | ohci->ed_controltail->ed_next = NULL; | |
348 | } else if (ed->ed_next) { | |
349 | ed->ed_next->ed_prev = ed->ed_prev; | |
350 | } | |
351 | break; | |
352 | ||
353 | case PIPE_BULK: | |
354 | /* remove ED from the HC's list: */ | |
355 | if (ed->ed_prev == NULL) { | |
356 | if (!ed->hwNextED) { | |
357 | ohci->hc_control &= ~OHCI_CTRL_BLE; | |
358 | ohci_writel (ohci, ohci->hc_control, | |
359 | &ohci->regs->control); | |
360 | // a ohci_readl() later syncs BLE with the HC | |
361 | } else | |
362 | ohci_writel (ohci, | |
363 | hc32_to_cpup (ohci, &ed->hwNextED), | |
364 | &ohci->regs->ed_bulkhead); | |
365 | } else { | |
366 | ed->ed_prev->ed_next = ed->ed_next; | |
367 | ed->ed_prev->hwNextED = ed->hwNextED; | |
368 | } | |
369 | /* remove ED from the HCD's list: */ | |
370 | if (ohci->ed_bulktail == ed) { | |
371 | ohci->ed_bulktail = ed->ed_prev; | |
372 | if (ohci->ed_bulktail) | |
373 | ohci->ed_bulktail->ed_next = NULL; | |
374 | } else if (ed->ed_next) { | |
375 | ed->ed_next->ed_prev = ed->ed_prev; | |
376 | } | |
377 | break; | |
378 | ||
379 | // case PIPE_INTERRUPT: | |
380 | // case PIPE_ISOCHRONOUS: | |
381 | default: | |
382 | periodic_unlink (ohci, ed); | |
383 | break; | |
384 | } | |
385 | } | |
386 | ||
387 | ||
388 | /*-------------------------------------------------------------------------*/ | |
389 | ||
390 | /* get and maybe (re)init an endpoint. init _should_ be done only as part | |
391 | * of enumeration, usb_set_configuration() or usb_set_interface(). | |
392 | */ | |
393 | static struct ed *ed_get ( | |
394 | struct ohci_hcd *ohci, | |
395 | struct usb_host_endpoint *ep, | |
396 | struct usb_device *udev, | |
397 | unsigned int pipe, | |
398 | int interval | |
399 | ) { | |
400 | struct ed *ed; | |
401 | unsigned long flags; | |
402 | ||
403 | spin_lock_irqsave (&ohci->lock, flags); | |
404 | ||
405 | if (!(ed = ep->hcpriv)) { | |
406 | struct td *td; | |
407 | int is_out; | |
408 | u32 info; | |
409 | ||
410 | ed = ed_alloc (ohci, GFP_ATOMIC); | |
411 | if (!ed) { | |
412 | /* out of memory */ | |
413 | goto done; | |
414 | } | |
415 | ||
416 | /* dummy td; end of td list for ed */ | |
417 | td = td_alloc (ohci, GFP_ATOMIC); | |
418 | if (!td) { | |
419 | /* out of memory */ | |
420 | ed_free (ohci, ed); | |
421 | ed = NULL; | |
422 | goto done; | |
423 | } | |
424 | ed->dummy = td; | |
425 | ed->hwTailP = cpu_to_hc32 (ohci, td->td_dma); | |
426 | ed->hwHeadP = ed->hwTailP; /* ED_C, ED_H zeroed */ | |
427 | ed->state = ED_IDLE; | |
428 | ||
429 | is_out = !(ep->desc.bEndpointAddress & USB_DIR_IN); | |
430 | ||
431 | /* FIXME usbcore changes dev->devnum before SET_ADDRESS | |
432 | * suceeds ... otherwise we wouldn't need "pipe". | |
433 | */ | |
434 | info = usb_pipedevice (pipe); | |
435 | ed->type = usb_pipetype(pipe); | |
436 | ||
437 | info |= (ep->desc.bEndpointAddress & ~USB_DIR_IN) << 7; | |
438 | info |= le16_to_cpu(ep->desc.wMaxPacketSize) << 16; | |
439 | if (udev->speed == USB_SPEED_LOW) | |
440 | info |= ED_LOWSPEED; | |
441 | /* only control transfers store pids in tds */ | |
442 | if (ed->type != PIPE_CONTROL) { | |
443 | info |= is_out ? ED_OUT : ED_IN; | |
444 | if (ed->type != PIPE_BULK) { | |
445 | /* periodic transfers... */ | |
446 | if (ed->type == PIPE_ISOCHRONOUS) | |
447 | info |= ED_ISO; | |
448 | else if (interval > 32) /* iso can be bigger */ | |
449 | interval = 32; | |
450 | ed->interval = interval; | |
451 | ed->load = usb_calc_bus_time ( | |
452 | udev->speed, !is_out, | |
453 | ed->type == PIPE_ISOCHRONOUS, | |
454 | le16_to_cpu(ep->desc.wMaxPacketSize)) | |
455 | / 1000; | |
456 | } | |
457 | } | |
458 | ed->hwINFO = cpu_to_hc32(ohci, info); | |
459 | ||
460 | ep->hcpriv = ed; | |
461 | } | |
462 | ||
463 | done: | |
464 | spin_unlock_irqrestore (&ohci->lock, flags); | |
465 | return ed; | |
466 | } | |
467 | ||
468 | /*-------------------------------------------------------------------------*/ | |
469 | ||
470 | /* request unlinking of an endpoint from an operational HC. | |
471 | * put the ep on the rm_list | |
472 | * real work is done at the next start frame (SF) hardware interrupt | |
473 | * caller guarantees HCD is running, so hardware access is safe, | |
474 | * and that ed->state is ED_OPER | |
475 | */ | |
476 | static void start_ed_unlink (struct ohci_hcd *ohci, struct ed *ed) | |
477 | { | |
478 | ed->hwINFO |= cpu_to_hc32 (ohci, ED_DEQUEUE); | |
479 | ed_deschedule (ohci, ed); | |
480 | ||
481 | /* rm_list is just singly linked, for simplicity */ | |
482 | ed->ed_next = ohci->ed_rm_list; | |
483 | ed->ed_prev = NULL; | |
484 | ohci->ed_rm_list = ed; | |
485 | ||
486 | /* enable SOF interrupt */ | |
487 | ohci_writel (ohci, OHCI_INTR_SF, &ohci->regs->intrstatus); | |
488 | ohci_writel (ohci, OHCI_INTR_SF, &ohci->regs->intrenable); | |
489 | // flush those writes, and get latest HCCA contents | |
490 | (void) ohci_readl (ohci, &ohci->regs->control); | |
491 | ||
492 | /* SF interrupt might get delayed; record the frame counter value that | |
493 | * indicates when the HC isn't looking at it, so concurrent unlinks | |
494 | * behave. frame_no wraps every 2^16 msec, and changes right before | |
495 | * SF is triggered. | |
496 | */ | |
497 | ed->tick = ohci_frame_no(ohci) + 1; | |
498 | ||
499 | } | |
500 | ||
501 | /*-------------------------------------------------------------------------* | |
502 | * TD handling functions | |
503 | *-------------------------------------------------------------------------*/ | |
504 | ||
505 | /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */ | |
506 | ||
507 | static void | |
508 | td_fill (struct ohci_hcd *ohci, u32 info, | |
509 | dma_addr_t data, int len, | |
510 | struct urb *urb, int index) | |
511 | { | |
512 | struct td *td, *td_pt; | |
513 | struct urb_priv *urb_priv = urb->hcpriv; | |
514 | int is_iso = info & TD_ISO; | |
515 | int hash; | |
516 | ||
517 | // ASSERT (index < urb_priv->length); | |
518 | ||
519 | /* aim for only one interrupt per urb. mostly applies to control | |
520 | * and iso; other urbs rarely need more than one TD per urb. | |
521 | * this way, only final tds (or ones with an error) cause IRQs. | |
522 | * at least immediately; use DI=6 in case any control request is | |
523 | * tempted to die part way through. (and to force the hc to flush | |
524 | * its donelist soonish, even on unlink paths.) | |
525 | * | |
526 | * NOTE: could delay interrupts even for the last TD, and get fewer | |
527 | * interrupts ... increasing per-urb latency by sharing interrupts. | |
528 | * Drivers that queue bulk urbs may request that behavior. | |
529 | */ | |
530 | if (index != (urb_priv->length - 1) | |
531 | || (urb->transfer_flags & URB_NO_INTERRUPT)) | |
532 | info |= TD_DI_SET (6); | |
533 | ||
534 | /* use this td as the next dummy */ | |
535 | td_pt = urb_priv->td [index]; | |
536 | ||
537 | /* fill the old dummy TD */ | |
538 | td = urb_priv->td [index] = urb_priv->ed->dummy; | |
539 | urb_priv->ed->dummy = td_pt; | |
540 | ||
541 | td->ed = urb_priv->ed; | |
542 | td->next_dl_td = NULL; | |
543 | td->index = index; | |
544 | td->urb = urb; | |
545 | td->data_dma = data; | |
546 | if (!len) | |
547 | data = 0; | |
548 | ||
549 | td->hwINFO = cpu_to_hc32 (ohci, info); | |
550 | if (is_iso) { | |
551 | td->hwCBP = cpu_to_hc32 (ohci, data & 0xFFFFF000); | |
552 | *ohci_hwPSWp(ohci, td, 0) = cpu_to_hc16 (ohci, | |
553 | (data & 0x0FFF) | 0xE000); | |
554 | td->ed->last_iso = info & 0xffff; | |
555 | } else { | |
556 | td->hwCBP = cpu_to_hc32 (ohci, data); | |
557 | } | |
558 | if (data) | |
559 | td->hwBE = cpu_to_hc32 (ohci, data + len - 1); | |
560 | else | |
561 | td->hwBE = 0; | |
562 | td->hwNextTD = cpu_to_hc32 (ohci, td_pt->td_dma); | |
563 | ||
564 | /* append to queue */ | |
565 | list_add_tail (&td->td_list, &td->ed->td_list); | |
566 | ||
567 | /* hash it for later reverse mapping */ | |
568 | hash = TD_HASH_FUNC (td->td_dma); | |
569 | td->td_hash = ohci->td_hash [hash]; | |
570 | ohci->td_hash [hash] = td; | |
571 | ||
572 | /* HC might read the TD (or cachelines) right away ... */ | |
573 | wmb (); | |
574 | td->ed->hwTailP = td->hwNextTD; | |
575 | } | |
576 | ||
577 | /*-------------------------------------------------------------------------*/ | |
578 | ||
579 | /* Prepare all TDs of a transfer, and queue them onto the ED. | |
580 | * Caller guarantees HC is active. | |
581 | * Usually the ED is already on the schedule, so TDs might be | |
582 | * processed as soon as they're queued. | |
583 | */ | |
584 | static void td_submit_urb ( | |
585 | struct ohci_hcd *ohci, | |
586 | struct urb *urb | |
587 | ) { | |
588 | struct urb_priv *urb_priv = urb->hcpriv; | |
589 | dma_addr_t data; | |
590 | int data_len = urb->transfer_buffer_length; | |
591 | int cnt = 0; | |
592 | u32 info = 0; | |
593 | int is_out = usb_pipeout (urb->pipe); | |
594 | int periodic = 0; | |
595 | ||
596 | /* OHCI handles the bulk/interrupt data toggles itself. We just | |
597 | * use the device toggle bits for resetting, and rely on the fact | |
598 | * that resetting toggle is meaningless if the endpoint is active. | |
599 | */ | |
600 | if (!usb_gettoggle (urb->dev, usb_pipeendpoint (urb->pipe), is_out)) { | |
601 | usb_settoggle (urb->dev, usb_pipeendpoint (urb->pipe), | |
602 | is_out, 1); | |
603 | urb_priv->ed->hwHeadP &= ~cpu_to_hc32 (ohci, ED_C); | |
604 | } | |
605 | ||
606 | urb_priv->td_cnt = 0; | |
607 | list_add (&urb_priv->pending, &ohci->pending); | |
608 | ||
609 | if (data_len) | |
610 | data = urb->transfer_dma; | |
611 | else | |
612 | data = 0; | |
613 | ||
614 | /* NOTE: TD_CC is set so we can tell which TDs the HC processed by | |
615 | * using TD_CC_GET, as well as by seeing them on the done list. | |
616 | * (CC = NotAccessed ... 0x0F, or 0x0E in PSWs for ISO.) | |
617 | */ | |
618 | switch (urb_priv->ed->type) { | |
619 | ||
620 | /* Bulk and interrupt are identical except for where in the schedule | |
621 | * their EDs live. | |
622 | */ | |
623 | case PIPE_INTERRUPT: | |
624 | /* ... and periodic urbs have extra accounting */ | |
625 | periodic = ohci_to_hcd(ohci)->self.bandwidth_int_reqs++ == 0 | |
626 | && ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0; | |
627 | /* FALLTHROUGH */ | |
628 | case PIPE_BULK: | |
629 | info = is_out | |
630 | ? TD_T_TOGGLE | TD_CC | TD_DP_OUT | |
631 | : TD_T_TOGGLE | TD_CC | TD_DP_IN; | |
632 | /* TDs _could_ transfer up to 8K each */ | |
633 | while (data_len > 4096) { | |
634 | td_fill (ohci, info, data, 4096, urb, cnt); | |
635 | data += 4096; | |
636 | data_len -= 4096; | |
637 | cnt++; | |
638 | } | |
639 | /* maybe avoid ED halt on final TD short read */ | |
640 | if (!(urb->transfer_flags & URB_SHORT_NOT_OK)) | |
641 | info |= TD_R; | |
642 | td_fill (ohci, info, data, data_len, urb, cnt); | |
643 | cnt++; | |
644 | if ((urb->transfer_flags & URB_ZERO_PACKET) | |
645 | && cnt < urb_priv->length) { | |
646 | td_fill (ohci, info, 0, 0, urb, cnt); | |
647 | cnt++; | |
648 | } | |
649 | /* maybe kickstart bulk list */ | |
650 | if (urb_priv->ed->type == PIPE_BULK) { | |
651 | wmb (); | |
652 | ohci_writel (ohci, OHCI_BLF, &ohci->regs->cmdstatus); | |
653 | } | |
654 | break; | |
655 | ||
656 | /* control manages DATA0/DATA1 toggle per-request; SETUP resets it, | |
657 | * any DATA phase works normally, and the STATUS ack is special. | |
658 | */ | |
659 | case PIPE_CONTROL: | |
660 | info = TD_CC | TD_DP_SETUP | TD_T_DATA0; | |
661 | td_fill (ohci, info, urb->setup_dma, 8, urb, cnt++); | |
662 | if (data_len > 0) { | |
663 | info = TD_CC | TD_R | TD_T_DATA1; | |
664 | info |= is_out ? TD_DP_OUT : TD_DP_IN; | |
665 | /* NOTE: mishandles transfers >8K, some >4K */ | |
666 | td_fill (ohci, info, data, data_len, urb, cnt++); | |
667 | } | |
668 | info = (is_out || data_len == 0) | |
669 | ? TD_CC | TD_DP_IN | TD_T_DATA1 | |
670 | : TD_CC | TD_DP_OUT | TD_T_DATA1; | |
671 | td_fill (ohci, info, data, 0, urb, cnt++); | |
672 | /* maybe kickstart control list */ | |
673 | wmb (); | |
674 | ohci_writel (ohci, OHCI_CLF, &ohci->regs->cmdstatus); | |
675 | break; | |
676 | ||
677 | /* ISO has no retransmit, so no toggle; and it uses special TDs. | |
678 | * Each TD could handle multiple consecutive frames (interval 1); | |
679 | * we could often reduce the number of TDs here. | |
680 | */ | |
681 | case PIPE_ISOCHRONOUS: | |
682 | for (cnt = 0; cnt < urb->number_of_packets; cnt++) { | |
683 | int frame = urb->start_frame; | |
684 | ||
685 | // FIXME scheduling should handle frame counter | |
686 | // roll-around ... exotic case (and OHCI has | |
687 | // a 2^16 iso range, vs other HCs max of 2^10) | |
688 | frame += cnt * urb->interval; | |
689 | frame &= 0xffff; | |
690 | td_fill (ohci, TD_CC | TD_ISO | frame, | |
691 | data + urb->iso_frame_desc [cnt].offset, | |
692 | urb->iso_frame_desc [cnt].length, urb, cnt); | |
693 | } | |
694 | periodic = ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs++ == 0 | |
695 | && ohci_to_hcd(ohci)->self.bandwidth_int_reqs == 0; | |
696 | break; | |
697 | } | |
698 | ||
699 | /* start periodic dma if needed */ | |
700 | if (periodic) { | |
701 | wmb (); | |
702 | ohci->hc_control |= OHCI_CTRL_PLE|OHCI_CTRL_IE; | |
703 | ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); | |
704 | } | |
705 | ||
706 | // ASSERT (urb_priv->length == cnt); | |
707 | } | |
708 | ||
709 | /*-------------------------------------------------------------------------* | |
710 | * Done List handling functions | |
711 | *-------------------------------------------------------------------------*/ | |
712 | ||
713 | /* calculate transfer length/status and update the urb | |
714 | * PRECONDITION: irqsafe (only for urb->status locking) | |
715 | */ | |
716 | static void td_done (struct ohci_hcd *ohci, struct urb *urb, struct td *td) | |
717 | { | |
718 | u32 tdINFO = hc32_to_cpup (ohci, &td->hwINFO); | |
719 | int cc = 0; | |
720 | ||
721 | list_del (&td->td_list); | |
722 | ||
723 | /* ISO ... drivers see per-TD length/status */ | |
724 | if (tdINFO & TD_ISO) { | |
725 | u16 tdPSW = ohci_hwPSW (ohci, td, 0); | |
726 | int dlen = 0; | |
727 | ||
728 | /* NOTE: assumes FC in tdINFO == 0, and that | |
729 | * only the first of 0..MAXPSW psws is used. | |
730 | */ | |
731 | ||
732 | cc = (tdPSW >> 12) & 0xF; | |
733 | if (tdINFO & TD_CC) /* hc didn't touch? */ | |
734 | return; | |
735 | ||
736 | if (usb_pipeout (urb->pipe)) | |
737 | dlen = urb->iso_frame_desc [td->index].length; | |
738 | else { | |
739 | /* short reads are always OK for ISO */ | |
740 | if (cc == TD_DATAUNDERRUN) | |
741 | cc = TD_CC_NOERROR; | |
742 | dlen = tdPSW & 0x3ff; | |
743 | } | |
744 | urb->actual_length += dlen; | |
745 | urb->iso_frame_desc [td->index].actual_length = dlen; | |
746 | urb->iso_frame_desc [td->index].status = cc_to_error [cc]; | |
747 | ||
748 | if (cc != TD_CC_NOERROR) | |
749 | ohci_vdbg (ohci, | |
750 | "urb %p iso td %p (%d) len %d cc %d\n", | |
751 | urb, td, 1 + td->index, dlen, cc); | |
752 | ||
753 | /* BULK, INT, CONTROL ... drivers see aggregate length/status, | |
754 | * except that "setup" bytes aren't counted and "short" transfers | |
755 | * might not be reported as errors. | |
756 | */ | |
757 | } else { | |
758 | int type = usb_pipetype (urb->pipe); | |
759 | u32 tdBE = hc32_to_cpup (ohci, &td->hwBE); | |
760 | ||
761 | cc = TD_CC_GET (tdINFO); | |
762 | ||
763 | /* update packet status if needed (short is normally ok) */ | |
764 | if (cc == TD_DATAUNDERRUN | |
765 | && !(urb->transfer_flags & URB_SHORT_NOT_OK)) | |
766 | cc = TD_CC_NOERROR; | |
767 | if (cc != TD_CC_NOERROR && cc < 0x0E) { | |
768 | spin_lock (&urb->lock); | |
769 | if (urb->status == -EINPROGRESS) | |
770 | urb->status = cc_to_error [cc]; | |
771 | spin_unlock (&urb->lock); | |
772 | } | |
773 | ||
774 | /* count all non-empty packets except control SETUP packet */ | |
775 | if ((type != PIPE_CONTROL || td->index != 0) && tdBE != 0) { | |
776 | if (td->hwCBP == 0) | |
777 | urb->actual_length += tdBE - td->data_dma + 1; | |
778 | else | |
779 | urb->actual_length += | |
780 | hc32_to_cpup (ohci, &td->hwCBP) | |
781 | - td->data_dma; | |
782 | } | |
783 | ||
784 | if (cc != TD_CC_NOERROR && cc < 0x0E) | |
785 | ohci_vdbg (ohci, | |
786 | "urb %p td %p (%d) cc %d, len=%d/%d\n", | |
787 | urb, td, 1 + td->index, cc, | |
788 | urb->actual_length, | |
789 | urb->transfer_buffer_length); | |
790 | } | |
791 | } | |
792 | ||
793 | /*-------------------------------------------------------------------------*/ | |
794 | ||
795 | static inline struct td * | |
796 | ed_halted (struct ohci_hcd *ohci, struct td *td, int cc, struct td *rev) | |
797 | { | |
798 | struct urb *urb = td->urb; | |
799 | struct ed *ed = td->ed; | |
800 | struct list_head *tmp = td->td_list.next; | |
801 | __hc32 toggle = ed->hwHeadP & cpu_to_hc32 (ohci, ED_C); | |
802 | ||
803 | /* clear ed halt; this is the td that caused it, but keep it inactive | |
804 | * until its urb->complete() has a chance to clean up. | |
805 | */ | |
806 | ed->hwINFO |= cpu_to_hc32 (ohci, ED_SKIP); | |
807 | wmb (); | |
808 | ed->hwHeadP &= ~cpu_to_hc32 (ohci, ED_H); | |
809 | ||
810 | /* put any later tds from this urb onto the donelist, after 'td', | |
811 | * order won't matter here: no errors, and nothing was transferred. | |
812 | * also patch the ed so it looks as if those tds completed normally. | |
813 | */ | |
814 | while (tmp != &ed->td_list) { | |
815 | struct td *next; | |
816 | __hc32 info; | |
817 | ||
818 | next = list_entry (tmp, struct td, td_list); | |
819 | tmp = next->td_list.next; | |
820 | ||
821 | if (next->urb != urb) | |
822 | break; | |
823 | ||
824 | /* NOTE: if multi-td control DATA segments get supported, | |
825 | * this urb had one of them, this td wasn't the last td | |
826 | * in that segment (TD_R clear), this ed halted because | |
827 | * of a short read, _and_ URB_SHORT_NOT_OK is clear ... | |
828 | * then we need to leave the control STATUS packet queued | |
829 | * and clear ED_SKIP. | |
830 | */ | |
831 | info = next->hwINFO; | |
832 | info |= cpu_to_hc32 (ohci, TD_DONE); | |
833 | info &= ~cpu_to_hc32 (ohci, TD_CC); | |
834 | next->hwINFO = info; | |
835 | ||
836 | next->next_dl_td = rev; | |
837 | rev = next; | |
838 | ||
839 | ed->hwHeadP = next->hwNextTD | toggle; | |
840 | } | |
841 | ||
842 | /* help for troubleshooting: report anything that | |
843 | * looks odd ... that doesn't include protocol stalls | |
844 | * (or maybe some other things) | |
845 | */ | |
846 | switch (cc) { | |
847 | case TD_DATAUNDERRUN: | |
848 | if ((urb->transfer_flags & URB_SHORT_NOT_OK) == 0) | |
849 | break; | |
850 | /* fallthrough */ | |
851 | case TD_CC_STALL: | |
852 | if (usb_pipecontrol (urb->pipe)) | |
853 | break; | |
854 | /* fallthrough */ | |
855 | default: | |
856 | ohci_dbg (ohci, | |
857 | "urb %p path %s ep%d%s %08x cc %d --> status %d\n", | |
858 | urb, urb->dev->devpath, | |
859 | usb_pipeendpoint (urb->pipe), | |
860 | usb_pipein (urb->pipe) ? "in" : "out", | |
861 | hc32_to_cpu (ohci, td->hwINFO), | |
862 | cc, cc_to_error [cc]); | |
863 | } | |
864 | ||
865 | return rev; | |
866 | } | |
867 | ||
868 | /* replies to the request have to be on a FIFO basis so | |
869 | * we unreverse the hc-reversed done-list | |
870 | */ | |
871 | static struct td *dl_reverse_done_list (struct ohci_hcd *ohci) | |
872 | { | |
873 | u32 td_dma; | |
874 | struct td *td_rev = NULL; | |
875 | struct td *td = NULL; | |
876 | ||
877 | td_dma = hc32_to_cpup (ohci, &ohci->hcca->done_head); | |
878 | ohci->hcca->done_head = 0; | |
879 | wmb(); | |
880 | ||
881 | /* get TD from hc's singly linked list, and | |
882 | * prepend to ours. ed->td_list changes later. | |
883 | */ | |
884 | while (td_dma) { | |
885 | int cc; | |
886 | ||
887 | td = dma_to_td (ohci, td_dma); | |
888 | if (!td) { | |
889 | ohci_err (ohci, "bad entry %8x\n", td_dma); | |
890 | break; | |
891 | } | |
892 | ||
893 | td->hwINFO |= cpu_to_hc32 (ohci, TD_DONE); | |
894 | cc = TD_CC_GET (hc32_to_cpup (ohci, &td->hwINFO)); | |
895 | ||
896 | /* Non-iso endpoints can halt on error; un-halt, | |
897 | * and dequeue any other TDs from this urb. | |
898 | * No other TD could have caused the halt. | |
899 | */ | |
900 | if (cc != TD_CC_NOERROR | |
901 | && (td->ed->hwHeadP & cpu_to_hc32 (ohci, ED_H))) | |
902 | td_rev = ed_halted (ohci, td, cc, td_rev); | |
903 | ||
904 | td->next_dl_td = td_rev; | |
905 | td_rev = td; | |
906 | td_dma = hc32_to_cpup (ohci, &td->hwNextTD); | |
907 | } | |
908 | return td_rev; | |
909 | } | |
910 | ||
911 | /*-------------------------------------------------------------------------*/ | |
912 | ||
913 | /* there are some urbs/eds to unlink; called in_irq(), with HCD locked */ | |
914 | static void | |
7d12e780 | 915 | finish_unlinks (struct ohci_hcd *ohci, u16 tick) |
1da177e4 LT |
916 | { |
917 | struct ed *ed, **last; | |
918 | ||
919 | rescan_all: | |
920 | for (last = &ohci->ed_rm_list, ed = *last; ed != NULL; ed = *last) { | |
921 | struct list_head *entry, *tmp; | |
922 | int completed, modified; | |
923 | __hc32 *prev; | |
924 | ||
925 | /* only take off EDs that the HC isn't using, accounting for | |
926 | * frame counter wraps and EDs with partially retired TDs | |
927 | */ | |
7d12e780 | 928 | if (likely (get_irq_regs() && HC_IS_RUNNING(ohci_to_hcd(ohci)->state))) { |
1da177e4 LT |
929 | if (tick_before (tick, ed->tick)) { |
930 | skip_ed: | |
931 | last = &ed->ed_next; | |
932 | continue; | |
933 | } | |
934 | ||
935 | if (!list_empty (&ed->td_list)) { | |
936 | struct td *td; | |
937 | u32 head; | |
938 | ||
939 | td = list_entry (ed->td_list.next, struct td, | |
940 | td_list); | |
941 | head = hc32_to_cpu (ohci, ed->hwHeadP) & | |
942 | TD_MASK; | |
943 | ||
944 | /* INTR_WDH may need to clean up first */ | |
945 | if (td->td_dma != head) | |
946 | goto skip_ed; | |
947 | } | |
948 | } | |
949 | ||
950 | /* reentrancy: if we drop the schedule lock, someone might | |
951 | * have modified this list. normally it's just prepending | |
952 | * entries (which we'd ignore), but paranoia won't hurt. | |
953 | */ | |
954 | *last = ed->ed_next; | |
955 | ed->ed_next = NULL; | |
956 | modified = 0; | |
957 | ||
958 | /* unlink urbs as requested, but rescan the list after | |
959 | * we call a completion since it might have unlinked | |
960 | * another (earlier) urb | |
961 | * | |
962 | * When we get here, the HC doesn't see this ed. But it | |
963 | * must not be rescheduled until all completed URBs have | |
964 | * been given back to the driver. | |
965 | */ | |
966 | rescan_this: | |
967 | completed = 0; | |
968 | prev = &ed->hwHeadP; | |
969 | list_for_each_safe (entry, tmp, &ed->td_list) { | |
970 | struct td *td; | |
971 | struct urb *urb; | |
972 | urb_priv_t *urb_priv; | |
973 | __hc32 savebits; | |
974 | ||
975 | td = list_entry (entry, struct td, td_list); | |
976 | urb = td->urb; | |
977 | urb_priv = td->urb->hcpriv; | |
978 | ||
979 | if (urb->status == -EINPROGRESS) { | |
980 | prev = &td->hwNextTD; | |
981 | continue; | |
982 | } | |
983 | ||
984 | /* patch pointer hc uses */ | |
985 | savebits = *prev & ~cpu_to_hc32 (ohci, TD_MASK); | |
986 | *prev = td->hwNextTD | savebits; | |
987 | ||
988 | /* HC may have partly processed this TD */ | |
989 | td_done (ohci, urb, td); | |
990 | urb_priv->td_cnt++; | |
991 | ||
992 | /* if URB is done, clean up */ | |
993 | if (urb_priv->td_cnt == urb_priv->length) { | |
994 | modified = completed = 1; | |
7d12e780 | 995 | finish_urb (ohci, urb); |
1da177e4 LT |
996 | } |
997 | } | |
998 | if (completed && !list_empty (&ed->td_list)) | |
999 | goto rescan_this; | |
1000 | ||
1001 | /* ED's now officially unlinked, hc doesn't see */ | |
1002 | ed->state = ED_IDLE; | |
1003 | ed->hwHeadP &= ~cpu_to_hc32(ohci, ED_H); | |
1004 | ed->hwNextED = 0; | |
1005 | wmb (); | |
1006 | ed->hwINFO &= ~cpu_to_hc32 (ohci, ED_SKIP | ED_DEQUEUE); | |
1007 | ||
1008 | /* but if there's work queued, reschedule */ | |
1009 | if (!list_empty (&ed->td_list)) { | |
1010 | if (HC_IS_RUNNING(ohci_to_hcd(ohci)->state)) | |
1011 | ed_schedule (ohci, ed); | |
1012 | } | |
1013 | ||
1014 | if (modified) | |
1015 | goto rescan_all; | |
1016 | } | |
1017 | ||
1018 | /* maybe reenable control and bulk lists */ | |
1019 | if (HC_IS_RUNNING(ohci_to_hcd(ohci)->state) | |
1020 | && ohci_to_hcd(ohci)->state != HC_STATE_QUIESCING | |
1021 | && !ohci->ed_rm_list) { | |
1022 | u32 command = 0, control = 0; | |
1023 | ||
1024 | if (ohci->ed_controltail) { | |
1025 | command |= OHCI_CLF; | |
0e498763 DB |
1026 | if (ohci->flags & OHCI_QUIRK_ZFMICRO) |
1027 | mdelay(1); | |
1da177e4 LT |
1028 | if (!(ohci->hc_control & OHCI_CTRL_CLE)) { |
1029 | control |= OHCI_CTRL_CLE; | |
1030 | ohci_writel (ohci, 0, | |
1031 | &ohci->regs->ed_controlcurrent); | |
1032 | } | |
1033 | } | |
1034 | if (ohci->ed_bulktail) { | |
1035 | command |= OHCI_BLF; | |
0e498763 DB |
1036 | if (ohci->flags & OHCI_QUIRK_ZFMICRO) |
1037 | mdelay(1); | |
1da177e4 LT |
1038 | if (!(ohci->hc_control & OHCI_CTRL_BLE)) { |
1039 | control |= OHCI_CTRL_BLE; | |
1040 | ohci_writel (ohci, 0, | |
1041 | &ohci->regs->ed_bulkcurrent); | |
1042 | } | |
1043 | } | |
1044 | ||
1045 | /* CLE/BLE to enable, CLF/BLF to (maybe) kickstart */ | |
1046 | if (control) { | |
1047 | ohci->hc_control |= control; | |
0e498763 DB |
1048 | if (ohci->flags & OHCI_QUIRK_ZFMICRO) |
1049 | mdelay(1); | |
1da177e4 LT |
1050 | ohci_writel (ohci, ohci->hc_control, |
1051 | &ohci->regs->control); | |
1052 | } | |
0e498763 DB |
1053 | if (command) { |
1054 | if (ohci->flags & OHCI_QUIRK_ZFMICRO) | |
1055 | mdelay(1); | |
1da177e4 | 1056 | ohci_writel (ohci, command, &ohci->regs->cmdstatus); |
0e498763 DB |
1057 | } |
1058 | } | |
1da177e4 LT |
1059 | } |
1060 | ||
1061 | ||
1062 | ||
1063 | /*-------------------------------------------------------------------------*/ | |
1064 | ||
1065 | /* | |
1066 | * Process normal completions (error or success) and clean the schedules. | |
1067 | * | |
1068 | * This is the main path for handing urbs back to drivers. The only other | |
1069 | * path is finish_unlinks(), which unlinks URBs using ed_rm_list, instead of | |
1070 | * scanning the (re-reversed) donelist as this does. | |
1071 | */ | |
1072 | static void | |
7d12e780 | 1073 | dl_done_list (struct ohci_hcd *ohci) |
1da177e4 LT |
1074 | { |
1075 | struct td *td = dl_reverse_done_list (ohci); | |
1076 | ||
1077 | while (td) { | |
1078 | struct td *td_next = td->next_dl_td; | |
1079 | struct urb *urb = td->urb; | |
1080 | urb_priv_t *urb_priv = urb->hcpriv; | |
1081 | struct ed *ed = td->ed; | |
1082 | ||
1083 | /* update URB's length and status from TD */ | |
1084 | td_done (ohci, urb, td); | |
1085 | urb_priv->td_cnt++; | |
1086 | ||
1087 | /* If all this urb's TDs are done, call complete() */ | |
1088 | if (urb_priv->td_cnt == urb_priv->length) | |
7d12e780 | 1089 | finish_urb (ohci, urb); |
1da177e4 LT |
1090 | |
1091 | /* clean schedule: unlink EDs that are no longer busy */ | |
1092 | if (list_empty (&ed->td_list)) { | |
1093 | if (ed->state == ED_OPER) | |
1094 | start_ed_unlink (ohci, ed); | |
1095 | ||
1096 | /* ... reenabling halted EDs only after fault cleanup */ | |
1097 | } else if ((ed->hwINFO & cpu_to_hc32 (ohci, ED_SKIP | ED_DEQUEUE)) | |
1098 | == cpu_to_hc32 (ohci, ED_SKIP)) { | |
1099 | td = list_entry (ed->td_list.next, struct td, td_list); | |
1100 | if (!(td->hwINFO & cpu_to_hc32 (ohci, TD_DONE))) { | |
1101 | ed->hwINFO &= ~cpu_to_hc32 (ohci, ED_SKIP); | |
1102 | /* ... hc may need waking-up */ | |
1103 | switch (ed->type) { | |
1104 | case PIPE_CONTROL: | |
1105 | ohci_writel (ohci, OHCI_CLF, | |
1106 | &ohci->regs->cmdstatus); | |
1107 | break; | |
1108 | case PIPE_BULK: | |
1109 | ohci_writel (ohci, OHCI_BLF, | |
1110 | &ohci->regs->cmdstatus); | |
1111 | break; | |
1112 | } | |
1113 | } | |
1114 | } | |
1115 | ||
1116 | td = td_next; | |
1117 | } | |
1118 | } |