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1da177e4 LT |
1 | #ifndef __LINUX_UHCI_HCD_H |
2 | #define __LINUX_UHCI_HCD_H | |
3 | ||
4 | #include <linux/list.h> | |
5 | #include <linux/usb.h> | |
6 | ||
7 | #define usb_packetid(pipe) (usb_pipein(pipe) ? USB_PID_IN : USB_PID_OUT) | |
8 | #define PIPE_DEVEP_MASK 0x0007ff00 | |
9 | ||
8b262bd2 | 10 | |
1da177e4 LT |
11 | /* |
12 | * Universal Host Controller Interface data structures and defines | |
13 | */ | |
14 | ||
15 | /* Command register */ | |
16 | #define USBCMD 0 | |
17 | #define USBCMD_RS 0x0001 /* Run/Stop */ | |
18 | #define USBCMD_HCRESET 0x0002 /* Host reset */ | |
19 | #define USBCMD_GRESET 0x0004 /* Global reset */ | |
20 | #define USBCMD_EGSM 0x0008 /* Global Suspend Mode */ | |
21 | #define USBCMD_FGR 0x0010 /* Force Global Resume */ | |
22 | #define USBCMD_SWDBG 0x0020 /* SW Debug mode */ | |
23 | #define USBCMD_CF 0x0040 /* Config Flag (sw only) */ | |
24 | #define USBCMD_MAXP 0x0080 /* Max Packet (0 = 32, 1 = 64) */ | |
25 | ||
26 | /* Status register */ | |
27 | #define USBSTS 2 | |
28 | #define USBSTS_USBINT 0x0001 /* Interrupt due to IOC */ | |
29 | #define USBSTS_ERROR 0x0002 /* Interrupt due to error */ | |
30 | #define USBSTS_RD 0x0004 /* Resume Detect */ | |
dccf4a48 AS |
31 | #define USBSTS_HSE 0x0008 /* Host System Error: PCI problems */ |
32 | #define USBSTS_HCPE 0x0010 /* Host Controller Process Error: | |
33 | * the schedule is buggy */ | |
1da177e4 LT |
34 | #define USBSTS_HCH 0x0020 /* HC Halted */ |
35 | ||
36 | /* Interrupt enable register */ | |
37 | #define USBINTR 4 | |
38 | #define USBINTR_TIMEOUT 0x0001 /* Timeout/CRC error enable */ | |
39 | #define USBINTR_RESUME 0x0002 /* Resume interrupt enable */ | |
40 | #define USBINTR_IOC 0x0004 /* Interrupt On Complete enable */ | |
41 | #define USBINTR_SP 0x0008 /* Short packet interrupt enable */ | |
42 | ||
43 | #define USBFRNUM 6 | |
44 | #define USBFLBASEADD 8 | |
45 | #define USBSOF 12 | |
a8bed8b6 | 46 | #define USBSOF_DEFAULT 64 /* Frame length is exactly 1 ms */ |
1da177e4 LT |
47 | |
48 | /* USB port status and control registers */ | |
49 | #define USBPORTSC1 16 | |
50 | #define USBPORTSC2 18 | |
dccf4a48 AS |
51 | #define USBPORTSC_CCS 0x0001 /* Current Connect Status |
52 | * ("device present") */ | |
1da177e4 LT |
53 | #define USBPORTSC_CSC 0x0002 /* Connect Status Change */ |
54 | #define USBPORTSC_PE 0x0004 /* Port Enable */ | |
55 | #define USBPORTSC_PEC 0x0008 /* Port Enable Change */ | |
56 | #define USBPORTSC_DPLUS 0x0010 /* D+ high (line status) */ | |
57 | #define USBPORTSC_DMINUS 0x0020 /* D- high (line status) */ | |
58 | #define USBPORTSC_RD 0x0040 /* Resume Detect */ | |
59 | #define USBPORTSC_RES1 0x0080 /* reserved, always 1 */ | |
60 | #define USBPORTSC_LSDA 0x0100 /* Low Speed Device Attached */ | |
61 | #define USBPORTSC_PR 0x0200 /* Port Reset */ | |
62 | /* OC and OCC from Intel 430TX and later (not UHCI 1.1d spec) */ | |
63 | #define USBPORTSC_OC 0x0400 /* Over Current condition */ | |
64 | #define USBPORTSC_OCC 0x0800 /* Over Current Change R/WC */ | |
65 | #define USBPORTSC_SUSP 0x1000 /* Suspend */ | |
66 | #define USBPORTSC_RES2 0x2000 /* reserved, write zeroes */ | |
67 | #define USBPORTSC_RES3 0x4000 /* reserved, write zeroes */ | |
68 | #define USBPORTSC_RES4 0x8000 /* reserved, write zeroes */ | |
69 | ||
70 | /* Legacy support register */ | |
71 | #define USBLEGSUP 0xc0 | |
72 | #define USBLEGSUP_DEFAULT 0x2000 /* only PIRQ enable set */ | |
a8bed8b6 AS |
73 | #define USBLEGSUP_RWC 0x8f00 /* the R/WC bits */ |
74 | #define USBLEGSUP_RO 0x5040 /* R/O and reserved bits */ | |
1da177e4 | 75 | |
551509d2 HH |
76 | #define UHCI_PTR_BITS cpu_to_le32(0x000F) |
77 | #define UHCI_PTR_TERM cpu_to_le32(0x0001) | |
78 | #define UHCI_PTR_QH cpu_to_le32(0x0002) | |
79 | #define UHCI_PTR_DEPTH cpu_to_le32(0x0004) | |
80 | #define UHCI_PTR_BREADTH cpu_to_le32(0x0000) | |
1da177e4 LT |
81 | |
82 | #define UHCI_NUMFRAMES 1024 /* in the frame list [array] */ | |
83 | #define UHCI_MAX_SOF_NUMBER 2047 /* in an SOF packet */ | |
dccf4a48 AS |
84 | #define CAN_SCHEDULE_FRAMES 1000 /* how far in the future frames |
85 | * can be scheduled */ | |
3ca2a321 | 86 | #define MAX_PHASE 32 /* Periodic scheduling length */ |
1da177e4 | 87 | |
84afddd7 AS |
88 | /* When no queues need Full-Speed Bandwidth Reclamation, |
89 | * delay this long before turning FSBR off */ | |
c5e3b741 | 90 | #define FSBR_OFF_DELAY msecs_to_jiffies(10) |
84afddd7 AS |
91 | |
92 | /* If a queue hasn't advanced after this much time, assume it is stuck */ | |
93 | #define QH_WAIT_TIMEOUT msecs_to_jiffies(200) | |
94 | ||
1da177e4 | 95 | |
8b262bd2 AS |
96 | /* |
97 | * Queue Headers | |
98 | */ | |
1da177e4 LT |
99 | |
100 | /* | |
dccf4a48 AS |
101 | * One role of a QH is to hold a queue of TDs for some endpoint. One QH goes |
102 | * with each endpoint, and qh->element (updated by the HC) is either: | |
103 | * - the next unprocessed TD in the endpoint's queue, or | |
104 | * - UHCI_PTR_TERM (when there's no more traffic for this endpoint). | |
1da177e4 LT |
105 | * |
106 | * The other role of a QH is to serve as a "skeleton" framelist entry, so we | |
107 | * can easily splice a QH for some endpoint into the schedule at the right | |
108 | * place. Then qh->element is UHCI_PTR_TERM. | |
109 | * | |
dccf4a48 | 110 | * In the schedule, qh->link maintains a list of QHs seen by the HC: |
1da177e4 | 111 | * skel1 --> ep1-qh --> ep2-qh --> ... --> skel2 --> ... |
dccf4a48 AS |
112 | * |
113 | * qh->node is the software equivalent of qh->link. The differences | |
114 | * are that the software list is doubly-linked and QHs in the UNLINKING | |
115 | * state are on the software list but not the hardware schedule. | |
116 | * | |
117 | * For bookkeeping purposes we maintain QHs even for Isochronous endpoints, | |
118 | * but they never get added to the hardware schedule. | |
1da177e4 | 119 | */ |
dccf4a48 AS |
120 | #define QH_STATE_IDLE 1 /* QH is not being used */ |
121 | #define QH_STATE_UNLINKING 2 /* QH has been removed from the | |
122 | * schedule but the hardware may | |
123 | * still be using it */ | |
124 | #define QH_STATE_ACTIVE 3 /* QH is on the schedule */ | |
125 | ||
1da177e4 LT |
126 | struct uhci_qh { |
127 | /* Hardware fields */ | |
dccf4a48 AS |
128 | __le32 link; /* Next QH in the schedule */ |
129 | __le32 element; /* Queue element (TD) pointer */ | |
1da177e4 LT |
130 | |
131 | /* Software fields */ | |
28b9325e AS |
132 | dma_addr_t dma_handle; |
133 | ||
dccf4a48 AS |
134 | struct list_head node; /* Node in the list of QHs */ |
135 | struct usb_host_endpoint *hep; /* Endpoint information */ | |
136 | struct usb_device *udev; | |
137 | struct list_head queue; /* Queue of urbps for this QH */ | |
af0bb599 | 138 | struct uhci_td *dummy_td; /* Dummy TD to end the queue */ |
59e29ed9 | 139 | struct uhci_td *post_td; /* Last TD completed */ |
1da177e4 | 140 | |
c8155cc5 AS |
141 | struct usb_iso_packet_descriptor *iso_packet_desc; |
142 | /* Next urb->iso_frame_desc entry */ | |
84afddd7 | 143 | unsigned long advance_jiffies; /* Time of last queue advance */ |
dccf4a48 | 144 | unsigned int unlink_frame; /* When the QH was unlinked */ |
caf3827a | 145 | unsigned int period; /* For Interrupt and Isochronous QHs */ |
3ca2a321 AS |
146 | short phase; /* Between 0 and period-1 */ |
147 | short load; /* Periodic time requirement, in us */ | |
c8155cc5 | 148 | unsigned int iso_frame; /* Frame # for iso_packet_desc */ |
caf3827a | 149 | |
dccf4a48 | 150 | int state; /* QH_STATE_xxx; see above */ |
4de7d2c2 | 151 | int type; /* Queue type (control, bulk, etc) */ |
17230acd | 152 | int skel; /* Skeleton queue number */ |
0ed8fee1 AS |
153 | |
154 | unsigned int initial_toggle:1; /* Endpoint's current toggle value */ | |
155 | unsigned int needs_fixup:1; /* Must fix the TD toggle values */ | |
59e29ed9 | 156 | unsigned int is_stopped:1; /* Queue was stopped by error/unlink */ |
84afddd7 | 157 | unsigned int wait_expired:1; /* QH_WAIT_TIMEOUT has expired */ |
3ca2a321 AS |
158 | unsigned int bandwidth_reserved:1; /* Periodic bandwidth has |
159 | * been allocated */ | |
1da177e4 LT |
160 | } __attribute__((aligned(16))); |
161 | ||
162 | /* | |
163 | * We need a special accessor for the element pointer because it is | |
8b262bd2 | 164 | * subject to asynchronous updates by the controller. |
1da177e4 | 165 | */ |
dccf4a48 | 166 | static inline __le32 qh_element(struct uhci_qh *qh) { |
1da177e4 LT |
167 | __le32 element = qh->element; |
168 | ||
169 | barrier(); | |
170 | return element; | |
171 | } | |
172 | ||
28b9325e AS |
173 | #define LINK_TO_QH(qh) (UHCI_PTR_QH | cpu_to_le32((qh)->dma_handle)) |
174 | ||
8b262bd2 AS |
175 | |
176 | /* | |
177 | * Transfer Descriptors | |
178 | */ | |
179 | ||
1da177e4 LT |
180 | /* |
181 | * for TD <status>: | |
182 | */ | |
183 | #define TD_CTRL_SPD (1 << 29) /* Short Packet Detect */ | |
184 | #define TD_CTRL_C_ERR_MASK (3 << 27) /* Error Counter bits */ | |
185 | #define TD_CTRL_C_ERR_SHIFT 27 | |
186 | #define TD_CTRL_LS (1 << 26) /* Low Speed Device */ | |
187 | #define TD_CTRL_IOS (1 << 25) /* Isochronous Select */ | |
188 | #define TD_CTRL_IOC (1 << 24) /* Interrupt on Complete */ | |
189 | #define TD_CTRL_ACTIVE (1 << 23) /* TD Active */ | |
190 | #define TD_CTRL_STALLED (1 << 22) /* TD Stalled */ | |
191 | #define TD_CTRL_DBUFERR (1 << 21) /* Data Buffer Error */ | |
192 | #define TD_CTRL_BABBLE (1 << 20) /* Babble Detected */ | |
193 | #define TD_CTRL_NAK (1 << 19) /* NAK Received */ | |
194 | #define TD_CTRL_CRCTIMEO (1 << 18) /* CRC/Time Out Error */ | |
195 | #define TD_CTRL_BITSTUFF (1 << 17) /* Bit Stuff Error */ | |
196 | #define TD_CTRL_ACTLEN_MASK 0x7FF /* actual length, encoded as n - 1 */ | |
197 | ||
198 | #define TD_CTRL_ANY_ERROR (TD_CTRL_STALLED | TD_CTRL_DBUFERR | \ | |
dccf4a48 AS |
199 | TD_CTRL_BABBLE | TD_CTRL_CRCTIME | \ |
200 | TD_CTRL_BITSTUFF) | |
1da177e4 LT |
201 | |
202 | #define uhci_maxerr(err) ((err) << TD_CTRL_C_ERR_SHIFT) | |
203 | #define uhci_status_bits(ctrl_sts) ((ctrl_sts) & 0xF60000) | |
dccf4a48 AS |
204 | #define uhci_actual_length(ctrl_sts) (((ctrl_sts) + 1) & \ |
205 | TD_CTRL_ACTLEN_MASK) /* 1-based */ | |
1da177e4 LT |
206 | |
207 | /* | |
208 | * for TD <info>: (a.k.a. Token) | |
209 | */ | |
210 | #define td_token(td) le32_to_cpu((td)->token) | |
211 | #define TD_TOKEN_DEVADDR_SHIFT 8 | |
212 | #define TD_TOKEN_TOGGLE_SHIFT 19 | |
213 | #define TD_TOKEN_TOGGLE (1 << 19) | |
214 | #define TD_TOKEN_EXPLEN_SHIFT 21 | |
dccf4a48 | 215 | #define TD_TOKEN_EXPLEN_MASK 0x7FF /* expected length, encoded as n-1 */ |
1da177e4 LT |
216 | #define TD_TOKEN_PID_MASK 0xFF |
217 | ||
fa346568 AS |
218 | #define uhci_explen(len) ((((len) - 1) & TD_TOKEN_EXPLEN_MASK) << \ |
219 | TD_TOKEN_EXPLEN_SHIFT) | |
1da177e4 | 220 | |
fa346568 AS |
221 | #define uhci_expected_length(token) ((((token) >> TD_TOKEN_EXPLEN_SHIFT) + \ |
222 | 1) & TD_TOKEN_EXPLEN_MASK) | |
1da177e4 LT |
223 | #define uhci_toggle(token) (((token) >> TD_TOKEN_TOGGLE_SHIFT) & 1) |
224 | #define uhci_endpoint(token) (((token) >> 15) & 0xf) | |
225 | #define uhci_devaddr(token) (((token) >> TD_TOKEN_DEVADDR_SHIFT) & 0x7f) | |
226 | #define uhci_devep(token) (((token) >> TD_TOKEN_DEVADDR_SHIFT) & 0x7ff) | |
227 | #define uhci_packetid(token) ((token) & TD_TOKEN_PID_MASK) | |
228 | #define uhci_packetout(token) (uhci_packetid(token) != USB_PID_IN) | |
229 | #define uhci_packetin(token) (uhci_packetid(token) == USB_PID_IN) | |
230 | ||
231 | /* | |
232 | * The documentation says "4 words for hardware, 4 words for software". | |
233 | * | |
234 | * That's silly, the hardware doesn't care. The hardware only cares that | |
235 | * the hardware words are 16-byte aligned, and we can have any amount of | |
8b262bd2 | 236 | * sw space after the TD entry. |
1da177e4 LT |
237 | * |
238 | * td->link points to either another TD (not necessarily for the same urb or | |
dccf4a48 | 239 | * even the same endpoint), or nothing (PTR_TERM), or a QH. |
1da177e4 LT |
240 | */ |
241 | struct uhci_td { | |
242 | /* Hardware fields */ | |
243 | __le32 link; | |
244 | __le32 status; | |
245 | __le32 token; | |
246 | __le32 buffer; | |
247 | ||
248 | /* Software fields */ | |
249 | dma_addr_t dma_handle; | |
250 | ||
8b262bd2 | 251 | struct list_head list; |
1da177e4 LT |
252 | |
253 | int frame; /* for iso: what frame? */ | |
8b262bd2 | 254 | struct list_head fl_list; |
1da177e4 LT |
255 | } __attribute__((aligned(16))); |
256 | ||
257 | /* | |
258 | * We need a special accessor for the control/status word because it is | |
8b262bd2 | 259 | * subject to asynchronous updates by the controller. |
1da177e4 | 260 | */ |
dccf4a48 | 261 | static inline u32 td_status(struct uhci_td *td) { |
1da177e4 LT |
262 | __le32 status = td->status; |
263 | ||
264 | barrier(); | |
265 | return le32_to_cpu(status); | |
266 | } | |
267 | ||
28b9325e AS |
268 | #define LINK_TO_TD(td) (cpu_to_le32((td)->dma_handle)) |
269 | ||
1da177e4 | 270 | |
8b262bd2 AS |
271 | /* |
272 | * Skeleton Queue Headers | |
273 | */ | |
274 | ||
1da177e4 | 275 | /* |
dccf4a48 AS |
276 | * The UHCI driver uses QHs with Interrupt, Control and Bulk URBs for |
277 | * automatic queuing. To make it easy to insert entries into the schedule, | |
17230acd AS |
278 | * we have a skeleton of QHs for each predefined Interrupt latency. |
279 | * Asynchronous QHs (low-speed control, full-speed control, and bulk) | |
280 | * go onto the period-1 interrupt list, since they all get accessed on | |
281 | * every frame. | |
1da177e4 | 282 | * |
17230acd AS |
283 | * When we want to add a new QH, we add it to the list starting from the |
284 | * appropriate skeleton QH. For instance, the schedule can look like this: | |
1da177e4 LT |
285 | * |
286 | * skel int128 QH | |
287 | * dev 1 interrupt QH | |
288 | * dev 5 interrupt QH | |
289 | * skel int64 QH | |
290 | * skel int32 QH | |
291 | * ... | |
17230acd AS |
292 | * skel int1 + async QH |
293 | * dev 5 low-speed control QH | |
1da177e4 LT |
294 | * dev 1 bulk QH |
295 | * dev 2 bulk QH | |
1da177e4 | 296 | * |
17230acd AS |
297 | * There is a special terminating QH used to keep full-speed bandwidth |
298 | * reclamation active when no full-speed control or bulk QHs are linked | |
299 | * into the schedule. It has an inactive TD (to work around a PIIX bug, | |
300 | * see the Intel errata) and it points back to itself. | |
1da177e4 | 301 | * |
17230acd AS |
302 | * There's a special skeleton QH for Isochronous QHs which never appears |
303 | * on the schedule. Isochronous TDs go on the schedule before the | |
dccf4a48 AS |
304 | * the skeleton QHs. The hardware accesses them directly rather than |
305 | * through their QH, which is used only for bookkeeping purposes. | |
306 | * While the UHCI spec doesn't forbid the use of QHs for Isochronous, | |
307 | * it doesn't use them either. And the spec says that queues never | |
308 | * advance on an error completion status, which makes them totally | |
309 | * unsuitable for Isochronous transfers. | |
17230acd AS |
310 | * |
311 | * There's also a special skeleton QH used for QHs which are in the process | |
312 | * of unlinking and so may still be in use by the hardware. It too never | |
313 | * appears on the schedule. | |
1da177e4 LT |
314 | */ |
315 | ||
17230acd AS |
316 | #define UHCI_NUM_SKELQH 11 |
317 | #define SKEL_UNLINK 0 | |
318 | #define skel_unlink_qh skelqh[SKEL_UNLINK] | |
319 | #define SKEL_ISO 1 | |
320 | #define skel_iso_qh skelqh[SKEL_ISO] | |
321 | /* int128, int64, ..., int1 = 2, 3, ..., 9 */ | |
322 | #define SKEL_INDEX(exponent) (9 - exponent) | |
323 | #define SKEL_ASYNC 9 | |
324 | #define skel_async_qh skelqh[SKEL_ASYNC] | |
325 | #define SKEL_TERM 10 | |
326 | #define skel_term_qh skelqh[SKEL_TERM] | |
327 | ||
328 | /* The following entries refer to sublists of skel_async_qh */ | |
329 | #define SKEL_LS_CONTROL 20 | |
330 | #define SKEL_FS_CONTROL 21 | |
331 | #define SKEL_FSBR SKEL_FS_CONTROL | |
332 | #define SKEL_BULK 22 | |
8b262bd2 AS |
333 | |
334 | /* | |
335 | * The UHCI controller and root hub | |
336 | */ | |
337 | ||
1da177e4 | 338 | /* |
8b262bd2 | 339 | * States for the root hub: |
1da177e4 LT |
340 | * |
341 | * To prevent "bouncing" in the presence of electrical noise, | |
c8f4fe43 AS |
342 | * when there are no devices attached we delay for 1 second in the |
343 | * RUNNING_NODEVS state before switching to the AUTO_STOPPED state. | |
344 | * | |
345 | * (Note that the AUTO_STOPPED state won't be necessary once the hub | |
346 | * driver learns to autosuspend.) | |
1da177e4 | 347 | */ |
c8f4fe43 | 348 | enum uhci_rh_state { |
6c1b445c | 349 | /* In the following states the HC must be halted. |
8b262bd2 | 350 | * These two must come first. */ |
6c1b445c | 351 | UHCI_RH_RESET, |
c8f4fe43 | 352 | UHCI_RH_SUSPENDED, |
a8bed8b6 | 353 | |
c8f4fe43 AS |
354 | UHCI_RH_AUTO_STOPPED, |
355 | UHCI_RH_RESUMING, | |
356 | ||
6c1b445c AS |
357 | /* In this state the HC changes from running to halted, |
358 | * so it can legally appear either way. */ | |
c8f4fe43 AS |
359 | UHCI_RH_SUSPENDING, |
360 | ||
6c1b445c | 361 | /* In the following states it's an error if the HC is halted. |
8b262bd2 | 362 | * These two must come last. */ |
c8f4fe43 AS |
363 | UHCI_RH_RUNNING, /* The normal state */ |
364 | UHCI_RH_RUNNING_NODEVS, /* Running with no devices attached */ | |
1da177e4 LT |
365 | }; |
366 | ||
367 | /* | |
8b262bd2 | 368 | * The full UHCI controller information: |
1da177e4 LT |
369 | */ |
370 | struct uhci_hcd { | |
371 | ||
372 | /* debugfs */ | |
373 | struct dentry *dentry; | |
374 | ||
375 | /* Grabbed from PCI */ | |
376 | unsigned long io_addr; | |
377 | ||
378 | struct dma_pool *qh_pool; | |
379 | struct dma_pool *td_pool; | |
380 | ||
1da177e4 | 381 | struct uhci_td *term_td; /* Terminating TD, see UHCI bug */ |
687f5f34 | 382 | struct uhci_qh *skelqh[UHCI_NUM_SKELQH]; /* Skeleton QHs */ |
0ed8fee1 | 383 | struct uhci_qh *next_qh; /* Next QH to scan */ |
1da177e4 LT |
384 | |
385 | spinlock_t lock; | |
a1d59ce8 | 386 | |
dccf4a48 | 387 | dma_addr_t frame_dma_handle; /* Hardware frame list */ |
8b262bd2 | 388 | __le32 *frame; |
dccf4a48 | 389 | void **frame_cpu; /* CPU's frame list */ |
a1d59ce8 | 390 | |
c8f4fe43 AS |
391 | enum uhci_rh_state rh_state; |
392 | unsigned long auto_stop_time; /* When to AUTO_STOP */ | |
393 | ||
1da177e4 LT |
394 | unsigned int frame_number; /* As of last check */ |
395 | unsigned int is_stopped; | |
396 | #define UHCI_IS_STOPPED 9999 /* Larger than a frame # */ | |
c8155cc5 AS |
397 | unsigned int last_iso_frame; /* Frame of last scan */ |
398 | unsigned int cur_iso_frame; /* Frame for current scan */ | |
1da177e4 LT |
399 | |
400 | unsigned int scan_in_progress:1; /* Schedule scan is running */ | |
401 | unsigned int need_rescan:1; /* Redo the schedule scan */ | |
e323de46 | 402 | unsigned int dead:1; /* Controller has died */ |
d8f12ab5 AS |
403 | unsigned int RD_enable:1; /* Suspended root hub with |
404 | Resume-Detect interrupts | |
405 | enabled */ | |
8d402e1a | 406 | unsigned int is_initialized:1; /* Data structure is usable */ |
84afddd7 | 407 | unsigned int fsbr_is_on:1; /* FSBR is turned on */ |
c5e3b741 AS |
408 | unsigned int fsbr_is_wanted:1; /* Does any URB want FSBR? */ |
409 | unsigned int fsbr_expiring:1; /* FSBR is timing out */ | |
410 | ||
411 | struct timer_list fsbr_timer; /* For turning off FBSR */ | |
1da177e4 LT |
412 | |
413 | /* Support for port suspend/resume/reset */ | |
414 | unsigned long port_c_suspend; /* Bit-arrays of ports */ | |
1da177e4 LT |
415 | unsigned long resuming_ports; |
416 | unsigned long ports_timeout; /* Time to stop signalling */ | |
417 | ||
dccf4a48 AS |
418 | struct list_head idle_qh_list; /* Where the idle QHs live */ |
419 | ||
1f09df8b | 420 | int rh_numports; /* Number of root-hub ports */ |
1da177e4 LT |
421 | |
422 | wait_queue_head_t waitqh; /* endpoint_disable waiters */ | |
dccf4a48 | 423 | int num_waiting; /* Number of waiters */ |
3ca2a321 AS |
424 | |
425 | int total_load; /* Sum of array values */ | |
426 | short load[MAX_PHASE]; /* Periodic allocations */ | |
1da177e4 LT |
427 | }; |
428 | ||
429 | /* Convert between a usb_hcd pointer and the corresponding uhci_hcd */ | |
430 | static inline struct uhci_hcd *hcd_to_uhci(struct usb_hcd *hcd) | |
431 | { | |
432 | return (struct uhci_hcd *) (hcd->hcd_priv); | |
433 | } | |
434 | static inline struct usb_hcd *uhci_to_hcd(struct uhci_hcd *uhci) | |
435 | { | |
436 | return container_of((void *) uhci, struct usb_hcd, hcd_priv); | |
437 | } | |
438 | ||
439 | #define uhci_dev(u) (uhci_to_hcd(u)->self.controller) | |
440 | ||
c4334726 AS |
441 | /* Utility macro for comparing frame numbers */ |
442 | #define uhci_frame_before_eq(f1, f2) (0 <= (int) ((f2) - (f1))) | |
443 | ||
8b262bd2 AS |
444 | |
445 | /* | |
446 | * Private per-URB data | |
447 | */ | |
1da177e4 | 448 | struct urb_priv { |
dccf4a48 | 449 | struct list_head node; /* Node in the QH's urbp list */ |
1da177e4 LT |
450 | |
451 | struct urb *urb; | |
452 | ||
453 | struct uhci_qh *qh; /* QH for this URB */ | |
8b262bd2 | 454 | struct list_head td_list; |
1da177e4 | 455 | |
84afddd7 | 456 | unsigned fsbr:1; /* URB wants FSBR */ |
1da177e4 LT |
457 | }; |
458 | ||
8b262bd2 | 459 | |
c8f4fe43 AS |
460 | /* Some special IDs */ |
461 | ||
462 | #define PCI_VENDOR_ID_GENESYS 0x17a0 | |
463 | #define PCI_DEVICE_ID_GL880S_UHCI 0x8083 | |
c8f4fe43 | 464 | |
1da177e4 | 465 | #endif |