[mirror_ubuntu-focal-kernel.git] / drivers / usb / host / uhci-hub.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Universal Host Controller Interface driver for USB.
 *
 * Maintainer: Alan Stern <stern@rowland.harvard.edu>
 *
 * (C) Copyright 1999 Linus Torvalds
 * (C) Copyright 1999-2002 Johannes Erdfelt, johannes@erdfelt.com
 * (C) Copyright 1999 Randy Dunlap
 * (C) Copyright 1999 Georg Acher, acher@in.tum.de
 * (C) Copyright 1999 Deti Fliegl, deti@fliegl.de
 * (C) Copyright 1999 Thomas Sailer, sailer@ife.ee.ethz.ch
 * (C) Copyright 2004 Alan Stern, stern@rowland.harvard.edu
 */

static const __u8 root_hub_hub_des[] =
{
	0x09,			/*  __u8  bLength; */
	USB_DT_HUB,		/*  __u8  bDescriptorType; Hub-descriptor */
	0x02,			/*  __u8  bNbrPorts; */
	HUB_CHAR_NO_LPSM |	/* __u16  wHubCharacteristics; */
		HUB_CHAR_INDV_PORT_OCPM, /* (per-port OC, no power switching) */
	0x00,
	0x01,			/*  __u8  bPwrOn2pwrGood; 2ms */
	0x00,			/*  __u8  bHubContrCurrent; 0 mA */
	0x00,			/*  __u8  DeviceRemovable; *** 7 Ports max */
	0xff			/*  __u8  PortPwrCtrlMask; *** 7 ports max */
};

#define	UHCI_RH_MAXCHILD	7

/* must write as zeroes */
#define WZ_BITS		(USBPORTSC_RES2 | USBPORTSC_RES3 | USBPORTSC_RES4)

/* status change bits:  nonzero writes will clear */
#define RWC_BITS	(USBPORTSC_OCC | USBPORTSC_PEC | USBPORTSC_CSC)

/* suspend/resume bits: port suspended or port resuming */
#define SUSPEND_BITS	(USBPORTSC_SUSP | USBPORTSC_RD)

/* A port that either is connected or has a changed-bit set will prevent
 * us from AUTO_STOPPING.
 */
static int any_ports_active(struct uhci_hcd *uhci)
{
	int port;

	for (port = 0; port < uhci->rh_numports; ++port) {
		if ((uhci_readw(uhci, USBPORTSC1 + port * 2) &
				(USBPORTSC_CCS | RWC_BITS)) ||
				test_bit(port, &uhci->port_c_suspend))
			return 1;
	}
	return 0;
}

static inline int get_hub_status_data(struct uhci_hcd *uhci, char *buf)
{
	int port;
	int mask = RWC_BITS;

	/* Some boards (both VIA and Intel apparently) report bogus
	 * overcurrent indications, causing massive log spam unless
	 * we completely ignore them.  This doesn't seem to be a problem
	 * with the chipset so much as with the way it is connected on
	 * the motherboard; if the overcurrent input is left to float
	 * then it may constantly register false positives. */
	if (ignore_oc)
		mask &= ~USBPORTSC_OCC;

	*buf = 0;
	for (port = 0; port < uhci->rh_numports; ++port) {
		if ((uhci_readw(uhci, USBPORTSC1 + port * 2) & mask) ||
				test_bit(port, &uhci->port_c_suspend))
			*buf |= (1 << (port + 1));
	}
	return !!*buf;
}

#define CLR_RH_PORTSTAT(x) \
	status = uhci_readw(uhci, port_addr);	\
	status &= ~(RWC_BITS|WZ_BITS); \
	status &= ~(x); \
	status |= RWC_BITS & (x); \
	uhci_writew(uhci, status, port_addr)

#define SET_RH_PORTSTAT(x) \
	status = uhci_readw(uhci, port_addr);	\
	status |= (x); \
	status &= ~(RWC_BITS|WZ_BITS); \
	uhci_writew(uhci, status, port_addr)

/* UHCI controllers don't automatically stop resume signalling after 20 msec,
 * so we have to poll and check timeouts in order to take care of it.
 */
static void uhci_finish_suspend(struct uhci_hcd *uhci, int port,
		unsigned long port_addr)
{
	int status;
	int i;

	if (uhci_readw(uhci, port_addr) & SUSPEND_BITS) {
		CLR_RH_PORTSTAT(SUSPEND_BITS);
		if (test_bit(port, &uhci->resuming_ports))
			set_bit(port, &uhci->port_c_suspend);

		/* The controller won't actually turn off the RD bit until
		 * it has had a chance to send a low-speed EOP sequence,
		 * which is supposed to take 3 bit times (= 2 microseconds).
		 * Experiments show that some controllers take longer, so
		 * we'll poll for completion. */
		for (i = 0; i < 10; ++i) {
			if (!(uhci_readw(uhci, port_addr) & SUSPEND_BITS))
				break;
			udelay(1);
		}
	}
	clear_bit(port, &uhci->resuming_ports);
	usb_hcd_end_port_resume(&uhci_to_hcd(uhci)->self, port);
}

/* Wait for the UHCI controller in HP's iLO2 server management chip.
 * It can take up to 250 us to finish a reset and set the CSC bit.
 */
static void wait_for_HP(struct uhci_hcd *uhci, unsigned long port_addr)
{
	int i;

	for (i = 10; i < 250; i += 10) {
		if (uhci_readw(uhci, port_addr) & USBPORTSC_CSC)
			return;
		udelay(10);
	}
	/* Log a warning? */
}

static void uhci_check_ports(struct uhci_hcd *uhci)
{
	unsigned int port;
	unsigned long port_addr;
	int status;

	for (port = 0; port < uhci->rh_numports; ++port) {
		port_addr = USBPORTSC1 + 2 * port;
		status = uhci_readw(uhci, port_addr);
		if (unlikely(status & USBPORTSC_PR)) {
			if (time_after_eq(jiffies, uhci->ports_timeout)) {
				CLR_RH_PORTSTAT(USBPORTSC_PR);
				udelay(10);

				/* HP's server management chip requires
				 * a longer delay. */
				if (uhci->wait_for_hp)
					wait_for_HP(uhci, port_addr);

				/* If the port was enabled before, turning
				 * reset on caused a port enable change.
				 * Turning reset off causes a port connect
				 * status change.  Clear these changes. */
				CLR_RH_PORTSTAT(USBPORTSC_CSC | USBPORTSC_PEC);
				SET_RH_PORTSTAT(USBPORTSC_PE);
			}
		}
		if (unlikely(status & USBPORTSC_RD)) {
			if (!test_bit(port, &uhci->resuming_ports)) {

				/* Port received a wakeup request */
				set_bit(port, &uhci->resuming_ports);
				uhci->ports_timeout = jiffies +
					msecs_to_jiffies(USB_RESUME_TIMEOUT);
				usb_hcd_start_port_resume(
						&uhci_to_hcd(uhci)->self, port);

				/* Make sure we see the port again
				 * after the resuming period is over. */
				mod_timer(&uhci_to_hcd(uhci)->rh_timer,
						uhci->ports_timeout);
			} else if (time_after_eq(jiffies,
						uhci->ports_timeout)) {
				uhci_finish_suspend(uhci, port, port_addr);
			}
		}
	}
}

static int uhci_hub_status_data(struct usb_hcd *hcd, char *buf)
{
	struct uhci_hcd *uhci = hcd_to_uhci(hcd);
	unsigned long flags;
	int status = 0;

	spin_lock_irqsave(&uhci->lock, flags);

	uhci_scan_schedule(uhci);
	if (!HCD_HW_ACCESSIBLE(hcd) || uhci->dead)
		goto done;
	uhci_check_ports(uhci);

	status = get_hub_status_data(uhci, buf);

	switch (uhci->rh_state) {
	    case UHCI_RH_SUSPENDED:
		/* if port change, ask to be resumed */
		if (status || uhci->resuming_ports) {
			status = 1;
			usb_hcd_resume_root_hub(hcd);
		}
		break;

	    case UHCI_RH_AUTO_STOPPED:
		/* if port change, auto start */
		if (status)
			wakeup_rh(uhci);
		break;

	    case UHCI_RH_RUNNING:
		/* are any devices attached? */
		if (!any_ports_active(uhci)) {
			uhci->rh_state = UHCI_RH_RUNNING_NODEVS;
			uhci->auto_stop_time = jiffies + HZ;
		}
		break;

	    case UHCI_RH_RUNNING_NODEVS:
		/* auto-stop if nothing connected for 1 second */
		if (any_ports_active(uhci))
			uhci->rh_state = UHCI_RH_RUNNING;
		else if (time_after_eq(jiffies, uhci->auto_stop_time) &&
				!uhci->wait_for_hp)
			suspend_rh(uhci, UHCI_RH_AUTO_STOPPED);
		break;

	    default:
		break;
	}

done:
	spin_unlock_irqrestore(&uhci->lock, flags);
	return status;
}

/* size of returned buffer is part of USB spec */
static int uhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
			u16 wIndex, char *buf, u16 wLength)
{
	struct uhci_hcd *uhci = hcd_to_uhci(hcd);
	int status, lstatus, retval = 0;
	unsigned int port = wIndex - 1;
	unsigned long port_addr = USBPORTSC1 + 2 * port;
	u16 wPortChange, wPortStatus;
	unsigned long flags;

	if (!HCD_HW_ACCESSIBLE(hcd) || uhci->dead)
		return -ETIMEDOUT;

	spin_lock_irqsave(&uhci->lock, flags);
	switch (typeReq) {

	case GetHubStatus:
		*(__le32 *)buf = cpu_to_le32(0);
		retval = 4; /* hub power */
		break;
	case GetPortStatus:
		if (port >= uhci->rh_numports)
			goto err;

		uhci_check_ports(uhci);
		status = uhci_readw(uhci, port_addr);

		/* Intel controllers report the OverCurrent bit active on.
		 * VIA controllers report it active off, so we'll adjust the
		 * bit value.  (It's not standardized in the UHCI spec.)
		 */
		if (uhci->oc_low)
			status ^= USBPORTSC_OC;

		/* UHCI doesn't support C_RESET (always false) */
		wPortChange = lstatus = 0;
		if (status & USBPORTSC_CSC)
			wPortChange |= USB_PORT_STAT_C_CONNECTION;
		if (status & USBPORTSC_PEC)
			wPortChange |= USB_PORT_STAT_C_ENABLE;
		if ((status & USBPORTSC_OCC) && !ignore_oc)
			wPortChange |= USB_PORT_STAT_C_OVERCURRENT;

		if (test_bit(port, &uhci->port_c_suspend)) {
			wPortChange |= USB_PORT_STAT_C_SUSPEND;
			lstatus |= 1;
		}
		if (test_bit(port, &uhci->resuming_ports))
			lstatus |= 4;

		/* UHCI has no power switching (always on) */
		wPortStatus = USB_PORT_STAT_POWER;
		if (status & USBPORTSC_CCS)
			wPortStatus |= USB_PORT_STAT_CONNECTION;
		if (status & USBPORTSC_PE) {
			wPortStatus |= USB_PORT_STAT_ENABLE;
			if (status & SUSPEND_BITS)
				wPortStatus |= USB_PORT_STAT_SUSPEND;
		}
		if (status & USBPORTSC_OC)
			wPortStatus |= USB_PORT_STAT_OVERCURRENT;
		if (status & USBPORTSC_PR)
			wPortStatus |= USB_PORT_STAT_RESET;
		if (status & USBPORTSC_LSDA)
			wPortStatus |= USB_PORT_STAT_LOW_SPEED;

		if (wPortChange)
			dev_dbg(uhci_dev(uhci), "port %d portsc %04x,%02x\n",
					wIndex, status, lstatus);

		*(__le16 *)buf = cpu_to_le16(wPortStatus);
		*(__le16 *)(buf + 2) = cpu_to_le16(wPortChange);
		retval = 4;
		break;
	case SetHubFeature:		/* We don't implement these */
	case ClearHubFeature:
		switch (wValue) {
		case C_HUB_OVER_CURRENT:
		case C_HUB_LOCAL_POWER:
			break;
		default:
			goto err;
		}
		break;
	case SetPortFeature:
		if (port >= uhci->rh_numports)
			goto err;

		switch (wValue) {
		case USB_PORT_FEAT_SUSPEND:
			SET_RH_PORTSTAT(USBPORTSC_SUSP);
			break;
		case USB_PORT_FEAT_RESET:
			SET_RH_PORTSTAT(USBPORTSC_PR);

			/* Reset terminates Resume signalling */
			uhci_finish_suspend(uhci, port, port_addr);

			/* USB v2.0 7.1.7.5 */
			uhci->ports_timeout = jiffies +
				msecs_to_jiffies(USB_RESUME_TIMEOUT);
			break;
		case USB_PORT_FEAT_POWER:
			/* UHCI has no power switching */
			break;
		default:
			goto err;
		}
		break;
	case ClearPortFeature:
		if (port >= uhci->rh_numports)
			goto err;

		switch (wValue) {
		case USB_PORT_FEAT_ENABLE:
			CLR_RH_PORTSTAT(USBPORTSC_PE);

			/* Disable terminates Resume signalling */
			uhci_finish_suspend(uhci, port, port_addr);
			break;
		case USB_PORT_FEAT_C_ENABLE:
			CLR_RH_PORTSTAT(USBPORTSC_PEC);
			break;
		case USB_PORT_FEAT_SUSPEND:
			if (!(uhci_readw(uhci, port_addr) & USBPORTSC_SUSP)) {

				/* Make certain the port isn't suspended */
				uhci_finish_suspend(uhci, port, port_addr);
			} else if (!test_and_set_bit(port,
						&uhci->resuming_ports)) {
				SET_RH_PORTSTAT(USBPORTSC_RD);

				/* The controller won't allow RD to be set
				 * if the port is disabled.  When this happens
				 * just skip the Resume signalling.
				 */
				if (!(uhci_readw(uhci, port_addr) &
						USBPORTSC_RD))
					uhci_finish_suspend(uhci, port,
							port_addr);
				else
					/* USB v2.0 7.1.7.7 */
					uhci->ports_timeout = jiffies +
						msecs_to_jiffies(20);
			}
			break;
		case USB_PORT_FEAT_C_SUSPEND:
			clear_bit(port, &uhci->port_c_suspend);
			break;
		case USB_PORT_FEAT_POWER:
			/* UHCI has no power switching */
			goto err;
		case USB_PORT_FEAT_C_CONNECTION:
			CLR_RH_PORTSTAT(USBPORTSC_CSC);
			break;
		case USB_PORT_FEAT_C_OVER_CURRENT:
			CLR_RH_PORTSTAT(USBPORTSC_OCC);
			break;
		case USB_PORT_FEAT_C_RESET:
			/* this driver won't report these */
			break;
		default:
			goto err;
		}
		break;
	case GetHubDescriptor:
		retval = min_t(unsigned int, sizeof(root_hub_hub_des), wLength);
		memcpy(buf, root_hub_hub_des, retval);
		if (retval > 2)
			buf[2] = uhci->rh_numports;
		break;
	default:
err:
		retval = -EPIPE;
	}
	spin_unlock_irqrestore(&uhci->lock, flags);

	return retval;
}
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
1da177e4 LT	2	/*
	3	* Universal Host Controller Interface driver for USB.
	4	*
	5	* Maintainer: Alan Stern <stern@rowland.harvard.edu>
	6	*
	7	* (C) Copyright 1999 Linus Torvalds
	8	* (C) Copyright 1999-2002 Johannes Erdfelt, johannes@erdfelt.com
	9	* (C) Copyright 1999 Randy Dunlap
	10	* (C) Copyright 1999 Georg Acher, acher@in.tum.de
	11	* (C) Copyright 1999 Deti Fliegl, deti@fliegl.de
	12	* (C) Copyright 1999 Thomas Sailer, sailer@ife.ee.ethz.ch
	13	* (C) Copyright 2004 Alan Stern, stern@rowland.harvard.edu
	14	*/
	15
bef4665a	16	static const __u8 root_hub_hub_des[] =
1da177e4 LT	17	{
1da177e4 LT	18	0x09, /* __u8 bLength; */
3e5dd4c3	19	USB_DT_HUB, /* __u8 bDescriptorType; Hub-descriptor */
1da177e4	20	0x02, /* __u8 bNbrPorts; */
673016d9 SS	21	HUB_CHAR_NO_LPSM \| /* __u16 wHubCharacteristics; */
	22	HUB_CHAR_INDV_PORT_OCPM, /* (per-port OC, no power switching) */
	23	0x00,
1da177e4 LT	24	0x01, /* __u8 bPwrOn2pwrGood; 2ms */
1da177e4 LT	25	0x00, /* __u8 bHubContrCurrent; 0 mA */
3171fcab CG	26	0x00, /* __u8 DeviceRemovable; *** 7 Ports max */
3171fcab CG	27	0xff /* __u8 PortPwrCtrlMask; *** 7 ports max */
1da177e4 LT	28	};
	29
	30	#define UHCI_RH_MAXCHILD 7
	31
	32	/* must write as zeroes */
	33	#define WZ_BITS (USBPORTSC_RES2 \| USBPORTSC_RES3 \| USBPORTSC_RES4)
	34
	35	/* status change bits: nonzero writes will clear */
	36	#define RWC_BITS (USBPORTSC_OCC \| USBPORTSC_PEC \| USBPORTSC_CSC)
	37
88018158 AS	38	/* suspend/resume bits: port suspended or port resuming */
	39	#define SUSPEND_BITS (USBPORTSC_SUSP \| USBPORTSC_RD)
	40
f5946f82 AS	41	/* A port that either is connected or has a changed-bit set will prevent
	42	* us from AUTO_STOPPING.
	43	*/
	44	static int any_ports_active(struct uhci_hcd *uhci)
	45	{
	46	int port;
	47
	48	for (port = 0; port < uhci->rh_numports; ++port) {
9faa091a	49	if ((uhci_readw(uhci, USBPORTSC1 + port * 2) &
f5946f82 AS	50	(USBPORTSC_CCS \| RWC_BITS)) \|\|
	51	test_bit(port, &uhci->port_c_suspend))
	52	return 1;
	53	}
	54	return 0;
	55	}
	56
6c1b445c	57	static inline int get_hub_status_data(struct uhci_hcd uhci, char buf)
1da177e4	58	{
1da177e4	59	int port;
5f8364b7 AS	60	int mask = RWC_BITS;
	61
	62	/* Some boards (both VIA and Intel apparently) report bogus
	63	* overcurrent indications, causing massive log spam unless
	64	* we completely ignore them. This doesn't seem to be a problem
	65	* with the chipset so much as with the way it is connected on
	66	* the motherboard; if the overcurrent input is left to float
	67	* then it may constantly register false positives. */
	68	if (ignore_oc)
	69	mask &= ~USBPORTSC_OCC;
1da177e4 LT	70
	71	*buf = 0;
	72	for (port = 0; port < uhci->rh_numports; ++port) {
9faa091a	73	if ((uhci_readw(uhci, USBPORTSC1 + port * 2) & mask) \|\|
1da177e4 LT	74	test_bit(port, &uhci->port_c_suspend))
	75	*buf \|= (1 << (port + 1));
	76	}
1da177e4 LT	77	return !!*buf;
	78	}
	79
1da177e4	80	#define CLR_RH_PORTSTAT(x) \
9faa091a	81	status = uhci_readw(uhci, port_addr); \
1da177e4 LT	82	status &= ~(RWC_BITS\|WZ_BITS); \
	83	status &= ~(x); \
	84	status \|= RWC_BITS & (x); \
9faa091a	85	uhci_writew(uhci, status, port_addr)
1da177e4 LT	86
1da177e4 LT	87	#define SET_RH_PORTSTAT(x) \
9faa091a	88	status = uhci_readw(uhci, port_addr); \
1da177e4 LT	89	status \|= (x); \
1da177e4 LT	90	status &= ~(RWC_BITS\|WZ_BITS); \
9faa091a	91	uhci_writew(uhci, status, port_addr)
1da177e4 LT	92
	93	/* UHCI controllers don't automatically stop resume signalling after 20 msec,
	94	* so we have to poll and check timeouts in order to take care of it.
	95	*/
	96	static void uhci_finish_suspend(struct uhci_hcd *uhci, int port,
	97	unsigned long port_addr)
	98	{
	99	int status;
de06a3b8	100	int i;
1da177e4	101
9faa091a	102	if (uhci_readw(uhci, port_addr) & SUSPEND_BITS) {
88018158	103	CLR_RH_PORTSTAT(SUSPEND_BITS);
8e326406 AS	104	if (test_bit(port, &uhci->resuming_ports))
8e326406 AS	105	set_bit(port, &uhci->port_c_suspend);
1da177e4 LT	106
	107	/* The controller won't actually turn off the RD bit until
	108	* it has had a chance to send a low-speed EOP sequence,
de06a3b8 AS	109	* which is supposed to take 3 bit times (= 2 microseconds).
	110	* Experiments show that some controllers take longer, so
	111	* we'll poll for completion. */
	112	for (i = 0; i < 10; ++i) {
9faa091a	113	if (!(uhci_readw(uhci, port_addr) & SUSPEND_BITS))
de06a3b8 AS	114	break;
	115	udelay(1);
	116	}
1da177e4	117	}
8e326406	118	clear_bit(port, &uhci->resuming_ports);
840008bb	119	usb_hcd_end_port_resume(&uhci_to_hcd(uhci)->self, port);
1da177e4 LT	120	}
1da177e4 LT	121
ae557175 AS	122	/* Wait for the UHCI controller in HP's iLO2 server management chip.
	123	* It can take up to 250 us to finish a reset and set the CSC bit.
	124	*/
9faa091a	125	static void wait_for_HP(struct uhci_hcd *uhci, unsigned long port_addr)
ae557175 AS	126	{
	127	int i;
	128
	129	for (i = 10; i < 250; i += 10) {
9faa091a	130	if (uhci_readw(uhci, port_addr) & USBPORTSC_CSC)
ae557175 AS	131	return;
	132	udelay(10);
	133	}
	134	/* Log a warning? */
	135	}
	136
1da177e4 LT	137	static void uhci_check_ports(struct uhci_hcd *uhci)
	138	{
	139	unsigned int port;
	140	unsigned long port_addr;
	141	int status;
	142
	143	for (port = 0; port < uhci->rh_numports; ++port) {
9faa091a JA	144	port_addr = USBPORTSC1 + 2 * port;
9faa091a JA	145	status = uhci_readw(uhci, port_addr);
1da177e4 LT	146	if (unlikely(status & USBPORTSC_PR)) {
	147	if (time_after_eq(jiffies, uhci->ports_timeout)) {
	148	CLR_RH_PORTSTAT(USBPORTSC_PR);
	149	udelay(10);
	150
ae557175 AS	151	/* HP's server management chip requires
ae557175 AS	152	* a longer delay. */
dfeca7a8	153	if (uhci->wait_for_hp)
9faa091a	154	wait_for_HP(uhci, port_addr);
ae557175	155
1da177e4 LT	156	/* If the port was enabled before, turning
	157	* reset on caused a port enable change.
	158	* Turning reset off causes a port connect
	159	* status change. Clear these changes. */
	160	CLR_RH_PORTSTAT(USBPORTSC_CSC \| USBPORTSC_PEC);
	161	SET_RH_PORTSTAT(USBPORTSC_PE);
	162	}
	163	}
	164	if (unlikely(status & USBPORTSC_RD)) {
	165	if (!test_bit(port, &uhci->resuming_ports)) {
	166
	167	/* Port received a wakeup request */
	168	set_bit(port, &uhci->resuming_ports);
	169	uhci->ports_timeout = jiffies +
b8fb6f79	170	msecs_to_jiffies(USB_RESUME_TIMEOUT);
840008bb AS	171	usb_hcd_start_port_resume(
840008bb AS	172	&uhci_to_hcd(uhci)->self, port);
6c1b445c AS	173
	174	/* Make sure we see the port again
	175	* after the resuming period is over. */
	176	mod_timer(&uhci_to_hcd(uhci)->rh_timer,
	177	uhci->ports_timeout);
1da177e4 LT	178	} else if (time_after_eq(jiffies,
	179	uhci->ports_timeout)) {
	180	uhci_finish_suspend(uhci, port, port_addr);
	181	}
	182	}
	183	}
	184	}
	185
6c1b445c AS	186	static int uhci_hub_status_data(struct usb_hcd hcd, char buf)
	187	{
	188	struct uhci_hcd *uhci = hcd_to_uhci(hcd);
	189	unsigned long flags;
1f09df8b	190	int status = 0;
6c1b445c AS	191
6c1b445c AS	192	spin_lock_irqsave(&uhci->lock, flags);
6c1b445c	193
7d12e780	194	uhci_scan_schedule(uhci);
541c7d43	195	if (!HCD_HW_ACCESSIBLE(hcd) \|\| uhci->dead)
1f09df8b	196	goto done;
6c1b445c	197	uhci_check_ports(uhci);
1f09df8b	198
6c1b445c AS	199	status = get_hub_status_data(uhci, buf);
	200
	201	switch (uhci->rh_state) {
6c1b445c AS	202	case UHCI_RH_SUSPENDED:
6c1b445c AS	203	/* if port change, ask to be resumed */
b446b96f AS	204	if (status \|\| uhci->resuming_ports) {
b446b96f AS	205	status = 1;
6c1b445c	206	usb_hcd_resume_root_hub(hcd);
b446b96f	207	}
6c1b445c AS	208	break;
	209
	210	case UHCI_RH_AUTO_STOPPED:
	211	/* if port change, auto start */
	212	if (status)
	213	wakeup_rh(uhci);
	214	break;
	215
	216	case UHCI_RH_RUNNING:
	217	/* are any devices attached? */
	218	if (!any_ports_active(uhci)) {
	219	uhci->rh_state = UHCI_RH_RUNNING_NODEVS;
	220	uhci->auto_stop_time = jiffies + HZ;
	221	}
	222	break;
	223
	224	case UHCI_RH_RUNNING_NODEVS:
	225	/* auto-stop if nothing connected for 1 second */
	226	if (any_ports_active(uhci))
	227	uhci->rh_state = UHCI_RH_RUNNING;
997ff893 AS	228	else if (time_after_eq(jiffies, uhci->auto_stop_time) &&
997ff893 AS	229	!uhci->wait_for_hp)
6c1b445c AS	230	suspend_rh(uhci, UHCI_RH_AUTO_STOPPED);
	231	break;
	232
	233	default:
	234	break;
	235	}
	236
	237	done:
	238	spin_unlock_irqrestore(&uhci->lock, flags);
	239	return status;
	240	}
	241
1da177e4 LT	242	/* size of returned buffer is part of USB spec */
	243	static int uhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
	244	u16 wIndex, char *buf, u16 wLength)
	245	{
	246	struct uhci_hcd *uhci = hcd_to_uhci(hcd);
5a3e2055	247	int status, lstatus, retval = 0;
1da177e4	248	unsigned int port = wIndex - 1;
9faa091a	249	unsigned long port_addr = USBPORTSC1 + 2 * port;
1da177e4 LT	250	u16 wPortChange, wPortStatus;
	251	unsigned long flags;
	252
541c7d43	253	if (!HCD_HW_ACCESSIBLE(hcd) \|\| uhci->dead)
a8bed8b6 AS	254	return -ETIMEDOUT;
a8bed8b6 AS	255
1da177e4 LT	256	spin_lock_irqsave(&uhci->lock, flags);
	257	switch (typeReq) {
	258
	259	case GetHubStatus:
	260	(__le32 )buf = cpu_to_le32(0);
5a3e2055 DZ	261	retval = 4; /* hub power */
5a3e2055 DZ	262	break;
1da177e4 LT	263	case GetPortStatus:
	264	if (port >= uhci->rh_numports)
	265	goto err;
	266
	267	uhci_check_ports(uhci);
9faa091a	268	status = uhci_readw(uhci, port_addr);
1da177e4 LT	269
	270	/* Intel controllers report the OverCurrent bit active on.
	271	* VIA controllers report it active off, so we'll adjust the
	272	* bit value. (It's not standardized in the UHCI spec.)
	273	*/
dfeca7a8	274	if (uhci->oc_low)
1da177e4 LT	275	status ^= USBPORTSC_OC;
	276
	277	/* UHCI doesn't support C_RESET (always false) */
	278	wPortChange = lstatus = 0;
	279	if (status & USBPORTSC_CSC)
	280	wPortChange \|= USB_PORT_STAT_C_CONNECTION;
	281	if (status & USBPORTSC_PEC)
	282	wPortChange \|= USB_PORT_STAT_C_ENABLE;
5f8364b7	283	if ((status & USBPORTSC_OCC) && !ignore_oc)
1da177e4 LT	284	wPortChange \|= USB_PORT_STAT_C_OVERCURRENT;
	285
	286	if (test_bit(port, &uhci->port_c_suspend)) {
	287	wPortChange \|= USB_PORT_STAT_C_SUSPEND;
	288	lstatus \|= 1;
	289	}
1da177e4 LT	290	if (test_bit(port, &uhci->resuming_ports))
	291	lstatus \|= 4;
	292
	293	/* UHCI has no power switching (always on) */
	294	wPortStatus = USB_PORT_STAT_POWER;
	295	if (status & USBPORTSC_CCS)
	296	wPortStatus \|= USB_PORT_STAT_CONNECTION;
	297	if (status & USBPORTSC_PE) {
	298	wPortStatus \|= USB_PORT_STAT_ENABLE;
88018158	299	if (status & SUSPEND_BITS)
1da177e4 LT	300	wPortStatus \|= USB_PORT_STAT_SUSPEND;
	301	}
	302	if (status & USBPORTSC_OC)
	303	wPortStatus \|= USB_PORT_STAT_OVERCURRENT;
	304	if (status & USBPORTSC_PR)
	305	wPortStatus \|= USB_PORT_STAT_RESET;
	306	if (status & USBPORTSC_LSDA)
	307	wPortStatus \|= USB_PORT_STAT_LOW_SPEED;
	308
	309	if (wPortChange)
	310	dev_dbg(uhci_dev(uhci), "port %d portsc %04x,%02x\n",
	311	wIndex, status, lstatus);
	312
	313	(__le16 )buf = cpu_to_le16(wPortStatus);
	314	(__le16 )(buf + 2) = cpu_to_le16(wPortChange);
5a3e2055 DZ	315	retval = 4;
5a3e2055 DZ	316	break;
1da177e4 LT	317	case SetHubFeature: /* We don't implement these */
	318	case ClearHubFeature:
	319	switch (wValue) {
	320	case C_HUB_OVER_CURRENT:
	321	case C_HUB_LOCAL_POWER:
5a3e2055	322	break;
1da177e4 LT	323	default:
	324	goto err;
	325	}
	326	break;
	327	case SetPortFeature:
	328	if (port >= uhci->rh_numports)
	329	goto err;
	330
	331	switch (wValue) {
	332	case USB_PORT_FEAT_SUSPEND:
1da177e4	333	SET_RH_PORTSTAT(USBPORTSC_SUSP);
5a3e2055	334	break;
1da177e4 LT	335	case USB_PORT_FEAT_RESET:
	336	SET_RH_PORTSTAT(USBPORTSC_PR);
	337
	338	/* Reset terminates Resume signalling */
	339	uhci_finish_suspend(uhci, port, port_addr);
	340
	341	/* USB v2.0 7.1.7.5 */
b8fb6f79 FB	342	uhci->ports_timeout = jiffies +
b8fb6f79 FB	343	msecs_to_jiffies(USB_RESUME_TIMEOUT);
5a3e2055	344	break;
1da177e4 LT	345	case USB_PORT_FEAT_POWER:
1da177e4 LT	346	/* UHCI has no power switching */
5a3e2055	347	break;
1da177e4 LT	348	default:
	349	goto err;
	350	}
	351	break;
	352	case ClearPortFeature:
	353	if (port >= uhci->rh_numports)
	354	goto err;
	355
	356	switch (wValue) {
	357	case USB_PORT_FEAT_ENABLE:
	358	CLR_RH_PORTSTAT(USBPORTSC_PE);
	359
	360	/* Disable terminates Resume signalling */
	361	uhci_finish_suspend(uhci, port, port_addr);
5a3e2055	362	break;
1da177e4 LT	363	case USB_PORT_FEAT_C_ENABLE:
1da177e4 LT	364	CLR_RH_PORTSTAT(USBPORTSC_PEC);
5a3e2055	365	break;
1da177e4	366	case USB_PORT_FEAT_SUSPEND:
9faa091a	367	if (!(uhci_readw(uhci, port_addr) & USBPORTSC_SUSP)) {
8e326406 AS	368
	369	/* Make certain the port isn't suspended */
	370	uhci_finish_suspend(uhci, port, port_addr);
	371	} else if (!test_and_set_bit(port,
1da177e4 LT	372	&uhci->resuming_ports)) {
	373	SET_RH_PORTSTAT(USBPORTSC_RD);
	374
	375	/* The controller won't allow RD to be set
	376	* if the port is disabled. When this happens
	377	* just skip the Resume signalling.
	378	*/
9faa091a JA	379	if (!(uhci_readw(uhci, port_addr) &
9faa091a JA	380	USBPORTSC_RD))
1da177e4 LT	381	uhci_finish_suspend(uhci, port,
	382	port_addr);
	383	else
	384	/* USB v2.0 7.1.7.7 */
	385	uhci->ports_timeout = jiffies +
	386	msecs_to_jiffies(20);
	387	}
5a3e2055	388	break;
1da177e4 LT	389	case USB_PORT_FEAT_C_SUSPEND:
1da177e4 LT	390	clear_bit(port, &uhci->port_c_suspend);
5a3e2055	391	break;
1da177e4 LT	392	case USB_PORT_FEAT_POWER:
	393	/* UHCI has no power switching */
	394	goto err;
	395	case USB_PORT_FEAT_C_CONNECTION:
	396	CLR_RH_PORTSTAT(USBPORTSC_CSC);
5a3e2055	397	break;
1da177e4 LT	398	case USB_PORT_FEAT_C_OVER_CURRENT:
1da177e4 LT	399	CLR_RH_PORTSTAT(USBPORTSC_OCC);
5a3e2055	400	break;
1da177e4 LT	401	case USB_PORT_FEAT_C_RESET:
1da177e4 LT	402	/* this driver won't report these */
5a3e2055	403	break;
1da177e4 LT	404	default:
	405	goto err;
	406	}
	407	break;
	408	case GetHubDescriptor:
5a3e2055 DZ	409	retval = min_t(unsigned int, sizeof(root_hub_hub_des), wLength);
	410	memcpy(buf, root_hub_hub_des, retval);
	411	if (retval > 2)
1da177e4	412	buf[2] = uhci->rh_numports;
5a3e2055	413	break;
1da177e4 LT	414	default:
	415	err:
	416	retval = -EPIPE;
	417	}
	418	spin_unlock_irqrestore(&uhci->lock, flags);
	419
	420	return retval;
	421	}