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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Universal Host Controller Interface driver for USB. | |
3 | * | |
4 | * Maintainer: Alan Stern <stern@rowland.harvard.edu> | |
5 | * | |
6 | * (C) Copyright 1999 Linus Torvalds | |
7 | * (C) Copyright 1999-2002 Johannes Erdfelt, johannes@erdfelt.com | |
8 | * (C) Copyright 1999 Randy Dunlap | |
9 | * (C) Copyright 1999 Georg Acher, acher@in.tum.de | |
10 | * (C) Copyright 1999 Deti Fliegl, deti@fliegl.de | |
11 | * (C) Copyright 1999 Thomas Sailer, sailer@ife.ee.ethz.ch | |
12 | * (C) Copyright 1999 Roman Weissgaerber, weissg@vienna.at | |
13 | * (C) Copyright 2000 Yggdrasil Computing, Inc. (port of new PCI interface | |
14 | * support from usb-ohci.c by Adam Richter, adam@yggdrasil.com). | |
15 | * (C) Copyright 1999 Gregory P. Smith (from usb-ohci.c) | |
b761d9d8 | 16 | * (C) Copyright 2004-2006 Alan Stern, stern@rowland.harvard.edu |
1da177e4 LT |
17 | */ |
18 | ||
1da177e4 LT |
19 | |
20 | /* | |
21 | * Technically, updating td->status here is a race, but it's not really a | |
22 | * problem. The worst that can happen is that we set the IOC bit again | |
23 | * generating a spurious interrupt. We could fix this by creating another | |
24 | * QH and leaving the IOC bit always set, but then we would have to play | |
25 | * games with the FSBR code to make sure we get the correct order in all | |
26 | * the cases. I don't think it's worth the effort | |
27 | */ | |
dccf4a48 | 28 | static void uhci_set_next_interrupt(struct uhci_hcd *uhci) |
1da177e4 | 29 | { |
6c1b445c | 30 | if (uhci->is_stopped) |
1f09df8b | 31 | mod_timer(&uhci_to_hcd(uhci)->rh_timer, jiffies); |
1da177e4 LT |
32 | uhci->term_td->status |= cpu_to_le32(TD_CTRL_IOC); |
33 | } | |
34 | ||
35 | static inline void uhci_clear_next_interrupt(struct uhci_hcd *uhci) | |
36 | { | |
37 | uhci->term_td->status &= ~cpu_to_le32(TD_CTRL_IOC); | |
38 | } | |
39 | ||
84afddd7 AS |
40 | |
41 | /* | |
42 | * Full-Speed Bandwidth Reclamation (FSBR). | |
43 | * We turn on FSBR whenever a queue that wants it is advancing, | |
44 | * and leave it on for a short time thereafter. | |
45 | */ | |
46 | static void uhci_fsbr_on(struct uhci_hcd *uhci) | |
47 | { | |
48 | uhci->fsbr_is_on = 1; | |
49 | uhci->skel_term_qh->link = cpu_to_le32( | |
50 | uhci->skel_fs_control_qh->dma_handle) | UHCI_PTR_QH; | |
51 | } | |
52 | ||
53 | static void uhci_fsbr_off(struct uhci_hcd *uhci) | |
54 | { | |
55 | uhci->fsbr_is_on = 0; | |
56 | uhci->skel_term_qh->link = UHCI_PTR_TERM; | |
57 | } | |
58 | ||
59 | static void uhci_add_fsbr(struct uhci_hcd *uhci, struct urb *urb) | |
60 | { | |
61 | struct urb_priv *urbp = urb->hcpriv; | |
62 | ||
63 | if (!(urb->transfer_flags & URB_NO_FSBR)) | |
64 | urbp->fsbr = 1; | |
65 | } | |
66 | ||
67 | static void uhci_qh_wants_fsbr(struct uhci_hcd *uhci, struct uhci_qh *qh) | |
68 | { | |
69 | struct urb_priv *urbp = | |
70 | list_entry(qh->queue.next, struct urb_priv, node); | |
71 | ||
72 | if (urbp->fsbr) { | |
73 | uhci->fsbr_jiffies = jiffies; | |
74 | if (!uhci->fsbr_is_on) | |
75 | uhci_fsbr_on(uhci); | |
76 | } | |
77 | } | |
78 | ||
79 | ||
2532178a | 80 | static struct uhci_td *uhci_alloc_td(struct uhci_hcd *uhci) |
1da177e4 LT |
81 | { |
82 | dma_addr_t dma_handle; | |
83 | struct uhci_td *td; | |
84 | ||
85 | td = dma_pool_alloc(uhci->td_pool, GFP_ATOMIC, &dma_handle); | |
86 | if (!td) | |
87 | return NULL; | |
88 | ||
89 | td->dma_handle = dma_handle; | |
1da177e4 | 90 | td->frame = -1; |
1da177e4 LT |
91 | |
92 | INIT_LIST_HEAD(&td->list); | |
1da177e4 LT |
93 | INIT_LIST_HEAD(&td->fl_list); |
94 | ||
1da177e4 LT |
95 | return td; |
96 | } | |
97 | ||
dccf4a48 AS |
98 | static void uhci_free_td(struct uhci_hcd *uhci, struct uhci_td *td) |
99 | { | |
100 | if (!list_empty(&td->list)) | |
101 | dev_warn(uhci_dev(uhci), "td %p still in list!\n", td); | |
dccf4a48 AS |
102 | if (!list_empty(&td->fl_list)) |
103 | dev_warn(uhci_dev(uhci), "td %p still in fl_list!\n", td); | |
104 | ||
105 | dma_pool_free(uhci->td_pool, td, td->dma_handle); | |
106 | } | |
107 | ||
1da177e4 LT |
108 | static inline void uhci_fill_td(struct uhci_td *td, u32 status, |
109 | u32 token, u32 buffer) | |
110 | { | |
111 | td->status = cpu_to_le32(status); | |
112 | td->token = cpu_to_le32(token); | |
113 | td->buffer = cpu_to_le32(buffer); | |
114 | } | |
115 | ||
04538a25 AS |
116 | static void uhci_add_td_to_urbp(struct uhci_td *td, struct urb_priv *urbp) |
117 | { | |
118 | list_add_tail(&td->list, &urbp->td_list); | |
119 | } | |
120 | ||
121 | static void uhci_remove_td_from_urbp(struct uhci_td *td) | |
122 | { | |
123 | list_del_init(&td->list); | |
124 | } | |
125 | ||
1da177e4 | 126 | /* |
687f5f34 | 127 | * We insert Isochronous URBs directly into the frame list at the beginning |
1da177e4 | 128 | */ |
dccf4a48 AS |
129 | static inline void uhci_insert_td_in_frame_list(struct uhci_hcd *uhci, |
130 | struct uhci_td *td, unsigned framenum) | |
1da177e4 LT |
131 | { |
132 | framenum &= (UHCI_NUMFRAMES - 1); | |
133 | ||
134 | td->frame = framenum; | |
135 | ||
136 | /* Is there a TD already mapped there? */ | |
a1d59ce8 | 137 | if (uhci->frame_cpu[framenum]) { |
1da177e4 LT |
138 | struct uhci_td *ftd, *ltd; |
139 | ||
a1d59ce8 | 140 | ftd = uhci->frame_cpu[framenum]; |
1da177e4 LT |
141 | ltd = list_entry(ftd->fl_list.prev, struct uhci_td, fl_list); |
142 | ||
143 | list_add_tail(&td->fl_list, &ftd->fl_list); | |
144 | ||
145 | td->link = ltd->link; | |
146 | wmb(); | |
147 | ltd->link = cpu_to_le32(td->dma_handle); | |
148 | } else { | |
a1d59ce8 | 149 | td->link = uhci->frame[framenum]; |
1da177e4 | 150 | wmb(); |
a1d59ce8 AS |
151 | uhci->frame[framenum] = cpu_to_le32(td->dma_handle); |
152 | uhci->frame_cpu[framenum] = td; | |
1da177e4 LT |
153 | } |
154 | } | |
155 | ||
dccf4a48 | 156 | static inline void uhci_remove_td_from_frame_list(struct uhci_hcd *uhci, |
b81d3436 | 157 | struct uhci_td *td) |
1da177e4 LT |
158 | { |
159 | /* If it's not inserted, don't remove it */ | |
b81d3436 AS |
160 | if (td->frame == -1) { |
161 | WARN_ON(!list_empty(&td->fl_list)); | |
1da177e4 | 162 | return; |
b81d3436 | 163 | } |
1da177e4 | 164 | |
b81d3436 | 165 | if (uhci->frame_cpu[td->frame] == td) { |
1da177e4 | 166 | if (list_empty(&td->fl_list)) { |
a1d59ce8 AS |
167 | uhci->frame[td->frame] = td->link; |
168 | uhci->frame_cpu[td->frame] = NULL; | |
1da177e4 LT |
169 | } else { |
170 | struct uhci_td *ntd; | |
171 | ||
172 | ntd = list_entry(td->fl_list.next, struct uhci_td, fl_list); | |
a1d59ce8 AS |
173 | uhci->frame[td->frame] = cpu_to_le32(ntd->dma_handle); |
174 | uhci->frame_cpu[td->frame] = ntd; | |
1da177e4 LT |
175 | } |
176 | } else { | |
177 | struct uhci_td *ptd; | |
178 | ||
179 | ptd = list_entry(td->fl_list.prev, struct uhci_td, fl_list); | |
180 | ptd->link = td->link; | |
181 | } | |
182 | ||
1da177e4 LT |
183 | list_del_init(&td->fl_list); |
184 | td->frame = -1; | |
185 | } | |
186 | ||
dccf4a48 AS |
187 | /* |
188 | * Remove all the TDs for an Isochronous URB from the frame list | |
189 | */ | |
190 | static void uhci_unlink_isochronous_tds(struct uhci_hcd *uhci, struct urb *urb) | |
b81d3436 AS |
191 | { |
192 | struct urb_priv *urbp = (struct urb_priv *) urb->hcpriv; | |
193 | struct uhci_td *td; | |
194 | ||
195 | list_for_each_entry(td, &urbp->td_list, list) | |
dccf4a48 | 196 | uhci_remove_td_from_frame_list(uhci, td); |
b81d3436 AS |
197 | } |
198 | ||
dccf4a48 AS |
199 | static struct uhci_qh *uhci_alloc_qh(struct uhci_hcd *uhci, |
200 | struct usb_device *udev, struct usb_host_endpoint *hep) | |
1da177e4 LT |
201 | { |
202 | dma_addr_t dma_handle; | |
203 | struct uhci_qh *qh; | |
204 | ||
205 | qh = dma_pool_alloc(uhci->qh_pool, GFP_ATOMIC, &dma_handle); | |
206 | if (!qh) | |
207 | return NULL; | |
208 | ||
59e29ed9 | 209 | memset(qh, 0, sizeof(*qh)); |
1da177e4 LT |
210 | qh->dma_handle = dma_handle; |
211 | ||
212 | qh->element = UHCI_PTR_TERM; | |
213 | qh->link = UHCI_PTR_TERM; | |
214 | ||
dccf4a48 AS |
215 | INIT_LIST_HEAD(&qh->queue); |
216 | INIT_LIST_HEAD(&qh->node); | |
1da177e4 | 217 | |
dccf4a48 | 218 | if (udev) { /* Normal QH */ |
af0bb599 AS |
219 | qh->dummy_td = uhci_alloc_td(uhci); |
220 | if (!qh->dummy_td) { | |
221 | dma_pool_free(uhci->qh_pool, qh, dma_handle); | |
222 | return NULL; | |
223 | } | |
dccf4a48 AS |
224 | qh->state = QH_STATE_IDLE; |
225 | qh->hep = hep; | |
226 | qh->udev = udev; | |
227 | hep->hcpriv = qh; | |
4de7d2c2 | 228 | qh->type = hep->desc.bmAttributes & USB_ENDPOINT_XFERTYPE_MASK; |
1da177e4 | 229 | |
dccf4a48 AS |
230 | } else { /* Skeleton QH */ |
231 | qh->state = QH_STATE_ACTIVE; | |
4de7d2c2 | 232 | qh->type = -1; |
dccf4a48 | 233 | } |
1da177e4 LT |
234 | return qh; |
235 | } | |
236 | ||
237 | static void uhci_free_qh(struct uhci_hcd *uhci, struct uhci_qh *qh) | |
238 | { | |
dccf4a48 AS |
239 | WARN_ON(qh->state != QH_STATE_IDLE && qh->udev); |
240 | if (!list_empty(&qh->queue)) | |
1da177e4 | 241 | dev_warn(uhci_dev(uhci), "qh %p list not empty!\n", qh); |
1da177e4 | 242 | |
dccf4a48 AS |
243 | list_del(&qh->node); |
244 | if (qh->udev) { | |
245 | qh->hep->hcpriv = NULL; | |
af0bb599 | 246 | uhci_free_td(uhci, qh->dummy_td); |
dccf4a48 | 247 | } |
1da177e4 LT |
248 | dma_pool_free(uhci->qh_pool, qh, qh->dma_handle); |
249 | } | |
250 | ||
0ed8fee1 | 251 | /* |
a0b458b6 AS |
252 | * When a queue is stopped and a dequeued URB is given back, adjust |
253 | * the previous TD link (if the URB isn't first on the queue) or | |
254 | * save its toggle value (if it is first and is currently executing). | |
10b8e47d AS |
255 | * |
256 | * Returns 0 if the URB should not yet be given back, 1 otherwise. | |
0ed8fee1 | 257 | */ |
10b8e47d | 258 | static int uhci_cleanup_queue(struct uhci_hcd *uhci, struct uhci_qh *qh, |
a0b458b6 | 259 | struct urb *urb) |
0ed8fee1 | 260 | { |
a0b458b6 | 261 | struct urb_priv *urbp = urb->hcpriv; |
0ed8fee1 | 262 | struct uhci_td *td; |
10b8e47d | 263 | int ret = 1; |
0ed8fee1 | 264 | |
a0b458b6 | 265 | /* Isochronous pipes don't use toggles and their TD link pointers |
10b8e47d AS |
266 | * get adjusted during uhci_urb_dequeue(). But since their queues |
267 | * cannot truly be stopped, we have to watch out for dequeues | |
268 | * occurring after the nominal unlink frame. */ | |
269 | if (qh->type == USB_ENDPOINT_XFER_ISOC) { | |
270 | ret = (uhci->frame_number + uhci->is_stopped != | |
271 | qh->unlink_frame); | |
272 | return ret; | |
273 | } | |
a0b458b6 AS |
274 | |
275 | /* If the URB isn't first on its queue, adjust the link pointer | |
276 | * of the last TD in the previous URB. The toggle doesn't need | |
277 | * to be saved since this URB can't be executing yet. */ | |
278 | if (qh->queue.next != &urbp->node) { | |
279 | struct urb_priv *purbp; | |
280 | struct uhci_td *ptd; | |
281 | ||
282 | purbp = list_entry(urbp->node.prev, struct urb_priv, node); | |
283 | WARN_ON(list_empty(&purbp->td_list)); | |
284 | ptd = list_entry(purbp->td_list.prev, struct uhci_td, | |
285 | list); | |
286 | td = list_entry(urbp->td_list.prev, struct uhci_td, | |
287 | list); | |
288 | ptd->link = td->link; | |
10b8e47d | 289 | return ret; |
a0b458b6 AS |
290 | } |
291 | ||
0ed8fee1 AS |
292 | /* If the QH element pointer is UHCI_PTR_TERM then then currently |
293 | * executing URB has already been unlinked, so this one isn't it. */ | |
a0b458b6 | 294 | if (qh_element(qh) == UHCI_PTR_TERM) |
10b8e47d | 295 | return ret; |
0ed8fee1 AS |
296 | qh->element = UHCI_PTR_TERM; |
297 | ||
a0b458b6 AS |
298 | /* Control pipes have to worry about toggles */ |
299 | if (qh->type == USB_ENDPOINT_XFER_CONTROL) | |
10b8e47d | 300 | return ret; |
0ed8fee1 | 301 | |
a0b458b6 | 302 | /* Save the next toggle value */ |
59e29ed9 AS |
303 | WARN_ON(list_empty(&urbp->td_list)); |
304 | td = list_entry(urbp->td_list.next, struct uhci_td, list); | |
305 | qh->needs_fixup = 1; | |
306 | qh->initial_toggle = uhci_toggle(td_token(td)); | |
10b8e47d | 307 | return ret; |
0ed8fee1 AS |
308 | } |
309 | ||
310 | /* | |
311 | * Fix up the data toggles for URBs in a queue, when one of them | |
312 | * terminates early (short transfer, error, or dequeued). | |
313 | */ | |
314 | static void uhci_fixup_toggles(struct uhci_qh *qh, int skip_first) | |
315 | { | |
316 | struct urb_priv *urbp = NULL; | |
317 | struct uhci_td *td; | |
318 | unsigned int toggle = qh->initial_toggle; | |
319 | unsigned int pipe; | |
320 | ||
321 | /* Fixups for a short transfer start with the second URB in the | |
322 | * queue (the short URB is the first). */ | |
323 | if (skip_first) | |
324 | urbp = list_entry(qh->queue.next, struct urb_priv, node); | |
325 | ||
326 | /* When starting with the first URB, if the QH element pointer is | |
327 | * still valid then we know the URB's toggles are okay. */ | |
328 | else if (qh_element(qh) != UHCI_PTR_TERM) | |
329 | toggle = 2; | |
330 | ||
331 | /* Fix up the toggle for the URBs in the queue. Normally this | |
332 | * loop won't run more than once: When an error or short transfer | |
333 | * occurs, the queue usually gets emptied. */ | |
1393adb2 | 334 | urbp = list_prepare_entry(urbp, &qh->queue, node); |
0ed8fee1 AS |
335 | list_for_each_entry_continue(urbp, &qh->queue, node) { |
336 | ||
337 | /* If the first TD has the right toggle value, we don't | |
338 | * need to change any toggles in this URB */ | |
339 | td = list_entry(urbp->td_list.next, struct uhci_td, list); | |
340 | if (toggle > 1 || uhci_toggle(td_token(td)) == toggle) { | |
341 | td = list_entry(urbp->td_list.next, struct uhci_td, | |
342 | list); | |
343 | toggle = uhci_toggle(td_token(td)) ^ 1; | |
344 | ||
345 | /* Otherwise all the toggles in the URB have to be switched */ | |
346 | } else { | |
347 | list_for_each_entry(td, &urbp->td_list, list) { | |
348 | td->token ^= __constant_cpu_to_le32( | |
349 | TD_TOKEN_TOGGLE); | |
350 | toggle ^= 1; | |
351 | } | |
352 | } | |
353 | } | |
354 | ||
355 | wmb(); | |
356 | pipe = list_entry(qh->queue.next, struct urb_priv, node)->urb->pipe; | |
357 | usb_settoggle(qh->udev, usb_pipeendpoint(pipe), | |
358 | usb_pipeout(pipe), toggle); | |
359 | qh->needs_fixup = 0; | |
360 | } | |
361 | ||
1da177e4 | 362 | /* |
dccf4a48 | 363 | * Put a QH on the schedule in both hardware and software |
1da177e4 | 364 | */ |
dccf4a48 | 365 | static void uhci_activate_qh(struct uhci_hcd *uhci, struct uhci_qh *qh) |
1da177e4 | 366 | { |
dccf4a48 | 367 | struct uhci_qh *pqh; |
1da177e4 | 368 | |
dccf4a48 | 369 | WARN_ON(list_empty(&qh->queue)); |
1da177e4 | 370 | |
dccf4a48 AS |
371 | /* Set the element pointer if it isn't set already. |
372 | * This isn't needed for Isochronous queues, but it doesn't hurt. */ | |
373 | if (qh_element(qh) == UHCI_PTR_TERM) { | |
374 | struct urb_priv *urbp = list_entry(qh->queue.next, | |
375 | struct urb_priv, node); | |
376 | struct uhci_td *td = list_entry(urbp->td_list.next, | |
377 | struct uhci_td, list); | |
1da177e4 | 378 | |
dccf4a48 | 379 | qh->element = cpu_to_le32(td->dma_handle); |
1da177e4 LT |
380 | } |
381 | ||
84afddd7 AS |
382 | /* Treat the queue as if it has just advanced */ |
383 | qh->wait_expired = 0; | |
384 | qh->advance_jiffies = jiffies; | |
385 | ||
dccf4a48 AS |
386 | if (qh->state == QH_STATE_ACTIVE) |
387 | return; | |
388 | qh->state = QH_STATE_ACTIVE; | |
389 | ||
390 | /* Move the QH from its old list to the end of the appropriate | |
391 | * skeleton's list */ | |
0ed8fee1 AS |
392 | if (qh == uhci->next_qh) |
393 | uhci->next_qh = list_entry(qh->node.next, struct uhci_qh, | |
394 | node); | |
dccf4a48 AS |
395 | list_move_tail(&qh->node, &qh->skel->node); |
396 | ||
397 | /* Link it into the schedule */ | |
398 | pqh = list_entry(qh->node.prev, struct uhci_qh, node); | |
399 | qh->link = pqh->link; | |
400 | wmb(); | |
401 | pqh->link = UHCI_PTR_QH | cpu_to_le32(qh->dma_handle); | |
1da177e4 LT |
402 | } |
403 | ||
404 | /* | |
dccf4a48 | 405 | * Take a QH off the hardware schedule |
1da177e4 | 406 | */ |
dccf4a48 | 407 | static void uhci_unlink_qh(struct uhci_hcd *uhci, struct uhci_qh *qh) |
1da177e4 LT |
408 | { |
409 | struct uhci_qh *pqh; | |
1da177e4 | 410 | |
dccf4a48 | 411 | if (qh->state == QH_STATE_UNLINKING) |
1da177e4 | 412 | return; |
dccf4a48 AS |
413 | WARN_ON(qh->state != QH_STATE_ACTIVE || !qh->udev); |
414 | qh->state = QH_STATE_UNLINKING; | |
1da177e4 | 415 | |
dccf4a48 AS |
416 | /* Unlink the QH from the schedule and record when we did it */ |
417 | pqh = list_entry(qh->node.prev, struct uhci_qh, node); | |
418 | pqh->link = qh->link; | |
419 | mb(); | |
1da177e4 LT |
420 | |
421 | uhci_get_current_frame_number(uhci); | |
dccf4a48 | 422 | qh->unlink_frame = uhci->frame_number; |
1da177e4 | 423 | |
dccf4a48 AS |
424 | /* Force an interrupt so we know when the QH is fully unlinked */ |
425 | if (list_empty(&uhci->skel_unlink_qh->node)) | |
1da177e4 LT |
426 | uhci_set_next_interrupt(uhci); |
427 | ||
dccf4a48 | 428 | /* Move the QH from its old list to the end of the unlinking list */ |
0ed8fee1 AS |
429 | if (qh == uhci->next_qh) |
430 | uhci->next_qh = list_entry(qh->node.next, struct uhci_qh, | |
431 | node); | |
dccf4a48 | 432 | list_move_tail(&qh->node, &uhci->skel_unlink_qh->node); |
1da177e4 LT |
433 | } |
434 | ||
dccf4a48 AS |
435 | /* |
436 | * When we and the controller are through with a QH, it becomes IDLE. | |
437 | * This happens when a QH has been off the schedule (on the unlinking | |
438 | * list) for more than one frame, or when an error occurs while adding | |
439 | * the first URB onto a new QH. | |
440 | */ | |
441 | static void uhci_make_qh_idle(struct uhci_hcd *uhci, struct uhci_qh *qh) | |
1da177e4 | 442 | { |
dccf4a48 | 443 | WARN_ON(qh->state == QH_STATE_ACTIVE); |
1da177e4 | 444 | |
0ed8fee1 AS |
445 | if (qh == uhci->next_qh) |
446 | uhci->next_qh = list_entry(qh->node.next, struct uhci_qh, | |
447 | node); | |
dccf4a48 AS |
448 | list_move(&qh->node, &uhci->idle_qh_list); |
449 | qh->state = QH_STATE_IDLE; | |
1da177e4 | 450 | |
59e29ed9 AS |
451 | /* Now that the QH is idle, its post_td isn't being used */ |
452 | if (qh->post_td) { | |
453 | uhci_free_td(uhci, qh->post_td); | |
454 | qh->post_td = NULL; | |
455 | } | |
456 | ||
dccf4a48 AS |
457 | /* If anyone is waiting for a QH to become idle, wake them up */ |
458 | if (uhci->num_waiting) | |
459 | wake_up_all(&uhci->waitqh); | |
1da177e4 LT |
460 | } |
461 | ||
dccf4a48 AS |
462 | static inline struct urb_priv *uhci_alloc_urb_priv(struct uhci_hcd *uhci, |
463 | struct urb *urb) | |
1da177e4 LT |
464 | { |
465 | struct urb_priv *urbp; | |
466 | ||
467 | urbp = kmem_cache_alloc(uhci_up_cachep, SLAB_ATOMIC); | |
468 | if (!urbp) | |
469 | return NULL; | |
470 | ||
471 | memset((void *)urbp, 0, sizeof(*urbp)); | |
472 | ||
1da177e4 | 473 | urbp->urb = urb; |
dccf4a48 | 474 | urb->hcpriv = urbp; |
1da177e4 | 475 | |
dccf4a48 | 476 | INIT_LIST_HEAD(&urbp->node); |
1da177e4 | 477 | INIT_LIST_HEAD(&urbp->td_list); |
1da177e4 | 478 | |
1da177e4 LT |
479 | return urbp; |
480 | } | |
481 | ||
dccf4a48 AS |
482 | static void uhci_free_urb_priv(struct uhci_hcd *uhci, |
483 | struct urb_priv *urbp) | |
1da177e4 LT |
484 | { |
485 | struct uhci_td *td, *tmp; | |
1da177e4 | 486 | |
dccf4a48 AS |
487 | if (!list_empty(&urbp->node)) |
488 | dev_warn(uhci_dev(uhci), "urb %p still on QH's list!\n", | |
489 | urbp->urb); | |
1da177e4 | 490 | |
1da177e4 | 491 | list_for_each_entry_safe(td, tmp, &urbp->td_list, list) { |
04538a25 AS |
492 | uhci_remove_td_from_urbp(td); |
493 | uhci_free_td(uhci, td); | |
1da177e4 LT |
494 | } |
495 | ||
dccf4a48 | 496 | urbp->urb->hcpriv = NULL; |
1da177e4 LT |
497 | kmem_cache_free(uhci_up_cachep, urbp); |
498 | } | |
499 | ||
1da177e4 LT |
500 | /* |
501 | * Map status to standard result codes | |
502 | * | |
503 | * <status> is (td_status(td) & 0xF60000), a.k.a. | |
504 | * uhci_status_bits(td_status(td)). | |
505 | * Note: <status> does not include the TD_CTRL_NAK bit. | |
506 | * <dir_out> is True for output TDs and False for input TDs. | |
507 | */ | |
508 | static int uhci_map_status(int status, int dir_out) | |
509 | { | |
510 | if (!status) | |
511 | return 0; | |
512 | if (status & TD_CTRL_BITSTUFF) /* Bitstuff error */ | |
513 | return -EPROTO; | |
514 | if (status & TD_CTRL_CRCTIMEO) { /* CRC/Timeout */ | |
515 | if (dir_out) | |
516 | return -EPROTO; | |
517 | else | |
518 | return -EILSEQ; | |
519 | } | |
520 | if (status & TD_CTRL_BABBLE) /* Babble */ | |
521 | return -EOVERFLOW; | |
522 | if (status & TD_CTRL_DBUFERR) /* Buffer error */ | |
523 | return -ENOSR; | |
524 | if (status & TD_CTRL_STALLED) /* Stalled */ | |
525 | return -EPIPE; | |
526 | WARN_ON(status & TD_CTRL_ACTIVE); /* Active */ | |
527 | return 0; | |
528 | } | |
529 | ||
530 | /* | |
531 | * Control transfers | |
532 | */ | |
dccf4a48 AS |
533 | static int uhci_submit_control(struct uhci_hcd *uhci, struct urb *urb, |
534 | struct uhci_qh *qh) | |
1da177e4 | 535 | { |
1da177e4 | 536 | struct uhci_td *td; |
1da177e4 | 537 | unsigned long destination, status; |
dccf4a48 | 538 | int maxsze = le16_to_cpu(qh->hep->desc.wMaxPacketSize); |
1da177e4 LT |
539 | int len = urb->transfer_buffer_length; |
540 | dma_addr_t data = urb->transfer_dma; | |
dccf4a48 | 541 | __le32 *plink; |
04538a25 | 542 | struct urb_priv *urbp = urb->hcpriv; |
1da177e4 LT |
543 | |
544 | /* The "pipe" thing contains the destination in bits 8--18 */ | |
545 | destination = (urb->pipe & PIPE_DEVEP_MASK) | USB_PID_SETUP; | |
546 | ||
af0bb599 AS |
547 | /* 3 errors, dummy TD remains inactive */ |
548 | status = uhci_maxerr(3); | |
1da177e4 LT |
549 | if (urb->dev->speed == USB_SPEED_LOW) |
550 | status |= TD_CTRL_LS; | |
551 | ||
552 | /* | |
553 | * Build the TD for the control request setup packet | |
554 | */ | |
af0bb599 | 555 | td = qh->dummy_td; |
04538a25 | 556 | uhci_add_td_to_urbp(td, urbp); |
fa346568 | 557 | uhci_fill_td(td, status, destination | uhci_explen(8), |
dccf4a48 AS |
558 | urb->setup_dma); |
559 | plink = &td->link; | |
af0bb599 | 560 | status |= TD_CTRL_ACTIVE; |
1da177e4 LT |
561 | |
562 | /* | |
563 | * If direction is "send", change the packet ID from SETUP (0x2D) | |
564 | * to OUT (0xE1). Else change it from SETUP to IN (0x69) and | |
565 | * set Short Packet Detect (SPD) for all data packets. | |
566 | */ | |
567 | if (usb_pipeout(urb->pipe)) | |
568 | destination ^= (USB_PID_SETUP ^ USB_PID_OUT); | |
569 | else { | |
570 | destination ^= (USB_PID_SETUP ^ USB_PID_IN); | |
571 | status |= TD_CTRL_SPD; | |
572 | } | |
573 | ||
574 | /* | |
687f5f34 | 575 | * Build the DATA TDs |
1da177e4 LT |
576 | */ |
577 | while (len > 0) { | |
dccf4a48 | 578 | int pktsze = min(len, maxsze); |
1da177e4 | 579 | |
2532178a | 580 | td = uhci_alloc_td(uhci); |
1da177e4 | 581 | if (!td) |
af0bb599 | 582 | goto nomem; |
dccf4a48 | 583 | *plink = cpu_to_le32(td->dma_handle); |
1da177e4 LT |
584 | |
585 | /* Alternate Data0/1 (start with Data1) */ | |
586 | destination ^= TD_TOKEN_TOGGLE; | |
587 | ||
04538a25 | 588 | uhci_add_td_to_urbp(td, urbp); |
fa346568 | 589 | uhci_fill_td(td, status, destination | uhci_explen(pktsze), |
dccf4a48 AS |
590 | data); |
591 | plink = &td->link; | |
1da177e4 LT |
592 | |
593 | data += pktsze; | |
594 | len -= pktsze; | |
595 | } | |
596 | ||
597 | /* | |
598 | * Build the final TD for control status | |
599 | */ | |
2532178a | 600 | td = uhci_alloc_td(uhci); |
1da177e4 | 601 | if (!td) |
af0bb599 | 602 | goto nomem; |
dccf4a48 | 603 | *plink = cpu_to_le32(td->dma_handle); |
1da177e4 LT |
604 | |
605 | /* | |
606 | * It's IN if the pipe is an output pipe or we're not expecting | |
607 | * data back. | |
608 | */ | |
609 | destination &= ~TD_TOKEN_PID_MASK; | |
610 | if (usb_pipeout(urb->pipe) || !urb->transfer_buffer_length) | |
611 | destination |= USB_PID_IN; | |
612 | else | |
613 | destination |= USB_PID_OUT; | |
614 | ||
615 | destination |= TD_TOKEN_TOGGLE; /* End in Data1 */ | |
616 | ||
617 | status &= ~TD_CTRL_SPD; | |
618 | ||
04538a25 | 619 | uhci_add_td_to_urbp(td, urbp); |
1da177e4 | 620 | uhci_fill_td(td, status | TD_CTRL_IOC, |
dccf4a48 | 621 | destination | uhci_explen(0), 0); |
af0bb599 AS |
622 | plink = &td->link; |
623 | ||
624 | /* | |
625 | * Build the new dummy TD and activate the old one | |
626 | */ | |
627 | td = uhci_alloc_td(uhci); | |
628 | if (!td) | |
629 | goto nomem; | |
630 | *plink = cpu_to_le32(td->dma_handle); | |
631 | ||
632 | uhci_fill_td(td, 0, USB_PID_OUT | uhci_explen(0), 0); | |
633 | wmb(); | |
634 | qh->dummy_td->status |= __constant_cpu_to_le32(TD_CTRL_ACTIVE); | |
635 | qh->dummy_td = td; | |
1da177e4 LT |
636 | |
637 | /* Low-speed transfers get a different queue, and won't hog the bus. | |
638 | * Also, some devices enumerate better without FSBR; the easiest way | |
639 | * to do that is to put URBs on the low-speed queue while the device | |
630aa3cf | 640 | * isn't in the CONFIGURED state. */ |
1da177e4 | 641 | if (urb->dev->speed == USB_SPEED_LOW || |
630aa3cf | 642 | urb->dev->state != USB_STATE_CONFIGURED) |
dccf4a48 | 643 | qh->skel = uhci->skel_ls_control_qh; |
1da177e4 | 644 | else { |
dccf4a48 | 645 | qh->skel = uhci->skel_fs_control_qh; |
84afddd7 | 646 | uhci_add_fsbr(uhci, urb); |
1da177e4 | 647 | } |
59e29ed9 AS |
648 | |
649 | urb->actual_length = -8; /* Account for the SETUP packet */ | |
dccf4a48 | 650 | return 0; |
af0bb599 AS |
651 | |
652 | nomem: | |
653 | /* Remove the dummy TD from the td_list so it doesn't get freed */ | |
04538a25 | 654 | uhci_remove_td_from_urbp(qh->dummy_td); |
af0bb599 | 655 | return -ENOMEM; |
1da177e4 LT |
656 | } |
657 | ||
1da177e4 LT |
658 | /* |
659 | * Common submit for bulk and interrupt | |
660 | */ | |
dccf4a48 AS |
661 | static int uhci_submit_common(struct uhci_hcd *uhci, struct urb *urb, |
662 | struct uhci_qh *qh) | |
1da177e4 LT |
663 | { |
664 | struct uhci_td *td; | |
1da177e4 | 665 | unsigned long destination, status; |
dccf4a48 | 666 | int maxsze = le16_to_cpu(qh->hep->desc.wMaxPacketSize); |
1da177e4 | 667 | int len = urb->transfer_buffer_length; |
1da177e4 | 668 | dma_addr_t data = urb->transfer_dma; |
af0bb599 | 669 | __le32 *plink; |
04538a25 | 670 | struct urb_priv *urbp = urb->hcpriv; |
af0bb599 | 671 | unsigned int toggle; |
1da177e4 LT |
672 | |
673 | if (len < 0) | |
674 | return -EINVAL; | |
675 | ||
676 | /* The "pipe" thing contains the destination in bits 8--18 */ | |
677 | destination = (urb->pipe & PIPE_DEVEP_MASK) | usb_packetid(urb->pipe); | |
af0bb599 AS |
678 | toggle = usb_gettoggle(urb->dev, usb_pipeendpoint(urb->pipe), |
679 | usb_pipeout(urb->pipe)); | |
1da177e4 | 680 | |
af0bb599 AS |
681 | /* 3 errors, dummy TD remains inactive */ |
682 | status = uhci_maxerr(3); | |
1da177e4 LT |
683 | if (urb->dev->speed == USB_SPEED_LOW) |
684 | status |= TD_CTRL_LS; | |
685 | if (usb_pipein(urb->pipe)) | |
686 | status |= TD_CTRL_SPD; | |
687 | ||
688 | /* | |
687f5f34 | 689 | * Build the DATA TDs |
1da177e4 | 690 | */ |
af0bb599 AS |
691 | plink = NULL; |
692 | td = qh->dummy_td; | |
1da177e4 LT |
693 | do { /* Allow zero length packets */ |
694 | int pktsze = maxsze; | |
695 | ||
dccf4a48 | 696 | if (len <= pktsze) { /* The last packet */ |
1da177e4 LT |
697 | pktsze = len; |
698 | if (!(urb->transfer_flags & URB_SHORT_NOT_OK)) | |
699 | status &= ~TD_CTRL_SPD; | |
700 | } | |
701 | ||
af0bb599 AS |
702 | if (plink) { |
703 | td = uhci_alloc_td(uhci); | |
704 | if (!td) | |
705 | goto nomem; | |
706 | *plink = cpu_to_le32(td->dma_handle); | |
707 | } | |
04538a25 | 708 | uhci_add_td_to_urbp(td, urbp); |
dccf4a48 | 709 | uhci_fill_td(td, status, |
af0bb599 AS |
710 | destination | uhci_explen(pktsze) | |
711 | (toggle << TD_TOKEN_TOGGLE_SHIFT), | |
712 | data); | |
dccf4a48 | 713 | plink = &td->link; |
af0bb599 | 714 | status |= TD_CTRL_ACTIVE; |
1da177e4 LT |
715 | |
716 | data += pktsze; | |
717 | len -= maxsze; | |
af0bb599 | 718 | toggle ^= 1; |
1da177e4 LT |
719 | } while (len > 0); |
720 | ||
721 | /* | |
722 | * URB_ZERO_PACKET means adding a 0-length packet, if direction | |
723 | * is OUT and the transfer_length was an exact multiple of maxsze, | |
724 | * hence (len = transfer_length - N * maxsze) == 0 | |
725 | * however, if transfer_length == 0, the zero packet was already | |
726 | * prepared above. | |
727 | */ | |
dccf4a48 AS |
728 | if ((urb->transfer_flags & URB_ZERO_PACKET) && |
729 | usb_pipeout(urb->pipe) && len == 0 && | |
730 | urb->transfer_buffer_length > 0) { | |
2532178a | 731 | td = uhci_alloc_td(uhci); |
1da177e4 | 732 | if (!td) |
af0bb599 | 733 | goto nomem; |
dccf4a48 | 734 | *plink = cpu_to_le32(td->dma_handle); |
1da177e4 | 735 | |
04538a25 | 736 | uhci_add_td_to_urbp(td, urbp); |
af0bb599 AS |
737 | uhci_fill_td(td, status, |
738 | destination | uhci_explen(0) | | |
739 | (toggle << TD_TOKEN_TOGGLE_SHIFT), | |
740 | data); | |
741 | plink = &td->link; | |
1da177e4 | 742 | |
af0bb599 | 743 | toggle ^= 1; |
1da177e4 LT |
744 | } |
745 | ||
746 | /* Set the interrupt-on-completion flag on the last packet. | |
747 | * A more-or-less typical 4 KB URB (= size of one memory page) | |
748 | * will require about 3 ms to transfer; that's a little on the | |
749 | * fast side but not enough to justify delaying an interrupt | |
750 | * more than 2 or 3 URBs, so we will ignore the URB_NO_INTERRUPT | |
751 | * flag setting. */ | |
dccf4a48 | 752 | td->status |= __constant_cpu_to_le32(TD_CTRL_IOC); |
1da177e4 | 753 | |
af0bb599 AS |
754 | /* |
755 | * Build the new dummy TD and activate the old one | |
756 | */ | |
757 | td = uhci_alloc_td(uhci); | |
758 | if (!td) | |
759 | goto nomem; | |
760 | *plink = cpu_to_le32(td->dma_handle); | |
761 | ||
762 | uhci_fill_td(td, 0, USB_PID_OUT | uhci_explen(0), 0); | |
763 | wmb(); | |
764 | qh->dummy_td->status |= __constant_cpu_to_le32(TD_CTRL_ACTIVE); | |
765 | qh->dummy_td = td; | |
766 | ||
767 | usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe), | |
768 | usb_pipeout(urb->pipe), toggle); | |
dccf4a48 | 769 | return 0; |
af0bb599 AS |
770 | |
771 | nomem: | |
772 | /* Remove the dummy TD from the td_list so it doesn't get freed */ | |
04538a25 | 773 | uhci_remove_td_from_urbp(qh->dummy_td); |
af0bb599 | 774 | return -ENOMEM; |
1da177e4 LT |
775 | } |
776 | ||
dccf4a48 AS |
777 | static inline int uhci_submit_bulk(struct uhci_hcd *uhci, struct urb *urb, |
778 | struct uhci_qh *qh) | |
1da177e4 LT |
779 | { |
780 | int ret; | |
781 | ||
782 | /* Can't have low-speed bulk transfers */ | |
783 | if (urb->dev->speed == USB_SPEED_LOW) | |
784 | return -EINVAL; | |
785 | ||
dccf4a48 AS |
786 | qh->skel = uhci->skel_bulk_qh; |
787 | ret = uhci_submit_common(uhci, urb, qh); | |
788 | if (ret == 0) | |
84afddd7 | 789 | uhci_add_fsbr(uhci, urb); |
1da177e4 LT |
790 | return ret; |
791 | } | |
792 | ||
dccf4a48 AS |
793 | static inline int uhci_submit_interrupt(struct uhci_hcd *uhci, struct urb *urb, |
794 | struct uhci_qh *qh) | |
1da177e4 | 795 | { |
dccf4a48 AS |
796 | /* USB 1.1 interrupt transfers only involve one packet per interval. |
797 | * Drivers can submit URBs of any length, but longer ones will need | |
798 | * multiple intervals to complete. | |
1da177e4 | 799 | */ |
dccf4a48 AS |
800 | qh->skel = uhci->skelqh[__interval_to_skel(urb->interval)]; |
801 | return uhci_submit_common(uhci, urb, qh); | |
1da177e4 LT |
802 | } |
803 | ||
b1869000 AS |
804 | /* |
805 | * Fix up the data structures following a short transfer | |
806 | */ | |
807 | static int uhci_fixup_short_transfer(struct uhci_hcd *uhci, | |
59e29ed9 | 808 | struct uhci_qh *qh, struct urb_priv *urbp) |
b1869000 AS |
809 | { |
810 | struct uhci_td *td; | |
59e29ed9 AS |
811 | struct list_head *tmp; |
812 | int ret; | |
b1869000 AS |
813 | |
814 | td = list_entry(urbp->td_list.prev, struct uhci_td, list); | |
815 | if (qh->type == USB_ENDPOINT_XFER_CONTROL) { | |
b1869000 AS |
816 | |
817 | /* When a control transfer is short, we have to restart | |
818 | * the queue at the status stage transaction, which is | |
819 | * the last TD. */ | |
59e29ed9 | 820 | WARN_ON(list_empty(&urbp->td_list)); |
b1869000 | 821 | qh->element = cpu_to_le32(td->dma_handle); |
59e29ed9 | 822 | tmp = td->list.prev; |
b1869000 AS |
823 | ret = -EINPROGRESS; |
824 | ||
59e29ed9 | 825 | } else { |
b1869000 AS |
826 | |
827 | /* When a bulk/interrupt transfer is short, we have to | |
828 | * fix up the toggles of the following URBs on the queue | |
829 | * before restarting the queue at the next URB. */ | |
59e29ed9 | 830 | qh->initial_toggle = uhci_toggle(td_token(qh->post_td)) ^ 1; |
b1869000 AS |
831 | uhci_fixup_toggles(qh, 1); |
832 | ||
59e29ed9 AS |
833 | if (list_empty(&urbp->td_list)) |
834 | td = qh->post_td; | |
b1869000 | 835 | qh->element = td->link; |
59e29ed9 AS |
836 | tmp = urbp->td_list.prev; |
837 | ret = 0; | |
b1869000 AS |
838 | } |
839 | ||
59e29ed9 AS |
840 | /* Remove all the TDs we skipped over, from tmp back to the start */ |
841 | while (tmp != &urbp->td_list) { | |
842 | td = list_entry(tmp, struct uhci_td, list); | |
843 | tmp = tmp->prev; | |
844 | ||
04538a25 AS |
845 | uhci_remove_td_from_urbp(td); |
846 | uhci_free_td(uhci, td); | |
59e29ed9 | 847 | } |
b1869000 AS |
848 | return ret; |
849 | } | |
850 | ||
851 | /* | |
852 | * Common result for control, bulk, and interrupt | |
853 | */ | |
854 | static int uhci_result_common(struct uhci_hcd *uhci, struct urb *urb) | |
855 | { | |
856 | struct urb_priv *urbp = urb->hcpriv; | |
857 | struct uhci_qh *qh = urbp->qh; | |
59e29ed9 | 858 | struct uhci_td *td, *tmp; |
b1869000 AS |
859 | unsigned status; |
860 | int ret = 0; | |
861 | ||
59e29ed9 | 862 | list_for_each_entry_safe(td, tmp, &urbp->td_list, list) { |
b1869000 AS |
863 | unsigned int ctrlstat; |
864 | int len; | |
865 | ||
b1869000 AS |
866 | ctrlstat = td_status(td); |
867 | status = uhci_status_bits(ctrlstat); | |
868 | if (status & TD_CTRL_ACTIVE) | |
869 | return -EINPROGRESS; | |
870 | ||
871 | len = uhci_actual_length(ctrlstat); | |
872 | urb->actual_length += len; | |
873 | ||
874 | if (status) { | |
875 | ret = uhci_map_status(status, | |
876 | uhci_packetout(td_token(td))); | |
877 | if ((debug == 1 && ret != -EPIPE) || debug > 1) { | |
878 | /* Some debugging code */ | |
879 | dev_dbg(uhci_dev(uhci), | |
880 | "%s: failed with status %x\n", | |
881 | __FUNCTION__, status); | |
882 | ||
883 | if (debug > 1 && errbuf) { | |
884 | /* Print the chain for debugging */ | |
885 | uhci_show_qh(urbp->qh, errbuf, | |
886 | ERRBUF_LEN, 0); | |
887 | lprintk(errbuf); | |
888 | } | |
889 | } | |
890 | ||
891 | } else if (len < uhci_expected_length(td_token(td))) { | |
892 | ||
893 | /* We received a short packet */ | |
894 | if (urb->transfer_flags & URB_SHORT_NOT_OK) | |
895 | ret = -EREMOTEIO; | |
896 | else if (ctrlstat & TD_CTRL_SPD) | |
897 | ret = 1; | |
898 | } | |
899 | ||
04538a25 | 900 | uhci_remove_td_from_urbp(td); |
59e29ed9 | 901 | if (qh->post_td) |
04538a25 | 902 | uhci_free_td(uhci, qh->post_td); |
59e29ed9 AS |
903 | qh->post_td = td; |
904 | ||
b1869000 AS |
905 | if (ret != 0) |
906 | goto err; | |
907 | } | |
908 | return ret; | |
909 | ||
910 | err: | |
911 | if (ret < 0) { | |
912 | /* In case a control transfer gets an error | |
913 | * during the setup stage */ | |
914 | urb->actual_length = max(urb->actual_length, 0); | |
915 | ||
916 | /* Note that the queue has stopped and save | |
917 | * the next toggle value */ | |
918 | qh->element = UHCI_PTR_TERM; | |
919 | qh->is_stopped = 1; | |
920 | qh->needs_fixup = (qh->type != USB_ENDPOINT_XFER_CONTROL); | |
921 | qh->initial_toggle = uhci_toggle(td_token(td)) ^ | |
922 | (ret == -EREMOTEIO); | |
923 | ||
924 | } else /* Short packet received */ | |
59e29ed9 | 925 | ret = uhci_fixup_short_transfer(uhci, qh, urbp); |
b1869000 AS |
926 | return ret; |
927 | } | |
928 | ||
1da177e4 LT |
929 | /* |
930 | * Isochronous transfers | |
931 | */ | |
0ed8fee1 AS |
932 | static int uhci_submit_isochronous(struct uhci_hcd *uhci, struct urb *urb, |
933 | struct uhci_qh *qh) | |
1da177e4 | 934 | { |
0ed8fee1 AS |
935 | struct uhci_td *td = NULL; /* Since urb->number_of_packets > 0 */ |
936 | int i, frame; | |
937 | unsigned long destination, status; | |
938 | struct urb_priv *urbp = (struct urb_priv *) urb->hcpriv; | |
1da177e4 LT |
939 | |
940 | if (urb->number_of_packets > 900) /* 900? Why? */ | |
941 | return -EFBIG; | |
942 | ||
0ed8fee1 AS |
943 | status = TD_CTRL_ACTIVE | TD_CTRL_IOS; |
944 | destination = (urb->pipe & PIPE_DEVEP_MASK) | usb_packetid(urb->pipe); | |
1da177e4 | 945 | |
0ed8fee1 | 946 | /* Figure out the starting frame number */ |
1da177e4 | 947 | if (urb->transfer_flags & URB_ISO_ASAP) { |
0ed8fee1 | 948 | if (list_empty(&qh->queue)) { |
1da177e4 | 949 | uhci_get_current_frame_number(uhci); |
0ed8fee1 AS |
950 | urb->start_frame = (uhci->frame_number + 10); |
951 | ||
952 | } else { /* Go right after the last one */ | |
953 | struct urb *last_urb; | |
954 | ||
955 | last_urb = list_entry(qh->queue.prev, | |
956 | struct urb_priv, node)->urb; | |
957 | urb->start_frame = (last_urb->start_frame + | |
958 | last_urb->number_of_packets * | |
959 | last_urb->interval); | |
960 | } | |
1da177e4 | 961 | } else { |
1da177e4 LT |
962 | /* FIXME: Sanity check */ |
963 | } | |
1da177e4 | 964 | |
b81d3436 | 965 | for (i = 0; i < urb->number_of_packets; i++) { |
2532178a | 966 | td = uhci_alloc_td(uhci); |
1da177e4 LT |
967 | if (!td) |
968 | return -ENOMEM; | |
969 | ||
04538a25 | 970 | uhci_add_td_to_urbp(td, urbp); |
dccf4a48 AS |
971 | uhci_fill_td(td, status, destination | |
972 | uhci_explen(urb->iso_frame_desc[i].length), | |
973 | urb->transfer_dma + | |
974 | urb->iso_frame_desc[i].offset); | |
b81d3436 | 975 | } |
1da177e4 | 976 | |
dccf4a48 AS |
977 | /* Set the interrupt-on-completion flag on the last packet. */ |
978 | td->status |= __constant_cpu_to_le32(TD_CTRL_IOC); | |
979 | ||
980 | qh->skel = uhci->skel_iso_qh; | |
981 | ||
982 | /* Add the TDs to the frame list */ | |
b81d3436 AS |
983 | frame = urb->start_frame; |
984 | list_for_each_entry(td, &urbp->td_list, list) { | |
dccf4a48 | 985 | uhci_insert_td_in_frame_list(uhci, td, frame); |
b81d3436 | 986 | frame += urb->interval; |
1da177e4 LT |
987 | } |
988 | ||
dccf4a48 | 989 | return 0; |
1da177e4 LT |
990 | } |
991 | ||
992 | static int uhci_result_isochronous(struct uhci_hcd *uhci, struct urb *urb) | |
993 | { | |
994 | struct uhci_td *td; | |
995 | struct urb_priv *urbp = (struct urb_priv *)urb->hcpriv; | |
996 | int status; | |
997 | int i, ret = 0; | |
998 | ||
b81d3436 | 999 | urb->actual_length = urb->error_count = 0; |
1da177e4 LT |
1000 | |
1001 | i = 0; | |
1002 | list_for_each_entry(td, &urbp->td_list, list) { | |
1003 | int actlength; | |
1004 | unsigned int ctrlstat = td_status(td); | |
1005 | ||
1006 | if (ctrlstat & TD_CTRL_ACTIVE) | |
1007 | return -EINPROGRESS; | |
1008 | ||
1009 | actlength = uhci_actual_length(ctrlstat); | |
1010 | urb->iso_frame_desc[i].actual_length = actlength; | |
1011 | urb->actual_length += actlength; | |
1012 | ||
1013 | status = uhci_map_status(uhci_status_bits(ctrlstat), | |
1014 | usb_pipeout(urb->pipe)); | |
1015 | urb->iso_frame_desc[i].status = status; | |
1016 | if (status) { | |
1017 | urb->error_count++; | |
1018 | ret = status; | |
1019 | } | |
1020 | ||
1021 | i++; | |
1022 | } | |
1023 | ||
1024 | return ret; | |
1025 | } | |
1026 | ||
1da177e4 | 1027 | static int uhci_urb_enqueue(struct usb_hcd *hcd, |
dccf4a48 | 1028 | struct usb_host_endpoint *hep, |
55016f10 | 1029 | struct urb *urb, gfp_t mem_flags) |
1da177e4 LT |
1030 | { |
1031 | int ret; | |
1032 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
1033 | unsigned long flags; | |
dccf4a48 AS |
1034 | struct urb_priv *urbp; |
1035 | struct uhci_qh *qh; | |
1da177e4 LT |
1036 | int bustime; |
1037 | ||
1038 | spin_lock_irqsave(&uhci->lock, flags); | |
1039 | ||
1040 | ret = urb->status; | |
1041 | if (ret != -EINPROGRESS) /* URB already unlinked! */ | |
dccf4a48 | 1042 | goto done; |
1da177e4 | 1043 | |
dccf4a48 AS |
1044 | ret = -ENOMEM; |
1045 | urbp = uhci_alloc_urb_priv(uhci, urb); | |
1046 | if (!urbp) | |
1047 | goto done; | |
1da177e4 | 1048 | |
dccf4a48 AS |
1049 | if (hep->hcpriv) |
1050 | qh = (struct uhci_qh *) hep->hcpriv; | |
1051 | else { | |
1052 | qh = uhci_alloc_qh(uhci, urb->dev, hep); | |
1053 | if (!qh) | |
1054 | goto err_no_qh; | |
1da177e4 | 1055 | } |
dccf4a48 | 1056 | urbp->qh = qh; |
1da177e4 | 1057 | |
4de7d2c2 AS |
1058 | switch (qh->type) { |
1059 | case USB_ENDPOINT_XFER_CONTROL: | |
dccf4a48 AS |
1060 | ret = uhci_submit_control(uhci, urb, qh); |
1061 | break; | |
4de7d2c2 | 1062 | case USB_ENDPOINT_XFER_BULK: |
dccf4a48 | 1063 | ret = uhci_submit_bulk(uhci, urb, qh); |
1da177e4 | 1064 | break; |
4de7d2c2 | 1065 | case USB_ENDPOINT_XFER_INT: |
dccf4a48 | 1066 | if (list_empty(&qh->queue)) { |
1da177e4 LT |
1067 | bustime = usb_check_bandwidth(urb->dev, urb); |
1068 | if (bustime < 0) | |
1069 | ret = bustime; | |
1070 | else { | |
dccf4a48 AS |
1071 | ret = uhci_submit_interrupt(uhci, urb, qh); |
1072 | if (ret == 0) | |
1da177e4 LT |
1073 | usb_claim_bandwidth(urb->dev, urb, bustime, 0); |
1074 | } | |
1075 | } else { /* inherit from parent */ | |
dccf4a48 AS |
1076 | struct urb_priv *eurbp; |
1077 | ||
1078 | eurbp = list_entry(qh->queue.prev, struct urb_priv, | |
1079 | node); | |
1080 | urb->bandwidth = eurbp->urb->bandwidth; | |
1081 | ret = uhci_submit_interrupt(uhci, urb, qh); | |
1da177e4 LT |
1082 | } |
1083 | break; | |
4de7d2c2 | 1084 | case USB_ENDPOINT_XFER_ISOC: |
1da177e4 LT |
1085 | bustime = usb_check_bandwidth(urb->dev, urb); |
1086 | if (bustime < 0) { | |
1087 | ret = bustime; | |
1088 | break; | |
1089 | } | |
1090 | ||
dccf4a48 AS |
1091 | ret = uhci_submit_isochronous(uhci, urb, qh); |
1092 | if (ret == 0) | |
1da177e4 LT |
1093 | usb_claim_bandwidth(urb->dev, urb, bustime, 1); |
1094 | break; | |
1095 | } | |
dccf4a48 AS |
1096 | if (ret != 0) |
1097 | goto err_submit_failed; | |
1da177e4 | 1098 | |
dccf4a48 AS |
1099 | /* Add this URB to the QH */ |
1100 | urbp->qh = qh; | |
1101 | list_add_tail(&urbp->node, &qh->queue); | |
1da177e4 | 1102 | |
dccf4a48 AS |
1103 | /* If the new URB is the first and only one on this QH then either |
1104 | * the QH is new and idle or else it's unlinked and waiting to | |
2775562a AS |
1105 | * become idle, so we can activate it right away. But only if the |
1106 | * queue isn't stopped. */ | |
84afddd7 | 1107 | if (qh->queue.next == &urbp->node && !qh->is_stopped) { |
dccf4a48 | 1108 | uhci_activate_qh(uhci, qh); |
84afddd7 AS |
1109 | uhci_qh_wants_fsbr(uhci, qh); |
1110 | } | |
dccf4a48 AS |
1111 | goto done; |
1112 | ||
1113 | err_submit_failed: | |
1114 | if (qh->state == QH_STATE_IDLE) | |
1115 | uhci_make_qh_idle(uhci, qh); /* Reclaim unused QH */ | |
1da177e4 | 1116 | |
dccf4a48 AS |
1117 | err_no_qh: |
1118 | uhci_free_urb_priv(uhci, urbp); | |
1119 | ||
1120 | done: | |
1da177e4 LT |
1121 | spin_unlock_irqrestore(&uhci->lock, flags); |
1122 | return ret; | |
1123 | } | |
1124 | ||
0ed8fee1 AS |
1125 | static int uhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb) |
1126 | { | |
1127 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
1128 | unsigned long flags; | |
1129 | struct urb_priv *urbp; | |
10b8e47d | 1130 | struct uhci_qh *qh; |
0ed8fee1 AS |
1131 | |
1132 | spin_lock_irqsave(&uhci->lock, flags); | |
1133 | urbp = urb->hcpriv; | |
1134 | if (!urbp) /* URB was never linked! */ | |
1135 | goto done; | |
10b8e47d | 1136 | qh = urbp->qh; |
0ed8fee1 AS |
1137 | |
1138 | /* Remove Isochronous TDs from the frame list ASAP */ | |
10b8e47d | 1139 | if (qh->type == USB_ENDPOINT_XFER_ISOC) { |
0ed8fee1 | 1140 | uhci_unlink_isochronous_tds(uhci, urb); |
10b8e47d AS |
1141 | mb(); |
1142 | ||
1143 | /* If the URB has already started, update the QH unlink time */ | |
1144 | uhci_get_current_frame_number(uhci); | |
1145 | if (uhci_frame_before_eq(urb->start_frame, uhci->frame_number)) | |
1146 | qh->unlink_frame = uhci->frame_number; | |
1147 | } | |
1148 | ||
1149 | uhci_unlink_qh(uhci, qh); | |
0ed8fee1 AS |
1150 | |
1151 | done: | |
1152 | spin_unlock_irqrestore(&uhci->lock, flags); | |
1153 | return 0; | |
1154 | } | |
1155 | ||
1da177e4 | 1156 | /* |
0ed8fee1 | 1157 | * Finish unlinking an URB and give it back |
1da177e4 | 1158 | */ |
0ed8fee1 AS |
1159 | static void uhci_giveback_urb(struct uhci_hcd *uhci, struct uhci_qh *qh, |
1160 | struct urb *urb, struct pt_regs *regs) | |
1161 | __releases(uhci->lock) | |
1162 | __acquires(uhci->lock) | |
1da177e4 | 1163 | { |
dccf4a48 | 1164 | struct urb_priv *urbp = (struct urb_priv *) urb->hcpriv; |
1da177e4 | 1165 | |
0ed8fee1 | 1166 | /* Isochronous TDs get unlinked directly from the frame list */ |
4de7d2c2 | 1167 | if (qh->type == USB_ENDPOINT_XFER_ISOC) |
0ed8fee1 | 1168 | uhci_unlink_isochronous_tds(uhci, urb); |
1da177e4 | 1169 | |
0ed8fee1 AS |
1170 | /* Take the URB off the QH's queue. If the queue is now empty, |
1171 | * this is a perfect time for a toggle fixup. */ | |
1172 | list_del_init(&urbp->node); | |
1173 | if (list_empty(&qh->queue) && qh->needs_fixup) { | |
1174 | usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe), | |
1175 | usb_pipeout(urb->pipe), qh->initial_toggle); | |
1176 | qh->needs_fixup = 0; | |
1177 | } | |
1178 | ||
0ed8fee1 | 1179 | uhci_free_urb_priv(uhci, urbp); |
1da177e4 | 1180 | |
4de7d2c2 AS |
1181 | switch (qh->type) { |
1182 | case USB_ENDPOINT_XFER_ISOC: | |
1da177e4 LT |
1183 | /* Release bandwidth for Interrupt or Isoc. transfers */ |
1184 | if (urb->bandwidth) | |
1185 | usb_release_bandwidth(urb->dev, urb, 1); | |
1da177e4 | 1186 | break; |
4de7d2c2 | 1187 | case USB_ENDPOINT_XFER_INT: |
1da177e4 LT |
1188 | /* Release bandwidth for Interrupt or Isoc. transfers */ |
1189 | /* Make sure we don't release if we have a queued URB */ | |
0ed8fee1 | 1190 | if (list_empty(&qh->queue) && urb->bandwidth) |
1da177e4 LT |
1191 | usb_release_bandwidth(urb->dev, urb, 0); |
1192 | else | |
1193 | /* bandwidth was passed on to queued URB, */ | |
1194 | /* so don't let usb_unlink_urb() release it */ | |
1195 | urb->bandwidth = 0; | |
1da177e4 | 1196 | break; |
1da177e4 LT |
1197 | } |
1198 | ||
0ed8fee1 AS |
1199 | spin_unlock(&uhci->lock); |
1200 | usb_hcd_giveback_urb(uhci_to_hcd(uhci), urb, regs); | |
1201 | spin_lock(&uhci->lock); | |
1da177e4 | 1202 | |
0ed8fee1 AS |
1203 | /* If the queue is now empty, we can unlink the QH and give up its |
1204 | * reserved bandwidth. */ | |
1205 | if (list_empty(&qh->queue)) { | |
1206 | uhci_unlink_qh(uhci, qh); | |
1da177e4 | 1207 | |
0ed8fee1 AS |
1208 | /* Bandwidth stuff not yet implemented */ |
1209 | } | |
dccf4a48 | 1210 | } |
1da177e4 | 1211 | |
dccf4a48 | 1212 | /* |
0ed8fee1 | 1213 | * Scan the URBs in a QH's queue |
dccf4a48 | 1214 | */ |
0ed8fee1 AS |
1215 | #define QH_FINISHED_UNLINKING(qh) \ |
1216 | (qh->state == QH_STATE_UNLINKING && \ | |
1217 | uhci->frame_number + uhci->is_stopped != qh->unlink_frame) | |
1da177e4 | 1218 | |
0ed8fee1 AS |
1219 | static void uhci_scan_qh(struct uhci_hcd *uhci, struct uhci_qh *qh, |
1220 | struct pt_regs *regs) | |
1da177e4 | 1221 | { |
1da177e4 | 1222 | struct urb_priv *urbp; |
0ed8fee1 AS |
1223 | struct urb *urb; |
1224 | int status; | |
1da177e4 | 1225 | |
0ed8fee1 AS |
1226 | while (!list_empty(&qh->queue)) { |
1227 | urbp = list_entry(qh->queue.next, struct urb_priv, node); | |
1228 | urb = urbp->urb; | |
1da177e4 | 1229 | |
b1869000 | 1230 | if (qh->type == USB_ENDPOINT_XFER_ISOC) |
0ed8fee1 | 1231 | status = uhci_result_isochronous(uhci, urb); |
b1869000 | 1232 | else |
0ed8fee1 | 1233 | status = uhci_result_common(uhci, urb); |
0ed8fee1 AS |
1234 | if (status == -EINPROGRESS) |
1235 | break; | |
1da177e4 | 1236 | |
0ed8fee1 AS |
1237 | spin_lock(&urb->lock); |
1238 | if (urb->status == -EINPROGRESS) /* Not dequeued */ | |
1239 | urb->status = status; | |
1240 | else | |
2775562a | 1241 | status = ECONNRESET; /* Not -ECONNRESET */ |
0ed8fee1 | 1242 | spin_unlock(&urb->lock); |
1da177e4 | 1243 | |
0ed8fee1 AS |
1244 | /* Dequeued but completed URBs can't be given back unless |
1245 | * the QH is stopped or has finished unlinking. */ | |
2775562a AS |
1246 | if (status == ECONNRESET) { |
1247 | if (QH_FINISHED_UNLINKING(qh)) | |
1248 | qh->is_stopped = 1; | |
1249 | else if (!qh->is_stopped) | |
1250 | return; | |
1251 | } | |
1da177e4 | 1252 | |
0ed8fee1 | 1253 | uhci_giveback_urb(uhci, qh, urb, regs); |
2775562a | 1254 | if (status < 0) |
0ed8fee1 AS |
1255 | break; |
1256 | } | |
1da177e4 | 1257 | |
0ed8fee1 AS |
1258 | /* If the QH is neither stopped nor finished unlinking (normal case), |
1259 | * our work here is done. */ | |
2775562a AS |
1260 | if (QH_FINISHED_UNLINKING(qh)) |
1261 | qh->is_stopped = 1; | |
1262 | else if (!qh->is_stopped) | |
0ed8fee1 | 1263 | return; |
1da177e4 | 1264 | |
0ed8fee1 | 1265 | /* Otherwise give back each of the dequeued URBs */ |
2775562a | 1266 | restart: |
0ed8fee1 AS |
1267 | list_for_each_entry(urbp, &qh->queue, node) { |
1268 | urb = urbp->urb; | |
1269 | if (urb->status != -EINPROGRESS) { | |
10b8e47d AS |
1270 | |
1271 | /* Fix up the TD links and save the toggles for | |
1272 | * non-Isochronous queues. For Isochronous queues, | |
1273 | * test for too-recent dequeues. */ | |
1274 | if (!uhci_cleanup_queue(uhci, qh, urb)) { | |
1275 | qh->is_stopped = 0; | |
1276 | return; | |
1277 | } | |
0ed8fee1 AS |
1278 | uhci_giveback_urb(uhci, qh, urb, regs); |
1279 | goto restart; | |
1280 | } | |
1281 | } | |
1282 | qh->is_stopped = 0; | |
1da177e4 | 1283 | |
0ed8fee1 AS |
1284 | /* There are no more dequeued URBs. If there are still URBs on the |
1285 | * queue, the QH can now be re-activated. */ | |
1286 | if (!list_empty(&qh->queue)) { | |
1287 | if (qh->needs_fixup) | |
1288 | uhci_fixup_toggles(qh, 0); | |
84afddd7 AS |
1289 | |
1290 | /* If the first URB on the queue wants FSBR but its time | |
1291 | * limit has expired, set the next TD to interrupt on | |
1292 | * completion before reactivating the QH. */ | |
1293 | urbp = list_entry(qh->queue.next, struct urb_priv, node); | |
1294 | if (urbp->fsbr && qh->wait_expired) { | |
1295 | struct uhci_td *td = list_entry(urbp->td_list.next, | |
1296 | struct uhci_td, list); | |
1297 | ||
1298 | td->status |= __cpu_to_le32(TD_CTRL_IOC); | |
1299 | } | |
1300 | ||
0ed8fee1 | 1301 | uhci_activate_qh(uhci, qh); |
1da177e4 LT |
1302 | } |
1303 | ||
0ed8fee1 AS |
1304 | /* The queue is empty. The QH can become idle if it is fully |
1305 | * unlinked. */ | |
1306 | else if (QH_FINISHED_UNLINKING(qh)) | |
1307 | uhci_make_qh_idle(uhci, qh); | |
1da177e4 LT |
1308 | } |
1309 | ||
84afddd7 AS |
1310 | /* |
1311 | * Check for queues that have made some forward progress. | |
1312 | * Returns 0 if the queue is not Isochronous, is ACTIVE, and | |
1313 | * has not advanced since last examined; 1 otherwise. | |
b761d9d8 AS |
1314 | * |
1315 | * Early Intel controllers have a bug which causes qh->element sometimes | |
1316 | * not to advance when a TD completes successfully. The queue remains | |
1317 | * stuck on the inactive completed TD. We detect such cases and advance | |
1318 | * the element pointer by hand. | |
84afddd7 AS |
1319 | */ |
1320 | static int uhci_advance_check(struct uhci_hcd *uhci, struct uhci_qh *qh) | |
1321 | { | |
1322 | struct urb_priv *urbp = NULL; | |
1323 | struct uhci_td *td; | |
1324 | int ret = 1; | |
1325 | unsigned status; | |
1326 | ||
1327 | if (qh->type == USB_ENDPOINT_XFER_ISOC) | |
1328 | return ret; | |
1329 | ||
1330 | /* Treat an UNLINKING queue as though it hasn't advanced. | |
1331 | * This is okay because reactivation will treat it as though | |
1332 | * it has advanced, and if it is going to become IDLE then | |
1333 | * this doesn't matter anyway. Furthermore it's possible | |
1334 | * for an UNLINKING queue not to have any URBs at all, or | |
1335 | * for its first URB not to have any TDs (if it was dequeued | |
1336 | * just as it completed). So it's not easy in any case to | |
1337 | * test whether such queues have advanced. */ | |
1338 | if (qh->state != QH_STATE_ACTIVE) { | |
1339 | urbp = NULL; | |
1340 | status = 0; | |
1341 | ||
1342 | } else { | |
1343 | urbp = list_entry(qh->queue.next, struct urb_priv, node); | |
1344 | td = list_entry(urbp->td_list.next, struct uhci_td, list); | |
1345 | status = td_status(td); | |
1346 | if (!(status & TD_CTRL_ACTIVE)) { | |
1347 | ||
1348 | /* We're okay, the queue has advanced */ | |
1349 | qh->wait_expired = 0; | |
1350 | qh->advance_jiffies = jiffies; | |
1351 | return ret; | |
1352 | } | |
1353 | ret = 0; | |
1354 | } | |
1355 | ||
1356 | /* The queue hasn't advanced; check for timeout */ | |
1357 | if (!qh->wait_expired && time_after(jiffies, | |
1358 | qh->advance_jiffies + QH_WAIT_TIMEOUT)) { | |
b761d9d8 AS |
1359 | |
1360 | /* Detect the Intel bug and work around it */ | |
1361 | if (qh->post_td && qh_element(qh) == | |
1362 | cpu_to_le32(qh->post_td->dma_handle)) { | |
1363 | qh->element = qh->post_td->link; | |
1364 | qh->advance_jiffies = jiffies; | |
1365 | return 1; | |
1366 | } | |
1367 | ||
84afddd7 AS |
1368 | qh->wait_expired = 1; |
1369 | ||
1370 | /* If the current URB wants FSBR, unlink it temporarily | |
1371 | * so that we can safely set the next TD to interrupt on | |
1372 | * completion. That way we'll know as soon as the queue | |
1373 | * starts moving again. */ | |
1374 | if (urbp && urbp->fsbr && !(status & TD_CTRL_IOC)) | |
1375 | uhci_unlink_qh(uhci, qh); | |
1376 | } | |
1377 | return ret; | |
1378 | } | |
1379 | ||
0ed8fee1 AS |
1380 | /* |
1381 | * Process events in the schedule, but only in one thread at a time | |
1382 | */ | |
1da177e4 LT |
1383 | static void uhci_scan_schedule(struct uhci_hcd *uhci, struct pt_regs *regs) |
1384 | { | |
0ed8fee1 AS |
1385 | int i; |
1386 | struct uhci_qh *qh; | |
1da177e4 LT |
1387 | |
1388 | /* Don't allow re-entrant calls */ | |
1389 | if (uhci->scan_in_progress) { | |
1390 | uhci->need_rescan = 1; | |
1391 | return; | |
1392 | } | |
1393 | uhci->scan_in_progress = 1; | |
84afddd7 | 1394 | rescan: |
1da177e4 LT |
1395 | uhci->need_rescan = 0; |
1396 | ||
6c1b445c | 1397 | uhci_clear_next_interrupt(uhci); |
1da177e4 LT |
1398 | uhci_get_current_frame_number(uhci); |
1399 | ||
0ed8fee1 AS |
1400 | /* Go through all the QH queues and process the URBs in each one */ |
1401 | for (i = 0; i < UHCI_NUM_SKELQH - 1; ++i) { | |
1402 | uhci->next_qh = list_entry(uhci->skelqh[i]->node.next, | |
1403 | struct uhci_qh, node); | |
1404 | while ((qh = uhci->next_qh) != uhci->skelqh[i]) { | |
1405 | uhci->next_qh = list_entry(qh->node.next, | |
1406 | struct uhci_qh, node); | |
84afddd7 AS |
1407 | |
1408 | if (uhci_advance_check(uhci, qh)) { | |
1409 | uhci_scan_qh(uhci, qh, regs); | |
1410 | if (qh->state == QH_STATE_ACTIVE) | |
1411 | uhci_qh_wants_fsbr(uhci, qh); | |
1412 | } | |
0ed8fee1 | 1413 | } |
1da177e4 | 1414 | } |
1da177e4 LT |
1415 | |
1416 | if (uhci->need_rescan) | |
1417 | goto rescan; | |
1418 | uhci->scan_in_progress = 0; | |
1419 | ||
84afddd7 AS |
1420 | if (uhci->fsbr_is_on && time_after(jiffies, |
1421 | uhci->fsbr_jiffies + FSBR_OFF_DELAY)) | |
1422 | uhci_fsbr_off(uhci); | |
1423 | ||
04538a25 | 1424 | if (list_empty(&uhci->skel_unlink_qh->node)) |
1da177e4 LT |
1425 | uhci_clear_next_interrupt(uhci); |
1426 | else | |
1427 | uhci_set_next_interrupt(uhci); | |
1da177e4 | 1428 | } |