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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Universal Host Controller Interface driver for USB. | |
3 | * | |
4 | * Maintainer: Alan Stern <stern@rowland.harvard.edu> | |
5 | * | |
6 | * (C) Copyright 1999 Linus Torvalds | |
7 | * (C) Copyright 1999-2002 Johannes Erdfelt, johannes@erdfelt.com | |
8 | * (C) Copyright 1999 Randy Dunlap | |
9 | * (C) Copyright 1999 Georg Acher, acher@in.tum.de | |
10 | * (C) Copyright 1999 Deti Fliegl, deti@fliegl.de | |
11 | * (C) Copyright 1999 Thomas Sailer, sailer@ife.ee.ethz.ch | |
12 | * (C) Copyright 1999 Roman Weissgaerber, weissg@vienna.at | |
13 | * (C) Copyright 2000 Yggdrasil Computing, Inc. (port of new PCI interface | |
14 | * support from usb-ohci.c by Adam Richter, adam@yggdrasil.com). | |
15 | * (C) Copyright 1999 Gregory P. Smith (from usb-ohci.c) | |
b761d9d8 | 16 | * (C) Copyright 2004-2006 Alan Stern, stern@rowland.harvard.edu |
1da177e4 LT |
17 | */ |
18 | ||
1da177e4 LT |
19 | |
20 | /* | |
21 | * Technically, updating td->status here is a race, but it's not really a | |
22 | * problem. The worst that can happen is that we set the IOC bit again | |
23 | * generating a spurious interrupt. We could fix this by creating another | |
24 | * QH and leaving the IOC bit always set, but then we would have to play | |
25 | * games with the FSBR code to make sure we get the correct order in all | |
26 | * the cases. I don't think it's worth the effort | |
27 | */ | |
dccf4a48 | 28 | static void uhci_set_next_interrupt(struct uhci_hcd *uhci) |
1da177e4 | 29 | { |
6c1b445c | 30 | if (uhci->is_stopped) |
1f09df8b | 31 | mod_timer(&uhci_to_hcd(uhci)->rh_timer, jiffies); |
1da177e4 LT |
32 | uhci->term_td->status |= cpu_to_le32(TD_CTRL_IOC); |
33 | } | |
34 | ||
35 | static inline void uhci_clear_next_interrupt(struct uhci_hcd *uhci) | |
36 | { | |
37 | uhci->term_td->status &= ~cpu_to_le32(TD_CTRL_IOC); | |
38 | } | |
39 | ||
84afddd7 AS |
40 | |
41 | /* | |
42 | * Full-Speed Bandwidth Reclamation (FSBR). | |
43 | * We turn on FSBR whenever a queue that wants it is advancing, | |
44 | * and leave it on for a short time thereafter. | |
45 | */ | |
46 | static void uhci_fsbr_on(struct uhci_hcd *uhci) | |
47 | { | |
48 | uhci->fsbr_is_on = 1; | |
49 | uhci->skel_term_qh->link = cpu_to_le32( | |
50 | uhci->skel_fs_control_qh->dma_handle) | UHCI_PTR_QH; | |
51 | } | |
52 | ||
53 | static void uhci_fsbr_off(struct uhci_hcd *uhci) | |
54 | { | |
55 | uhci->fsbr_is_on = 0; | |
56 | uhci->skel_term_qh->link = UHCI_PTR_TERM; | |
57 | } | |
58 | ||
59 | static void uhci_add_fsbr(struct uhci_hcd *uhci, struct urb *urb) | |
60 | { | |
61 | struct urb_priv *urbp = urb->hcpriv; | |
62 | ||
63 | if (!(urb->transfer_flags & URB_NO_FSBR)) | |
64 | urbp->fsbr = 1; | |
65 | } | |
66 | ||
67 | static void uhci_qh_wants_fsbr(struct uhci_hcd *uhci, struct uhci_qh *qh) | |
68 | { | |
69 | struct urb_priv *urbp = | |
70 | list_entry(qh->queue.next, struct urb_priv, node); | |
71 | ||
72 | if (urbp->fsbr) { | |
73 | uhci->fsbr_jiffies = jiffies; | |
74 | if (!uhci->fsbr_is_on) | |
75 | uhci_fsbr_on(uhci); | |
76 | } | |
77 | } | |
78 | ||
79 | ||
2532178a | 80 | static struct uhci_td *uhci_alloc_td(struct uhci_hcd *uhci) |
1da177e4 LT |
81 | { |
82 | dma_addr_t dma_handle; | |
83 | struct uhci_td *td; | |
84 | ||
85 | td = dma_pool_alloc(uhci->td_pool, GFP_ATOMIC, &dma_handle); | |
86 | if (!td) | |
87 | return NULL; | |
88 | ||
89 | td->dma_handle = dma_handle; | |
1da177e4 | 90 | td->frame = -1; |
1da177e4 LT |
91 | |
92 | INIT_LIST_HEAD(&td->list); | |
1da177e4 LT |
93 | INIT_LIST_HEAD(&td->fl_list); |
94 | ||
1da177e4 LT |
95 | return td; |
96 | } | |
97 | ||
dccf4a48 AS |
98 | static void uhci_free_td(struct uhci_hcd *uhci, struct uhci_td *td) |
99 | { | |
100 | if (!list_empty(&td->list)) | |
101 | dev_warn(uhci_dev(uhci), "td %p still in list!\n", td); | |
dccf4a48 AS |
102 | if (!list_empty(&td->fl_list)) |
103 | dev_warn(uhci_dev(uhci), "td %p still in fl_list!\n", td); | |
104 | ||
105 | dma_pool_free(uhci->td_pool, td, td->dma_handle); | |
106 | } | |
107 | ||
1da177e4 LT |
108 | static inline void uhci_fill_td(struct uhci_td *td, u32 status, |
109 | u32 token, u32 buffer) | |
110 | { | |
111 | td->status = cpu_to_le32(status); | |
112 | td->token = cpu_to_le32(token); | |
113 | td->buffer = cpu_to_le32(buffer); | |
114 | } | |
115 | ||
04538a25 AS |
116 | static void uhci_add_td_to_urbp(struct uhci_td *td, struct urb_priv *urbp) |
117 | { | |
118 | list_add_tail(&td->list, &urbp->td_list); | |
119 | } | |
120 | ||
121 | static void uhci_remove_td_from_urbp(struct uhci_td *td) | |
122 | { | |
123 | list_del_init(&td->list); | |
124 | } | |
125 | ||
1da177e4 | 126 | /* |
687f5f34 | 127 | * We insert Isochronous URBs directly into the frame list at the beginning |
1da177e4 | 128 | */ |
dccf4a48 AS |
129 | static inline void uhci_insert_td_in_frame_list(struct uhci_hcd *uhci, |
130 | struct uhci_td *td, unsigned framenum) | |
1da177e4 LT |
131 | { |
132 | framenum &= (UHCI_NUMFRAMES - 1); | |
133 | ||
134 | td->frame = framenum; | |
135 | ||
136 | /* Is there a TD already mapped there? */ | |
a1d59ce8 | 137 | if (uhci->frame_cpu[framenum]) { |
1da177e4 LT |
138 | struct uhci_td *ftd, *ltd; |
139 | ||
a1d59ce8 | 140 | ftd = uhci->frame_cpu[framenum]; |
1da177e4 LT |
141 | ltd = list_entry(ftd->fl_list.prev, struct uhci_td, fl_list); |
142 | ||
143 | list_add_tail(&td->fl_list, &ftd->fl_list); | |
144 | ||
145 | td->link = ltd->link; | |
146 | wmb(); | |
147 | ltd->link = cpu_to_le32(td->dma_handle); | |
148 | } else { | |
a1d59ce8 | 149 | td->link = uhci->frame[framenum]; |
1da177e4 | 150 | wmb(); |
a1d59ce8 AS |
151 | uhci->frame[framenum] = cpu_to_le32(td->dma_handle); |
152 | uhci->frame_cpu[framenum] = td; | |
1da177e4 LT |
153 | } |
154 | } | |
155 | ||
dccf4a48 | 156 | static inline void uhci_remove_td_from_frame_list(struct uhci_hcd *uhci, |
b81d3436 | 157 | struct uhci_td *td) |
1da177e4 LT |
158 | { |
159 | /* If it's not inserted, don't remove it */ | |
b81d3436 AS |
160 | if (td->frame == -1) { |
161 | WARN_ON(!list_empty(&td->fl_list)); | |
1da177e4 | 162 | return; |
b81d3436 | 163 | } |
1da177e4 | 164 | |
b81d3436 | 165 | if (uhci->frame_cpu[td->frame] == td) { |
1da177e4 | 166 | if (list_empty(&td->fl_list)) { |
a1d59ce8 AS |
167 | uhci->frame[td->frame] = td->link; |
168 | uhci->frame_cpu[td->frame] = NULL; | |
1da177e4 LT |
169 | } else { |
170 | struct uhci_td *ntd; | |
171 | ||
172 | ntd = list_entry(td->fl_list.next, struct uhci_td, fl_list); | |
a1d59ce8 AS |
173 | uhci->frame[td->frame] = cpu_to_le32(ntd->dma_handle); |
174 | uhci->frame_cpu[td->frame] = ntd; | |
1da177e4 LT |
175 | } |
176 | } else { | |
177 | struct uhci_td *ptd; | |
178 | ||
179 | ptd = list_entry(td->fl_list.prev, struct uhci_td, fl_list); | |
180 | ptd->link = td->link; | |
181 | } | |
182 | ||
1da177e4 LT |
183 | list_del_init(&td->fl_list); |
184 | td->frame = -1; | |
185 | } | |
186 | ||
c8155cc5 AS |
187 | static inline void uhci_remove_tds_from_frame(struct uhci_hcd *uhci, |
188 | unsigned int framenum) | |
189 | { | |
190 | struct uhci_td *ftd, *ltd; | |
191 | ||
192 | framenum &= (UHCI_NUMFRAMES - 1); | |
193 | ||
194 | ftd = uhci->frame_cpu[framenum]; | |
195 | if (ftd) { | |
196 | ltd = list_entry(ftd->fl_list.prev, struct uhci_td, fl_list); | |
197 | uhci->frame[framenum] = ltd->link; | |
198 | uhci->frame_cpu[framenum] = NULL; | |
199 | ||
200 | while (!list_empty(&ftd->fl_list)) | |
201 | list_del_init(ftd->fl_list.prev); | |
202 | } | |
203 | } | |
204 | ||
dccf4a48 AS |
205 | /* |
206 | * Remove all the TDs for an Isochronous URB from the frame list | |
207 | */ | |
208 | static void uhci_unlink_isochronous_tds(struct uhci_hcd *uhci, struct urb *urb) | |
b81d3436 AS |
209 | { |
210 | struct urb_priv *urbp = (struct urb_priv *) urb->hcpriv; | |
211 | struct uhci_td *td; | |
212 | ||
213 | list_for_each_entry(td, &urbp->td_list, list) | |
dccf4a48 | 214 | uhci_remove_td_from_frame_list(uhci, td); |
b81d3436 AS |
215 | } |
216 | ||
dccf4a48 AS |
217 | static struct uhci_qh *uhci_alloc_qh(struct uhci_hcd *uhci, |
218 | struct usb_device *udev, struct usb_host_endpoint *hep) | |
1da177e4 LT |
219 | { |
220 | dma_addr_t dma_handle; | |
221 | struct uhci_qh *qh; | |
222 | ||
223 | qh = dma_pool_alloc(uhci->qh_pool, GFP_ATOMIC, &dma_handle); | |
224 | if (!qh) | |
225 | return NULL; | |
226 | ||
59e29ed9 | 227 | memset(qh, 0, sizeof(*qh)); |
1da177e4 LT |
228 | qh->dma_handle = dma_handle; |
229 | ||
230 | qh->element = UHCI_PTR_TERM; | |
231 | qh->link = UHCI_PTR_TERM; | |
232 | ||
dccf4a48 AS |
233 | INIT_LIST_HEAD(&qh->queue); |
234 | INIT_LIST_HEAD(&qh->node); | |
1da177e4 | 235 | |
dccf4a48 | 236 | if (udev) { /* Normal QH */ |
af0bb599 AS |
237 | qh->dummy_td = uhci_alloc_td(uhci); |
238 | if (!qh->dummy_td) { | |
239 | dma_pool_free(uhci->qh_pool, qh, dma_handle); | |
240 | return NULL; | |
241 | } | |
dccf4a48 AS |
242 | qh->state = QH_STATE_IDLE; |
243 | qh->hep = hep; | |
244 | qh->udev = udev; | |
245 | hep->hcpriv = qh; | |
4de7d2c2 | 246 | qh->type = hep->desc.bmAttributes & USB_ENDPOINT_XFERTYPE_MASK; |
1da177e4 | 247 | |
dccf4a48 AS |
248 | } else { /* Skeleton QH */ |
249 | qh->state = QH_STATE_ACTIVE; | |
4de7d2c2 | 250 | qh->type = -1; |
dccf4a48 | 251 | } |
1da177e4 LT |
252 | return qh; |
253 | } | |
254 | ||
255 | static void uhci_free_qh(struct uhci_hcd *uhci, struct uhci_qh *qh) | |
256 | { | |
dccf4a48 AS |
257 | WARN_ON(qh->state != QH_STATE_IDLE && qh->udev); |
258 | if (!list_empty(&qh->queue)) | |
1da177e4 | 259 | dev_warn(uhci_dev(uhci), "qh %p list not empty!\n", qh); |
1da177e4 | 260 | |
dccf4a48 AS |
261 | list_del(&qh->node); |
262 | if (qh->udev) { | |
263 | qh->hep->hcpriv = NULL; | |
af0bb599 | 264 | uhci_free_td(uhci, qh->dummy_td); |
dccf4a48 | 265 | } |
1da177e4 LT |
266 | dma_pool_free(uhci->qh_pool, qh, qh->dma_handle); |
267 | } | |
268 | ||
0ed8fee1 | 269 | /* |
a0b458b6 AS |
270 | * When a queue is stopped and a dequeued URB is given back, adjust |
271 | * the previous TD link (if the URB isn't first on the queue) or | |
272 | * save its toggle value (if it is first and is currently executing). | |
10b8e47d AS |
273 | * |
274 | * Returns 0 if the URB should not yet be given back, 1 otherwise. | |
0ed8fee1 | 275 | */ |
10b8e47d | 276 | static int uhci_cleanup_queue(struct uhci_hcd *uhci, struct uhci_qh *qh, |
a0b458b6 | 277 | struct urb *urb) |
0ed8fee1 | 278 | { |
a0b458b6 | 279 | struct urb_priv *urbp = urb->hcpriv; |
0ed8fee1 | 280 | struct uhci_td *td; |
10b8e47d | 281 | int ret = 1; |
0ed8fee1 | 282 | |
a0b458b6 | 283 | /* Isochronous pipes don't use toggles and their TD link pointers |
10b8e47d AS |
284 | * get adjusted during uhci_urb_dequeue(). But since their queues |
285 | * cannot truly be stopped, we have to watch out for dequeues | |
286 | * occurring after the nominal unlink frame. */ | |
287 | if (qh->type == USB_ENDPOINT_XFER_ISOC) { | |
288 | ret = (uhci->frame_number + uhci->is_stopped != | |
289 | qh->unlink_frame); | |
290 | return ret; | |
291 | } | |
a0b458b6 AS |
292 | |
293 | /* If the URB isn't first on its queue, adjust the link pointer | |
294 | * of the last TD in the previous URB. The toggle doesn't need | |
295 | * to be saved since this URB can't be executing yet. */ | |
296 | if (qh->queue.next != &urbp->node) { | |
297 | struct urb_priv *purbp; | |
298 | struct uhci_td *ptd; | |
299 | ||
300 | purbp = list_entry(urbp->node.prev, struct urb_priv, node); | |
301 | WARN_ON(list_empty(&purbp->td_list)); | |
302 | ptd = list_entry(purbp->td_list.prev, struct uhci_td, | |
303 | list); | |
304 | td = list_entry(urbp->td_list.prev, struct uhci_td, | |
305 | list); | |
306 | ptd->link = td->link; | |
10b8e47d | 307 | return ret; |
a0b458b6 AS |
308 | } |
309 | ||
0ed8fee1 AS |
310 | /* If the QH element pointer is UHCI_PTR_TERM then then currently |
311 | * executing URB has already been unlinked, so this one isn't it. */ | |
a0b458b6 | 312 | if (qh_element(qh) == UHCI_PTR_TERM) |
10b8e47d | 313 | return ret; |
0ed8fee1 AS |
314 | qh->element = UHCI_PTR_TERM; |
315 | ||
a0b458b6 AS |
316 | /* Control pipes have to worry about toggles */ |
317 | if (qh->type == USB_ENDPOINT_XFER_CONTROL) | |
10b8e47d | 318 | return ret; |
0ed8fee1 | 319 | |
a0b458b6 | 320 | /* Save the next toggle value */ |
59e29ed9 AS |
321 | WARN_ON(list_empty(&urbp->td_list)); |
322 | td = list_entry(urbp->td_list.next, struct uhci_td, list); | |
323 | qh->needs_fixup = 1; | |
324 | qh->initial_toggle = uhci_toggle(td_token(td)); | |
10b8e47d | 325 | return ret; |
0ed8fee1 AS |
326 | } |
327 | ||
328 | /* | |
329 | * Fix up the data toggles for URBs in a queue, when one of them | |
330 | * terminates early (short transfer, error, or dequeued). | |
331 | */ | |
332 | static void uhci_fixup_toggles(struct uhci_qh *qh, int skip_first) | |
333 | { | |
334 | struct urb_priv *urbp = NULL; | |
335 | struct uhci_td *td; | |
336 | unsigned int toggle = qh->initial_toggle; | |
337 | unsigned int pipe; | |
338 | ||
339 | /* Fixups for a short transfer start with the second URB in the | |
340 | * queue (the short URB is the first). */ | |
341 | if (skip_first) | |
342 | urbp = list_entry(qh->queue.next, struct urb_priv, node); | |
343 | ||
344 | /* When starting with the first URB, if the QH element pointer is | |
345 | * still valid then we know the URB's toggles are okay. */ | |
346 | else if (qh_element(qh) != UHCI_PTR_TERM) | |
347 | toggle = 2; | |
348 | ||
349 | /* Fix up the toggle for the URBs in the queue. Normally this | |
350 | * loop won't run more than once: When an error or short transfer | |
351 | * occurs, the queue usually gets emptied. */ | |
1393adb2 | 352 | urbp = list_prepare_entry(urbp, &qh->queue, node); |
0ed8fee1 AS |
353 | list_for_each_entry_continue(urbp, &qh->queue, node) { |
354 | ||
355 | /* If the first TD has the right toggle value, we don't | |
356 | * need to change any toggles in this URB */ | |
357 | td = list_entry(urbp->td_list.next, struct uhci_td, list); | |
358 | if (toggle > 1 || uhci_toggle(td_token(td)) == toggle) { | |
359 | td = list_entry(urbp->td_list.next, struct uhci_td, | |
360 | list); | |
361 | toggle = uhci_toggle(td_token(td)) ^ 1; | |
362 | ||
363 | /* Otherwise all the toggles in the URB have to be switched */ | |
364 | } else { | |
365 | list_for_each_entry(td, &urbp->td_list, list) { | |
366 | td->token ^= __constant_cpu_to_le32( | |
367 | TD_TOKEN_TOGGLE); | |
368 | toggle ^= 1; | |
369 | } | |
370 | } | |
371 | } | |
372 | ||
373 | wmb(); | |
374 | pipe = list_entry(qh->queue.next, struct urb_priv, node)->urb->pipe; | |
375 | usb_settoggle(qh->udev, usb_pipeendpoint(pipe), | |
376 | usb_pipeout(pipe), toggle); | |
377 | qh->needs_fixup = 0; | |
378 | } | |
379 | ||
1da177e4 | 380 | /* |
dccf4a48 | 381 | * Put a QH on the schedule in both hardware and software |
1da177e4 | 382 | */ |
dccf4a48 | 383 | static void uhci_activate_qh(struct uhci_hcd *uhci, struct uhci_qh *qh) |
1da177e4 | 384 | { |
dccf4a48 | 385 | struct uhci_qh *pqh; |
1da177e4 | 386 | |
dccf4a48 | 387 | WARN_ON(list_empty(&qh->queue)); |
1da177e4 | 388 | |
dccf4a48 AS |
389 | /* Set the element pointer if it isn't set already. |
390 | * This isn't needed for Isochronous queues, but it doesn't hurt. */ | |
391 | if (qh_element(qh) == UHCI_PTR_TERM) { | |
392 | struct urb_priv *urbp = list_entry(qh->queue.next, | |
393 | struct urb_priv, node); | |
394 | struct uhci_td *td = list_entry(urbp->td_list.next, | |
395 | struct uhci_td, list); | |
1da177e4 | 396 | |
dccf4a48 | 397 | qh->element = cpu_to_le32(td->dma_handle); |
1da177e4 LT |
398 | } |
399 | ||
84afddd7 AS |
400 | /* Treat the queue as if it has just advanced */ |
401 | qh->wait_expired = 0; | |
402 | qh->advance_jiffies = jiffies; | |
403 | ||
dccf4a48 AS |
404 | if (qh->state == QH_STATE_ACTIVE) |
405 | return; | |
406 | qh->state = QH_STATE_ACTIVE; | |
407 | ||
408 | /* Move the QH from its old list to the end of the appropriate | |
409 | * skeleton's list */ | |
0ed8fee1 AS |
410 | if (qh == uhci->next_qh) |
411 | uhci->next_qh = list_entry(qh->node.next, struct uhci_qh, | |
412 | node); | |
dccf4a48 AS |
413 | list_move_tail(&qh->node, &qh->skel->node); |
414 | ||
415 | /* Link it into the schedule */ | |
416 | pqh = list_entry(qh->node.prev, struct uhci_qh, node); | |
417 | qh->link = pqh->link; | |
418 | wmb(); | |
419 | pqh->link = UHCI_PTR_QH | cpu_to_le32(qh->dma_handle); | |
1da177e4 LT |
420 | } |
421 | ||
422 | /* | |
dccf4a48 | 423 | * Take a QH off the hardware schedule |
1da177e4 | 424 | */ |
dccf4a48 | 425 | static void uhci_unlink_qh(struct uhci_hcd *uhci, struct uhci_qh *qh) |
1da177e4 LT |
426 | { |
427 | struct uhci_qh *pqh; | |
1da177e4 | 428 | |
dccf4a48 | 429 | if (qh->state == QH_STATE_UNLINKING) |
1da177e4 | 430 | return; |
dccf4a48 AS |
431 | WARN_ON(qh->state != QH_STATE_ACTIVE || !qh->udev); |
432 | qh->state = QH_STATE_UNLINKING; | |
1da177e4 | 433 | |
dccf4a48 AS |
434 | /* Unlink the QH from the schedule and record when we did it */ |
435 | pqh = list_entry(qh->node.prev, struct uhci_qh, node); | |
436 | pqh->link = qh->link; | |
437 | mb(); | |
1da177e4 LT |
438 | |
439 | uhci_get_current_frame_number(uhci); | |
dccf4a48 | 440 | qh->unlink_frame = uhci->frame_number; |
1da177e4 | 441 | |
dccf4a48 AS |
442 | /* Force an interrupt so we know when the QH is fully unlinked */ |
443 | if (list_empty(&uhci->skel_unlink_qh->node)) | |
1da177e4 LT |
444 | uhci_set_next_interrupt(uhci); |
445 | ||
dccf4a48 | 446 | /* Move the QH from its old list to the end of the unlinking list */ |
0ed8fee1 AS |
447 | if (qh == uhci->next_qh) |
448 | uhci->next_qh = list_entry(qh->node.next, struct uhci_qh, | |
449 | node); | |
dccf4a48 | 450 | list_move_tail(&qh->node, &uhci->skel_unlink_qh->node); |
1da177e4 LT |
451 | } |
452 | ||
dccf4a48 AS |
453 | /* |
454 | * When we and the controller are through with a QH, it becomes IDLE. | |
455 | * This happens when a QH has been off the schedule (on the unlinking | |
456 | * list) for more than one frame, or when an error occurs while adding | |
457 | * the first URB onto a new QH. | |
458 | */ | |
459 | static void uhci_make_qh_idle(struct uhci_hcd *uhci, struct uhci_qh *qh) | |
1da177e4 | 460 | { |
dccf4a48 | 461 | WARN_ON(qh->state == QH_STATE_ACTIVE); |
1da177e4 | 462 | |
0ed8fee1 AS |
463 | if (qh == uhci->next_qh) |
464 | uhci->next_qh = list_entry(qh->node.next, struct uhci_qh, | |
465 | node); | |
dccf4a48 AS |
466 | list_move(&qh->node, &uhci->idle_qh_list); |
467 | qh->state = QH_STATE_IDLE; | |
1da177e4 | 468 | |
59e29ed9 AS |
469 | /* Now that the QH is idle, its post_td isn't being used */ |
470 | if (qh->post_td) { | |
471 | uhci_free_td(uhci, qh->post_td); | |
472 | qh->post_td = NULL; | |
473 | } | |
474 | ||
dccf4a48 AS |
475 | /* If anyone is waiting for a QH to become idle, wake them up */ |
476 | if (uhci->num_waiting) | |
477 | wake_up_all(&uhci->waitqh); | |
1da177e4 LT |
478 | } |
479 | ||
dccf4a48 AS |
480 | static inline struct urb_priv *uhci_alloc_urb_priv(struct uhci_hcd *uhci, |
481 | struct urb *urb) | |
1da177e4 LT |
482 | { |
483 | struct urb_priv *urbp; | |
484 | ||
485 | urbp = kmem_cache_alloc(uhci_up_cachep, SLAB_ATOMIC); | |
486 | if (!urbp) | |
487 | return NULL; | |
488 | ||
489 | memset((void *)urbp, 0, sizeof(*urbp)); | |
490 | ||
1da177e4 | 491 | urbp->urb = urb; |
dccf4a48 | 492 | urb->hcpriv = urbp; |
1da177e4 | 493 | |
dccf4a48 | 494 | INIT_LIST_HEAD(&urbp->node); |
1da177e4 | 495 | INIT_LIST_HEAD(&urbp->td_list); |
1da177e4 | 496 | |
1da177e4 LT |
497 | return urbp; |
498 | } | |
499 | ||
dccf4a48 AS |
500 | static void uhci_free_urb_priv(struct uhci_hcd *uhci, |
501 | struct urb_priv *urbp) | |
1da177e4 LT |
502 | { |
503 | struct uhci_td *td, *tmp; | |
1da177e4 | 504 | |
dccf4a48 AS |
505 | if (!list_empty(&urbp->node)) |
506 | dev_warn(uhci_dev(uhci), "urb %p still on QH's list!\n", | |
507 | urbp->urb); | |
1da177e4 | 508 | |
1da177e4 | 509 | list_for_each_entry_safe(td, tmp, &urbp->td_list, list) { |
04538a25 AS |
510 | uhci_remove_td_from_urbp(td); |
511 | uhci_free_td(uhci, td); | |
1da177e4 LT |
512 | } |
513 | ||
dccf4a48 | 514 | urbp->urb->hcpriv = NULL; |
1da177e4 LT |
515 | kmem_cache_free(uhci_up_cachep, urbp); |
516 | } | |
517 | ||
1da177e4 LT |
518 | /* |
519 | * Map status to standard result codes | |
520 | * | |
521 | * <status> is (td_status(td) & 0xF60000), a.k.a. | |
522 | * uhci_status_bits(td_status(td)). | |
523 | * Note: <status> does not include the TD_CTRL_NAK bit. | |
524 | * <dir_out> is True for output TDs and False for input TDs. | |
525 | */ | |
526 | static int uhci_map_status(int status, int dir_out) | |
527 | { | |
528 | if (!status) | |
529 | return 0; | |
530 | if (status & TD_CTRL_BITSTUFF) /* Bitstuff error */ | |
531 | return -EPROTO; | |
532 | if (status & TD_CTRL_CRCTIMEO) { /* CRC/Timeout */ | |
533 | if (dir_out) | |
534 | return -EPROTO; | |
535 | else | |
536 | return -EILSEQ; | |
537 | } | |
538 | if (status & TD_CTRL_BABBLE) /* Babble */ | |
539 | return -EOVERFLOW; | |
540 | if (status & TD_CTRL_DBUFERR) /* Buffer error */ | |
541 | return -ENOSR; | |
542 | if (status & TD_CTRL_STALLED) /* Stalled */ | |
543 | return -EPIPE; | |
1da177e4 LT |
544 | return 0; |
545 | } | |
546 | ||
547 | /* | |
548 | * Control transfers | |
549 | */ | |
dccf4a48 AS |
550 | static int uhci_submit_control(struct uhci_hcd *uhci, struct urb *urb, |
551 | struct uhci_qh *qh) | |
1da177e4 | 552 | { |
1da177e4 | 553 | struct uhci_td *td; |
1da177e4 | 554 | unsigned long destination, status; |
dccf4a48 | 555 | int maxsze = le16_to_cpu(qh->hep->desc.wMaxPacketSize); |
1da177e4 LT |
556 | int len = urb->transfer_buffer_length; |
557 | dma_addr_t data = urb->transfer_dma; | |
dccf4a48 | 558 | __le32 *plink; |
04538a25 | 559 | struct urb_priv *urbp = urb->hcpriv; |
1da177e4 LT |
560 | |
561 | /* The "pipe" thing contains the destination in bits 8--18 */ | |
562 | destination = (urb->pipe & PIPE_DEVEP_MASK) | USB_PID_SETUP; | |
563 | ||
af0bb599 AS |
564 | /* 3 errors, dummy TD remains inactive */ |
565 | status = uhci_maxerr(3); | |
1da177e4 LT |
566 | if (urb->dev->speed == USB_SPEED_LOW) |
567 | status |= TD_CTRL_LS; | |
568 | ||
569 | /* | |
570 | * Build the TD for the control request setup packet | |
571 | */ | |
af0bb599 | 572 | td = qh->dummy_td; |
04538a25 | 573 | uhci_add_td_to_urbp(td, urbp); |
fa346568 | 574 | uhci_fill_td(td, status, destination | uhci_explen(8), |
dccf4a48 AS |
575 | urb->setup_dma); |
576 | plink = &td->link; | |
af0bb599 | 577 | status |= TD_CTRL_ACTIVE; |
1da177e4 LT |
578 | |
579 | /* | |
580 | * If direction is "send", change the packet ID from SETUP (0x2D) | |
581 | * to OUT (0xE1). Else change it from SETUP to IN (0x69) and | |
582 | * set Short Packet Detect (SPD) for all data packets. | |
583 | */ | |
584 | if (usb_pipeout(urb->pipe)) | |
585 | destination ^= (USB_PID_SETUP ^ USB_PID_OUT); | |
586 | else { | |
587 | destination ^= (USB_PID_SETUP ^ USB_PID_IN); | |
588 | status |= TD_CTRL_SPD; | |
589 | } | |
590 | ||
591 | /* | |
687f5f34 | 592 | * Build the DATA TDs |
1da177e4 LT |
593 | */ |
594 | while (len > 0) { | |
dccf4a48 | 595 | int pktsze = min(len, maxsze); |
1da177e4 | 596 | |
2532178a | 597 | td = uhci_alloc_td(uhci); |
1da177e4 | 598 | if (!td) |
af0bb599 | 599 | goto nomem; |
dccf4a48 | 600 | *plink = cpu_to_le32(td->dma_handle); |
1da177e4 LT |
601 | |
602 | /* Alternate Data0/1 (start with Data1) */ | |
603 | destination ^= TD_TOKEN_TOGGLE; | |
604 | ||
04538a25 | 605 | uhci_add_td_to_urbp(td, urbp); |
fa346568 | 606 | uhci_fill_td(td, status, destination | uhci_explen(pktsze), |
dccf4a48 AS |
607 | data); |
608 | plink = &td->link; | |
1da177e4 LT |
609 | |
610 | data += pktsze; | |
611 | len -= pktsze; | |
612 | } | |
613 | ||
614 | /* | |
615 | * Build the final TD for control status | |
616 | */ | |
2532178a | 617 | td = uhci_alloc_td(uhci); |
1da177e4 | 618 | if (!td) |
af0bb599 | 619 | goto nomem; |
dccf4a48 | 620 | *plink = cpu_to_le32(td->dma_handle); |
1da177e4 LT |
621 | |
622 | /* | |
623 | * It's IN if the pipe is an output pipe or we're not expecting | |
624 | * data back. | |
625 | */ | |
626 | destination &= ~TD_TOKEN_PID_MASK; | |
627 | if (usb_pipeout(urb->pipe) || !urb->transfer_buffer_length) | |
628 | destination |= USB_PID_IN; | |
629 | else | |
630 | destination |= USB_PID_OUT; | |
631 | ||
632 | destination |= TD_TOKEN_TOGGLE; /* End in Data1 */ | |
633 | ||
634 | status &= ~TD_CTRL_SPD; | |
635 | ||
04538a25 | 636 | uhci_add_td_to_urbp(td, urbp); |
1da177e4 | 637 | uhci_fill_td(td, status | TD_CTRL_IOC, |
dccf4a48 | 638 | destination | uhci_explen(0), 0); |
af0bb599 AS |
639 | plink = &td->link; |
640 | ||
641 | /* | |
642 | * Build the new dummy TD and activate the old one | |
643 | */ | |
644 | td = uhci_alloc_td(uhci); | |
645 | if (!td) | |
646 | goto nomem; | |
647 | *plink = cpu_to_le32(td->dma_handle); | |
648 | ||
649 | uhci_fill_td(td, 0, USB_PID_OUT | uhci_explen(0), 0); | |
650 | wmb(); | |
651 | qh->dummy_td->status |= __constant_cpu_to_le32(TD_CTRL_ACTIVE); | |
652 | qh->dummy_td = td; | |
1da177e4 LT |
653 | |
654 | /* Low-speed transfers get a different queue, and won't hog the bus. | |
655 | * Also, some devices enumerate better without FSBR; the easiest way | |
656 | * to do that is to put URBs on the low-speed queue while the device | |
630aa3cf | 657 | * isn't in the CONFIGURED state. */ |
1da177e4 | 658 | if (urb->dev->speed == USB_SPEED_LOW || |
630aa3cf | 659 | urb->dev->state != USB_STATE_CONFIGURED) |
dccf4a48 | 660 | qh->skel = uhci->skel_ls_control_qh; |
1da177e4 | 661 | else { |
dccf4a48 | 662 | qh->skel = uhci->skel_fs_control_qh; |
84afddd7 | 663 | uhci_add_fsbr(uhci, urb); |
1da177e4 | 664 | } |
59e29ed9 AS |
665 | |
666 | urb->actual_length = -8; /* Account for the SETUP packet */ | |
dccf4a48 | 667 | return 0; |
af0bb599 AS |
668 | |
669 | nomem: | |
670 | /* Remove the dummy TD from the td_list so it doesn't get freed */ | |
04538a25 | 671 | uhci_remove_td_from_urbp(qh->dummy_td); |
af0bb599 | 672 | return -ENOMEM; |
1da177e4 LT |
673 | } |
674 | ||
1da177e4 LT |
675 | /* |
676 | * Common submit for bulk and interrupt | |
677 | */ | |
dccf4a48 AS |
678 | static int uhci_submit_common(struct uhci_hcd *uhci, struct urb *urb, |
679 | struct uhci_qh *qh) | |
1da177e4 LT |
680 | { |
681 | struct uhci_td *td; | |
1da177e4 | 682 | unsigned long destination, status; |
dccf4a48 | 683 | int maxsze = le16_to_cpu(qh->hep->desc.wMaxPacketSize); |
1da177e4 | 684 | int len = urb->transfer_buffer_length; |
1da177e4 | 685 | dma_addr_t data = urb->transfer_dma; |
af0bb599 | 686 | __le32 *plink; |
04538a25 | 687 | struct urb_priv *urbp = urb->hcpriv; |
af0bb599 | 688 | unsigned int toggle; |
1da177e4 LT |
689 | |
690 | if (len < 0) | |
691 | return -EINVAL; | |
692 | ||
693 | /* The "pipe" thing contains the destination in bits 8--18 */ | |
694 | destination = (urb->pipe & PIPE_DEVEP_MASK) | usb_packetid(urb->pipe); | |
af0bb599 AS |
695 | toggle = usb_gettoggle(urb->dev, usb_pipeendpoint(urb->pipe), |
696 | usb_pipeout(urb->pipe)); | |
1da177e4 | 697 | |
af0bb599 AS |
698 | /* 3 errors, dummy TD remains inactive */ |
699 | status = uhci_maxerr(3); | |
1da177e4 LT |
700 | if (urb->dev->speed == USB_SPEED_LOW) |
701 | status |= TD_CTRL_LS; | |
702 | if (usb_pipein(urb->pipe)) | |
703 | status |= TD_CTRL_SPD; | |
704 | ||
705 | /* | |
687f5f34 | 706 | * Build the DATA TDs |
1da177e4 | 707 | */ |
af0bb599 AS |
708 | plink = NULL; |
709 | td = qh->dummy_td; | |
1da177e4 LT |
710 | do { /* Allow zero length packets */ |
711 | int pktsze = maxsze; | |
712 | ||
dccf4a48 | 713 | if (len <= pktsze) { /* The last packet */ |
1da177e4 LT |
714 | pktsze = len; |
715 | if (!(urb->transfer_flags & URB_SHORT_NOT_OK)) | |
716 | status &= ~TD_CTRL_SPD; | |
717 | } | |
718 | ||
af0bb599 AS |
719 | if (plink) { |
720 | td = uhci_alloc_td(uhci); | |
721 | if (!td) | |
722 | goto nomem; | |
723 | *plink = cpu_to_le32(td->dma_handle); | |
724 | } | |
04538a25 | 725 | uhci_add_td_to_urbp(td, urbp); |
dccf4a48 | 726 | uhci_fill_td(td, status, |
af0bb599 AS |
727 | destination | uhci_explen(pktsze) | |
728 | (toggle << TD_TOKEN_TOGGLE_SHIFT), | |
729 | data); | |
dccf4a48 | 730 | plink = &td->link; |
af0bb599 | 731 | status |= TD_CTRL_ACTIVE; |
1da177e4 LT |
732 | |
733 | data += pktsze; | |
734 | len -= maxsze; | |
af0bb599 | 735 | toggle ^= 1; |
1da177e4 LT |
736 | } while (len > 0); |
737 | ||
738 | /* | |
739 | * URB_ZERO_PACKET means adding a 0-length packet, if direction | |
740 | * is OUT and the transfer_length was an exact multiple of maxsze, | |
741 | * hence (len = transfer_length - N * maxsze) == 0 | |
742 | * however, if transfer_length == 0, the zero packet was already | |
743 | * prepared above. | |
744 | */ | |
dccf4a48 AS |
745 | if ((urb->transfer_flags & URB_ZERO_PACKET) && |
746 | usb_pipeout(urb->pipe) && len == 0 && | |
747 | urb->transfer_buffer_length > 0) { | |
2532178a | 748 | td = uhci_alloc_td(uhci); |
1da177e4 | 749 | if (!td) |
af0bb599 | 750 | goto nomem; |
dccf4a48 | 751 | *plink = cpu_to_le32(td->dma_handle); |
1da177e4 | 752 | |
04538a25 | 753 | uhci_add_td_to_urbp(td, urbp); |
af0bb599 AS |
754 | uhci_fill_td(td, status, |
755 | destination | uhci_explen(0) | | |
756 | (toggle << TD_TOKEN_TOGGLE_SHIFT), | |
757 | data); | |
758 | plink = &td->link; | |
1da177e4 | 759 | |
af0bb599 | 760 | toggle ^= 1; |
1da177e4 LT |
761 | } |
762 | ||
763 | /* Set the interrupt-on-completion flag on the last packet. | |
764 | * A more-or-less typical 4 KB URB (= size of one memory page) | |
765 | * will require about 3 ms to transfer; that's a little on the | |
766 | * fast side but not enough to justify delaying an interrupt | |
767 | * more than 2 or 3 URBs, so we will ignore the URB_NO_INTERRUPT | |
768 | * flag setting. */ | |
dccf4a48 | 769 | td->status |= __constant_cpu_to_le32(TD_CTRL_IOC); |
1da177e4 | 770 | |
af0bb599 AS |
771 | /* |
772 | * Build the new dummy TD and activate the old one | |
773 | */ | |
774 | td = uhci_alloc_td(uhci); | |
775 | if (!td) | |
776 | goto nomem; | |
777 | *plink = cpu_to_le32(td->dma_handle); | |
778 | ||
779 | uhci_fill_td(td, 0, USB_PID_OUT | uhci_explen(0), 0); | |
780 | wmb(); | |
781 | qh->dummy_td->status |= __constant_cpu_to_le32(TD_CTRL_ACTIVE); | |
782 | qh->dummy_td = td; | |
caf3827a | 783 | qh->period = urb->interval; |
af0bb599 AS |
784 | |
785 | usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe), | |
786 | usb_pipeout(urb->pipe), toggle); | |
dccf4a48 | 787 | return 0; |
af0bb599 AS |
788 | |
789 | nomem: | |
790 | /* Remove the dummy TD from the td_list so it doesn't get freed */ | |
04538a25 | 791 | uhci_remove_td_from_urbp(qh->dummy_td); |
af0bb599 | 792 | return -ENOMEM; |
1da177e4 LT |
793 | } |
794 | ||
dccf4a48 AS |
795 | static inline int uhci_submit_bulk(struct uhci_hcd *uhci, struct urb *urb, |
796 | struct uhci_qh *qh) | |
1da177e4 LT |
797 | { |
798 | int ret; | |
799 | ||
800 | /* Can't have low-speed bulk transfers */ | |
801 | if (urb->dev->speed == USB_SPEED_LOW) | |
802 | return -EINVAL; | |
803 | ||
dccf4a48 AS |
804 | qh->skel = uhci->skel_bulk_qh; |
805 | ret = uhci_submit_common(uhci, urb, qh); | |
806 | if (ret == 0) | |
84afddd7 | 807 | uhci_add_fsbr(uhci, urb); |
1da177e4 LT |
808 | return ret; |
809 | } | |
810 | ||
caf3827a | 811 | static int uhci_submit_interrupt(struct uhci_hcd *uhci, struct urb *urb, |
dccf4a48 | 812 | struct uhci_qh *qh) |
1da177e4 | 813 | { |
caf3827a AS |
814 | int exponent; |
815 | ||
dccf4a48 AS |
816 | /* USB 1.1 interrupt transfers only involve one packet per interval. |
817 | * Drivers can submit URBs of any length, but longer ones will need | |
818 | * multiple intervals to complete. | |
1da177e4 | 819 | */ |
caf3827a AS |
820 | |
821 | /* Figure out which power-of-two queue to use */ | |
822 | for (exponent = 7; exponent >= 0; --exponent) { | |
823 | if ((1 << exponent) <= urb->interval) | |
824 | break; | |
825 | } | |
826 | if (exponent < 0) | |
827 | return -EINVAL; | |
828 | urb->interval = 1 << exponent; | |
829 | ||
830 | if (qh->period == 0) | |
831 | qh->skel = uhci->skelqh[UHCI_SKEL_INDEX(exponent)]; | |
832 | else if (qh->period != urb->interval) | |
833 | return -EINVAL; /* Can't change the period */ | |
834 | ||
dccf4a48 | 835 | return uhci_submit_common(uhci, urb, qh); |
1da177e4 LT |
836 | } |
837 | ||
b1869000 AS |
838 | /* |
839 | * Fix up the data structures following a short transfer | |
840 | */ | |
841 | static int uhci_fixup_short_transfer(struct uhci_hcd *uhci, | |
59e29ed9 | 842 | struct uhci_qh *qh, struct urb_priv *urbp) |
b1869000 AS |
843 | { |
844 | struct uhci_td *td; | |
59e29ed9 AS |
845 | struct list_head *tmp; |
846 | int ret; | |
b1869000 AS |
847 | |
848 | td = list_entry(urbp->td_list.prev, struct uhci_td, list); | |
849 | if (qh->type == USB_ENDPOINT_XFER_CONTROL) { | |
b1869000 AS |
850 | |
851 | /* When a control transfer is short, we have to restart | |
852 | * the queue at the status stage transaction, which is | |
853 | * the last TD. */ | |
59e29ed9 | 854 | WARN_ON(list_empty(&urbp->td_list)); |
b1869000 | 855 | qh->element = cpu_to_le32(td->dma_handle); |
59e29ed9 | 856 | tmp = td->list.prev; |
b1869000 AS |
857 | ret = -EINPROGRESS; |
858 | ||
59e29ed9 | 859 | } else { |
b1869000 AS |
860 | |
861 | /* When a bulk/interrupt transfer is short, we have to | |
862 | * fix up the toggles of the following URBs on the queue | |
863 | * before restarting the queue at the next URB. */ | |
59e29ed9 | 864 | qh->initial_toggle = uhci_toggle(td_token(qh->post_td)) ^ 1; |
b1869000 AS |
865 | uhci_fixup_toggles(qh, 1); |
866 | ||
59e29ed9 AS |
867 | if (list_empty(&urbp->td_list)) |
868 | td = qh->post_td; | |
b1869000 | 869 | qh->element = td->link; |
59e29ed9 AS |
870 | tmp = urbp->td_list.prev; |
871 | ret = 0; | |
b1869000 AS |
872 | } |
873 | ||
59e29ed9 AS |
874 | /* Remove all the TDs we skipped over, from tmp back to the start */ |
875 | while (tmp != &urbp->td_list) { | |
876 | td = list_entry(tmp, struct uhci_td, list); | |
877 | tmp = tmp->prev; | |
878 | ||
04538a25 AS |
879 | uhci_remove_td_from_urbp(td); |
880 | uhci_free_td(uhci, td); | |
59e29ed9 | 881 | } |
b1869000 AS |
882 | return ret; |
883 | } | |
884 | ||
885 | /* | |
886 | * Common result for control, bulk, and interrupt | |
887 | */ | |
888 | static int uhci_result_common(struct uhci_hcd *uhci, struct urb *urb) | |
889 | { | |
890 | struct urb_priv *urbp = urb->hcpriv; | |
891 | struct uhci_qh *qh = urbp->qh; | |
59e29ed9 | 892 | struct uhci_td *td, *tmp; |
b1869000 AS |
893 | unsigned status; |
894 | int ret = 0; | |
895 | ||
59e29ed9 | 896 | list_for_each_entry_safe(td, tmp, &urbp->td_list, list) { |
b1869000 AS |
897 | unsigned int ctrlstat; |
898 | int len; | |
899 | ||
b1869000 AS |
900 | ctrlstat = td_status(td); |
901 | status = uhci_status_bits(ctrlstat); | |
902 | if (status & TD_CTRL_ACTIVE) | |
903 | return -EINPROGRESS; | |
904 | ||
905 | len = uhci_actual_length(ctrlstat); | |
906 | urb->actual_length += len; | |
907 | ||
908 | if (status) { | |
909 | ret = uhci_map_status(status, | |
910 | uhci_packetout(td_token(td))); | |
911 | if ((debug == 1 && ret != -EPIPE) || debug > 1) { | |
912 | /* Some debugging code */ | |
913 | dev_dbg(uhci_dev(uhci), | |
914 | "%s: failed with status %x\n", | |
915 | __FUNCTION__, status); | |
916 | ||
917 | if (debug > 1 && errbuf) { | |
918 | /* Print the chain for debugging */ | |
919 | uhci_show_qh(urbp->qh, errbuf, | |
920 | ERRBUF_LEN, 0); | |
921 | lprintk(errbuf); | |
922 | } | |
923 | } | |
924 | ||
925 | } else if (len < uhci_expected_length(td_token(td))) { | |
926 | ||
927 | /* We received a short packet */ | |
928 | if (urb->transfer_flags & URB_SHORT_NOT_OK) | |
929 | ret = -EREMOTEIO; | |
930 | else if (ctrlstat & TD_CTRL_SPD) | |
931 | ret = 1; | |
932 | } | |
933 | ||
04538a25 | 934 | uhci_remove_td_from_urbp(td); |
59e29ed9 | 935 | if (qh->post_td) |
04538a25 | 936 | uhci_free_td(uhci, qh->post_td); |
59e29ed9 AS |
937 | qh->post_td = td; |
938 | ||
b1869000 AS |
939 | if (ret != 0) |
940 | goto err; | |
941 | } | |
942 | return ret; | |
943 | ||
944 | err: | |
945 | if (ret < 0) { | |
946 | /* In case a control transfer gets an error | |
947 | * during the setup stage */ | |
948 | urb->actual_length = max(urb->actual_length, 0); | |
949 | ||
950 | /* Note that the queue has stopped and save | |
951 | * the next toggle value */ | |
952 | qh->element = UHCI_PTR_TERM; | |
953 | qh->is_stopped = 1; | |
954 | qh->needs_fixup = (qh->type != USB_ENDPOINT_XFER_CONTROL); | |
955 | qh->initial_toggle = uhci_toggle(td_token(td)) ^ | |
956 | (ret == -EREMOTEIO); | |
957 | ||
958 | } else /* Short packet received */ | |
59e29ed9 | 959 | ret = uhci_fixup_short_transfer(uhci, qh, urbp); |
b1869000 AS |
960 | return ret; |
961 | } | |
962 | ||
1da177e4 LT |
963 | /* |
964 | * Isochronous transfers | |
965 | */ | |
0ed8fee1 AS |
966 | static int uhci_submit_isochronous(struct uhci_hcd *uhci, struct urb *urb, |
967 | struct uhci_qh *qh) | |
1da177e4 | 968 | { |
0ed8fee1 AS |
969 | struct uhci_td *td = NULL; /* Since urb->number_of_packets > 0 */ |
970 | int i, frame; | |
971 | unsigned long destination, status; | |
972 | struct urb_priv *urbp = (struct urb_priv *) urb->hcpriv; | |
1da177e4 | 973 | |
caf3827a AS |
974 | /* Values must not be too big (could overflow below) */ |
975 | if (urb->interval >= UHCI_NUMFRAMES || | |
976 | urb->number_of_packets >= UHCI_NUMFRAMES) | |
1da177e4 LT |
977 | return -EFBIG; |
978 | ||
caf3827a | 979 | /* Check the period and figure out the starting frame number */ |
caf3827a AS |
980 | if (qh->period == 0) { |
981 | if (urb->transfer_flags & URB_ISO_ASAP) { | |
c8155cc5 | 982 | uhci_get_current_frame_number(uhci); |
caf3827a AS |
983 | urb->start_frame = uhci->frame_number + 10; |
984 | } else { | |
c8155cc5 | 985 | i = urb->start_frame - uhci->last_iso_frame; |
caf3827a AS |
986 | if (i <= 0 || i >= UHCI_NUMFRAMES) |
987 | return -EINVAL; | |
988 | } | |
989 | } else if (qh->period != urb->interval) { | |
990 | return -EINVAL; /* Can't change the period */ | |
1da177e4 | 991 | |
caf3827a | 992 | } else { /* Pick up where the last URB leaves off */ |
0ed8fee1 | 993 | if (list_empty(&qh->queue)) { |
c8155cc5 | 994 | frame = qh->iso_frame; |
caf3827a AS |
995 | } else { |
996 | struct urb *lurb; | |
0ed8fee1 | 997 | |
caf3827a | 998 | lurb = list_entry(qh->queue.prev, |
0ed8fee1 | 999 | struct urb_priv, node)->urb; |
caf3827a AS |
1000 | frame = lurb->start_frame + |
1001 | lurb->number_of_packets * | |
1002 | lurb->interval; | |
0ed8fee1 | 1003 | } |
caf3827a AS |
1004 | if (urb->transfer_flags & URB_ISO_ASAP) |
1005 | urb->start_frame = frame; | |
c8155cc5 AS |
1006 | else if (urb->start_frame != frame) |
1007 | return -EINVAL; | |
1da177e4 | 1008 | } |
1da177e4 | 1009 | |
caf3827a | 1010 | /* Make sure we won't have to go too far into the future */ |
c8155cc5 | 1011 | if (uhci_frame_before_eq(uhci->last_iso_frame + UHCI_NUMFRAMES, |
caf3827a AS |
1012 | urb->start_frame + urb->number_of_packets * |
1013 | urb->interval)) | |
1014 | return -EFBIG; | |
1015 | ||
1016 | status = TD_CTRL_ACTIVE | TD_CTRL_IOS; | |
1017 | destination = (urb->pipe & PIPE_DEVEP_MASK) | usb_packetid(urb->pipe); | |
1018 | ||
b81d3436 | 1019 | for (i = 0; i < urb->number_of_packets; i++) { |
2532178a | 1020 | td = uhci_alloc_td(uhci); |
1da177e4 LT |
1021 | if (!td) |
1022 | return -ENOMEM; | |
1023 | ||
04538a25 | 1024 | uhci_add_td_to_urbp(td, urbp); |
dccf4a48 AS |
1025 | uhci_fill_td(td, status, destination | |
1026 | uhci_explen(urb->iso_frame_desc[i].length), | |
1027 | urb->transfer_dma + | |
1028 | urb->iso_frame_desc[i].offset); | |
b81d3436 | 1029 | } |
1da177e4 | 1030 | |
dccf4a48 AS |
1031 | /* Set the interrupt-on-completion flag on the last packet. */ |
1032 | td->status |= __constant_cpu_to_le32(TD_CTRL_IOC); | |
1033 | ||
1034 | qh->skel = uhci->skel_iso_qh; | |
caf3827a | 1035 | qh->period = urb->interval; |
dccf4a48 AS |
1036 | |
1037 | /* Add the TDs to the frame list */ | |
b81d3436 AS |
1038 | frame = urb->start_frame; |
1039 | list_for_each_entry(td, &urbp->td_list, list) { | |
dccf4a48 | 1040 | uhci_insert_td_in_frame_list(uhci, td, frame); |
c8155cc5 AS |
1041 | frame += qh->period; |
1042 | } | |
1043 | ||
1044 | if (list_empty(&qh->queue)) { | |
1045 | qh->iso_packet_desc = &urb->iso_frame_desc[0]; | |
1046 | qh->iso_frame = urb->start_frame; | |
1047 | qh->iso_status = 0; | |
1da177e4 LT |
1048 | } |
1049 | ||
dccf4a48 | 1050 | return 0; |
1da177e4 LT |
1051 | } |
1052 | ||
1053 | static int uhci_result_isochronous(struct uhci_hcd *uhci, struct urb *urb) | |
1054 | { | |
c8155cc5 AS |
1055 | struct uhci_td *td, *tmp; |
1056 | struct urb_priv *urbp = urb->hcpriv; | |
1057 | struct uhci_qh *qh = urbp->qh; | |
1da177e4 | 1058 | |
c8155cc5 AS |
1059 | list_for_each_entry_safe(td, tmp, &urbp->td_list, list) { |
1060 | unsigned int ctrlstat; | |
1061 | int status; | |
1da177e4 | 1062 | int actlength; |
1da177e4 | 1063 | |
c8155cc5 | 1064 | if (uhci_frame_before_eq(uhci->cur_iso_frame, qh->iso_frame)) |
1da177e4 LT |
1065 | return -EINPROGRESS; |
1066 | ||
c8155cc5 AS |
1067 | uhci_remove_tds_from_frame(uhci, qh->iso_frame); |
1068 | ||
1069 | ctrlstat = td_status(td); | |
1070 | if (ctrlstat & TD_CTRL_ACTIVE) { | |
1071 | status = -EXDEV; /* TD was added too late? */ | |
1072 | } else { | |
1073 | status = uhci_map_status(uhci_status_bits(ctrlstat), | |
1074 | usb_pipeout(urb->pipe)); | |
1075 | actlength = uhci_actual_length(ctrlstat); | |
1076 | ||
1077 | urb->actual_length += actlength; | |
1078 | qh->iso_packet_desc->actual_length = actlength; | |
1079 | qh->iso_packet_desc->status = status; | |
1080 | } | |
1da177e4 | 1081 | |
1da177e4 LT |
1082 | if (status) { |
1083 | urb->error_count++; | |
c8155cc5 | 1084 | qh->iso_status = status; |
1da177e4 LT |
1085 | } |
1086 | ||
c8155cc5 AS |
1087 | uhci_remove_td_from_urbp(td); |
1088 | uhci_free_td(uhci, td); | |
1089 | qh->iso_frame += qh->period; | |
1090 | ++qh->iso_packet_desc; | |
1da177e4 | 1091 | } |
c8155cc5 | 1092 | return qh->iso_status; |
1da177e4 LT |
1093 | } |
1094 | ||
1da177e4 | 1095 | static int uhci_urb_enqueue(struct usb_hcd *hcd, |
dccf4a48 | 1096 | struct usb_host_endpoint *hep, |
55016f10 | 1097 | struct urb *urb, gfp_t mem_flags) |
1da177e4 LT |
1098 | { |
1099 | int ret; | |
1100 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
1101 | unsigned long flags; | |
dccf4a48 AS |
1102 | struct urb_priv *urbp; |
1103 | struct uhci_qh *qh; | |
1da177e4 LT |
1104 | int bustime; |
1105 | ||
1106 | spin_lock_irqsave(&uhci->lock, flags); | |
1107 | ||
1108 | ret = urb->status; | |
1109 | if (ret != -EINPROGRESS) /* URB already unlinked! */ | |
dccf4a48 | 1110 | goto done; |
1da177e4 | 1111 | |
dccf4a48 AS |
1112 | ret = -ENOMEM; |
1113 | urbp = uhci_alloc_urb_priv(uhci, urb); | |
1114 | if (!urbp) | |
1115 | goto done; | |
1da177e4 | 1116 | |
dccf4a48 AS |
1117 | if (hep->hcpriv) |
1118 | qh = (struct uhci_qh *) hep->hcpriv; | |
1119 | else { | |
1120 | qh = uhci_alloc_qh(uhci, urb->dev, hep); | |
1121 | if (!qh) | |
1122 | goto err_no_qh; | |
1da177e4 | 1123 | } |
dccf4a48 | 1124 | urbp->qh = qh; |
1da177e4 | 1125 | |
4de7d2c2 AS |
1126 | switch (qh->type) { |
1127 | case USB_ENDPOINT_XFER_CONTROL: | |
dccf4a48 AS |
1128 | ret = uhci_submit_control(uhci, urb, qh); |
1129 | break; | |
4de7d2c2 | 1130 | case USB_ENDPOINT_XFER_BULK: |
dccf4a48 | 1131 | ret = uhci_submit_bulk(uhci, urb, qh); |
1da177e4 | 1132 | break; |
4de7d2c2 | 1133 | case USB_ENDPOINT_XFER_INT: |
dccf4a48 | 1134 | if (list_empty(&qh->queue)) { |
1da177e4 LT |
1135 | bustime = usb_check_bandwidth(urb->dev, urb); |
1136 | if (bustime < 0) | |
1137 | ret = bustime; | |
1138 | else { | |
dccf4a48 AS |
1139 | ret = uhci_submit_interrupt(uhci, urb, qh); |
1140 | if (ret == 0) | |
1da177e4 LT |
1141 | usb_claim_bandwidth(urb->dev, urb, bustime, 0); |
1142 | } | |
1143 | } else { /* inherit from parent */ | |
dccf4a48 AS |
1144 | struct urb_priv *eurbp; |
1145 | ||
1146 | eurbp = list_entry(qh->queue.prev, struct urb_priv, | |
1147 | node); | |
1148 | urb->bandwidth = eurbp->urb->bandwidth; | |
1149 | ret = uhci_submit_interrupt(uhci, urb, qh); | |
1da177e4 LT |
1150 | } |
1151 | break; | |
4de7d2c2 | 1152 | case USB_ENDPOINT_XFER_ISOC: |
c8155cc5 | 1153 | urb->error_count = 0; |
1da177e4 LT |
1154 | bustime = usb_check_bandwidth(urb->dev, urb); |
1155 | if (bustime < 0) { | |
1156 | ret = bustime; | |
1157 | break; | |
1158 | } | |
1159 | ||
dccf4a48 AS |
1160 | ret = uhci_submit_isochronous(uhci, urb, qh); |
1161 | if (ret == 0) | |
1da177e4 LT |
1162 | usb_claim_bandwidth(urb->dev, urb, bustime, 1); |
1163 | break; | |
1164 | } | |
dccf4a48 AS |
1165 | if (ret != 0) |
1166 | goto err_submit_failed; | |
1da177e4 | 1167 | |
dccf4a48 AS |
1168 | /* Add this URB to the QH */ |
1169 | urbp->qh = qh; | |
1170 | list_add_tail(&urbp->node, &qh->queue); | |
1da177e4 | 1171 | |
dccf4a48 AS |
1172 | /* If the new URB is the first and only one on this QH then either |
1173 | * the QH is new and idle or else it's unlinked and waiting to | |
2775562a AS |
1174 | * become idle, so we can activate it right away. But only if the |
1175 | * queue isn't stopped. */ | |
84afddd7 | 1176 | if (qh->queue.next == &urbp->node && !qh->is_stopped) { |
dccf4a48 | 1177 | uhci_activate_qh(uhci, qh); |
84afddd7 AS |
1178 | uhci_qh_wants_fsbr(uhci, qh); |
1179 | } | |
dccf4a48 AS |
1180 | goto done; |
1181 | ||
1182 | err_submit_failed: | |
1183 | if (qh->state == QH_STATE_IDLE) | |
1184 | uhci_make_qh_idle(uhci, qh); /* Reclaim unused QH */ | |
1da177e4 | 1185 | |
dccf4a48 AS |
1186 | err_no_qh: |
1187 | uhci_free_urb_priv(uhci, urbp); | |
1188 | ||
1189 | done: | |
1da177e4 LT |
1190 | spin_unlock_irqrestore(&uhci->lock, flags); |
1191 | return ret; | |
1192 | } | |
1193 | ||
0ed8fee1 AS |
1194 | static int uhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb) |
1195 | { | |
1196 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
1197 | unsigned long flags; | |
1198 | struct urb_priv *urbp; | |
10b8e47d | 1199 | struct uhci_qh *qh; |
0ed8fee1 AS |
1200 | |
1201 | spin_lock_irqsave(&uhci->lock, flags); | |
1202 | urbp = urb->hcpriv; | |
1203 | if (!urbp) /* URB was never linked! */ | |
1204 | goto done; | |
10b8e47d | 1205 | qh = urbp->qh; |
0ed8fee1 AS |
1206 | |
1207 | /* Remove Isochronous TDs from the frame list ASAP */ | |
10b8e47d | 1208 | if (qh->type == USB_ENDPOINT_XFER_ISOC) { |
0ed8fee1 | 1209 | uhci_unlink_isochronous_tds(uhci, urb); |
10b8e47d AS |
1210 | mb(); |
1211 | ||
1212 | /* If the URB has already started, update the QH unlink time */ | |
1213 | uhci_get_current_frame_number(uhci); | |
1214 | if (uhci_frame_before_eq(urb->start_frame, uhci->frame_number)) | |
1215 | qh->unlink_frame = uhci->frame_number; | |
1216 | } | |
1217 | ||
1218 | uhci_unlink_qh(uhci, qh); | |
0ed8fee1 AS |
1219 | |
1220 | done: | |
1221 | spin_unlock_irqrestore(&uhci->lock, flags); | |
1222 | return 0; | |
1223 | } | |
1224 | ||
1da177e4 | 1225 | /* |
0ed8fee1 | 1226 | * Finish unlinking an URB and give it back |
1da177e4 | 1227 | */ |
0ed8fee1 AS |
1228 | static void uhci_giveback_urb(struct uhci_hcd *uhci, struct uhci_qh *qh, |
1229 | struct urb *urb, struct pt_regs *regs) | |
1230 | __releases(uhci->lock) | |
1231 | __acquires(uhci->lock) | |
1da177e4 | 1232 | { |
dccf4a48 | 1233 | struct urb_priv *urbp = (struct urb_priv *) urb->hcpriv; |
1da177e4 | 1234 | |
c8155cc5 AS |
1235 | /* When giving back the first URB in an Isochronous queue, |
1236 | * reinitialize the QH's iso-related members for the next URB. */ | |
1237 | if (qh->type == USB_ENDPOINT_XFER_ISOC && | |
1238 | urbp->node.prev == &qh->queue && | |
1239 | urbp->node.next != &qh->queue) { | |
1240 | struct urb *nurb = list_entry(urbp->node.next, | |
1241 | struct urb_priv, node)->urb; | |
1242 | ||
1243 | qh->iso_packet_desc = &nurb->iso_frame_desc[0]; | |
1244 | qh->iso_frame = nurb->start_frame; | |
1245 | qh->iso_status = 0; | |
1246 | } | |
1da177e4 | 1247 | |
0ed8fee1 AS |
1248 | /* Take the URB off the QH's queue. If the queue is now empty, |
1249 | * this is a perfect time for a toggle fixup. */ | |
1250 | list_del_init(&urbp->node); | |
1251 | if (list_empty(&qh->queue) && qh->needs_fixup) { | |
1252 | usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe), | |
1253 | usb_pipeout(urb->pipe), qh->initial_toggle); | |
1254 | qh->needs_fixup = 0; | |
1255 | } | |
1256 | ||
0ed8fee1 | 1257 | uhci_free_urb_priv(uhci, urbp); |
1da177e4 | 1258 | |
4de7d2c2 AS |
1259 | switch (qh->type) { |
1260 | case USB_ENDPOINT_XFER_ISOC: | |
1da177e4 LT |
1261 | /* Release bandwidth for Interrupt or Isoc. transfers */ |
1262 | if (urb->bandwidth) | |
1263 | usb_release_bandwidth(urb->dev, urb, 1); | |
1da177e4 | 1264 | break; |
4de7d2c2 | 1265 | case USB_ENDPOINT_XFER_INT: |
1da177e4 LT |
1266 | /* Release bandwidth for Interrupt or Isoc. transfers */ |
1267 | /* Make sure we don't release if we have a queued URB */ | |
0ed8fee1 | 1268 | if (list_empty(&qh->queue) && urb->bandwidth) |
1da177e4 LT |
1269 | usb_release_bandwidth(urb->dev, urb, 0); |
1270 | else | |
1271 | /* bandwidth was passed on to queued URB, */ | |
1272 | /* so don't let usb_unlink_urb() release it */ | |
1273 | urb->bandwidth = 0; | |
1da177e4 | 1274 | break; |
1da177e4 LT |
1275 | } |
1276 | ||
0ed8fee1 AS |
1277 | spin_unlock(&uhci->lock); |
1278 | usb_hcd_giveback_urb(uhci_to_hcd(uhci), urb, regs); | |
1279 | spin_lock(&uhci->lock); | |
1da177e4 | 1280 | |
0ed8fee1 AS |
1281 | /* If the queue is now empty, we can unlink the QH and give up its |
1282 | * reserved bandwidth. */ | |
1283 | if (list_empty(&qh->queue)) { | |
1284 | uhci_unlink_qh(uhci, qh); | |
1da177e4 | 1285 | |
0ed8fee1 | 1286 | /* Bandwidth stuff not yet implemented */ |
caf3827a | 1287 | qh->period = 0; |
0ed8fee1 | 1288 | } |
dccf4a48 | 1289 | } |
1da177e4 | 1290 | |
dccf4a48 | 1291 | /* |
0ed8fee1 | 1292 | * Scan the URBs in a QH's queue |
dccf4a48 | 1293 | */ |
0ed8fee1 AS |
1294 | #define QH_FINISHED_UNLINKING(qh) \ |
1295 | (qh->state == QH_STATE_UNLINKING && \ | |
1296 | uhci->frame_number + uhci->is_stopped != qh->unlink_frame) | |
1da177e4 | 1297 | |
0ed8fee1 AS |
1298 | static void uhci_scan_qh(struct uhci_hcd *uhci, struct uhci_qh *qh, |
1299 | struct pt_regs *regs) | |
1da177e4 | 1300 | { |
1da177e4 | 1301 | struct urb_priv *urbp; |
0ed8fee1 AS |
1302 | struct urb *urb; |
1303 | int status; | |
1da177e4 | 1304 | |
0ed8fee1 AS |
1305 | while (!list_empty(&qh->queue)) { |
1306 | urbp = list_entry(qh->queue.next, struct urb_priv, node); | |
1307 | urb = urbp->urb; | |
1da177e4 | 1308 | |
b1869000 | 1309 | if (qh->type == USB_ENDPOINT_XFER_ISOC) |
0ed8fee1 | 1310 | status = uhci_result_isochronous(uhci, urb); |
b1869000 | 1311 | else |
0ed8fee1 | 1312 | status = uhci_result_common(uhci, urb); |
0ed8fee1 AS |
1313 | if (status == -EINPROGRESS) |
1314 | break; | |
1da177e4 | 1315 | |
0ed8fee1 AS |
1316 | spin_lock(&urb->lock); |
1317 | if (urb->status == -EINPROGRESS) /* Not dequeued */ | |
1318 | urb->status = status; | |
1319 | else | |
2775562a | 1320 | status = ECONNRESET; /* Not -ECONNRESET */ |
0ed8fee1 | 1321 | spin_unlock(&urb->lock); |
1da177e4 | 1322 | |
0ed8fee1 AS |
1323 | /* Dequeued but completed URBs can't be given back unless |
1324 | * the QH is stopped or has finished unlinking. */ | |
2775562a AS |
1325 | if (status == ECONNRESET) { |
1326 | if (QH_FINISHED_UNLINKING(qh)) | |
1327 | qh->is_stopped = 1; | |
1328 | else if (!qh->is_stopped) | |
1329 | return; | |
1330 | } | |
1da177e4 | 1331 | |
0ed8fee1 | 1332 | uhci_giveback_urb(uhci, qh, urb, regs); |
2775562a | 1333 | if (status < 0) |
0ed8fee1 AS |
1334 | break; |
1335 | } | |
1da177e4 | 1336 | |
0ed8fee1 AS |
1337 | /* If the QH is neither stopped nor finished unlinking (normal case), |
1338 | * our work here is done. */ | |
2775562a AS |
1339 | if (QH_FINISHED_UNLINKING(qh)) |
1340 | qh->is_stopped = 1; | |
1341 | else if (!qh->is_stopped) | |
0ed8fee1 | 1342 | return; |
1da177e4 | 1343 | |
0ed8fee1 | 1344 | /* Otherwise give back each of the dequeued URBs */ |
2775562a | 1345 | restart: |
0ed8fee1 AS |
1346 | list_for_each_entry(urbp, &qh->queue, node) { |
1347 | urb = urbp->urb; | |
1348 | if (urb->status != -EINPROGRESS) { | |
10b8e47d AS |
1349 | |
1350 | /* Fix up the TD links and save the toggles for | |
1351 | * non-Isochronous queues. For Isochronous queues, | |
1352 | * test for too-recent dequeues. */ | |
1353 | if (!uhci_cleanup_queue(uhci, qh, urb)) { | |
1354 | qh->is_stopped = 0; | |
1355 | return; | |
1356 | } | |
0ed8fee1 AS |
1357 | uhci_giveback_urb(uhci, qh, urb, regs); |
1358 | goto restart; | |
1359 | } | |
1360 | } | |
1361 | qh->is_stopped = 0; | |
1da177e4 | 1362 | |
0ed8fee1 AS |
1363 | /* There are no more dequeued URBs. If there are still URBs on the |
1364 | * queue, the QH can now be re-activated. */ | |
1365 | if (!list_empty(&qh->queue)) { | |
1366 | if (qh->needs_fixup) | |
1367 | uhci_fixup_toggles(qh, 0); | |
84afddd7 AS |
1368 | |
1369 | /* If the first URB on the queue wants FSBR but its time | |
1370 | * limit has expired, set the next TD to interrupt on | |
1371 | * completion before reactivating the QH. */ | |
1372 | urbp = list_entry(qh->queue.next, struct urb_priv, node); | |
1373 | if (urbp->fsbr && qh->wait_expired) { | |
1374 | struct uhci_td *td = list_entry(urbp->td_list.next, | |
1375 | struct uhci_td, list); | |
1376 | ||
1377 | td->status |= __cpu_to_le32(TD_CTRL_IOC); | |
1378 | } | |
1379 | ||
0ed8fee1 | 1380 | uhci_activate_qh(uhci, qh); |
1da177e4 LT |
1381 | } |
1382 | ||
0ed8fee1 AS |
1383 | /* The queue is empty. The QH can become idle if it is fully |
1384 | * unlinked. */ | |
1385 | else if (QH_FINISHED_UNLINKING(qh)) | |
1386 | uhci_make_qh_idle(uhci, qh); | |
1da177e4 LT |
1387 | } |
1388 | ||
84afddd7 AS |
1389 | /* |
1390 | * Check for queues that have made some forward progress. | |
1391 | * Returns 0 if the queue is not Isochronous, is ACTIVE, and | |
1392 | * has not advanced since last examined; 1 otherwise. | |
b761d9d8 AS |
1393 | * |
1394 | * Early Intel controllers have a bug which causes qh->element sometimes | |
1395 | * not to advance when a TD completes successfully. The queue remains | |
1396 | * stuck on the inactive completed TD. We detect such cases and advance | |
1397 | * the element pointer by hand. | |
84afddd7 AS |
1398 | */ |
1399 | static int uhci_advance_check(struct uhci_hcd *uhci, struct uhci_qh *qh) | |
1400 | { | |
1401 | struct urb_priv *urbp = NULL; | |
1402 | struct uhci_td *td; | |
1403 | int ret = 1; | |
1404 | unsigned status; | |
1405 | ||
1406 | if (qh->type == USB_ENDPOINT_XFER_ISOC) | |
1407 | return ret; | |
1408 | ||
1409 | /* Treat an UNLINKING queue as though it hasn't advanced. | |
1410 | * This is okay because reactivation will treat it as though | |
1411 | * it has advanced, and if it is going to become IDLE then | |
1412 | * this doesn't matter anyway. Furthermore it's possible | |
1413 | * for an UNLINKING queue not to have any URBs at all, or | |
1414 | * for its first URB not to have any TDs (if it was dequeued | |
1415 | * just as it completed). So it's not easy in any case to | |
1416 | * test whether such queues have advanced. */ | |
1417 | if (qh->state != QH_STATE_ACTIVE) { | |
1418 | urbp = NULL; | |
1419 | status = 0; | |
1420 | ||
1421 | } else { | |
1422 | urbp = list_entry(qh->queue.next, struct urb_priv, node); | |
1423 | td = list_entry(urbp->td_list.next, struct uhci_td, list); | |
1424 | status = td_status(td); | |
1425 | if (!(status & TD_CTRL_ACTIVE)) { | |
1426 | ||
1427 | /* We're okay, the queue has advanced */ | |
1428 | qh->wait_expired = 0; | |
1429 | qh->advance_jiffies = jiffies; | |
1430 | return ret; | |
1431 | } | |
1432 | ret = 0; | |
1433 | } | |
1434 | ||
1435 | /* The queue hasn't advanced; check for timeout */ | |
1436 | if (!qh->wait_expired && time_after(jiffies, | |
1437 | qh->advance_jiffies + QH_WAIT_TIMEOUT)) { | |
b761d9d8 AS |
1438 | |
1439 | /* Detect the Intel bug and work around it */ | |
1440 | if (qh->post_td && qh_element(qh) == | |
1441 | cpu_to_le32(qh->post_td->dma_handle)) { | |
1442 | qh->element = qh->post_td->link; | |
1443 | qh->advance_jiffies = jiffies; | |
1444 | return 1; | |
1445 | } | |
1446 | ||
84afddd7 AS |
1447 | qh->wait_expired = 1; |
1448 | ||
1449 | /* If the current URB wants FSBR, unlink it temporarily | |
1450 | * so that we can safely set the next TD to interrupt on | |
1451 | * completion. That way we'll know as soon as the queue | |
1452 | * starts moving again. */ | |
1453 | if (urbp && urbp->fsbr && !(status & TD_CTRL_IOC)) | |
1454 | uhci_unlink_qh(uhci, qh); | |
1455 | } | |
1456 | return ret; | |
1457 | } | |
1458 | ||
0ed8fee1 AS |
1459 | /* |
1460 | * Process events in the schedule, but only in one thread at a time | |
1461 | */ | |
1da177e4 LT |
1462 | static void uhci_scan_schedule(struct uhci_hcd *uhci, struct pt_regs *regs) |
1463 | { | |
0ed8fee1 AS |
1464 | int i; |
1465 | struct uhci_qh *qh; | |
1da177e4 LT |
1466 | |
1467 | /* Don't allow re-entrant calls */ | |
1468 | if (uhci->scan_in_progress) { | |
1469 | uhci->need_rescan = 1; | |
1470 | return; | |
1471 | } | |
1472 | uhci->scan_in_progress = 1; | |
84afddd7 | 1473 | rescan: |
1da177e4 LT |
1474 | uhci->need_rescan = 0; |
1475 | ||
6c1b445c | 1476 | uhci_clear_next_interrupt(uhci); |
1da177e4 | 1477 | uhci_get_current_frame_number(uhci); |
c8155cc5 | 1478 | uhci->cur_iso_frame = uhci->frame_number; |
1da177e4 | 1479 | |
0ed8fee1 AS |
1480 | /* Go through all the QH queues and process the URBs in each one */ |
1481 | for (i = 0; i < UHCI_NUM_SKELQH - 1; ++i) { | |
1482 | uhci->next_qh = list_entry(uhci->skelqh[i]->node.next, | |
1483 | struct uhci_qh, node); | |
1484 | while ((qh = uhci->next_qh) != uhci->skelqh[i]) { | |
1485 | uhci->next_qh = list_entry(qh->node.next, | |
1486 | struct uhci_qh, node); | |
84afddd7 AS |
1487 | |
1488 | if (uhci_advance_check(uhci, qh)) { | |
1489 | uhci_scan_qh(uhci, qh, regs); | |
1490 | if (qh->state == QH_STATE_ACTIVE) | |
1491 | uhci_qh_wants_fsbr(uhci, qh); | |
1492 | } | |
0ed8fee1 | 1493 | } |
1da177e4 | 1494 | } |
1da177e4 | 1495 | |
c8155cc5 | 1496 | uhci->last_iso_frame = uhci->cur_iso_frame; |
1da177e4 LT |
1497 | if (uhci->need_rescan) |
1498 | goto rescan; | |
1499 | uhci->scan_in_progress = 0; | |
1500 | ||
84afddd7 AS |
1501 | if (uhci->fsbr_is_on && time_after(jiffies, |
1502 | uhci->fsbr_jiffies + FSBR_OFF_DELAY)) | |
1503 | uhci_fsbr_off(uhci); | |
1504 | ||
04538a25 | 1505 | if (list_empty(&uhci->skel_unlink_qh->node)) |
1da177e4 LT |
1506 | uhci_clear_next_interrupt(uhci); |
1507 | else | |
1508 | uhci_set_next_interrupt(uhci); | |
1da177e4 | 1509 | } |