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66d4eadd SS |
1 | /* |
2 | * xHCI host controller driver | |
3 | * | |
4 | * Copyright (C) 2008 Intel Corp. | |
5 | * | |
6 | * Author: Sarah Sharp | |
7 | * Some code borrowed from the Linux EHCI driver. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | * for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software Foundation, | |
20 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
23 | #include <linux/irq.h> | |
24 | #include <linux/module.h> | |
25 | ||
26 | #include "xhci.h" | |
27 | ||
28 | #define DRIVER_AUTHOR "Sarah Sharp" | |
29 | #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver" | |
30 | ||
31 | /* TODO: copied from ehci-hcd.c - can this be refactored? */ | |
32 | /* | |
33 | * handshake - spin reading hc until handshake completes or fails | |
34 | * @ptr: address of hc register to be read | |
35 | * @mask: bits to look at in result of read | |
36 | * @done: value of those bits when handshake succeeds | |
37 | * @usec: timeout in microseconds | |
38 | * | |
39 | * Returns negative errno, or zero on success | |
40 | * | |
41 | * Success happens when the "mask" bits have the specified value (hardware | |
42 | * handshake done). There are two failure modes: "usec" have passed (major | |
43 | * hardware flakeout), or the register reads as all-ones (hardware removed). | |
44 | */ | |
45 | static int handshake(struct xhci_hcd *xhci, void __iomem *ptr, | |
46 | u32 mask, u32 done, int usec) | |
47 | { | |
48 | u32 result; | |
49 | ||
50 | do { | |
51 | result = xhci_readl(xhci, ptr); | |
52 | if (result == ~(u32)0) /* card removed */ | |
53 | return -ENODEV; | |
54 | result &= mask; | |
55 | if (result == done) | |
56 | return 0; | |
57 | udelay(1); | |
58 | usec--; | |
59 | } while (usec > 0); | |
60 | return -ETIMEDOUT; | |
61 | } | |
62 | ||
63 | /* | |
64 | * Force HC into halt state. | |
65 | * | |
66 | * Disable any IRQs and clear the run/stop bit. | |
67 | * HC will complete any current and actively pipelined transactions, and | |
68 | * should halt within 16 microframes of the run/stop bit being cleared. | |
69 | * Read HC Halted bit in the status register to see when the HC is finished. | |
70 | * XXX: shouldn't we set HC_STATE_HALT here somewhere? | |
71 | */ | |
72 | int xhci_halt(struct xhci_hcd *xhci) | |
73 | { | |
74 | u32 halted; | |
75 | u32 cmd; | |
76 | u32 mask; | |
77 | ||
78 | xhci_dbg(xhci, "// Halt the HC\n"); | |
79 | /* Disable all interrupts from the host controller */ | |
80 | mask = ~(XHCI_IRQS); | |
81 | halted = xhci_readl(xhci, &xhci->op_regs->status) & STS_HALT; | |
82 | if (!halted) | |
83 | mask &= ~CMD_RUN; | |
84 | ||
85 | cmd = xhci_readl(xhci, &xhci->op_regs->command); | |
86 | cmd &= mask; | |
87 | xhci_writel(xhci, cmd, &xhci->op_regs->command); | |
88 | ||
89 | return handshake(xhci, &xhci->op_regs->status, | |
90 | STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC); | |
91 | } | |
92 | ||
93 | /* | |
94 | * Reset a halted HC, and set the internal HC state to HC_STATE_HALT. | |
95 | * | |
96 | * This resets pipelines, timers, counters, state machines, etc. | |
97 | * Transactions will be terminated immediately, and operational registers | |
98 | * will be set to their defaults. | |
99 | */ | |
100 | int xhci_reset(struct xhci_hcd *xhci) | |
101 | { | |
102 | u32 command; | |
103 | u32 state; | |
104 | ||
105 | state = xhci_readl(xhci, &xhci->op_regs->status); | |
106 | BUG_ON((state & STS_HALT) == 0); | |
107 | ||
108 | xhci_dbg(xhci, "// Reset the HC\n"); | |
109 | command = xhci_readl(xhci, &xhci->op_regs->command); | |
110 | command |= CMD_RESET; | |
111 | xhci_writel(xhci, command, &xhci->op_regs->command); | |
112 | /* XXX: Why does EHCI set this here? Shouldn't other code do this? */ | |
113 | xhci_to_hcd(xhci)->state = HC_STATE_HALT; | |
114 | ||
115 | return handshake(xhci, &xhci->op_regs->command, CMD_RESET, 0, 250 * 1000); | |
116 | } | |
117 | ||
118 | /* | |
119 | * Stop the HC from processing the endpoint queues. | |
120 | */ | |
121 | static void xhci_quiesce(struct xhci_hcd *xhci) | |
122 | { | |
123 | /* | |
124 | * Queues are per endpoint, so we need to disable an endpoint or slot. | |
125 | * | |
126 | * To disable a slot, we need to insert a disable slot command on the | |
127 | * command ring and ring the doorbell. This will also free any internal | |
128 | * resources associated with the slot (which might not be what we want). | |
129 | * | |
130 | * A Release Endpoint command sounds better - doesn't free internal HC | |
131 | * memory, but removes the endpoints from the schedule and releases the | |
132 | * bandwidth, disables the doorbells, and clears the endpoint enable | |
133 | * flag. Usually used prior to a set interface command. | |
134 | * | |
135 | * TODO: Implement after command ring code is done. | |
136 | */ | |
137 | BUG_ON(!HC_IS_RUNNING(xhci_to_hcd(xhci)->state)); | |
138 | xhci_dbg(xhci, "Finished quiescing -- code not written yet\n"); | |
139 | } | |
140 | ||
141 | #if 0 | |
142 | /* Set up MSI-X table for entry 0 (may claim other entries later) */ | |
143 | static int xhci_setup_msix(struct xhci_hcd *xhci) | |
144 | { | |
145 | int ret; | |
146 | struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller); | |
147 | ||
148 | xhci->msix_count = 0; | |
149 | /* XXX: did I do this right? ixgbe does kcalloc for more than one */ | |
150 | xhci->msix_entries = kmalloc(sizeof(struct msix_entry), GFP_KERNEL); | |
151 | if (!xhci->msix_entries) { | |
152 | xhci_err(xhci, "Failed to allocate MSI-X entries\n"); | |
153 | return -ENOMEM; | |
154 | } | |
155 | xhci->msix_entries[0].entry = 0; | |
156 | ||
157 | ret = pci_enable_msix(pdev, xhci->msix_entries, xhci->msix_count); | |
158 | if (ret) { | |
159 | xhci_err(xhci, "Failed to enable MSI-X\n"); | |
160 | goto free_entries; | |
161 | } | |
162 | ||
163 | /* | |
164 | * Pass the xhci pointer value as the request_irq "cookie". | |
165 | * If more irqs are added, this will need to be unique for each one. | |
166 | */ | |
167 | ret = request_irq(xhci->msix_entries[0].vector, &xhci_irq, 0, | |
168 | "xHCI", xhci_to_hcd(xhci)); | |
169 | if (ret) { | |
170 | xhci_err(xhci, "Failed to allocate MSI-X interrupt\n"); | |
171 | goto disable_msix; | |
172 | } | |
173 | xhci_dbg(xhci, "Finished setting up MSI-X\n"); | |
174 | return 0; | |
175 | ||
176 | disable_msix: | |
177 | pci_disable_msix(pdev); | |
178 | free_entries: | |
179 | kfree(xhci->msix_entries); | |
180 | xhci->msix_entries = NULL; | |
181 | return ret; | |
182 | } | |
183 | ||
184 | /* XXX: code duplication; can xhci_setup_msix call this? */ | |
185 | /* Free any IRQs and disable MSI-X */ | |
186 | static void xhci_cleanup_msix(struct xhci_hcd *xhci) | |
187 | { | |
188 | struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller); | |
189 | if (!xhci->msix_entries) | |
190 | return; | |
191 | ||
192 | free_irq(xhci->msix_entries[0].vector, xhci); | |
193 | pci_disable_msix(pdev); | |
194 | kfree(xhci->msix_entries); | |
195 | xhci->msix_entries = NULL; | |
196 | xhci_dbg(xhci, "Finished cleaning up MSI-X\n"); | |
197 | } | |
198 | #endif | |
199 | ||
200 | /* | |
201 | * Initialize memory for HCD and xHC (one-time init). | |
202 | * | |
203 | * Program the PAGESIZE register, initialize the device context array, create | |
204 | * device contexts (?), set up a command ring segment (or two?), create event | |
205 | * ring (one for now). | |
206 | */ | |
207 | int xhci_init(struct usb_hcd *hcd) | |
208 | { | |
209 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
210 | int retval = 0; | |
211 | ||
212 | xhci_dbg(xhci, "xhci_init\n"); | |
213 | spin_lock_init(&xhci->lock); | |
214 | retval = xhci_mem_init(xhci, GFP_KERNEL); | |
215 | xhci_dbg(xhci, "Finished xhci_init\n"); | |
216 | ||
217 | return retval; | |
218 | } | |
219 | ||
7f84eef0 SS |
220 | /* |
221 | * Called in interrupt context when there might be work | |
222 | * queued on the event ring | |
223 | * | |
224 | * xhci->lock must be held by caller. | |
225 | */ | |
226 | static void xhci_work(struct xhci_hcd *xhci) | |
227 | { | |
228 | u32 temp; | |
229 | ||
230 | /* | |
231 | * Clear the op reg interrupt status first, | |
232 | * so we can receive interrupts from other MSI-X interrupters. | |
233 | * Write 1 to clear the interrupt status. | |
234 | */ | |
235 | temp = xhci_readl(xhci, &xhci->op_regs->status); | |
236 | temp |= STS_EINT; | |
237 | xhci_writel(xhci, temp, &xhci->op_regs->status); | |
238 | /* FIXME when MSI-X is supported and there are multiple vectors */ | |
239 | /* Clear the MSI-X event interrupt status */ | |
240 | ||
241 | /* Acknowledge the interrupt */ | |
242 | temp = xhci_readl(xhci, &xhci->ir_set->irq_pending); | |
243 | temp |= 0x3; | |
244 | xhci_writel(xhci, temp, &xhci->ir_set->irq_pending); | |
245 | /* Flush posted writes */ | |
246 | xhci_readl(xhci, &xhci->ir_set->irq_pending); | |
247 | ||
248 | /* FIXME this should be a delayed service routine that clears the EHB */ | |
249 | handle_event(xhci); | |
250 | ||
251 | /* Clear the event handler busy flag; the event ring should be empty. */ | |
252 | temp = xhci_readl(xhci, &xhci->ir_set->erst_dequeue[0]); | |
253 | xhci_writel(xhci, temp & ~ERST_EHB, &xhci->ir_set->erst_dequeue[0]); | |
254 | /* Flush posted writes -- FIXME is this necessary? */ | |
255 | xhci_readl(xhci, &xhci->ir_set->irq_pending); | |
256 | } | |
257 | ||
258 | /*-------------------------------------------------------------------------*/ | |
259 | ||
260 | /* | |
261 | * xHCI spec says we can get an interrupt, and if the HC has an error condition, | |
262 | * we might get bad data out of the event ring. Section 4.10.2.7 has a list of | |
263 | * indicators of an event TRB error, but we check the status *first* to be safe. | |
264 | */ | |
265 | irqreturn_t xhci_irq(struct usb_hcd *hcd) | |
266 | { | |
267 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
268 | u32 temp, temp2; | |
269 | ||
270 | spin_lock(&xhci->lock); | |
271 | /* Check if the xHC generated the interrupt, or the irq is shared */ | |
272 | temp = xhci_readl(xhci, &xhci->op_regs->status); | |
273 | temp2 = xhci_readl(xhci, &xhci->ir_set->irq_pending); | |
274 | if (!(temp & STS_EINT) && !ER_IRQ_PENDING(temp2)) { | |
275 | spin_unlock(&xhci->lock); | |
276 | return IRQ_NONE; | |
277 | } | |
278 | ||
279 | temp = xhci_readl(xhci, &xhci->op_regs->status); | |
280 | if (temp & STS_FATAL) { | |
281 | xhci_warn(xhci, "WARNING: Host System Error\n"); | |
282 | xhci_halt(xhci); | |
283 | xhci_to_hcd(xhci)->state = HC_STATE_HALT; | |
284 | return -ESHUTDOWN; | |
285 | } | |
286 | ||
287 | xhci_work(xhci); | |
288 | spin_unlock(&xhci->lock); | |
289 | ||
290 | return IRQ_HANDLED; | |
291 | } | |
292 | ||
293 | #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING | |
294 | void event_ring_work(unsigned long arg) | |
295 | { | |
296 | unsigned long flags; | |
297 | int temp; | |
298 | struct xhci_hcd *xhci = (struct xhci_hcd *) arg; | |
299 | int i, j; | |
300 | ||
301 | xhci_dbg(xhci, "Poll event ring: %lu\n", jiffies); | |
302 | ||
303 | spin_lock_irqsave(&xhci->lock, flags); | |
304 | temp = xhci_readl(xhci, &xhci->op_regs->status); | |
305 | xhci_dbg(xhci, "op reg status = 0x%x\n", temp); | |
306 | temp = xhci_readl(xhci, &xhci->ir_set->irq_pending); | |
307 | xhci_dbg(xhci, "ir_set 0 pending = 0x%x\n", temp); | |
308 | xhci_dbg(xhci, "No-op commands handled = %d\n", xhci->noops_handled); | |
309 | xhci_dbg(xhci, "HC error bitmask = 0x%x\n", xhci->error_bitmask); | |
310 | xhci->error_bitmask = 0; | |
311 | xhci_dbg(xhci, "Event ring:\n"); | |
312 | xhci_debug_segment(xhci, xhci->event_ring->deq_seg); | |
313 | xhci_dbg_ring_ptrs(xhci, xhci->event_ring); | |
314 | temp = xhci_readl(xhci, &xhci->ir_set->erst_dequeue[0]); | |
315 | temp &= ERST_PTR_MASK; | |
316 | xhci_dbg(xhci, "ERST deq = 0x%x\n", temp); | |
317 | xhci_dbg(xhci, "Command ring:\n"); | |
318 | xhci_debug_segment(xhci, xhci->cmd_ring->deq_seg); | |
319 | xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring); | |
320 | xhci_dbg_cmd_ptrs(xhci); | |
3ffbba95 SS |
321 | for (i = 0; i < MAX_HC_SLOTS; ++i) { |
322 | if (xhci->devs[i]) { | |
323 | for (j = 0; j < 31; ++j) { | |
324 | if (xhci->devs[i]->ep_rings[j]) { | |
325 | xhci_dbg(xhci, "Dev %d endpoint ring %d:\n", i, j); | |
326 | xhci_debug_segment(xhci, xhci->devs[i]->ep_rings[j]->deq_seg); | |
327 | } | |
328 | } | |
329 | } | |
330 | } | |
7f84eef0 SS |
331 | |
332 | if (xhci->noops_submitted != NUM_TEST_NOOPS) | |
333 | if (setup_one_noop(xhci)) | |
334 | ring_cmd_db(xhci); | |
335 | spin_unlock_irqrestore(&xhci->lock, flags); | |
336 | ||
337 | if (!xhci->zombie) | |
338 | mod_timer(&xhci->event_ring_timer, jiffies + POLL_TIMEOUT * HZ); | |
339 | else | |
340 | xhci_dbg(xhci, "Quit polling the event ring.\n"); | |
341 | } | |
342 | #endif | |
343 | ||
66d4eadd SS |
344 | /* |
345 | * Start the HC after it was halted. | |
346 | * | |
347 | * This function is called by the USB core when the HC driver is added. | |
348 | * Its opposite is xhci_stop(). | |
349 | * | |
350 | * xhci_init() must be called once before this function can be called. | |
351 | * Reset the HC, enable device slot contexts, program DCBAAP, and | |
352 | * set command ring pointer and event ring pointer. | |
353 | * | |
354 | * Setup MSI-X vectors and enable interrupts. | |
355 | */ | |
356 | int xhci_run(struct usb_hcd *hcd) | |
357 | { | |
358 | u32 temp; | |
359 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
7f84eef0 | 360 | void (*doorbell)(struct xhci_hcd *) = NULL; |
66d4eadd | 361 | |
0f2a7930 SS |
362 | hcd->uses_new_polling = 1; |
363 | hcd->poll_rh = 0; | |
364 | ||
7f84eef0 | 365 | xhci_dbg(xhci, "xhci_run\n"); |
66d4eadd SS |
366 | #if 0 /* FIXME: MSI not setup yet */ |
367 | /* Do this at the very last minute */ | |
368 | ret = xhci_setup_msix(xhci); | |
369 | if (!ret) | |
370 | return ret; | |
371 | ||
372 | return -ENOSYS; | |
373 | #endif | |
7f84eef0 SS |
374 | #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING |
375 | init_timer(&xhci->event_ring_timer); | |
376 | xhci->event_ring_timer.data = (unsigned long) xhci; | |
377 | xhci->event_ring_timer.function = event_ring_work; | |
378 | /* Poll the event ring */ | |
379 | xhci->event_ring_timer.expires = jiffies + POLL_TIMEOUT * HZ; | |
380 | xhci->zombie = 0; | |
381 | xhci_dbg(xhci, "Setting event ring polling timer\n"); | |
382 | add_timer(&xhci->event_ring_timer); | |
383 | #endif | |
384 | ||
66d4eadd SS |
385 | xhci_dbg(xhci, "// Set the interrupt modulation register\n"); |
386 | temp = xhci_readl(xhci, &xhci->ir_set->irq_control); | |
387 | temp &= 0xffff; | |
388 | temp |= (u32) 160; | |
389 | xhci_writel(xhci, temp, &xhci->ir_set->irq_control); | |
390 | ||
391 | /* Set the HCD state before we enable the irqs */ | |
392 | hcd->state = HC_STATE_RUNNING; | |
393 | temp = xhci_readl(xhci, &xhci->op_regs->command); | |
394 | temp |= (CMD_EIE); | |
395 | xhci_dbg(xhci, "// Enable interrupts, cmd = 0x%x.\n", | |
396 | temp); | |
397 | xhci_writel(xhci, temp, &xhci->op_regs->command); | |
398 | ||
399 | temp = xhci_readl(xhci, &xhci->ir_set->irq_pending); | |
400 | xhci_dbg(xhci, "// Enabling event ring interrupter 0x%x" | |
401 | " by writing 0x%x to irq_pending\n", | |
402 | (unsigned int) xhci->ir_set, | |
403 | (unsigned int) ER_IRQ_ENABLE(temp)); | |
404 | xhci_writel(xhci, ER_IRQ_ENABLE(temp), | |
405 | &xhci->ir_set->irq_pending); | |
406 | xhci_print_ir_set(xhci, xhci->ir_set, 0); | |
407 | ||
7f84eef0 SS |
408 | if (NUM_TEST_NOOPS > 0) |
409 | doorbell = setup_one_noop(xhci); | |
410 | ||
0ebbab37 SS |
411 | xhci_dbg(xhci, "Command ring memory map follows:\n"); |
412 | xhci_debug_ring(xhci, xhci->cmd_ring); | |
7f84eef0 SS |
413 | xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring); |
414 | xhci_dbg_cmd_ptrs(xhci); | |
415 | ||
0ebbab37 SS |
416 | xhci_dbg(xhci, "ERST memory map follows:\n"); |
417 | xhci_dbg_erst(xhci, &xhci->erst); | |
7f84eef0 SS |
418 | xhci_dbg(xhci, "Event ring:\n"); |
419 | xhci_debug_ring(xhci, xhci->event_ring); | |
420 | xhci_dbg_ring_ptrs(xhci, xhci->event_ring); | |
421 | temp = xhci_readl(xhci, &xhci->ir_set->erst_dequeue[1]); | |
422 | xhci_dbg(xhci, "ERST deq upper = 0x%x\n", temp); | |
423 | temp = xhci_readl(xhci, &xhci->ir_set->erst_dequeue[0]); | |
424 | temp &= ERST_PTR_MASK; | |
425 | xhci_dbg(xhci, "ERST deq = 0x%x\n", temp); | |
0ebbab37 | 426 | |
66d4eadd SS |
427 | temp = xhci_readl(xhci, &xhci->op_regs->command); |
428 | temp |= (CMD_RUN); | |
429 | xhci_dbg(xhci, "// Turn on HC, cmd = 0x%x.\n", | |
430 | temp); | |
431 | xhci_writel(xhci, temp, &xhci->op_regs->command); | |
432 | /* Flush PCI posted writes */ | |
433 | temp = xhci_readl(xhci, &xhci->op_regs->command); | |
434 | xhci_dbg(xhci, "// @%x = 0x%x\n", | |
435 | (unsigned int) &xhci->op_regs->command, temp); | |
7f84eef0 SS |
436 | if (doorbell) |
437 | (*doorbell)(xhci); | |
66d4eadd SS |
438 | |
439 | xhci_dbg(xhci, "Finished xhci_run\n"); | |
440 | return 0; | |
441 | } | |
442 | ||
443 | /* | |
444 | * Stop xHCI driver. | |
445 | * | |
446 | * This function is called by the USB core when the HC driver is removed. | |
447 | * Its opposite is xhci_run(). | |
448 | * | |
449 | * Disable device contexts, disable IRQs, and quiesce the HC. | |
450 | * Reset the HC, finish any completed transactions, and cleanup memory. | |
451 | */ | |
452 | void xhci_stop(struct usb_hcd *hcd) | |
453 | { | |
454 | u32 temp; | |
455 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
456 | ||
457 | spin_lock_irq(&xhci->lock); | |
458 | if (HC_IS_RUNNING(hcd->state)) | |
459 | xhci_quiesce(xhci); | |
460 | xhci_halt(xhci); | |
461 | xhci_reset(xhci); | |
462 | spin_unlock_irq(&xhci->lock); | |
463 | ||
464 | #if 0 /* No MSI yet */ | |
465 | xhci_cleanup_msix(xhci); | |
466 | #endif | |
7f84eef0 SS |
467 | #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING |
468 | /* Tell the event ring poll function not to reschedule */ | |
469 | xhci->zombie = 1; | |
470 | del_timer_sync(&xhci->event_ring_timer); | |
471 | #endif | |
472 | ||
66d4eadd SS |
473 | xhci_dbg(xhci, "// Disabling event ring interrupts\n"); |
474 | temp = xhci_readl(xhci, &xhci->op_regs->status); | |
475 | xhci_writel(xhci, temp & ~STS_EINT, &xhci->op_regs->status); | |
476 | temp = xhci_readl(xhci, &xhci->ir_set->irq_pending); | |
477 | xhci_writel(xhci, ER_IRQ_DISABLE(temp), | |
478 | &xhci->ir_set->irq_pending); | |
479 | xhci_print_ir_set(xhci, xhci->ir_set, 0); | |
480 | ||
481 | xhci_dbg(xhci, "cleaning up memory\n"); | |
482 | xhci_mem_cleanup(xhci); | |
483 | xhci_dbg(xhci, "xhci_stop completed - status = %x\n", | |
484 | xhci_readl(xhci, &xhci->op_regs->status)); | |
485 | } | |
486 | ||
487 | /* | |
488 | * Shutdown HC (not bus-specific) | |
489 | * | |
490 | * This is called when the machine is rebooting or halting. We assume that the | |
491 | * machine will be powered off, and the HC's internal state will be reset. | |
492 | * Don't bother to free memory. | |
493 | */ | |
494 | void xhci_shutdown(struct usb_hcd *hcd) | |
495 | { | |
496 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
497 | ||
498 | spin_lock_irq(&xhci->lock); | |
499 | xhci_halt(xhci); | |
500 | spin_unlock_irq(&xhci->lock); | |
501 | ||
502 | #if 0 | |
503 | xhci_cleanup_msix(xhci); | |
504 | #endif | |
505 | ||
506 | xhci_dbg(xhci, "xhci_shutdown completed - status = %x\n", | |
507 | xhci_readl(xhci, &xhci->op_regs->status)); | |
508 | } | |
509 | ||
7f84eef0 SS |
510 | /*-------------------------------------------------------------------------*/ |
511 | ||
d0e96f5a SS |
512 | /** |
513 | * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and | |
514 | * HCDs. Find the index for an endpoint given its descriptor. Use the return | |
515 | * value to right shift 1 for the bitmask. | |
516 | * | |
517 | * Index = (epnum * 2) + direction - 1, | |
518 | * where direction = 0 for OUT, 1 for IN. | |
519 | * For control endpoints, the IN index is used (OUT index is unused), so | |
520 | * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2) | |
521 | */ | |
522 | unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc) | |
523 | { | |
524 | unsigned int index; | |
525 | if (usb_endpoint_xfer_control(desc)) | |
526 | index = (unsigned int) (usb_endpoint_num(desc)*2); | |
527 | else | |
528 | index = (unsigned int) (usb_endpoint_num(desc)*2) + | |
529 | (usb_endpoint_dir_in(desc) ? 1 : 0) - 1; | |
530 | return index; | |
531 | } | |
532 | ||
533 | /* Returns 1 if the arguments are OK; | |
534 | * returns 0 this is a root hub; returns -EINVAL for NULL pointers. | |
535 | */ | |
536 | int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev, | |
537 | struct usb_host_endpoint *ep, int check_ep, const char *func) { | |
538 | if (!hcd || (check_ep && !ep) || !udev) { | |
539 | printk(KERN_DEBUG "xHCI %s called with invalid args\n", | |
540 | func); | |
541 | return -EINVAL; | |
542 | } | |
543 | if (!udev->parent) { | |
544 | printk(KERN_DEBUG "xHCI %s called for root hub\n", | |
545 | func); | |
546 | return 0; | |
547 | } | |
548 | if (!udev->slot_id) { | |
549 | printk(KERN_DEBUG "xHCI %s called with unaddressed device\n", | |
550 | func); | |
551 | return -EINVAL; | |
552 | } | |
553 | return 1; | |
554 | } | |
555 | ||
556 | /* | |
557 | * non-error returns are a promise to giveback() the urb later | |
558 | * we drop ownership so next owner (or urb unlink) can get it | |
559 | */ | |
560 | int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags) | |
561 | { | |
562 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
563 | unsigned long flags; | |
564 | int ret = 0; | |
565 | unsigned int slot_id, ep_index; | |
566 | ||
567 | if (!urb || xhci_check_args(hcd, urb->dev, urb->ep, true, __func__) <= 0) | |
568 | return -EINVAL; | |
569 | ||
570 | slot_id = urb->dev->slot_id; | |
571 | ep_index = xhci_get_endpoint_index(&urb->ep->desc); | |
572 | /* Only support ep 0 control transfers for now */ | |
573 | if (ep_index != 0) { | |
574 | xhci_dbg(xhci, "WARN: urb submitted to unsupported ep %x\n", | |
575 | urb->ep->desc.bEndpointAddress); | |
576 | return -ENOSYS; | |
577 | } | |
578 | ||
579 | spin_lock_irqsave(&xhci->lock, flags); | |
580 | if (!xhci->devs || !xhci->devs[slot_id]) { | |
581 | if (!in_interrupt()) | |
582 | dev_warn(&urb->dev->dev, "WARN: urb submitted for dev with no Slot ID\n"); | |
583 | return -EINVAL; | |
584 | } | |
585 | if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) { | |
586 | if (!in_interrupt()) | |
587 | xhci_dbg(xhci, "urb submitted during PCI suspend\n"); | |
588 | ret = -ESHUTDOWN; | |
589 | goto exit; | |
590 | } | |
591 | ret = queue_ctrl_tx(xhci, mem_flags, urb, slot_id, ep_index); | |
592 | exit: | |
593 | spin_unlock_irqrestore(&xhci->lock, flags); | |
594 | return ret; | |
595 | } | |
596 | ||
597 | /* Remove from hardware lists | |
598 | * completions normally happen asynchronously | |
599 | */ | |
600 | int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) | |
601 | { | |
602 | return -ENOSYS; | |
603 | } | |
604 | ||
3ffbba95 SS |
605 | /* |
606 | * At this point, the struct usb_device is about to go away, the device has | |
607 | * disconnected, and all traffic has been stopped and the endpoints have been | |
608 | * disabled. Free any HC data structures associated with that device. | |
609 | */ | |
610 | void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev) | |
611 | { | |
612 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
613 | unsigned long flags; | |
614 | ||
615 | if (udev->slot_id == 0) | |
616 | return; | |
617 | ||
618 | spin_lock_irqsave(&xhci->lock, flags); | |
619 | if (queue_slot_control(xhci, TRB_DISABLE_SLOT, udev->slot_id)) { | |
620 | spin_unlock_irqrestore(&xhci->lock, flags); | |
621 | xhci_dbg(xhci, "FIXME: allocate a command ring segment\n"); | |
622 | return; | |
623 | } | |
624 | ring_cmd_db(xhci); | |
625 | spin_unlock_irqrestore(&xhci->lock, flags); | |
626 | /* | |
627 | * Event command completion handler will free any data structures | |
628 | * associated with the slot | |
629 | */ | |
630 | } | |
631 | ||
632 | /* | |
633 | * Returns 0 if the xHC ran out of device slots, the Enable Slot command | |
634 | * timed out, or allocating memory failed. Returns 1 on success. | |
635 | */ | |
636 | int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev) | |
637 | { | |
638 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
639 | unsigned long flags; | |
640 | int timeleft; | |
641 | int ret; | |
642 | ||
643 | spin_lock_irqsave(&xhci->lock, flags); | |
644 | ret = queue_slot_control(xhci, TRB_ENABLE_SLOT, 0); | |
645 | if (ret) { | |
646 | spin_unlock_irqrestore(&xhci->lock, flags); | |
647 | xhci_dbg(xhci, "FIXME: allocate a command ring segment\n"); | |
648 | return 0; | |
649 | } | |
650 | ring_cmd_db(xhci); | |
651 | spin_unlock_irqrestore(&xhci->lock, flags); | |
652 | ||
653 | /* XXX: how much time for xHC slot assignment? */ | |
654 | timeleft = wait_for_completion_interruptible_timeout(&xhci->addr_dev, | |
655 | USB_CTRL_SET_TIMEOUT); | |
656 | if (timeleft <= 0) { | |
657 | xhci_warn(xhci, "%s while waiting for a slot\n", | |
658 | timeleft == 0 ? "Timeout" : "Signal"); | |
659 | /* FIXME cancel the enable slot request */ | |
660 | return 0; | |
661 | } | |
662 | ||
663 | spin_lock_irqsave(&xhci->lock, flags); | |
664 | if (!xhci->slot_id) { | |
665 | xhci_err(xhci, "Error while assigning device slot ID\n"); | |
666 | spin_unlock_irqrestore(&xhci->lock, flags); | |
667 | return 0; | |
668 | } | |
669 | if (!xhci_alloc_virt_device(xhci, xhci->slot_id, udev, GFP_KERNEL)) { | |
670 | /* Disable slot, if we can do it without mem alloc */ | |
671 | xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n"); | |
672 | if (!queue_slot_control(xhci, TRB_DISABLE_SLOT, udev->slot_id)) | |
673 | ring_cmd_db(xhci); | |
674 | spin_unlock_irqrestore(&xhci->lock, flags); | |
675 | return 0; | |
676 | } | |
677 | udev->slot_id = xhci->slot_id; | |
678 | /* Is this a LS or FS device under a HS hub? */ | |
679 | /* Hub or peripherial? */ | |
680 | spin_unlock_irqrestore(&xhci->lock, flags); | |
681 | return 1; | |
682 | } | |
683 | ||
684 | /* | |
685 | * Issue an Address Device command (which will issue a SetAddress request to | |
686 | * the device). | |
687 | * We should be protected by the usb_address0_mutex in khubd's hub_port_init, so | |
688 | * we should only issue and wait on one address command at the same time. | |
689 | * | |
690 | * We add one to the device address issued by the hardware because the USB core | |
691 | * uses address 1 for the root hubs (even though they're not really devices). | |
692 | */ | |
693 | int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev) | |
694 | { | |
695 | unsigned long flags; | |
696 | int timeleft; | |
697 | struct xhci_virt_device *virt_dev; | |
698 | int ret = 0; | |
699 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
700 | u32 temp; | |
701 | ||
702 | if (!udev->slot_id) { | |
703 | xhci_dbg(xhci, "Bad Slot ID %d\n", udev->slot_id); | |
704 | return -EINVAL; | |
705 | } | |
706 | ||
707 | spin_lock_irqsave(&xhci->lock, flags); | |
708 | virt_dev = xhci->devs[udev->slot_id]; | |
709 | ||
710 | /* If this is a Set Address to an unconfigured device, setup ep 0 */ | |
711 | if (!udev->config) | |
712 | xhci_setup_addressable_virt_dev(xhci, udev); | |
713 | /* Otherwise, assume the core has the device configured how it wants */ | |
714 | ||
715 | ret = queue_address_device(xhci, virt_dev->in_ctx_dma, udev->slot_id); | |
716 | if (ret) { | |
717 | spin_unlock_irqrestore(&xhci->lock, flags); | |
718 | xhci_dbg(xhci, "FIXME: allocate a command ring segment\n"); | |
719 | return ret; | |
720 | } | |
721 | ring_cmd_db(xhci); | |
722 | spin_unlock_irqrestore(&xhci->lock, flags); | |
723 | ||
724 | /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */ | |
725 | timeleft = wait_for_completion_interruptible_timeout(&xhci->addr_dev, | |
726 | USB_CTRL_SET_TIMEOUT); | |
727 | /* FIXME: From section 4.3.4: "Software shall be responsible for timing | |
728 | * the SetAddress() "recovery interval" required by USB and aborting the | |
729 | * command on a timeout. | |
730 | */ | |
731 | if (timeleft <= 0) { | |
732 | xhci_warn(xhci, "%s while waiting for a slot\n", | |
733 | timeleft == 0 ? "Timeout" : "Signal"); | |
734 | /* FIXME cancel the address device command */ | |
735 | return -ETIME; | |
736 | } | |
737 | ||
738 | spin_lock_irqsave(&xhci->lock, flags); | |
739 | switch (virt_dev->cmd_status) { | |
740 | case COMP_CTX_STATE: | |
741 | case COMP_EBADSLT: | |
742 | xhci_err(xhci, "Setup ERROR: address device command for slot %d.\n", | |
743 | udev->slot_id); | |
744 | ret = -EINVAL; | |
745 | break; | |
746 | case COMP_TX_ERR: | |
747 | dev_warn(&udev->dev, "Device not responding to set address.\n"); | |
748 | ret = -EPROTO; | |
749 | break; | |
750 | case COMP_SUCCESS: | |
751 | xhci_dbg(xhci, "Successful Address Device command\n"); | |
752 | break; | |
753 | default: | |
754 | xhci_err(xhci, "ERROR: unexpected command completion " | |
755 | "code 0x%x.\n", virt_dev->cmd_status); | |
756 | ret = -EINVAL; | |
757 | break; | |
758 | } | |
759 | if (ret) { | |
760 | spin_unlock_irqrestore(&xhci->lock, flags); | |
761 | return ret; | |
762 | } | |
763 | temp = xhci_readl(xhci, &xhci->op_regs->dcbaa_ptr[0]); | |
764 | xhci_dbg(xhci, "Op regs DCBAA ptr[0] = %#08x\n", temp); | |
765 | temp = xhci_readl(xhci, &xhci->op_regs->dcbaa_ptr[1]); | |
766 | xhci_dbg(xhci, "Op regs DCBAA ptr[1] = %#08x\n", temp); | |
767 | xhci_dbg(xhci, "Slot ID %d dcbaa entry[0] @%08x = %#08x\n", | |
768 | udev->slot_id, | |
769 | (unsigned int) &xhci->dcbaa->dev_context_ptrs[2*udev->slot_id], | |
770 | xhci->dcbaa->dev_context_ptrs[2*udev->slot_id]); | |
771 | xhci_dbg(xhci, "Slot ID %d dcbaa entry[1] @%08x = %#08x\n", | |
772 | udev->slot_id, | |
773 | (unsigned int) &xhci->dcbaa->dev_context_ptrs[2*udev->slot_id+1], | |
774 | xhci->dcbaa->dev_context_ptrs[2*udev->slot_id+1]); | |
775 | xhci_dbg(xhci, "Output Context DMA address = %#08x\n", | |
776 | virt_dev->out_ctx_dma); | |
777 | xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id); | |
778 | xhci_dbg_ctx(xhci, virt_dev->in_ctx, virt_dev->in_ctx_dma, 2); | |
779 | xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id); | |
780 | xhci_dbg_ctx(xhci, virt_dev->out_ctx, virt_dev->out_ctx_dma, 2); | |
781 | /* | |
782 | * USB core uses address 1 for the roothubs, so we add one to the | |
783 | * address given back to us by the HC. | |
784 | */ | |
785 | udev->devnum = (virt_dev->out_ctx->slot.dev_state & DEV_ADDR_MASK) + 1; | |
786 | /* FIXME: Zero the input context control for later use? */ | |
787 | spin_unlock_irqrestore(&xhci->lock, flags); | |
788 | ||
789 | xhci_dbg(xhci, "Device address = %d\n", udev->devnum); | |
790 | /* XXX Meh, not sure if anyone else but choose_address uses this. */ | |
791 | set_bit(udev->devnum, udev->bus->devmap.devicemap); | |
792 | ||
793 | return 0; | |
794 | } | |
795 | ||
66d4eadd SS |
796 | int xhci_get_frame(struct usb_hcd *hcd) |
797 | { | |
798 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
799 | /* EHCI mods by the periodic size. Why? */ | |
800 | return xhci_readl(xhci, &xhci->run_regs->microframe_index) >> 3; | |
801 | } | |
802 | ||
803 | MODULE_DESCRIPTION(DRIVER_DESC); | |
804 | MODULE_AUTHOR(DRIVER_AUTHOR); | |
805 | MODULE_LICENSE("GPL"); | |
806 | ||
807 | static int __init xhci_hcd_init(void) | |
808 | { | |
809 | #ifdef CONFIG_PCI | |
810 | int retval = 0; | |
811 | ||
812 | retval = xhci_register_pci(); | |
813 | ||
814 | if (retval < 0) { | |
815 | printk(KERN_DEBUG "Problem registering PCI driver."); | |
816 | return retval; | |
817 | } | |
818 | #endif | |
819 | return 0; | |
820 | } | |
821 | module_init(xhci_hcd_init); | |
822 | ||
823 | static void __exit xhci_hcd_cleanup(void) | |
824 | { | |
825 | #ifdef CONFIG_PCI | |
826 | xhci_unregister_pci(); | |
827 | #endif | |
828 | } | |
829 | module_exit(xhci_hcd_cleanup); |