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66d4eadd SS |
1 | /* |
2 | * xHCI host controller driver | |
3 | * | |
4 | * Copyright (C) 2008 Intel Corp. | |
5 | * | |
6 | * Author: Sarah Sharp | |
7 | * Some code borrowed from the Linux EHCI driver. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | * for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software Foundation, | |
20 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
23 | #include <linux/usb.h> | |
0ebbab37 | 24 | #include <linux/pci.h> |
5a0e3ad6 | 25 | #include <linux/slab.h> |
527c6d7f | 26 | #include <linux/dmapool.h> |
66d4eadd SS |
27 | |
28 | #include "xhci.h" | |
29 | ||
0ebbab37 SS |
30 | /* |
31 | * Allocates a generic ring segment from the ring pool, sets the dma address, | |
32 | * initializes the segment to zero, and sets the private next pointer to NULL. | |
33 | * | |
34 | * Section 4.11.1.1: | |
35 | * "All components of all Command and Transfer TRBs shall be initialized to '0'" | |
36 | */ | |
37 | static struct xhci_segment *xhci_segment_alloc(struct xhci_hcd *xhci, gfp_t flags) | |
38 | { | |
39 | struct xhci_segment *seg; | |
40 | dma_addr_t dma; | |
41 | ||
42 | seg = kzalloc(sizeof *seg, flags); | |
43 | if (!seg) | |
326b4810 | 44 | return NULL; |
700e2052 | 45 | xhci_dbg(xhci, "Allocating priv segment structure at %p\n", seg); |
0ebbab37 SS |
46 | |
47 | seg->trbs = dma_pool_alloc(xhci->segment_pool, flags, &dma); | |
48 | if (!seg->trbs) { | |
49 | kfree(seg); | |
326b4810 | 50 | return NULL; |
0ebbab37 | 51 | } |
700e2052 GKH |
52 | xhci_dbg(xhci, "// Allocating segment at %p (virtual) 0x%llx (DMA)\n", |
53 | seg->trbs, (unsigned long long)dma); | |
0ebbab37 SS |
54 | |
55 | memset(seg->trbs, 0, SEGMENT_SIZE); | |
56 | seg->dma = dma; | |
57 | seg->next = NULL; | |
58 | ||
59 | return seg; | |
60 | } | |
61 | ||
62 | static void xhci_segment_free(struct xhci_hcd *xhci, struct xhci_segment *seg) | |
63 | { | |
64 | if (!seg) | |
65 | return; | |
66 | if (seg->trbs) { | |
700e2052 GKH |
67 | xhci_dbg(xhci, "Freeing DMA segment at %p (virtual) 0x%llx (DMA)\n", |
68 | seg->trbs, (unsigned long long)seg->dma); | |
0ebbab37 SS |
69 | dma_pool_free(xhci->segment_pool, seg->trbs, seg->dma); |
70 | seg->trbs = NULL; | |
71 | } | |
700e2052 | 72 | xhci_dbg(xhci, "Freeing priv segment structure at %p\n", seg); |
0ebbab37 SS |
73 | kfree(seg); |
74 | } | |
75 | ||
76 | /* | |
77 | * Make the prev segment point to the next segment. | |
78 | * | |
79 | * Change the last TRB in the prev segment to be a Link TRB which points to the | |
80 | * DMA address of the next segment. The caller needs to set any Link TRB | |
81 | * related flags, such as End TRB, Toggle Cycle, and no snoop. | |
82 | */ | |
83 | static void xhci_link_segments(struct xhci_hcd *xhci, struct xhci_segment *prev, | |
84 | struct xhci_segment *next, bool link_trbs) | |
85 | { | |
86 | u32 val; | |
87 | ||
88 | if (!prev || !next) | |
89 | return; | |
90 | prev->next = next; | |
91 | if (link_trbs) { | |
28ccd296 ME |
92 | prev->trbs[TRBS_PER_SEGMENT-1].link. |
93 | segment_ptr = cpu_to_le64(next->dma); | |
0ebbab37 SS |
94 | |
95 | /* Set the last TRB in the segment to have a TRB type ID of Link TRB */ | |
28ccd296 | 96 | val = le32_to_cpu(prev->trbs[TRBS_PER_SEGMENT-1].link.control); |
0ebbab37 SS |
97 | val &= ~TRB_TYPE_BITMASK; |
98 | val |= TRB_TYPE(TRB_LINK); | |
b0567b3f SS |
99 | /* Always set the chain bit with 0.95 hardware */ |
100 | if (xhci_link_trb_quirk(xhci)) | |
101 | val |= TRB_CHAIN; | |
28ccd296 | 102 | prev->trbs[TRBS_PER_SEGMENT-1].link.control = cpu_to_le32(val); |
0ebbab37 | 103 | } |
700e2052 GKH |
104 | xhci_dbg(xhci, "Linking segment 0x%llx to segment 0x%llx (DMA)\n", |
105 | (unsigned long long)prev->dma, | |
106 | (unsigned long long)next->dma); | |
0ebbab37 SS |
107 | } |
108 | ||
109 | /* XXX: Do we need the hcd structure in all these functions? */ | |
f94e0186 | 110 | void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring) |
0ebbab37 SS |
111 | { |
112 | struct xhci_segment *seg; | |
113 | struct xhci_segment *first_seg; | |
114 | ||
115 | if (!ring || !ring->first_seg) | |
116 | return; | |
117 | first_seg = ring->first_seg; | |
118 | seg = first_seg->next; | |
700e2052 | 119 | xhci_dbg(xhci, "Freeing ring at %p\n", ring); |
0ebbab37 SS |
120 | while (seg != first_seg) { |
121 | struct xhci_segment *next = seg->next; | |
122 | xhci_segment_free(xhci, seg); | |
123 | seg = next; | |
124 | } | |
125 | xhci_segment_free(xhci, first_seg); | |
126 | ring->first_seg = NULL; | |
127 | kfree(ring); | |
128 | } | |
129 | ||
74f9fe21 SS |
130 | static void xhci_initialize_ring_info(struct xhci_ring *ring) |
131 | { | |
132 | /* The ring is empty, so the enqueue pointer == dequeue pointer */ | |
133 | ring->enqueue = ring->first_seg->trbs; | |
134 | ring->enq_seg = ring->first_seg; | |
135 | ring->dequeue = ring->enqueue; | |
136 | ring->deq_seg = ring->first_seg; | |
137 | /* The ring is initialized to 0. The producer must write 1 to the cycle | |
138 | * bit to handover ownership of the TRB, so PCS = 1. The consumer must | |
139 | * compare CCS to the cycle bit to check ownership, so CCS = 1. | |
140 | */ | |
141 | ring->cycle_state = 1; | |
142 | /* Not necessary for new rings, but needed for re-initialized rings */ | |
143 | ring->enq_updates = 0; | |
144 | ring->deq_updates = 0; | |
145 | } | |
146 | ||
0ebbab37 SS |
147 | /** |
148 | * Create a new ring with zero or more segments. | |
149 | * | |
150 | * Link each segment together into a ring. | |
151 | * Set the end flag and the cycle toggle bit on the last segment. | |
152 | * See section 4.9.1 and figures 15 and 16. | |
153 | */ | |
154 | static struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci, | |
155 | unsigned int num_segs, bool link_trbs, gfp_t flags) | |
156 | { | |
157 | struct xhci_ring *ring; | |
158 | struct xhci_segment *prev; | |
159 | ||
160 | ring = kzalloc(sizeof *(ring), flags); | |
700e2052 | 161 | xhci_dbg(xhci, "Allocating ring at %p\n", ring); |
0ebbab37 | 162 | if (!ring) |
326b4810 | 163 | return NULL; |
0ebbab37 | 164 | |
d0e96f5a | 165 | INIT_LIST_HEAD(&ring->td_list); |
0ebbab37 SS |
166 | if (num_segs == 0) |
167 | return ring; | |
168 | ||
169 | ring->first_seg = xhci_segment_alloc(xhci, flags); | |
170 | if (!ring->first_seg) | |
171 | goto fail; | |
172 | num_segs--; | |
173 | ||
174 | prev = ring->first_seg; | |
175 | while (num_segs > 0) { | |
176 | struct xhci_segment *next; | |
177 | ||
178 | next = xhci_segment_alloc(xhci, flags); | |
179 | if (!next) | |
180 | goto fail; | |
181 | xhci_link_segments(xhci, prev, next, link_trbs); | |
182 | ||
183 | prev = next; | |
184 | num_segs--; | |
185 | } | |
186 | xhci_link_segments(xhci, prev, ring->first_seg, link_trbs); | |
187 | ||
188 | if (link_trbs) { | |
189 | /* See section 4.9.2.1 and 6.4.4.1 */ | |
28ccd296 ME |
190 | prev->trbs[TRBS_PER_SEGMENT-1].link. |
191 | control |= cpu_to_le32(LINK_TOGGLE); | |
0ebbab37 | 192 | xhci_dbg(xhci, "Wrote link toggle flag to" |
700e2052 GKH |
193 | " segment %p (virtual), 0x%llx (DMA)\n", |
194 | prev, (unsigned long long)prev->dma); | |
0ebbab37 | 195 | } |
74f9fe21 | 196 | xhci_initialize_ring_info(ring); |
0ebbab37 SS |
197 | return ring; |
198 | ||
199 | fail: | |
200 | xhci_ring_free(xhci, ring); | |
326b4810 | 201 | return NULL; |
0ebbab37 SS |
202 | } |
203 | ||
412566bd SS |
204 | void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci, |
205 | struct xhci_virt_device *virt_dev, | |
206 | unsigned int ep_index) | |
207 | { | |
208 | int rings_cached; | |
209 | ||
210 | rings_cached = virt_dev->num_rings_cached; | |
211 | if (rings_cached < XHCI_MAX_RINGS_CACHED) { | |
412566bd SS |
212 | virt_dev->ring_cache[rings_cached] = |
213 | virt_dev->eps[ep_index].ring; | |
30f89ca0 | 214 | virt_dev->num_rings_cached++; |
412566bd SS |
215 | xhci_dbg(xhci, "Cached old ring, " |
216 | "%d ring%s cached\n", | |
30f89ca0 SS |
217 | virt_dev->num_rings_cached, |
218 | (virt_dev->num_rings_cached > 1) ? "s" : ""); | |
412566bd SS |
219 | } else { |
220 | xhci_ring_free(xhci, virt_dev->eps[ep_index].ring); | |
221 | xhci_dbg(xhci, "Ring cache full (%d rings), " | |
222 | "freeing ring\n", | |
223 | virt_dev->num_rings_cached); | |
224 | } | |
225 | virt_dev->eps[ep_index].ring = NULL; | |
226 | } | |
227 | ||
74f9fe21 SS |
228 | /* Zero an endpoint ring (except for link TRBs) and move the enqueue and dequeue |
229 | * pointers to the beginning of the ring. | |
230 | */ | |
231 | static void xhci_reinit_cached_ring(struct xhci_hcd *xhci, | |
232 | struct xhci_ring *ring) | |
233 | { | |
234 | struct xhci_segment *seg = ring->first_seg; | |
235 | do { | |
236 | memset(seg->trbs, 0, | |
237 | sizeof(union xhci_trb)*TRBS_PER_SEGMENT); | |
238 | /* All endpoint rings have link TRBs */ | |
239 | xhci_link_segments(xhci, seg, seg->next, 1); | |
240 | seg = seg->next; | |
241 | } while (seg != ring->first_seg); | |
242 | xhci_initialize_ring_info(ring); | |
243 | /* td list should be empty since all URBs have been cancelled, | |
244 | * but just in case... | |
245 | */ | |
246 | INIT_LIST_HEAD(&ring->td_list); | |
247 | } | |
248 | ||
d115b048 JY |
249 | #define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32) |
250 | ||
326b4810 | 251 | static struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci, |
d115b048 JY |
252 | int type, gfp_t flags) |
253 | { | |
254 | struct xhci_container_ctx *ctx = kzalloc(sizeof(*ctx), flags); | |
255 | if (!ctx) | |
256 | return NULL; | |
257 | ||
258 | BUG_ON((type != XHCI_CTX_TYPE_DEVICE) && (type != XHCI_CTX_TYPE_INPUT)); | |
259 | ctx->type = type; | |
260 | ctx->size = HCC_64BYTE_CONTEXT(xhci->hcc_params) ? 2048 : 1024; | |
261 | if (type == XHCI_CTX_TYPE_INPUT) | |
262 | ctx->size += CTX_SIZE(xhci->hcc_params); | |
263 | ||
264 | ctx->bytes = dma_pool_alloc(xhci->device_pool, flags, &ctx->dma); | |
265 | memset(ctx->bytes, 0, ctx->size); | |
266 | return ctx; | |
267 | } | |
268 | ||
326b4810 | 269 | static void xhci_free_container_ctx(struct xhci_hcd *xhci, |
d115b048 JY |
270 | struct xhci_container_ctx *ctx) |
271 | { | |
a1d78c16 SS |
272 | if (!ctx) |
273 | return; | |
d115b048 JY |
274 | dma_pool_free(xhci->device_pool, ctx->bytes, ctx->dma); |
275 | kfree(ctx); | |
276 | } | |
277 | ||
278 | struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci, | |
279 | struct xhci_container_ctx *ctx) | |
280 | { | |
281 | BUG_ON(ctx->type != XHCI_CTX_TYPE_INPUT); | |
282 | return (struct xhci_input_control_ctx *)ctx->bytes; | |
283 | } | |
284 | ||
285 | struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, | |
286 | struct xhci_container_ctx *ctx) | |
287 | { | |
288 | if (ctx->type == XHCI_CTX_TYPE_DEVICE) | |
289 | return (struct xhci_slot_ctx *)ctx->bytes; | |
290 | ||
291 | return (struct xhci_slot_ctx *) | |
292 | (ctx->bytes + CTX_SIZE(xhci->hcc_params)); | |
293 | } | |
294 | ||
295 | struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, | |
296 | struct xhci_container_ctx *ctx, | |
297 | unsigned int ep_index) | |
298 | { | |
299 | /* increment ep index by offset of start of ep ctx array */ | |
300 | ep_index++; | |
301 | if (ctx->type == XHCI_CTX_TYPE_INPUT) | |
302 | ep_index++; | |
303 | ||
304 | return (struct xhci_ep_ctx *) | |
305 | (ctx->bytes + (ep_index * CTX_SIZE(xhci->hcc_params))); | |
306 | } | |
307 | ||
8df75f42 SS |
308 | |
309 | /***************** Streams structures manipulation *************************/ | |
310 | ||
8212a49d | 311 | static void xhci_free_stream_ctx(struct xhci_hcd *xhci, |
8df75f42 SS |
312 | unsigned int num_stream_ctxs, |
313 | struct xhci_stream_ctx *stream_ctx, dma_addr_t dma) | |
314 | { | |
315 | struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller); | |
316 | ||
317 | if (num_stream_ctxs > MEDIUM_STREAM_ARRAY_SIZE) | |
318 | pci_free_consistent(pdev, | |
319 | sizeof(struct xhci_stream_ctx)*num_stream_ctxs, | |
320 | stream_ctx, dma); | |
321 | else if (num_stream_ctxs <= SMALL_STREAM_ARRAY_SIZE) | |
322 | return dma_pool_free(xhci->small_streams_pool, | |
323 | stream_ctx, dma); | |
324 | else | |
325 | return dma_pool_free(xhci->medium_streams_pool, | |
326 | stream_ctx, dma); | |
327 | } | |
328 | ||
329 | /* | |
330 | * The stream context array for each endpoint with bulk streams enabled can | |
331 | * vary in size, based on: | |
332 | * - how many streams the endpoint supports, | |
333 | * - the maximum primary stream array size the host controller supports, | |
334 | * - and how many streams the device driver asks for. | |
335 | * | |
336 | * The stream context array must be a power of 2, and can be as small as | |
337 | * 64 bytes or as large as 1MB. | |
338 | */ | |
8212a49d | 339 | static struct xhci_stream_ctx *xhci_alloc_stream_ctx(struct xhci_hcd *xhci, |
8df75f42 SS |
340 | unsigned int num_stream_ctxs, dma_addr_t *dma, |
341 | gfp_t mem_flags) | |
342 | { | |
343 | struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller); | |
344 | ||
345 | if (num_stream_ctxs > MEDIUM_STREAM_ARRAY_SIZE) | |
346 | return pci_alloc_consistent(pdev, | |
347 | sizeof(struct xhci_stream_ctx)*num_stream_ctxs, | |
348 | dma); | |
349 | else if (num_stream_ctxs <= SMALL_STREAM_ARRAY_SIZE) | |
350 | return dma_pool_alloc(xhci->small_streams_pool, | |
351 | mem_flags, dma); | |
352 | else | |
353 | return dma_pool_alloc(xhci->medium_streams_pool, | |
354 | mem_flags, dma); | |
355 | } | |
356 | ||
e9df17eb SS |
357 | struct xhci_ring *xhci_dma_to_transfer_ring( |
358 | struct xhci_virt_ep *ep, | |
359 | u64 address) | |
360 | { | |
361 | if (ep->ep_state & EP_HAS_STREAMS) | |
362 | return radix_tree_lookup(&ep->stream_info->trb_address_map, | |
363 | address >> SEGMENT_SHIFT); | |
364 | return ep->ring; | |
365 | } | |
366 | ||
367 | /* Only use this when you know stream_info is valid */ | |
8df75f42 | 368 | #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING |
e9df17eb | 369 | static struct xhci_ring *dma_to_stream_ring( |
8df75f42 SS |
370 | struct xhci_stream_info *stream_info, |
371 | u64 address) | |
372 | { | |
373 | return radix_tree_lookup(&stream_info->trb_address_map, | |
374 | address >> SEGMENT_SHIFT); | |
375 | } | |
376 | #endif /* CONFIG_USB_XHCI_HCD_DEBUGGING */ | |
377 | ||
e9df17eb SS |
378 | struct xhci_ring *xhci_stream_id_to_ring( |
379 | struct xhci_virt_device *dev, | |
380 | unsigned int ep_index, | |
381 | unsigned int stream_id) | |
382 | { | |
383 | struct xhci_virt_ep *ep = &dev->eps[ep_index]; | |
384 | ||
385 | if (stream_id == 0) | |
386 | return ep->ring; | |
387 | if (!ep->stream_info) | |
388 | return NULL; | |
389 | ||
390 | if (stream_id > ep->stream_info->num_streams) | |
391 | return NULL; | |
392 | return ep->stream_info->stream_rings[stream_id]; | |
393 | } | |
394 | ||
8df75f42 SS |
395 | #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING |
396 | static int xhci_test_radix_tree(struct xhci_hcd *xhci, | |
397 | unsigned int num_streams, | |
398 | struct xhci_stream_info *stream_info) | |
399 | { | |
400 | u32 cur_stream; | |
401 | struct xhci_ring *cur_ring; | |
402 | u64 addr; | |
403 | ||
404 | for (cur_stream = 1; cur_stream < num_streams; cur_stream++) { | |
405 | struct xhci_ring *mapped_ring; | |
406 | int trb_size = sizeof(union xhci_trb); | |
407 | ||
408 | cur_ring = stream_info->stream_rings[cur_stream]; | |
409 | for (addr = cur_ring->first_seg->dma; | |
410 | addr < cur_ring->first_seg->dma + SEGMENT_SIZE; | |
411 | addr += trb_size) { | |
412 | mapped_ring = dma_to_stream_ring(stream_info, addr); | |
413 | if (cur_ring != mapped_ring) { | |
414 | xhci_warn(xhci, "WARN: DMA address 0x%08llx " | |
415 | "didn't map to stream ID %u; " | |
416 | "mapped to ring %p\n", | |
417 | (unsigned long long) addr, | |
418 | cur_stream, | |
419 | mapped_ring); | |
420 | return -EINVAL; | |
421 | } | |
422 | } | |
423 | /* One TRB after the end of the ring segment shouldn't return a | |
424 | * pointer to the current ring (although it may be a part of a | |
425 | * different ring). | |
426 | */ | |
427 | mapped_ring = dma_to_stream_ring(stream_info, addr); | |
428 | if (mapped_ring != cur_ring) { | |
429 | /* One TRB before should also fail */ | |
430 | addr = cur_ring->first_seg->dma - trb_size; | |
431 | mapped_ring = dma_to_stream_ring(stream_info, addr); | |
432 | } | |
433 | if (mapped_ring == cur_ring) { | |
434 | xhci_warn(xhci, "WARN: Bad DMA address 0x%08llx " | |
435 | "mapped to valid stream ID %u; " | |
436 | "mapped ring = %p\n", | |
437 | (unsigned long long) addr, | |
438 | cur_stream, | |
439 | mapped_ring); | |
440 | return -EINVAL; | |
441 | } | |
442 | } | |
443 | return 0; | |
444 | } | |
445 | #endif /* CONFIG_USB_XHCI_HCD_DEBUGGING */ | |
446 | ||
447 | /* | |
448 | * Change an endpoint's internal structure so it supports stream IDs. The | |
449 | * number of requested streams includes stream 0, which cannot be used by device | |
450 | * drivers. | |
451 | * | |
452 | * The number of stream contexts in the stream context array may be bigger than | |
453 | * the number of streams the driver wants to use. This is because the number of | |
454 | * stream context array entries must be a power of two. | |
455 | * | |
456 | * We need a radix tree for mapping physical addresses of TRBs to which stream | |
457 | * ID they belong to. We need to do this because the host controller won't tell | |
458 | * us which stream ring the TRB came from. We could store the stream ID in an | |
459 | * event data TRB, but that doesn't help us for the cancellation case, since the | |
460 | * endpoint may stop before it reaches that event data TRB. | |
461 | * | |
462 | * The radix tree maps the upper portion of the TRB DMA address to a ring | |
463 | * segment that has the same upper portion of DMA addresses. For example, say I | |
464 | * have segments of size 1KB, that are always 64-byte aligned. A segment may | |
465 | * start at 0x10c91000 and end at 0x10c913f0. If I use the upper 10 bits, the | |
466 | * key to the stream ID is 0x43244. I can use the DMA address of the TRB to | |
467 | * pass the radix tree a key to get the right stream ID: | |
468 | * | |
469 | * 0x10c90fff >> 10 = 0x43243 | |
470 | * 0x10c912c0 >> 10 = 0x43244 | |
471 | * 0x10c91400 >> 10 = 0x43245 | |
472 | * | |
473 | * Obviously, only those TRBs with DMA addresses that are within the segment | |
474 | * will make the radix tree return the stream ID for that ring. | |
475 | * | |
476 | * Caveats for the radix tree: | |
477 | * | |
478 | * The radix tree uses an unsigned long as a key pair. On 32-bit systems, an | |
479 | * unsigned long will be 32-bits; on a 64-bit system an unsigned long will be | |
480 | * 64-bits. Since we only request 32-bit DMA addresses, we can use that as the | |
481 | * key on 32-bit or 64-bit systems (it would also be fine if we asked for 64-bit | |
482 | * PCI DMA addresses on a 64-bit system). There might be a problem on 32-bit | |
483 | * extended systems (where the DMA address can be bigger than 32-bits), | |
484 | * if we allow the PCI dma mask to be bigger than 32-bits. So don't do that. | |
485 | */ | |
486 | struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci, | |
487 | unsigned int num_stream_ctxs, | |
488 | unsigned int num_streams, gfp_t mem_flags) | |
489 | { | |
490 | struct xhci_stream_info *stream_info; | |
491 | u32 cur_stream; | |
492 | struct xhci_ring *cur_ring; | |
493 | unsigned long key; | |
494 | u64 addr; | |
495 | int ret; | |
496 | ||
497 | xhci_dbg(xhci, "Allocating %u streams and %u " | |
498 | "stream context array entries.\n", | |
499 | num_streams, num_stream_ctxs); | |
500 | if (xhci->cmd_ring_reserved_trbs == MAX_RSVD_CMD_TRBS) { | |
501 | xhci_dbg(xhci, "Command ring has no reserved TRBs available\n"); | |
502 | return NULL; | |
503 | } | |
504 | xhci->cmd_ring_reserved_trbs++; | |
505 | ||
506 | stream_info = kzalloc(sizeof(struct xhci_stream_info), mem_flags); | |
507 | if (!stream_info) | |
508 | goto cleanup_trbs; | |
509 | ||
510 | stream_info->num_streams = num_streams; | |
511 | stream_info->num_stream_ctxs = num_stream_ctxs; | |
512 | ||
513 | /* Initialize the array of virtual pointers to stream rings. */ | |
514 | stream_info->stream_rings = kzalloc( | |
515 | sizeof(struct xhci_ring *)*num_streams, | |
516 | mem_flags); | |
517 | if (!stream_info->stream_rings) | |
518 | goto cleanup_info; | |
519 | ||
520 | /* Initialize the array of DMA addresses for stream rings for the HW. */ | |
521 | stream_info->stream_ctx_array = xhci_alloc_stream_ctx(xhci, | |
522 | num_stream_ctxs, &stream_info->ctx_array_dma, | |
523 | mem_flags); | |
524 | if (!stream_info->stream_ctx_array) | |
525 | goto cleanup_ctx; | |
526 | memset(stream_info->stream_ctx_array, 0, | |
527 | sizeof(struct xhci_stream_ctx)*num_stream_ctxs); | |
528 | ||
529 | /* Allocate everything needed to free the stream rings later */ | |
530 | stream_info->free_streams_command = | |
531 | xhci_alloc_command(xhci, true, true, mem_flags); | |
532 | if (!stream_info->free_streams_command) | |
533 | goto cleanup_ctx; | |
534 | ||
535 | INIT_RADIX_TREE(&stream_info->trb_address_map, GFP_ATOMIC); | |
536 | ||
537 | /* Allocate rings for all the streams that the driver will use, | |
538 | * and add their segment DMA addresses to the radix tree. | |
539 | * Stream 0 is reserved. | |
540 | */ | |
541 | for (cur_stream = 1; cur_stream < num_streams; cur_stream++) { | |
542 | stream_info->stream_rings[cur_stream] = | |
543 | xhci_ring_alloc(xhci, 1, true, mem_flags); | |
544 | cur_ring = stream_info->stream_rings[cur_stream]; | |
545 | if (!cur_ring) | |
546 | goto cleanup_rings; | |
e9df17eb | 547 | cur_ring->stream_id = cur_stream; |
8df75f42 SS |
548 | /* Set deq ptr, cycle bit, and stream context type */ |
549 | addr = cur_ring->first_seg->dma | | |
550 | SCT_FOR_CTX(SCT_PRI_TR) | | |
551 | cur_ring->cycle_state; | |
28ccd296 ME |
552 | stream_info->stream_ctx_array[cur_stream]. |
553 | stream_ring = cpu_to_le64(addr); | |
8df75f42 SS |
554 | xhci_dbg(xhci, "Setting stream %d ring ptr to 0x%08llx\n", |
555 | cur_stream, (unsigned long long) addr); | |
556 | ||
557 | key = (unsigned long) | |
558 | (cur_ring->first_seg->dma >> SEGMENT_SHIFT); | |
559 | ret = radix_tree_insert(&stream_info->trb_address_map, | |
560 | key, cur_ring); | |
561 | if (ret) { | |
562 | xhci_ring_free(xhci, cur_ring); | |
563 | stream_info->stream_rings[cur_stream] = NULL; | |
564 | goto cleanup_rings; | |
565 | } | |
566 | } | |
567 | /* Leave the other unused stream ring pointers in the stream context | |
568 | * array initialized to zero. This will cause the xHC to give us an | |
569 | * error if the device asks for a stream ID we don't have setup (if it | |
570 | * was any other way, the host controller would assume the ring is | |
571 | * "empty" and wait forever for data to be queued to that stream ID). | |
572 | */ | |
573 | #if XHCI_DEBUG | |
574 | /* Do a little test on the radix tree to make sure it returns the | |
575 | * correct values. | |
576 | */ | |
577 | if (xhci_test_radix_tree(xhci, num_streams, stream_info)) | |
578 | goto cleanup_rings; | |
579 | #endif | |
580 | ||
581 | return stream_info; | |
582 | ||
583 | cleanup_rings: | |
584 | for (cur_stream = 1; cur_stream < num_streams; cur_stream++) { | |
585 | cur_ring = stream_info->stream_rings[cur_stream]; | |
586 | if (cur_ring) { | |
587 | addr = cur_ring->first_seg->dma; | |
588 | radix_tree_delete(&stream_info->trb_address_map, | |
589 | addr >> SEGMENT_SHIFT); | |
590 | xhci_ring_free(xhci, cur_ring); | |
591 | stream_info->stream_rings[cur_stream] = NULL; | |
592 | } | |
593 | } | |
594 | xhci_free_command(xhci, stream_info->free_streams_command); | |
595 | cleanup_ctx: | |
596 | kfree(stream_info->stream_rings); | |
597 | cleanup_info: | |
598 | kfree(stream_info); | |
599 | cleanup_trbs: | |
600 | xhci->cmd_ring_reserved_trbs--; | |
601 | return NULL; | |
602 | } | |
603 | /* | |
604 | * Sets the MaxPStreams field and the Linear Stream Array field. | |
605 | * Sets the dequeue pointer to the stream context array. | |
606 | */ | |
607 | void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci, | |
608 | struct xhci_ep_ctx *ep_ctx, | |
609 | struct xhci_stream_info *stream_info) | |
610 | { | |
611 | u32 max_primary_streams; | |
612 | /* MaxPStreams is the number of stream context array entries, not the | |
613 | * number we're actually using. Must be in 2^(MaxPstreams + 1) format. | |
614 | * fls(0) = 0, fls(0x1) = 1, fls(0x10) = 2, fls(0x100) = 3, etc. | |
615 | */ | |
616 | max_primary_streams = fls(stream_info->num_stream_ctxs) - 2; | |
617 | xhci_dbg(xhci, "Setting number of stream ctx array entries to %u\n", | |
618 | 1 << (max_primary_streams + 1)); | |
28ccd296 ME |
619 | ep_ctx->ep_info &= cpu_to_le32(~EP_MAXPSTREAMS_MASK); |
620 | ep_ctx->ep_info |= cpu_to_le32(EP_MAXPSTREAMS(max_primary_streams) | |
621 | | EP_HAS_LSA); | |
622 | ep_ctx->deq = cpu_to_le64(stream_info->ctx_array_dma); | |
8df75f42 SS |
623 | } |
624 | ||
625 | /* | |
626 | * Sets the MaxPStreams field and the Linear Stream Array field to 0. | |
627 | * Reinstalls the "normal" endpoint ring (at its previous dequeue mark, | |
628 | * not at the beginning of the ring). | |
629 | */ | |
630 | void xhci_setup_no_streams_ep_input_ctx(struct xhci_hcd *xhci, | |
631 | struct xhci_ep_ctx *ep_ctx, | |
632 | struct xhci_virt_ep *ep) | |
633 | { | |
634 | dma_addr_t addr; | |
28ccd296 | 635 | ep_ctx->ep_info &= cpu_to_le32(~(EP_MAXPSTREAMS_MASK | EP_HAS_LSA)); |
8df75f42 | 636 | addr = xhci_trb_virt_to_dma(ep->ring->deq_seg, ep->ring->dequeue); |
28ccd296 | 637 | ep_ctx->deq = cpu_to_le64(addr | ep->ring->cycle_state); |
8df75f42 SS |
638 | } |
639 | ||
640 | /* Frees all stream contexts associated with the endpoint, | |
641 | * | |
642 | * Caller should fix the endpoint context streams fields. | |
643 | */ | |
644 | void xhci_free_stream_info(struct xhci_hcd *xhci, | |
645 | struct xhci_stream_info *stream_info) | |
646 | { | |
647 | int cur_stream; | |
648 | struct xhci_ring *cur_ring; | |
649 | dma_addr_t addr; | |
650 | ||
651 | if (!stream_info) | |
652 | return; | |
653 | ||
654 | for (cur_stream = 1; cur_stream < stream_info->num_streams; | |
655 | cur_stream++) { | |
656 | cur_ring = stream_info->stream_rings[cur_stream]; | |
657 | if (cur_ring) { | |
658 | addr = cur_ring->first_seg->dma; | |
659 | radix_tree_delete(&stream_info->trb_address_map, | |
660 | addr >> SEGMENT_SHIFT); | |
661 | xhci_ring_free(xhci, cur_ring); | |
662 | stream_info->stream_rings[cur_stream] = NULL; | |
663 | } | |
664 | } | |
665 | xhci_free_command(xhci, stream_info->free_streams_command); | |
666 | xhci->cmd_ring_reserved_trbs--; | |
667 | if (stream_info->stream_ctx_array) | |
668 | xhci_free_stream_ctx(xhci, | |
669 | stream_info->num_stream_ctxs, | |
670 | stream_info->stream_ctx_array, | |
671 | stream_info->ctx_array_dma); | |
672 | ||
673 | if (stream_info) | |
674 | kfree(stream_info->stream_rings); | |
675 | kfree(stream_info); | |
676 | } | |
677 | ||
678 | ||
679 | /***************** Device context manipulation *************************/ | |
680 | ||
6f5165cf SS |
681 | static void xhci_init_endpoint_timer(struct xhci_hcd *xhci, |
682 | struct xhci_virt_ep *ep) | |
683 | { | |
684 | init_timer(&ep->stop_cmd_timer); | |
685 | ep->stop_cmd_timer.data = (unsigned long) ep; | |
686 | ep->stop_cmd_timer.function = xhci_stop_endpoint_command_watchdog; | |
687 | ep->xhci = xhci; | |
688 | } | |
689 | ||
d0e96f5a | 690 | /* All the xhci_tds in the ring's TD list should be freed at this point */ |
3ffbba95 SS |
691 | void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id) |
692 | { | |
693 | struct xhci_virt_device *dev; | |
694 | int i; | |
695 | ||
696 | /* Slot ID 0 is reserved */ | |
697 | if (slot_id == 0 || !xhci->devs[slot_id]) | |
698 | return; | |
699 | ||
700 | dev = xhci->devs[slot_id]; | |
8e595a5d | 701 | xhci->dcbaa->dev_context_ptrs[slot_id] = 0; |
3ffbba95 SS |
702 | if (!dev) |
703 | return; | |
704 | ||
8df75f42 | 705 | for (i = 0; i < 31; ++i) { |
63a0d9ab SS |
706 | if (dev->eps[i].ring) |
707 | xhci_ring_free(xhci, dev->eps[i].ring); | |
8df75f42 SS |
708 | if (dev->eps[i].stream_info) |
709 | xhci_free_stream_info(xhci, | |
710 | dev->eps[i].stream_info); | |
711 | } | |
3ffbba95 | 712 | |
74f9fe21 SS |
713 | if (dev->ring_cache) { |
714 | for (i = 0; i < dev->num_rings_cached; i++) | |
715 | xhci_ring_free(xhci, dev->ring_cache[i]); | |
716 | kfree(dev->ring_cache); | |
717 | } | |
718 | ||
3ffbba95 | 719 | if (dev->in_ctx) |
d115b048 | 720 | xhci_free_container_ctx(xhci, dev->in_ctx); |
3ffbba95 | 721 | if (dev->out_ctx) |
d115b048 JY |
722 | xhci_free_container_ctx(xhci, dev->out_ctx); |
723 | ||
3ffbba95 | 724 | kfree(xhci->devs[slot_id]); |
326b4810 | 725 | xhci->devs[slot_id] = NULL; |
3ffbba95 SS |
726 | } |
727 | ||
728 | int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, | |
729 | struct usb_device *udev, gfp_t flags) | |
730 | { | |
3ffbba95 | 731 | struct xhci_virt_device *dev; |
63a0d9ab | 732 | int i; |
3ffbba95 SS |
733 | |
734 | /* Slot ID 0 is reserved */ | |
735 | if (slot_id == 0 || xhci->devs[slot_id]) { | |
736 | xhci_warn(xhci, "Bad Slot ID %d\n", slot_id); | |
737 | return 0; | |
738 | } | |
739 | ||
740 | xhci->devs[slot_id] = kzalloc(sizeof(*xhci->devs[slot_id]), flags); | |
741 | if (!xhci->devs[slot_id]) | |
742 | return 0; | |
743 | dev = xhci->devs[slot_id]; | |
744 | ||
d115b048 JY |
745 | /* Allocate the (output) device context that will be used in the HC. */ |
746 | dev->out_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_DEVICE, flags); | |
3ffbba95 SS |
747 | if (!dev->out_ctx) |
748 | goto fail; | |
d115b048 | 749 | |
700e2052 | 750 | xhci_dbg(xhci, "Slot %d output ctx = 0x%llx (dma)\n", slot_id, |
d115b048 | 751 | (unsigned long long)dev->out_ctx->dma); |
3ffbba95 SS |
752 | |
753 | /* Allocate the (input) device context for address device command */ | |
d115b048 | 754 | dev->in_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT, flags); |
3ffbba95 SS |
755 | if (!dev->in_ctx) |
756 | goto fail; | |
d115b048 | 757 | |
700e2052 | 758 | xhci_dbg(xhci, "Slot %d input ctx = 0x%llx (dma)\n", slot_id, |
d115b048 | 759 | (unsigned long long)dev->in_ctx->dma); |
3ffbba95 | 760 | |
6f5165cf SS |
761 | /* Initialize the cancellation list and watchdog timers for each ep */ |
762 | for (i = 0; i < 31; i++) { | |
763 | xhci_init_endpoint_timer(xhci, &dev->eps[i]); | |
63a0d9ab | 764 | INIT_LIST_HEAD(&dev->eps[i].cancelled_td_list); |
6f5165cf | 765 | } |
63a0d9ab | 766 | |
3ffbba95 | 767 | /* Allocate endpoint 0 ring */ |
63a0d9ab SS |
768 | dev->eps[0].ring = xhci_ring_alloc(xhci, 1, true, flags); |
769 | if (!dev->eps[0].ring) | |
3ffbba95 SS |
770 | goto fail; |
771 | ||
74f9fe21 SS |
772 | /* Allocate pointers to the ring cache */ |
773 | dev->ring_cache = kzalloc( | |
774 | sizeof(struct xhci_ring *)*XHCI_MAX_RINGS_CACHED, | |
775 | flags); | |
776 | if (!dev->ring_cache) | |
777 | goto fail; | |
778 | dev->num_rings_cached = 0; | |
779 | ||
f94e0186 | 780 | init_completion(&dev->cmd_completion); |
913a8a34 | 781 | INIT_LIST_HEAD(&dev->cmd_list); |
64927730 | 782 | dev->udev = udev; |
f94e0186 | 783 | |
28c2d2ef | 784 | /* Point to output device context in dcbaa. */ |
28ccd296 | 785 | xhci->dcbaa->dev_context_ptrs[slot_id] = cpu_to_le64(dev->out_ctx->dma); |
700e2052 | 786 | xhci_dbg(xhci, "Set slot id %d dcbaa entry %p to 0x%llx\n", |
28ccd296 ME |
787 | slot_id, |
788 | &xhci->dcbaa->dev_context_ptrs[slot_id], | |
789 | (unsigned long long) le64_to_cpu(xhci->dcbaa->dev_context_ptrs[slot_id])); | |
3ffbba95 SS |
790 | |
791 | return 1; | |
792 | fail: | |
793 | xhci_free_virt_device(xhci, slot_id); | |
794 | return 0; | |
795 | } | |
796 | ||
2d1ee590 SS |
797 | void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci, |
798 | struct usb_device *udev) | |
799 | { | |
800 | struct xhci_virt_device *virt_dev; | |
801 | struct xhci_ep_ctx *ep0_ctx; | |
802 | struct xhci_ring *ep_ring; | |
803 | ||
804 | virt_dev = xhci->devs[udev->slot_id]; | |
805 | ep0_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, 0); | |
806 | ep_ring = virt_dev->eps[0].ring; | |
807 | /* | |
808 | * FIXME we don't keep track of the dequeue pointer very well after a | |
809 | * Set TR dequeue pointer, so we're setting the dequeue pointer of the | |
810 | * host to our enqueue pointer. This should only be called after a | |
811 | * configured device has reset, so all control transfers should have | |
812 | * been completed or cancelled before the reset. | |
813 | */ | |
28ccd296 ME |
814 | ep0_ctx->deq = cpu_to_le64(xhci_trb_virt_to_dma(ep_ring->enq_seg, |
815 | ep_ring->enqueue) | |
816 | | ep_ring->cycle_state); | |
2d1ee590 SS |
817 | } |
818 | ||
f6ff0ac8 SS |
819 | /* |
820 | * The xHCI roothub may have ports of differing speeds in any order in the port | |
821 | * status registers. xhci->port_array provides an array of the port speed for | |
822 | * each offset into the port status registers. | |
823 | * | |
824 | * The xHCI hardware wants to know the roothub port number that the USB device | |
825 | * is attached to (or the roothub port its ancestor hub is attached to). All we | |
826 | * know is the index of that port under either the USB 2.0 or the USB 3.0 | |
827 | * roothub, but that doesn't give us the real index into the HW port status | |
828 | * registers. Scan through the xHCI roothub port array, looking for the Nth | |
829 | * entry of the correct port speed. Return the port number of that entry. | |
830 | */ | |
831 | static u32 xhci_find_real_port_number(struct xhci_hcd *xhci, | |
832 | struct usb_device *udev) | |
833 | { | |
834 | struct usb_device *top_dev; | |
835 | unsigned int num_similar_speed_ports; | |
836 | unsigned int faked_port_num; | |
837 | int i; | |
838 | ||
839 | for (top_dev = udev; top_dev->parent && top_dev->parent->parent; | |
840 | top_dev = top_dev->parent) | |
841 | /* Found device below root hub */; | |
842 | faked_port_num = top_dev->portnum; | |
843 | for (i = 0, num_similar_speed_ports = 0; | |
844 | i < HCS_MAX_PORTS(xhci->hcs_params1); i++) { | |
845 | u8 port_speed = xhci->port_array[i]; | |
846 | ||
847 | /* | |
848 | * Skip ports that don't have known speeds, or have duplicate | |
849 | * Extended Capabilities port speed entries. | |
850 | */ | |
22e04870 | 851 | if (port_speed == 0 || port_speed == DUPLICATE_ENTRY) |
f6ff0ac8 SS |
852 | continue; |
853 | ||
854 | /* | |
855 | * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and | |
856 | * 1.1 ports are under the USB 2.0 hub. If the port speed | |
857 | * matches the device speed, it's a similar speed port. | |
858 | */ | |
859 | if ((port_speed == 0x03) == (udev->speed == USB_SPEED_SUPER)) | |
860 | num_similar_speed_ports++; | |
861 | if (num_similar_speed_ports == faked_port_num) | |
862 | /* Roothub ports are numbered from 1 to N */ | |
863 | return i+1; | |
864 | } | |
865 | return 0; | |
866 | } | |
867 | ||
3ffbba95 SS |
868 | /* Setup an xHCI virtual device for a Set Address command */ |
869 | int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev) | |
870 | { | |
871 | struct xhci_virt_device *dev; | |
872 | struct xhci_ep_ctx *ep0_ctx; | |
d115b048 JY |
873 | struct xhci_slot_ctx *slot_ctx; |
874 | struct xhci_input_control_ctx *ctrl_ctx; | |
f6ff0ac8 SS |
875 | u32 port_num; |
876 | struct usb_device *top_dev; | |
3ffbba95 SS |
877 | |
878 | dev = xhci->devs[udev->slot_id]; | |
879 | /* Slot ID 0 is reserved */ | |
880 | if (udev->slot_id == 0 || !dev) { | |
881 | xhci_warn(xhci, "Slot ID %d is not assigned to this device\n", | |
882 | udev->slot_id); | |
883 | return -EINVAL; | |
884 | } | |
d115b048 JY |
885 | ep0_ctx = xhci_get_ep_ctx(xhci, dev->in_ctx, 0); |
886 | ctrl_ctx = xhci_get_input_control_ctx(xhci, dev->in_ctx); | |
887 | slot_ctx = xhci_get_slot_ctx(xhci, dev->in_ctx); | |
3ffbba95 SS |
888 | |
889 | /* 2) New slot context and endpoint 0 context are valid*/ | |
28ccd296 | 890 | ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG); |
3ffbba95 SS |
891 | |
892 | /* 3) Only the control endpoint is valid - one endpoint context */ | |
28ccd296 | 893 | slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1) | (u32) udev->route); |
3ffbba95 SS |
894 | switch (udev->speed) { |
895 | case USB_SPEED_SUPER: | |
28ccd296 | 896 | slot_ctx->dev_info |= cpu_to_le32((u32) SLOT_SPEED_SS); |
3ffbba95 SS |
897 | break; |
898 | case USB_SPEED_HIGH: | |
28ccd296 | 899 | slot_ctx->dev_info |= cpu_to_le32((u32) SLOT_SPEED_HS); |
3ffbba95 SS |
900 | break; |
901 | case USB_SPEED_FULL: | |
28ccd296 | 902 | slot_ctx->dev_info |= cpu_to_le32((u32) SLOT_SPEED_FS); |
3ffbba95 SS |
903 | break; |
904 | case USB_SPEED_LOW: | |
28ccd296 | 905 | slot_ctx->dev_info |= cpu_to_le32((u32) SLOT_SPEED_LS); |
3ffbba95 | 906 | break; |
551cdbbe | 907 | case USB_SPEED_WIRELESS: |
3ffbba95 SS |
908 | xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n"); |
909 | return -EINVAL; | |
910 | break; | |
911 | default: | |
912 | /* Speed was set earlier, this shouldn't happen. */ | |
913 | BUG(); | |
914 | } | |
915 | /* Find the root hub port this device is under */ | |
f6ff0ac8 SS |
916 | port_num = xhci_find_real_port_number(xhci, udev); |
917 | if (!port_num) | |
918 | return -EINVAL; | |
28ccd296 | 919 | slot_ctx->dev_info2 |= cpu_to_le32((u32) ROOT_HUB_PORT(port_num)); |
f6ff0ac8 | 920 | /* Set the port number in the virtual_device to the faked port number */ |
3ffbba95 SS |
921 | for (top_dev = udev; top_dev->parent && top_dev->parent->parent; |
922 | top_dev = top_dev->parent) | |
923 | /* Found device below root hub */; | |
be88fe4f | 924 | dev->port = top_dev->portnum; |
f6ff0ac8 SS |
925 | xhci_dbg(xhci, "Set root hub portnum to %d\n", port_num); |
926 | xhci_dbg(xhci, "Set fake root hub portnum to %d\n", dev->port); | |
3ffbba95 | 927 | |
aa1b13ef SS |
928 | /* Is this a LS/FS device under an external HS hub? */ |
929 | if (udev->tt && udev->tt->hub->parent) { | |
28ccd296 ME |
930 | slot_ctx->tt_info = cpu_to_le32(udev->tt->hub->slot_id | |
931 | (udev->ttport << 8)); | |
07b6de10 | 932 | if (udev->tt->multi) |
28ccd296 | 933 | slot_ctx->dev_info |= cpu_to_le32(DEV_MTT); |
3ffbba95 | 934 | } |
700e2052 | 935 | xhci_dbg(xhci, "udev->tt = %p\n", udev->tt); |
3ffbba95 SS |
936 | xhci_dbg(xhci, "udev->ttport = 0x%x\n", udev->ttport); |
937 | ||
938 | /* Step 4 - ring already allocated */ | |
939 | /* Step 5 */ | |
28ccd296 | 940 | ep0_ctx->ep_info2 = cpu_to_le32(EP_TYPE(CTRL_EP)); |
3ffbba95 | 941 | /* |
3ffbba95 SS |
942 | * XXX: Not sure about wireless USB devices. |
943 | */ | |
47aded8a SS |
944 | switch (udev->speed) { |
945 | case USB_SPEED_SUPER: | |
28ccd296 | 946 | ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(512)); |
47aded8a SS |
947 | break; |
948 | case USB_SPEED_HIGH: | |
949 | /* USB core guesses at a 64-byte max packet first for FS devices */ | |
950 | case USB_SPEED_FULL: | |
28ccd296 | 951 | ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(64)); |
47aded8a SS |
952 | break; |
953 | case USB_SPEED_LOW: | |
28ccd296 | 954 | ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(8)); |
47aded8a | 955 | break; |
551cdbbe | 956 | case USB_SPEED_WIRELESS: |
47aded8a SS |
957 | xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n"); |
958 | return -EINVAL; | |
959 | break; | |
960 | default: | |
961 | /* New speed? */ | |
962 | BUG(); | |
963 | } | |
3ffbba95 | 964 | /* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */ |
28ccd296 | 965 | ep0_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(0) | ERROR_COUNT(3)); |
3ffbba95 | 966 | |
28ccd296 ME |
967 | ep0_ctx->deq = cpu_to_le64(dev->eps[0].ring->first_seg->dma | |
968 | dev->eps[0].ring->cycle_state); | |
3ffbba95 SS |
969 | |
970 | /* Steps 7 and 8 were done in xhci_alloc_virt_device() */ | |
971 | ||
972 | return 0; | |
973 | } | |
974 | ||
dfa49c4a DT |
975 | /* |
976 | * Convert interval expressed as 2^(bInterval - 1) == interval into | |
977 | * straight exponent value 2^n == interval. | |
978 | * | |
979 | */ | |
980 | static unsigned int xhci_parse_exponent_interval(struct usb_device *udev, | |
981 | struct usb_host_endpoint *ep) | |
982 | { | |
983 | unsigned int interval; | |
984 | ||
985 | interval = clamp_val(ep->desc.bInterval, 1, 16) - 1; | |
986 | if (interval != ep->desc.bInterval - 1) | |
987 | dev_warn(&udev->dev, | |
cd3c18ba | 988 | "ep %#x - rounding interval to %d %sframes\n", |
dfa49c4a | 989 | ep->desc.bEndpointAddress, |
cd3c18ba DT |
990 | 1 << interval, |
991 | udev->speed == USB_SPEED_FULL ? "" : "micro"); | |
992 | ||
993 | if (udev->speed == USB_SPEED_FULL) { | |
994 | /* | |
995 | * Full speed isoc endpoints specify interval in frames, | |
996 | * not microframes. We are using microframes everywhere, | |
997 | * so adjust accordingly. | |
998 | */ | |
999 | interval += 3; /* 1 frame = 2^3 uframes */ | |
1000 | } | |
dfa49c4a DT |
1001 | |
1002 | return interval; | |
1003 | } | |
1004 | ||
1005 | /* | |
1006 | * Convert bInterval expressed in frames (in 1-255 range) to exponent of | |
1007 | * microframes, rounded down to nearest power of 2. | |
1008 | */ | |
1009 | static unsigned int xhci_parse_frame_interval(struct usb_device *udev, | |
1010 | struct usb_host_endpoint *ep) | |
1011 | { | |
1012 | unsigned int interval; | |
1013 | ||
1014 | interval = fls(8 * ep->desc.bInterval) - 1; | |
1015 | interval = clamp_val(interval, 3, 10); | |
1016 | if ((1 << interval) != 8 * ep->desc.bInterval) | |
1017 | dev_warn(&udev->dev, | |
1018 | "ep %#x - rounding interval to %d microframes, ep desc says %d microframes\n", | |
1019 | ep->desc.bEndpointAddress, | |
1020 | 1 << interval, | |
1021 | 8 * ep->desc.bInterval); | |
1022 | ||
1023 | return interval; | |
1024 | } | |
1025 | ||
f94e0186 SS |
1026 | /* Return the polling or NAK interval. |
1027 | * | |
1028 | * The polling interval is expressed in "microframes". If xHCI's Interval field | |
1029 | * is set to N, it will service the endpoint every 2^(Interval)*125us. | |
1030 | * | |
1031 | * The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval | |
1032 | * is set to 0. | |
1033 | */ | |
575688e1 | 1034 | static unsigned int xhci_get_endpoint_interval(struct usb_device *udev, |
f94e0186 SS |
1035 | struct usb_host_endpoint *ep) |
1036 | { | |
1037 | unsigned int interval = 0; | |
1038 | ||
1039 | switch (udev->speed) { | |
1040 | case USB_SPEED_HIGH: | |
1041 | /* Max NAK rate */ | |
1042 | if (usb_endpoint_xfer_control(&ep->desc) || | |
dfa49c4a | 1043 | usb_endpoint_xfer_bulk(&ep->desc)) { |
f94e0186 | 1044 | interval = ep->desc.bInterval; |
dfa49c4a DT |
1045 | break; |
1046 | } | |
f94e0186 | 1047 | /* Fall through - SS and HS isoc/int have same decoding */ |
dfa49c4a | 1048 | |
f94e0186 SS |
1049 | case USB_SPEED_SUPER: |
1050 | if (usb_endpoint_xfer_int(&ep->desc) || | |
dfa49c4a DT |
1051 | usb_endpoint_xfer_isoc(&ep->desc)) { |
1052 | interval = xhci_parse_exponent_interval(udev, ep); | |
f94e0186 SS |
1053 | } |
1054 | break; | |
dfa49c4a | 1055 | |
f94e0186 | 1056 | case USB_SPEED_FULL: |
b513d447 | 1057 | if (usb_endpoint_xfer_isoc(&ep->desc)) { |
dfa49c4a DT |
1058 | interval = xhci_parse_exponent_interval(udev, ep); |
1059 | break; | |
1060 | } | |
1061 | /* | |
b513d447 | 1062 | * Fall through for interrupt endpoint interval decoding |
dfa49c4a DT |
1063 | * since it uses the same rules as low speed interrupt |
1064 | * endpoints. | |
1065 | */ | |
1066 | ||
f94e0186 SS |
1067 | case USB_SPEED_LOW: |
1068 | if (usb_endpoint_xfer_int(&ep->desc) || | |
dfa49c4a DT |
1069 | usb_endpoint_xfer_isoc(&ep->desc)) { |
1070 | ||
1071 | interval = xhci_parse_frame_interval(udev, ep); | |
f94e0186 SS |
1072 | } |
1073 | break; | |
dfa49c4a | 1074 | |
f94e0186 SS |
1075 | default: |
1076 | BUG(); | |
1077 | } | |
1078 | return EP_INTERVAL(interval); | |
1079 | } | |
1080 | ||
c30c791c | 1081 | /* The "Mult" field in the endpoint context is only set for SuperSpeed isoc eps. |
1cf62246 SS |
1082 | * High speed endpoint descriptors can define "the number of additional |
1083 | * transaction opportunities per microframe", but that goes in the Max Burst | |
1084 | * endpoint context field. | |
1085 | */ | |
575688e1 | 1086 | static u32 xhci_get_endpoint_mult(struct usb_device *udev, |
1cf62246 SS |
1087 | struct usb_host_endpoint *ep) |
1088 | { | |
c30c791c SS |
1089 | if (udev->speed != USB_SPEED_SUPER || |
1090 | !usb_endpoint_xfer_isoc(&ep->desc)) | |
1cf62246 | 1091 | return 0; |
842f1690 | 1092 | return ep->ss_ep_comp.bmAttributes; |
1cf62246 SS |
1093 | } |
1094 | ||
575688e1 | 1095 | static u32 xhci_get_endpoint_type(struct usb_device *udev, |
f94e0186 SS |
1096 | struct usb_host_endpoint *ep) |
1097 | { | |
1098 | int in; | |
1099 | u32 type; | |
1100 | ||
1101 | in = usb_endpoint_dir_in(&ep->desc); | |
1102 | if (usb_endpoint_xfer_control(&ep->desc)) { | |
1103 | type = EP_TYPE(CTRL_EP); | |
1104 | } else if (usb_endpoint_xfer_bulk(&ep->desc)) { | |
1105 | if (in) | |
1106 | type = EP_TYPE(BULK_IN_EP); | |
1107 | else | |
1108 | type = EP_TYPE(BULK_OUT_EP); | |
1109 | } else if (usb_endpoint_xfer_isoc(&ep->desc)) { | |
1110 | if (in) | |
1111 | type = EP_TYPE(ISOC_IN_EP); | |
1112 | else | |
1113 | type = EP_TYPE(ISOC_OUT_EP); | |
1114 | } else if (usb_endpoint_xfer_int(&ep->desc)) { | |
1115 | if (in) | |
1116 | type = EP_TYPE(INT_IN_EP); | |
1117 | else | |
1118 | type = EP_TYPE(INT_OUT_EP); | |
1119 | } else { | |
1120 | BUG(); | |
1121 | } | |
1122 | return type; | |
1123 | } | |
1124 | ||
9238f25d SS |
1125 | /* Return the maximum endpoint service interval time (ESIT) payload. |
1126 | * Basically, this is the maxpacket size, multiplied by the burst size | |
1127 | * and mult size. | |
1128 | */ | |
575688e1 | 1129 | static u32 xhci_get_max_esit_payload(struct xhci_hcd *xhci, |
9238f25d SS |
1130 | struct usb_device *udev, |
1131 | struct usb_host_endpoint *ep) | |
1132 | { | |
1133 | int max_burst; | |
1134 | int max_packet; | |
1135 | ||
1136 | /* Only applies for interrupt or isochronous endpoints */ | |
1137 | if (usb_endpoint_xfer_control(&ep->desc) || | |
1138 | usb_endpoint_xfer_bulk(&ep->desc)) | |
1139 | return 0; | |
1140 | ||
842f1690 | 1141 | if (udev->speed == USB_SPEED_SUPER) |
64b3c304 | 1142 | return le16_to_cpu(ep->ss_ep_comp.wBytesPerInterval); |
9238f25d | 1143 | |
28ccd296 ME |
1144 | max_packet = GET_MAX_PACKET(le16_to_cpu(ep->desc.wMaxPacketSize)); |
1145 | max_burst = (le16_to_cpu(ep->desc.wMaxPacketSize) & 0x1800) >> 11; | |
9238f25d SS |
1146 | /* A 0 in max burst means 1 transfer per ESIT */ |
1147 | return max_packet * (max_burst + 1); | |
1148 | } | |
1149 | ||
8df75f42 SS |
1150 | /* Set up an endpoint with one ring segment. Do not allocate stream rings. |
1151 | * Drivers will have to call usb_alloc_streams() to do that. | |
1152 | */ | |
f94e0186 SS |
1153 | int xhci_endpoint_init(struct xhci_hcd *xhci, |
1154 | struct xhci_virt_device *virt_dev, | |
1155 | struct usb_device *udev, | |
f88ba78d SS |
1156 | struct usb_host_endpoint *ep, |
1157 | gfp_t mem_flags) | |
f94e0186 SS |
1158 | { |
1159 | unsigned int ep_index; | |
1160 | struct xhci_ep_ctx *ep_ctx; | |
1161 | struct xhci_ring *ep_ring; | |
1162 | unsigned int max_packet; | |
1163 | unsigned int max_burst; | |
9238f25d | 1164 | u32 max_esit_payload; |
f94e0186 SS |
1165 | |
1166 | ep_index = xhci_get_endpoint_index(&ep->desc); | |
d115b048 | 1167 | ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index); |
f94e0186 SS |
1168 | |
1169 | /* Set up the endpoint ring */ | |
a061a5a0 AX |
1170 | /* |
1171 | * Isochronous endpoint ring needs bigger size because one isoc URB | |
1172 | * carries multiple packets and it will insert multiple tds to the | |
1173 | * ring. | |
1174 | * This should be replaced with dynamic ring resizing in the future. | |
1175 | */ | |
1176 | if (usb_endpoint_xfer_isoc(&ep->desc)) | |
1177 | virt_dev->eps[ep_index].new_ring = | |
1178 | xhci_ring_alloc(xhci, 8, true, mem_flags); | |
1179 | else | |
1180 | virt_dev->eps[ep_index].new_ring = | |
1181 | xhci_ring_alloc(xhci, 1, true, mem_flags); | |
74f9fe21 SS |
1182 | if (!virt_dev->eps[ep_index].new_ring) { |
1183 | /* Attempt to use the ring cache */ | |
1184 | if (virt_dev->num_rings_cached == 0) | |
1185 | return -ENOMEM; | |
1186 | virt_dev->eps[ep_index].new_ring = | |
1187 | virt_dev->ring_cache[virt_dev->num_rings_cached]; | |
1188 | virt_dev->ring_cache[virt_dev->num_rings_cached] = NULL; | |
1189 | virt_dev->num_rings_cached--; | |
1190 | xhci_reinit_cached_ring(xhci, virt_dev->eps[ep_index].new_ring); | |
1191 | } | |
d18240db | 1192 | virt_dev->eps[ep_index].skip = false; |
63a0d9ab | 1193 | ep_ring = virt_dev->eps[ep_index].new_ring; |
28ccd296 | 1194 | ep_ctx->deq = cpu_to_le64(ep_ring->first_seg->dma | ep_ring->cycle_state); |
f94e0186 | 1195 | |
28ccd296 ME |
1196 | ep_ctx->ep_info = cpu_to_le32(xhci_get_endpoint_interval(udev, ep) |
1197 | | EP_MULT(xhci_get_endpoint_mult(udev, ep))); | |
f94e0186 SS |
1198 | |
1199 | /* FIXME dig Mult and streams info out of ep companion desc */ | |
1200 | ||
47692d17 | 1201 | /* Allow 3 retries for everything but isoc; |
7b1fc2ea | 1202 | * CErr shall be set to 0 for Isoch endpoints. |
47692d17 | 1203 | */ |
f94e0186 | 1204 | if (!usb_endpoint_xfer_isoc(&ep->desc)) |
28ccd296 | 1205 | ep_ctx->ep_info2 = cpu_to_le32(ERROR_COUNT(3)); |
f94e0186 | 1206 | else |
7b1fc2ea | 1207 | ep_ctx->ep_info2 = cpu_to_le32(ERROR_COUNT(0)); |
f94e0186 | 1208 | |
28ccd296 | 1209 | ep_ctx->ep_info2 |= cpu_to_le32(xhci_get_endpoint_type(udev, ep)); |
f94e0186 SS |
1210 | |
1211 | /* Set the max packet size and max burst */ | |
1212 | switch (udev->speed) { | |
1213 | case USB_SPEED_SUPER: | |
28ccd296 ME |
1214 | max_packet = le16_to_cpu(ep->desc.wMaxPacketSize); |
1215 | ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet)); | |
b10de142 | 1216 | /* dig out max burst from ep companion desc */ |
842f1690 AS |
1217 | max_packet = ep->ss_ep_comp.bMaxBurst; |
1218 | if (!max_packet) | |
1219 | xhci_warn(xhci, "WARN no SS endpoint bMaxBurst\n"); | |
28ccd296 | 1220 | ep_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(max_packet)); |
f94e0186 SS |
1221 | break; |
1222 | case USB_SPEED_HIGH: | |
1223 | /* bits 11:12 specify the number of additional transaction | |
1224 | * opportunities per microframe (USB 2.0, section 9.6.6) | |
1225 | */ | |
1226 | if (usb_endpoint_xfer_isoc(&ep->desc) || | |
1227 | usb_endpoint_xfer_int(&ep->desc)) { | |
28ccd296 ME |
1228 | max_burst = (le16_to_cpu(ep->desc.wMaxPacketSize) |
1229 | & 0x1800) >> 11; | |
1230 | ep_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(max_burst)); | |
f94e0186 SS |
1231 | } |
1232 | /* Fall through */ | |
1233 | case USB_SPEED_FULL: | |
1234 | case USB_SPEED_LOW: | |
28ccd296 ME |
1235 | max_packet = GET_MAX_PACKET(le16_to_cpu(ep->desc.wMaxPacketSize)); |
1236 | ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet)); | |
f94e0186 SS |
1237 | break; |
1238 | default: | |
1239 | BUG(); | |
1240 | } | |
9238f25d | 1241 | max_esit_payload = xhci_get_max_esit_payload(xhci, udev, ep); |
28ccd296 | 1242 | ep_ctx->tx_info = cpu_to_le32(MAX_ESIT_PAYLOAD_FOR_EP(max_esit_payload)); |
9238f25d SS |
1243 | |
1244 | /* | |
1245 | * XXX no idea how to calculate the average TRB buffer length for bulk | |
1246 | * endpoints, as the driver gives us no clue how big each scatter gather | |
1247 | * list entry (or buffer) is going to be. | |
1248 | * | |
1249 | * For isochronous and interrupt endpoints, we set it to the max | |
1250 | * available, until we have new API in the USB core to allow drivers to | |
1251 | * declare how much bandwidth they actually need. | |
1252 | * | |
1253 | * Normally, it would be calculated by taking the total of the buffer | |
1254 | * lengths in the TD and then dividing by the number of TRBs in a TD, | |
1255 | * including link TRBs, No-op TRBs, and Event data TRBs. Since we don't | |
1256 | * use Event Data TRBs, and we don't chain in a link TRB on short | |
1257 | * transfers, we're basically dividing by 1. | |
51eb01a7 AX |
1258 | * |
1259 | * xHCI 1.0 specification indicates that the Average TRB Length should | |
1260 | * be set to 8 for control endpoints. | |
9238f25d | 1261 | */ |
51eb01a7 AX |
1262 | if (usb_endpoint_xfer_control(&ep->desc) && xhci->hci_version == 0x100) |
1263 | ep_ctx->tx_info |= cpu_to_le32(AVG_TRB_LENGTH_FOR_EP(8)); | |
1264 | else | |
1265 | ep_ctx->tx_info |= | |
1266 | cpu_to_le32(AVG_TRB_LENGTH_FOR_EP(max_esit_payload)); | |
9238f25d | 1267 | |
f94e0186 SS |
1268 | /* FIXME Debug endpoint context */ |
1269 | return 0; | |
1270 | } | |
1271 | ||
1272 | void xhci_endpoint_zero(struct xhci_hcd *xhci, | |
1273 | struct xhci_virt_device *virt_dev, | |
1274 | struct usb_host_endpoint *ep) | |
1275 | { | |
1276 | unsigned int ep_index; | |
1277 | struct xhci_ep_ctx *ep_ctx; | |
1278 | ||
1279 | ep_index = xhci_get_endpoint_index(&ep->desc); | |
d115b048 | 1280 | ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index); |
f94e0186 SS |
1281 | |
1282 | ep_ctx->ep_info = 0; | |
1283 | ep_ctx->ep_info2 = 0; | |
8e595a5d | 1284 | ep_ctx->deq = 0; |
f94e0186 SS |
1285 | ep_ctx->tx_info = 0; |
1286 | /* Don't free the endpoint ring until the set interface or configuration | |
1287 | * request succeeds. | |
1288 | */ | |
1289 | } | |
1290 | ||
f2217e8e SS |
1291 | /* Copy output xhci_ep_ctx to the input xhci_ep_ctx copy. |
1292 | * Useful when you want to change one particular aspect of the endpoint and then | |
1293 | * issue a configure endpoint command. | |
1294 | */ | |
1295 | void xhci_endpoint_copy(struct xhci_hcd *xhci, | |
913a8a34 SS |
1296 | struct xhci_container_ctx *in_ctx, |
1297 | struct xhci_container_ctx *out_ctx, | |
1298 | unsigned int ep_index) | |
f2217e8e SS |
1299 | { |
1300 | struct xhci_ep_ctx *out_ep_ctx; | |
1301 | struct xhci_ep_ctx *in_ep_ctx; | |
1302 | ||
913a8a34 SS |
1303 | out_ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index); |
1304 | in_ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index); | |
f2217e8e SS |
1305 | |
1306 | in_ep_ctx->ep_info = out_ep_ctx->ep_info; | |
1307 | in_ep_ctx->ep_info2 = out_ep_ctx->ep_info2; | |
1308 | in_ep_ctx->deq = out_ep_ctx->deq; | |
1309 | in_ep_ctx->tx_info = out_ep_ctx->tx_info; | |
1310 | } | |
1311 | ||
1312 | /* Copy output xhci_slot_ctx to the input xhci_slot_ctx. | |
1313 | * Useful when you want to change one particular aspect of the endpoint and then | |
1314 | * issue a configure endpoint command. Only the context entries field matters, | |
1315 | * but we'll copy the whole thing anyway. | |
1316 | */ | |
913a8a34 SS |
1317 | void xhci_slot_copy(struct xhci_hcd *xhci, |
1318 | struct xhci_container_ctx *in_ctx, | |
1319 | struct xhci_container_ctx *out_ctx) | |
f2217e8e SS |
1320 | { |
1321 | struct xhci_slot_ctx *in_slot_ctx; | |
1322 | struct xhci_slot_ctx *out_slot_ctx; | |
1323 | ||
913a8a34 SS |
1324 | in_slot_ctx = xhci_get_slot_ctx(xhci, in_ctx); |
1325 | out_slot_ctx = xhci_get_slot_ctx(xhci, out_ctx); | |
f2217e8e SS |
1326 | |
1327 | in_slot_ctx->dev_info = out_slot_ctx->dev_info; | |
1328 | in_slot_ctx->dev_info2 = out_slot_ctx->dev_info2; | |
1329 | in_slot_ctx->tt_info = out_slot_ctx->tt_info; | |
1330 | in_slot_ctx->dev_state = out_slot_ctx->dev_state; | |
1331 | } | |
1332 | ||
254c80a3 JY |
1333 | /* Set up the scratchpad buffer array and scratchpad buffers, if needed. */ |
1334 | static int scratchpad_alloc(struct xhci_hcd *xhci, gfp_t flags) | |
1335 | { | |
1336 | int i; | |
1337 | struct device *dev = xhci_to_hcd(xhci)->self.controller; | |
1338 | int num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2); | |
1339 | ||
1340 | xhci_dbg(xhci, "Allocating %d scratchpad buffers\n", num_sp); | |
1341 | ||
1342 | if (!num_sp) | |
1343 | return 0; | |
1344 | ||
1345 | xhci->scratchpad = kzalloc(sizeof(*xhci->scratchpad), flags); | |
1346 | if (!xhci->scratchpad) | |
1347 | goto fail_sp; | |
1348 | ||
1349 | xhci->scratchpad->sp_array = | |
1350 | pci_alloc_consistent(to_pci_dev(dev), | |
1351 | num_sp * sizeof(u64), | |
1352 | &xhci->scratchpad->sp_dma); | |
1353 | if (!xhci->scratchpad->sp_array) | |
1354 | goto fail_sp2; | |
1355 | ||
1356 | xhci->scratchpad->sp_buffers = kzalloc(sizeof(void *) * num_sp, flags); | |
1357 | if (!xhci->scratchpad->sp_buffers) | |
1358 | goto fail_sp3; | |
1359 | ||
1360 | xhci->scratchpad->sp_dma_buffers = | |
1361 | kzalloc(sizeof(dma_addr_t) * num_sp, flags); | |
1362 | ||
1363 | if (!xhci->scratchpad->sp_dma_buffers) | |
1364 | goto fail_sp4; | |
1365 | ||
28ccd296 | 1366 | xhci->dcbaa->dev_context_ptrs[0] = cpu_to_le64(xhci->scratchpad->sp_dma); |
254c80a3 JY |
1367 | for (i = 0; i < num_sp; i++) { |
1368 | dma_addr_t dma; | |
1369 | void *buf = pci_alloc_consistent(to_pci_dev(dev), | |
1370 | xhci->page_size, &dma); | |
1371 | if (!buf) | |
1372 | goto fail_sp5; | |
1373 | ||
1374 | xhci->scratchpad->sp_array[i] = dma; | |
1375 | xhci->scratchpad->sp_buffers[i] = buf; | |
1376 | xhci->scratchpad->sp_dma_buffers[i] = dma; | |
1377 | } | |
1378 | ||
1379 | return 0; | |
1380 | ||
1381 | fail_sp5: | |
1382 | for (i = i - 1; i >= 0; i--) { | |
1383 | pci_free_consistent(to_pci_dev(dev), xhci->page_size, | |
1384 | xhci->scratchpad->sp_buffers[i], | |
1385 | xhci->scratchpad->sp_dma_buffers[i]); | |
1386 | } | |
1387 | kfree(xhci->scratchpad->sp_dma_buffers); | |
1388 | ||
1389 | fail_sp4: | |
1390 | kfree(xhci->scratchpad->sp_buffers); | |
1391 | ||
1392 | fail_sp3: | |
1393 | pci_free_consistent(to_pci_dev(dev), num_sp * sizeof(u64), | |
1394 | xhci->scratchpad->sp_array, | |
1395 | xhci->scratchpad->sp_dma); | |
1396 | ||
1397 | fail_sp2: | |
1398 | kfree(xhci->scratchpad); | |
1399 | xhci->scratchpad = NULL; | |
1400 | ||
1401 | fail_sp: | |
1402 | return -ENOMEM; | |
1403 | } | |
1404 | ||
1405 | static void scratchpad_free(struct xhci_hcd *xhci) | |
1406 | { | |
1407 | int num_sp; | |
1408 | int i; | |
1409 | struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller); | |
1410 | ||
1411 | if (!xhci->scratchpad) | |
1412 | return; | |
1413 | ||
1414 | num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2); | |
1415 | ||
1416 | for (i = 0; i < num_sp; i++) { | |
1417 | pci_free_consistent(pdev, xhci->page_size, | |
1418 | xhci->scratchpad->sp_buffers[i], | |
1419 | xhci->scratchpad->sp_dma_buffers[i]); | |
1420 | } | |
1421 | kfree(xhci->scratchpad->sp_dma_buffers); | |
1422 | kfree(xhci->scratchpad->sp_buffers); | |
1423 | pci_free_consistent(pdev, num_sp * sizeof(u64), | |
1424 | xhci->scratchpad->sp_array, | |
1425 | xhci->scratchpad->sp_dma); | |
1426 | kfree(xhci->scratchpad); | |
1427 | xhci->scratchpad = NULL; | |
1428 | } | |
1429 | ||
913a8a34 | 1430 | struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci, |
a1d78c16 SS |
1431 | bool allocate_in_ctx, bool allocate_completion, |
1432 | gfp_t mem_flags) | |
913a8a34 SS |
1433 | { |
1434 | struct xhci_command *command; | |
1435 | ||
1436 | command = kzalloc(sizeof(*command), mem_flags); | |
1437 | if (!command) | |
1438 | return NULL; | |
1439 | ||
a1d78c16 SS |
1440 | if (allocate_in_ctx) { |
1441 | command->in_ctx = | |
1442 | xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT, | |
1443 | mem_flags); | |
1444 | if (!command->in_ctx) { | |
1445 | kfree(command); | |
1446 | return NULL; | |
1447 | } | |
06e18291 | 1448 | } |
913a8a34 SS |
1449 | |
1450 | if (allocate_completion) { | |
1451 | command->completion = | |
1452 | kzalloc(sizeof(struct completion), mem_flags); | |
1453 | if (!command->completion) { | |
1454 | xhci_free_container_ctx(xhci, command->in_ctx); | |
06e18291 | 1455 | kfree(command); |
913a8a34 SS |
1456 | return NULL; |
1457 | } | |
1458 | init_completion(command->completion); | |
1459 | } | |
1460 | ||
1461 | command->status = 0; | |
1462 | INIT_LIST_HEAD(&command->cmd_list); | |
1463 | return command; | |
1464 | } | |
1465 | ||
8e51adcc AX |
1466 | void xhci_urb_free_priv(struct xhci_hcd *xhci, struct urb_priv *urb_priv) |
1467 | { | |
1468 | int last; | |
1469 | ||
1470 | if (!urb_priv) | |
1471 | return; | |
1472 | ||
1473 | last = urb_priv->length - 1; | |
1474 | if (last >= 0) { | |
1475 | int i; | |
1476 | for (i = 0; i <= last; i++) | |
1477 | kfree(urb_priv->td[i]); | |
1478 | } | |
1479 | kfree(urb_priv); | |
1480 | } | |
1481 | ||
913a8a34 SS |
1482 | void xhci_free_command(struct xhci_hcd *xhci, |
1483 | struct xhci_command *command) | |
1484 | { | |
1485 | xhci_free_container_ctx(xhci, | |
1486 | command->in_ctx); | |
1487 | kfree(command->completion); | |
1488 | kfree(command); | |
1489 | } | |
1490 | ||
66d4eadd SS |
1491 | void xhci_mem_cleanup(struct xhci_hcd *xhci) |
1492 | { | |
0ebbab37 SS |
1493 | struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller); |
1494 | int size; | |
3ffbba95 | 1495 | int i; |
0ebbab37 SS |
1496 | |
1497 | /* Free the Event Ring Segment Table and the actual Event Ring */ | |
d94c05e3 SS |
1498 | if (xhci->ir_set) { |
1499 | xhci_writel(xhci, 0, &xhci->ir_set->erst_size); | |
1500 | xhci_write_64(xhci, 0, &xhci->ir_set->erst_base); | |
1501 | xhci_write_64(xhci, 0, &xhci->ir_set->erst_dequeue); | |
1502 | } | |
0ebbab37 SS |
1503 | size = sizeof(struct xhci_erst_entry)*(xhci->erst.num_entries); |
1504 | if (xhci->erst.entries) | |
1505 | pci_free_consistent(pdev, size, | |
1506 | xhci->erst.entries, xhci->erst.erst_dma_addr); | |
1507 | xhci->erst.entries = NULL; | |
1508 | xhci_dbg(xhci, "Freed ERST\n"); | |
1509 | if (xhci->event_ring) | |
1510 | xhci_ring_free(xhci, xhci->event_ring); | |
1511 | xhci->event_ring = NULL; | |
1512 | xhci_dbg(xhci, "Freed event ring\n"); | |
1513 | ||
8e595a5d | 1514 | xhci_write_64(xhci, 0, &xhci->op_regs->cmd_ring); |
0ebbab37 SS |
1515 | if (xhci->cmd_ring) |
1516 | xhci_ring_free(xhci, xhci->cmd_ring); | |
1517 | xhci->cmd_ring = NULL; | |
1518 | xhci_dbg(xhci, "Freed command ring\n"); | |
3ffbba95 SS |
1519 | |
1520 | for (i = 1; i < MAX_HC_SLOTS; ++i) | |
1521 | xhci_free_virt_device(xhci, i); | |
1522 | ||
0ebbab37 SS |
1523 | if (xhci->segment_pool) |
1524 | dma_pool_destroy(xhci->segment_pool); | |
1525 | xhci->segment_pool = NULL; | |
1526 | xhci_dbg(xhci, "Freed segment pool\n"); | |
3ffbba95 SS |
1527 | |
1528 | if (xhci->device_pool) | |
1529 | dma_pool_destroy(xhci->device_pool); | |
1530 | xhci->device_pool = NULL; | |
1531 | xhci_dbg(xhci, "Freed device context pool\n"); | |
1532 | ||
8df75f42 SS |
1533 | if (xhci->small_streams_pool) |
1534 | dma_pool_destroy(xhci->small_streams_pool); | |
1535 | xhci->small_streams_pool = NULL; | |
1536 | xhci_dbg(xhci, "Freed small stream array pool\n"); | |
1537 | ||
1538 | if (xhci->medium_streams_pool) | |
1539 | dma_pool_destroy(xhci->medium_streams_pool); | |
1540 | xhci->medium_streams_pool = NULL; | |
1541 | xhci_dbg(xhci, "Freed medium stream array pool\n"); | |
1542 | ||
8e595a5d | 1543 | xhci_write_64(xhci, 0, &xhci->op_regs->dcbaa_ptr); |
a74588f9 SS |
1544 | if (xhci->dcbaa) |
1545 | pci_free_consistent(pdev, sizeof(*xhci->dcbaa), | |
1546 | xhci->dcbaa, xhci->dcbaa->dma); | |
1547 | xhci->dcbaa = NULL; | |
3ffbba95 | 1548 | |
5294bea4 | 1549 | scratchpad_free(xhci); |
da6699ce SS |
1550 | |
1551 | xhci->num_usb2_ports = 0; | |
1552 | xhci->num_usb3_ports = 0; | |
1553 | kfree(xhci->usb2_ports); | |
1554 | kfree(xhci->usb3_ports); | |
1555 | kfree(xhci->port_array); | |
1556 | ||
66d4eadd SS |
1557 | xhci->page_size = 0; |
1558 | xhci->page_shift = 0; | |
20b67cf5 | 1559 | xhci->bus_state[0].bus_suspended = 0; |
f6ff0ac8 | 1560 | xhci->bus_state[1].bus_suspended = 0; |
66d4eadd SS |
1561 | } |
1562 | ||
6648f29d SS |
1563 | static int xhci_test_trb_in_td(struct xhci_hcd *xhci, |
1564 | struct xhci_segment *input_seg, | |
1565 | union xhci_trb *start_trb, | |
1566 | union xhci_trb *end_trb, | |
1567 | dma_addr_t input_dma, | |
1568 | struct xhci_segment *result_seg, | |
1569 | char *test_name, int test_number) | |
1570 | { | |
1571 | unsigned long long start_dma; | |
1572 | unsigned long long end_dma; | |
1573 | struct xhci_segment *seg; | |
1574 | ||
1575 | start_dma = xhci_trb_virt_to_dma(input_seg, start_trb); | |
1576 | end_dma = xhci_trb_virt_to_dma(input_seg, end_trb); | |
1577 | ||
1578 | seg = trb_in_td(input_seg, start_trb, end_trb, input_dma); | |
1579 | if (seg != result_seg) { | |
1580 | xhci_warn(xhci, "WARN: %s TRB math test %d failed!\n", | |
1581 | test_name, test_number); | |
1582 | xhci_warn(xhci, "Tested TRB math w/ seg %p and " | |
1583 | "input DMA 0x%llx\n", | |
1584 | input_seg, | |
1585 | (unsigned long long) input_dma); | |
1586 | xhci_warn(xhci, "starting TRB %p (0x%llx DMA), " | |
1587 | "ending TRB %p (0x%llx DMA)\n", | |
1588 | start_trb, start_dma, | |
1589 | end_trb, end_dma); | |
1590 | xhci_warn(xhci, "Expected seg %p, got seg %p\n", | |
1591 | result_seg, seg); | |
1592 | return -1; | |
1593 | } | |
1594 | return 0; | |
1595 | } | |
1596 | ||
1597 | /* TRB math checks for xhci_trb_in_td(), using the command and event rings. */ | |
1598 | static int xhci_check_trb_in_td_math(struct xhci_hcd *xhci, gfp_t mem_flags) | |
1599 | { | |
1600 | struct { | |
1601 | dma_addr_t input_dma; | |
1602 | struct xhci_segment *result_seg; | |
1603 | } simple_test_vector [] = { | |
1604 | /* A zeroed DMA field should fail */ | |
1605 | { 0, NULL }, | |
1606 | /* One TRB before the ring start should fail */ | |
1607 | { xhci->event_ring->first_seg->dma - 16, NULL }, | |
1608 | /* One byte before the ring start should fail */ | |
1609 | { xhci->event_ring->first_seg->dma - 1, NULL }, | |
1610 | /* Starting TRB should succeed */ | |
1611 | { xhci->event_ring->first_seg->dma, xhci->event_ring->first_seg }, | |
1612 | /* Ending TRB should succeed */ | |
1613 | { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16, | |
1614 | xhci->event_ring->first_seg }, | |
1615 | /* One byte after the ring end should fail */ | |
1616 | { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16 + 1, NULL }, | |
1617 | /* One TRB after the ring end should fail */ | |
1618 | { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT)*16, NULL }, | |
1619 | /* An address of all ones should fail */ | |
1620 | { (dma_addr_t) (~0), NULL }, | |
1621 | }; | |
1622 | struct { | |
1623 | struct xhci_segment *input_seg; | |
1624 | union xhci_trb *start_trb; | |
1625 | union xhci_trb *end_trb; | |
1626 | dma_addr_t input_dma; | |
1627 | struct xhci_segment *result_seg; | |
1628 | } complex_test_vector [] = { | |
1629 | /* Test feeding a valid DMA address from a different ring */ | |
1630 | { .input_seg = xhci->event_ring->first_seg, | |
1631 | .start_trb = xhci->event_ring->first_seg->trbs, | |
1632 | .end_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1], | |
1633 | .input_dma = xhci->cmd_ring->first_seg->dma, | |
1634 | .result_seg = NULL, | |
1635 | }, | |
1636 | /* Test feeding a valid end TRB from a different ring */ | |
1637 | { .input_seg = xhci->event_ring->first_seg, | |
1638 | .start_trb = xhci->event_ring->first_seg->trbs, | |
1639 | .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1], | |
1640 | .input_dma = xhci->cmd_ring->first_seg->dma, | |
1641 | .result_seg = NULL, | |
1642 | }, | |
1643 | /* Test feeding a valid start and end TRB from a different ring */ | |
1644 | { .input_seg = xhci->event_ring->first_seg, | |
1645 | .start_trb = xhci->cmd_ring->first_seg->trbs, | |
1646 | .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1], | |
1647 | .input_dma = xhci->cmd_ring->first_seg->dma, | |
1648 | .result_seg = NULL, | |
1649 | }, | |
1650 | /* TRB in this ring, but after this TD */ | |
1651 | { .input_seg = xhci->event_ring->first_seg, | |
1652 | .start_trb = &xhci->event_ring->first_seg->trbs[0], | |
1653 | .end_trb = &xhci->event_ring->first_seg->trbs[3], | |
1654 | .input_dma = xhci->event_ring->first_seg->dma + 4*16, | |
1655 | .result_seg = NULL, | |
1656 | }, | |
1657 | /* TRB in this ring, but before this TD */ | |
1658 | { .input_seg = xhci->event_ring->first_seg, | |
1659 | .start_trb = &xhci->event_ring->first_seg->trbs[3], | |
1660 | .end_trb = &xhci->event_ring->first_seg->trbs[6], | |
1661 | .input_dma = xhci->event_ring->first_seg->dma + 2*16, | |
1662 | .result_seg = NULL, | |
1663 | }, | |
1664 | /* TRB in this ring, but after this wrapped TD */ | |
1665 | { .input_seg = xhci->event_ring->first_seg, | |
1666 | .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3], | |
1667 | .end_trb = &xhci->event_ring->first_seg->trbs[1], | |
1668 | .input_dma = xhci->event_ring->first_seg->dma + 2*16, | |
1669 | .result_seg = NULL, | |
1670 | }, | |
1671 | /* TRB in this ring, but before this wrapped TD */ | |
1672 | { .input_seg = xhci->event_ring->first_seg, | |
1673 | .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3], | |
1674 | .end_trb = &xhci->event_ring->first_seg->trbs[1], | |
1675 | .input_dma = xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 4)*16, | |
1676 | .result_seg = NULL, | |
1677 | }, | |
1678 | /* TRB not in this ring, and we have a wrapped TD */ | |
1679 | { .input_seg = xhci->event_ring->first_seg, | |
1680 | .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3], | |
1681 | .end_trb = &xhci->event_ring->first_seg->trbs[1], | |
1682 | .input_dma = xhci->cmd_ring->first_seg->dma + 2*16, | |
1683 | .result_seg = NULL, | |
1684 | }, | |
1685 | }; | |
1686 | ||
1687 | unsigned int num_tests; | |
1688 | int i, ret; | |
1689 | ||
e10fa478 | 1690 | num_tests = ARRAY_SIZE(simple_test_vector); |
6648f29d SS |
1691 | for (i = 0; i < num_tests; i++) { |
1692 | ret = xhci_test_trb_in_td(xhci, | |
1693 | xhci->event_ring->first_seg, | |
1694 | xhci->event_ring->first_seg->trbs, | |
1695 | &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1], | |
1696 | simple_test_vector[i].input_dma, | |
1697 | simple_test_vector[i].result_seg, | |
1698 | "Simple", i); | |
1699 | if (ret < 0) | |
1700 | return ret; | |
1701 | } | |
1702 | ||
e10fa478 | 1703 | num_tests = ARRAY_SIZE(complex_test_vector); |
6648f29d SS |
1704 | for (i = 0; i < num_tests; i++) { |
1705 | ret = xhci_test_trb_in_td(xhci, | |
1706 | complex_test_vector[i].input_seg, | |
1707 | complex_test_vector[i].start_trb, | |
1708 | complex_test_vector[i].end_trb, | |
1709 | complex_test_vector[i].input_dma, | |
1710 | complex_test_vector[i].result_seg, | |
1711 | "Complex", i); | |
1712 | if (ret < 0) | |
1713 | return ret; | |
1714 | } | |
1715 | xhci_dbg(xhci, "TRB math tests passed.\n"); | |
1716 | return 0; | |
1717 | } | |
1718 | ||
257d585a SS |
1719 | static void xhci_set_hc_event_deq(struct xhci_hcd *xhci) |
1720 | { | |
1721 | u64 temp; | |
1722 | dma_addr_t deq; | |
1723 | ||
1724 | deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg, | |
1725 | xhci->event_ring->dequeue); | |
1726 | if (deq == 0 && !in_interrupt()) | |
1727 | xhci_warn(xhci, "WARN something wrong with SW event ring " | |
1728 | "dequeue ptr.\n"); | |
1729 | /* Update HC event ring dequeue pointer */ | |
1730 | temp = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); | |
1731 | temp &= ERST_PTR_MASK; | |
1732 | /* Don't clear the EHB bit (which is RW1C) because | |
1733 | * there might be more events to service. | |
1734 | */ | |
1735 | temp &= ~ERST_EHB; | |
1736 | xhci_dbg(xhci, "// Write event ring dequeue pointer, " | |
1737 | "preserving EHB bit\n"); | |
1738 | xhci_write_64(xhci, ((u64) deq & (u64) ~ERST_PTR_MASK) | temp, | |
1739 | &xhci->ir_set->erst_dequeue); | |
1740 | } | |
1741 | ||
da6699ce | 1742 | static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int num_ports, |
28ccd296 | 1743 | __le32 __iomem *addr, u8 major_revision) |
da6699ce SS |
1744 | { |
1745 | u32 temp, port_offset, port_count; | |
1746 | int i; | |
1747 | ||
1748 | if (major_revision > 0x03) { | |
1749 | xhci_warn(xhci, "Ignoring unknown port speed, " | |
1750 | "Ext Cap %p, revision = 0x%x\n", | |
1751 | addr, major_revision); | |
1752 | /* Ignoring port protocol we can't understand. FIXME */ | |
1753 | return; | |
1754 | } | |
1755 | ||
1756 | /* Port offset and count in the third dword, see section 7.2 */ | |
1757 | temp = xhci_readl(xhci, addr + 2); | |
1758 | port_offset = XHCI_EXT_PORT_OFF(temp); | |
1759 | port_count = XHCI_EXT_PORT_COUNT(temp); | |
1760 | xhci_dbg(xhci, "Ext Cap %p, port offset = %u, " | |
1761 | "count = %u, revision = 0x%x\n", | |
1762 | addr, port_offset, port_count, major_revision); | |
1763 | /* Port count includes the current port offset */ | |
1764 | if (port_offset == 0 || (port_offset + port_count - 1) > num_ports) | |
1765 | /* WTF? "Valid values are ‘1’ to MaxPorts" */ | |
1766 | return; | |
1767 | port_offset--; | |
1768 | for (i = port_offset; i < (port_offset + port_count); i++) { | |
1769 | /* Duplicate entry. Ignore the port if the revisions differ. */ | |
1770 | if (xhci->port_array[i] != 0) { | |
1771 | xhci_warn(xhci, "Duplicate port entry, Ext Cap %p," | |
1772 | " port %u\n", addr, i); | |
1773 | xhci_warn(xhci, "Port was marked as USB %u, " | |
1774 | "duplicated as USB %u\n", | |
1775 | xhci->port_array[i], major_revision); | |
1776 | /* Only adjust the roothub port counts if we haven't | |
1777 | * found a similar duplicate. | |
1778 | */ | |
1779 | if (xhci->port_array[i] != major_revision && | |
22e04870 | 1780 | xhci->port_array[i] != DUPLICATE_ENTRY) { |
da6699ce SS |
1781 | if (xhci->port_array[i] == 0x03) |
1782 | xhci->num_usb3_ports--; | |
1783 | else | |
1784 | xhci->num_usb2_ports--; | |
22e04870 | 1785 | xhci->port_array[i] = DUPLICATE_ENTRY; |
da6699ce SS |
1786 | } |
1787 | /* FIXME: Should we disable the port? */ | |
f8bbeabc | 1788 | continue; |
da6699ce SS |
1789 | } |
1790 | xhci->port_array[i] = major_revision; | |
1791 | if (major_revision == 0x03) | |
1792 | xhci->num_usb3_ports++; | |
1793 | else | |
1794 | xhci->num_usb2_ports++; | |
1795 | } | |
1796 | /* FIXME: Should we disable ports not in the Extended Capabilities? */ | |
1797 | } | |
1798 | ||
1799 | /* | |
1800 | * Scan the Extended Capabilities for the "Supported Protocol Capabilities" that | |
1801 | * specify what speeds each port is supposed to be. We can't count on the port | |
1802 | * speed bits in the PORTSC register being correct until a device is connected, | |
1803 | * but we need to set up the two fake roothubs with the correct number of USB | |
1804 | * 3.0 and USB 2.0 ports at host controller initialization time. | |
1805 | */ | |
1806 | static int xhci_setup_port_arrays(struct xhci_hcd *xhci, gfp_t flags) | |
1807 | { | |
28ccd296 | 1808 | __le32 __iomem *addr; |
da6699ce SS |
1809 | u32 offset; |
1810 | unsigned int num_ports; | |
1811 | int i, port_index; | |
1812 | ||
1813 | addr = &xhci->cap_regs->hcc_params; | |
1814 | offset = XHCI_HCC_EXT_CAPS(xhci_readl(xhci, addr)); | |
1815 | if (offset == 0) { | |
1816 | xhci_err(xhci, "No Extended Capability registers, " | |
1817 | "unable to set up roothub.\n"); | |
1818 | return -ENODEV; | |
1819 | } | |
1820 | ||
1821 | num_ports = HCS_MAX_PORTS(xhci->hcs_params1); | |
1822 | xhci->port_array = kzalloc(sizeof(*xhci->port_array)*num_ports, flags); | |
1823 | if (!xhci->port_array) | |
1824 | return -ENOMEM; | |
1825 | ||
1826 | /* | |
1827 | * For whatever reason, the first capability offset is from the | |
1828 | * capability register base, not from the HCCPARAMS register. | |
1829 | * See section 5.3.6 for offset calculation. | |
1830 | */ | |
1831 | addr = &xhci->cap_regs->hc_capbase + offset; | |
1832 | while (1) { | |
1833 | u32 cap_id; | |
1834 | ||
1835 | cap_id = xhci_readl(xhci, addr); | |
1836 | if (XHCI_EXT_CAPS_ID(cap_id) == XHCI_EXT_CAPS_PROTOCOL) | |
1837 | xhci_add_in_port(xhci, num_ports, addr, | |
1838 | (u8) XHCI_EXT_PORT_MAJOR(cap_id)); | |
1839 | offset = XHCI_EXT_CAPS_NEXT(cap_id); | |
1840 | if (!offset || (xhci->num_usb2_ports + xhci->num_usb3_ports) | |
1841 | == num_ports) | |
1842 | break; | |
1843 | /* | |
1844 | * Once you're into the Extended Capabilities, the offset is | |
1845 | * always relative to the register holding the offset. | |
1846 | */ | |
1847 | addr += offset; | |
1848 | } | |
1849 | ||
1850 | if (xhci->num_usb2_ports == 0 && xhci->num_usb3_ports == 0) { | |
1851 | xhci_warn(xhci, "No ports on the roothubs?\n"); | |
1852 | return -ENODEV; | |
1853 | } | |
1854 | xhci_dbg(xhci, "Found %u USB 2.0 ports and %u USB 3.0 ports.\n", | |
1855 | xhci->num_usb2_ports, xhci->num_usb3_ports); | |
d30b2a20 SS |
1856 | |
1857 | /* Place limits on the number of roothub ports so that the hub | |
1858 | * descriptors aren't longer than the USB core will allocate. | |
1859 | */ | |
1860 | if (xhci->num_usb3_ports > 15) { | |
1861 | xhci_dbg(xhci, "Limiting USB 3.0 roothub ports to 15.\n"); | |
1862 | xhci->num_usb3_ports = 15; | |
1863 | } | |
1864 | if (xhci->num_usb2_ports > USB_MAXCHILDREN) { | |
1865 | xhci_dbg(xhci, "Limiting USB 2.0 roothub ports to %u.\n", | |
1866 | USB_MAXCHILDREN); | |
1867 | xhci->num_usb2_ports = USB_MAXCHILDREN; | |
1868 | } | |
1869 | ||
da6699ce SS |
1870 | /* |
1871 | * Note we could have all USB 3.0 ports, or all USB 2.0 ports. | |
1872 | * Not sure how the USB core will handle a hub with no ports... | |
1873 | */ | |
1874 | if (xhci->num_usb2_ports) { | |
1875 | xhci->usb2_ports = kmalloc(sizeof(*xhci->usb2_ports)* | |
1876 | xhci->num_usb2_ports, flags); | |
1877 | if (!xhci->usb2_ports) | |
1878 | return -ENOMEM; | |
1879 | ||
1880 | port_index = 0; | |
f8bbeabc SS |
1881 | for (i = 0; i < num_ports; i++) { |
1882 | if (xhci->port_array[i] == 0x03 || | |
1883 | xhci->port_array[i] == 0 || | |
22e04870 | 1884 | xhci->port_array[i] == DUPLICATE_ENTRY) |
f8bbeabc SS |
1885 | continue; |
1886 | ||
1887 | xhci->usb2_ports[port_index] = | |
1888 | &xhci->op_regs->port_status_base + | |
1889 | NUM_PORT_REGS*i; | |
1890 | xhci_dbg(xhci, "USB 2.0 port at index %u, " | |
1891 | "addr = %p\n", i, | |
1892 | xhci->usb2_ports[port_index]); | |
1893 | port_index++; | |
d30b2a20 SS |
1894 | if (port_index == xhci->num_usb2_ports) |
1895 | break; | |
f8bbeabc | 1896 | } |
da6699ce SS |
1897 | } |
1898 | if (xhci->num_usb3_ports) { | |
1899 | xhci->usb3_ports = kmalloc(sizeof(*xhci->usb3_ports)* | |
1900 | xhci->num_usb3_ports, flags); | |
1901 | if (!xhci->usb3_ports) | |
1902 | return -ENOMEM; | |
1903 | ||
1904 | port_index = 0; | |
1905 | for (i = 0; i < num_ports; i++) | |
1906 | if (xhci->port_array[i] == 0x03) { | |
1907 | xhci->usb3_ports[port_index] = | |
1908 | &xhci->op_regs->port_status_base + | |
1909 | NUM_PORT_REGS*i; | |
1910 | xhci_dbg(xhci, "USB 3.0 port at index %u, " | |
1911 | "addr = %p\n", i, | |
1912 | xhci->usb3_ports[port_index]); | |
1913 | port_index++; | |
d30b2a20 SS |
1914 | if (port_index == xhci->num_usb3_ports) |
1915 | break; | |
da6699ce SS |
1916 | } |
1917 | } | |
1918 | return 0; | |
1919 | } | |
6648f29d | 1920 | |
66d4eadd SS |
1921 | int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags) |
1922 | { | |
0ebbab37 SS |
1923 | dma_addr_t dma; |
1924 | struct device *dev = xhci_to_hcd(xhci)->self.controller; | |
66d4eadd | 1925 | unsigned int val, val2; |
8e595a5d | 1926 | u64 val_64; |
0ebbab37 | 1927 | struct xhci_segment *seg; |
66d4eadd SS |
1928 | u32 page_size; |
1929 | int i; | |
1930 | ||
1931 | page_size = xhci_readl(xhci, &xhci->op_regs->page_size); | |
1932 | xhci_dbg(xhci, "Supported page size register = 0x%x\n", page_size); | |
1933 | for (i = 0; i < 16; i++) { | |
1934 | if ((0x1 & page_size) != 0) | |
1935 | break; | |
1936 | page_size = page_size >> 1; | |
1937 | } | |
1938 | if (i < 16) | |
1939 | xhci_dbg(xhci, "Supported page size of %iK\n", (1 << (i+12)) / 1024); | |
1940 | else | |
1941 | xhci_warn(xhci, "WARN: no supported page size\n"); | |
1942 | /* Use 4K pages, since that's common and the minimum the HC supports */ | |
1943 | xhci->page_shift = 12; | |
1944 | xhci->page_size = 1 << xhci->page_shift; | |
1945 | xhci_dbg(xhci, "HCD page size set to %iK\n", xhci->page_size / 1024); | |
1946 | ||
1947 | /* | |
1948 | * Program the Number of Device Slots Enabled field in the CONFIG | |
1949 | * register with the max value of slots the HC can handle. | |
1950 | */ | |
1951 | val = HCS_MAX_SLOTS(xhci_readl(xhci, &xhci->cap_regs->hcs_params1)); | |
1952 | xhci_dbg(xhci, "// xHC can handle at most %d device slots.\n", | |
1953 | (unsigned int) val); | |
1954 | val2 = xhci_readl(xhci, &xhci->op_regs->config_reg); | |
1955 | val |= (val2 & ~HCS_SLOTS_MASK); | |
1956 | xhci_dbg(xhci, "// Setting Max device slots reg = 0x%x.\n", | |
1957 | (unsigned int) val); | |
1958 | xhci_writel(xhci, val, &xhci->op_regs->config_reg); | |
1959 | ||
a74588f9 SS |
1960 | /* |
1961 | * Section 5.4.8 - doorbell array must be | |
1962 | * "physically contiguous and 64-byte (cache line) aligned". | |
1963 | */ | |
1964 | xhci->dcbaa = pci_alloc_consistent(to_pci_dev(dev), | |
1965 | sizeof(*xhci->dcbaa), &dma); | |
1966 | if (!xhci->dcbaa) | |
1967 | goto fail; | |
1968 | memset(xhci->dcbaa, 0, sizeof *(xhci->dcbaa)); | |
1969 | xhci->dcbaa->dma = dma; | |
700e2052 GKH |
1970 | xhci_dbg(xhci, "// Device context base array address = 0x%llx (DMA), %p (virt)\n", |
1971 | (unsigned long long)xhci->dcbaa->dma, xhci->dcbaa); | |
8e595a5d | 1972 | xhci_write_64(xhci, dma, &xhci->op_regs->dcbaa_ptr); |
a74588f9 | 1973 | |
0ebbab37 SS |
1974 | /* |
1975 | * Initialize the ring segment pool. The ring must be a contiguous | |
1976 | * structure comprised of TRBs. The TRBs must be 16 byte aligned, | |
1977 | * however, the command ring segment needs 64-byte aligned segments, | |
1978 | * so we pick the greater alignment need. | |
1979 | */ | |
1980 | xhci->segment_pool = dma_pool_create("xHCI ring segments", dev, | |
1981 | SEGMENT_SIZE, 64, xhci->page_size); | |
d115b048 | 1982 | |
3ffbba95 | 1983 | /* See Table 46 and Note on Figure 55 */ |
3ffbba95 | 1984 | xhci->device_pool = dma_pool_create("xHCI input/output contexts", dev, |
d115b048 | 1985 | 2112, 64, xhci->page_size); |
3ffbba95 | 1986 | if (!xhci->segment_pool || !xhci->device_pool) |
0ebbab37 SS |
1987 | goto fail; |
1988 | ||
8df75f42 SS |
1989 | /* Linear stream context arrays don't have any boundary restrictions, |
1990 | * and only need to be 16-byte aligned. | |
1991 | */ | |
1992 | xhci->small_streams_pool = | |
1993 | dma_pool_create("xHCI 256 byte stream ctx arrays", | |
1994 | dev, SMALL_STREAM_ARRAY_SIZE, 16, 0); | |
1995 | xhci->medium_streams_pool = | |
1996 | dma_pool_create("xHCI 1KB stream ctx arrays", | |
1997 | dev, MEDIUM_STREAM_ARRAY_SIZE, 16, 0); | |
1998 | /* Any stream context array bigger than MEDIUM_STREAM_ARRAY_SIZE | |
1999 | * will be allocated with pci_alloc_consistent() | |
2000 | */ | |
2001 | ||
2002 | if (!xhci->small_streams_pool || !xhci->medium_streams_pool) | |
2003 | goto fail; | |
2004 | ||
0ebbab37 SS |
2005 | /* Set up the command ring to have one segments for now. */ |
2006 | xhci->cmd_ring = xhci_ring_alloc(xhci, 1, true, flags); | |
2007 | if (!xhci->cmd_ring) | |
2008 | goto fail; | |
700e2052 GKH |
2009 | xhci_dbg(xhci, "Allocated command ring at %p\n", xhci->cmd_ring); |
2010 | xhci_dbg(xhci, "First segment DMA is 0x%llx\n", | |
2011 | (unsigned long long)xhci->cmd_ring->first_seg->dma); | |
0ebbab37 SS |
2012 | |
2013 | /* Set the address in the Command Ring Control register */ | |
8e595a5d SS |
2014 | val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring); |
2015 | val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) | | |
2016 | (xhci->cmd_ring->first_seg->dma & (u64) ~CMD_RING_RSVD_BITS) | | |
0ebbab37 | 2017 | xhci->cmd_ring->cycle_state; |
8e595a5d SS |
2018 | xhci_dbg(xhci, "// Setting command ring address to 0x%x\n", val); |
2019 | xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring); | |
0ebbab37 SS |
2020 | xhci_dbg_cmd_ptrs(xhci); |
2021 | ||
2022 | val = xhci_readl(xhci, &xhci->cap_regs->db_off); | |
2023 | val &= DBOFF_MASK; | |
2024 | xhci_dbg(xhci, "// Doorbell array is located at offset 0x%x" | |
2025 | " from cap regs base addr\n", val); | |
c50a00f8 | 2026 | xhci->dba = (void __iomem *) xhci->cap_regs + val; |
0ebbab37 SS |
2027 | xhci_dbg_regs(xhci); |
2028 | xhci_print_run_regs(xhci); | |
2029 | /* Set ir_set to interrupt register set 0 */ | |
c50a00f8 | 2030 | xhci->ir_set = &xhci->run_regs->ir_set[0]; |
0ebbab37 SS |
2031 | |
2032 | /* | |
2033 | * Event ring setup: Allocate a normal ring, but also setup | |
2034 | * the event ring segment table (ERST). Section 4.9.3. | |
2035 | */ | |
2036 | xhci_dbg(xhci, "// Allocating event ring\n"); | |
2037 | xhci->event_ring = xhci_ring_alloc(xhci, ERST_NUM_SEGS, false, flags); | |
2038 | if (!xhci->event_ring) | |
2039 | goto fail; | |
6648f29d SS |
2040 | if (xhci_check_trb_in_td_math(xhci, flags) < 0) |
2041 | goto fail; | |
0ebbab37 SS |
2042 | |
2043 | xhci->erst.entries = pci_alloc_consistent(to_pci_dev(dev), | |
2044 | sizeof(struct xhci_erst_entry)*ERST_NUM_SEGS, &dma); | |
2045 | if (!xhci->erst.entries) | |
2046 | goto fail; | |
700e2052 GKH |
2047 | xhci_dbg(xhci, "// Allocated event ring segment table at 0x%llx\n", |
2048 | (unsigned long long)dma); | |
0ebbab37 SS |
2049 | |
2050 | memset(xhci->erst.entries, 0, sizeof(struct xhci_erst_entry)*ERST_NUM_SEGS); | |
2051 | xhci->erst.num_entries = ERST_NUM_SEGS; | |
2052 | xhci->erst.erst_dma_addr = dma; | |
700e2052 | 2053 | xhci_dbg(xhci, "Set ERST to 0; private num segs = %i, virt addr = %p, dma addr = 0x%llx\n", |
0ebbab37 | 2054 | xhci->erst.num_entries, |
700e2052 GKH |
2055 | xhci->erst.entries, |
2056 | (unsigned long long)xhci->erst.erst_dma_addr); | |
0ebbab37 SS |
2057 | |
2058 | /* set ring base address and size for each segment table entry */ | |
2059 | for (val = 0, seg = xhci->event_ring->first_seg; val < ERST_NUM_SEGS; val++) { | |
2060 | struct xhci_erst_entry *entry = &xhci->erst.entries[val]; | |
28ccd296 ME |
2061 | entry->seg_addr = cpu_to_le64(seg->dma); |
2062 | entry->seg_size = cpu_to_le32(TRBS_PER_SEGMENT); | |
0ebbab37 SS |
2063 | entry->rsvd = 0; |
2064 | seg = seg->next; | |
2065 | } | |
2066 | ||
2067 | /* set ERST count with the number of entries in the segment table */ | |
2068 | val = xhci_readl(xhci, &xhci->ir_set->erst_size); | |
2069 | val &= ERST_SIZE_MASK; | |
2070 | val |= ERST_NUM_SEGS; | |
2071 | xhci_dbg(xhci, "// Write ERST size = %i to ir_set 0 (some bits preserved)\n", | |
2072 | val); | |
2073 | xhci_writel(xhci, val, &xhci->ir_set->erst_size); | |
2074 | ||
2075 | xhci_dbg(xhci, "// Set ERST entries to point to event ring.\n"); | |
2076 | /* set the segment table base address */ | |
700e2052 GKH |
2077 | xhci_dbg(xhci, "// Set ERST base address for ir_set 0 = 0x%llx\n", |
2078 | (unsigned long long)xhci->erst.erst_dma_addr); | |
8e595a5d SS |
2079 | val_64 = xhci_read_64(xhci, &xhci->ir_set->erst_base); |
2080 | val_64 &= ERST_PTR_MASK; | |
2081 | val_64 |= (xhci->erst.erst_dma_addr & (u64) ~ERST_PTR_MASK); | |
2082 | xhci_write_64(xhci, val_64, &xhci->ir_set->erst_base); | |
0ebbab37 SS |
2083 | |
2084 | /* Set the event ring dequeue address */ | |
23e3be11 | 2085 | xhci_set_hc_event_deq(xhci); |
0ebbab37 | 2086 | xhci_dbg(xhci, "Wrote ERST address to ir_set 0.\n"); |
09ece30e | 2087 | xhci_print_ir_set(xhci, 0); |
0ebbab37 SS |
2088 | |
2089 | /* | |
2090 | * XXX: Might need to set the Interrupter Moderation Register to | |
2091 | * something other than the default (~1ms minimum between interrupts). | |
2092 | * See section 5.5.1.2. | |
2093 | */ | |
3ffbba95 SS |
2094 | init_completion(&xhci->addr_dev); |
2095 | for (i = 0; i < MAX_HC_SLOTS; ++i) | |
326b4810 | 2096 | xhci->devs[i] = NULL; |
f6ff0ac8 | 2097 | for (i = 0; i < USB_MAXCHILDREN; ++i) { |
20b67cf5 | 2098 | xhci->bus_state[0].resume_done[i] = 0; |
f6ff0ac8 SS |
2099 | xhci->bus_state[1].resume_done[i] = 0; |
2100 | } | |
66d4eadd | 2101 | |
254c80a3 JY |
2102 | if (scratchpad_alloc(xhci, flags)) |
2103 | goto fail; | |
da6699ce SS |
2104 | if (xhci_setup_port_arrays(xhci, flags)) |
2105 | goto fail; | |
254c80a3 | 2106 | |
66d4eadd | 2107 | return 0; |
254c80a3 | 2108 | |
66d4eadd SS |
2109 | fail: |
2110 | xhci_warn(xhci, "Couldn't initialize memory\n"); | |
2111 | xhci_mem_cleanup(xhci); | |
2112 | return -ENOMEM; | |
2113 | } |