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Commit | Line | Data |
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66d4eadd SS |
1 | /* |
2 | * xHCI host controller driver | |
3 | * | |
4 | * Copyright (C) 2008 Intel Corp. | |
5 | * | |
6 | * Author: Sarah Sharp | |
7 | * Some code borrowed from the Linux EHCI driver. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | * for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software Foundation, | |
20 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
23 | #include <linux/usb.h> | |
0ebbab37 | 24 | #include <linux/pci.h> |
5a0e3ad6 | 25 | #include <linux/slab.h> |
527c6d7f | 26 | #include <linux/dmapool.h> |
008eb957 | 27 | #include <linux/dma-mapping.h> |
66d4eadd SS |
28 | |
29 | #include "xhci.h" | |
3a7fa5be | 30 | #include "xhci-trace.h" |
66d4eadd | 31 | |
0ebbab37 SS |
32 | /* |
33 | * Allocates a generic ring segment from the ring pool, sets the dma address, | |
34 | * initializes the segment to zero, and sets the private next pointer to NULL. | |
35 | * | |
36 | * Section 4.11.1.1: | |
37 | * "All components of all Command and Transfer TRBs shall be initialized to '0'" | |
38 | */ | |
186a7ef1 AX |
39 | static struct xhci_segment *xhci_segment_alloc(struct xhci_hcd *xhci, |
40 | unsigned int cycle_state, gfp_t flags) | |
0ebbab37 SS |
41 | { |
42 | struct xhci_segment *seg; | |
43 | dma_addr_t dma; | |
186a7ef1 | 44 | int i; |
0ebbab37 SS |
45 | |
46 | seg = kzalloc(sizeof *seg, flags); | |
47 | if (!seg) | |
326b4810 | 48 | return NULL; |
0ebbab37 SS |
49 | |
50 | seg->trbs = dma_pool_alloc(xhci->segment_pool, flags, &dma); | |
51 | if (!seg->trbs) { | |
52 | kfree(seg); | |
326b4810 | 53 | return NULL; |
0ebbab37 | 54 | } |
0ebbab37 | 55 | |
eb8ccd2b | 56 | memset(seg->trbs, 0, TRB_SEGMENT_SIZE); |
186a7ef1 AX |
57 | /* If the cycle state is 0, set the cycle bit to 1 for all the TRBs */ |
58 | if (cycle_state == 0) { | |
59 | for (i = 0; i < TRBS_PER_SEGMENT; i++) | |
58719487 | 60 | seg->trbs[i].link.control |= cpu_to_le32(TRB_CYCLE); |
186a7ef1 | 61 | } |
0ebbab37 SS |
62 | seg->dma = dma; |
63 | seg->next = NULL; | |
64 | ||
65 | return seg; | |
66 | } | |
67 | ||
68 | static void xhci_segment_free(struct xhci_hcd *xhci, struct xhci_segment *seg) | |
69 | { | |
0ebbab37 | 70 | if (seg->trbs) { |
0ebbab37 SS |
71 | dma_pool_free(xhci->segment_pool, seg->trbs, seg->dma); |
72 | seg->trbs = NULL; | |
73 | } | |
0ebbab37 SS |
74 | kfree(seg); |
75 | } | |
76 | ||
70d43601 AX |
77 | static void xhci_free_segments_for_ring(struct xhci_hcd *xhci, |
78 | struct xhci_segment *first) | |
79 | { | |
80 | struct xhci_segment *seg; | |
81 | ||
82 | seg = first->next; | |
83 | while (seg != first) { | |
84 | struct xhci_segment *next = seg->next; | |
85 | xhci_segment_free(xhci, seg); | |
86 | seg = next; | |
87 | } | |
88 | xhci_segment_free(xhci, first); | |
89 | } | |
90 | ||
0ebbab37 SS |
91 | /* |
92 | * Make the prev segment point to the next segment. | |
93 | * | |
94 | * Change the last TRB in the prev segment to be a Link TRB which points to the | |
95 | * DMA address of the next segment. The caller needs to set any Link TRB | |
96 | * related flags, such as End TRB, Toggle Cycle, and no snoop. | |
97 | */ | |
98 | static void xhci_link_segments(struct xhci_hcd *xhci, struct xhci_segment *prev, | |
3b72fca0 | 99 | struct xhci_segment *next, enum xhci_ring_type type) |
0ebbab37 SS |
100 | { |
101 | u32 val; | |
102 | ||
103 | if (!prev || !next) | |
104 | return; | |
105 | prev->next = next; | |
3b72fca0 | 106 | if (type != TYPE_EVENT) { |
f5960b69 ME |
107 | prev->trbs[TRBS_PER_SEGMENT-1].link.segment_ptr = |
108 | cpu_to_le64(next->dma); | |
0ebbab37 SS |
109 | |
110 | /* Set the last TRB in the segment to have a TRB type ID of Link TRB */ | |
28ccd296 | 111 | val = le32_to_cpu(prev->trbs[TRBS_PER_SEGMENT-1].link.control); |
0ebbab37 SS |
112 | val &= ~TRB_TYPE_BITMASK; |
113 | val |= TRB_TYPE(TRB_LINK); | |
b0567b3f | 114 | /* Always set the chain bit with 0.95 hardware */ |
7e393a83 AX |
115 | /* Set chain bit for isoc rings on AMD 0.96 host */ |
116 | if (xhci_link_trb_quirk(xhci) || | |
3b72fca0 AX |
117 | (type == TYPE_ISOC && |
118 | (xhci->quirks & XHCI_AMD_0x96_HOST))) | |
b0567b3f | 119 | val |= TRB_CHAIN; |
28ccd296 | 120 | prev->trbs[TRBS_PER_SEGMENT-1].link.control = cpu_to_le32(val); |
0ebbab37 | 121 | } |
0ebbab37 SS |
122 | } |
123 | ||
8dfec614 AX |
124 | /* |
125 | * Link the ring to the new segments. | |
126 | * Set Toggle Cycle for the new ring if needed. | |
127 | */ | |
128 | static void xhci_link_rings(struct xhci_hcd *xhci, struct xhci_ring *ring, | |
129 | struct xhci_segment *first, struct xhci_segment *last, | |
130 | unsigned int num_segs) | |
131 | { | |
132 | struct xhci_segment *next; | |
133 | ||
134 | if (!ring || !first || !last) | |
135 | return; | |
136 | ||
137 | next = ring->enq_seg->next; | |
138 | xhci_link_segments(xhci, ring->enq_seg, first, ring->type); | |
139 | xhci_link_segments(xhci, last, next, ring->type); | |
140 | ring->num_segs += num_segs; | |
141 | ring->num_trbs_free += (TRBS_PER_SEGMENT - 1) * num_segs; | |
142 | ||
143 | if (ring->type != TYPE_EVENT && ring->enq_seg == ring->last_seg) { | |
144 | ring->last_seg->trbs[TRBS_PER_SEGMENT-1].link.control | |
145 | &= ~cpu_to_le32(LINK_TOGGLE); | |
146 | last->trbs[TRBS_PER_SEGMENT-1].link.control | |
147 | |= cpu_to_le32(LINK_TOGGLE); | |
148 | ring->last_seg = last; | |
149 | } | |
150 | } | |
151 | ||
0ebbab37 | 152 | /* XXX: Do we need the hcd structure in all these functions? */ |
f94e0186 | 153 | void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring) |
0ebbab37 | 154 | { |
0e6c7f74 | 155 | if (!ring) |
0ebbab37 | 156 | return; |
70d43601 AX |
157 | |
158 | if (ring->first_seg) | |
159 | xhci_free_segments_for_ring(xhci, ring->first_seg); | |
160 | ||
0ebbab37 SS |
161 | kfree(ring); |
162 | } | |
163 | ||
186a7ef1 AX |
164 | static void xhci_initialize_ring_info(struct xhci_ring *ring, |
165 | unsigned int cycle_state) | |
74f9fe21 SS |
166 | { |
167 | /* The ring is empty, so the enqueue pointer == dequeue pointer */ | |
168 | ring->enqueue = ring->first_seg->trbs; | |
169 | ring->enq_seg = ring->first_seg; | |
170 | ring->dequeue = ring->enqueue; | |
171 | ring->deq_seg = ring->first_seg; | |
172 | /* The ring is initialized to 0. The producer must write 1 to the cycle | |
173 | * bit to handover ownership of the TRB, so PCS = 1. The consumer must | |
174 | * compare CCS to the cycle bit to check ownership, so CCS = 1. | |
186a7ef1 AX |
175 | * |
176 | * New rings are initialized with cycle state equal to 1; if we are | |
177 | * handling ring expansion, set the cycle state equal to the old ring. | |
74f9fe21 | 178 | */ |
186a7ef1 | 179 | ring->cycle_state = cycle_state; |
74f9fe21 SS |
180 | /* Not necessary for new rings, but needed for re-initialized rings */ |
181 | ring->enq_updates = 0; | |
182 | ring->deq_updates = 0; | |
b008df60 AX |
183 | |
184 | /* | |
185 | * Each segment has a link TRB, and leave an extra TRB for SW | |
186 | * accounting purpose | |
187 | */ | |
188 | ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1; | |
74f9fe21 SS |
189 | } |
190 | ||
70d43601 AX |
191 | /* Allocate segments and link them for a ring */ |
192 | static int xhci_alloc_segments_for_ring(struct xhci_hcd *xhci, | |
193 | struct xhci_segment **first, struct xhci_segment **last, | |
186a7ef1 AX |
194 | unsigned int num_segs, unsigned int cycle_state, |
195 | enum xhci_ring_type type, gfp_t flags) | |
70d43601 AX |
196 | { |
197 | struct xhci_segment *prev; | |
198 | ||
186a7ef1 | 199 | prev = xhci_segment_alloc(xhci, cycle_state, flags); |
70d43601 AX |
200 | if (!prev) |
201 | return -ENOMEM; | |
202 | num_segs--; | |
203 | ||
204 | *first = prev; | |
205 | while (num_segs > 0) { | |
206 | struct xhci_segment *next; | |
207 | ||
186a7ef1 | 208 | next = xhci_segment_alloc(xhci, cycle_state, flags); |
70d43601 | 209 | if (!next) { |
68e5254a JW |
210 | prev = *first; |
211 | while (prev) { | |
212 | next = prev->next; | |
213 | xhci_segment_free(xhci, prev); | |
214 | prev = next; | |
215 | } | |
70d43601 AX |
216 | return -ENOMEM; |
217 | } | |
218 | xhci_link_segments(xhci, prev, next, type); | |
219 | ||
220 | prev = next; | |
221 | num_segs--; | |
222 | } | |
223 | xhci_link_segments(xhci, prev, *first, type); | |
224 | *last = prev; | |
225 | ||
226 | return 0; | |
227 | } | |
228 | ||
0ebbab37 SS |
229 | /** |
230 | * Create a new ring with zero or more segments. | |
231 | * | |
232 | * Link each segment together into a ring. | |
233 | * Set the end flag and the cycle toggle bit on the last segment. | |
234 | * See section 4.9.1 and figures 15 and 16. | |
235 | */ | |
236 | static struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci, | |
186a7ef1 AX |
237 | unsigned int num_segs, unsigned int cycle_state, |
238 | enum xhci_ring_type type, gfp_t flags) | |
0ebbab37 SS |
239 | { |
240 | struct xhci_ring *ring; | |
70d43601 | 241 | int ret; |
0ebbab37 SS |
242 | |
243 | ring = kzalloc(sizeof *(ring), flags); | |
0ebbab37 | 244 | if (!ring) |
326b4810 | 245 | return NULL; |
0ebbab37 | 246 | |
3fe4fe08 | 247 | ring->num_segs = num_segs; |
d0e96f5a | 248 | INIT_LIST_HEAD(&ring->td_list); |
3b72fca0 | 249 | ring->type = type; |
0ebbab37 SS |
250 | if (num_segs == 0) |
251 | return ring; | |
252 | ||
70d43601 | 253 | ret = xhci_alloc_segments_for_ring(xhci, &ring->first_seg, |
186a7ef1 | 254 | &ring->last_seg, num_segs, cycle_state, type, flags); |
70d43601 | 255 | if (ret) |
0ebbab37 | 256 | goto fail; |
0ebbab37 | 257 | |
3b72fca0 AX |
258 | /* Only event ring does not use link TRB */ |
259 | if (type != TYPE_EVENT) { | |
0ebbab37 | 260 | /* See section 4.9.2.1 and 6.4.4.1 */ |
70d43601 | 261 | ring->last_seg->trbs[TRBS_PER_SEGMENT - 1].link.control |= |
f5960b69 | 262 | cpu_to_le32(LINK_TOGGLE); |
0ebbab37 | 263 | } |
186a7ef1 | 264 | xhci_initialize_ring_info(ring, cycle_state); |
0ebbab37 SS |
265 | return ring; |
266 | ||
267 | fail: | |
68e5254a | 268 | kfree(ring); |
326b4810 | 269 | return NULL; |
0ebbab37 SS |
270 | } |
271 | ||
412566bd SS |
272 | void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci, |
273 | struct xhci_virt_device *virt_dev, | |
274 | unsigned int ep_index) | |
275 | { | |
276 | int rings_cached; | |
277 | ||
278 | rings_cached = virt_dev->num_rings_cached; | |
279 | if (rings_cached < XHCI_MAX_RINGS_CACHED) { | |
412566bd SS |
280 | virt_dev->ring_cache[rings_cached] = |
281 | virt_dev->eps[ep_index].ring; | |
30f89ca0 | 282 | virt_dev->num_rings_cached++; |
412566bd SS |
283 | xhci_dbg(xhci, "Cached old ring, " |
284 | "%d ring%s cached\n", | |
30f89ca0 SS |
285 | virt_dev->num_rings_cached, |
286 | (virt_dev->num_rings_cached > 1) ? "s" : ""); | |
412566bd SS |
287 | } else { |
288 | xhci_ring_free(xhci, virt_dev->eps[ep_index].ring); | |
289 | xhci_dbg(xhci, "Ring cache full (%d rings), " | |
290 | "freeing ring\n", | |
291 | virt_dev->num_rings_cached); | |
292 | } | |
293 | virt_dev->eps[ep_index].ring = NULL; | |
294 | } | |
295 | ||
74f9fe21 SS |
296 | /* Zero an endpoint ring (except for link TRBs) and move the enqueue and dequeue |
297 | * pointers to the beginning of the ring. | |
298 | */ | |
299 | static void xhci_reinit_cached_ring(struct xhci_hcd *xhci, | |
186a7ef1 AX |
300 | struct xhci_ring *ring, unsigned int cycle_state, |
301 | enum xhci_ring_type type) | |
74f9fe21 SS |
302 | { |
303 | struct xhci_segment *seg = ring->first_seg; | |
186a7ef1 AX |
304 | int i; |
305 | ||
74f9fe21 SS |
306 | do { |
307 | memset(seg->trbs, 0, | |
308 | sizeof(union xhci_trb)*TRBS_PER_SEGMENT); | |
186a7ef1 AX |
309 | if (cycle_state == 0) { |
310 | for (i = 0; i < TRBS_PER_SEGMENT; i++) | |
58719487 XR |
311 | seg->trbs[i].link.control |= |
312 | cpu_to_le32(TRB_CYCLE); | |
186a7ef1 | 313 | } |
74f9fe21 | 314 | /* All endpoint rings have link TRBs */ |
3b72fca0 | 315 | xhci_link_segments(xhci, seg, seg->next, type); |
74f9fe21 SS |
316 | seg = seg->next; |
317 | } while (seg != ring->first_seg); | |
3b72fca0 | 318 | ring->type = type; |
186a7ef1 | 319 | xhci_initialize_ring_info(ring, cycle_state); |
74f9fe21 SS |
320 | /* td list should be empty since all URBs have been cancelled, |
321 | * but just in case... | |
322 | */ | |
323 | INIT_LIST_HEAD(&ring->td_list); | |
324 | } | |
325 | ||
8dfec614 AX |
326 | /* |
327 | * Expand an existing ring. | |
328 | * Look for a cached ring or allocate a new ring which has same segment numbers | |
329 | * and link the two rings. | |
330 | */ | |
331 | int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring, | |
332 | unsigned int num_trbs, gfp_t flags) | |
333 | { | |
334 | struct xhci_segment *first; | |
335 | struct xhci_segment *last; | |
336 | unsigned int num_segs; | |
337 | unsigned int num_segs_needed; | |
338 | int ret; | |
339 | ||
340 | num_segs_needed = (num_trbs + (TRBS_PER_SEGMENT - 1) - 1) / | |
341 | (TRBS_PER_SEGMENT - 1); | |
342 | ||
343 | /* Allocate number of segments we needed, or double the ring size */ | |
344 | num_segs = ring->num_segs > num_segs_needed ? | |
345 | ring->num_segs : num_segs_needed; | |
346 | ||
347 | ret = xhci_alloc_segments_for_ring(xhci, &first, &last, | |
348 | num_segs, ring->cycle_state, ring->type, flags); | |
349 | if (ret) | |
350 | return -ENOMEM; | |
351 | ||
352 | xhci_link_rings(xhci, ring, first, last, num_segs); | |
68ffb011 XR |
353 | xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion, |
354 | "ring expansion succeed, now has %d segments", | |
8dfec614 AX |
355 | ring->num_segs); |
356 | ||
357 | return 0; | |
358 | } | |
359 | ||
d115b048 JY |
360 | #define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32) |
361 | ||
326b4810 | 362 | static struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci, |
d115b048 JY |
363 | int type, gfp_t flags) |
364 | { | |
29f9d54b SS |
365 | struct xhci_container_ctx *ctx; |
366 | ||
367 | if ((type != XHCI_CTX_TYPE_DEVICE) && (type != XHCI_CTX_TYPE_INPUT)) | |
368 | return NULL; | |
369 | ||
370 | ctx = kzalloc(sizeof(*ctx), flags); | |
d115b048 JY |
371 | if (!ctx) |
372 | return NULL; | |
373 | ||
d115b048 JY |
374 | ctx->type = type; |
375 | ctx->size = HCC_64BYTE_CONTEXT(xhci->hcc_params) ? 2048 : 1024; | |
376 | if (type == XHCI_CTX_TYPE_INPUT) | |
377 | ctx->size += CTX_SIZE(xhci->hcc_params); | |
378 | ||
379 | ctx->bytes = dma_pool_alloc(xhci->device_pool, flags, &ctx->dma); | |
025f880c MN |
380 | if (!ctx->bytes) { |
381 | kfree(ctx); | |
382 | return NULL; | |
383 | } | |
d115b048 JY |
384 | memset(ctx->bytes, 0, ctx->size); |
385 | return ctx; | |
386 | } | |
387 | ||
326b4810 | 388 | static void xhci_free_container_ctx(struct xhci_hcd *xhci, |
d115b048 JY |
389 | struct xhci_container_ctx *ctx) |
390 | { | |
a1d78c16 SS |
391 | if (!ctx) |
392 | return; | |
d115b048 JY |
393 | dma_pool_free(xhci->device_pool, ctx->bytes, ctx->dma); |
394 | kfree(ctx); | |
395 | } | |
396 | ||
397 | struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci, | |
398 | struct xhci_container_ctx *ctx) | |
399 | { | |
92f8e767 SS |
400 | if (ctx->type != XHCI_CTX_TYPE_INPUT) |
401 | return NULL; | |
402 | ||
d115b048 JY |
403 | return (struct xhci_input_control_ctx *)ctx->bytes; |
404 | } | |
405 | ||
406 | struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, | |
407 | struct xhci_container_ctx *ctx) | |
408 | { | |
409 | if (ctx->type == XHCI_CTX_TYPE_DEVICE) | |
410 | return (struct xhci_slot_ctx *)ctx->bytes; | |
411 | ||
412 | return (struct xhci_slot_ctx *) | |
413 | (ctx->bytes + CTX_SIZE(xhci->hcc_params)); | |
414 | } | |
415 | ||
416 | struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, | |
417 | struct xhci_container_ctx *ctx, | |
418 | unsigned int ep_index) | |
419 | { | |
420 | /* increment ep index by offset of start of ep ctx array */ | |
421 | ep_index++; | |
422 | if (ctx->type == XHCI_CTX_TYPE_INPUT) | |
423 | ep_index++; | |
424 | ||
425 | return (struct xhci_ep_ctx *) | |
426 | (ctx->bytes + (ep_index * CTX_SIZE(xhci->hcc_params))); | |
427 | } | |
428 | ||
8df75f42 SS |
429 | |
430 | /***************** Streams structures manipulation *************************/ | |
431 | ||
8212a49d | 432 | static void xhci_free_stream_ctx(struct xhci_hcd *xhci, |
8df75f42 SS |
433 | unsigned int num_stream_ctxs, |
434 | struct xhci_stream_ctx *stream_ctx, dma_addr_t dma) | |
435 | { | |
2a100047 | 436 | struct device *dev = xhci_to_hcd(xhci)->self.controller; |
8df75f42 SS |
437 | |
438 | if (num_stream_ctxs > MEDIUM_STREAM_ARRAY_SIZE) | |
2a100047 | 439 | dma_free_coherent(dev, |
8df75f42 SS |
440 | sizeof(struct xhci_stream_ctx)*num_stream_ctxs, |
441 | stream_ctx, dma); | |
442 | else if (num_stream_ctxs <= SMALL_STREAM_ARRAY_SIZE) | |
443 | return dma_pool_free(xhci->small_streams_pool, | |
444 | stream_ctx, dma); | |
445 | else | |
446 | return dma_pool_free(xhci->medium_streams_pool, | |
447 | stream_ctx, dma); | |
448 | } | |
449 | ||
450 | /* | |
451 | * The stream context array for each endpoint with bulk streams enabled can | |
452 | * vary in size, based on: | |
453 | * - how many streams the endpoint supports, | |
454 | * - the maximum primary stream array size the host controller supports, | |
455 | * - and how many streams the device driver asks for. | |
456 | * | |
457 | * The stream context array must be a power of 2, and can be as small as | |
458 | * 64 bytes or as large as 1MB. | |
459 | */ | |
8212a49d | 460 | static struct xhci_stream_ctx *xhci_alloc_stream_ctx(struct xhci_hcd *xhci, |
8df75f42 SS |
461 | unsigned int num_stream_ctxs, dma_addr_t *dma, |
462 | gfp_t mem_flags) | |
463 | { | |
2a100047 | 464 | struct device *dev = xhci_to_hcd(xhci)->self.controller; |
8df75f42 SS |
465 | |
466 | if (num_stream_ctxs > MEDIUM_STREAM_ARRAY_SIZE) | |
2a100047 | 467 | return dma_alloc_coherent(dev, |
8df75f42 | 468 | sizeof(struct xhci_stream_ctx)*num_stream_ctxs, |
22d45f01 | 469 | dma, mem_flags); |
8df75f42 SS |
470 | else if (num_stream_ctxs <= SMALL_STREAM_ARRAY_SIZE) |
471 | return dma_pool_alloc(xhci->small_streams_pool, | |
472 | mem_flags, dma); | |
473 | else | |
474 | return dma_pool_alloc(xhci->medium_streams_pool, | |
475 | mem_flags, dma); | |
476 | } | |
477 | ||
e9df17eb SS |
478 | struct xhci_ring *xhci_dma_to_transfer_ring( |
479 | struct xhci_virt_ep *ep, | |
480 | u64 address) | |
481 | { | |
482 | if (ep->ep_state & EP_HAS_STREAMS) | |
483 | return radix_tree_lookup(&ep->stream_info->trb_address_map, | |
eb8ccd2b | 484 | address >> TRB_SEGMENT_SHIFT); |
e9df17eb SS |
485 | return ep->ring; |
486 | } | |
487 | ||
e9df17eb SS |
488 | struct xhci_ring *xhci_stream_id_to_ring( |
489 | struct xhci_virt_device *dev, | |
490 | unsigned int ep_index, | |
491 | unsigned int stream_id) | |
492 | { | |
493 | struct xhci_virt_ep *ep = &dev->eps[ep_index]; | |
494 | ||
495 | if (stream_id == 0) | |
496 | return ep->ring; | |
497 | if (!ep->stream_info) | |
498 | return NULL; | |
499 | ||
500 | if (stream_id > ep->stream_info->num_streams) | |
501 | return NULL; | |
502 | return ep->stream_info->stream_rings[stream_id]; | |
503 | } | |
504 | ||
8df75f42 SS |
505 | /* |
506 | * Change an endpoint's internal structure so it supports stream IDs. The | |
507 | * number of requested streams includes stream 0, which cannot be used by device | |
508 | * drivers. | |
509 | * | |
510 | * The number of stream contexts in the stream context array may be bigger than | |
511 | * the number of streams the driver wants to use. This is because the number of | |
512 | * stream context array entries must be a power of two. | |
513 | * | |
514 | * We need a radix tree for mapping physical addresses of TRBs to which stream | |
515 | * ID they belong to. We need to do this because the host controller won't tell | |
516 | * us which stream ring the TRB came from. We could store the stream ID in an | |
517 | * event data TRB, but that doesn't help us for the cancellation case, since the | |
518 | * endpoint may stop before it reaches that event data TRB. | |
519 | * | |
520 | * The radix tree maps the upper portion of the TRB DMA address to a ring | |
521 | * segment that has the same upper portion of DMA addresses. For example, say I | |
522 | * have segments of size 1KB, that are always 64-byte aligned. A segment may | |
523 | * start at 0x10c91000 and end at 0x10c913f0. If I use the upper 10 bits, the | |
524 | * key to the stream ID is 0x43244. I can use the DMA address of the TRB to | |
525 | * pass the radix tree a key to get the right stream ID: | |
526 | * | |
527 | * 0x10c90fff >> 10 = 0x43243 | |
528 | * 0x10c912c0 >> 10 = 0x43244 | |
529 | * 0x10c91400 >> 10 = 0x43245 | |
530 | * | |
531 | * Obviously, only those TRBs with DMA addresses that are within the segment | |
532 | * will make the radix tree return the stream ID for that ring. | |
533 | * | |
534 | * Caveats for the radix tree: | |
535 | * | |
536 | * The radix tree uses an unsigned long as a key pair. On 32-bit systems, an | |
537 | * unsigned long will be 32-bits; on a 64-bit system an unsigned long will be | |
538 | * 64-bits. Since we only request 32-bit DMA addresses, we can use that as the | |
539 | * key on 32-bit or 64-bit systems (it would also be fine if we asked for 64-bit | |
540 | * PCI DMA addresses on a 64-bit system). There might be a problem on 32-bit | |
541 | * extended systems (where the DMA address can be bigger than 32-bits), | |
542 | * if we allow the PCI dma mask to be bigger than 32-bits. So don't do that. | |
543 | */ | |
544 | struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci, | |
545 | unsigned int num_stream_ctxs, | |
546 | unsigned int num_streams, gfp_t mem_flags) | |
547 | { | |
548 | struct xhci_stream_info *stream_info; | |
549 | u32 cur_stream; | |
550 | struct xhci_ring *cur_ring; | |
551 | unsigned long key; | |
552 | u64 addr; | |
553 | int ret; | |
554 | ||
555 | xhci_dbg(xhci, "Allocating %u streams and %u " | |
556 | "stream context array entries.\n", | |
557 | num_streams, num_stream_ctxs); | |
558 | if (xhci->cmd_ring_reserved_trbs == MAX_RSVD_CMD_TRBS) { | |
559 | xhci_dbg(xhci, "Command ring has no reserved TRBs available\n"); | |
560 | return NULL; | |
561 | } | |
562 | xhci->cmd_ring_reserved_trbs++; | |
563 | ||
564 | stream_info = kzalloc(sizeof(struct xhci_stream_info), mem_flags); | |
565 | if (!stream_info) | |
566 | goto cleanup_trbs; | |
567 | ||
568 | stream_info->num_streams = num_streams; | |
569 | stream_info->num_stream_ctxs = num_stream_ctxs; | |
570 | ||
571 | /* Initialize the array of virtual pointers to stream rings. */ | |
572 | stream_info->stream_rings = kzalloc( | |
573 | sizeof(struct xhci_ring *)*num_streams, | |
574 | mem_flags); | |
575 | if (!stream_info->stream_rings) | |
576 | goto cleanup_info; | |
577 | ||
578 | /* Initialize the array of DMA addresses for stream rings for the HW. */ | |
579 | stream_info->stream_ctx_array = xhci_alloc_stream_ctx(xhci, | |
580 | num_stream_ctxs, &stream_info->ctx_array_dma, | |
581 | mem_flags); | |
582 | if (!stream_info->stream_ctx_array) | |
583 | goto cleanup_ctx; | |
584 | memset(stream_info->stream_ctx_array, 0, | |
585 | sizeof(struct xhci_stream_ctx)*num_stream_ctxs); | |
586 | ||
587 | /* Allocate everything needed to free the stream rings later */ | |
588 | stream_info->free_streams_command = | |
589 | xhci_alloc_command(xhci, true, true, mem_flags); | |
590 | if (!stream_info->free_streams_command) | |
591 | goto cleanup_ctx; | |
592 | ||
593 | INIT_RADIX_TREE(&stream_info->trb_address_map, GFP_ATOMIC); | |
594 | ||
595 | /* Allocate rings for all the streams that the driver will use, | |
596 | * and add their segment DMA addresses to the radix tree. | |
597 | * Stream 0 is reserved. | |
598 | */ | |
599 | for (cur_stream = 1; cur_stream < num_streams; cur_stream++) { | |
600 | stream_info->stream_rings[cur_stream] = | |
2fdcd47b | 601 | xhci_ring_alloc(xhci, 2, 1, TYPE_STREAM, mem_flags); |
8df75f42 SS |
602 | cur_ring = stream_info->stream_rings[cur_stream]; |
603 | if (!cur_ring) | |
604 | goto cleanup_rings; | |
e9df17eb | 605 | cur_ring->stream_id = cur_stream; |
8df75f42 SS |
606 | /* Set deq ptr, cycle bit, and stream context type */ |
607 | addr = cur_ring->first_seg->dma | | |
608 | SCT_FOR_CTX(SCT_PRI_TR) | | |
609 | cur_ring->cycle_state; | |
f5960b69 ME |
610 | stream_info->stream_ctx_array[cur_stream].stream_ring = |
611 | cpu_to_le64(addr); | |
8df75f42 SS |
612 | xhci_dbg(xhci, "Setting stream %d ring ptr to 0x%08llx\n", |
613 | cur_stream, (unsigned long long) addr); | |
614 | ||
615 | key = (unsigned long) | |
eb8ccd2b | 616 | (cur_ring->first_seg->dma >> TRB_SEGMENT_SHIFT); |
8df75f42 SS |
617 | ret = radix_tree_insert(&stream_info->trb_address_map, |
618 | key, cur_ring); | |
619 | if (ret) { | |
620 | xhci_ring_free(xhci, cur_ring); | |
621 | stream_info->stream_rings[cur_stream] = NULL; | |
622 | goto cleanup_rings; | |
623 | } | |
624 | } | |
625 | /* Leave the other unused stream ring pointers in the stream context | |
626 | * array initialized to zero. This will cause the xHC to give us an | |
627 | * error if the device asks for a stream ID we don't have setup (if it | |
628 | * was any other way, the host controller would assume the ring is | |
629 | * "empty" and wait forever for data to be queued to that stream ID). | |
630 | */ | |
8df75f42 SS |
631 | |
632 | return stream_info; | |
633 | ||
634 | cleanup_rings: | |
635 | for (cur_stream = 1; cur_stream < num_streams; cur_stream++) { | |
636 | cur_ring = stream_info->stream_rings[cur_stream]; | |
637 | if (cur_ring) { | |
638 | addr = cur_ring->first_seg->dma; | |
639 | radix_tree_delete(&stream_info->trb_address_map, | |
eb8ccd2b | 640 | addr >> TRB_SEGMENT_SHIFT); |
8df75f42 SS |
641 | xhci_ring_free(xhci, cur_ring); |
642 | stream_info->stream_rings[cur_stream] = NULL; | |
643 | } | |
644 | } | |
645 | xhci_free_command(xhci, stream_info->free_streams_command); | |
646 | cleanup_ctx: | |
647 | kfree(stream_info->stream_rings); | |
648 | cleanup_info: | |
649 | kfree(stream_info); | |
650 | cleanup_trbs: | |
651 | xhci->cmd_ring_reserved_trbs--; | |
652 | return NULL; | |
653 | } | |
654 | /* | |
655 | * Sets the MaxPStreams field and the Linear Stream Array field. | |
656 | * Sets the dequeue pointer to the stream context array. | |
657 | */ | |
658 | void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci, | |
659 | struct xhci_ep_ctx *ep_ctx, | |
660 | struct xhci_stream_info *stream_info) | |
661 | { | |
662 | u32 max_primary_streams; | |
663 | /* MaxPStreams is the number of stream context array entries, not the | |
664 | * number we're actually using. Must be in 2^(MaxPstreams + 1) format. | |
665 | * fls(0) = 0, fls(0x1) = 1, fls(0x10) = 2, fls(0x100) = 3, etc. | |
666 | */ | |
667 | max_primary_streams = fls(stream_info->num_stream_ctxs) - 2; | |
3a7fa5be XR |
668 | xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, |
669 | "Setting number of stream ctx array entries to %u", | |
8df75f42 | 670 | 1 << (max_primary_streams + 1)); |
28ccd296 ME |
671 | ep_ctx->ep_info &= cpu_to_le32(~EP_MAXPSTREAMS_MASK); |
672 | ep_ctx->ep_info |= cpu_to_le32(EP_MAXPSTREAMS(max_primary_streams) | |
673 | | EP_HAS_LSA); | |
674 | ep_ctx->deq = cpu_to_le64(stream_info->ctx_array_dma); | |
8df75f42 SS |
675 | } |
676 | ||
677 | /* | |
678 | * Sets the MaxPStreams field and the Linear Stream Array field to 0. | |
679 | * Reinstalls the "normal" endpoint ring (at its previous dequeue mark, | |
680 | * not at the beginning of the ring). | |
681 | */ | |
682 | void xhci_setup_no_streams_ep_input_ctx(struct xhci_hcd *xhci, | |
683 | struct xhci_ep_ctx *ep_ctx, | |
684 | struct xhci_virt_ep *ep) | |
685 | { | |
686 | dma_addr_t addr; | |
28ccd296 | 687 | ep_ctx->ep_info &= cpu_to_le32(~(EP_MAXPSTREAMS_MASK | EP_HAS_LSA)); |
8df75f42 | 688 | addr = xhci_trb_virt_to_dma(ep->ring->deq_seg, ep->ring->dequeue); |
28ccd296 | 689 | ep_ctx->deq = cpu_to_le64(addr | ep->ring->cycle_state); |
8df75f42 SS |
690 | } |
691 | ||
692 | /* Frees all stream contexts associated with the endpoint, | |
693 | * | |
694 | * Caller should fix the endpoint context streams fields. | |
695 | */ | |
696 | void xhci_free_stream_info(struct xhci_hcd *xhci, | |
697 | struct xhci_stream_info *stream_info) | |
698 | { | |
699 | int cur_stream; | |
700 | struct xhci_ring *cur_ring; | |
701 | dma_addr_t addr; | |
702 | ||
703 | if (!stream_info) | |
704 | return; | |
705 | ||
706 | for (cur_stream = 1; cur_stream < stream_info->num_streams; | |
707 | cur_stream++) { | |
708 | cur_ring = stream_info->stream_rings[cur_stream]; | |
709 | if (cur_ring) { | |
710 | addr = cur_ring->first_seg->dma; | |
711 | radix_tree_delete(&stream_info->trb_address_map, | |
eb8ccd2b | 712 | addr >> TRB_SEGMENT_SHIFT); |
8df75f42 SS |
713 | xhci_ring_free(xhci, cur_ring); |
714 | stream_info->stream_rings[cur_stream] = NULL; | |
715 | } | |
716 | } | |
717 | xhci_free_command(xhci, stream_info->free_streams_command); | |
718 | xhci->cmd_ring_reserved_trbs--; | |
719 | if (stream_info->stream_ctx_array) | |
720 | xhci_free_stream_ctx(xhci, | |
721 | stream_info->num_stream_ctxs, | |
722 | stream_info->stream_ctx_array, | |
723 | stream_info->ctx_array_dma); | |
724 | ||
0d3703be | 725 | kfree(stream_info->stream_rings); |
8df75f42 SS |
726 | kfree(stream_info); |
727 | } | |
728 | ||
729 | ||
730 | /***************** Device context manipulation *************************/ | |
731 | ||
6f5165cf SS |
732 | static void xhci_init_endpoint_timer(struct xhci_hcd *xhci, |
733 | struct xhci_virt_ep *ep) | |
734 | { | |
735 | init_timer(&ep->stop_cmd_timer); | |
736 | ep->stop_cmd_timer.data = (unsigned long) ep; | |
737 | ep->stop_cmd_timer.function = xhci_stop_endpoint_command_watchdog; | |
738 | ep->xhci = xhci; | |
739 | } | |
740 | ||
839c817c SS |
741 | static void xhci_free_tt_info(struct xhci_hcd *xhci, |
742 | struct xhci_virt_device *virt_dev, | |
743 | int slot_id) | |
744 | { | |
839c817c | 745 | struct list_head *tt_list_head; |
46ed8f00 TI |
746 | struct xhci_tt_bw_info *tt_info, *next; |
747 | bool slot_found = false; | |
839c817c SS |
748 | |
749 | /* If the device never made it past the Set Address stage, | |
750 | * it may not have the real_port set correctly. | |
751 | */ | |
752 | if (virt_dev->real_port == 0 || | |
753 | virt_dev->real_port > HCS_MAX_PORTS(xhci->hcs_params1)) { | |
754 | xhci_dbg(xhci, "Bad real port.\n"); | |
755 | return; | |
756 | } | |
757 | ||
758 | tt_list_head = &(xhci->rh_bw[virt_dev->real_port - 1].tts); | |
46ed8f00 TI |
759 | list_for_each_entry_safe(tt_info, next, tt_list_head, tt_list) { |
760 | /* Multi-TT hubs will have more than one entry */ | |
761 | if (tt_info->slot_id == slot_id) { | |
762 | slot_found = true; | |
763 | list_del(&tt_info->tt_list); | |
764 | kfree(tt_info); | |
765 | } else if (slot_found) { | |
839c817c | 766 | break; |
46ed8f00 | 767 | } |
839c817c | 768 | } |
839c817c SS |
769 | } |
770 | ||
771 | int xhci_alloc_tt_info(struct xhci_hcd *xhci, | |
772 | struct xhci_virt_device *virt_dev, | |
773 | struct usb_device *hdev, | |
774 | struct usb_tt *tt, gfp_t mem_flags) | |
775 | { | |
776 | struct xhci_tt_bw_info *tt_info; | |
777 | unsigned int num_ports; | |
778 | int i, j; | |
779 | ||
780 | if (!tt->multi) | |
781 | num_ports = 1; | |
782 | else | |
783 | num_ports = hdev->maxchild; | |
784 | ||
785 | for (i = 0; i < num_ports; i++, tt_info++) { | |
786 | struct xhci_interval_bw_table *bw_table; | |
787 | ||
788 | tt_info = kzalloc(sizeof(*tt_info), mem_flags); | |
789 | if (!tt_info) | |
790 | goto free_tts; | |
791 | INIT_LIST_HEAD(&tt_info->tt_list); | |
792 | list_add(&tt_info->tt_list, | |
793 | &xhci->rh_bw[virt_dev->real_port - 1].tts); | |
794 | tt_info->slot_id = virt_dev->udev->slot_id; | |
795 | if (tt->multi) | |
796 | tt_info->ttport = i+1; | |
797 | bw_table = &tt_info->bw_table; | |
798 | for (j = 0; j < XHCI_MAX_INTERVAL; j++) | |
799 | INIT_LIST_HEAD(&bw_table->interval_bw[j].endpoints); | |
800 | } | |
801 | return 0; | |
802 | ||
803 | free_tts: | |
804 | xhci_free_tt_info(xhci, virt_dev, virt_dev->udev->slot_id); | |
805 | return -ENOMEM; | |
806 | } | |
807 | ||
808 | ||
809 | /* All the xhci_tds in the ring's TD list should be freed at this point. | |
810 | * Should be called with xhci->lock held if there is any chance the TT lists | |
811 | * will be manipulated by the configure endpoint, allocate device, or update | |
812 | * hub functions while this function is removing the TT entries from the list. | |
813 | */ | |
3ffbba95 SS |
814 | void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id) |
815 | { | |
816 | struct xhci_virt_device *dev; | |
817 | int i; | |
2e27980e | 818 | int old_active_eps = 0; |
3ffbba95 SS |
819 | |
820 | /* Slot ID 0 is reserved */ | |
821 | if (slot_id == 0 || !xhci->devs[slot_id]) | |
822 | return; | |
823 | ||
824 | dev = xhci->devs[slot_id]; | |
8e595a5d | 825 | xhci->dcbaa->dev_context_ptrs[slot_id] = 0; |
3ffbba95 SS |
826 | if (!dev) |
827 | return; | |
828 | ||
2e27980e SS |
829 | if (dev->tt_info) |
830 | old_active_eps = dev->tt_info->active_eps; | |
831 | ||
8df75f42 | 832 | for (i = 0; i < 31; ++i) { |
63a0d9ab SS |
833 | if (dev->eps[i].ring) |
834 | xhci_ring_free(xhci, dev->eps[i].ring); | |
8df75f42 SS |
835 | if (dev->eps[i].stream_info) |
836 | xhci_free_stream_info(xhci, | |
837 | dev->eps[i].stream_info); | |
2e27980e SS |
838 | /* Endpoints on the TT/root port lists should have been removed |
839 | * when usb_disable_device() was called for the device. | |
840 | * We can't drop them anyway, because the udev might have gone | |
841 | * away by this point, and we can't tell what speed it was. | |
842 | */ | |
843 | if (!list_empty(&dev->eps[i].bw_endpoint_list)) | |
844 | xhci_warn(xhci, "Slot %u endpoint %u " | |
845 | "not removed from BW list!\n", | |
846 | slot_id, i); | |
8df75f42 | 847 | } |
839c817c SS |
848 | /* If this is a hub, free the TT(s) from the TT list */ |
849 | xhci_free_tt_info(xhci, dev, slot_id); | |
2e27980e SS |
850 | /* If necessary, update the number of active TTs on this root port */ |
851 | xhci_update_tt_active_eps(xhci, dev, old_active_eps); | |
3ffbba95 | 852 | |
74f9fe21 SS |
853 | if (dev->ring_cache) { |
854 | for (i = 0; i < dev->num_rings_cached; i++) | |
855 | xhci_ring_free(xhci, dev->ring_cache[i]); | |
856 | kfree(dev->ring_cache); | |
857 | } | |
858 | ||
3ffbba95 | 859 | if (dev->in_ctx) |
d115b048 | 860 | xhci_free_container_ctx(xhci, dev->in_ctx); |
3ffbba95 | 861 | if (dev->out_ctx) |
d115b048 JY |
862 | xhci_free_container_ctx(xhci, dev->out_ctx); |
863 | ||
3ffbba95 | 864 | kfree(xhci->devs[slot_id]); |
326b4810 | 865 | xhci->devs[slot_id] = NULL; |
3ffbba95 SS |
866 | } |
867 | ||
868 | int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, | |
869 | struct usb_device *udev, gfp_t flags) | |
870 | { | |
3ffbba95 | 871 | struct xhci_virt_device *dev; |
63a0d9ab | 872 | int i; |
3ffbba95 SS |
873 | |
874 | /* Slot ID 0 is reserved */ | |
875 | if (slot_id == 0 || xhci->devs[slot_id]) { | |
876 | xhci_warn(xhci, "Bad Slot ID %d\n", slot_id); | |
877 | return 0; | |
878 | } | |
879 | ||
880 | xhci->devs[slot_id] = kzalloc(sizeof(*xhci->devs[slot_id]), flags); | |
881 | if (!xhci->devs[slot_id]) | |
882 | return 0; | |
883 | dev = xhci->devs[slot_id]; | |
884 | ||
d115b048 JY |
885 | /* Allocate the (output) device context that will be used in the HC. */ |
886 | dev->out_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_DEVICE, flags); | |
3ffbba95 SS |
887 | if (!dev->out_ctx) |
888 | goto fail; | |
d115b048 | 889 | |
700e2052 | 890 | xhci_dbg(xhci, "Slot %d output ctx = 0x%llx (dma)\n", slot_id, |
d115b048 | 891 | (unsigned long long)dev->out_ctx->dma); |
3ffbba95 SS |
892 | |
893 | /* Allocate the (input) device context for address device command */ | |
d115b048 | 894 | dev->in_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT, flags); |
3ffbba95 SS |
895 | if (!dev->in_ctx) |
896 | goto fail; | |
d115b048 | 897 | |
700e2052 | 898 | xhci_dbg(xhci, "Slot %d input ctx = 0x%llx (dma)\n", slot_id, |
d115b048 | 899 | (unsigned long long)dev->in_ctx->dma); |
3ffbba95 | 900 | |
6f5165cf SS |
901 | /* Initialize the cancellation list and watchdog timers for each ep */ |
902 | for (i = 0; i < 31; i++) { | |
903 | xhci_init_endpoint_timer(xhci, &dev->eps[i]); | |
63a0d9ab | 904 | INIT_LIST_HEAD(&dev->eps[i].cancelled_td_list); |
2e27980e | 905 | INIT_LIST_HEAD(&dev->eps[i].bw_endpoint_list); |
6f5165cf | 906 | } |
63a0d9ab | 907 | |
3ffbba95 | 908 | /* Allocate endpoint 0 ring */ |
2fdcd47b | 909 | dev->eps[0].ring = xhci_ring_alloc(xhci, 2, 1, TYPE_CTRL, flags); |
63a0d9ab | 910 | if (!dev->eps[0].ring) |
3ffbba95 SS |
911 | goto fail; |
912 | ||
74f9fe21 SS |
913 | /* Allocate pointers to the ring cache */ |
914 | dev->ring_cache = kzalloc( | |
915 | sizeof(struct xhci_ring *)*XHCI_MAX_RINGS_CACHED, | |
916 | flags); | |
917 | if (!dev->ring_cache) | |
918 | goto fail; | |
919 | dev->num_rings_cached = 0; | |
920 | ||
f94e0186 | 921 | init_completion(&dev->cmd_completion); |
913a8a34 | 922 | INIT_LIST_HEAD(&dev->cmd_list); |
64927730 | 923 | dev->udev = udev; |
f94e0186 | 924 | |
28c2d2ef | 925 | /* Point to output device context in dcbaa. */ |
28ccd296 | 926 | xhci->dcbaa->dev_context_ptrs[slot_id] = cpu_to_le64(dev->out_ctx->dma); |
700e2052 | 927 | xhci_dbg(xhci, "Set slot id %d dcbaa entry %p to 0x%llx\n", |
28ccd296 ME |
928 | slot_id, |
929 | &xhci->dcbaa->dev_context_ptrs[slot_id], | |
f5960b69 | 930 | le64_to_cpu(xhci->dcbaa->dev_context_ptrs[slot_id])); |
3ffbba95 SS |
931 | |
932 | return 1; | |
933 | fail: | |
934 | xhci_free_virt_device(xhci, slot_id); | |
935 | return 0; | |
936 | } | |
937 | ||
2d1ee590 SS |
938 | void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci, |
939 | struct usb_device *udev) | |
940 | { | |
941 | struct xhci_virt_device *virt_dev; | |
942 | struct xhci_ep_ctx *ep0_ctx; | |
943 | struct xhci_ring *ep_ring; | |
944 | ||
945 | virt_dev = xhci->devs[udev->slot_id]; | |
946 | ep0_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, 0); | |
947 | ep_ring = virt_dev->eps[0].ring; | |
948 | /* | |
949 | * FIXME we don't keep track of the dequeue pointer very well after a | |
950 | * Set TR dequeue pointer, so we're setting the dequeue pointer of the | |
951 | * host to our enqueue pointer. This should only be called after a | |
952 | * configured device has reset, so all control transfers should have | |
953 | * been completed or cancelled before the reset. | |
954 | */ | |
28ccd296 ME |
955 | ep0_ctx->deq = cpu_to_le64(xhci_trb_virt_to_dma(ep_ring->enq_seg, |
956 | ep_ring->enqueue) | |
957 | | ep_ring->cycle_state); | |
2d1ee590 SS |
958 | } |
959 | ||
f6ff0ac8 SS |
960 | /* |
961 | * The xHCI roothub may have ports of differing speeds in any order in the port | |
962 | * status registers. xhci->port_array provides an array of the port speed for | |
963 | * each offset into the port status registers. | |
964 | * | |
965 | * The xHCI hardware wants to know the roothub port number that the USB device | |
966 | * is attached to (or the roothub port its ancestor hub is attached to). All we | |
967 | * know is the index of that port under either the USB 2.0 or the USB 3.0 | |
968 | * roothub, but that doesn't give us the real index into the HW port status | |
3f5eb141 | 969 | * registers. Call xhci_find_raw_port_number() to get real index. |
f6ff0ac8 SS |
970 | */ |
971 | static u32 xhci_find_real_port_number(struct xhci_hcd *xhci, | |
972 | struct usb_device *udev) | |
973 | { | |
974 | struct usb_device *top_dev; | |
3f5eb141 LT |
975 | struct usb_hcd *hcd; |
976 | ||
977 | if (udev->speed == USB_SPEED_SUPER) | |
978 | hcd = xhci->shared_hcd; | |
979 | else | |
980 | hcd = xhci->main_hcd; | |
f6ff0ac8 SS |
981 | |
982 | for (top_dev = udev; top_dev->parent && top_dev->parent->parent; | |
983 | top_dev = top_dev->parent) | |
984 | /* Found device below root hub */; | |
f6ff0ac8 | 985 | |
3f5eb141 | 986 | return xhci_find_raw_port_number(hcd, top_dev->portnum); |
f6ff0ac8 SS |
987 | } |
988 | ||
3ffbba95 SS |
989 | /* Setup an xHCI virtual device for a Set Address command */ |
990 | int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev) | |
991 | { | |
992 | struct xhci_virt_device *dev; | |
993 | struct xhci_ep_ctx *ep0_ctx; | |
d115b048 | 994 | struct xhci_slot_ctx *slot_ctx; |
f6ff0ac8 | 995 | u32 port_num; |
bd18fd5c | 996 | u32 max_packets; |
f6ff0ac8 | 997 | struct usb_device *top_dev; |
3ffbba95 SS |
998 | |
999 | dev = xhci->devs[udev->slot_id]; | |
1000 | /* Slot ID 0 is reserved */ | |
1001 | if (udev->slot_id == 0 || !dev) { | |
1002 | xhci_warn(xhci, "Slot ID %d is not assigned to this device\n", | |
1003 | udev->slot_id); | |
1004 | return -EINVAL; | |
1005 | } | |
d115b048 | 1006 | ep0_ctx = xhci_get_ep_ctx(xhci, dev->in_ctx, 0); |
d115b048 | 1007 | slot_ctx = xhci_get_slot_ctx(xhci, dev->in_ctx); |
3ffbba95 | 1008 | |
3ffbba95 | 1009 | /* 3) Only the control endpoint is valid - one endpoint context */ |
f5960b69 | 1010 | slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1) | udev->route); |
3ffbba95 SS |
1011 | switch (udev->speed) { |
1012 | case USB_SPEED_SUPER: | |
f5960b69 | 1013 | slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_SS); |
bd18fd5c | 1014 | max_packets = MAX_PACKET(512); |
3ffbba95 SS |
1015 | break; |
1016 | case USB_SPEED_HIGH: | |
f5960b69 | 1017 | slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_HS); |
bd18fd5c | 1018 | max_packets = MAX_PACKET(64); |
3ffbba95 | 1019 | break; |
bd18fd5c | 1020 | /* USB core guesses at a 64-byte max packet first for FS devices */ |
3ffbba95 | 1021 | case USB_SPEED_FULL: |
f5960b69 | 1022 | slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_FS); |
bd18fd5c | 1023 | max_packets = MAX_PACKET(64); |
3ffbba95 SS |
1024 | break; |
1025 | case USB_SPEED_LOW: | |
f5960b69 | 1026 | slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_LS); |
bd18fd5c | 1027 | max_packets = MAX_PACKET(8); |
3ffbba95 | 1028 | break; |
551cdbbe | 1029 | case USB_SPEED_WIRELESS: |
3ffbba95 SS |
1030 | xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n"); |
1031 | return -EINVAL; | |
1032 | break; | |
1033 | default: | |
1034 | /* Speed was set earlier, this shouldn't happen. */ | |
bd18fd5c | 1035 | return -EINVAL; |
3ffbba95 SS |
1036 | } |
1037 | /* Find the root hub port this device is under */ | |
f6ff0ac8 SS |
1038 | port_num = xhci_find_real_port_number(xhci, udev); |
1039 | if (!port_num) | |
1040 | return -EINVAL; | |
f5960b69 | 1041 | slot_ctx->dev_info2 |= cpu_to_le32(ROOT_HUB_PORT(port_num)); |
f6ff0ac8 | 1042 | /* Set the port number in the virtual_device to the faked port number */ |
3ffbba95 SS |
1043 | for (top_dev = udev; top_dev->parent && top_dev->parent->parent; |
1044 | top_dev = top_dev->parent) | |
1045 | /* Found device below root hub */; | |
fe30182c | 1046 | dev->fake_port = top_dev->portnum; |
66381755 | 1047 | dev->real_port = port_num; |
f6ff0ac8 | 1048 | xhci_dbg(xhci, "Set root hub portnum to %d\n", port_num); |
fe30182c | 1049 | xhci_dbg(xhci, "Set fake root hub portnum to %d\n", dev->fake_port); |
3ffbba95 | 1050 | |
839c817c SS |
1051 | /* Find the right bandwidth table that this device will be a part of. |
1052 | * If this is a full speed device attached directly to a root port (or a | |
1053 | * decendent of one), it counts as a primary bandwidth domain, not a | |
1054 | * secondary bandwidth domain under a TT. An xhci_tt_info structure | |
1055 | * will never be created for the HS root hub. | |
1056 | */ | |
1057 | if (!udev->tt || !udev->tt->hub->parent) { | |
1058 | dev->bw_table = &xhci->rh_bw[port_num - 1].bw_table; | |
1059 | } else { | |
1060 | struct xhci_root_port_bw_info *rh_bw; | |
1061 | struct xhci_tt_bw_info *tt_bw; | |
1062 | ||
1063 | rh_bw = &xhci->rh_bw[port_num - 1]; | |
1064 | /* Find the right TT. */ | |
1065 | list_for_each_entry(tt_bw, &rh_bw->tts, tt_list) { | |
1066 | if (tt_bw->slot_id != udev->tt->hub->slot_id) | |
1067 | continue; | |
1068 | ||
1069 | if (!dev->udev->tt->multi || | |
1070 | (udev->tt->multi && | |
1071 | tt_bw->ttport == dev->udev->ttport)) { | |
1072 | dev->bw_table = &tt_bw->bw_table; | |
1073 | dev->tt_info = tt_bw; | |
1074 | break; | |
1075 | } | |
1076 | } | |
1077 | if (!dev->tt_info) | |
1078 | xhci_warn(xhci, "WARN: Didn't find a matching TT\n"); | |
1079 | } | |
1080 | ||
aa1b13ef SS |
1081 | /* Is this a LS/FS device under an external HS hub? */ |
1082 | if (udev->tt && udev->tt->hub->parent) { | |
28ccd296 ME |
1083 | slot_ctx->tt_info = cpu_to_le32(udev->tt->hub->slot_id | |
1084 | (udev->ttport << 8)); | |
07b6de10 | 1085 | if (udev->tt->multi) |
28ccd296 | 1086 | slot_ctx->dev_info |= cpu_to_le32(DEV_MTT); |
3ffbba95 | 1087 | } |
700e2052 | 1088 | xhci_dbg(xhci, "udev->tt = %p\n", udev->tt); |
3ffbba95 SS |
1089 | xhci_dbg(xhci, "udev->ttport = 0x%x\n", udev->ttport); |
1090 | ||
1091 | /* Step 4 - ring already allocated */ | |
1092 | /* Step 5 */ | |
28ccd296 | 1093 | ep0_ctx->ep_info2 = cpu_to_le32(EP_TYPE(CTRL_EP)); |
bd18fd5c | 1094 | |
3ffbba95 | 1095 | /* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */ |
bd18fd5c MN |
1096 | ep0_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(0) | ERROR_COUNT(3) | |
1097 | max_packets); | |
3ffbba95 | 1098 | |
28ccd296 ME |
1099 | ep0_ctx->deq = cpu_to_le64(dev->eps[0].ring->first_seg->dma | |
1100 | dev->eps[0].ring->cycle_state); | |
3ffbba95 SS |
1101 | |
1102 | /* Steps 7 and 8 were done in xhci_alloc_virt_device() */ | |
1103 | ||
1104 | return 0; | |
1105 | } | |
1106 | ||
dfa49c4a DT |
1107 | /* |
1108 | * Convert interval expressed as 2^(bInterval - 1) == interval into | |
1109 | * straight exponent value 2^n == interval. | |
1110 | * | |
1111 | */ | |
1112 | static unsigned int xhci_parse_exponent_interval(struct usb_device *udev, | |
1113 | struct usb_host_endpoint *ep) | |
1114 | { | |
1115 | unsigned int interval; | |
1116 | ||
1117 | interval = clamp_val(ep->desc.bInterval, 1, 16) - 1; | |
1118 | if (interval != ep->desc.bInterval - 1) | |
1119 | dev_warn(&udev->dev, | |
cd3c18ba | 1120 | "ep %#x - rounding interval to %d %sframes\n", |
dfa49c4a | 1121 | ep->desc.bEndpointAddress, |
cd3c18ba DT |
1122 | 1 << interval, |
1123 | udev->speed == USB_SPEED_FULL ? "" : "micro"); | |
1124 | ||
1125 | if (udev->speed == USB_SPEED_FULL) { | |
1126 | /* | |
1127 | * Full speed isoc endpoints specify interval in frames, | |
1128 | * not microframes. We are using microframes everywhere, | |
1129 | * so adjust accordingly. | |
1130 | */ | |
1131 | interval += 3; /* 1 frame = 2^3 uframes */ | |
1132 | } | |
dfa49c4a DT |
1133 | |
1134 | return interval; | |
1135 | } | |
1136 | ||
1137 | /* | |
340a3504 | 1138 | * Convert bInterval expressed in microframes (in 1-255 range) to exponent of |
dfa49c4a DT |
1139 | * microframes, rounded down to nearest power of 2. |
1140 | */ | |
340a3504 SS |
1141 | static unsigned int xhci_microframes_to_exponent(struct usb_device *udev, |
1142 | struct usb_host_endpoint *ep, unsigned int desc_interval, | |
1143 | unsigned int min_exponent, unsigned int max_exponent) | |
dfa49c4a DT |
1144 | { |
1145 | unsigned int interval; | |
1146 | ||
340a3504 SS |
1147 | interval = fls(desc_interval) - 1; |
1148 | interval = clamp_val(interval, min_exponent, max_exponent); | |
1149 | if ((1 << interval) != desc_interval) | |
dfa49c4a DT |
1150 | dev_warn(&udev->dev, |
1151 | "ep %#x - rounding interval to %d microframes, ep desc says %d microframes\n", | |
1152 | ep->desc.bEndpointAddress, | |
1153 | 1 << interval, | |
340a3504 | 1154 | desc_interval); |
dfa49c4a DT |
1155 | |
1156 | return interval; | |
1157 | } | |
1158 | ||
340a3504 SS |
1159 | static unsigned int xhci_parse_microframe_interval(struct usb_device *udev, |
1160 | struct usb_host_endpoint *ep) | |
1161 | { | |
55c1945e SS |
1162 | if (ep->desc.bInterval == 0) |
1163 | return 0; | |
340a3504 SS |
1164 | return xhci_microframes_to_exponent(udev, ep, |
1165 | ep->desc.bInterval, 0, 15); | |
1166 | } | |
1167 | ||
1168 | ||
1169 | static unsigned int xhci_parse_frame_interval(struct usb_device *udev, | |
1170 | struct usb_host_endpoint *ep) | |
1171 | { | |
1172 | return xhci_microframes_to_exponent(udev, ep, | |
1173 | ep->desc.bInterval * 8, 3, 10); | |
1174 | } | |
1175 | ||
f94e0186 SS |
1176 | /* Return the polling or NAK interval. |
1177 | * | |
1178 | * The polling interval is expressed in "microframes". If xHCI's Interval field | |
1179 | * is set to N, it will service the endpoint every 2^(Interval)*125us. | |
1180 | * | |
1181 | * The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval | |
1182 | * is set to 0. | |
1183 | */ | |
575688e1 | 1184 | static unsigned int xhci_get_endpoint_interval(struct usb_device *udev, |
f94e0186 SS |
1185 | struct usb_host_endpoint *ep) |
1186 | { | |
1187 | unsigned int interval = 0; | |
1188 | ||
1189 | switch (udev->speed) { | |
1190 | case USB_SPEED_HIGH: | |
1191 | /* Max NAK rate */ | |
1192 | if (usb_endpoint_xfer_control(&ep->desc) || | |
dfa49c4a | 1193 | usb_endpoint_xfer_bulk(&ep->desc)) { |
340a3504 | 1194 | interval = xhci_parse_microframe_interval(udev, ep); |
dfa49c4a DT |
1195 | break; |
1196 | } | |
f94e0186 | 1197 | /* Fall through - SS and HS isoc/int have same decoding */ |
dfa49c4a | 1198 | |
f94e0186 SS |
1199 | case USB_SPEED_SUPER: |
1200 | if (usb_endpoint_xfer_int(&ep->desc) || | |
dfa49c4a DT |
1201 | usb_endpoint_xfer_isoc(&ep->desc)) { |
1202 | interval = xhci_parse_exponent_interval(udev, ep); | |
f94e0186 SS |
1203 | } |
1204 | break; | |
dfa49c4a | 1205 | |
f94e0186 | 1206 | case USB_SPEED_FULL: |
b513d447 | 1207 | if (usb_endpoint_xfer_isoc(&ep->desc)) { |
dfa49c4a DT |
1208 | interval = xhci_parse_exponent_interval(udev, ep); |
1209 | break; | |
1210 | } | |
1211 | /* | |
b513d447 | 1212 | * Fall through for interrupt endpoint interval decoding |
dfa49c4a DT |
1213 | * since it uses the same rules as low speed interrupt |
1214 | * endpoints. | |
1215 | */ | |
1216 | ||
f94e0186 SS |
1217 | case USB_SPEED_LOW: |
1218 | if (usb_endpoint_xfer_int(&ep->desc) || | |
dfa49c4a DT |
1219 | usb_endpoint_xfer_isoc(&ep->desc)) { |
1220 | ||
1221 | interval = xhci_parse_frame_interval(udev, ep); | |
f94e0186 SS |
1222 | } |
1223 | break; | |
dfa49c4a | 1224 | |
f94e0186 SS |
1225 | default: |
1226 | BUG(); | |
1227 | } | |
1228 | return EP_INTERVAL(interval); | |
1229 | } | |
1230 | ||
c30c791c | 1231 | /* The "Mult" field in the endpoint context is only set for SuperSpeed isoc eps. |
1cf62246 SS |
1232 | * High speed endpoint descriptors can define "the number of additional |
1233 | * transaction opportunities per microframe", but that goes in the Max Burst | |
1234 | * endpoint context field. | |
1235 | */ | |
575688e1 | 1236 | static u32 xhci_get_endpoint_mult(struct usb_device *udev, |
1cf62246 SS |
1237 | struct usb_host_endpoint *ep) |
1238 | { | |
c30c791c SS |
1239 | if (udev->speed != USB_SPEED_SUPER || |
1240 | !usb_endpoint_xfer_isoc(&ep->desc)) | |
1cf62246 | 1241 | return 0; |
842f1690 | 1242 | return ep->ss_ep_comp.bmAttributes; |
1cf62246 SS |
1243 | } |
1244 | ||
575688e1 | 1245 | static u32 xhci_get_endpoint_type(struct usb_device *udev, |
f94e0186 SS |
1246 | struct usb_host_endpoint *ep) |
1247 | { | |
1248 | int in; | |
1249 | u32 type; | |
1250 | ||
1251 | in = usb_endpoint_dir_in(&ep->desc); | |
1252 | if (usb_endpoint_xfer_control(&ep->desc)) { | |
1253 | type = EP_TYPE(CTRL_EP); | |
1254 | } else if (usb_endpoint_xfer_bulk(&ep->desc)) { | |
1255 | if (in) | |
1256 | type = EP_TYPE(BULK_IN_EP); | |
1257 | else | |
1258 | type = EP_TYPE(BULK_OUT_EP); | |
1259 | } else if (usb_endpoint_xfer_isoc(&ep->desc)) { | |
1260 | if (in) | |
1261 | type = EP_TYPE(ISOC_IN_EP); | |
1262 | else | |
1263 | type = EP_TYPE(ISOC_OUT_EP); | |
1264 | } else if (usb_endpoint_xfer_int(&ep->desc)) { | |
1265 | if (in) | |
1266 | type = EP_TYPE(INT_IN_EP); | |
1267 | else | |
1268 | type = EP_TYPE(INT_OUT_EP); | |
1269 | } else { | |
17d65554 | 1270 | type = 0; |
f94e0186 SS |
1271 | } |
1272 | return type; | |
1273 | } | |
1274 | ||
9238f25d SS |
1275 | /* Return the maximum endpoint service interval time (ESIT) payload. |
1276 | * Basically, this is the maxpacket size, multiplied by the burst size | |
1277 | * and mult size. | |
1278 | */ | |
575688e1 | 1279 | static u32 xhci_get_max_esit_payload(struct xhci_hcd *xhci, |
9238f25d SS |
1280 | struct usb_device *udev, |
1281 | struct usb_host_endpoint *ep) | |
1282 | { | |
1283 | int max_burst; | |
1284 | int max_packet; | |
1285 | ||
1286 | /* Only applies for interrupt or isochronous endpoints */ | |
1287 | if (usb_endpoint_xfer_control(&ep->desc) || | |
1288 | usb_endpoint_xfer_bulk(&ep->desc)) | |
1289 | return 0; | |
1290 | ||
842f1690 | 1291 | if (udev->speed == USB_SPEED_SUPER) |
64b3c304 | 1292 | return le16_to_cpu(ep->ss_ep_comp.wBytesPerInterval); |
9238f25d | 1293 | |
29cc8897 KM |
1294 | max_packet = GET_MAX_PACKET(usb_endpoint_maxp(&ep->desc)); |
1295 | max_burst = (usb_endpoint_maxp(&ep->desc) & 0x1800) >> 11; | |
9238f25d SS |
1296 | /* A 0 in max burst means 1 transfer per ESIT */ |
1297 | return max_packet * (max_burst + 1); | |
1298 | } | |
1299 | ||
8df75f42 SS |
1300 | /* Set up an endpoint with one ring segment. Do not allocate stream rings. |
1301 | * Drivers will have to call usb_alloc_streams() to do that. | |
1302 | */ | |
f94e0186 SS |
1303 | int xhci_endpoint_init(struct xhci_hcd *xhci, |
1304 | struct xhci_virt_device *virt_dev, | |
1305 | struct usb_device *udev, | |
f88ba78d SS |
1306 | struct usb_host_endpoint *ep, |
1307 | gfp_t mem_flags) | |
f94e0186 SS |
1308 | { |
1309 | unsigned int ep_index; | |
1310 | struct xhci_ep_ctx *ep_ctx; | |
1311 | struct xhci_ring *ep_ring; | |
1312 | unsigned int max_packet; | |
1313 | unsigned int max_burst; | |
3b72fca0 | 1314 | enum xhci_ring_type type; |
9238f25d | 1315 | u32 max_esit_payload; |
17d65554 | 1316 | u32 endpoint_type; |
f94e0186 SS |
1317 | |
1318 | ep_index = xhci_get_endpoint_index(&ep->desc); | |
d115b048 | 1319 | ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index); |
f94e0186 | 1320 | |
17d65554 MN |
1321 | endpoint_type = xhci_get_endpoint_type(udev, ep); |
1322 | if (!endpoint_type) | |
1323 | return -EINVAL; | |
1324 | ep_ctx->ep_info2 = cpu_to_le32(endpoint_type); | |
1325 | ||
3b72fca0 | 1326 | type = usb_endpoint_type(&ep->desc); |
f94e0186 | 1327 | /* Set up the endpoint ring */ |
8dfec614 | 1328 | virt_dev->eps[ep_index].new_ring = |
2fdcd47b | 1329 | xhci_ring_alloc(xhci, 2, 1, type, mem_flags); |
74f9fe21 SS |
1330 | if (!virt_dev->eps[ep_index].new_ring) { |
1331 | /* Attempt to use the ring cache */ | |
1332 | if (virt_dev->num_rings_cached == 0) | |
1333 | return -ENOMEM; | |
1334 | virt_dev->eps[ep_index].new_ring = | |
1335 | virt_dev->ring_cache[virt_dev->num_rings_cached]; | |
1336 | virt_dev->ring_cache[virt_dev->num_rings_cached] = NULL; | |
1337 | virt_dev->num_rings_cached--; | |
7e393a83 | 1338 | xhci_reinit_cached_ring(xhci, virt_dev->eps[ep_index].new_ring, |
186a7ef1 | 1339 | 1, type); |
74f9fe21 | 1340 | } |
d18240db | 1341 | virt_dev->eps[ep_index].skip = false; |
63a0d9ab | 1342 | ep_ring = virt_dev->eps[ep_index].new_ring; |
28ccd296 | 1343 | ep_ctx->deq = cpu_to_le64(ep_ring->first_seg->dma | ep_ring->cycle_state); |
f94e0186 | 1344 | |
28ccd296 ME |
1345 | ep_ctx->ep_info = cpu_to_le32(xhci_get_endpoint_interval(udev, ep) |
1346 | | EP_MULT(xhci_get_endpoint_mult(udev, ep))); | |
f94e0186 SS |
1347 | |
1348 | /* FIXME dig Mult and streams info out of ep companion desc */ | |
1349 | ||
47692d17 | 1350 | /* Allow 3 retries for everything but isoc; |
7b1fc2ea | 1351 | * CErr shall be set to 0 for Isoch endpoints. |
47692d17 | 1352 | */ |
f94e0186 | 1353 | if (!usb_endpoint_xfer_isoc(&ep->desc)) |
17d65554 | 1354 | ep_ctx->ep_info2 |= cpu_to_le32(ERROR_COUNT(3)); |
f94e0186 | 1355 | else |
17d65554 | 1356 | ep_ctx->ep_info2 |= cpu_to_le32(ERROR_COUNT(0)); |
f94e0186 SS |
1357 | |
1358 | /* Set the max packet size and max burst */ | |
e4f47e36 AS |
1359 | max_packet = GET_MAX_PACKET(usb_endpoint_maxp(&ep->desc)); |
1360 | max_burst = 0; | |
f94e0186 SS |
1361 | switch (udev->speed) { |
1362 | case USB_SPEED_SUPER: | |
b10de142 | 1363 | /* dig out max burst from ep companion desc */ |
e4f47e36 | 1364 | max_burst = ep->ss_ep_comp.bMaxBurst; |
f94e0186 SS |
1365 | break; |
1366 | case USB_SPEED_HIGH: | |
e4f47e36 AS |
1367 | /* Some devices get this wrong */ |
1368 | if (usb_endpoint_xfer_bulk(&ep->desc)) | |
1369 | max_packet = 512; | |
f94e0186 SS |
1370 | /* bits 11:12 specify the number of additional transaction |
1371 | * opportunities per microframe (USB 2.0, section 9.6.6) | |
1372 | */ | |
1373 | if (usb_endpoint_xfer_isoc(&ep->desc) || | |
1374 | usb_endpoint_xfer_int(&ep->desc)) { | |
29cc8897 | 1375 | max_burst = (usb_endpoint_maxp(&ep->desc) |
28ccd296 | 1376 | & 0x1800) >> 11; |
f94e0186 | 1377 | } |
e4f47e36 | 1378 | break; |
f94e0186 SS |
1379 | case USB_SPEED_FULL: |
1380 | case USB_SPEED_LOW: | |
f94e0186 SS |
1381 | break; |
1382 | default: | |
1383 | BUG(); | |
1384 | } | |
e4f47e36 AS |
1385 | ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet) | |
1386 | MAX_BURST(max_burst)); | |
9238f25d | 1387 | max_esit_payload = xhci_get_max_esit_payload(xhci, udev, ep); |
28ccd296 | 1388 | ep_ctx->tx_info = cpu_to_le32(MAX_ESIT_PAYLOAD_FOR_EP(max_esit_payload)); |
9238f25d SS |
1389 | |
1390 | /* | |
1391 | * XXX no idea how to calculate the average TRB buffer length for bulk | |
1392 | * endpoints, as the driver gives us no clue how big each scatter gather | |
1393 | * list entry (or buffer) is going to be. | |
1394 | * | |
1395 | * For isochronous and interrupt endpoints, we set it to the max | |
1396 | * available, until we have new API in the USB core to allow drivers to | |
1397 | * declare how much bandwidth they actually need. | |
1398 | * | |
1399 | * Normally, it would be calculated by taking the total of the buffer | |
1400 | * lengths in the TD and then dividing by the number of TRBs in a TD, | |
1401 | * including link TRBs, No-op TRBs, and Event data TRBs. Since we don't | |
1402 | * use Event Data TRBs, and we don't chain in a link TRB on short | |
1403 | * transfers, we're basically dividing by 1. | |
51eb01a7 AX |
1404 | * |
1405 | * xHCI 1.0 specification indicates that the Average TRB Length should | |
1406 | * be set to 8 for control endpoints. | |
9238f25d | 1407 | */ |
51eb01a7 AX |
1408 | if (usb_endpoint_xfer_control(&ep->desc) && xhci->hci_version == 0x100) |
1409 | ep_ctx->tx_info |= cpu_to_le32(AVG_TRB_LENGTH_FOR_EP(8)); | |
1410 | else | |
1411 | ep_ctx->tx_info |= | |
1412 | cpu_to_le32(AVG_TRB_LENGTH_FOR_EP(max_esit_payload)); | |
9238f25d | 1413 | |
f94e0186 SS |
1414 | /* FIXME Debug endpoint context */ |
1415 | return 0; | |
1416 | } | |
1417 | ||
1418 | void xhci_endpoint_zero(struct xhci_hcd *xhci, | |
1419 | struct xhci_virt_device *virt_dev, | |
1420 | struct usb_host_endpoint *ep) | |
1421 | { | |
1422 | unsigned int ep_index; | |
1423 | struct xhci_ep_ctx *ep_ctx; | |
1424 | ||
1425 | ep_index = xhci_get_endpoint_index(&ep->desc); | |
d115b048 | 1426 | ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index); |
f94e0186 SS |
1427 | |
1428 | ep_ctx->ep_info = 0; | |
1429 | ep_ctx->ep_info2 = 0; | |
8e595a5d | 1430 | ep_ctx->deq = 0; |
f94e0186 SS |
1431 | ep_ctx->tx_info = 0; |
1432 | /* Don't free the endpoint ring until the set interface or configuration | |
1433 | * request succeeds. | |
1434 | */ | |
1435 | } | |
1436 | ||
9af5d71d SS |
1437 | void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info) |
1438 | { | |
1439 | bw_info->ep_interval = 0; | |
1440 | bw_info->mult = 0; | |
1441 | bw_info->num_packets = 0; | |
1442 | bw_info->max_packet_size = 0; | |
1443 | bw_info->type = 0; | |
1444 | bw_info->max_esit_payload = 0; | |
1445 | } | |
1446 | ||
1447 | void xhci_update_bw_info(struct xhci_hcd *xhci, | |
1448 | struct xhci_container_ctx *in_ctx, | |
1449 | struct xhci_input_control_ctx *ctrl_ctx, | |
1450 | struct xhci_virt_device *virt_dev) | |
1451 | { | |
1452 | struct xhci_bw_info *bw_info; | |
1453 | struct xhci_ep_ctx *ep_ctx; | |
1454 | unsigned int ep_type; | |
1455 | int i; | |
1456 | ||
1457 | for (i = 1; i < 31; ++i) { | |
1458 | bw_info = &virt_dev->eps[i].bw_info; | |
1459 | ||
1460 | /* We can't tell what endpoint type is being dropped, but | |
1461 | * unconditionally clearing the bandwidth info for non-periodic | |
1462 | * endpoints should be harmless because the info will never be | |
1463 | * set in the first place. | |
1464 | */ | |
1465 | if (!EP_IS_ADDED(ctrl_ctx, i) && EP_IS_DROPPED(ctrl_ctx, i)) { | |
1466 | /* Dropped endpoint */ | |
1467 | xhci_clear_endpoint_bw_info(bw_info); | |
1468 | continue; | |
1469 | } | |
1470 | ||
1471 | if (EP_IS_ADDED(ctrl_ctx, i)) { | |
1472 | ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, i); | |
1473 | ep_type = CTX_TO_EP_TYPE(le32_to_cpu(ep_ctx->ep_info2)); | |
1474 | ||
1475 | /* Ignore non-periodic endpoints */ | |
1476 | if (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP && | |
1477 | ep_type != ISOC_IN_EP && | |
1478 | ep_type != INT_IN_EP) | |
1479 | continue; | |
1480 | ||
1481 | /* Added or changed endpoint */ | |
1482 | bw_info->ep_interval = CTX_TO_EP_INTERVAL( | |
1483 | le32_to_cpu(ep_ctx->ep_info)); | |
170c0263 SS |
1484 | /* Number of packets and mult are zero-based in the |
1485 | * input context, but we want one-based for the | |
1486 | * interval table. | |
9af5d71d | 1487 | */ |
170c0263 SS |
1488 | bw_info->mult = CTX_TO_EP_MULT( |
1489 | le32_to_cpu(ep_ctx->ep_info)) + 1; | |
9af5d71d SS |
1490 | bw_info->num_packets = CTX_TO_MAX_BURST( |
1491 | le32_to_cpu(ep_ctx->ep_info2)) + 1; | |
1492 | bw_info->max_packet_size = MAX_PACKET_DECODED( | |
1493 | le32_to_cpu(ep_ctx->ep_info2)); | |
1494 | bw_info->type = ep_type; | |
1495 | bw_info->max_esit_payload = CTX_TO_MAX_ESIT_PAYLOAD( | |
1496 | le32_to_cpu(ep_ctx->tx_info)); | |
1497 | } | |
1498 | } | |
1499 | } | |
1500 | ||
f2217e8e SS |
1501 | /* Copy output xhci_ep_ctx to the input xhci_ep_ctx copy. |
1502 | * Useful when you want to change one particular aspect of the endpoint and then | |
1503 | * issue a configure endpoint command. | |
1504 | */ | |
1505 | void xhci_endpoint_copy(struct xhci_hcd *xhci, | |
913a8a34 SS |
1506 | struct xhci_container_ctx *in_ctx, |
1507 | struct xhci_container_ctx *out_ctx, | |
1508 | unsigned int ep_index) | |
f2217e8e SS |
1509 | { |
1510 | struct xhci_ep_ctx *out_ep_ctx; | |
1511 | struct xhci_ep_ctx *in_ep_ctx; | |
1512 | ||
913a8a34 SS |
1513 | out_ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index); |
1514 | in_ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index); | |
f2217e8e SS |
1515 | |
1516 | in_ep_ctx->ep_info = out_ep_ctx->ep_info; | |
1517 | in_ep_ctx->ep_info2 = out_ep_ctx->ep_info2; | |
1518 | in_ep_ctx->deq = out_ep_ctx->deq; | |
1519 | in_ep_ctx->tx_info = out_ep_ctx->tx_info; | |
1520 | } | |
1521 | ||
1522 | /* Copy output xhci_slot_ctx to the input xhci_slot_ctx. | |
1523 | * Useful when you want to change one particular aspect of the endpoint and then | |
1524 | * issue a configure endpoint command. Only the context entries field matters, | |
1525 | * but we'll copy the whole thing anyway. | |
1526 | */ | |
913a8a34 SS |
1527 | void xhci_slot_copy(struct xhci_hcd *xhci, |
1528 | struct xhci_container_ctx *in_ctx, | |
1529 | struct xhci_container_ctx *out_ctx) | |
f2217e8e SS |
1530 | { |
1531 | struct xhci_slot_ctx *in_slot_ctx; | |
1532 | struct xhci_slot_ctx *out_slot_ctx; | |
1533 | ||
913a8a34 SS |
1534 | in_slot_ctx = xhci_get_slot_ctx(xhci, in_ctx); |
1535 | out_slot_ctx = xhci_get_slot_ctx(xhci, out_ctx); | |
f2217e8e SS |
1536 | |
1537 | in_slot_ctx->dev_info = out_slot_ctx->dev_info; | |
1538 | in_slot_ctx->dev_info2 = out_slot_ctx->dev_info2; | |
1539 | in_slot_ctx->tt_info = out_slot_ctx->tt_info; | |
1540 | in_slot_ctx->dev_state = out_slot_ctx->dev_state; | |
1541 | } | |
1542 | ||
254c80a3 JY |
1543 | /* Set up the scratchpad buffer array and scratchpad buffers, if needed. */ |
1544 | static int scratchpad_alloc(struct xhci_hcd *xhci, gfp_t flags) | |
1545 | { | |
1546 | int i; | |
1547 | struct device *dev = xhci_to_hcd(xhci)->self.controller; | |
1548 | int num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2); | |
1549 | ||
d195fcff XR |
1550 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
1551 | "Allocating %d scratchpad buffers", num_sp); | |
254c80a3 JY |
1552 | |
1553 | if (!num_sp) | |
1554 | return 0; | |
1555 | ||
1556 | xhci->scratchpad = kzalloc(sizeof(*xhci->scratchpad), flags); | |
1557 | if (!xhci->scratchpad) | |
1558 | goto fail_sp; | |
1559 | ||
22d45f01 | 1560 | xhci->scratchpad->sp_array = dma_alloc_coherent(dev, |
254c80a3 | 1561 | num_sp * sizeof(u64), |
22d45f01 | 1562 | &xhci->scratchpad->sp_dma, flags); |
254c80a3 JY |
1563 | if (!xhci->scratchpad->sp_array) |
1564 | goto fail_sp2; | |
1565 | ||
1566 | xhci->scratchpad->sp_buffers = kzalloc(sizeof(void *) * num_sp, flags); | |
1567 | if (!xhci->scratchpad->sp_buffers) | |
1568 | goto fail_sp3; | |
1569 | ||
1570 | xhci->scratchpad->sp_dma_buffers = | |
1571 | kzalloc(sizeof(dma_addr_t) * num_sp, flags); | |
1572 | ||
1573 | if (!xhci->scratchpad->sp_dma_buffers) | |
1574 | goto fail_sp4; | |
1575 | ||
28ccd296 | 1576 | xhci->dcbaa->dev_context_ptrs[0] = cpu_to_le64(xhci->scratchpad->sp_dma); |
254c80a3 JY |
1577 | for (i = 0; i < num_sp; i++) { |
1578 | dma_addr_t dma; | |
22d45f01 SAS |
1579 | void *buf = dma_alloc_coherent(dev, xhci->page_size, &dma, |
1580 | flags); | |
254c80a3 JY |
1581 | if (!buf) |
1582 | goto fail_sp5; | |
1583 | ||
1584 | xhci->scratchpad->sp_array[i] = dma; | |
1585 | xhci->scratchpad->sp_buffers[i] = buf; | |
1586 | xhci->scratchpad->sp_dma_buffers[i] = dma; | |
1587 | } | |
1588 | ||
1589 | return 0; | |
1590 | ||
1591 | fail_sp5: | |
1592 | for (i = i - 1; i >= 0; i--) { | |
22d45f01 | 1593 | dma_free_coherent(dev, xhci->page_size, |
254c80a3 JY |
1594 | xhci->scratchpad->sp_buffers[i], |
1595 | xhci->scratchpad->sp_dma_buffers[i]); | |
1596 | } | |
1597 | kfree(xhci->scratchpad->sp_dma_buffers); | |
1598 | ||
1599 | fail_sp4: | |
1600 | kfree(xhci->scratchpad->sp_buffers); | |
1601 | ||
1602 | fail_sp3: | |
22d45f01 | 1603 | dma_free_coherent(dev, num_sp * sizeof(u64), |
254c80a3 JY |
1604 | xhci->scratchpad->sp_array, |
1605 | xhci->scratchpad->sp_dma); | |
1606 | ||
1607 | fail_sp2: | |
1608 | kfree(xhci->scratchpad); | |
1609 | xhci->scratchpad = NULL; | |
1610 | ||
1611 | fail_sp: | |
1612 | return -ENOMEM; | |
1613 | } | |
1614 | ||
1615 | static void scratchpad_free(struct xhci_hcd *xhci) | |
1616 | { | |
1617 | int num_sp; | |
1618 | int i; | |
2a100047 | 1619 | struct device *dev = xhci_to_hcd(xhci)->self.controller; |
254c80a3 JY |
1620 | |
1621 | if (!xhci->scratchpad) | |
1622 | return; | |
1623 | ||
1624 | num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2); | |
1625 | ||
1626 | for (i = 0; i < num_sp; i++) { | |
2a100047 | 1627 | dma_free_coherent(dev, xhci->page_size, |
254c80a3 JY |
1628 | xhci->scratchpad->sp_buffers[i], |
1629 | xhci->scratchpad->sp_dma_buffers[i]); | |
1630 | } | |
1631 | kfree(xhci->scratchpad->sp_dma_buffers); | |
1632 | kfree(xhci->scratchpad->sp_buffers); | |
2a100047 | 1633 | dma_free_coherent(dev, num_sp * sizeof(u64), |
254c80a3 JY |
1634 | xhci->scratchpad->sp_array, |
1635 | xhci->scratchpad->sp_dma); | |
1636 | kfree(xhci->scratchpad); | |
1637 | xhci->scratchpad = NULL; | |
1638 | } | |
1639 | ||
913a8a34 | 1640 | struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci, |
a1d78c16 SS |
1641 | bool allocate_in_ctx, bool allocate_completion, |
1642 | gfp_t mem_flags) | |
913a8a34 SS |
1643 | { |
1644 | struct xhci_command *command; | |
1645 | ||
1646 | command = kzalloc(sizeof(*command), mem_flags); | |
1647 | if (!command) | |
1648 | return NULL; | |
1649 | ||
a1d78c16 SS |
1650 | if (allocate_in_ctx) { |
1651 | command->in_ctx = | |
1652 | xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT, | |
1653 | mem_flags); | |
1654 | if (!command->in_ctx) { | |
1655 | kfree(command); | |
1656 | return NULL; | |
1657 | } | |
06e18291 | 1658 | } |
913a8a34 SS |
1659 | |
1660 | if (allocate_completion) { | |
1661 | command->completion = | |
1662 | kzalloc(sizeof(struct completion), mem_flags); | |
1663 | if (!command->completion) { | |
1664 | xhci_free_container_ctx(xhci, command->in_ctx); | |
06e18291 | 1665 | kfree(command); |
913a8a34 SS |
1666 | return NULL; |
1667 | } | |
1668 | init_completion(command->completion); | |
1669 | } | |
1670 | ||
1671 | command->status = 0; | |
1672 | INIT_LIST_HEAD(&command->cmd_list); | |
1673 | return command; | |
1674 | } | |
1675 | ||
8e51adcc AX |
1676 | void xhci_urb_free_priv(struct xhci_hcd *xhci, struct urb_priv *urb_priv) |
1677 | { | |
2ffdea25 AX |
1678 | if (urb_priv) { |
1679 | kfree(urb_priv->td[0]); | |
1680 | kfree(urb_priv); | |
8e51adcc | 1681 | } |
8e51adcc AX |
1682 | } |
1683 | ||
913a8a34 SS |
1684 | void xhci_free_command(struct xhci_hcd *xhci, |
1685 | struct xhci_command *command) | |
1686 | { | |
1687 | xhci_free_container_ctx(xhci, | |
1688 | command->in_ctx); | |
1689 | kfree(command->completion); | |
1690 | kfree(command); | |
1691 | } | |
1692 | ||
66d4eadd SS |
1693 | void xhci_mem_cleanup(struct xhci_hcd *xhci) |
1694 | { | |
2a100047 | 1695 | struct device *dev = xhci_to_hcd(xhci)->self.controller; |
b92cc66c | 1696 | struct xhci_cd *cur_cd, *next_cd; |
0ebbab37 | 1697 | int size; |
32f1d2c5 | 1698 | int i, j, num_ports; |
0ebbab37 SS |
1699 | |
1700 | /* Free the Event Ring Segment Table and the actual Event Ring */ | |
0ebbab37 SS |
1701 | size = sizeof(struct xhci_erst_entry)*(xhci->erst.num_entries); |
1702 | if (xhci->erst.entries) | |
2a100047 | 1703 | dma_free_coherent(dev, size, |
0ebbab37 SS |
1704 | xhci->erst.entries, xhci->erst.erst_dma_addr); |
1705 | xhci->erst.entries = NULL; | |
d195fcff | 1706 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed ERST"); |
0ebbab37 SS |
1707 | if (xhci->event_ring) |
1708 | xhci_ring_free(xhci, xhci->event_ring); | |
1709 | xhci->event_ring = NULL; | |
d195fcff | 1710 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed event ring"); |
0ebbab37 | 1711 | |
dbc33303 SS |
1712 | if (xhci->lpm_command) |
1713 | xhci_free_command(xhci, xhci->lpm_command); | |
33b2831a | 1714 | xhci->cmd_ring_reserved_trbs = 0; |
0ebbab37 SS |
1715 | if (xhci->cmd_ring) |
1716 | xhci_ring_free(xhci, xhci->cmd_ring); | |
1717 | xhci->cmd_ring = NULL; | |
d195fcff | 1718 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed command ring"); |
b92cc66c EF |
1719 | list_for_each_entry_safe(cur_cd, next_cd, |
1720 | &xhci->cancel_cmd_list, cancel_cmd_list) { | |
1721 | list_del(&cur_cd->cancel_cmd_list); | |
1722 | kfree(cur_cd); | |
1723 | } | |
3ffbba95 SS |
1724 | |
1725 | for (i = 1; i < MAX_HC_SLOTS; ++i) | |
1726 | xhci_free_virt_device(xhci, i); | |
1727 | ||
0ebbab37 SS |
1728 | if (xhci->segment_pool) |
1729 | dma_pool_destroy(xhci->segment_pool); | |
1730 | xhci->segment_pool = NULL; | |
d195fcff | 1731 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed segment pool"); |
3ffbba95 SS |
1732 | |
1733 | if (xhci->device_pool) | |
1734 | dma_pool_destroy(xhci->device_pool); | |
1735 | xhci->device_pool = NULL; | |
d195fcff | 1736 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed device context pool"); |
3ffbba95 | 1737 | |
8df75f42 SS |
1738 | if (xhci->small_streams_pool) |
1739 | dma_pool_destroy(xhci->small_streams_pool); | |
1740 | xhci->small_streams_pool = NULL; | |
d195fcff XR |
1741 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
1742 | "Freed small stream array pool"); | |
8df75f42 SS |
1743 | |
1744 | if (xhci->medium_streams_pool) | |
1745 | dma_pool_destroy(xhci->medium_streams_pool); | |
1746 | xhci->medium_streams_pool = NULL; | |
d195fcff XR |
1747 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
1748 | "Freed medium stream array pool"); | |
8df75f42 | 1749 | |
a74588f9 | 1750 | if (xhci->dcbaa) |
2a100047 | 1751 | dma_free_coherent(dev, sizeof(*xhci->dcbaa), |
a74588f9 SS |
1752 | xhci->dcbaa, xhci->dcbaa->dma); |
1753 | xhci->dcbaa = NULL; | |
3ffbba95 | 1754 | |
5294bea4 | 1755 | scratchpad_free(xhci); |
da6699ce | 1756 | |
88696ae4 VM |
1757 | if (!xhci->rh_bw) |
1758 | goto no_bw; | |
1759 | ||
32f1d2c5 TI |
1760 | num_ports = HCS_MAX_PORTS(xhci->hcs_params1); |
1761 | for (i = 0; i < num_ports; i++) { | |
1762 | struct xhci_interval_bw_table *bwt = &xhci->rh_bw[i].bw_table; | |
1763 | for (j = 0; j < XHCI_MAX_INTERVAL; j++) { | |
1764 | struct list_head *ep = &bwt->interval_bw[j].endpoints; | |
1765 | while (!list_empty(ep)) | |
1766 | list_del_init(ep->next); | |
f8a9e72d ON |
1767 | } |
1768 | } | |
1769 | ||
32f1d2c5 TI |
1770 | for (i = 0; i < num_ports; i++) { |
1771 | struct xhci_tt_bw_info *tt, *n; | |
1772 | list_for_each_entry_safe(tt, n, &xhci->rh_bw[i].tts, tt_list) { | |
1773 | list_del(&tt->tt_list); | |
1774 | kfree(tt); | |
1775 | } | |
f8a9e72d ON |
1776 | } |
1777 | ||
88696ae4 | 1778 | no_bw: |
da6699ce SS |
1779 | xhci->num_usb2_ports = 0; |
1780 | xhci->num_usb3_ports = 0; | |
f8a9e72d | 1781 | xhci->num_active_eps = 0; |
da6699ce SS |
1782 | kfree(xhci->usb2_ports); |
1783 | kfree(xhci->usb3_ports); | |
1784 | kfree(xhci->port_array); | |
839c817c | 1785 | kfree(xhci->rh_bw); |
b630d4b9 | 1786 | kfree(xhci->ext_caps); |
da6699ce | 1787 | |
66d4eadd SS |
1788 | xhci->page_size = 0; |
1789 | xhci->page_shift = 0; | |
20b67cf5 | 1790 | xhci->bus_state[0].bus_suspended = 0; |
f6ff0ac8 | 1791 | xhci->bus_state[1].bus_suspended = 0; |
66d4eadd SS |
1792 | } |
1793 | ||
6648f29d SS |
1794 | static int xhci_test_trb_in_td(struct xhci_hcd *xhci, |
1795 | struct xhci_segment *input_seg, | |
1796 | union xhci_trb *start_trb, | |
1797 | union xhci_trb *end_trb, | |
1798 | dma_addr_t input_dma, | |
1799 | struct xhci_segment *result_seg, | |
1800 | char *test_name, int test_number) | |
1801 | { | |
1802 | unsigned long long start_dma; | |
1803 | unsigned long long end_dma; | |
1804 | struct xhci_segment *seg; | |
1805 | ||
1806 | start_dma = xhci_trb_virt_to_dma(input_seg, start_trb); | |
1807 | end_dma = xhci_trb_virt_to_dma(input_seg, end_trb); | |
1808 | ||
1809 | seg = trb_in_td(input_seg, start_trb, end_trb, input_dma); | |
1810 | if (seg != result_seg) { | |
1811 | xhci_warn(xhci, "WARN: %s TRB math test %d failed!\n", | |
1812 | test_name, test_number); | |
1813 | xhci_warn(xhci, "Tested TRB math w/ seg %p and " | |
1814 | "input DMA 0x%llx\n", | |
1815 | input_seg, | |
1816 | (unsigned long long) input_dma); | |
1817 | xhci_warn(xhci, "starting TRB %p (0x%llx DMA), " | |
1818 | "ending TRB %p (0x%llx DMA)\n", | |
1819 | start_trb, start_dma, | |
1820 | end_trb, end_dma); | |
1821 | xhci_warn(xhci, "Expected seg %p, got seg %p\n", | |
1822 | result_seg, seg); | |
1823 | return -1; | |
1824 | } | |
1825 | return 0; | |
1826 | } | |
1827 | ||
1828 | /* TRB math checks for xhci_trb_in_td(), using the command and event rings. */ | |
1829 | static int xhci_check_trb_in_td_math(struct xhci_hcd *xhci, gfp_t mem_flags) | |
1830 | { | |
1831 | struct { | |
1832 | dma_addr_t input_dma; | |
1833 | struct xhci_segment *result_seg; | |
1834 | } simple_test_vector [] = { | |
1835 | /* A zeroed DMA field should fail */ | |
1836 | { 0, NULL }, | |
1837 | /* One TRB before the ring start should fail */ | |
1838 | { xhci->event_ring->first_seg->dma - 16, NULL }, | |
1839 | /* One byte before the ring start should fail */ | |
1840 | { xhci->event_ring->first_seg->dma - 1, NULL }, | |
1841 | /* Starting TRB should succeed */ | |
1842 | { xhci->event_ring->first_seg->dma, xhci->event_ring->first_seg }, | |
1843 | /* Ending TRB should succeed */ | |
1844 | { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16, | |
1845 | xhci->event_ring->first_seg }, | |
1846 | /* One byte after the ring end should fail */ | |
1847 | { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16 + 1, NULL }, | |
1848 | /* One TRB after the ring end should fail */ | |
1849 | { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT)*16, NULL }, | |
1850 | /* An address of all ones should fail */ | |
1851 | { (dma_addr_t) (~0), NULL }, | |
1852 | }; | |
1853 | struct { | |
1854 | struct xhci_segment *input_seg; | |
1855 | union xhci_trb *start_trb; | |
1856 | union xhci_trb *end_trb; | |
1857 | dma_addr_t input_dma; | |
1858 | struct xhci_segment *result_seg; | |
1859 | } complex_test_vector [] = { | |
1860 | /* Test feeding a valid DMA address from a different ring */ | |
1861 | { .input_seg = xhci->event_ring->first_seg, | |
1862 | .start_trb = xhci->event_ring->first_seg->trbs, | |
1863 | .end_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1], | |
1864 | .input_dma = xhci->cmd_ring->first_seg->dma, | |
1865 | .result_seg = NULL, | |
1866 | }, | |
1867 | /* Test feeding a valid end TRB from a different ring */ | |
1868 | { .input_seg = xhci->event_ring->first_seg, | |
1869 | .start_trb = xhci->event_ring->first_seg->trbs, | |
1870 | .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1], | |
1871 | .input_dma = xhci->cmd_ring->first_seg->dma, | |
1872 | .result_seg = NULL, | |
1873 | }, | |
1874 | /* Test feeding a valid start and end TRB from a different ring */ | |
1875 | { .input_seg = xhci->event_ring->first_seg, | |
1876 | .start_trb = xhci->cmd_ring->first_seg->trbs, | |
1877 | .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1], | |
1878 | .input_dma = xhci->cmd_ring->first_seg->dma, | |
1879 | .result_seg = NULL, | |
1880 | }, | |
1881 | /* TRB in this ring, but after this TD */ | |
1882 | { .input_seg = xhci->event_ring->first_seg, | |
1883 | .start_trb = &xhci->event_ring->first_seg->trbs[0], | |
1884 | .end_trb = &xhci->event_ring->first_seg->trbs[3], | |
1885 | .input_dma = xhci->event_ring->first_seg->dma + 4*16, | |
1886 | .result_seg = NULL, | |
1887 | }, | |
1888 | /* TRB in this ring, but before this TD */ | |
1889 | { .input_seg = xhci->event_ring->first_seg, | |
1890 | .start_trb = &xhci->event_ring->first_seg->trbs[3], | |
1891 | .end_trb = &xhci->event_ring->first_seg->trbs[6], | |
1892 | .input_dma = xhci->event_ring->first_seg->dma + 2*16, | |
1893 | .result_seg = NULL, | |
1894 | }, | |
1895 | /* TRB in this ring, but after this wrapped TD */ | |
1896 | { .input_seg = xhci->event_ring->first_seg, | |
1897 | .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3], | |
1898 | .end_trb = &xhci->event_ring->first_seg->trbs[1], | |
1899 | .input_dma = xhci->event_ring->first_seg->dma + 2*16, | |
1900 | .result_seg = NULL, | |
1901 | }, | |
1902 | /* TRB in this ring, but before this wrapped TD */ | |
1903 | { .input_seg = xhci->event_ring->first_seg, | |
1904 | .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3], | |
1905 | .end_trb = &xhci->event_ring->first_seg->trbs[1], | |
1906 | .input_dma = xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 4)*16, | |
1907 | .result_seg = NULL, | |
1908 | }, | |
1909 | /* TRB not in this ring, and we have a wrapped TD */ | |
1910 | { .input_seg = xhci->event_ring->first_seg, | |
1911 | .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3], | |
1912 | .end_trb = &xhci->event_ring->first_seg->trbs[1], | |
1913 | .input_dma = xhci->cmd_ring->first_seg->dma + 2*16, | |
1914 | .result_seg = NULL, | |
1915 | }, | |
1916 | }; | |
1917 | ||
1918 | unsigned int num_tests; | |
1919 | int i, ret; | |
1920 | ||
e10fa478 | 1921 | num_tests = ARRAY_SIZE(simple_test_vector); |
6648f29d SS |
1922 | for (i = 0; i < num_tests; i++) { |
1923 | ret = xhci_test_trb_in_td(xhci, | |
1924 | xhci->event_ring->first_seg, | |
1925 | xhci->event_ring->first_seg->trbs, | |
1926 | &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1], | |
1927 | simple_test_vector[i].input_dma, | |
1928 | simple_test_vector[i].result_seg, | |
1929 | "Simple", i); | |
1930 | if (ret < 0) | |
1931 | return ret; | |
1932 | } | |
1933 | ||
e10fa478 | 1934 | num_tests = ARRAY_SIZE(complex_test_vector); |
6648f29d SS |
1935 | for (i = 0; i < num_tests; i++) { |
1936 | ret = xhci_test_trb_in_td(xhci, | |
1937 | complex_test_vector[i].input_seg, | |
1938 | complex_test_vector[i].start_trb, | |
1939 | complex_test_vector[i].end_trb, | |
1940 | complex_test_vector[i].input_dma, | |
1941 | complex_test_vector[i].result_seg, | |
1942 | "Complex", i); | |
1943 | if (ret < 0) | |
1944 | return ret; | |
1945 | } | |
1946 | xhci_dbg(xhci, "TRB math tests passed.\n"); | |
1947 | return 0; | |
1948 | } | |
1949 | ||
257d585a SS |
1950 | static void xhci_set_hc_event_deq(struct xhci_hcd *xhci) |
1951 | { | |
1952 | u64 temp; | |
1953 | dma_addr_t deq; | |
1954 | ||
1955 | deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg, | |
1956 | xhci->event_ring->dequeue); | |
1957 | if (deq == 0 && !in_interrupt()) | |
1958 | xhci_warn(xhci, "WARN something wrong with SW event ring " | |
1959 | "dequeue ptr.\n"); | |
1960 | /* Update HC event ring dequeue pointer */ | |
e8b37332 | 1961 | temp = readq(&xhci->ir_set->erst_dequeue); |
257d585a SS |
1962 | temp &= ERST_PTR_MASK; |
1963 | /* Don't clear the EHB bit (which is RW1C) because | |
1964 | * there might be more events to service. | |
1965 | */ | |
1966 | temp &= ~ERST_EHB; | |
d195fcff XR |
1967 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
1968 | "// Write event ring dequeue pointer, " | |
1969 | "preserving EHB bit"); | |
477632df | 1970 | xhci_write_64(xhci, ((u64) deq & (u64) ~ERST_PTR_MASK) | temp, |
257d585a SS |
1971 | &xhci->ir_set->erst_dequeue); |
1972 | } | |
1973 | ||
da6699ce | 1974 | static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int num_ports, |
b630d4b9 | 1975 | __le32 __iomem *addr, u8 major_revision, int max_caps) |
da6699ce SS |
1976 | { |
1977 | u32 temp, port_offset, port_count; | |
1978 | int i; | |
1979 | ||
1980 | if (major_revision > 0x03) { | |
1981 | xhci_warn(xhci, "Ignoring unknown port speed, " | |
1982 | "Ext Cap %p, revision = 0x%x\n", | |
1983 | addr, major_revision); | |
1984 | /* Ignoring port protocol we can't understand. FIXME */ | |
1985 | return; | |
1986 | } | |
1987 | ||
1988 | /* Port offset and count in the third dword, see section 7.2 */ | |
b0ba9720 | 1989 | temp = readl(addr + 2); |
da6699ce SS |
1990 | port_offset = XHCI_EXT_PORT_OFF(temp); |
1991 | port_count = XHCI_EXT_PORT_COUNT(temp); | |
d195fcff XR |
1992 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
1993 | "Ext Cap %p, port offset = %u, " | |
1994 | "count = %u, revision = 0x%x", | |
da6699ce SS |
1995 | addr, port_offset, port_count, major_revision); |
1996 | /* Port count includes the current port offset */ | |
1997 | if (port_offset == 0 || (port_offset + port_count - 1) > num_ports) | |
1998 | /* WTF? "Valid values are ‘1’ to MaxPorts" */ | |
1999 | return; | |
fc71ff75 | 2000 | |
b630d4b9 MN |
2001 | /* cache usb2 port capabilities */ |
2002 | if (major_revision < 0x03 && xhci->num_ext_caps < max_caps) | |
2003 | xhci->ext_caps[xhci->num_ext_caps++] = temp; | |
2004 | ||
fc71ff75 AX |
2005 | /* Check the host's USB2 LPM capability */ |
2006 | if ((xhci->hci_version == 0x96) && (major_revision != 0x03) && | |
2007 | (temp & XHCI_L1C)) { | |
d195fcff XR |
2008 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2009 | "xHCI 0.96: support USB2 software lpm"); | |
fc71ff75 AX |
2010 | xhci->sw_lpm_support = 1; |
2011 | } | |
2012 | ||
2013 | if ((xhci->hci_version >= 0x100) && (major_revision != 0x03)) { | |
d195fcff XR |
2014 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2015 | "xHCI 1.0: support USB2 software lpm"); | |
fc71ff75 AX |
2016 | xhci->sw_lpm_support = 1; |
2017 | if (temp & XHCI_HLC) { | |
d195fcff XR |
2018 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2019 | "xHCI 1.0: support USB2 hardware lpm"); | |
fc71ff75 AX |
2020 | xhci->hw_lpm_support = 1; |
2021 | } | |
2022 | } | |
2023 | ||
da6699ce SS |
2024 | port_offset--; |
2025 | for (i = port_offset; i < (port_offset + port_count); i++) { | |
2026 | /* Duplicate entry. Ignore the port if the revisions differ. */ | |
2027 | if (xhci->port_array[i] != 0) { | |
2028 | xhci_warn(xhci, "Duplicate port entry, Ext Cap %p," | |
2029 | " port %u\n", addr, i); | |
2030 | xhci_warn(xhci, "Port was marked as USB %u, " | |
2031 | "duplicated as USB %u\n", | |
2032 | xhci->port_array[i], major_revision); | |
2033 | /* Only adjust the roothub port counts if we haven't | |
2034 | * found a similar duplicate. | |
2035 | */ | |
2036 | if (xhci->port_array[i] != major_revision && | |
22e04870 | 2037 | xhci->port_array[i] != DUPLICATE_ENTRY) { |
da6699ce SS |
2038 | if (xhci->port_array[i] == 0x03) |
2039 | xhci->num_usb3_ports--; | |
2040 | else | |
2041 | xhci->num_usb2_ports--; | |
22e04870 | 2042 | xhci->port_array[i] = DUPLICATE_ENTRY; |
da6699ce SS |
2043 | } |
2044 | /* FIXME: Should we disable the port? */ | |
f8bbeabc | 2045 | continue; |
da6699ce SS |
2046 | } |
2047 | xhci->port_array[i] = major_revision; | |
2048 | if (major_revision == 0x03) | |
2049 | xhci->num_usb3_ports++; | |
2050 | else | |
2051 | xhci->num_usb2_ports++; | |
2052 | } | |
2053 | /* FIXME: Should we disable ports not in the Extended Capabilities? */ | |
2054 | } | |
2055 | ||
2056 | /* | |
2057 | * Scan the Extended Capabilities for the "Supported Protocol Capabilities" that | |
2058 | * specify what speeds each port is supposed to be. We can't count on the port | |
2059 | * speed bits in the PORTSC register being correct until a device is connected, | |
2060 | * but we need to set up the two fake roothubs with the correct number of USB | |
2061 | * 3.0 and USB 2.0 ports at host controller initialization time. | |
2062 | */ | |
2063 | static int xhci_setup_port_arrays(struct xhci_hcd *xhci, gfp_t flags) | |
2064 | { | |
b630d4b9 MN |
2065 | __le32 __iomem *addr, *tmp_addr; |
2066 | u32 offset, tmp_offset; | |
da6699ce | 2067 | unsigned int num_ports; |
2e27980e | 2068 | int i, j, port_index; |
b630d4b9 | 2069 | int cap_count = 0; |
da6699ce SS |
2070 | |
2071 | addr = &xhci->cap_regs->hcc_params; | |
b0ba9720 | 2072 | offset = XHCI_HCC_EXT_CAPS(readl(addr)); |
da6699ce SS |
2073 | if (offset == 0) { |
2074 | xhci_err(xhci, "No Extended Capability registers, " | |
2075 | "unable to set up roothub.\n"); | |
2076 | return -ENODEV; | |
2077 | } | |
2078 | ||
2079 | num_ports = HCS_MAX_PORTS(xhci->hcs_params1); | |
2080 | xhci->port_array = kzalloc(sizeof(*xhci->port_array)*num_ports, flags); | |
2081 | if (!xhci->port_array) | |
2082 | return -ENOMEM; | |
2083 | ||
839c817c SS |
2084 | xhci->rh_bw = kzalloc(sizeof(*xhci->rh_bw)*num_ports, flags); |
2085 | if (!xhci->rh_bw) | |
2086 | return -ENOMEM; | |
2e27980e SS |
2087 | for (i = 0; i < num_ports; i++) { |
2088 | struct xhci_interval_bw_table *bw_table; | |
2089 | ||
839c817c | 2090 | INIT_LIST_HEAD(&xhci->rh_bw[i].tts); |
2e27980e SS |
2091 | bw_table = &xhci->rh_bw[i].bw_table; |
2092 | for (j = 0; j < XHCI_MAX_INTERVAL; j++) | |
2093 | INIT_LIST_HEAD(&bw_table->interval_bw[j].endpoints); | |
2094 | } | |
839c817c | 2095 | |
da6699ce SS |
2096 | /* |
2097 | * For whatever reason, the first capability offset is from the | |
2098 | * capability register base, not from the HCCPARAMS register. | |
2099 | * See section 5.3.6 for offset calculation. | |
2100 | */ | |
2101 | addr = &xhci->cap_regs->hc_capbase + offset; | |
b630d4b9 MN |
2102 | |
2103 | tmp_addr = addr; | |
2104 | tmp_offset = offset; | |
2105 | ||
2106 | /* count extended protocol capability entries for later caching */ | |
2107 | do { | |
2108 | u32 cap_id; | |
b0ba9720 | 2109 | cap_id = readl(tmp_addr); |
b630d4b9 MN |
2110 | if (XHCI_EXT_CAPS_ID(cap_id) == XHCI_EXT_CAPS_PROTOCOL) |
2111 | cap_count++; | |
2112 | tmp_offset = XHCI_EXT_CAPS_NEXT(cap_id); | |
2113 | tmp_addr += tmp_offset; | |
2114 | } while (tmp_offset); | |
2115 | ||
2116 | xhci->ext_caps = kzalloc(sizeof(*xhci->ext_caps) * cap_count, flags); | |
2117 | if (!xhci->ext_caps) | |
2118 | return -ENOMEM; | |
2119 | ||
da6699ce SS |
2120 | while (1) { |
2121 | u32 cap_id; | |
2122 | ||
b0ba9720 | 2123 | cap_id = readl(addr); |
da6699ce SS |
2124 | if (XHCI_EXT_CAPS_ID(cap_id) == XHCI_EXT_CAPS_PROTOCOL) |
2125 | xhci_add_in_port(xhci, num_ports, addr, | |
b630d4b9 MN |
2126 | (u8) XHCI_EXT_PORT_MAJOR(cap_id), |
2127 | cap_count); | |
da6699ce SS |
2128 | offset = XHCI_EXT_CAPS_NEXT(cap_id); |
2129 | if (!offset || (xhci->num_usb2_ports + xhci->num_usb3_ports) | |
2130 | == num_ports) | |
2131 | break; | |
2132 | /* | |
2133 | * Once you're into the Extended Capabilities, the offset is | |
2134 | * always relative to the register holding the offset. | |
2135 | */ | |
2136 | addr += offset; | |
2137 | } | |
2138 | ||
2139 | if (xhci->num_usb2_ports == 0 && xhci->num_usb3_ports == 0) { | |
2140 | xhci_warn(xhci, "No ports on the roothubs?\n"); | |
2141 | return -ENODEV; | |
2142 | } | |
d195fcff XR |
2143 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2144 | "Found %u USB 2.0 ports and %u USB 3.0 ports.", | |
da6699ce | 2145 | xhci->num_usb2_ports, xhci->num_usb3_ports); |
d30b2a20 SS |
2146 | |
2147 | /* Place limits on the number of roothub ports so that the hub | |
2148 | * descriptors aren't longer than the USB core will allocate. | |
2149 | */ | |
2150 | if (xhci->num_usb3_ports > 15) { | |
d195fcff XR |
2151 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2152 | "Limiting USB 3.0 roothub ports to 15."); | |
d30b2a20 SS |
2153 | xhci->num_usb3_ports = 15; |
2154 | } | |
2155 | if (xhci->num_usb2_ports > USB_MAXCHILDREN) { | |
d195fcff XR |
2156 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2157 | "Limiting USB 2.0 roothub ports to %u.", | |
d30b2a20 SS |
2158 | USB_MAXCHILDREN); |
2159 | xhci->num_usb2_ports = USB_MAXCHILDREN; | |
2160 | } | |
2161 | ||
da6699ce SS |
2162 | /* |
2163 | * Note we could have all USB 3.0 ports, or all USB 2.0 ports. | |
2164 | * Not sure how the USB core will handle a hub with no ports... | |
2165 | */ | |
2166 | if (xhci->num_usb2_ports) { | |
2167 | xhci->usb2_ports = kmalloc(sizeof(*xhci->usb2_ports)* | |
2168 | xhci->num_usb2_ports, flags); | |
2169 | if (!xhci->usb2_ports) | |
2170 | return -ENOMEM; | |
2171 | ||
2172 | port_index = 0; | |
f8bbeabc SS |
2173 | for (i = 0; i < num_ports; i++) { |
2174 | if (xhci->port_array[i] == 0x03 || | |
2175 | xhci->port_array[i] == 0 || | |
22e04870 | 2176 | xhci->port_array[i] == DUPLICATE_ENTRY) |
f8bbeabc SS |
2177 | continue; |
2178 | ||
2179 | xhci->usb2_ports[port_index] = | |
2180 | &xhci->op_regs->port_status_base + | |
2181 | NUM_PORT_REGS*i; | |
d195fcff XR |
2182 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2183 | "USB 2.0 port at index %u, " | |
2184 | "addr = %p", i, | |
f8bbeabc SS |
2185 | xhci->usb2_ports[port_index]); |
2186 | port_index++; | |
d30b2a20 SS |
2187 | if (port_index == xhci->num_usb2_ports) |
2188 | break; | |
f8bbeabc | 2189 | } |
da6699ce SS |
2190 | } |
2191 | if (xhci->num_usb3_ports) { | |
2192 | xhci->usb3_ports = kmalloc(sizeof(*xhci->usb3_ports)* | |
2193 | xhci->num_usb3_ports, flags); | |
2194 | if (!xhci->usb3_ports) | |
2195 | return -ENOMEM; | |
2196 | ||
2197 | port_index = 0; | |
2198 | for (i = 0; i < num_ports; i++) | |
2199 | if (xhci->port_array[i] == 0x03) { | |
2200 | xhci->usb3_ports[port_index] = | |
2201 | &xhci->op_regs->port_status_base + | |
2202 | NUM_PORT_REGS*i; | |
d195fcff XR |
2203 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2204 | "USB 3.0 port at index %u, " | |
2205 | "addr = %p", i, | |
da6699ce SS |
2206 | xhci->usb3_ports[port_index]); |
2207 | port_index++; | |
d30b2a20 SS |
2208 | if (port_index == xhci->num_usb3_ports) |
2209 | break; | |
da6699ce SS |
2210 | } |
2211 | } | |
2212 | return 0; | |
2213 | } | |
6648f29d | 2214 | |
66d4eadd SS |
2215 | int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags) |
2216 | { | |
0ebbab37 SS |
2217 | dma_addr_t dma; |
2218 | struct device *dev = xhci_to_hcd(xhci)->self.controller; | |
66d4eadd | 2219 | unsigned int val, val2; |
8e595a5d | 2220 | u64 val_64; |
0ebbab37 | 2221 | struct xhci_segment *seg; |
623bef9e | 2222 | u32 page_size, temp; |
66d4eadd SS |
2223 | int i; |
2224 | ||
331de00a SA |
2225 | INIT_LIST_HEAD(&xhci->cancel_cmd_list); |
2226 | ||
b0ba9720 | 2227 | page_size = readl(&xhci->op_regs->page_size); |
d195fcff XR |
2228 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2229 | "Supported page size register = 0x%x", page_size); | |
66d4eadd SS |
2230 | for (i = 0; i < 16; i++) { |
2231 | if ((0x1 & page_size) != 0) | |
2232 | break; | |
2233 | page_size = page_size >> 1; | |
2234 | } | |
2235 | if (i < 16) | |
d195fcff XR |
2236 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2237 | "Supported page size of %iK", (1 << (i+12)) / 1024); | |
66d4eadd SS |
2238 | else |
2239 | xhci_warn(xhci, "WARN: no supported page size\n"); | |
2240 | /* Use 4K pages, since that's common and the minimum the HC supports */ | |
2241 | xhci->page_shift = 12; | |
2242 | xhci->page_size = 1 << xhci->page_shift; | |
d195fcff XR |
2243 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2244 | "HCD page size set to %iK", xhci->page_size / 1024); | |
66d4eadd SS |
2245 | |
2246 | /* | |
2247 | * Program the Number of Device Slots Enabled field in the CONFIG | |
2248 | * register with the max value of slots the HC can handle. | |
2249 | */ | |
b0ba9720 | 2250 | val = HCS_MAX_SLOTS(readl(&xhci->cap_regs->hcs_params1)); |
d195fcff XR |
2251 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2252 | "// xHC can handle at most %d device slots.", val); | |
b0ba9720 | 2253 | val2 = readl(&xhci->op_regs->config_reg); |
66d4eadd | 2254 | val |= (val2 & ~HCS_SLOTS_MASK); |
d195fcff XR |
2255 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2256 | "// Setting Max device slots reg = 0x%x.", val); | |
204b7793 | 2257 | writel(val, &xhci->op_regs->config_reg); |
66d4eadd | 2258 | |
a74588f9 SS |
2259 | /* |
2260 | * Section 5.4.8 - doorbell array must be | |
2261 | * "physically contiguous and 64-byte (cache line) aligned". | |
2262 | */ | |
22d45f01 SAS |
2263 | xhci->dcbaa = dma_alloc_coherent(dev, sizeof(*xhci->dcbaa), &dma, |
2264 | GFP_KERNEL); | |
a74588f9 SS |
2265 | if (!xhci->dcbaa) |
2266 | goto fail; | |
2267 | memset(xhci->dcbaa, 0, sizeof *(xhci->dcbaa)); | |
2268 | xhci->dcbaa->dma = dma; | |
d195fcff XR |
2269 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2270 | "// Device context base array address = 0x%llx (DMA), %p (virt)", | |
700e2052 | 2271 | (unsigned long long)xhci->dcbaa->dma, xhci->dcbaa); |
477632df | 2272 | xhci_write_64(xhci, dma, &xhci->op_regs->dcbaa_ptr); |
a74588f9 | 2273 | |
0ebbab37 SS |
2274 | /* |
2275 | * Initialize the ring segment pool. The ring must be a contiguous | |
2276 | * structure comprised of TRBs. The TRBs must be 16 byte aligned, | |
2277 | * however, the command ring segment needs 64-byte aligned segments, | |
2278 | * so we pick the greater alignment need. | |
2279 | */ | |
2280 | xhci->segment_pool = dma_pool_create("xHCI ring segments", dev, | |
eb8ccd2b | 2281 | TRB_SEGMENT_SIZE, 64, xhci->page_size); |
d115b048 | 2282 | |
3ffbba95 | 2283 | /* See Table 46 and Note on Figure 55 */ |
3ffbba95 | 2284 | xhci->device_pool = dma_pool_create("xHCI input/output contexts", dev, |
d115b048 | 2285 | 2112, 64, xhci->page_size); |
3ffbba95 | 2286 | if (!xhci->segment_pool || !xhci->device_pool) |
0ebbab37 SS |
2287 | goto fail; |
2288 | ||
8df75f42 SS |
2289 | /* Linear stream context arrays don't have any boundary restrictions, |
2290 | * and only need to be 16-byte aligned. | |
2291 | */ | |
2292 | xhci->small_streams_pool = | |
2293 | dma_pool_create("xHCI 256 byte stream ctx arrays", | |
2294 | dev, SMALL_STREAM_ARRAY_SIZE, 16, 0); | |
2295 | xhci->medium_streams_pool = | |
2296 | dma_pool_create("xHCI 1KB stream ctx arrays", | |
2297 | dev, MEDIUM_STREAM_ARRAY_SIZE, 16, 0); | |
2298 | /* Any stream context array bigger than MEDIUM_STREAM_ARRAY_SIZE | |
22d45f01 | 2299 | * will be allocated with dma_alloc_coherent() |
8df75f42 SS |
2300 | */ |
2301 | ||
2302 | if (!xhci->small_streams_pool || !xhci->medium_streams_pool) | |
2303 | goto fail; | |
2304 | ||
0ebbab37 | 2305 | /* Set up the command ring to have one segments for now. */ |
186a7ef1 | 2306 | xhci->cmd_ring = xhci_ring_alloc(xhci, 1, 1, TYPE_COMMAND, flags); |
0ebbab37 SS |
2307 | if (!xhci->cmd_ring) |
2308 | goto fail; | |
d195fcff XR |
2309 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2310 | "Allocated command ring at %p", xhci->cmd_ring); | |
2311 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "First segment DMA is 0x%llx", | |
700e2052 | 2312 | (unsigned long long)xhci->cmd_ring->first_seg->dma); |
0ebbab37 SS |
2313 | |
2314 | /* Set the address in the Command Ring Control register */ | |
e8b37332 | 2315 | val_64 = readq(&xhci->op_regs->cmd_ring); |
8e595a5d SS |
2316 | val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) | |
2317 | (xhci->cmd_ring->first_seg->dma & (u64) ~CMD_RING_RSVD_BITS) | | |
0ebbab37 | 2318 | xhci->cmd_ring->cycle_state; |
d195fcff XR |
2319 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2320 | "// Setting command ring address to 0x%x", val); | |
477632df | 2321 | xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring); |
0ebbab37 SS |
2322 | xhci_dbg_cmd_ptrs(xhci); |
2323 | ||
dbc33303 SS |
2324 | xhci->lpm_command = xhci_alloc_command(xhci, true, true, flags); |
2325 | if (!xhci->lpm_command) | |
2326 | goto fail; | |
2327 | ||
2328 | /* Reserve one command ring TRB for disabling LPM. | |
2329 | * Since the USB core grabs the shared usb_bus bandwidth mutex before | |
2330 | * disabling LPM, we only need to reserve one TRB for all devices. | |
2331 | */ | |
2332 | xhci->cmd_ring_reserved_trbs++; | |
2333 | ||
b0ba9720 | 2334 | val = readl(&xhci->cap_regs->db_off); |
0ebbab37 | 2335 | val &= DBOFF_MASK; |
d195fcff XR |
2336 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2337 | "// Doorbell array is located at offset 0x%x" | |
2338 | " from cap regs base addr", val); | |
c50a00f8 | 2339 | xhci->dba = (void __iomem *) xhci->cap_regs + val; |
0ebbab37 SS |
2340 | xhci_dbg_regs(xhci); |
2341 | xhci_print_run_regs(xhci); | |
2342 | /* Set ir_set to interrupt register set 0 */ | |
c50a00f8 | 2343 | xhci->ir_set = &xhci->run_regs->ir_set[0]; |
0ebbab37 SS |
2344 | |
2345 | /* | |
2346 | * Event ring setup: Allocate a normal ring, but also setup | |
2347 | * the event ring segment table (ERST). Section 4.9.3. | |
2348 | */ | |
d195fcff | 2349 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Allocating event ring"); |
186a7ef1 | 2350 | xhci->event_ring = xhci_ring_alloc(xhci, ERST_NUM_SEGS, 1, TYPE_EVENT, |
7e393a83 | 2351 | flags); |
0ebbab37 SS |
2352 | if (!xhci->event_ring) |
2353 | goto fail; | |
6648f29d SS |
2354 | if (xhci_check_trb_in_td_math(xhci, flags) < 0) |
2355 | goto fail; | |
0ebbab37 | 2356 | |
22d45f01 SAS |
2357 | xhci->erst.entries = dma_alloc_coherent(dev, |
2358 | sizeof(struct xhci_erst_entry) * ERST_NUM_SEGS, &dma, | |
2359 | GFP_KERNEL); | |
0ebbab37 SS |
2360 | if (!xhci->erst.entries) |
2361 | goto fail; | |
d195fcff XR |
2362 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2363 | "// Allocated event ring segment table at 0x%llx", | |
700e2052 | 2364 | (unsigned long long)dma); |
0ebbab37 SS |
2365 | |
2366 | memset(xhci->erst.entries, 0, sizeof(struct xhci_erst_entry)*ERST_NUM_SEGS); | |
2367 | xhci->erst.num_entries = ERST_NUM_SEGS; | |
2368 | xhci->erst.erst_dma_addr = dma; | |
d195fcff XR |
2369 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2370 | "Set ERST to 0; private num segs = %i, virt addr = %p, dma addr = 0x%llx", | |
0ebbab37 | 2371 | xhci->erst.num_entries, |
700e2052 GKH |
2372 | xhci->erst.entries, |
2373 | (unsigned long long)xhci->erst.erst_dma_addr); | |
0ebbab37 SS |
2374 | |
2375 | /* set ring base address and size for each segment table entry */ | |
2376 | for (val = 0, seg = xhci->event_ring->first_seg; val < ERST_NUM_SEGS; val++) { | |
2377 | struct xhci_erst_entry *entry = &xhci->erst.entries[val]; | |
28ccd296 ME |
2378 | entry->seg_addr = cpu_to_le64(seg->dma); |
2379 | entry->seg_size = cpu_to_le32(TRBS_PER_SEGMENT); | |
0ebbab37 SS |
2380 | entry->rsvd = 0; |
2381 | seg = seg->next; | |
2382 | } | |
2383 | ||
2384 | /* set ERST count with the number of entries in the segment table */ | |
b0ba9720 | 2385 | val = readl(&xhci->ir_set->erst_size); |
0ebbab37 SS |
2386 | val &= ERST_SIZE_MASK; |
2387 | val |= ERST_NUM_SEGS; | |
d195fcff XR |
2388 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2389 | "// Write ERST size = %i to ir_set 0 (some bits preserved)", | |
0ebbab37 | 2390 | val); |
204b7793 | 2391 | writel(val, &xhci->ir_set->erst_size); |
0ebbab37 | 2392 | |
d195fcff XR |
2393 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2394 | "// Set ERST entries to point to event ring."); | |
0ebbab37 | 2395 | /* set the segment table base address */ |
d195fcff XR |
2396 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2397 | "// Set ERST base address for ir_set 0 = 0x%llx", | |
700e2052 | 2398 | (unsigned long long)xhci->erst.erst_dma_addr); |
e8b37332 | 2399 | val_64 = readq(&xhci->ir_set->erst_base); |
8e595a5d SS |
2400 | val_64 &= ERST_PTR_MASK; |
2401 | val_64 |= (xhci->erst.erst_dma_addr & (u64) ~ERST_PTR_MASK); | |
477632df | 2402 | xhci_write_64(xhci, val_64, &xhci->ir_set->erst_base); |
0ebbab37 SS |
2403 | |
2404 | /* Set the event ring dequeue address */ | |
23e3be11 | 2405 | xhci_set_hc_event_deq(xhci); |
d195fcff XR |
2406 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2407 | "Wrote ERST address to ir_set 0."); | |
09ece30e | 2408 | xhci_print_ir_set(xhci, 0); |
0ebbab37 SS |
2409 | |
2410 | /* | |
2411 | * XXX: Might need to set the Interrupter Moderation Register to | |
2412 | * something other than the default (~1ms minimum between interrupts). | |
2413 | * See section 5.5.1.2. | |
2414 | */ | |
3ffbba95 SS |
2415 | init_completion(&xhci->addr_dev); |
2416 | for (i = 0; i < MAX_HC_SLOTS; ++i) | |
326b4810 | 2417 | xhci->devs[i] = NULL; |
f6ff0ac8 | 2418 | for (i = 0; i < USB_MAXCHILDREN; ++i) { |
20b67cf5 | 2419 | xhci->bus_state[0].resume_done[i] = 0; |
f6ff0ac8 | 2420 | xhci->bus_state[1].resume_done[i] = 0; |
8b3d4570 SS |
2421 | /* Only the USB 2.0 completions will ever be used. */ |
2422 | init_completion(&xhci->bus_state[1].rexit_done[i]); | |
f6ff0ac8 | 2423 | } |
66d4eadd | 2424 | |
254c80a3 JY |
2425 | if (scratchpad_alloc(xhci, flags)) |
2426 | goto fail; | |
da6699ce SS |
2427 | if (xhci_setup_port_arrays(xhci, flags)) |
2428 | goto fail; | |
254c80a3 | 2429 | |
623bef9e SS |
2430 | /* Enable USB 3.0 device notifications for function remote wake, which |
2431 | * is necessary for allowing USB 3.0 devices to do remote wakeup from | |
2432 | * U3 (device suspend). | |
2433 | */ | |
b0ba9720 | 2434 | temp = readl(&xhci->op_regs->dev_notification); |
623bef9e SS |
2435 | temp &= ~DEV_NOTE_MASK; |
2436 | temp |= DEV_NOTE_FWAKE; | |
204b7793 | 2437 | writel(temp, &xhci->op_regs->dev_notification); |
623bef9e | 2438 | |
66d4eadd | 2439 | return 0; |
254c80a3 | 2440 | |
66d4eadd SS |
2441 | fail: |
2442 | xhci_warn(xhci, "Couldn't initialize memory\n"); | |
159e1fcc SS |
2443 | xhci_halt(xhci); |
2444 | xhci_reset(xhci); | |
66d4eadd SS |
2445 | xhci_mem_cleanup(xhci); |
2446 | return -ENOMEM; | |
2447 | } |