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Commit | Line | Data |
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66d4eadd SS |
1 | /* |
2 | * xHCI host controller driver | |
3 | * | |
4 | * Copyright (C) 2008 Intel Corp. | |
5 | * | |
6 | * Author: Sarah Sharp | |
7 | * Some code borrowed from the Linux EHCI driver. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | * for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software Foundation, | |
20 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
23 | #include <linux/usb.h> | |
0ebbab37 | 24 | #include <linux/pci.h> |
5a0e3ad6 | 25 | #include <linux/slab.h> |
527c6d7f | 26 | #include <linux/dmapool.h> |
008eb957 | 27 | #include <linux/dma-mapping.h> |
66d4eadd SS |
28 | |
29 | #include "xhci.h" | |
3a7fa5be | 30 | #include "xhci-trace.h" |
66d4eadd | 31 | |
0ebbab37 SS |
32 | /* |
33 | * Allocates a generic ring segment from the ring pool, sets the dma address, | |
34 | * initializes the segment to zero, and sets the private next pointer to NULL. | |
35 | * | |
36 | * Section 4.11.1.1: | |
37 | * "All components of all Command and Transfer TRBs shall be initialized to '0'" | |
38 | */ | |
186a7ef1 | 39 | static struct xhci_segment *xhci_segment_alloc(struct xhci_hcd *xhci, |
f9c589e1 MN |
40 | unsigned int cycle_state, |
41 | unsigned int max_packet, | |
42 | gfp_t flags) | |
0ebbab37 SS |
43 | { |
44 | struct xhci_segment *seg; | |
45 | dma_addr_t dma; | |
186a7ef1 | 46 | int i; |
0ebbab37 SS |
47 | |
48 | seg = kzalloc(sizeof *seg, flags); | |
49 | if (!seg) | |
326b4810 | 50 | return NULL; |
0ebbab37 | 51 | |
84c1eeb0 | 52 | seg->trbs = dma_pool_zalloc(xhci->segment_pool, flags, &dma); |
0ebbab37 SS |
53 | if (!seg->trbs) { |
54 | kfree(seg); | |
326b4810 | 55 | return NULL; |
0ebbab37 | 56 | } |
0ebbab37 | 57 | |
f9c589e1 MN |
58 | if (max_packet) { |
59 | seg->bounce_buf = kzalloc(max_packet, flags | GFP_DMA); | |
60 | if (!seg->bounce_buf) { | |
61 | dma_pool_free(xhci->segment_pool, seg->trbs, dma); | |
62 | kfree(seg); | |
63 | return NULL; | |
64 | } | |
65 | } | |
186a7ef1 AX |
66 | /* If the cycle state is 0, set the cycle bit to 1 for all the TRBs */ |
67 | if (cycle_state == 0) { | |
68 | for (i = 0; i < TRBS_PER_SEGMENT; i++) | |
58719487 | 69 | seg->trbs[i].link.control |= cpu_to_le32(TRB_CYCLE); |
186a7ef1 | 70 | } |
0ebbab37 SS |
71 | seg->dma = dma; |
72 | seg->next = NULL; | |
73 | ||
74 | return seg; | |
75 | } | |
76 | ||
77 | static void xhci_segment_free(struct xhci_hcd *xhci, struct xhci_segment *seg) | |
78 | { | |
0ebbab37 | 79 | if (seg->trbs) { |
0ebbab37 SS |
80 | dma_pool_free(xhci->segment_pool, seg->trbs, seg->dma); |
81 | seg->trbs = NULL; | |
82 | } | |
f9c589e1 | 83 | kfree(seg->bounce_buf); |
0ebbab37 SS |
84 | kfree(seg); |
85 | } | |
86 | ||
70d43601 AX |
87 | static void xhci_free_segments_for_ring(struct xhci_hcd *xhci, |
88 | struct xhci_segment *first) | |
89 | { | |
90 | struct xhci_segment *seg; | |
91 | ||
92 | seg = first->next; | |
93 | while (seg != first) { | |
94 | struct xhci_segment *next = seg->next; | |
95 | xhci_segment_free(xhci, seg); | |
96 | seg = next; | |
97 | } | |
98 | xhci_segment_free(xhci, first); | |
99 | } | |
100 | ||
0ebbab37 SS |
101 | /* |
102 | * Make the prev segment point to the next segment. | |
103 | * | |
104 | * Change the last TRB in the prev segment to be a Link TRB which points to the | |
105 | * DMA address of the next segment. The caller needs to set any Link TRB | |
106 | * related flags, such as End TRB, Toggle Cycle, and no snoop. | |
107 | */ | |
108 | static void xhci_link_segments(struct xhci_hcd *xhci, struct xhci_segment *prev, | |
3b72fca0 | 109 | struct xhci_segment *next, enum xhci_ring_type type) |
0ebbab37 SS |
110 | { |
111 | u32 val; | |
112 | ||
113 | if (!prev || !next) | |
114 | return; | |
115 | prev->next = next; | |
3b72fca0 | 116 | if (type != TYPE_EVENT) { |
f5960b69 ME |
117 | prev->trbs[TRBS_PER_SEGMENT-1].link.segment_ptr = |
118 | cpu_to_le64(next->dma); | |
0ebbab37 SS |
119 | |
120 | /* Set the last TRB in the segment to have a TRB type ID of Link TRB */ | |
28ccd296 | 121 | val = le32_to_cpu(prev->trbs[TRBS_PER_SEGMENT-1].link.control); |
0ebbab37 SS |
122 | val &= ~TRB_TYPE_BITMASK; |
123 | val |= TRB_TYPE(TRB_LINK); | |
b0567b3f | 124 | /* Always set the chain bit with 0.95 hardware */ |
7e393a83 AX |
125 | /* Set chain bit for isoc rings on AMD 0.96 host */ |
126 | if (xhci_link_trb_quirk(xhci) || | |
3b72fca0 AX |
127 | (type == TYPE_ISOC && |
128 | (xhci->quirks & XHCI_AMD_0x96_HOST))) | |
b0567b3f | 129 | val |= TRB_CHAIN; |
28ccd296 | 130 | prev->trbs[TRBS_PER_SEGMENT-1].link.control = cpu_to_le32(val); |
0ebbab37 | 131 | } |
0ebbab37 SS |
132 | } |
133 | ||
8dfec614 AX |
134 | /* |
135 | * Link the ring to the new segments. | |
136 | * Set Toggle Cycle for the new ring if needed. | |
137 | */ | |
138 | static void xhci_link_rings(struct xhci_hcd *xhci, struct xhci_ring *ring, | |
139 | struct xhci_segment *first, struct xhci_segment *last, | |
140 | unsigned int num_segs) | |
141 | { | |
142 | struct xhci_segment *next; | |
143 | ||
144 | if (!ring || !first || !last) | |
145 | return; | |
146 | ||
147 | next = ring->enq_seg->next; | |
148 | xhci_link_segments(xhci, ring->enq_seg, first, ring->type); | |
149 | xhci_link_segments(xhci, last, next, ring->type); | |
150 | ring->num_segs += num_segs; | |
151 | ring->num_trbs_free += (TRBS_PER_SEGMENT - 1) * num_segs; | |
152 | ||
153 | if (ring->type != TYPE_EVENT && ring->enq_seg == ring->last_seg) { | |
154 | ring->last_seg->trbs[TRBS_PER_SEGMENT-1].link.control | |
155 | &= ~cpu_to_le32(LINK_TOGGLE); | |
156 | last->trbs[TRBS_PER_SEGMENT-1].link.control | |
157 | |= cpu_to_le32(LINK_TOGGLE); | |
158 | ring->last_seg = last; | |
159 | } | |
160 | } | |
161 | ||
15341303 GH |
162 | /* |
163 | * We need a radix tree for mapping physical addresses of TRBs to which stream | |
164 | * ID they belong to. We need to do this because the host controller won't tell | |
165 | * us which stream ring the TRB came from. We could store the stream ID in an | |
166 | * event data TRB, but that doesn't help us for the cancellation case, since the | |
167 | * endpoint may stop before it reaches that event data TRB. | |
168 | * | |
169 | * The radix tree maps the upper portion of the TRB DMA address to a ring | |
170 | * segment that has the same upper portion of DMA addresses. For example, say I | |
84c1e40f | 171 | * have segments of size 1KB, that are always 1KB aligned. A segment may |
15341303 GH |
172 | * start at 0x10c91000 and end at 0x10c913f0. If I use the upper 10 bits, the |
173 | * key to the stream ID is 0x43244. I can use the DMA address of the TRB to | |
174 | * pass the radix tree a key to get the right stream ID: | |
175 | * | |
176 | * 0x10c90fff >> 10 = 0x43243 | |
177 | * 0x10c912c0 >> 10 = 0x43244 | |
178 | * 0x10c91400 >> 10 = 0x43245 | |
179 | * | |
180 | * Obviously, only those TRBs with DMA addresses that are within the segment | |
181 | * will make the radix tree return the stream ID for that ring. | |
182 | * | |
183 | * Caveats for the radix tree: | |
184 | * | |
185 | * The radix tree uses an unsigned long as a key pair. On 32-bit systems, an | |
186 | * unsigned long will be 32-bits; on a 64-bit system an unsigned long will be | |
187 | * 64-bits. Since we only request 32-bit DMA addresses, we can use that as the | |
188 | * key on 32-bit or 64-bit systems (it would also be fine if we asked for 64-bit | |
189 | * PCI DMA addresses on a 64-bit system). There might be a problem on 32-bit | |
190 | * extended systems (where the DMA address can be bigger than 32-bits), | |
191 | * if we allow the PCI dma mask to be bigger than 32-bits. So don't do that. | |
192 | */ | |
d5734223 SS |
193 | static int xhci_insert_segment_mapping(struct radix_tree_root *trb_address_map, |
194 | struct xhci_ring *ring, | |
195 | struct xhci_segment *seg, | |
196 | gfp_t mem_flags) | |
15341303 | 197 | { |
15341303 GH |
198 | unsigned long key; |
199 | int ret; | |
200 | ||
d5734223 SS |
201 | key = (unsigned long)(seg->dma >> TRB_SEGMENT_SHIFT); |
202 | /* Skip any segments that were already added. */ | |
203 | if (radix_tree_lookup(trb_address_map, key)) | |
15341303 GH |
204 | return 0; |
205 | ||
d5734223 SS |
206 | ret = radix_tree_maybe_preload(mem_flags); |
207 | if (ret) | |
208 | return ret; | |
209 | ret = radix_tree_insert(trb_address_map, | |
210 | key, ring); | |
211 | radix_tree_preload_end(); | |
212 | return ret; | |
213 | } | |
15341303 | 214 | |
d5734223 SS |
215 | static void xhci_remove_segment_mapping(struct radix_tree_root *trb_address_map, |
216 | struct xhci_segment *seg) | |
217 | { | |
218 | unsigned long key; | |
219 | ||
220 | key = (unsigned long)(seg->dma >> TRB_SEGMENT_SHIFT); | |
221 | if (radix_tree_lookup(trb_address_map, key)) | |
222 | radix_tree_delete(trb_address_map, key); | |
223 | } | |
224 | ||
225 | static int xhci_update_stream_segment_mapping( | |
226 | struct radix_tree_root *trb_address_map, | |
227 | struct xhci_ring *ring, | |
228 | struct xhci_segment *first_seg, | |
229 | struct xhci_segment *last_seg, | |
230 | gfp_t mem_flags) | |
231 | { | |
232 | struct xhci_segment *seg; | |
233 | struct xhci_segment *failed_seg; | |
234 | int ret; | |
235 | ||
236 | if (WARN_ON_ONCE(trb_address_map == NULL)) | |
237 | return 0; | |
238 | ||
239 | seg = first_seg; | |
240 | do { | |
241 | ret = xhci_insert_segment_mapping(trb_address_map, | |
242 | ring, seg, mem_flags); | |
15341303 | 243 | if (ret) |
d5734223 SS |
244 | goto remove_streams; |
245 | if (seg == last_seg) | |
246 | return 0; | |
15341303 | 247 | seg = seg->next; |
d5734223 | 248 | } while (seg != first_seg); |
15341303 GH |
249 | |
250 | return 0; | |
d5734223 SS |
251 | |
252 | remove_streams: | |
253 | failed_seg = seg; | |
254 | seg = first_seg; | |
255 | do { | |
256 | xhci_remove_segment_mapping(trb_address_map, seg); | |
257 | if (seg == failed_seg) | |
258 | return ret; | |
259 | seg = seg->next; | |
260 | } while (seg != first_seg); | |
261 | ||
262 | return ret; | |
15341303 GH |
263 | } |
264 | ||
265 | static void xhci_remove_stream_mapping(struct xhci_ring *ring) | |
266 | { | |
267 | struct xhci_segment *seg; | |
15341303 GH |
268 | |
269 | if (WARN_ON_ONCE(ring->trb_address_map == NULL)) | |
270 | return; | |
271 | ||
272 | seg = ring->first_seg; | |
273 | do { | |
d5734223 | 274 | xhci_remove_segment_mapping(ring->trb_address_map, seg); |
15341303 GH |
275 | seg = seg->next; |
276 | } while (seg != ring->first_seg); | |
277 | } | |
278 | ||
d5734223 SS |
279 | static int xhci_update_stream_mapping(struct xhci_ring *ring, gfp_t mem_flags) |
280 | { | |
281 | return xhci_update_stream_segment_mapping(ring->trb_address_map, ring, | |
282 | ring->first_seg, ring->last_seg, mem_flags); | |
283 | } | |
284 | ||
0ebbab37 | 285 | /* XXX: Do we need the hcd structure in all these functions? */ |
f94e0186 | 286 | void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring) |
0ebbab37 | 287 | { |
0e6c7f74 | 288 | if (!ring) |
0ebbab37 | 289 | return; |
70d43601 | 290 | |
15341303 GH |
291 | if (ring->first_seg) { |
292 | if (ring->type == TYPE_STREAM) | |
293 | xhci_remove_stream_mapping(ring); | |
70d43601 | 294 | xhci_free_segments_for_ring(xhci, ring->first_seg); |
15341303 | 295 | } |
70d43601 | 296 | |
0ebbab37 SS |
297 | kfree(ring); |
298 | } | |
299 | ||
186a7ef1 AX |
300 | static void xhci_initialize_ring_info(struct xhci_ring *ring, |
301 | unsigned int cycle_state) | |
74f9fe21 SS |
302 | { |
303 | /* The ring is empty, so the enqueue pointer == dequeue pointer */ | |
304 | ring->enqueue = ring->first_seg->trbs; | |
305 | ring->enq_seg = ring->first_seg; | |
306 | ring->dequeue = ring->enqueue; | |
307 | ring->deq_seg = ring->first_seg; | |
308 | /* The ring is initialized to 0. The producer must write 1 to the cycle | |
309 | * bit to handover ownership of the TRB, so PCS = 1. The consumer must | |
310 | * compare CCS to the cycle bit to check ownership, so CCS = 1. | |
186a7ef1 AX |
311 | * |
312 | * New rings are initialized with cycle state equal to 1; if we are | |
313 | * handling ring expansion, set the cycle state equal to the old ring. | |
74f9fe21 | 314 | */ |
186a7ef1 | 315 | ring->cycle_state = cycle_state; |
74f9fe21 SS |
316 | /* Not necessary for new rings, but needed for re-initialized rings */ |
317 | ring->enq_updates = 0; | |
318 | ring->deq_updates = 0; | |
b008df60 AX |
319 | |
320 | /* | |
321 | * Each segment has a link TRB, and leave an extra TRB for SW | |
322 | * accounting purpose | |
323 | */ | |
324 | ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1; | |
74f9fe21 SS |
325 | } |
326 | ||
70d43601 AX |
327 | /* Allocate segments and link them for a ring */ |
328 | static int xhci_alloc_segments_for_ring(struct xhci_hcd *xhci, | |
329 | struct xhci_segment **first, struct xhci_segment **last, | |
186a7ef1 | 330 | unsigned int num_segs, unsigned int cycle_state, |
f9c589e1 | 331 | enum xhci_ring_type type, unsigned int max_packet, gfp_t flags) |
70d43601 AX |
332 | { |
333 | struct xhci_segment *prev; | |
334 | ||
f9c589e1 | 335 | prev = xhci_segment_alloc(xhci, cycle_state, max_packet, flags); |
70d43601 AX |
336 | if (!prev) |
337 | return -ENOMEM; | |
338 | num_segs--; | |
339 | ||
340 | *first = prev; | |
341 | while (num_segs > 0) { | |
342 | struct xhci_segment *next; | |
343 | ||
f9c589e1 | 344 | next = xhci_segment_alloc(xhci, cycle_state, max_packet, flags); |
70d43601 | 345 | if (!next) { |
68e5254a JW |
346 | prev = *first; |
347 | while (prev) { | |
348 | next = prev->next; | |
349 | xhci_segment_free(xhci, prev); | |
350 | prev = next; | |
351 | } | |
70d43601 AX |
352 | return -ENOMEM; |
353 | } | |
354 | xhci_link_segments(xhci, prev, next, type); | |
355 | ||
356 | prev = next; | |
357 | num_segs--; | |
358 | } | |
359 | xhci_link_segments(xhci, prev, *first, type); | |
360 | *last = prev; | |
361 | ||
362 | return 0; | |
363 | } | |
364 | ||
0ebbab37 SS |
365 | /** |
366 | * Create a new ring with zero or more segments. | |
367 | * | |
368 | * Link each segment together into a ring. | |
369 | * Set the end flag and the cycle toggle bit on the last segment. | |
370 | * See section 4.9.1 and figures 15 and 16. | |
371 | */ | |
372 | static struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci, | |
186a7ef1 | 373 | unsigned int num_segs, unsigned int cycle_state, |
f9c589e1 | 374 | enum xhci_ring_type type, unsigned int max_packet, gfp_t flags) |
0ebbab37 SS |
375 | { |
376 | struct xhci_ring *ring; | |
70d43601 | 377 | int ret; |
0ebbab37 SS |
378 | |
379 | ring = kzalloc(sizeof *(ring), flags); | |
0ebbab37 | 380 | if (!ring) |
326b4810 | 381 | return NULL; |
0ebbab37 | 382 | |
3fe4fe08 | 383 | ring->num_segs = num_segs; |
f9c589e1 | 384 | ring->bounce_buf_len = max_packet; |
d0e96f5a | 385 | INIT_LIST_HEAD(&ring->td_list); |
3b72fca0 | 386 | ring->type = type; |
0ebbab37 SS |
387 | if (num_segs == 0) |
388 | return ring; | |
389 | ||
70d43601 | 390 | ret = xhci_alloc_segments_for_ring(xhci, &ring->first_seg, |
f9c589e1 MN |
391 | &ring->last_seg, num_segs, cycle_state, type, |
392 | max_packet, flags); | |
70d43601 | 393 | if (ret) |
0ebbab37 | 394 | goto fail; |
0ebbab37 | 395 | |
3b72fca0 AX |
396 | /* Only event ring does not use link TRB */ |
397 | if (type != TYPE_EVENT) { | |
0ebbab37 | 398 | /* See section 4.9.2.1 and 6.4.4.1 */ |
70d43601 | 399 | ring->last_seg->trbs[TRBS_PER_SEGMENT - 1].link.control |= |
f5960b69 | 400 | cpu_to_le32(LINK_TOGGLE); |
0ebbab37 | 401 | } |
186a7ef1 | 402 | xhci_initialize_ring_info(ring, cycle_state); |
0ebbab37 SS |
403 | return ring; |
404 | ||
405 | fail: | |
68e5254a | 406 | kfree(ring); |
326b4810 | 407 | return NULL; |
0ebbab37 SS |
408 | } |
409 | ||
412566bd SS |
410 | void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci, |
411 | struct xhci_virt_device *virt_dev, | |
412 | unsigned int ep_index) | |
413 | { | |
414 | int rings_cached; | |
415 | ||
416 | rings_cached = virt_dev->num_rings_cached; | |
417 | if (rings_cached < XHCI_MAX_RINGS_CACHED) { | |
412566bd SS |
418 | virt_dev->ring_cache[rings_cached] = |
419 | virt_dev->eps[ep_index].ring; | |
30f89ca0 | 420 | virt_dev->num_rings_cached++; |
412566bd SS |
421 | xhci_dbg(xhci, "Cached old ring, " |
422 | "%d ring%s cached\n", | |
30f89ca0 SS |
423 | virt_dev->num_rings_cached, |
424 | (virt_dev->num_rings_cached > 1) ? "s" : ""); | |
412566bd SS |
425 | } else { |
426 | xhci_ring_free(xhci, virt_dev->eps[ep_index].ring); | |
427 | xhci_dbg(xhci, "Ring cache full (%d rings), " | |
428 | "freeing ring\n", | |
429 | virt_dev->num_rings_cached); | |
430 | } | |
431 | virt_dev->eps[ep_index].ring = NULL; | |
432 | } | |
433 | ||
74f9fe21 SS |
434 | /* Zero an endpoint ring (except for link TRBs) and move the enqueue and dequeue |
435 | * pointers to the beginning of the ring. | |
436 | */ | |
437 | static void xhci_reinit_cached_ring(struct xhci_hcd *xhci, | |
186a7ef1 AX |
438 | struct xhci_ring *ring, unsigned int cycle_state, |
439 | enum xhci_ring_type type) | |
74f9fe21 SS |
440 | { |
441 | struct xhci_segment *seg = ring->first_seg; | |
186a7ef1 AX |
442 | int i; |
443 | ||
74f9fe21 SS |
444 | do { |
445 | memset(seg->trbs, 0, | |
446 | sizeof(union xhci_trb)*TRBS_PER_SEGMENT); | |
186a7ef1 AX |
447 | if (cycle_state == 0) { |
448 | for (i = 0; i < TRBS_PER_SEGMENT; i++) | |
58719487 XR |
449 | seg->trbs[i].link.control |= |
450 | cpu_to_le32(TRB_CYCLE); | |
186a7ef1 | 451 | } |
74f9fe21 | 452 | /* All endpoint rings have link TRBs */ |
3b72fca0 | 453 | xhci_link_segments(xhci, seg, seg->next, type); |
74f9fe21 SS |
454 | seg = seg->next; |
455 | } while (seg != ring->first_seg); | |
3b72fca0 | 456 | ring->type = type; |
186a7ef1 | 457 | xhci_initialize_ring_info(ring, cycle_state); |
74f9fe21 SS |
458 | /* td list should be empty since all URBs have been cancelled, |
459 | * but just in case... | |
460 | */ | |
461 | INIT_LIST_HEAD(&ring->td_list); | |
462 | } | |
463 | ||
8dfec614 AX |
464 | /* |
465 | * Expand an existing ring. | |
466 | * Look for a cached ring or allocate a new ring which has same segment numbers | |
467 | * and link the two rings. | |
468 | */ | |
469 | int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring, | |
470 | unsigned int num_trbs, gfp_t flags) | |
471 | { | |
472 | struct xhci_segment *first; | |
473 | struct xhci_segment *last; | |
474 | unsigned int num_segs; | |
475 | unsigned int num_segs_needed; | |
476 | int ret; | |
477 | ||
478 | num_segs_needed = (num_trbs + (TRBS_PER_SEGMENT - 1) - 1) / | |
479 | (TRBS_PER_SEGMENT - 1); | |
480 | ||
481 | /* Allocate number of segments we needed, or double the ring size */ | |
482 | num_segs = ring->num_segs > num_segs_needed ? | |
483 | ring->num_segs : num_segs_needed; | |
484 | ||
485 | ret = xhci_alloc_segments_for_ring(xhci, &first, &last, | |
f9c589e1 MN |
486 | num_segs, ring->cycle_state, ring->type, |
487 | ring->bounce_buf_len, flags); | |
8dfec614 AX |
488 | if (ret) |
489 | return -ENOMEM; | |
490 | ||
d5734223 SS |
491 | if (ring->type == TYPE_STREAM) |
492 | ret = xhci_update_stream_segment_mapping(ring->trb_address_map, | |
493 | ring, first, last, flags); | |
494 | if (ret) { | |
495 | struct xhci_segment *next; | |
496 | do { | |
497 | next = first->next; | |
498 | xhci_segment_free(xhci, first); | |
499 | if (first == last) | |
500 | break; | |
501 | first = next; | |
502 | } while (true); | |
503 | return ret; | |
504 | } | |
505 | ||
8dfec614 | 506 | xhci_link_rings(xhci, ring, first, last, num_segs); |
68ffb011 XR |
507 | xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion, |
508 | "ring expansion succeed, now has %d segments", | |
8dfec614 AX |
509 | ring->num_segs); |
510 | ||
511 | return 0; | |
512 | } | |
513 | ||
d115b048 JY |
514 | #define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32) |
515 | ||
326b4810 | 516 | static struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci, |
d115b048 JY |
517 | int type, gfp_t flags) |
518 | { | |
29f9d54b SS |
519 | struct xhci_container_ctx *ctx; |
520 | ||
521 | if ((type != XHCI_CTX_TYPE_DEVICE) && (type != XHCI_CTX_TYPE_INPUT)) | |
522 | return NULL; | |
523 | ||
524 | ctx = kzalloc(sizeof(*ctx), flags); | |
d115b048 JY |
525 | if (!ctx) |
526 | return NULL; | |
527 | ||
d115b048 JY |
528 | ctx->type = type; |
529 | ctx->size = HCC_64BYTE_CONTEXT(xhci->hcc_params) ? 2048 : 1024; | |
530 | if (type == XHCI_CTX_TYPE_INPUT) | |
531 | ctx->size += CTX_SIZE(xhci->hcc_params); | |
532 | ||
84c1eeb0 | 533 | ctx->bytes = dma_pool_zalloc(xhci->device_pool, flags, &ctx->dma); |
025f880c MN |
534 | if (!ctx->bytes) { |
535 | kfree(ctx); | |
536 | return NULL; | |
537 | } | |
d115b048 JY |
538 | return ctx; |
539 | } | |
540 | ||
326b4810 | 541 | static void xhci_free_container_ctx(struct xhci_hcd *xhci, |
d115b048 JY |
542 | struct xhci_container_ctx *ctx) |
543 | { | |
a1d78c16 SS |
544 | if (!ctx) |
545 | return; | |
d115b048 JY |
546 | dma_pool_free(xhci->device_pool, ctx->bytes, ctx->dma); |
547 | kfree(ctx); | |
548 | } | |
549 | ||
4daf9df5 | 550 | struct xhci_input_control_ctx *xhci_get_input_control_ctx( |
d115b048 JY |
551 | struct xhci_container_ctx *ctx) |
552 | { | |
92f8e767 SS |
553 | if (ctx->type != XHCI_CTX_TYPE_INPUT) |
554 | return NULL; | |
555 | ||
d115b048 JY |
556 | return (struct xhci_input_control_ctx *)ctx->bytes; |
557 | } | |
558 | ||
559 | struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, | |
560 | struct xhci_container_ctx *ctx) | |
561 | { | |
562 | if (ctx->type == XHCI_CTX_TYPE_DEVICE) | |
563 | return (struct xhci_slot_ctx *)ctx->bytes; | |
564 | ||
565 | return (struct xhci_slot_ctx *) | |
566 | (ctx->bytes + CTX_SIZE(xhci->hcc_params)); | |
567 | } | |
568 | ||
569 | struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, | |
570 | struct xhci_container_ctx *ctx, | |
571 | unsigned int ep_index) | |
572 | { | |
573 | /* increment ep index by offset of start of ep ctx array */ | |
574 | ep_index++; | |
575 | if (ctx->type == XHCI_CTX_TYPE_INPUT) | |
576 | ep_index++; | |
577 | ||
578 | return (struct xhci_ep_ctx *) | |
579 | (ctx->bytes + (ep_index * CTX_SIZE(xhci->hcc_params))); | |
580 | } | |
581 | ||
8df75f42 SS |
582 | |
583 | /***************** Streams structures manipulation *************************/ | |
584 | ||
8212a49d | 585 | static void xhci_free_stream_ctx(struct xhci_hcd *xhci, |
8df75f42 SS |
586 | unsigned int num_stream_ctxs, |
587 | struct xhci_stream_ctx *stream_ctx, dma_addr_t dma) | |
588 | { | |
2a100047 | 589 | struct device *dev = xhci_to_hcd(xhci)->self.controller; |
ee4aa54b | 590 | size_t size = sizeof(struct xhci_stream_ctx) * num_stream_ctxs; |
8df75f42 | 591 | |
ee4aa54b HG |
592 | if (size > MEDIUM_STREAM_ARRAY_SIZE) |
593 | dma_free_coherent(dev, size, | |
8df75f42 | 594 | stream_ctx, dma); |
ee4aa54b | 595 | else if (size <= SMALL_STREAM_ARRAY_SIZE) |
8df75f42 SS |
596 | return dma_pool_free(xhci->small_streams_pool, |
597 | stream_ctx, dma); | |
598 | else | |
599 | return dma_pool_free(xhci->medium_streams_pool, | |
600 | stream_ctx, dma); | |
601 | } | |
602 | ||
603 | /* | |
604 | * The stream context array for each endpoint with bulk streams enabled can | |
605 | * vary in size, based on: | |
606 | * - how many streams the endpoint supports, | |
607 | * - the maximum primary stream array size the host controller supports, | |
608 | * - and how many streams the device driver asks for. | |
609 | * | |
610 | * The stream context array must be a power of 2, and can be as small as | |
611 | * 64 bytes or as large as 1MB. | |
612 | */ | |
8212a49d | 613 | static struct xhci_stream_ctx *xhci_alloc_stream_ctx(struct xhci_hcd *xhci, |
8df75f42 SS |
614 | unsigned int num_stream_ctxs, dma_addr_t *dma, |
615 | gfp_t mem_flags) | |
616 | { | |
2a100047 | 617 | struct device *dev = xhci_to_hcd(xhci)->self.controller; |
ee4aa54b | 618 | size_t size = sizeof(struct xhci_stream_ctx) * num_stream_ctxs; |
8df75f42 | 619 | |
ee4aa54b HG |
620 | if (size > MEDIUM_STREAM_ARRAY_SIZE) |
621 | return dma_alloc_coherent(dev, size, | |
22d45f01 | 622 | dma, mem_flags); |
ee4aa54b | 623 | else if (size <= SMALL_STREAM_ARRAY_SIZE) |
8df75f42 SS |
624 | return dma_pool_alloc(xhci->small_streams_pool, |
625 | mem_flags, dma); | |
626 | else | |
627 | return dma_pool_alloc(xhci->medium_streams_pool, | |
628 | mem_flags, dma); | |
629 | } | |
630 | ||
e9df17eb SS |
631 | struct xhci_ring *xhci_dma_to_transfer_ring( |
632 | struct xhci_virt_ep *ep, | |
633 | u64 address) | |
634 | { | |
635 | if (ep->ep_state & EP_HAS_STREAMS) | |
636 | return radix_tree_lookup(&ep->stream_info->trb_address_map, | |
eb8ccd2b | 637 | address >> TRB_SEGMENT_SHIFT); |
e9df17eb SS |
638 | return ep->ring; |
639 | } | |
640 | ||
e9df17eb SS |
641 | struct xhci_ring *xhci_stream_id_to_ring( |
642 | struct xhci_virt_device *dev, | |
643 | unsigned int ep_index, | |
644 | unsigned int stream_id) | |
645 | { | |
646 | struct xhci_virt_ep *ep = &dev->eps[ep_index]; | |
647 | ||
648 | if (stream_id == 0) | |
649 | return ep->ring; | |
650 | if (!ep->stream_info) | |
651 | return NULL; | |
652 | ||
653 | if (stream_id > ep->stream_info->num_streams) | |
654 | return NULL; | |
655 | return ep->stream_info->stream_rings[stream_id]; | |
656 | } | |
657 | ||
8df75f42 SS |
658 | /* |
659 | * Change an endpoint's internal structure so it supports stream IDs. The | |
660 | * number of requested streams includes stream 0, which cannot be used by device | |
661 | * drivers. | |
662 | * | |
663 | * The number of stream contexts in the stream context array may be bigger than | |
664 | * the number of streams the driver wants to use. This is because the number of | |
665 | * stream context array entries must be a power of two. | |
8df75f42 SS |
666 | */ |
667 | struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci, | |
668 | unsigned int num_stream_ctxs, | |
f9c589e1 MN |
669 | unsigned int num_streams, |
670 | unsigned int max_packet, gfp_t mem_flags) | |
8df75f42 SS |
671 | { |
672 | struct xhci_stream_info *stream_info; | |
673 | u32 cur_stream; | |
674 | struct xhci_ring *cur_ring; | |
8df75f42 SS |
675 | u64 addr; |
676 | int ret; | |
677 | ||
678 | xhci_dbg(xhci, "Allocating %u streams and %u " | |
679 | "stream context array entries.\n", | |
680 | num_streams, num_stream_ctxs); | |
681 | if (xhci->cmd_ring_reserved_trbs == MAX_RSVD_CMD_TRBS) { | |
682 | xhci_dbg(xhci, "Command ring has no reserved TRBs available\n"); | |
683 | return NULL; | |
684 | } | |
685 | xhci->cmd_ring_reserved_trbs++; | |
686 | ||
687 | stream_info = kzalloc(sizeof(struct xhci_stream_info), mem_flags); | |
688 | if (!stream_info) | |
689 | goto cleanup_trbs; | |
690 | ||
691 | stream_info->num_streams = num_streams; | |
692 | stream_info->num_stream_ctxs = num_stream_ctxs; | |
693 | ||
694 | /* Initialize the array of virtual pointers to stream rings. */ | |
695 | stream_info->stream_rings = kzalloc( | |
696 | sizeof(struct xhci_ring *)*num_streams, | |
697 | mem_flags); | |
698 | if (!stream_info->stream_rings) | |
699 | goto cleanup_info; | |
700 | ||
701 | /* Initialize the array of DMA addresses for stream rings for the HW. */ | |
702 | stream_info->stream_ctx_array = xhci_alloc_stream_ctx(xhci, | |
703 | num_stream_ctxs, &stream_info->ctx_array_dma, | |
704 | mem_flags); | |
705 | if (!stream_info->stream_ctx_array) | |
706 | goto cleanup_ctx; | |
707 | memset(stream_info->stream_ctx_array, 0, | |
708 | sizeof(struct xhci_stream_ctx)*num_stream_ctxs); | |
709 | ||
710 | /* Allocate everything needed to free the stream rings later */ | |
711 | stream_info->free_streams_command = | |
712 | xhci_alloc_command(xhci, true, true, mem_flags); | |
713 | if (!stream_info->free_streams_command) | |
714 | goto cleanup_ctx; | |
715 | ||
716 | INIT_RADIX_TREE(&stream_info->trb_address_map, GFP_ATOMIC); | |
717 | ||
718 | /* Allocate rings for all the streams that the driver will use, | |
719 | * and add their segment DMA addresses to the radix tree. | |
720 | * Stream 0 is reserved. | |
721 | */ | |
f9c589e1 | 722 | |
8df75f42 SS |
723 | for (cur_stream = 1; cur_stream < num_streams; cur_stream++) { |
724 | stream_info->stream_rings[cur_stream] = | |
f9c589e1 MN |
725 | xhci_ring_alloc(xhci, 2, 1, TYPE_STREAM, max_packet, |
726 | mem_flags); | |
8df75f42 SS |
727 | cur_ring = stream_info->stream_rings[cur_stream]; |
728 | if (!cur_ring) | |
729 | goto cleanup_rings; | |
e9df17eb | 730 | cur_ring->stream_id = cur_stream; |
15341303 | 731 | cur_ring->trb_address_map = &stream_info->trb_address_map; |
8df75f42 SS |
732 | /* Set deq ptr, cycle bit, and stream context type */ |
733 | addr = cur_ring->first_seg->dma | | |
734 | SCT_FOR_CTX(SCT_PRI_TR) | | |
735 | cur_ring->cycle_state; | |
f5960b69 ME |
736 | stream_info->stream_ctx_array[cur_stream].stream_ring = |
737 | cpu_to_le64(addr); | |
8df75f42 SS |
738 | xhci_dbg(xhci, "Setting stream %d ring ptr to 0x%08llx\n", |
739 | cur_stream, (unsigned long long) addr); | |
740 | ||
15341303 | 741 | ret = xhci_update_stream_mapping(cur_ring, mem_flags); |
8df75f42 SS |
742 | if (ret) { |
743 | xhci_ring_free(xhci, cur_ring); | |
744 | stream_info->stream_rings[cur_stream] = NULL; | |
745 | goto cleanup_rings; | |
746 | } | |
747 | } | |
748 | /* Leave the other unused stream ring pointers in the stream context | |
749 | * array initialized to zero. This will cause the xHC to give us an | |
750 | * error if the device asks for a stream ID we don't have setup (if it | |
751 | * was any other way, the host controller would assume the ring is | |
752 | * "empty" and wait forever for data to be queued to that stream ID). | |
753 | */ | |
8df75f42 SS |
754 | |
755 | return stream_info; | |
756 | ||
757 | cleanup_rings: | |
758 | for (cur_stream = 1; cur_stream < num_streams; cur_stream++) { | |
759 | cur_ring = stream_info->stream_rings[cur_stream]; | |
760 | if (cur_ring) { | |
8df75f42 SS |
761 | xhci_ring_free(xhci, cur_ring); |
762 | stream_info->stream_rings[cur_stream] = NULL; | |
763 | } | |
764 | } | |
765 | xhci_free_command(xhci, stream_info->free_streams_command); | |
766 | cleanup_ctx: | |
767 | kfree(stream_info->stream_rings); | |
768 | cleanup_info: | |
769 | kfree(stream_info); | |
770 | cleanup_trbs: | |
771 | xhci->cmd_ring_reserved_trbs--; | |
772 | return NULL; | |
773 | } | |
774 | /* | |
775 | * Sets the MaxPStreams field and the Linear Stream Array field. | |
776 | * Sets the dequeue pointer to the stream context array. | |
777 | */ | |
778 | void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci, | |
779 | struct xhci_ep_ctx *ep_ctx, | |
780 | struct xhci_stream_info *stream_info) | |
781 | { | |
782 | u32 max_primary_streams; | |
783 | /* MaxPStreams is the number of stream context array entries, not the | |
784 | * number we're actually using. Must be in 2^(MaxPstreams + 1) format. | |
785 | * fls(0) = 0, fls(0x1) = 1, fls(0x10) = 2, fls(0x100) = 3, etc. | |
786 | */ | |
787 | max_primary_streams = fls(stream_info->num_stream_ctxs) - 2; | |
3a7fa5be XR |
788 | xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, |
789 | "Setting number of stream ctx array entries to %u", | |
8df75f42 | 790 | 1 << (max_primary_streams + 1)); |
28ccd296 ME |
791 | ep_ctx->ep_info &= cpu_to_le32(~EP_MAXPSTREAMS_MASK); |
792 | ep_ctx->ep_info |= cpu_to_le32(EP_MAXPSTREAMS(max_primary_streams) | |
793 | | EP_HAS_LSA); | |
794 | ep_ctx->deq = cpu_to_le64(stream_info->ctx_array_dma); | |
8df75f42 SS |
795 | } |
796 | ||
797 | /* | |
798 | * Sets the MaxPStreams field and the Linear Stream Array field to 0. | |
799 | * Reinstalls the "normal" endpoint ring (at its previous dequeue mark, | |
800 | * not at the beginning of the ring). | |
801 | */ | |
4daf9df5 | 802 | void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx *ep_ctx, |
8df75f42 SS |
803 | struct xhci_virt_ep *ep) |
804 | { | |
805 | dma_addr_t addr; | |
28ccd296 | 806 | ep_ctx->ep_info &= cpu_to_le32(~(EP_MAXPSTREAMS_MASK | EP_HAS_LSA)); |
8df75f42 | 807 | addr = xhci_trb_virt_to_dma(ep->ring->deq_seg, ep->ring->dequeue); |
28ccd296 | 808 | ep_ctx->deq = cpu_to_le64(addr | ep->ring->cycle_state); |
8df75f42 SS |
809 | } |
810 | ||
811 | /* Frees all stream contexts associated with the endpoint, | |
812 | * | |
813 | * Caller should fix the endpoint context streams fields. | |
814 | */ | |
815 | void xhci_free_stream_info(struct xhci_hcd *xhci, | |
816 | struct xhci_stream_info *stream_info) | |
817 | { | |
818 | int cur_stream; | |
819 | struct xhci_ring *cur_ring; | |
8df75f42 SS |
820 | |
821 | if (!stream_info) | |
822 | return; | |
823 | ||
824 | for (cur_stream = 1; cur_stream < stream_info->num_streams; | |
825 | cur_stream++) { | |
826 | cur_ring = stream_info->stream_rings[cur_stream]; | |
827 | if (cur_ring) { | |
8df75f42 SS |
828 | xhci_ring_free(xhci, cur_ring); |
829 | stream_info->stream_rings[cur_stream] = NULL; | |
830 | } | |
831 | } | |
832 | xhci_free_command(xhci, stream_info->free_streams_command); | |
833 | xhci->cmd_ring_reserved_trbs--; | |
834 | if (stream_info->stream_ctx_array) | |
835 | xhci_free_stream_ctx(xhci, | |
836 | stream_info->num_stream_ctxs, | |
837 | stream_info->stream_ctx_array, | |
838 | stream_info->ctx_array_dma); | |
839 | ||
0d3703be | 840 | kfree(stream_info->stream_rings); |
8df75f42 SS |
841 | kfree(stream_info); |
842 | } | |
843 | ||
844 | ||
845 | /***************** Device context manipulation *************************/ | |
846 | ||
6f5165cf SS |
847 | static void xhci_init_endpoint_timer(struct xhci_hcd *xhci, |
848 | struct xhci_virt_ep *ep) | |
849 | { | |
9e08a03d JL |
850 | setup_timer(&ep->stop_cmd_timer, xhci_stop_endpoint_command_watchdog, |
851 | (unsigned long)ep); | |
6f5165cf SS |
852 | ep->xhci = xhci; |
853 | } | |
854 | ||
839c817c SS |
855 | static void xhci_free_tt_info(struct xhci_hcd *xhci, |
856 | struct xhci_virt_device *virt_dev, | |
857 | int slot_id) | |
858 | { | |
839c817c | 859 | struct list_head *tt_list_head; |
46ed8f00 TI |
860 | struct xhci_tt_bw_info *tt_info, *next; |
861 | bool slot_found = false; | |
839c817c SS |
862 | |
863 | /* If the device never made it past the Set Address stage, | |
864 | * it may not have the real_port set correctly. | |
865 | */ | |
866 | if (virt_dev->real_port == 0 || | |
867 | virt_dev->real_port > HCS_MAX_PORTS(xhci->hcs_params1)) { | |
868 | xhci_dbg(xhci, "Bad real port.\n"); | |
869 | return; | |
870 | } | |
871 | ||
872 | tt_list_head = &(xhci->rh_bw[virt_dev->real_port - 1].tts); | |
46ed8f00 TI |
873 | list_for_each_entry_safe(tt_info, next, tt_list_head, tt_list) { |
874 | /* Multi-TT hubs will have more than one entry */ | |
875 | if (tt_info->slot_id == slot_id) { | |
876 | slot_found = true; | |
877 | list_del(&tt_info->tt_list); | |
878 | kfree(tt_info); | |
879 | } else if (slot_found) { | |
839c817c | 880 | break; |
46ed8f00 | 881 | } |
839c817c | 882 | } |
839c817c SS |
883 | } |
884 | ||
885 | int xhci_alloc_tt_info(struct xhci_hcd *xhci, | |
886 | struct xhci_virt_device *virt_dev, | |
887 | struct usb_device *hdev, | |
888 | struct usb_tt *tt, gfp_t mem_flags) | |
889 | { | |
890 | struct xhci_tt_bw_info *tt_info; | |
891 | unsigned int num_ports; | |
892 | int i, j; | |
893 | ||
894 | if (!tt->multi) | |
895 | num_ports = 1; | |
896 | else | |
897 | num_ports = hdev->maxchild; | |
898 | ||
899 | for (i = 0; i < num_ports; i++, tt_info++) { | |
900 | struct xhci_interval_bw_table *bw_table; | |
901 | ||
902 | tt_info = kzalloc(sizeof(*tt_info), mem_flags); | |
903 | if (!tt_info) | |
904 | goto free_tts; | |
905 | INIT_LIST_HEAD(&tt_info->tt_list); | |
906 | list_add(&tt_info->tt_list, | |
907 | &xhci->rh_bw[virt_dev->real_port - 1].tts); | |
908 | tt_info->slot_id = virt_dev->udev->slot_id; | |
909 | if (tt->multi) | |
910 | tt_info->ttport = i+1; | |
911 | bw_table = &tt_info->bw_table; | |
912 | for (j = 0; j < XHCI_MAX_INTERVAL; j++) | |
913 | INIT_LIST_HEAD(&bw_table->interval_bw[j].endpoints); | |
914 | } | |
915 | return 0; | |
916 | ||
917 | free_tts: | |
918 | xhci_free_tt_info(xhci, virt_dev, virt_dev->udev->slot_id); | |
919 | return -ENOMEM; | |
920 | } | |
921 | ||
922 | ||
923 | /* All the xhci_tds in the ring's TD list should be freed at this point. | |
924 | * Should be called with xhci->lock held if there is any chance the TT lists | |
925 | * will be manipulated by the configure endpoint, allocate device, or update | |
926 | * hub functions while this function is removing the TT entries from the list. | |
927 | */ | |
3ffbba95 SS |
928 | void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id) |
929 | { | |
930 | struct xhci_virt_device *dev; | |
931 | int i; | |
2e27980e | 932 | int old_active_eps = 0; |
3ffbba95 SS |
933 | |
934 | /* Slot ID 0 is reserved */ | |
935 | if (slot_id == 0 || !xhci->devs[slot_id]) | |
936 | return; | |
937 | ||
938 | dev = xhci->devs[slot_id]; | |
a711edee FB |
939 | |
940 | trace_xhci_free_virt_device(dev); | |
941 | ||
8e595a5d | 942 | xhci->dcbaa->dev_context_ptrs[slot_id] = 0; |
3ffbba95 SS |
943 | if (!dev) |
944 | return; | |
945 | ||
2e27980e SS |
946 | if (dev->tt_info) |
947 | old_active_eps = dev->tt_info->active_eps; | |
948 | ||
98871e94 | 949 | for (i = 0; i < 31; i++) { |
63a0d9ab SS |
950 | if (dev->eps[i].ring) |
951 | xhci_ring_free(xhci, dev->eps[i].ring); | |
8df75f42 SS |
952 | if (dev->eps[i].stream_info) |
953 | xhci_free_stream_info(xhci, | |
954 | dev->eps[i].stream_info); | |
2e27980e SS |
955 | /* Endpoints on the TT/root port lists should have been removed |
956 | * when usb_disable_device() was called for the device. | |
957 | * We can't drop them anyway, because the udev might have gone | |
958 | * away by this point, and we can't tell what speed it was. | |
959 | */ | |
960 | if (!list_empty(&dev->eps[i].bw_endpoint_list)) | |
961 | xhci_warn(xhci, "Slot %u endpoint %u " | |
962 | "not removed from BW list!\n", | |
963 | slot_id, i); | |
8df75f42 | 964 | } |
839c817c SS |
965 | /* If this is a hub, free the TT(s) from the TT list */ |
966 | xhci_free_tt_info(xhci, dev, slot_id); | |
2e27980e SS |
967 | /* If necessary, update the number of active TTs on this root port */ |
968 | xhci_update_tt_active_eps(xhci, dev, old_active_eps); | |
3ffbba95 | 969 | |
74f9fe21 SS |
970 | if (dev->ring_cache) { |
971 | for (i = 0; i < dev->num_rings_cached; i++) | |
972 | xhci_ring_free(xhci, dev->ring_cache[i]); | |
973 | kfree(dev->ring_cache); | |
974 | } | |
975 | ||
3ffbba95 | 976 | if (dev->in_ctx) |
d115b048 | 977 | xhci_free_container_ctx(xhci, dev->in_ctx); |
3ffbba95 | 978 | if (dev->out_ctx) |
d115b048 JY |
979 | xhci_free_container_ctx(xhci, dev->out_ctx); |
980 | ||
3ffbba95 | 981 | kfree(xhci->devs[slot_id]); |
326b4810 | 982 | xhci->devs[slot_id] = NULL; |
3ffbba95 SS |
983 | } |
984 | ||
ee8665e2 MN |
985 | /* |
986 | * Free a virt_device structure. | |
987 | * If the virt_device added a tt_info (a hub) and has children pointing to | |
988 | * that tt_info, then free the child first. Recursive. | |
989 | * We can't rely on udev at this point to find child-parent relationships. | |
990 | */ | |
991 | void xhci_free_virt_devices_depth_first(struct xhci_hcd *xhci, int slot_id) | |
992 | { | |
993 | struct xhci_virt_device *vdev; | |
994 | struct list_head *tt_list_head; | |
995 | struct xhci_tt_bw_info *tt_info, *next; | |
996 | int i; | |
997 | ||
998 | vdev = xhci->devs[slot_id]; | |
999 | if (!vdev) | |
1000 | return; | |
1001 | ||
1002 | tt_list_head = &(xhci->rh_bw[vdev->real_port - 1].tts); | |
1003 | list_for_each_entry_safe(tt_info, next, tt_list_head, tt_list) { | |
1004 | /* is this a hub device that added a tt_info to the tts list */ | |
1005 | if (tt_info->slot_id == slot_id) { | |
1006 | /* are any devices using this tt_info? */ | |
1007 | for (i = 1; i < HCS_MAX_SLOTS(xhci->hcs_params1); i++) { | |
1008 | vdev = xhci->devs[i]; | |
1009 | if (vdev && (vdev->tt_info == tt_info)) | |
1010 | xhci_free_virt_devices_depth_first( | |
1011 | xhci, i); | |
1012 | } | |
1013 | } | |
1014 | } | |
1015 | /* we are now at a leaf device */ | |
1016 | xhci_free_virt_device(xhci, slot_id); | |
1017 | } | |
1018 | ||
3ffbba95 SS |
1019 | int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, |
1020 | struct usb_device *udev, gfp_t flags) | |
1021 | { | |
3ffbba95 | 1022 | struct xhci_virt_device *dev; |
63a0d9ab | 1023 | int i; |
3ffbba95 SS |
1024 | |
1025 | /* Slot ID 0 is reserved */ | |
1026 | if (slot_id == 0 || xhci->devs[slot_id]) { | |
1027 | xhci_warn(xhci, "Bad Slot ID %d\n", slot_id); | |
1028 | return 0; | |
1029 | } | |
1030 | ||
1031 | xhci->devs[slot_id] = kzalloc(sizeof(*xhci->devs[slot_id]), flags); | |
1032 | if (!xhci->devs[slot_id]) | |
1033 | return 0; | |
1034 | dev = xhci->devs[slot_id]; | |
1035 | ||
d115b048 JY |
1036 | /* Allocate the (output) device context that will be used in the HC. */ |
1037 | dev->out_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_DEVICE, flags); | |
3ffbba95 SS |
1038 | if (!dev->out_ctx) |
1039 | goto fail; | |
d115b048 | 1040 | |
700e2052 | 1041 | xhci_dbg(xhci, "Slot %d output ctx = 0x%llx (dma)\n", slot_id, |
d115b048 | 1042 | (unsigned long long)dev->out_ctx->dma); |
3ffbba95 SS |
1043 | |
1044 | /* Allocate the (input) device context for address device command */ | |
d115b048 | 1045 | dev->in_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT, flags); |
3ffbba95 SS |
1046 | if (!dev->in_ctx) |
1047 | goto fail; | |
d115b048 | 1048 | |
700e2052 | 1049 | xhci_dbg(xhci, "Slot %d input ctx = 0x%llx (dma)\n", slot_id, |
d115b048 | 1050 | (unsigned long long)dev->in_ctx->dma); |
3ffbba95 | 1051 | |
6f5165cf SS |
1052 | /* Initialize the cancellation list and watchdog timers for each ep */ |
1053 | for (i = 0; i < 31; i++) { | |
1054 | xhci_init_endpoint_timer(xhci, &dev->eps[i]); | |
63a0d9ab | 1055 | INIT_LIST_HEAD(&dev->eps[i].cancelled_td_list); |
2e27980e | 1056 | INIT_LIST_HEAD(&dev->eps[i].bw_endpoint_list); |
6f5165cf | 1057 | } |
63a0d9ab | 1058 | |
3ffbba95 | 1059 | /* Allocate endpoint 0 ring */ |
f9c589e1 | 1060 | dev->eps[0].ring = xhci_ring_alloc(xhci, 2, 1, TYPE_CTRL, 0, flags); |
63a0d9ab | 1061 | if (!dev->eps[0].ring) |
3ffbba95 SS |
1062 | goto fail; |
1063 | ||
74f9fe21 SS |
1064 | /* Allocate pointers to the ring cache */ |
1065 | dev->ring_cache = kzalloc( | |
1066 | sizeof(struct xhci_ring *)*XHCI_MAX_RINGS_CACHED, | |
1067 | flags); | |
1068 | if (!dev->ring_cache) | |
1069 | goto fail; | |
1070 | dev->num_rings_cached = 0; | |
1071 | ||
64927730 | 1072 | dev->udev = udev; |
f94e0186 | 1073 | |
28c2d2ef | 1074 | /* Point to output device context in dcbaa. */ |
28ccd296 | 1075 | xhci->dcbaa->dev_context_ptrs[slot_id] = cpu_to_le64(dev->out_ctx->dma); |
700e2052 | 1076 | xhci_dbg(xhci, "Set slot id %d dcbaa entry %p to 0x%llx\n", |
28ccd296 ME |
1077 | slot_id, |
1078 | &xhci->dcbaa->dev_context_ptrs[slot_id], | |
f5960b69 | 1079 | le64_to_cpu(xhci->dcbaa->dev_context_ptrs[slot_id])); |
3ffbba95 | 1080 | |
a711edee FB |
1081 | trace_xhci_alloc_virt_device(dev); |
1082 | ||
3ffbba95 SS |
1083 | return 1; |
1084 | fail: | |
1085 | xhci_free_virt_device(xhci, slot_id); | |
1086 | return 0; | |
1087 | } | |
1088 | ||
2d1ee590 SS |
1089 | void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci, |
1090 | struct usb_device *udev) | |
1091 | { | |
1092 | struct xhci_virt_device *virt_dev; | |
1093 | struct xhci_ep_ctx *ep0_ctx; | |
1094 | struct xhci_ring *ep_ring; | |
1095 | ||
1096 | virt_dev = xhci->devs[udev->slot_id]; | |
1097 | ep0_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, 0); | |
1098 | ep_ring = virt_dev->eps[0].ring; | |
1099 | /* | |
1100 | * FIXME we don't keep track of the dequeue pointer very well after a | |
1101 | * Set TR dequeue pointer, so we're setting the dequeue pointer of the | |
1102 | * host to our enqueue pointer. This should only be called after a | |
1103 | * configured device has reset, so all control transfers should have | |
1104 | * been completed or cancelled before the reset. | |
1105 | */ | |
28ccd296 ME |
1106 | ep0_ctx->deq = cpu_to_le64(xhci_trb_virt_to_dma(ep_ring->enq_seg, |
1107 | ep_ring->enqueue) | |
1108 | | ep_ring->cycle_state); | |
2d1ee590 SS |
1109 | } |
1110 | ||
f6ff0ac8 SS |
1111 | /* |
1112 | * The xHCI roothub may have ports of differing speeds in any order in the port | |
1113 | * status registers. xhci->port_array provides an array of the port speed for | |
1114 | * each offset into the port status registers. | |
1115 | * | |
1116 | * The xHCI hardware wants to know the roothub port number that the USB device | |
1117 | * is attached to (or the roothub port its ancestor hub is attached to). All we | |
1118 | * know is the index of that port under either the USB 2.0 or the USB 3.0 | |
1119 | * roothub, but that doesn't give us the real index into the HW port status | |
3f5eb141 | 1120 | * registers. Call xhci_find_raw_port_number() to get real index. |
f6ff0ac8 SS |
1121 | */ |
1122 | static u32 xhci_find_real_port_number(struct xhci_hcd *xhci, | |
1123 | struct usb_device *udev) | |
1124 | { | |
1125 | struct usb_device *top_dev; | |
3f5eb141 LT |
1126 | struct usb_hcd *hcd; |
1127 | ||
0caf6b33 | 1128 | if (udev->speed >= USB_SPEED_SUPER) |
3f5eb141 LT |
1129 | hcd = xhci->shared_hcd; |
1130 | else | |
1131 | hcd = xhci->main_hcd; | |
f6ff0ac8 SS |
1132 | |
1133 | for (top_dev = udev; top_dev->parent && top_dev->parent->parent; | |
1134 | top_dev = top_dev->parent) | |
1135 | /* Found device below root hub */; | |
f6ff0ac8 | 1136 | |
3f5eb141 | 1137 | return xhci_find_raw_port_number(hcd, top_dev->portnum); |
f6ff0ac8 SS |
1138 | } |
1139 | ||
3ffbba95 SS |
1140 | /* Setup an xHCI virtual device for a Set Address command */ |
1141 | int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev) | |
1142 | { | |
1143 | struct xhci_virt_device *dev; | |
1144 | struct xhci_ep_ctx *ep0_ctx; | |
d115b048 | 1145 | struct xhci_slot_ctx *slot_ctx; |
f6ff0ac8 | 1146 | u32 port_num; |
bd18fd5c | 1147 | u32 max_packets; |
f6ff0ac8 | 1148 | struct usb_device *top_dev; |
3ffbba95 SS |
1149 | |
1150 | dev = xhci->devs[udev->slot_id]; | |
1151 | /* Slot ID 0 is reserved */ | |
1152 | if (udev->slot_id == 0 || !dev) { | |
1153 | xhci_warn(xhci, "Slot ID %d is not assigned to this device\n", | |
1154 | udev->slot_id); | |
1155 | return -EINVAL; | |
1156 | } | |
d115b048 | 1157 | ep0_ctx = xhci_get_ep_ctx(xhci, dev->in_ctx, 0); |
d115b048 | 1158 | slot_ctx = xhci_get_slot_ctx(xhci, dev->in_ctx); |
3ffbba95 | 1159 | |
3ffbba95 | 1160 | /* 3) Only the control endpoint is valid - one endpoint context */ |
f5960b69 | 1161 | slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1) | udev->route); |
3ffbba95 | 1162 | switch (udev->speed) { |
0caf6b33 | 1163 | case USB_SPEED_SUPER_PLUS: |
d7854041 MN |
1164 | slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_SSP); |
1165 | max_packets = MAX_PACKET(512); | |
1166 | break; | |
3ffbba95 | 1167 | case USB_SPEED_SUPER: |
f5960b69 | 1168 | slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_SS); |
bd18fd5c | 1169 | max_packets = MAX_PACKET(512); |
3ffbba95 SS |
1170 | break; |
1171 | case USB_SPEED_HIGH: | |
f5960b69 | 1172 | slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_HS); |
bd18fd5c | 1173 | max_packets = MAX_PACKET(64); |
3ffbba95 | 1174 | break; |
bd18fd5c | 1175 | /* USB core guesses at a 64-byte max packet first for FS devices */ |
3ffbba95 | 1176 | case USB_SPEED_FULL: |
f5960b69 | 1177 | slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_FS); |
bd18fd5c | 1178 | max_packets = MAX_PACKET(64); |
3ffbba95 SS |
1179 | break; |
1180 | case USB_SPEED_LOW: | |
f5960b69 | 1181 | slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_LS); |
bd18fd5c | 1182 | max_packets = MAX_PACKET(8); |
3ffbba95 | 1183 | break; |
551cdbbe | 1184 | case USB_SPEED_WIRELESS: |
3ffbba95 SS |
1185 | xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n"); |
1186 | return -EINVAL; | |
1187 | break; | |
1188 | default: | |
1189 | /* Speed was set earlier, this shouldn't happen. */ | |
bd18fd5c | 1190 | return -EINVAL; |
3ffbba95 SS |
1191 | } |
1192 | /* Find the root hub port this device is under */ | |
f6ff0ac8 SS |
1193 | port_num = xhci_find_real_port_number(xhci, udev); |
1194 | if (!port_num) | |
1195 | return -EINVAL; | |
f5960b69 | 1196 | slot_ctx->dev_info2 |= cpu_to_le32(ROOT_HUB_PORT(port_num)); |
f6ff0ac8 | 1197 | /* Set the port number in the virtual_device to the faked port number */ |
3ffbba95 SS |
1198 | for (top_dev = udev; top_dev->parent && top_dev->parent->parent; |
1199 | top_dev = top_dev->parent) | |
1200 | /* Found device below root hub */; | |
fe30182c | 1201 | dev->fake_port = top_dev->portnum; |
66381755 | 1202 | dev->real_port = port_num; |
f6ff0ac8 | 1203 | xhci_dbg(xhci, "Set root hub portnum to %d\n", port_num); |
fe30182c | 1204 | xhci_dbg(xhci, "Set fake root hub portnum to %d\n", dev->fake_port); |
3ffbba95 | 1205 | |
839c817c SS |
1206 | /* Find the right bandwidth table that this device will be a part of. |
1207 | * If this is a full speed device attached directly to a root port (or a | |
1208 | * decendent of one), it counts as a primary bandwidth domain, not a | |
1209 | * secondary bandwidth domain under a TT. An xhci_tt_info structure | |
1210 | * will never be created for the HS root hub. | |
1211 | */ | |
1212 | if (!udev->tt || !udev->tt->hub->parent) { | |
1213 | dev->bw_table = &xhci->rh_bw[port_num - 1].bw_table; | |
1214 | } else { | |
1215 | struct xhci_root_port_bw_info *rh_bw; | |
1216 | struct xhci_tt_bw_info *tt_bw; | |
1217 | ||
1218 | rh_bw = &xhci->rh_bw[port_num - 1]; | |
1219 | /* Find the right TT. */ | |
1220 | list_for_each_entry(tt_bw, &rh_bw->tts, tt_list) { | |
1221 | if (tt_bw->slot_id != udev->tt->hub->slot_id) | |
1222 | continue; | |
1223 | ||
1224 | if (!dev->udev->tt->multi || | |
1225 | (udev->tt->multi && | |
1226 | tt_bw->ttport == dev->udev->ttport)) { | |
1227 | dev->bw_table = &tt_bw->bw_table; | |
1228 | dev->tt_info = tt_bw; | |
1229 | break; | |
1230 | } | |
1231 | } | |
1232 | if (!dev->tt_info) | |
1233 | xhci_warn(xhci, "WARN: Didn't find a matching TT\n"); | |
1234 | } | |
1235 | ||
aa1b13ef SS |
1236 | /* Is this a LS/FS device under an external HS hub? */ |
1237 | if (udev->tt && udev->tt->hub->parent) { | |
28ccd296 ME |
1238 | slot_ctx->tt_info = cpu_to_le32(udev->tt->hub->slot_id | |
1239 | (udev->ttport << 8)); | |
07b6de10 | 1240 | if (udev->tt->multi) |
28ccd296 | 1241 | slot_ctx->dev_info |= cpu_to_le32(DEV_MTT); |
3ffbba95 | 1242 | } |
700e2052 | 1243 | xhci_dbg(xhci, "udev->tt = %p\n", udev->tt); |
3ffbba95 SS |
1244 | xhci_dbg(xhci, "udev->ttport = 0x%x\n", udev->ttport); |
1245 | ||
1246 | /* Step 4 - ring already allocated */ | |
1247 | /* Step 5 */ | |
28ccd296 | 1248 | ep0_ctx->ep_info2 = cpu_to_le32(EP_TYPE(CTRL_EP)); |
bd18fd5c | 1249 | |
3ffbba95 | 1250 | /* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */ |
bd18fd5c MN |
1251 | ep0_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(0) | ERROR_COUNT(3) | |
1252 | max_packets); | |
3ffbba95 | 1253 | |
28ccd296 ME |
1254 | ep0_ctx->deq = cpu_to_le64(dev->eps[0].ring->first_seg->dma | |
1255 | dev->eps[0].ring->cycle_state); | |
3ffbba95 | 1256 | |
a711edee FB |
1257 | trace_xhci_setup_addressable_virt_device(dev); |
1258 | ||
3ffbba95 SS |
1259 | /* Steps 7 and 8 were done in xhci_alloc_virt_device() */ |
1260 | ||
1261 | return 0; | |
1262 | } | |
1263 | ||
dfa49c4a DT |
1264 | /* |
1265 | * Convert interval expressed as 2^(bInterval - 1) == interval into | |
1266 | * straight exponent value 2^n == interval. | |
1267 | * | |
1268 | */ | |
1269 | static unsigned int xhci_parse_exponent_interval(struct usb_device *udev, | |
1270 | struct usb_host_endpoint *ep) | |
1271 | { | |
1272 | unsigned int interval; | |
1273 | ||
1274 | interval = clamp_val(ep->desc.bInterval, 1, 16) - 1; | |
1275 | if (interval != ep->desc.bInterval - 1) | |
1276 | dev_warn(&udev->dev, | |
cd3c18ba | 1277 | "ep %#x - rounding interval to %d %sframes\n", |
dfa49c4a | 1278 | ep->desc.bEndpointAddress, |
cd3c18ba DT |
1279 | 1 << interval, |
1280 | udev->speed == USB_SPEED_FULL ? "" : "micro"); | |
1281 | ||
1282 | if (udev->speed == USB_SPEED_FULL) { | |
1283 | /* | |
1284 | * Full speed isoc endpoints specify interval in frames, | |
1285 | * not microframes. We are using microframes everywhere, | |
1286 | * so adjust accordingly. | |
1287 | */ | |
1288 | interval += 3; /* 1 frame = 2^3 uframes */ | |
1289 | } | |
dfa49c4a DT |
1290 | |
1291 | return interval; | |
1292 | } | |
1293 | ||
1294 | /* | |
340a3504 | 1295 | * Convert bInterval expressed in microframes (in 1-255 range) to exponent of |
dfa49c4a DT |
1296 | * microframes, rounded down to nearest power of 2. |
1297 | */ | |
340a3504 SS |
1298 | static unsigned int xhci_microframes_to_exponent(struct usb_device *udev, |
1299 | struct usb_host_endpoint *ep, unsigned int desc_interval, | |
1300 | unsigned int min_exponent, unsigned int max_exponent) | |
dfa49c4a DT |
1301 | { |
1302 | unsigned int interval; | |
1303 | ||
340a3504 SS |
1304 | interval = fls(desc_interval) - 1; |
1305 | interval = clamp_val(interval, min_exponent, max_exponent); | |
1306 | if ((1 << interval) != desc_interval) | |
a5da9568 | 1307 | dev_dbg(&udev->dev, |
dfa49c4a DT |
1308 | "ep %#x - rounding interval to %d microframes, ep desc says %d microframes\n", |
1309 | ep->desc.bEndpointAddress, | |
1310 | 1 << interval, | |
340a3504 | 1311 | desc_interval); |
dfa49c4a DT |
1312 | |
1313 | return interval; | |
1314 | } | |
1315 | ||
340a3504 SS |
1316 | static unsigned int xhci_parse_microframe_interval(struct usb_device *udev, |
1317 | struct usb_host_endpoint *ep) | |
1318 | { | |
55c1945e SS |
1319 | if (ep->desc.bInterval == 0) |
1320 | return 0; | |
340a3504 SS |
1321 | return xhci_microframes_to_exponent(udev, ep, |
1322 | ep->desc.bInterval, 0, 15); | |
1323 | } | |
1324 | ||
1325 | ||
1326 | static unsigned int xhci_parse_frame_interval(struct usb_device *udev, | |
1327 | struct usb_host_endpoint *ep) | |
1328 | { | |
1329 | return xhci_microframes_to_exponent(udev, ep, | |
1330 | ep->desc.bInterval * 8, 3, 10); | |
1331 | } | |
1332 | ||
f94e0186 SS |
1333 | /* Return the polling or NAK interval. |
1334 | * | |
1335 | * The polling interval is expressed in "microframes". If xHCI's Interval field | |
1336 | * is set to N, it will service the endpoint every 2^(Interval)*125us. | |
1337 | * | |
1338 | * The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval | |
1339 | * is set to 0. | |
1340 | */ | |
575688e1 | 1341 | static unsigned int xhci_get_endpoint_interval(struct usb_device *udev, |
f94e0186 SS |
1342 | struct usb_host_endpoint *ep) |
1343 | { | |
1344 | unsigned int interval = 0; | |
1345 | ||
1346 | switch (udev->speed) { | |
1347 | case USB_SPEED_HIGH: | |
1348 | /* Max NAK rate */ | |
1349 | if (usb_endpoint_xfer_control(&ep->desc) || | |
dfa49c4a | 1350 | usb_endpoint_xfer_bulk(&ep->desc)) { |
340a3504 | 1351 | interval = xhci_parse_microframe_interval(udev, ep); |
dfa49c4a DT |
1352 | break; |
1353 | } | |
f94e0186 | 1354 | /* Fall through - SS and HS isoc/int have same decoding */ |
dfa49c4a | 1355 | |
0caf6b33 | 1356 | case USB_SPEED_SUPER_PLUS: |
f94e0186 SS |
1357 | case USB_SPEED_SUPER: |
1358 | if (usb_endpoint_xfer_int(&ep->desc) || | |
dfa49c4a DT |
1359 | usb_endpoint_xfer_isoc(&ep->desc)) { |
1360 | interval = xhci_parse_exponent_interval(udev, ep); | |
f94e0186 SS |
1361 | } |
1362 | break; | |
dfa49c4a | 1363 | |
f94e0186 | 1364 | case USB_SPEED_FULL: |
b513d447 | 1365 | if (usb_endpoint_xfer_isoc(&ep->desc)) { |
dfa49c4a DT |
1366 | interval = xhci_parse_exponent_interval(udev, ep); |
1367 | break; | |
1368 | } | |
1369 | /* | |
b513d447 | 1370 | * Fall through for interrupt endpoint interval decoding |
dfa49c4a DT |
1371 | * since it uses the same rules as low speed interrupt |
1372 | * endpoints. | |
1373 | */ | |
1374 | ||
f94e0186 SS |
1375 | case USB_SPEED_LOW: |
1376 | if (usb_endpoint_xfer_int(&ep->desc) || | |
dfa49c4a DT |
1377 | usb_endpoint_xfer_isoc(&ep->desc)) { |
1378 | ||
1379 | interval = xhci_parse_frame_interval(udev, ep); | |
f94e0186 SS |
1380 | } |
1381 | break; | |
dfa49c4a | 1382 | |
f94e0186 SS |
1383 | default: |
1384 | BUG(); | |
1385 | } | |
def4e6f7 | 1386 | return interval; |
f94e0186 SS |
1387 | } |
1388 | ||
c30c791c | 1389 | /* The "Mult" field in the endpoint context is only set for SuperSpeed isoc eps. |
1cf62246 SS |
1390 | * High speed endpoint descriptors can define "the number of additional |
1391 | * transaction opportunities per microframe", but that goes in the Max Burst | |
1392 | * endpoint context field. | |
1393 | */ | |
575688e1 | 1394 | static u32 xhci_get_endpoint_mult(struct usb_device *udev, |
1cf62246 SS |
1395 | struct usb_host_endpoint *ep) |
1396 | { | |
0caf6b33 | 1397 | if (udev->speed < USB_SPEED_SUPER || |
c30c791c | 1398 | !usb_endpoint_xfer_isoc(&ep->desc)) |
1cf62246 | 1399 | return 0; |
842f1690 | 1400 | return ep->ss_ep_comp.bmAttributes; |
1cf62246 SS |
1401 | } |
1402 | ||
def4e6f7 MN |
1403 | static u32 xhci_get_endpoint_max_burst(struct usb_device *udev, |
1404 | struct usb_host_endpoint *ep) | |
1405 | { | |
1406 | /* Super speed and Plus have max burst in ep companion desc */ | |
1407 | if (udev->speed >= USB_SPEED_SUPER) | |
1408 | return ep->ss_ep_comp.bMaxBurst; | |
1409 | ||
1410 | if (udev->speed == USB_SPEED_HIGH && | |
1411 | (usb_endpoint_xfer_isoc(&ep->desc) || | |
1412 | usb_endpoint_xfer_int(&ep->desc))) | |
dcf5228c | 1413 | return usb_endpoint_maxp_mult(&ep->desc) - 1; |
def4e6f7 MN |
1414 | |
1415 | return 0; | |
1416 | } | |
1417 | ||
4daf9df5 | 1418 | static u32 xhci_get_endpoint_type(struct usb_host_endpoint *ep) |
f94e0186 SS |
1419 | { |
1420 | int in; | |
f94e0186 SS |
1421 | |
1422 | in = usb_endpoint_dir_in(&ep->desc); | |
def4e6f7 | 1423 | |
c0e625c4 FB |
1424 | switch (usb_endpoint_type(&ep->desc)) { |
1425 | case USB_ENDPOINT_XFER_CONTROL: | |
def4e6f7 | 1426 | return CTRL_EP; |
c0e625c4 | 1427 | case USB_ENDPOINT_XFER_BULK: |
def4e6f7 | 1428 | return in ? BULK_IN_EP : BULK_OUT_EP; |
c0e625c4 | 1429 | case USB_ENDPOINT_XFER_ISOC: |
def4e6f7 | 1430 | return in ? ISOC_IN_EP : ISOC_OUT_EP; |
c0e625c4 | 1431 | case USB_ENDPOINT_XFER_INT: |
def4e6f7 | 1432 | return in ? INT_IN_EP : INT_OUT_EP; |
c0e625c4 | 1433 | } |
def4e6f7 | 1434 | return 0; |
f94e0186 SS |
1435 | } |
1436 | ||
9238f25d SS |
1437 | /* Return the maximum endpoint service interval time (ESIT) payload. |
1438 | * Basically, this is the maxpacket size, multiplied by the burst size | |
1439 | * and mult size. | |
1440 | */ | |
4daf9df5 | 1441 | static u32 xhci_get_max_esit_payload(struct usb_device *udev, |
9238f25d SS |
1442 | struct usb_host_endpoint *ep) |
1443 | { | |
1444 | int max_burst; | |
1445 | int max_packet; | |
1446 | ||
1447 | /* Only applies for interrupt or isochronous endpoints */ | |
1448 | if (usb_endpoint_xfer_control(&ep->desc) || | |
1449 | usb_endpoint_xfer_bulk(&ep->desc)) | |
1450 | return 0; | |
1451 | ||
8ef8a9f5 MN |
1452 | /* SuperSpeedPlus Isoc ep sending over 48k per esit */ |
1453 | if ((udev->speed >= USB_SPEED_SUPER_PLUS) && | |
1454 | USB_SS_SSP_ISOC_COMP(ep->ss_ep_comp.bmAttributes)) | |
1455 | return le32_to_cpu(ep->ssp_isoc_ep_comp.dwBytesPerInterval); | |
1456 | /* SuperSpeed or SuperSpeedPlus Isoc ep with less than 48k per esit */ | |
1457 | else if (udev->speed >= USB_SPEED_SUPER) | |
64b3c304 | 1458 | return le16_to_cpu(ep->ss_ep_comp.wBytesPerInterval); |
9238f25d | 1459 | |
734d3ddd | 1460 | max_packet = usb_endpoint_maxp(&ep->desc); |
dcf5228c | 1461 | max_burst = usb_endpoint_maxp_mult(&ep->desc); |
9238f25d | 1462 | /* A 0 in max burst means 1 transfer per ESIT */ |
dcf5228c | 1463 | return max_packet * max_burst; |
9238f25d SS |
1464 | } |
1465 | ||
8df75f42 SS |
1466 | /* Set up an endpoint with one ring segment. Do not allocate stream rings. |
1467 | * Drivers will have to call usb_alloc_streams() to do that. | |
1468 | */ | |
f94e0186 SS |
1469 | int xhci_endpoint_init(struct xhci_hcd *xhci, |
1470 | struct xhci_virt_device *virt_dev, | |
1471 | struct usb_device *udev, | |
f88ba78d SS |
1472 | struct usb_host_endpoint *ep, |
1473 | gfp_t mem_flags) | |
f94e0186 SS |
1474 | { |
1475 | unsigned int ep_index; | |
1476 | struct xhci_ep_ctx *ep_ctx; | |
1477 | struct xhci_ring *ep_ring; | |
1478 | unsigned int max_packet; | |
def4e6f7 | 1479 | enum xhci_ring_type ring_type; |
9238f25d | 1480 | u32 max_esit_payload; |
17d65554 | 1481 | u32 endpoint_type; |
def4e6f7 MN |
1482 | unsigned int max_burst; |
1483 | unsigned int interval; | |
1484 | unsigned int mult; | |
1485 | unsigned int avg_trb_len; | |
1486 | unsigned int err_count = 0; | |
f94e0186 SS |
1487 | |
1488 | ep_index = xhci_get_endpoint_index(&ep->desc); | |
d115b048 | 1489 | ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index); |
f94e0186 | 1490 | |
4daf9df5 | 1491 | endpoint_type = xhci_get_endpoint_type(ep); |
17d65554 MN |
1492 | if (!endpoint_type) |
1493 | return -EINVAL; | |
17d65554 | 1494 | |
def4e6f7 | 1495 | ring_type = usb_endpoint_type(&ep->desc); |
f94e0186 | 1496 | |
def4e6f7 MN |
1497 | /* |
1498 | * Get values to fill the endpoint context, mostly from ep descriptor. | |
1499 | * The average TRB buffer lengt for bulk endpoints is unclear as we | |
1500 | * have no clue on scatter gather list entry size. For Isoc and Int, | |
1501 | * set it to max available. See xHCI 1.1 spec 4.14.1.1 for details. | |
1502 | */ | |
1503 | max_esit_payload = xhci_get_max_esit_payload(udev, ep); | |
1504 | interval = xhci_get_endpoint_interval(udev, ep); | |
1505 | mult = xhci_get_endpoint_mult(udev, ep); | |
734d3ddd | 1506 | max_packet = usb_endpoint_maxp(&ep->desc); |
def4e6f7 MN |
1507 | max_burst = xhci_get_endpoint_max_burst(udev, ep); |
1508 | avg_trb_len = max_esit_payload; | |
f94e0186 SS |
1509 | |
1510 | /* FIXME dig Mult and streams info out of ep companion desc */ | |
1511 | ||
def4e6f7 | 1512 | /* Allow 3 retries for everything but isoc, set CErr = 3 */ |
f94e0186 | 1513 | if (!usb_endpoint_xfer_isoc(&ep->desc)) |
def4e6f7 MN |
1514 | err_count = 3; |
1515 | /* Some devices get this wrong */ | |
1516 | if (usb_endpoint_xfer_bulk(&ep->desc) && udev->speed == USB_SPEED_HIGH) | |
1517 | max_packet = 512; | |
1518 | /* xHCI 1.0 and 1.1 indicates that ctrl ep avg TRB Length should be 8 */ | |
dca77945 | 1519 | if (usb_endpoint_xfer_control(&ep->desc) && xhci->hci_version >= 0x100) |
def4e6f7 | 1520 | avg_trb_len = 8; |
8ef8a9f5 MN |
1521 | /* xhci 1.1 with LEC support doesn't use mult field, use RsvdZ */ |
1522 | if ((xhci->hci_version > 0x100) && HCC2_LEC(xhci->hcc_params2)) | |
1523 | mult = 0; | |
def4e6f7 | 1524 | |
f9c589e1 MN |
1525 | /* Set up the endpoint ring */ |
1526 | virt_dev->eps[ep_index].new_ring = | |
1527 | xhci_ring_alloc(xhci, 2, 1, ring_type, max_packet, mem_flags); | |
1528 | if (!virt_dev->eps[ep_index].new_ring) { | |
1529 | /* Attempt to use the ring cache */ | |
1530 | if (virt_dev->num_rings_cached == 0) | |
1531 | return -ENOMEM; | |
1532 | virt_dev->num_rings_cached--; | |
1533 | virt_dev->eps[ep_index].new_ring = | |
1534 | virt_dev->ring_cache[virt_dev->num_rings_cached]; | |
1535 | virt_dev->ring_cache[virt_dev->num_rings_cached] = NULL; | |
1536 | xhci_reinit_cached_ring(xhci, virt_dev->eps[ep_index].new_ring, | |
1537 | 1, ring_type); | |
1538 | } | |
1539 | virt_dev->eps[ep_index].skip = false; | |
1540 | ep_ring = virt_dev->eps[ep_index].new_ring; | |
1541 | ||
def4e6f7 | 1542 | /* Fill the endpoint context */ |
8ef8a9f5 MN |
1543 | ep_ctx->ep_info = cpu_to_le32(EP_MAX_ESIT_PAYLOAD_HI(max_esit_payload) | |
1544 | EP_INTERVAL(interval) | | |
def4e6f7 MN |
1545 | EP_MULT(mult)); |
1546 | ep_ctx->ep_info2 = cpu_to_le32(EP_TYPE(endpoint_type) | | |
1547 | MAX_PACKET(max_packet) | | |
1548 | MAX_BURST(max_burst) | | |
1549 | ERROR_COUNT(err_count)); | |
1550 | ep_ctx->deq = cpu_to_le64(ep_ring->first_seg->dma | | |
1551 | ep_ring->cycle_state); | |
1552 | ||
1553 | ep_ctx->tx_info = cpu_to_le32(EP_MAX_ESIT_PAYLOAD_LO(max_esit_payload) | | |
1554 | EP_AVG_TRB_LENGTH(avg_trb_len)); | |
9238f25d | 1555 | |
f94e0186 SS |
1556 | /* FIXME Debug endpoint context */ |
1557 | return 0; | |
1558 | } | |
1559 | ||
1560 | void xhci_endpoint_zero(struct xhci_hcd *xhci, | |
1561 | struct xhci_virt_device *virt_dev, | |
1562 | struct usb_host_endpoint *ep) | |
1563 | { | |
1564 | unsigned int ep_index; | |
1565 | struct xhci_ep_ctx *ep_ctx; | |
1566 | ||
1567 | ep_index = xhci_get_endpoint_index(&ep->desc); | |
d115b048 | 1568 | ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index); |
f94e0186 SS |
1569 | |
1570 | ep_ctx->ep_info = 0; | |
1571 | ep_ctx->ep_info2 = 0; | |
8e595a5d | 1572 | ep_ctx->deq = 0; |
f94e0186 SS |
1573 | ep_ctx->tx_info = 0; |
1574 | /* Don't free the endpoint ring until the set interface or configuration | |
1575 | * request succeeds. | |
1576 | */ | |
1577 | } | |
1578 | ||
9af5d71d SS |
1579 | void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info) |
1580 | { | |
1581 | bw_info->ep_interval = 0; | |
1582 | bw_info->mult = 0; | |
1583 | bw_info->num_packets = 0; | |
1584 | bw_info->max_packet_size = 0; | |
1585 | bw_info->type = 0; | |
1586 | bw_info->max_esit_payload = 0; | |
1587 | } | |
1588 | ||
1589 | void xhci_update_bw_info(struct xhci_hcd *xhci, | |
1590 | struct xhci_container_ctx *in_ctx, | |
1591 | struct xhci_input_control_ctx *ctrl_ctx, | |
1592 | struct xhci_virt_device *virt_dev) | |
1593 | { | |
1594 | struct xhci_bw_info *bw_info; | |
1595 | struct xhci_ep_ctx *ep_ctx; | |
1596 | unsigned int ep_type; | |
1597 | int i; | |
1598 | ||
98871e94 | 1599 | for (i = 1; i < 31; i++) { |
9af5d71d SS |
1600 | bw_info = &virt_dev->eps[i].bw_info; |
1601 | ||
1602 | /* We can't tell what endpoint type is being dropped, but | |
1603 | * unconditionally clearing the bandwidth info for non-periodic | |
1604 | * endpoints should be harmless because the info will never be | |
1605 | * set in the first place. | |
1606 | */ | |
1607 | if (!EP_IS_ADDED(ctrl_ctx, i) && EP_IS_DROPPED(ctrl_ctx, i)) { | |
1608 | /* Dropped endpoint */ | |
1609 | xhci_clear_endpoint_bw_info(bw_info); | |
1610 | continue; | |
1611 | } | |
1612 | ||
1613 | if (EP_IS_ADDED(ctrl_ctx, i)) { | |
1614 | ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, i); | |
1615 | ep_type = CTX_TO_EP_TYPE(le32_to_cpu(ep_ctx->ep_info2)); | |
1616 | ||
1617 | /* Ignore non-periodic endpoints */ | |
1618 | if (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP && | |
1619 | ep_type != ISOC_IN_EP && | |
1620 | ep_type != INT_IN_EP) | |
1621 | continue; | |
1622 | ||
1623 | /* Added or changed endpoint */ | |
1624 | bw_info->ep_interval = CTX_TO_EP_INTERVAL( | |
1625 | le32_to_cpu(ep_ctx->ep_info)); | |
170c0263 SS |
1626 | /* Number of packets and mult are zero-based in the |
1627 | * input context, but we want one-based for the | |
1628 | * interval table. | |
9af5d71d | 1629 | */ |
170c0263 SS |
1630 | bw_info->mult = CTX_TO_EP_MULT( |
1631 | le32_to_cpu(ep_ctx->ep_info)) + 1; | |
9af5d71d SS |
1632 | bw_info->num_packets = CTX_TO_MAX_BURST( |
1633 | le32_to_cpu(ep_ctx->ep_info2)) + 1; | |
1634 | bw_info->max_packet_size = MAX_PACKET_DECODED( | |
1635 | le32_to_cpu(ep_ctx->ep_info2)); | |
1636 | bw_info->type = ep_type; | |
1637 | bw_info->max_esit_payload = CTX_TO_MAX_ESIT_PAYLOAD( | |
1638 | le32_to_cpu(ep_ctx->tx_info)); | |
1639 | } | |
1640 | } | |
1641 | } | |
1642 | ||
f2217e8e SS |
1643 | /* Copy output xhci_ep_ctx to the input xhci_ep_ctx copy. |
1644 | * Useful when you want to change one particular aspect of the endpoint and then | |
1645 | * issue a configure endpoint command. | |
1646 | */ | |
1647 | void xhci_endpoint_copy(struct xhci_hcd *xhci, | |
913a8a34 SS |
1648 | struct xhci_container_ctx *in_ctx, |
1649 | struct xhci_container_ctx *out_ctx, | |
1650 | unsigned int ep_index) | |
f2217e8e SS |
1651 | { |
1652 | struct xhci_ep_ctx *out_ep_ctx; | |
1653 | struct xhci_ep_ctx *in_ep_ctx; | |
1654 | ||
913a8a34 SS |
1655 | out_ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index); |
1656 | in_ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index); | |
f2217e8e SS |
1657 | |
1658 | in_ep_ctx->ep_info = out_ep_ctx->ep_info; | |
1659 | in_ep_ctx->ep_info2 = out_ep_ctx->ep_info2; | |
1660 | in_ep_ctx->deq = out_ep_ctx->deq; | |
1661 | in_ep_ctx->tx_info = out_ep_ctx->tx_info; | |
1662 | } | |
1663 | ||
1664 | /* Copy output xhci_slot_ctx to the input xhci_slot_ctx. | |
1665 | * Useful when you want to change one particular aspect of the endpoint and then | |
1666 | * issue a configure endpoint command. Only the context entries field matters, | |
1667 | * but we'll copy the whole thing anyway. | |
1668 | */ | |
913a8a34 SS |
1669 | void xhci_slot_copy(struct xhci_hcd *xhci, |
1670 | struct xhci_container_ctx *in_ctx, | |
1671 | struct xhci_container_ctx *out_ctx) | |
f2217e8e SS |
1672 | { |
1673 | struct xhci_slot_ctx *in_slot_ctx; | |
1674 | struct xhci_slot_ctx *out_slot_ctx; | |
1675 | ||
913a8a34 SS |
1676 | in_slot_ctx = xhci_get_slot_ctx(xhci, in_ctx); |
1677 | out_slot_ctx = xhci_get_slot_ctx(xhci, out_ctx); | |
f2217e8e SS |
1678 | |
1679 | in_slot_ctx->dev_info = out_slot_ctx->dev_info; | |
1680 | in_slot_ctx->dev_info2 = out_slot_ctx->dev_info2; | |
1681 | in_slot_ctx->tt_info = out_slot_ctx->tt_info; | |
1682 | in_slot_ctx->dev_state = out_slot_ctx->dev_state; | |
1683 | } | |
1684 | ||
254c80a3 JY |
1685 | /* Set up the scratchpad buffer array and scratchpad buffers, if needed. */ |
1686 | static int scratchpad_alloc(struct xhci_hcd *xhci, gfp_t flags) | |
1687 | { | |
1688 | int i; | |
1689 | struct device *dev = xhci_to_hcd(xhci)->self.controller; | |
1690 | int num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2); | |
1691 | ||
d195fcff XR |
1692 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
1693 | "Allocating %d scratchpad buffers", num_sp); | |
254c80a3 JY |
1694 | |
1695 | if (!num_sp) | |
1696 | return 0; | |
1697 | ||
1698 | xhci->scratchpad = kzalloc(sizeof(*xhci->scratchpad), flags); | |
1699 | if (!xhci->scratchpad) | |
1700 | goto fail_sp; | |
1701 | ||
22d45f01 | 1702 | xhci->scratchpad->sp_array = dma_alloc_coherent(dev, |
254c80a3 | 1703 | num_sp * sizeof(u64), |
22d45f01 | 1704 | &xhci->scratchpad->sp_dma, flags); |
254c80a3 JY |
1705 | if (!xhci->scratchpad->sp_array) |
1706 | goto fail_sp2; | |
1707 | ||
1708 | xhci->scratchpad->sp_buffers = kzalloc(sizeof(void *) * num_sp, flags); | |
1709 | if (!xhci->scratchpad->sp_buffers) | |
1710 | goto fail_sp3; | |
1711 | ||
1712 | xhci->scratchpad->sp_dma_buffers = | |
1713 | kzalloc(sizeof(dma_addr_t) * num_sp, flags); | |
1714 | ||
1715 | if (!xhci->scratchpad->sp_dma_buffers) | |
1716 | goto fail_sp4; | |
1717 | ||
28ccd296 | 1718 | xhci->dcbaa->dev_context_ptrs[0] = cpu_to_le64(xhci->scratchpad->sp_dma); |
254c80a3 JY |
1719 | for (i = 0; i < num_sp; i++) { |
1720 | dma_addr_t dma; | |
22d45f01 SAS |
1721 | void *buf = dma_alloc_coherent(dev, xhci->page_size, &dma, |
1722 | flags); | |
254c80a3 JY |
1723 | if (!buf) |
1724 | goto fail_sp5; | |
1725 | ||
1726 | xhci->scratchpad->sp_array[i] = dma; | |
1727 | xhci->scratchpad->sp_buffers[i] = buf; | |
1728 | xhci->scratchpad->sp_dma_buffers[i] = dma; | |
1729 | } | |
1730 | ||
1731 | return 0; | |
1732 | ||
1733 | fail_sp5: | |
1734 | for (i = i - 1; i >= 0; i--) { | |
22d45f01 | 1735 | dma_free_coherent(dev, xhci->page_size, |
254c80a3 JY |
1736 | xhci->scratchpad->sp_buffers[i], |
1737 | xhci->scratchpad->sp_dma_buffers[i]); | |
1738 | } | |
1739 | kfree(xhci->scratchpad->sp_dma_buffers); | |
1740 | ||
1741 | fail_sp4: | |
1742 | kfree(xhci->scratchpad->sp_buffers); | |
1743 | ||
1744 | fail_sp3: | |
22d45f01 | 1745 | dma_free_coherent(dev, num_sp * sizeof(u64), |
254c80a3 JY |
1746 | xhci->scratchpad->sp_array, |
1747 | xhci->scratchpad->sp_dma); | |
1748 | ||
1749 | fail_sp2: | |
1750 | kfree(xhci->scratchpad); | |
1751 | xhci->scratchpad = NULL; | |
1752 | ||
1753 | fail_sp: | |
1754 | return -ENOMEM; | |
1755 | } | |
1756 | ||
1757 | static void scratchpad_free(struct xhci_hcd *xhci) | |
1758 | { | |
1759 | int num_sp; | |
1760 | int i; | |
2a100047 | 1761 | struct device *dev = xhci_to_hcd(xhci)->self.controller; |
254c80a3 JY |
1762 | |
1763 | if (!xhci->scratchpad) | |
1764 | return; | |
1765 | ||
1766 | num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2); | |
1767 | ||
1768 | for (i = 0; i < num_sp; i++) { | |
2a100047 | 1769 | dma_free_coherent(dev, xhci->page_size, |
254c80a3 JY |
1770 | xhci->scratchpad->sp_buffers[i], |
1771 | xhci->scratchpad->sp_dma_buffers[i]); | |
1772 | } | |
1773 | kfree(xhci->scratchpad->sp_dma_buffers); | |
1774 | kfree(xhci->scratchpad->sp_buffers); | |
2a100047 | 1775 | dma_free_coherent(dev, num_sp * sizeof(u64), |
254c80a3 JY |
1776 | xhci->scratchpad->sp_array, |
1777 | xhci->scratchpad->sp_dma); | |
1778 | kfree(xhci->scratchpad); | |
1779 | xhci->scratchpad = NULL; | |
1780 | } | |
1781 | ||
913a8a34 | 1782 | struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci, |
a1d78c16 SS |
1783 | bool allocate_in_ctx, bool allocate_completion, |
1784 | gfp_t mem_flags) | |
913a8a34 SS |
1785 | { |
1786 | struct xhci_command *command; | |
1787 | ||
1788 | command = kzalloc(sizeof(*command), mem_flags); | |
1789 | if (!command) | |
1790 | return NULL; | |
1791 | ||
a1d78c16 SS |
1792 | if (allocate_in_ctx) { |
1793 | command->in_ctx = | |
1794 | xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT, | |
1795 | mem_flags); | |
1796 | if (!command->in_ctx) { | |
1797 | kfree(command); | |
1798 | return NULL; | |
1799 | } | |
06e18291 | 1800 | } |
913a8a34 SS |
1801 | |
1802 | if (allocate_completion) { | |
1803 | command->completion = | |
1804 | kzalloc(sizeof(struct completion), mem_flags); | |
1805 | if (!command->completion) { | |
1806 | xhci_free_container_ctx(xhci, command->in_ctx); | |
06e18291 | 1807 | kfree(command); |
913a8a34 SS |
1808 | return NULL; |
1809 | } | |
1810 | init_completion(command->completion); | |
1811 | } | |
1812 | ||
1813 | command->status = 0; | |
1814 | INIT_LIST_HEAD(&command->cmd_list); | |
1815 | return command; | |
1816 | } | |
1817 | ||
4daf9df5 | 1818 | void xhci_urb_free_priv(struct urb_priv *urb_priv) |
8e51adcc | 1819 | { |
7e64b037 | 1820 | kfree(urb_priv); |
8e51adcc AX |
1821 | } |
1822 | ||
913a8a34 SS |
1823 | void xhci_free_command(struct xhci_hcd *xhci, |
1824 | struct xhci_command *command) | |
1825 | { | |
1826 | xhci_free_container_ctx(xhci, | |
1827 | command->in_ctx); | |
1828 | kfree(command->completion); | |
1829 | kfree(command); | |
1830 | } | |
1831 | ||
66d4eadd SS |
1832 | void xhci_mem_cleanup(struct xhci_hcd *xhci) |
1833 | { | |
2a100047 | 1834 | struct device *dev = xhci_to_hcd(xhci)->self.controller; |
0ebbab37 | 1835 | int size; |
32f1d2c5 | 1836 | int i, j, num_ports; |
0ebbab37 | 1837 | |
cb4d5ce5 | 1838 | cancel_delayed_work_sync(&xhci->cmd_timer); |
c311e391 | 1839 | |
0ebbab37 | 1840 | /* Free the Event Ring Segment Table and the actual Event Ring */ |
0ebbab37 SS |
1841 | size = sizeof(struct xhci_erst_entry)*(xhci->erst.num_entries); |
1842 | if (xhci->erst.entries) | |
2a100047 | 1843 | dma_free_coherent(dev, size, |
0ebbab37 SS |
1844 | xhci->erst.entries, xhci->erst.erst_dma_addr); |
1845 | xhci->erst.entries = NULL; | |
d195fcff | 1846 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed ERST"); |
0ebbab37 SS |
1847 | if (xhci->event_ring) |
1848 | xhci_ring_free(xhci, xhci->event_ring); | |
1849 | xhci->event_ring = NULL; | |
d195fcff | 1850 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed event ring"); |
0ebbab37 | 1851 | |
dbc33303 SS |
1852 | if (xhci->lpm_command) |
1853 | xhci_free_command(xhci, xhci->lpm_command); | |
0eda06c7 | 1854 | xhci->lpm_command = NULL; |
0ebbab37 SS |
1855 | if (xhci->cmd_ring) |
1856 | xhci_ring_free(xhci, xhci->cmd_ring); | |
1857 | xhci->cmd_ring = NULL; | |
d195fcff | 1858 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed command ring"); |
c9aa1a2d | 1859 | xhci_cleanup_command_queue(xhci); |
3ffbba95 | 1860 | |
5dc2808c | 1861 | num_ports = HCS_MAX_PORTS(xhci->hcs_params1); |
c207e7c5 | 1862 | for (i = 0; i < num_ports && xhci->rh_bw; i++) { |
5dc2808c MN |
1863 | struct xhci_interval_bw_table *bwt = &xhci->rh_bw[i].bw_table; |
1864 | for (j = 0; j < XHCI_MAX_INTERVAL; j++) { | |
1865 | struct list_head *ep = &bwt->interval_bw[j].endpoints; | |
1866 | while (!list_empty(ep)) | |
1867 | list_del_init(ep->next); | |
1868 | } | |
1869 | } | |
1870 | ||
ee8665e2 MN |
1871 | for (i = HCS_MAX_SLOTS(xhci->hcs_params1); i > 0; i--) |
1872 | xhci_free_virt_devices_depth_first(xhci, i); | |
3ffbba95 | 1873 | |
c7360b34 | 1874 | dma_pool_destroy(xhci->segment_pool); |
0ebbab37 | 1875 | xhci->segment_pool = NULL; |
d195fcff | 1876 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed segment pool"); |
3ffbba95 | 1877 | |
c7360b34 | 1878 | dma_pool_destroy(xhci->device_pool); |
3ffbba95 | 1879 | xhci->device_pool = NULL; |
d195fcff | 1880 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed device context pool"); |
3ffbba95 | 1881 | |
c7360b34 | 1882 | dma_pool_destroy(xhci->small_streams_pool); |
8df75f42 | 1883 | xhci->small_streams_pool = NULL; |
d195fcff XR |
1884 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
1885 | "Freed small stream array pool"); | |
8df75f42 | 1886 | |
c7360b34 | 1887 | dma_pool_destroy(xhci->medium_streams_pool); |
8df75f42 | 1888 | xhci->medium_streams_pool = NULL; |
d195fcff XR |
1889 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
1890 | "Freed medium stream array pool"); | |
8df75f42 | 1891 | |
a74588f9 | 1892 | if (xhci->dcbaa) |
2a100047 | 1893 | dma_free_coherent(dev, sizeof(*xhci->dcbaa), |
a74588f9 SS |
1894 | xhci->dcbaa, xhci->dcbaa->dma); |
1895 | xhci->dcbaa = NULL; | |
3ffbba95 | 1896 | |
5294bea4 | 1897 | scratchpad_free(xhci); |
da6699ce | 1898 | |
88696ae4 VM |
1899 | if (!xhci->rh_bw) |
1900 | goto no_bw; | |
1901 | ||
32f1d2c5 TI |
1902 | for (i = 0; i < num_ports; i++) { |
1903 | struct xhci_tt_bw_info *tt, *n; | |
1904 | list_for_each_entry_safe(tt, n, &xhci->rh_bw[i].tts, tt_list) { | |
1905 | list_del(&tt->tt_list); | |
1906 | kfree(tt); | |
1907 | } | |
f8a9e72d ON |
1908 | } |
1909 | ||
88696ae4 | 1910 | no_bw: |
127329d7 | 1911 | xhci->cmd_ring_reserved_trbs = 0; |
da6699ce SS |
1912 | xhci->num_usb2_ports = 0; |
1913 | xhci->num_usb3_ports = 0; | |
f8a9e72d | 1914 | xhci->num_active_eps = 0; |
da6699ce SS |
1915 | kfree(xhci->usb2_ports); |
1916 | kfree(xhci->usb3_ports); | |
1917 | kfree(xhci->port_array); | |
839c817c | 1918 | kfree(xhci->rh_bw); |
b630d4b9 | 1919 | kfree(xhci->ext_caps); |
da6699ce | 1920 | |
71504062 LB |
1921 | xhci->usb2_ports = NULL; |
1922 | xhci->usb3_ports = NULL; | |
1923 | xhci->port_array = NULL; | |
1924 | xhci->rh_bw = NULL; | |
1925 | xhci->ext_caps = NULL; | |
1926 | ||
66d4eadd SS |
1927 | xhci->page_size = 0; |
1928 | xhci->page_shift = 0; | |
20b67cf5 | 1929 | xhci->bus_state[0].bus_suspended = 0; |
f6ff0ac8 | 1930 | xhci->bus_state[1].bus_suspended = 0; |
66d4eadd SS |
1931 | } |
1932 | ||
6648f29d SS |
1933 | static int xhci_test_trb_in_td(struct xhci_hcd *xhci, |
1934 | struct xhci_segment *input_seg, | |
1935 | union xhci_trb *start_trb, | |
1936 | union xhci_trb *end_trb, | |
1937 | dma_addr_t input_dma, | |
1938 | struct xhci_segment *result_seg, | |
1939 | char *test_name, int test_number) | |
1940 | { | |
1941 | unsigned long long start_dma; | |
1942 | unsigned long long end_dma; | |
1943 | struct xhci_segment *seg; | |
1944 | ||
1945 | start_dma = xhci_trb_virt_to_dma(input_seg, start_trb); | |
1946 | end_dma = xhci_trb_virt_to_dma(input_seg, end_trb); | |
1947 | ||
cffb9be8 | 1948 | seg = trb_in_td(xhci, input_seg, start_trb, end_trb, input_dma, false); |
6648f29d SS |
1949 | if (seg != result_seg) { |
1950 | xhci_warn(xhci, "WARN: %s TRB math test %d failed!\n", | |
1951 | test_name, test_number); | |
1952 | xhci_warn(xhci, "Tested TRB math w/ seg %p and " | |
1953 | "input DMA 0x%llx\n", | |
1954 | input_seg, | |
1955 | (unsigned long long) input_dma); | |
1956 | xhci_warn(xhci, "starting TRB %p (0x%llx DMA), " | |
1957 | "ending TRB %p (0x%llx DMA)\n", | |
1958 | start_trb, start_dma, | |
1959 | end_trb, end_dma); | |
1960 | xhci_warn(xhci, "Expected seg %p, got seg %p\n", | |
1961 | result_seg, seg); | |
cffb9be8 HG |
1962 | trb_in_td(xhci, input_seg, start_trb, end_trb, input_dma, |
1963 | true); | |
6648f29d SS |
1964 | return -1; |
1965 | } | |
1966 | return 0; | |
1967 | } | |
1968 | ||
1969 | /* TRB math checks for xhci_trb_in_td(), using the command and event rings. */ | |
4daf9df5 | 1970 | static int xhci_check_trb_in_td_math(struct xhci_hcd *xhci) |
6648f29d SS |
1971 | { |
1972 | struct { | |
1973 | dma_addr_t input_dma; | |
1974 | struct xhci_segment *result_seg; | |
1975 | } simple_test_vector [] = { | |
1976 | /* A zeroed DMA field should fail */ | |
1977 | { 0, NULL }, | |
1978 | /* One TRB before the ring start should fail */ | |
1979 | { xhci->event_ring->first_seg->dma - 16, NULL }, | |
1980 | /* One byte before the ring start should fail */ | |
1981 | { xhci->event_ring->first_seg->dma - 1, NULL }, | |
1982 | /* Starting TRB should succeed */ | |
1983 | { xhci->event_ring->first_seg->dma, xhci->event_ring->first_seg }, | |
1984 | /* Ending TRB should succeed */ | |
1985 | { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16, | |
1986 | xhci->event_ring->first_seg }, | |
1987 | /* One byte after the ring end should fail */ | |
1988 | { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16 + 1, NULL }, | |
1989 | /* One TRB after the ring end should fail */ | |
1990 | { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT)*16, NULL }, | |
1991 | /* An address of all ones should fail */ | |
1992 | { (dma_addr_t) (~0), NULL }, | |
1993 | }; | |
1994 | struct { | |
1995 | struct xhci_segment *input_seg; | |
1996 | union xhci_trb *start_trb; | |
1997 | union xhci_trb *end_trb; | |
1998 | dma_addr_t input_dma; | |
1999 | struct xhci_segment *result_seg; | |
2000 | } complex_test_vector [] = { | |
2001 | /* Test feeding a valid DMA address from a different ring */ | |
2002 | { .input_seg = xhci->event_ring->first_seg, | |
2003 | .start_trb = xhci->event_ring->first_seg->trbs, | |
2004 | .end_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1], | |
2005 | .input_dma = xhci->cmd_ring->first_seg->dma, | |
2006 | .result_seg = NULL, | |
2007 | }, | |
2008 | /* Test feeding a valid end TRB from a different ring */ | |
2009 | { .input_seg = xhci->event_ring->first_seg, | |
2010 | .start_trb = xhci->event_ring->first_seg->trbs, | |
2011 | .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1], | |
2012 | .input_dma = xhci->cmd_ring->first_seg->dma, | |
2013 | .result_seg = NULL, | |
2014 | }, | |
2015 | /* Test feeding a valid start and end TRB from a different ring */ | |
2016 | { .input_seg = xhci->event_ring->first_seg, | |
2017 | .start_trb = xhci->cmd_ring->first_seg->trbs, | |
2018 | .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1], | |
2019 | .input_dma = xhci->cmd_ring->first_seg->dma, | |
2020 | .result_seg = NULL, | |
2021 | }, | |
2022 | /* TRB in this ring, but after this TD */ | |
2023 | { .input_seg = xhci->event_ring->first_seg, | |
2024 | .start_trb = &xhci->event_ring->first_seg->trbs[0], | |
2025 | .end_trb = &xhci->event_ring->first_seg->trbs[3], | |
2026 | .input_dma = xhci->event_ring->first_seg->dma + 4*16, | |
2027 | .result_seg = NULL, | |
2028 | }, | |
2029 | /* TRB in this ring, but before this TD */ | |
2030 | { .input_seg = xhci->event_ring->first_seg, | |
2031 | .start_trb = &xhci->event_ring->first_seg->trbs[3], | |
2032 | .end_trb = &xhci->event_ring->first_seg->trbs[6], | |
2033 | .input_dma = xhci->event_ring->first_seg->dma + 2*16, | |
2034 | .result_seg = NULL, | |
2035 | }, | |
2036 | /* TRB in this ring, but after this wrapped TD */ | |
2037 | { .input_seg = xhci->event_ring->first_seg, | |
2038 | .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3], | |
2039 | .end_trb = &xhci->event_ring->first_seg->trbs[1], | |
2040 | .input_dma = xhci->event_ring->first_seg->dma + 2*16, | |
2041 | .result_seg = NULL, | |
2042 | }, | |
2043 | /* TRB in this ring, but before this wrapped TD */ | |
2044 | { .input_seg = xhci->event_ring->first_seg, | |
2045 | .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3], | |
2046 | .end_trb = &xhci->event_ring->first_seg->trbs[1], | |
2047 | .input_dma = xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 4)*16, | |
2048 | .result_seg = NULL, | |
2049 | }, | |
2050 | /* TRB not in this ring, and we have a wrapped TD */ | |
2051 | { .input_seg = xhci->event_ring->first_seg, | |
2052 | .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3], | |
2053 | .end_trb = &xhci->event_ring->first_seg->trbs[1], | |
2054 | .input_dma = xhci->cmd_ring->first_seg->dma + 2*16, | |
2055 | .result_seg = NULL, | |
2056 | }, | |
2057 | }; | |
2058 | ||
2059 | unsigned int num_tests; | |
2060 | int i, ret; | |
2061 | ||
e10fa478 | 2062 | num_tests = ARRAY_SIZE(simple_test_vector); |
6648f29d SS |
2063 | for (i = 0; i < num_tests; i++) { |
2064 | ret = xhci_test_trb_in_td(xhci, | |
2065 | xhci->event_ring->first_seg, | |
2066 | xhci->event_ring->first_seg->trbs, | |
2067 | &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1], | |
2068 | simple_test_vector[i].input_dma, | |
2069 | simple_test_vector[i].result_seg, | |
2070 | "Simple", i); | |
2071 | if (ret < 0) | |
2072 | return ret; | |
2073 | } | |
2074 | ||
e10fa478 | 2075 | num_tests = ARRAY_SIZE(complex_test_vector); |
6648f29d SS |
2076 | for (i = 0; i < num_tests; i++) { |
2077 | ret = xhci_test_trb_in_td(xhci, | |
2078 | complex_test_vector[i].input_seg, | |
2079 | complex_test_vector[i].start_trb, | |
2080 | complex_test_vector[i].end_trb, | |
2081 | complex_test_vector[i].input_dma, | |
2082 | complex_test_vector[i].result_seg, | |
2083 | "Complex", i); | |
2084 | if (ret < 0) | |
2085 | return ret; | |
2086 | } | |
2087 | xhci_dbg(xhci, "TRB math tests passed.\n"); | |
2088 | return 0; | |
2089 | } | |
2090 | ||
257d585a SS |
2091 | static void xhci_set_hc_event_deq(struct xhci_hcd *xhci) |
2092 | { | |
2093 | u64 temp; | |
2094 | dma_addr_t deq; | |
2095 | ||
2096 | deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg, | |
2097 | xhci->event_ring->dequeue); | |
2098 | if (deq == 0 && !in_interrupt()) | |
2099 | xhci_warn(xhci, "WARN something wrong with SW event ring " | |
2100 | "dequeue ptr.\n"); | |
2101 | /* Update HC event ring dequeue pointer */ | |
f7b2e403 | 2102 | temp = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); |
257d585a SS |
2103 | temp &= ERST_PTR_MASK; |
2104 | /* Don't clear the EHB bit (which is RW1C) because | |
2105 | * there might be more events to service. | |
2106 | */ | |
2107 | temp &= ~ERST_EHB; | |
d195fcff XR |
2108 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2109 | "// Write event ring dequeue pointer, " | |
2110 | "preserving EHB bit"); | |
477632df | 2111 | xhci_write_64(xhci, ((u64) deq & (u64) ~ERST_PTR_MASK) | temp, |
257d585a SS |
2112 | &xhci->ir_set->erst_dequeue); |
2113 | } | |
2114 | ||
da6699ce | 2115 | static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int num_ports, |
d5ddcdf4 | 2116 | __le32 __iomem *addr, int max_caps) |
da6699ce SS |
2117 | { |
2118 | u32 temp, port_offset, port_count; | |
2119 | int i; | |
d5ddcdf4 | 2120 | u8 major_revision; |
47189098 | 2121 | struct xhci_hub *rhub; |
da6699ce | 2122 | |
47189098 | 2123 | temp = readl(addr); |
d5ddcdf4 | 2124 | major_revision = XHCI_EXT_PORT_MAJOR(temp); |
47189098 | 2125 | |
d5ddcdf4 | 2126 | if (major_revision == 0x03) { |
47189098 | 2127 | rhub = &xhci->usb3_rhub; |
d5ddcdf4 | 2128 | } else if (major_revision <= 0x02) { |
47189098 MN |
2129 | rhub = &xhci->usb2_rhub; |
2130 | } else { | |
da6699ce SS |
2131 | xhci_warn(xhci, "Ignoring unknown port speed, " |
2132 | "Ext Cap %p, revision = 0x%x\n", | |
2133 | addr, major_revision); | |
2134 | /* Ignoring port protocol we can't understand. FIXME */ | |
2135 | return; | |
2136 | } | |
47189098 MN |
2137 | rhub->maj_rev = XHCI_EXT_PORT_MAJOR(temp); |
2138 | rhub->min_rev = XHCI_EXT_PORT_MINOR(temp); | |
da6699ce SS |
2139 | |
2140 | /* Port offset and count in the third dword, see section 7.2 */ | |
b0ba9720 | 2141 | temp = readl(addr + 2); |
da6699ce SS |
2142 | port_offset = XHCI_EXT_PORT_OFF(temp); |
2143 | port_count = XHCI_EXT_PORT_COUNT(temp); | |
d195fcff XR |
2144 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2145 | "Ext Cap %p, port offset = %u, " | |
2146 | "count = %u, revision = 0x%x", | |
da6699ce SS |
2147 | addr, port_offset, port_count, major_revision); |
2148 | /* Port count includes the current port offset */ | |
2149 | if (port_offset == 0 || (port_offset + port_count - 1) > num_ports) | |
2150 | /* WTF? "Valid values are ‘1’ to MaxPorts" */ | |
2151 | return; | |
fc71ff75 | 2152 | |
47189098 MN |
2153 | rhub->psi_count = XHCI_EXT_PORT_PSIC(temp); |
2154 | if (rhub->psi_count) { | |
2155 | rhub->psi = kcalloc(rhub->psi_count, sizeof(*rhub->psi), | |
2156 | GFP_KERNEL); | |
2157 | if (!rhub->psi) | |
2158 | rhub->psi_count = 0; | |
2159 | ||
2160 | rhub->psi_uid_count++; | |
2161 | for (i = 0; i < rhub->psi_count; i++) { | |
2162 | rhub->psi[i] = readl(addr + 4 + i); | |
2163 | ||
2164 | /* count unique ID values, two consecutive entries can | |
2165 | * have the same ID if link is assymetric | |
2166 | */ | |
2167 | if (i && (XHCI_EXT_PORT_PSIV(rhub->psi[i]) != | |
2168 | XHCI_EXT_PORT_PSIV(rhub->psi[i - 1]))) | |
2169 | rhub->psi_uid_count++; | |
2170 | ||
2171 | xhci_dbg(xhci, "PSIV:%d PSIE:%d PLT:%d PFD:%d LP:%d PSIM:%d\n", | |
2172 | XHCI_EXT_PORT_PSIV(rhub->psi[i]), | |
2173 | XHCI_EXT_PORT_PSIE(rhub->psi[i]), | |
2174 | XHCI_EXT_PORT_PLT(rhub->psi[i]), | |
2175 | XHCI_EXT_PORT_PFD(rhub->psi[i]), | |
2176 | XHCI_EXT_PORT_LP(rhub->psi[i]), | |
2177 | XHCI_EXT_PORT_PSIM(rhub->psi[i])); | |
2178 | } | |
2179 | } | |
b630d4b9 MN |
2180 | /* cache usb2 port capabilities */ |
2181 | if (major_revision < 0x03 && xhci->num_ext_caps < max_caps) | |
2182 | xhci->ext_caps[xhci->num_ext_caps++] = temp; | |
2183 | ||
fc71ff75 AX |
2184 | /* Check the host's USB2 LPM capability */ |
2185 | if ((xhci->hci_version == 0x96) && (major_revision != 0x03) && | |
2186 | (temp & XHCI_L1C)) { | |
d195fcff XR |
2187 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2188 | "xHCI 0.96: support USB2 software lpm"); | |
fc71ff75 AX |
2189 | xhci->sw_lpm_support = 1; |
2190 | } | |
2191 | ||
2192 | if ((xhci->hci_version >= 0x100) && (major_revision != 0x03)) { | |
d195fcff XR |
2193 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2194 | "xHCI 1.0: support USB2 software lpm"); | |
fc71ff75 AX |
2195 | xhci->sw_lpm_support = 1; |
2196 | if (temp & XHCI_HLC) { | |
d195fcff XR |
2197 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2198 | "xHCI 1.0: support USB2 hardware lpm"); | |
fc71ff75 AX |
2199 | xhci->hw_lpm_support = 1; |
2200 | } | |
2201 | } | |
2202 | ||
da6699ce SS |
2203 | port_offset--; |
2204 | for (i = port_offset; i < (port_offset + port_count); i++) { | |
2205 | /* Duplicate entry. Ignore the port if the revisions differ. */ | |
2206 | if (xhci->port_array[i] != 0) { | |
2207 | xhci_warn(xhci, "Duplicate port entry, Ext Cap %p," | |
2208 | " port %u\n", addr, i); | |
2209 | xhci_warn(xhci, "Port was marked as USB %u, " | |
2210 | "duplicated as USB %u\n", | |
2211 | xhci->port_array[i], major_revision); | |
2212 | /* Only adjust the roothub port counts if we haven't | |
2213 | * found a similar duplicate. | |
2214 | */ | |
2215 | if (xhci->port_array[i] != major_revision && | |
22e04870 | 2216 | xhci->port_array[i] != DUPLICATE_ENTRY) { |
da6699ce SS |
2217 | if (xhci->port_array[i] == 0x03) |
2218 | xhci->num_usb3_ports--; | |
2219 | else | |
2220 | xhci->num_usb2_ports--; | |
22e04870 | 2221 | xhci->port_array[i] = DUPLICATE_ENTRY; |
da6699ce SS |
2222 | } |
2223 | /* FIXME: Should we disable the port? */ | |
f8bbeabc | 2224 | continue; |
da6699ce SS |
2225 | } |
2226 | xhci->port_array[i] = major_revision; | |
2227 | if (major_revision == 0x03) | |
2228 | xhci->num_usb3_ports++; | |
2229 | else | |
2230 | xhci->num_usb2_ports++; | |
2231 | } | |
2232 | /* FIXME: Should we disable ports not in the Extended Capabilities? */ | |
2233 | } | |
2234 | ||
2235 | /* | |
2236 | * Scan the Extended Capabilities for the "Supported Protocol Capabilities" that | |
2237 | * specify what speeds each port is supposed to be. We can't count on the port | |
2238 | * speed bits in the PORTSC register being correct until a device is connected, | |
2239 | * but we need to set up the two fake roothubs with the correct number of USB | |
2240 | * 3.0 and USB 2.0 ports at host controller initialization time. | |
2241 | */ | |
2242 | static int xhci_setup_port_arrays(struct xhci_hcd *xhci, gfp_t flags) | |
2243 | { | |
d5ddcdf4 MN |
2244 | void __iomem *base; |
2245 | u32 offset; | |
da6699ce | 2246 | unsigned int num_ports; |
2e27980e | 2247 | int i, j, port_index; |
b630d4b9 | 2248 | int cap_count = 0; |
d5ddcdf4 | 2249 | u32 cap_start; |
da6699ce SS |
2250 | |
2251 | num_ports = HCS_MAX_PORTS(xhci->hcs_params1); | |
2252 | xhci->port_array = kzalloc(sizeof(*xhci->port_array)*num_ports, flags); | |
2253 | if (!xhci->port_array) | |
2254 | return -ENOMEM; | |
2255 | ||
839c817c SS |
2256 | xhci->rh_bw = kzalloc(sizeof(*xhci->rh_bw)*num_ports, flags); |
2257 | if (!xhci->rh_bw) | |
2258 | return -ENOMEM; | |
2e27980e SS |
2259 | for (i = 0; i < num_ports; i++) { |
2260 | struct xhci_interval_bw_table *bw_table; | |
2261 | ||
839c817c | 2262 | INIT_LIST_HEAD(&xhci->rh_bw[i].tts); |
2e27980e SS |
2263 | bw_table = &xhci->rh_bw[i].bw_table; |
2264 | for (j = 0; j < XHCI_MAX_INTERVAL; j++) | |
2265 | INIT_LIST_HEAD(&bw_table->interval_bw[j].endpoints); | |
2266 | } | |
d5ddcdf4 | 2267 | base = &xhci->cap_regs->hc_capbase; |
839c817c | 2268 | |
d5ddcdf4 MN |
2269 | cap_start = xhci_find_next_ext_cap(base, 0, XHCI_EXT_CAPS_PROTOCOL); |
2270 | if (!cap_start) { | |
2271 | xhci_err(xhci, "No Extended Capability registers, unable to set up roothub\n"); | |
2272 | return -ENODEV; | |
2273 | } | |
b630d4b9 | 2274 | |
d5ddcdf4 | 2275 | offset = cap_start; |
b630d4b9 | 2276 | /* count extended protocol capability entries for later caching */ |
d5ddcdf4 MN |
2277 | while (offset) { |
2278 | cap_count++; | |
2279 | offset = xhci_find_next_ext_cap(base, offset, | |
2280 | XHCI_EXT_CAPS_PROTOCOL); | |
2281 | } | |
b630d4b9 MN |
2282 | |
2283 | xhci->ext_caps = kzalloc(sizeof(*xhci->ext_caps) * cap_count, flags); | |
2284 | if (!xhci->ext_caps) | |
2285 | return -ENOMEM; | |
2286 | ||
d5ddcdf4 MN |
2287 | offset = cap_start; |
2288 | ||
2289 | while (offset) { | |
2290 | xhci_add_in_port(xhci, num_ports, base + offset, cap_count); | |
2291 | if (xhci->num_usb2_ports + xhci->num_usb3_ports == num_ports) | |
da6699ce | 2292 | break; |
d5ddcdf4 MN |
2293 | offset = xhci_find_next_ext_cap(base, offset, |
2294 | XHCI_EXT_CAPS_PROTOCOL); | |
da6699ce SS |
2295 | } |
2296 | ||
2297 | if (xhci->num_usb2_ports == 0 && xhci->num_usb3_ports == 0) { | |
2298 | xhci_warn(xhci, "No ports on the roothubs?\n"); | |
2299 | return -ENODEV; | |
2300 | } | |
d195fcff XR |
2301 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2302 | "Found %u USB 2.0 ports and %u USB 3.0 ports.", | |
da6699ce | 2303 | xhci->num_usb2_ports, xhci->num_usb3_ports); |
d30b2a20 SS |
2304 | |
2305 | /* Place limits on the number of roothub ports so that the hub | |
2306 | * descriptors aren't longer than the USB core will allocate. | |
2307 | */ | |
2308 | if (xhci->num_usb3_ports > 15) { | |
d195fcff XR |
2309 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2310 | "Limiting USB 3.0 roothub ports to 15."); | |
d30b2a20 SS |
2311 | xhci->num_usb3_ports = 15; |
2312 | } | |
2313 | if (xhci->num_usb2_ports > USB_MAXCHILDREN) { | |
d195fcff XR |
2314 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2315 | "Limiting USB 2.0 roothub ports to %u.", | |
d30b2a20 SS |
2316 | USB_MAXCHILDREN); |
2317 | xhci->num_usb2_ports = USB_MAXCHILDREN; | |
2318 | } | |
2319 | ||
da6699ce SS |
2320 | /* |
2321 | * Note we could have all USB 3.0 ports, or all USB 2.0 ports. | |
2322 | * Not sure how the USB core will handle a hub with no ports... | |
2323 | */ | |
2324 | if (xhci->num_usb2_ports) { | |
2325 | xhci->usb2_ports = kmalloc(sizeof(*xhci->usb2_ports)* | |
2326 | xhci->num_usb2_ports, flags); | |
2327 | if (!xhci->usb2_ports) | |
2328 | return -ENOMEM; | |
2329 | ||
2330 | port_index = 0; | |
f8bbeabc SS |
2331 | for (i = 0; i < num_ports; i++) { |
2332 | if (xhci->port_array[i] == 0x03 || | |
2333 | xhci->port_array[i] == 0 || | |
22e04870 | 2334 | xhci->port_array[i] == DUPLICATE_ENTRY) |
f8bbeabc SS |
2335 | continue; |
2336 | ||
2337 | xhci->usb2_ports[port_index] = | |
2338 | &xhci->op_regs->port_status_base + | |
2339 | NUM_PORT_REGS*i; | |
d195fcff XR |
2340 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2341 | "USB 2.0 port at index %u, " | |
2342 | "addr = %p", i, | |
f8bbeabc SS |
2343 | xhci->usb2_ports[port_index]); |
2344 | port_index++; | |
d30b2a20 SS |
2345 | if (port_index == xhci->num_usb2_ports) |
2346 | break; | |
f8bbeabc | 2347 | } |
da6699ce SS |
2348 | } |
2349 | if (xhci->num_usb3_ports) { | |
2350 | xhci->usb3_ports = kmalloc(sizeof(*xhci->usb3_ports)* | |
2351 | xhci->num_usb3_ports, flags); | |
2352 | if (!xhci->usb3_ports) | |
2353 | return -ENOMEM; | |
2354 | ||
2355 | port_index = 0; | |
2356 | for (i = 0; i < num_ports; i++) | |
2357 | if (xhci->port_array[i] == 0x03) { | |
2358 | xhci->usb3_ports[port_index] = | |
2359 | &xhci->op_regs->port_status_base + | |
2360 | NUM_PORT_REGS*i; | |
d195fcff XR |
2361 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2362 | "USB 3.0 port at index %u, " | |
2363 | "addr = %p", i, | |
da6699ce SS |
2364 | xhci->usb3_ports[port_index]); |
2365 | port_index++; | |
d30b2a20 SS |
2366 | if (port_index == xhci->num_usb3_ports) |
2367 | break; | |
da6699ce SS |
2368 | } |
2369 | } | |
2370 | return 0; | |
2371 | } | |
6648f29d | 2372 | |
66d4eadd SS |
2373 | int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags) |
2374 | { | |
0ebbab37 SS |
2375 | dma_addr_t dma; |
2376 | struct device *dev = xhci_to_hcd(xhci)->self.controller; | |
66d4eadd | 2377 | unsigned int val, val2; |
8e595a5d | 2378 | u64 val_64; |
0ebbab37 | 2379 | struct xhci_segment *seg; |
623bef9e | 2380 | u32 page_size, temp; |
66d4eadd SS |
2381 | int i; |
2382 | ||
c9aa1a2d | 2383 | INIT_LIST_HEAD(&xhci->cmd_list); |
331de00a | 2384 | |
cb4d5ce5 OH |
2385 | /* init command timeout work */ |
2386 | INIT_DELAYED_WORK(&xhci->cmd_timer, xhci_handle_command_timeout); | |
1c111b6c | 2387 | init_completion(&xhci->cmd_ring_stop_completion); |
cc8e4fc0 | 2388 | |
b0ba9720 | 2389 | page_size = readl(&xhci->op_regs->page_size); |
d195fcff XR |
2390 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2391 | "Supported page size register = 0x%x", page_size); | |
66d4eadd SS |
2392 | for (i = 0; i < 16; i++) { |
2393 | if ((0x1 & page_size) != 0) | |
2394 | break; | |
2395 | page_size = page_size >> 1; | |
2396 | } | |
2397 | if (i < 16) | |
d195fcff XR |
2398 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2399 | "Supported page size of %iK", (1 << (i+12)) / 1024); | |
66d4eadd SS |
2400 | else |
2401 | xhci_warn(xhci, "WARN: no supported page size\n"); | |
2402 | /* Use 4K pages, since that's common and the minimum the HC supports */ | |
2403 | xhci->page_shift = 12; | |
2404 | xhci->page_size = 1 << xhci->page_shift; | |
d195fcff XR |
2405 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2406 | "HCD page size set to %iK", xhci->page_size / 1024); | |
66d4eadd SS |
2407 | |
2408 | /* | |
2409 | * Program the Number of Device Slots Enabled field in the CONFIG | |
2410 | * register with the max value of slots the HC can handle. | |
2411 | */ | |
b0ba9720 | 2412 | val = HCS_MAX_SLOTS(readl(&xhci->cap_regs->hcs_params1)); |
d195fcff XR |
2413 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2414 | "// xHC can handle at most %d device slots.", val); | |
b0ba9720 | 2415 | val2 = readl(&xhci->op_regs->config_reg); |
66d4eadd | 2416 | val |= (val2 & ~HCS_SLOTS_MASK); |
d195fcff XR |
2417 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2418 | "// Setting Max device slots reg = 0x%x.", val); | |
204b7793 | 2419 | writel(val, &xhci->op_regs->config_reg); |
66d4eadd | 2420 | |
a74588f9 SS |
2421 | /* |
2422 | * Section 5.4.8 - doorbell array must be | |
2423 | * "physically contiguous and 64-byte (cache line) aligned". | |
2424 | */ | |
22d45f01 | 2425 | xhci->dcbaa = dma_alloc_coherent(dev, sizeof(*xhci->dcbaa), &dma, |
c95a9f83 | 2426 | flags); |
a74588f9 SS |
2427 | if (!xhci->dcbaa) |
2428 | goto fail; | |
2429 | memset(xhci->dcbaa, 0, sizeof *(xhci->dcbaa)); | |
2430 | xhci->dcbaa->dma = dma; | |
d195fcff XR |
2431 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2432 | "// Device context base array address = 0x%llx (DMA), %p (virt)", | |
700e2052 | 2433 | (unsigned long long)xhci->dcbaa->dma, xhci->dcbaa); |
477632df | 2434 | xhci_write_64(xhci, dma, &xhci->op_regs->dcbaa_ptr); |
a74588f9 | 2435 | |
0ebbab37 SS |
2436 | /* |
2437 | * Initialize the ring segment pool. The ring must be a contiguous | |
2438 | * structure comprised of TRBs. The TRBs must be 16 byte aligned, | |
84c1e40f HG |
2439 | * however, the command ring segment needs 64-byte aligned segments |
2440 | * and our use of dma addresses in the trb_address_map radix tree needs | |
2441 | * TRB_SEGMENT_SIZE alignment, so we pick the greater alignment need. | |
0ebbab37 SS |
2442 | */ |
2443 | xhci->segment_pool = dma_pool_create("xHCI ring segments", dev, | |
84c1e40f | 2444 | TRB_SEGMENT_SIZE, TRB_SEGMENT_SIZE, xhci->page_size); |
d115b048 | 2445 | |
3ffbba95 | 2446 | /* See Table 46 and Note on Figure 55 */ |
3ffbba95 | 2447 | xhci->device_pool = dma_pool_create("xHCI input/output contexts", dev, |
d115b048 | 2448 | 2112, 64, xhci->page_size); |
3ffbba95 | 2449 | if (!xhci->segment_pool || !xhci->device_pool) |
0ebbab37 SS |
2450 | goto fail; |
2451 | ||
8df75f42 SS |
2452 | /* Linear stream context arrays don't have any boundary restrictions, |
2453 | * and only need to be 16-byte aligned. | |
2454 | */ | |
2455 | xhci->small_streams_pool = | |
2456 | dma_pool_create("xHCI 256 byte stream ctx arrays", | |
2457 | dev, SMALL_STREAM_ARRAY_SIZE, 16, 0); | |
2458 | xhci->medium_streams_pool = | |
2459 | dma_pool_create("xHCI 1KB stream ctx arrays", | |
2460 | dev, MEDIUM_STREAM_ARRAY_SIZE, 16, 0); | |
2461 | /* Any stream context array bigger than MEDIUM_STREAM_ARRAY_SIZE | |
22d45f01 | 2462 | * will be allocated with dma_alloc_coherent() |
8df75f42 SS |
2463 | */ |
2464 | ||
2465 | if (!xhci->small_streams_pool || !xhci->medium_streams_pool) | |
2466 | goto fail; | |
2467 | ||
0ebbab37 | 2468 | /* Set up the command ring to have one segments for now. */ |
f9c589e1 | 2469 | xhci->cmd_ring = xhci_ring_alloc(xhci, 1, 1, TYPE_COMMAND, 0, flags); |
0ebbab37 SS |
2470 | if (!xhci->cmd_ring) |
2471 | goto fail; | |
d195fcff XR |
2472 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2473 | "Allocated command ring at %p", xhci->cmd_ring); | |
2474 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "First segment DMA is 0x%llx", | |
700e2052 | 2475 | (unsigned long long)xhci->cmd_ring->first_seg->dma); |
0ebbab37 SS |
2476 | |
2477 | /* Set the address in the Command Ring Control register */ | |
f7b2e403 | 2478 | val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring); |
8e595a5d SS |
2479 | val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) | |
2480 | (xhci->cmd_ring->first_seg->dma & (u64) ~CMD_RING_RSVD_BITS) | | |
0ebbab37 | 2481 | xhci->cmd_ring->cycle_state; |
d195fcff XR |
2482 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2483 | "// Setting command ring address to 0x%x", val); | |
477632df | 2484 | xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring); |
0ebbab37 SS |
2485 | xhci_dbg_cmd_ptrs(xhci); |
2486 | ||
dbc33303 SS |
2487 | xhci->lpm_command = xhci_alloc_command(xhci, true, true, flags); |
2488 | if (!xhci->lpm_command) | |
2489 | goto fail; | |
2490 | ||
2491 | /* Reserve one command ring TRB for disabling LPM. | |
2492 | * Since the USB core grabs the shared usb_bus bandwidth mutex before | |
2493 | * disabling LPM, we only need to reserve one TRB for all devices. | |
2494 | */ | |
2495 | xhci->cmd_ring_reserved_trbs++; | |
2496 | ||
b0ba9720 | 2497 | val = readl(&xhci->cap_regs->db_off); |
0ebbab37 | 2498 | val &= DBOFF_MASK; |
d195fcff XR |
2499 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2500 | "// Doorbell array is located at offset 0x%x" | |
2501 | " from cap regs base addr", val); | |
c50a00f8 | 2502 | xhci->dba = (void __iomem *) xhci->cap_regs + val; |
0ebbab37 SS |
2503 | xhci_dbg_regs(xhci); |
2504 | xhci_print_run_regs(xhci); | |
2505 | /* Set ir_set to interrupt register set 0 */ | |
c50a00f8 | 2506 | xhci->ir_set = &xhci->run_regs->ir_set[0]; |
0ebbab37 SS |
2507 | |
2508 | /* | |
2509 | * Event ring setup: Allocate a normal ring, but also setup | |
2510 | * the event ring segment table (ERST). Section 4.9.3. | |
2511 | */ | |
d195fcff | 2512 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Allocating event ring"); |
186a7ef1 | 2513 | xhci->event_ring = xhci_ring_alloc(xhci, ERST_NUM_SEGS, 1, TYPE_EVENT, |
f9c589e1 | 2514 | 0, flags); |
0ebbab37 SS |
2515 | if (!xhci->event_ring) |
2516 | goto fail; | |
4daf9df5 | 2517 | if (xhci_check_trb_in_td_math(xhci) < 0) |
6648f29d | 2518 | goto fail; |
0ebbab37 | 2519 | |
22d45f01 SAS |
2520 | xhci->erst.entries = dma_alloc_coherent(dev, |
2521 | sizeof(struct xhci_erst_entry) * ERST_NUM_SEGS, &dma, | |
c95a9f83 | 2522 | flags); |
0ebbab37 SS |
2523 | if (!xhci->erst.entries) |
2524 | goto fail; | |
d195fcff XR |
2525 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2526 | "// Allocated event ring segment table at 0x%llx", | |
700e2052 | 2527 | (unsigned long long)dma); |
0ebbab37 SS |
2528 | |
2529 | memset(xhci->erst.entries, 0, sizeof(struct xhci_erst_entry)*ERST_NUM_SEGS); | |
2530 | xhci->erst.num_entries = ERST_NUM_SEGS; | |
2531 | xhci->erst.erst_dma_addr = dma; | |
d195fcff XR |
2532 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2533 | "Set ERST to 0; private num segs = %i, virt addr = %p, dma addr = 0x%llx", | |
0ebbab37 | 2534 | xhci->erst.num_entries, |
700e2052 GKH |
2535 | xhci->erst.entries, |
2536 | (unsigned long long)xhci->erst.erst_dma_addr); | |
0ebbab37 SS |
2537 | |
2538 | /* set ring base address and size for each segment table entry */ | |
2539 | for (val = 0, seg = xhci->event_ring->first_seg; val < ERST_NUM_SEGS; val++) { | |
2540 | struct xhci_erst_entry *entry = &xhci->erst.entries[val]; | |
28ccd296 ME |
2541 | entry->seg_addr = cpu_to_le64(seg->dma); |
2542 | entry->seg_size = cpu_to_le32(TRBS_PER_SEGMENT); | |
0ebbab37 SS |
2543 | entry->rsvd = 0; |
2544 | seg = seg->next; | |
2545 | } | |
2546 | ||
2547 | /* set ERST count with the number of entries in the segment table */ | |
b0ba9720 | 2548 | val = readl(&xhci->ir_set->erst_size); |
0ebbab37 SS |
2549 | val &= ERST_SIZE_MASK; |
2550 | val |= ERST_NUM_SEGS; | |
d195fcff XR |
2551 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2552 | "// Write ERST size = %i to ir_set 0 (some bits preserved)", | |
0ebbab37 | 2553 | val); |
204b7793 | 2554 | writel(val, &xhci->ir_set->erst_size); |
0ebbab37 | 2555 | |
d195fcff XR |
2556 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2557 | "// Set ERST entries to point to event ring."); | |
0ebbab37 | 2558 | /* set the segment table base address */ |
d195fcff XR |
2559 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2560 | "// Set ERST base address for ir_set 0 = 0x%llx", | |
700e2052 | 2561 | (unsigned long long)xhci->erst.erst_dma_addr); |
f7b2e403 | 2562 | val_64 = xhci_read_64(xhci, &xhci->ir_set->erst_base); |
8e595a5d SS |
2563 | val_64 &= ERST_PTR_MASK; |
2564 | val_64 |= (xhci->erst.erst_dma_addr & (u64) ~ERST_PTR_MASK); | |
477632df | 2565 | xhci_write_64(xhci, val_64, &xhci->ir_set->erst_base); |
0ebbab37 SS |
2566 | |
2567 | /* Set the event ring dequeue address */ | |
23e3be11 | 2568 | xhci_set_hc_event_deq(xhci); |
d195fcff XR |
2569 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2570 | "Wrote ERST address to ir_set 0."); | |
09ece30e | 2571 | xhci_print_ir_set(xhci, 0); |
0ebbab37 SS |
2572 | |
2573 | /* | |
2574 | * XXX: Might need to set the Interrupter Moderation Register to | |
2575 | * something other than the default (~1ms minimum between interrupts). | |
2576 | * See section 5.5.1.2. | |
2577 | */ | |
98871e94 | 2578 | for (i = 0; i < MAX_HC_SLOTS; i++) |
326b4810 | 2579 | xhci->devs[i] = NULL; |
98871e94 | 2580 | for (i = 0; i < USB_MAXCHILDREN; i++) { |
20b67cf5 | 2581 | xhci->bus_state[0].resume_done[i] = 0; |
f6ff0ac8 | 2582 | xhci->bus_state[1].resume_done[i] = 0; |
8b3d4570 SS |
2583 | /* Only the USB 2.0 completions will ever be used. */ |
2584 | init_completion(&xhci->bus_state[1].rexit_done[i]); | |
f6ff0ac8 | 2585 | } |
66d4eadd | 2586 | |
254c80a3 JY |
2587 | if (scratchpad_alloc(xhci, flags)) |
2588 | goto fail; | |
da6699ce SS |
2589 | if (xhci_setup_port_arrays(xhci, flags)) |
2590 | goto fail; | |
254c80a3 | 2591 | |
623bef9e SS |
2592 | /* Enable USB 3.0 device notifications for function remote wake, which |
2593 | * is necessary for allowing USB 3.0 devices to do remote wakeup from | |
2594 | * U3 (device suspend). | |
2595 | */ | |
b0ba9720 | 2596 | temp = readl(&xhci->op_regs->dev_notification); |
623bef9e SS |
2597 | temp &= ~DEV_NOTE_MASK; |
2598 | temp |= DEV_NOTE_FWAKE; | |
204b7793 | 2599 | writel(temp, &xhci->op_regs->dev_notification); |
623bef9e | 2600 | |
66d4eadd | 2601 | return 0; |
254c80a3 | 2602 | |
66d4eadd SS |
2603 | fail: |
2604 | xhci_warn(xhci, "Couldn't initialize memory\n"); | |
159e1fcc SS |
2605 | xhci_halt(xhci); |
2606 | xhci_reset(xhci); | |
66d4eadd SS |
2607 | xhci_mem_cleanup(xhci); |
2608 | return -ENOMEM; | |
2609 | } |