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Commit | Line | Data |
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66d4eadd SS |
1 | /* |
2 | * xHCI host controller driver | |
3 | * | |
4 | * Copyright (C) 2008 Intel Corp. | |
5 | * | |
6 | * Author: Sarah Sharp | |
7 | * Some code borrowed from the Linux EHCI driver. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | * for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software Foundation, | |
20 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
23 | #include <linux/usb.h> | |
0ebbab37 | 24 | #include <linux/pci.h> |
5a0e3ad6 | 25 | #include <linux/slab.h> |
527c6d7f | 26 | #include <linux/dmapool.h> |
008eb957 | 27 | #include <linux/dma-mapping.h> |
66d4eadd SS |
28 | |
29 | #include "xhci.h" | |
3a7fa5be | 30 | #include "xhci-trace.h" |
66d4eadd | 31 | |
0ebbab37 SS |
32 | /* |
33 | * Allocates a generic ring segment from the ring pool, sets the dma address, | |
34 | * initializes the segment to zero, and sets the private next pointer to NULL. | |
35 | * | |
36 | * Section 4.11.1.1: | |
37 | * "All components of all Command and Transfer TRBs shall be initialized to '0'" | |
38 | */ | |
186a7ef1 | 39 | static struct xhci_segment *xhci_segment_alloc(struct xhci_hcd *xhci, |
f9c589e1 MN |
40 | unsigned int cycle_state, |
41 | unsigned int max_packet, | |
42 | gfp_t flags) | |
0ebbab37 SS |
43 | { |
44 | struct xhci_segment *seg; | |
45 | dma_addr_t dma; | |
186a7ef1 | 46 | int i; |
0ebbab37 SS |
47 | |
48 | seg = kzalloc(sizeof *seg, flags); | |
49 | if (!seg) | |
326b4810 | 50 | return NULL; |
0ebbab37 | 51 | |
84c1eeb0 | 52 | seg->trbs = dma_pool_zalloc(xhci->segment_pool, flags, &dma); |
0ebbab37 SS |
53 | if (!seg->trbs) { |
54 | kfree(seg); | |
326b4810 | 55 | return NULL; |
0ebbab37 | 56 | } |
0ebbab37 | 57 | |
f9c589e1 | 58 | if (max_packet) { |
5db851cf | 59 | seg->bounce_buf = kzalloc(max_packet, flags); |
f9c589e1 MN |
60 | if (!seg->bounce_buf) { |
61 | dma_pool_free(xhci->segment_pool, seg->trbs, dma); | |
62 | kfree(seg); | |
63 | return NULL; | |
64 | } | |
65 | } | |
186a7ef1 AX |
66 | /* If the cycle state is 0, set the cycle bit to 1 for all the TRBs */ |
67 | if (cycle_state == 0) { | |
68 | for (i = 0; i < TRBS_PER_SEGMENT; i++) | |
58719487 | 69 | seg->trbs[i].link.control |= cpu_to_le32(TRB_CYCLE); |
186a7ef1 | 70 | } |
0ebbab37 SS |
71 | seg->dma = dma; |
72 | seg->next = NULL; | |
73 | ||
74 | return seg; | |
75 | } | |
76 | ||
77 | static void xhci_segment_free(struct xhci_hcd *xhci, struct xhci_segment *seg) | |
78 | { | |
0ebbab37 | 79 | if (seg->trbs) { |
0ebbab37 SS |
80 | dma_pool_free(xhci->segment_pool, seg->trbs, seg->dma); |
81 | seg->trbs = NULL; | |
82 | } | |
f9c589e1 | 83 | kfree(seg->bounce_buf); |
0ebbab37 SS |
84 | kfree(seg); |
85 | } | |
86 | ||
70d43601 AX |
87 | static void xhci_free_segments_for_ring(struct xhci_hcd *xhci, |
88 | struct xhci_segment *first) | |
89 | { | |
90 | struct xhci_segment *seg; | |
91 | ||
92 | seg = first->next; | |
93 | while (seg != first) { | |
94 | struct xhci_segment *next = seg->next; | |
95 | xhci_segment_free(xhci, seg); | |
96 | seg = next; | |
97 | } | |
98 | xhci_segment_free(xhci, first); | |
99 | } | |
100 | ||
0ebbab37 SS |
101 | /* |
102 | * Make the prev segment point to the next segment. | |
103 | * | |
104 | * Change the last TRB in the prev segment to be a Link TRB which points to the | |
105 | * DMA address of the next segment. The caller needs to set any Link TRB | |
106 | * related flags, such as End TRB, Toggle Cycle, and no snoop. | |
107 | */ | |
108 | static void xhci_link_segments(struct xhci_hcd *xhci, struct xhci_segment *prev, | |
3b72fca0 | 109 | struct xhci_segment *next, enum xhci_ring_type type) |
0ebbab37 SS |
110 | { |
111 | u32 val; | |
112 | ||
113 | if (!prev || !next) | |
114 | return; | |
115 | prev->next = next; | |
3b72fca0 | 116 | if (type != TYPE_EVENT) { |
f5960b69 ME |
117 | prev->trbs[TRBS_PER_SEGMENT-1].link.segment_ptr = |
118 | cpu_to_le64(next->dma); | |
0ebbab37 SS |
119 | |
120 | /* Set the last TRB in the segment to have a TRB type ID of Link TRB */ | |
28ccd296 | 121 | val = le32_to_cpu(prev->trbs[TRBS_PER_SEGMENT-1].link.control); |
0ebbab37 SS |
122 | val &= ~TRB_TYPE_BITMASK; |
123 | val |= TRB_TYPE(TRB_LINK); | |
b0567b3f | 124 | /* Always set the chain bit with 0.95 hardware */ |
7e393a83 AX |
125 | /* Set chain bit for isoc rings on AMD 0.96 host */ |
126 | if (xhci_link_trb_quirk(xhci) || | |
3b72fca0 AX |
127 | (type == TYPE_ISOC && |
128 | (xhci->quirks & XHCI_AMD_0x96_HOST))) | |
b0567b3f | 129 | val |= TRB_CHAIN; |
28ccd296 | 130 | prev->trbs[TRBS_PER_SEGMENT-1].link.control = cpu_to_le32(val); |
0ebbab37 | 131 | } |
0ebbab37 SS |
132 | } |
133 | ||
8dfec614 AX |
134 | /* |
135 | * Link the ring to the new segments. | |
136 | * Set Toggle Cycle for the new ring if needed. | |
137 | */ | |
138 | static void xhci_link_rings(struct xhci_hcd *xhci, struct xhci_ring *ring, | |
139 | struct xhci_segment *first, struct xhci_segment *last, | |
140 | unsigned int num_segs) | |
141 | { | |
142 | struct xhci_segment *next; | |
143 | ||
144 | if (!ring || !first || !last) | |
145 | return; | |
146 | ||
147 | next = ring->enq_seg->next; | |
148 | xhci_link_segments(xhci, ring->enq_seg, first, ring->type); | |
149 | xhci_link_segments(xhci, last, next, ring->type); | |
150 | ring->num_segs += num_segs; | |
151 | ring->num_trbs_free += (TRBS_PER_SEGMENT - 1) * num_segs; | |
152 | ||
153 | if (ring->type != TYPE_EVENT && ring->enq_seg == ring->last_seg) { | |
154 | ring->last_seg->trbs[TRBS_PER_SEGMENT-1].link.control | |
155 | &= ~cpu_to_le32(LINK_TOGGLE); | |
156 | last->trbs[TRBS_PER_SEGMENT-1].link.control | |
157 | |= cpu_to_le32(LINK_TOGGLE); | |
158 | ring->last_seg = last; | |
159 | } | |
160 | } | |
161 | ||
15341303 GH |
162 | /* |
163 | * We need a radix tree for mapping physical addresses of TRBs to which stream | |
164 | * ID they belong to. We need to do this because the host controller won't tell | |
165 | * us which stream ring the TRB came from. We could store the stream ID in an | |
166 | * event data TRB, but that doesn't help us for the cancellation case, since the | |
167 | * endpoint may stop before it reaches that event data TRB. | |
168 | * | |
169 | * The radix tree maps the upper portion of the TRB DMA address to a ring | |
170 | * segment that has the same upper portion of DMA addresses. For example, say I | |
84c1e40f | 171 | * have segments of size 1KB, that are always 1KB aligned. A segment may |
15341303 GH |
172 | * start at 0x10c91000 and end at 0x10c913f0. If I use the upper 10 bits, the |
173 | * key to the stream ID is 0x43244. I can use the DMA address of the TRB to | |
174 | * pass the radix tree a key to get the right stream ID: | |
175 | * | |
176 | * 0x10c90fff >> 10 = 0x43243 | |
177 | * 0x10c912c0 >> 10 = 0x43244 | |
178 | * 0x10c91400 >> 10 = 0x43245 | |
179 | * | |
180 | * Obviously, only those TRBs with DMA addresses that are within the segment | |
181 | * will make the radix tree return the stream ID for that ring. | |
182 | * | |
183 | * Caveats for the radix tree: | |
184 | * | |
185 | * The radix tree uses an unsigned long as a key pair. On 32-bit systems, an | |
186 | * unsigned long will be 32-bits; on a 64-bit system an unsigned long will be | |
187 | * 64-bits. Since we only request 32-bit DMA addresses, we can use that as the | |
188 | * key on 32-bit or 64-bit systems (it would also be fine if we asked for 64-bit | |
189 | * PCI DMA addresses on a 64-bit system). There might be a problem on 32-bit | |
190 | * extended systems (where the DMA address can be bigger than 32-bits), | |
191 | * if we allow the PCI dma mask to be bigger than 32-bits. So don't do that. | |
192 | */ | |
d5734223 SS |
193 | static int xhci_insert_segment_mapping(struct radix_tree_root *trb_address_map, |
194 | struct xhci_ring *ring, | |
195 | struct xhci_segment *seg, | |
196 | gfp_t mem_flags) | |
15341303 | 197 | { |
15341303 GH |
198 | unsigned long key; |
199 | int ret; | |
200 | ||
d5734223 SS |
201 | key = (unsigned long)(seg->dma >> TRB_SEGMENT_SHIFT); |
202 | /* Skip any segments that were already added. */ | |
203 | if (radix_tree_lookup(trb_address_map, key)) | |
15341303 GH |
204 | return 0; |
205 | ||
d5734223 SS |
206 | ret = radix_tree_maybe_preload(mem_flags); |
207 | if (ret) | |
208 | return ret; | |
209 | ret = radix_tree_insert(trb_address_map, | |
210 | key, ring); | |
211 | radix_tree_preload_end(); | |
212 | return ret; | |
213 | } | |
15341303 | 214 | |
d5734223 SS |
215 | static void xhci_remove_segment_mapping(struct radix_tree_root *trb_address_map, |
216 | struct xhci_segment *seg) | |
217 | { | |
218 | unsigned long key; | |
219 | ||
220 | key = (unsigned long)(seg->dma >> TRB_SEGMENT_SHIFT); | |
221 | if (radix_tree_lookup(trb_address_map, key)) | |
222 | radix_tree_delete(trb_address_map, key); | |
223 | } | |
224 | ||
225 | static int xhci_update_stream_segment_mapping( | |
226 | struct radix_tree_root *trb_address_map, | |
227 | struct xhci_ring *ring, | |
228 | struct xhci_segment *first_seg, | |
229 | struct xhci_segment *last_seg, | |
230 | gfp_t mem_flags) | |
231 | { | |
232 | struct xhci_segment *seg; | |
233 | struct xhci_segment *failed_seg; | |
234 | int ret; | |
235 | ||
236 | if (WARN_ON_ONCE(trb_address_map == NULL)) | |
237 | return 0; | |
238 | ||
239 | seg = first_seg; | |
240 | do { | |
241 | ret = xhci_insert_segment_mapping(trb_address_map, | |
242 | ring, seg, mem_flags); | |
15341303 | 243 | if (ret) |
d5734223 SS |
244 | goto remove_streams; |
245 | if (seg == last_seg) | |
246 | return 0; | |
15341303 | 247 | seg = seg->next; |
d5734223 | 248 | } while (seg != first_seg); |
15341303 GH |
249 | |
250 | return 0; | |
d5734223 SS |
251 | |
252 | remove_streams: | |
253 | failed_seg = seg; | |
254 | seg = first_seg; | |
255 | do { | |
256 | xhci_remove_segment_mapping(trb_address_map, seg); | |
257 | if (seg == failed_seg) | |
258 | return ret; | |
259 | seg = seg->next; | |
260 | } while (seg != first_seg); | |
261 | ||
262 | return ret; | |
15341303 GH |
263 | } |
264 | ||
265 | static void xhci_remove_stream_mapping(struct xhci_ring *ring) | |
266 | { | |
267 | struct xhci_segment *seg; | |
15341303 GH |
268 | |
269 | if (WARN_ON_ONCE(ring->trb_address_map == NULL)) | |
270 | return; | |
271 | ||
272 | seg = ring->first_seg; | |
273 | do { | |
d5734223 | 274 | xhci_remove_segment_mapping(ring->trb_address_map, seg); |
15341303 GH |
275 | seg = seg->next; |
276 | } while (seg != ring->first_seg); | |
277 | } | |
278 | ||
d5734223 SS |
279 | static int xhci_update_stream_mapping(struct xhci_ring *ring, gfp_t mem_flags) |
280 | { | |
281 | return xhci_update_stream_segment_mapping(ring->trb_address_map, ring, | |
282 | ring->first_seg, ring->last_seg, mem_flags); | |
283 | } | |
284 | ||
0ebbab37 | 285 | /* XXX: Do we need the hcd structure in all these functions? */ |
f94e0186 | 286 | void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring) |
0ebbab37 | 287 | { |
0e6c7f74 | 288 | if (!ring) |
0ebbab37 | 289 | return; |
70d43601 | 290 | |
b2d6edbb LB |
291 | trace_xhci_ring_free(ring); |
292 | ||
15341303 GH |
293 | if (ring->first_seg) { |
294 | if (ring->type == TYPE_STREAM) | |
295 | xhci_remove_stream_mapping(ring); | |
70d43601 | 296 | xhci_free_segments_for_ring(xhci, ring->first_seg); |
15341303 | 297 | } |
70d43601 | 298 | |
0ebbab37 SS |
299 | kfree(ring); |
300 | } | |
301 | ||
186a7ef1 AX |
302 | static void xhci_initialize_ring_info(struct xhci_ring *ring, |
303 | unsigned int cycle_state) | |
74f9fe21 SS |
304 | { |
305 | /* The ring is empty, so the enqueue pointer == dequeue pointer */ | |
306 | ring->enqueue = ring->first_seg->trbs; | |
307 | ring->enq_seg = ring->first_seg; | |
308 | ring->dequeue = ring->enqueue; | |
309 | ring->deq_seg = ring->first_seg; | |
310 | /* The ring is initialized to 0. The producer must write 1 to the cycle | |
311 | * bit to handover ownership of the TRB, so PCS = 1. The consumer must | |
312 | * compare CCS to the cycle bit to check ownership, so CCS = 1. | |
186a7ef1 AX |
313 | * |
314 | * New rings are initialized with cycle state equal to 1; if we are | |
315 | * handling ring expansion, set the cycle state equal to the old ring. | |
74f9fe21 | 316 | */ |
186a7ef1 | 317 | ring->cycle_state = cycle_state; |
b008df60 AX |
318 | |
319 | /* | |
320 | * Each segment has a link TRB, and leave an extra TRB for SW | |
321 | * accounting purpose | |
322 | */ | |
323 | ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1; | |
74f9fe21 SS |
324 | } |
325 | ||
70d43601 AX |
326 | /* Allocate segments and link them for a ring */ |
327 | static int xhci_alloc_segments_for_ring(struct xhci_hcd *xhci, | |
328 | struct xhci_segment **first, struct xhci_segment **last, | |
186a7ef1 | 329 | unsigned int num_segs, unsigned int cycle_state, |
f9c589e1 | 330 | enum xhci_ring_type type, unsigned int max_packet, gfp_t flags) |
70d43601 AX |
331 | { |
332 | struct xhci_segment *prev; | |
333 | ||
f9c589e1 | 334 | prev = xhci_segment_alloc(xhci, cycle_state, max_packet, flags); |
70d43601 AX |
335 | if (!prev) |
336 | return -ENOMEM; | |
337 | num_segs--; | |
338 | ||
339 | *first = prev; | |
340 | while (num_segs > 0) { | |
341 | struct xhci_segment *next; | |
342 | ||
f9c589e1 | 343 | next = xhci_segment_alloc(xhci, cycle_state, max_packet, flags); |
70d43601 | 344 | if (!next) { |
68e5254a JW |
345 | prev = *first; |
346 | while (prev) { | |
347 | next = prev->next; | |
348 | xhci_segment_free(xhci, prev); | |
349 | prev = next; | |
350 | } | |
70d43601 AX |
351 | return -ENOMEM; |
352 | } | |
353 | xhci_link_segments(xhci, prev, next, type); | |
354 | ||
355 | prev = next; | |
356 | num_segs--; | |
357 | } | |
358 | xhci_link_segments(xhci, prev, *first, type); | |
359 | *last = prev; | |
360 | ||
361 | return 0; | |
362 | } | |
363 | ||
0ebbab37 SS |
364 | /** |
365 | * Create a new ring with zero or more segments. | |
366 | * | |
367 | * Link each segment together into a ring. | |
368 | * Set the end flag and the cycle toggle bit on the last segment. | |
369 | * See section 4.9.1 and figures 15 and 16. | |
370 | */ | |
371 | static struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci, | |
186a7ef1 | 372 | unsigned int num_segs, unsigned int cycle_state, |
f9c589e1 | 373 | enum xhci_ring_type type, unsigned int max_packet, gfp_t flags) |
0ebbab37 SS |
374 | { |
375 | struct xhci_ring *ring; | |
70d43601 | 376 | int ret; |
0ebbab37 SS |
377 | |
378 | ring = kzalloc(sizeof *(ring), flags); | |
0ebbab37 | 379 | if (!ring) |
326b4810 | 380 | return NULL; |
0ebbab37 | 381 | |
3fe4fe08 | 382 | ring->num_segs = num_segs; |
f9c589e1 | 383 | ring->bounce_buf_len = max_packet; |
d0e96f5a | 384 | INIT_LIST_HEAD(&ring->td_list); |
3b72fca0 | 385 | ring->type = type; |
0ebbab37 SS |
386 | if (num_segs == 0) |
387 | return ring; | |
388 | ||
70d43601 | 389 | ret = xhci_alloc_segments_for_ring(xhci, &ring->first_seg, |
f9c589e1 MN |
390 | &ring->last_seg, num_segs, cycle_state, type, |
391 | max_packet, flags); | |
70d43601 | 392 | if (ret) |
0ebbab37 | 393 | goto fail; |
0ebbab37 | 394 | |
3b72fca0 AX |
395 | /* Only event ring does not use link TRB */ |
396 | if (type != TYPE_EVENT) { | |
0ebbab37 | 397 | /* See section 4.9.2.1 and 6.4.4.1 */ |
70d43601 | 398 | ring->last_seg->trbs[TRBS_PER_SEGMENT - 1].link.control |= |
f5960b69 | 399 | cpu_to_le32(LINK_TOGGLE); |
0ebbab37 | 400 | } |
186a7ef1 | 401 | xhci_initialize_ring_info(ring, cycle_state); |
b2d6edbb | 402 | trace_xhci_ring_alloc(ring); |
0ebbab37 SS |
403 | return ring; |
404 | ||
405 | fail: | |
68e5254a | 406 | kfree(ring); |
326b4810 | 407 | return NULL; |
0ebbab37 SS |
408 | } |
409 | ||
412566bd SS |
410 | void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci, |
411 | struct xhci_virt_device *virt_dev, | |
412 | unsigned int ep_index) | |
413 | { | |
414 | int rings_cached; | |
415 | ||
416 | rings_cached = virt_dev->num_rings_cached; | |
417 | if (rings_cached < XHCI_MAX_RINGS_CACHED) { | |
412566bd SS |
418 | virt_dev->ring_cache[rings_cached] = |
419 | virt_dev->eps[ep_index].ring; | |
30f89ca0 | 420 | virt_dev->num_rings_cached++; |
412566bd SS |
421 | xhci_dbg(xhci, "Cached old ring, " |
422 | "%d ring%s cached\n", | |
30f89ca0 SS |
423 | virt_dev->num_rings_cached, |
424 | (virt_dev->num_rings_cached > 1) ? "s" : ""); | |
412566bd SS |
425 | } else { |
426 | xhci_ring_free(xhci, virt_dev->eps[ep_index].ring); | |
427 | xhci_dbg(xhci, "Ring cache full (%d rings), " | |
428 | "freeing ring\n", | |
429 | virt_dev->num_rings_cached); | |
430 | } | |
431 | virt_dev->eps[ep_index].ring = NULL; | |
432 | } | |
433 | ||
74f9fe21 SS |
434 | /* Zero an endpoint ring (except for link TRBs) and move the enqueue and dequeue |
435 | * pointers to the beginning of the ring. | |
436 | */ | |
437 | static void xhci_reinit_cached_ring(struct xhci_hcd *xhci, | |
186a7ef1 AX |
438 | struct xhci_ring *ring, unsigned int cycle_state, |
439 | enum xhci_ring_type type) | |
74f9fe21 SS |
440 | { |
441 | struct xhci_segment *seg = ring->first_seg; | |
186a7ef1 AX |
442 | int i; |
443 | ||
74f9fe21 SS |
444 | do { |
445 | memset(seg->trbs, 0, | |
446 | sizeof(union xhci_trb)*TRBS_PER_SEGMENT); | |
186a7ef1 AX |
447 | if (cycle_state == 0) { |
448 | for (i = 0; i < TRBS_PER_SEGMENT; i++) | |
58719487 XR |
449 | seg->trbs[i].link.control |= |
450 | cpu_to_le32(TRB_CYCLE); | |
186a7ef1 | 451 | } |
74f9fe21 | 452 | /* All endpoint rings have link TRBs */ |
3b72fca0 | 453 | xhci_link_segments(xhci, seg, seg->next, type); |
74f9fe21 SS |
454 | seg = seg->next; |
455 | } while (seg != ring->first_seg); | |
3b72fca0 | 456 | ring->type = type; |
186a7ef1 | 457 | xhci_initialize_ring_info(ring, cycle_state); |
74f9fe21 SS |
458 | /* td list should be empty since all URBs have been cancelled, |
459 | * but just in case... | |
460 | */ | |
461 | INIT_LIST_HEAD(&ring->td_list); | |
462 | } | |
463 | ||
8dfec614 AX |
464 | /* |
465 | * Expand an existing ring. | |
466 | * Look for a cached ring or allocate a new ring which has same segment numbers | |
467 | * and link the two rings. | |
468 | */ | |
469 | int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring, | |
470 | unsigned int num_trbs, gfp_t flags) | |
471 | { | |
472 | struct xhci_segment *first; | |
473 | struct xhci_segment *last; | |
474 | unsigned int num_segs; | |
475 | unsigned int num_segs_needed; | |
476 | int ret; | |
477 | ||
478 | num_segs_needed = (num_trbs + (TRBS_PER_SEGMENT - 1) - 1) / | |
479 | (TRBS_PER_SEGMENT - 1); | |
480 | ||
481 | /* Allocate number of segments we needed, or double the ring size */ | |
482 | num_segs = ring->num_segs > num_segs_needed ? | |
483 | ring->num_segs : num_segs_needed; | |
484 | ||
485 | ret = xhci_alloc_segments_for_ring(xhci, &first, &last, | |
f9c589e1 MN |
486 | num_segs, ring->cycle_state, ring->type, |
487 | ring->bounce_buf_len, flags); | |
8dfec614 AX |
488 | if (ret) |
489 | return -ENOMEM; | |
490 | ||
d5734223 SS |
491 | if (ring->type == TYPE_STREAM) |
492 | ret = xhci_update_stream_segment_mapping(ring->trb_address_map, | |
493 | ring, first, last, flags); | |
494 | if (ret) { | |
495 | struct xhci_segment *next; | |
496 | do { | |
497 | next = first->next; | |
498 | xhci_segment_free(xhci, first); | |
499 | if (first == last) | |
500 | break; | |
501 | first = next; | |
502 | } while (true); | |
503 | return ret; | |
504 | } | |
505 | ||
8dfec614 | 506 | xhci_link_rings(xhci, ring, first, last, num_segs); |
b2d6edbb | 507 | trace_xhci_ring_expansion(ring); |
68ffb011 XR |
508 | xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion, |
509 | "ring expansion succeed, now has %d segments", | |
8dfec614 AX |
510 | ring->num_segs); |
511 | ||
512 | return 0; | |
513 | } | |
514 | ||
d115b048 JY |
515 | #define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32) |
516 | ||
326b4810 | 517 | static struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci, |
d115b048 JY |
518 | int type, gfp_t flags) |
519 | { | |
29f9d54b SS |
520 | struct xhci_container_ctx *ctx; |
521 | ||
522 | if ((type != XHCI_CTX_TYPE_DEVICE) && (type != XHCI_CTX_TYPE_INPUT)) | |
523 | return NULL; | |
524 | ||
525 | ctx = kzalloc(sizeof(*ctx), flags); | |
d115b048 JY |
526 | if (!ctx) |
527 | return NULL; | |
528 | ||
d115b048 JY |
529 | ctx->type = type; |
530 | ctx->size = HCC_64BYTE_CONTEXT(xhci->hcc_params) ? 2048 : 1024; | |
531 | if (type == XHCI_CTX_TYPE_INPUT) | |
532 | ctx->size += CTX_SIZE(xhci->hcc_params); | |
533 | ||
84c1eeb0 | 534 | ctx->bytes = dma_pool_zalloc(xhci->device_pool, flags, &ctx->dma); |
025f880c MN |
535 | if (!ctx->bytes) { |
536 | kfree(ctx); | |
537 | return NULL; | |
538 | } | |
d115b048 JY |
539 | return ctx; |
540 | } | |
541 | ||
326b4810 | 542 | static void xhci_free_container_ctx(struct xhci_hcd *xhci, |
d115b048 JY |
543 | struct xhci_container_ctx *ctx) |
544 | { | |
a1d78c16 SS |
545 | if (!ctx) |
546 | return; | |
d115b048 JY |
547 | dma_pool_free(xhci->device_pool, ctx->bytes, ctx->dma); |
548 | kfree(ctx); | |
549 | } | |
550 | ||
4daf9df5 | 551 | struct xhci_input_control_ctx *xhci_get_input_control_ctx( |
d115b048 JY |
552 | struct xhci_container_ctx *ctx) |
553 | { | |
92f8e767 SS |
554 | if (ctx->type != XHCI_CTX_TYPE_INPUT) |
555 | return NULL; | |
556 | ||
d115b048 JY |
557 | return (struct xhci_input_control_ctx *)ctx->bytes; |
558 | } | |
559 | ||
560 | struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, | |
561 | struct xhci_container_ctx *ctx) | |
562 | { | |
563 | if (ctx->type == XHCI_CTX_TYPE_DEVICE) | |
564 | return (struct xhci_slot_ctx *)ctx->bytes; | |
565 | ||
566 | return (struct xhci_slot_ctx *) | |
567 | (ctx->bytes + CTX_SIZE(xhci->hcc_params)); | |
568 | } | |
569 | ||
570 | struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, | |
571 | struct xhci_container_ctx *ctx, | |
572 | unsigned int ep_index) | |
573 | { | |
574 | /* increment ep index by offset of start of ep ctx array */ | |
575 | ep_index++; | |
576 | if (ctx->type == XHCI_CTX_TYPE_INPUT) | |
577 | ep_index++; | |
578 | ||
579 | return (struct xhci_ep_ctx *) | |
580 | (ctx->bytes + (ep_index * CTX_SIZE(xhci->hcc_params))); | |
581 | } | |
582 | ||
8df75f42 SS |
583 | |
584 | /***************** Streams structures manipulation *************************/ | |
585 | ||
8212a49d | 586 | static void xhci_free_stream_ctx(struct xhci_hcd *xhci, |
8df75f42 SS |
587 | unsigned int num_stream_ctxs, |
588 | struct xhci_stream_ctx *stream_ctx, dma_addr_t dma) | |
589 | { | |
4c39d4b9 | 590 | struct device *dev = xhci_to_hcd(xhci)->self.sysdev; |
ee4aa54b | 591 | size_t size = sizeof(struct xhci_stream_ctx) * num_stream_ctxs; |
8df75f42 | 592 | |
ee4aa54b HG |
593 | if (size > MEDIUM_STREAM_ARRAY_SIZE) |
594 | dma_free_coherent(dev, size, | |
8df75f42 | 595 | stream_ctx, dma); |
ee4aa54b | 596 | else if (size <= SMALL_STREAM_ARRAY_SIZE) |
8df75f42 SS |
597 | return dma_pool_free(xhci->small_streams_pool, |
598 | stream_ctx, dma); | |
599 | else | |
600 | return dma_pool_free(xhci->medium_streams_pool, | |
601 | stream_ctx, dma); | |
602 | } | |
603 | ||
604 | /* | |
605 | * The stream context array for each endpoint with bulk streams enabled can | |
606 | * vary in size, based on: | |
607 | * - how many streams the endpoint supports, | |
608 | * - the maximum primary stream array size the host controller supports, | |
609 | * - and how many streams the device driver asks for. | |
610 | * | |
611 | * The stream context array must be a power of 2, and can be as small as | |
612 | * 64 bytes or as large as 1MB. | |
613 | */ | |
8212a49d | 614 | static struct xhci_stream_ctx *xhci_alloc_stream_ctx(struct xhci_hcd *xhci, |
8df75f42 SS |
615 | unsigned int num_stream_ctxs, dma_addr_t *dma, |
616 | gfp_t mem_flags) | |
617 | { | |
4c39d4b9 | 618 | struct device *dev = xhci_to_hcd(xhci)->self.sysdev; |
ee4aa54b | 619 | size_t size = sizeof(struct xhci_stream_ctx) * num_stream_ctxs; |
8df75f42 | 620 | |
ee4aa54b HG |
621 | if (size > MEDIUM_STREAM_ARRAY_SIZE) |
622 | return dma_alloc_coherent(dev, size, | |
22d45f01 | 623 | dma, mem_flags); |
ee4aa54b | 624 | else if (size <= SMALL_STREAM_ARRAY_SIZE) |
8df75f42 SS |
625 | return dma_pool_alloc(xhci->small_streams_pool, |
626 | mem_flags, dma); | |
627 | else | |
628 | return dma_pool_alloc(xhci->medium_streams_pool, | |
629 | mem_flags, dma); | |
630 | } | |
631 | ||
e9df17eb SS |
632 | struct xhci_ring *xhci_dma_to_transfer_ring( |
633 | struct xhci_virt_ep *ep, | |
634 | u64 address) | |
635 | { | |
636 | if (ep->ep_state & EP_HAS_STREAMS) | |
637 | return radix_tree_lookup(&ep->stream_info->trb_address_map, | |
eb8ccd2b | 638 | address >> TRB_SEGMENT_SHIFT); |
e9df17eb SS |
639 | return ep->ring; |
640 | } | |
641 | ||
e9df17eb SS |
642 | struct xhci_ring *xhci_stream_id_to_ring( |
643 | struct xhci_virt_device *dev, | |
644 | unsigned int ep_index, | |
645 | unsigned int stream_id) | |
646 | { | |
647 | struct xhci_virt_ep *ep = &dev->eps[ep_index]; | |
648 | ||
649 | if (stream_id == 0) | |
650 | return ep->ring; | |
651 | if (!ep->stream_info) | |
652 | return NULL; | |
653 | ||
654 | if (stream_id > ep->stream_info->num_streams) | |
655 | return NULL; | |
656 | return ep->stream_info->stream_rings[stream_id]; | |
657 | } | |
658 | ||
8df75f42 SS |
659 | /* |
660 | * Change an endpoint's internal structure so it supports stream IDs. The | |
661 | * number of requested streams includes stream 0, which cannot be used by device | |
662 | * drivers. | |
663 | * | |
664 | * The number of stream contexts in the stream context array may be bigger than | |
665 | * the number of streams the driver wants to use. This is because the number of | |
666 | * stream context array entries must be a power of two. | |
8df75f42 SS |
667 | */ |
668 | struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci, | |
669 | unsigned int num_stream_ctxs, | |
f9c589e1 MN |
670 | unsigned int num_streams, |
671 | unsigned int max_packet, gfp_t mem_flags) | |
8df75f42 SS |
672 | { |
673 | struct xhci_stream_info *stream_info; | |
674 | u32 cur_stream; | |
675 | struct xhci_ring *cur_ring; | |
8df75f42 SS |
676 | u64 addr; |
677 | int ret; | |
678 | ||
679 | xhci_dbg(xhci, "Allocating %u streams and %u " | |
680 | "stream context array entries.\n", | |
681 | num_streams, num_stream_ctxs); | |
682 | if (xhci->cmd_ring_reserved_trbs == MAX_RSVD_CMD_TRBS) { | |
683 | xhci_dbg(xhci, "Command ring has no reserved TRBs available\n"); | |
684 | return NULL; | |
685 | } | |
686 | xhci->cmd_ring_reserved_trbs++; | |
687 | ||
688 | stream_info = kzalloc(sizeof(struct xhci_stream_info), mem_flags); | |
689 | if (!stream_info) | |
690 | goto cleanup_trbs; | |
691 | ||
692 | stream_info->num_streams = num_streams; | |
693 | stream_info->num_stream_ctxs = num_stream_ctxs; | |
694 | ||
695 | /* Initialize the array of virtual pointers to stream rings. */ | |
696 | stream_info->stream_rings = kzalloc( | |
697 | sizeof(struct xhci_ring *)*num_streams, | |
698 | mem_flags); | |
699 | if (!stream_info->stream_rings) | |
700 | goto cleanup_info; | |
701 | ||
702 | /* Initialize the array of DMA addresses for stream rings for the HW. */ | |
703 | stream_info->stream_ctx_array = xhci_alloc_stream_ctx(xhci, | |
704 | num_stream_ctxs, &stream_info->ctx_array_dma, | |
705 | mem_flags); | |
706 | if (!stream_info->stream_ctx_array) | |
707 | goto cleanup_ctx; | |
708 | memset(stream_info->stream_ctx_array, 0, | |
709 | sizeof(struct xhci_stream_ctx)*num_stream_ctxs); | |
710 | ||
711 | /* Allocate everything needed to free the stream rings later */ | |
712 | stream_info->free_streams_command = | |
713 | xhci_alloc_command(xhci, true, true, mem_flags); | |
714 | if (!stream_info->free_streams_command) | |
715 | goto cleanup_ctx; | |
716 | ||
717 | INIT_RADIX_TREE(&stream_info->trb_address_map, GFP_ATOMIC); | |
718 | ||
719 | /* Allocate rings for all the streams that the driver will use, | |
720 | * and add their segment DMA addresses to the radix tree. | |
721 | * Stream 0 is reserved. | |
722 | */ | |
f9c589e1 | 723 | |
8df75f42 SS |
724 | for (cur_stream = 1; cur_stream < num_streams; cur_stream++) { |
725 | stream_info->stream_rings[cur_stream] = | |
f9c589e1 MN |
726 | xhci_ring_alloc(xhci, 2, 1, TYPE_STREAM, max_packet, |
727 | mem_flags); | |
8df75f42 SS |
728 | cur_ring = stream_info->stream_rings[cur_stream]; |
729 | if (!cur_ring) | |
730 | goto cleanup_rings; | |
e9df17eb | 731 | cur_ring->stream_id = cur_stream; |
15341303 | 732 | cur_ring->trb_address_map = &stream_info->trb_address_map; |
8df75f42 SS |
733 | /* Set deq ptr, cycle bit, and stream context type */ |
734 | addr = cur_ring->first_seg->dma | | |
735 | SCT_FOR_CTX(SCT_PRI_TR) | | |
736 | cur_ring->cycle_state; | |
f5960b69 ME |
737 | stream_info->stream_ctx_array[cur_stream].stream_ring = |
738 | cpu_to_le64(addr); | |
8df75f42 SS |
739 | xhci_dbg(xhci, "Setting stream %d ring ptr to 0x%08llx\n", |
740 | cur_stream, (unsigned long long) addr); | |
741 | ||
15341303 | 742 | ret = xhci_update_stream_mapping(cur_ring, mem_flags); |
8df75f42 SS |
743 | if (ret) { |
744 | xhci_ring_free(xhci, cur_ring); | |
745 | stream_info->stream_rings[cur_stream] = NULL; | |
746 | goto cleanup_rings; | |
747 | } | |
748 | } | |
749 | /* Leave the other unused stream ring pointers in the stream context | |
750 | * array initialized to zero. This will cause the xHC to give us an | |
751 | * error if the device asks for a stream ID we don't have setup (if it | |
752 | * was any other way, the host controller would assume the ring is | |
753 | * "empty" and wait forever for data to be queued to that stream ID). | |
754 | */ | |
8df75f42 SS |
755 | |
756 | return stream_info; | |
757 | ||
758 | cleanup_rings: | |
759 | for (cur_stream = 1; cur_stream < num_streams; cur_stream++) { | |
760 | cur_ring = stream_info->stream_rings[cur_stream]; | |
761 | if (cur_ring) { | |
8df75f42 SS |
762 | xhci_ring_free(xhci, cur_ring); |
763 | stream_info->stream_rings[cur_stream] = NULL; | |
764 | } | |
765 | } | |
766 | xhci_free_command(xhci, stream_info->free_streams_command); | |
767 | cleanup_ctx: | |
768 | kfree(stream_info->stream_rings); | |
769 | cleanup_info: | |
770 | kfree(stream_info); | |
771 | cleanup_trbs: | |
772 | xhci->cmd_ring_reserved_trbs--; | |
773 | return NULL; | |
774 | } | |
775 | /* | |
776 | * Sets the MaxPStreams field and the Linear Stream Array field. | |
777 | * Sets the dequeue pointer to the stream context array. | |
778 | */ | |
779 | void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci, | |
780 | struct xhci_ep_ctx *ep_ctx, | |
781 | struct xhci_stream_info *stream_info) | |
782 | { | |
783 | u32 max_primary_streams; | |
784 | /* MaxPStreams is the number of stream context array entries, not the | |
785 | * number we're actually using. Must be in 2^(MaxPstreams + 1) format. | |
786 | * fls(0) = 0, fls(0x1) = 1, fls(0x10) = 2, fls(0x100) = 3, etc. | |
787 | */ | |
788 | max_primary_streams = fls(stream_info->num_stream_ctxs) - 2; | |
3a7fa5be XR |
789 | xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, |
790 | "Setting number of stream ctx array entries to %u", | |
8df75f42 | 791 | 1 << (max_primary_streams + 1)); |
28ccd296 ME |
792 | ep_ctx->ep_info &= cpu_to_le32(~EP_MAXPSTREAMS_MASK); |
793 | ep_ctx->ep_info |= cpu_to_le32(EP_MAXPSTREAMS(max_primary_streams) | |
794 | | EP_HAS_LSA); | |
795 | ep_ctx->deq = cpu_to_le64(stream_info->ctx_array_dma); | |
8df75f42 SS |
796 | } |
797 | ||
798 | /* | |
799 | * Sets the MaxPStreams field and the Linear Stream Array field to 0. | |
800 | * Reinstalls the "normal" endpoint ring (at its previous dequeue mark, | |
801 | * not at the beginning of the ring). | |
802 | */ | |
4daf9df5 | 803 | void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx *ep_ctx, |
8df75f42 SS |
804 | struct xhci_virt_ep *ep) |
805 | { | |
806 | dma_addr_t addr; | |
28ccd296 | 807 | ep_ctx->ep_info &= cpu_to_le32(~(EP_MAXPSTREAMS_MASK | EP_HAS_LSA)); |
8df75f42 | 808 | addr = xhci_trb_virt_to_dma(ep->ring->deq_seg, ep->ring->dequeue); |
28ccd296 | 809 | ep_ctx->deq = cpu_to_le64(addr | ep->ring->cycle_state); |
8df75f42 SS |
810 | } |
811 | ||
812 | /* Frees all stream contexts associated with the endpoint, | |
813 | * | |
814 | * Caller should fix the endpoint context streams fields. | |
815 | */ | |
816 | void xhci_free_stream_info(struct xhci_hcd *xhci, | |
817 | struct xhci_stream_info *stream_info) | |
818 | { | |
819 | int cur_stream; | |
820 | struct xhci_ring *cur_ring; | |
8df75f42 SS |
821 | |
822 | if (!stream_info) | |
823 | return; | |
824 | ||
825 | for (cur_stream = 1; cur_stream < stream_info->num_streams; | |
826 | cur_stream++) { | |
827 | cur_ring = stream_info->stream_rings[cur_stream]; | |
828 | if (cur_ring) { | |
8df75f42 SS |
829 | xhci_ring_free(xhci, cur_ring); |
830 | stream_info->stream_rings[cur_stream] = NULL; | |
831 | } | |
832 | } | |
833 | xhci_free_command(xhci, stream_info->free_streams_command); | |
834 | xhci->cmd_ring_reserved_trbs--; | |
835 | if (stream_info->stream_ctx_array) | |
836 | xhci_free_stream_ctx(xhci, | |
837 | stream_info->num_stream_ctxs, | |
838 | stream_info->stream_ctx_array, | |
839 | stream_info->ctx_array_dma); | |
840 | ||
0d3703be | 841 | kfree(stream_info->stream_rings); |
8df75f42 SS |
842 | kfree(stream_info); |
843 | } | |
844 | ||
845 | ||
846 | /***************** Device context manipulation *************************/ | |
847 | ||
6f5165cf SS |
848 | static void xhci_init_endpoint_timer(struct xhci_hcd *xhci, |
849 | struct xhci_virt_ep *ep) | |
850 | { | |
9e08a03d JL |
851 | setup_timer(&ep->stop_cmd_timer, xhci_stop_endpoint_command_watchdog, |
852 | (unsigned long)ep); | |
6f5165cf SS |
853 | ep->xhci = xhci; |
854 | } | |
855 | ||
839c817c SS |
856 | static void xhci_free_tt_info(struct xhci_hcd *xhci, |
857 | struct xhci_virt_device *virt_dev, | |
858 | int slot_id) | |
859 | { | |
839c817c | 860 | struct list_head *tt_list_head; |
46ed8f00 TI |
861 | struct xhci_tt_bw_info *tt_info, *next; |
862 | bool slot_found = false; | |
839c817c SS |
863 | |
864 | /* If the device never made it past the Set Address stage, | |
865 | * it may not have the real_port set correctly. | |
866 | */ | |
867 | if (virt_dev->real_port == 0 || | |
868 | virt_dev->real_port > HCS_MAX_PORTS(xhci->hcs_params1)) { | |
869 | xhci_dbg(xhci, "Bad real port.\n"); | |
870 | return; | |
871 | } | |
872 | ||
873 | tt_list_head = &(xhci->rh_bw[virt_dev->real_port - 1].tts); | |
46ed8f00 TI |
874 | list_for_each_entry_safe(tt_info, next, tt_list_head, tt_list) { |
875 | /* Multi-TT hubs will have more than one entry */ | |
876 | if (tt_info->slot_id == slot_id) { | |
877 | slot_found = true; | |
878 | list_del(&tt_info->tt_list); | |
879 | kfree(tt_info); | |
880 | } else if (slot_found) { | |
839c817c | 881 | break; |
46ed8f00 | 882 | } |
839c817c | 883 | } |
839c817c SS |
884 | } |
885 | ||
886 | int xhci_alloc_tt_info(struct xhci_hcd *xhci, | |
887 | struct xhci_virt_device *virt_dev, | |
888 | struct usb_device *hdev, | |
889 | struct usb_tt *tt, gfp_t mem_flags) | |
890 | { | |
891 | struct xhci_tt_bw_info *tt_info; | |
892 | unsigned int num_ports; | |
893 | int i, j; | |
894 | ||
895 | if (!tt->multi) | |
896 | num_ports = 1; | |
897 | else | |
898 | num_ports = hdev->maxchild; | |
899 | ||
900 | for (i = 0; i < num_ports; i++, tt_info++) { | |
901 | struct xhci_interval_bw_table *bw_table; | |
902 | ||
903 | tt_info = kzalloc(sizeof(*tt_info), mem_flags); | |
904 | if (!tt_info) | |
905 | goto free_tts; | |
906 | INIT_LIST_HEAD(&tt_info->tt_list); | |
907 | list_add(&tt_info->tt_list, | |
908 | &xhci->rh_bw[virt_dev->real_port - 1].tts); | |
909 | tt_info->slot_id = virt_dev->udev->slot_id; | |
910 | if (tt->multi) | |
911 | tt_info->ttport = i+1; | |
912 | bw_table = &tt_info->bw_table; | |
913 | for (j = 0; j < XHCI_MAX_INTERVAL; j++) | |
914 | INIT_LIST_HEAD(&bw_table->interval_bw[j].endpoints); | |
915 | } | |
916 | return 0; | |
917 | ||
918 | free_tts: | |
919 | xhci_free_tt_info(xhci, virt_dev, virt_dev->udev->slot_id); | |
920 | return -ENOMEM; | |
921 | } | |
922 | ||
923 | ||
924 | /* All the xhci_tds in the ring's TD list should be freed at this point. | |
925 | * Should be called with xhci->lock held if there is any chance the TT lists | |
926 | * will be manipulated by the configure endpoint, allocate device, or update | |
927 | * hub functions while this function is removing the TT entries from the list. | |
928 | */ | |
3ffbba95 SS |
929 | void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id) |
930 | { | |
931 | struct xhci_virt_device *dev; | |
932 | int i; | |
2e27980e | 933 | int old_active_eps = 0; |
3ffbba95 SS |
934 | |
935 | /* Slot ID 0 is reserved */ | |
936 | if (slot_id == 0 || !xhci->devs[slot_id]) | |
937 | return; | |
938 | ||
939 | dev = xhci->devs[slot_id]; | |
a711edee FB |
940 | |
941 | trace_xhci_free_virt_device(dev); | |
942 | ||
8e595a5d | 943 | xhci->dcbaa->dev_context_ptrs[slot_id] = 0; |
3ffbba95 SS |
944 | if (!dev) |
945 | return; | |
946 | ||
2e27980e SS |
947 | if (dev->tt_info) |
948 | old_active_eps = dev->tt_info->active_eps; | |
949 | ||
98871e94 | 950 | for (i = 0; i < 31; i++) { |
63a0d9ab SS |
951 | if (dev->eps[i].ring) |
952 | xhci_ring_free(xhci, dev->eps[i].ring); | |
8df75f42 SS |
953 | if (dev->eps[i].stream_info) |
954 | xhci_free_stream_info(xhci, | |
955 | dev->eps[i].stream_info); | |
2e27980e SS |
956 | /* Endpoints on the TT/root port lists should have been removed |
957 | * when usb_disable_device() was called for the device. | |
958 | * We can't drop them anyway, because the udev might have gone | |
959 | * away by this point, and we can't tell what speed it was. | |
960 | */ | |
961 | if (!list_empty(&dev->eps[i].bw_endpoint_list)) | |
962 | xhci_warn(xhci, "Slot %u endpoint %u " | |
963 | "not removed from BW list!\n", | |
964 | slot_id, i); | |
8df75f42 | 965 | } |
839c817c SS |
966 | /* If this is a hub, free the TT(s) from the TT list */ |
967 | xhci_free_tt_info(xhci, dev, slot_id); | |
2e27980e SS |
968 | /* If necessary, update the number of active TTs on this root port */ |
969 | xhci_update_tt_active_eps(xhci, dev, old_active_eps); | |
3ffbba95 | 970 | |
74f9fe21 SS |
971 | if (dev->ring_cache) { |
972 | for (i = 0; i < dev->num_rings_cached; i++) | |
973 | xhci_ring_free(xhci, dev->ring_cache[i]); | |
974 | kfree(dev->ring_cache); | |
975 | } | |
976 | ||
3ffbba95 | 977 | if (dev->in_ctx) |
d115b048 | 978 | xhci_free_container_ctx(xhci, dev->in_ctx); |
3ffbba95 | 979 | if (dev->out_ctx) |
d115b048 JY |
980 | xhci_free_container_ctx(xhci, dev->out_ctx); |
981 | ||
3ffbba95 | 982 | kfree(xhci->devs[slot_id]); |
326b4810 | 983 | xhci->devs[slot_id] = NULL; |
3ffbba95 SS |
984 | } |
985 | ||
ee8665e2 MN |
986 | /* |
987 | * Free a virt_device structure. | |
988 | * If the virt_device added a tt_info (a hub) and has children pointing to | |
989 | * that tt_info, then free the child first. Recursive. | |
990 | * We can't rely on udev at this point to find child-parent relationships. | |
991 | */ | |
992 | void xhci_free_virt_devices_depth_first(struct xhci_hcd *xhci, int slot_id) | |
993 | { | |
994 | struct xhci_virt_device *vdev; | |
995 | struct list_head *tt_list_head; | |
996 | struct xhci_tt_bw_info *tt_info, *next; | |
997 | int i; | |
998 | ||
999 | vdev = xhci->devs[slot_id]; | |
1000 | if (!vdev) | |
1001 | return; | |
1002 | ||
1003 | tt_list_head = &(xhci->rh_bw[vdev->real_port - 1].tts); | |
1004 | list_for_each_entry_safe(tt_info, next, tt_list_head, tt_list) { | |
1005 | /* is this a hub device that added a tt_info to the tts list */ | |
1006 | if (tt_info->slot_id == slot_id) { | |
1007 | /* are any devices using this tt_info? */ | |
1008 | for (i = 1; i < HCS_MAX_SLOTS(xhci->hcs_params1); i++) { | |
1009 | vdev = xhci->devs[i]; | |
1010 | if (vdev && (vdev->tt_info == tt_info)) | |
1011 | xhci_free_virt_devices_depth_first( | |
1012 | xhci, i); | |
1013 | } | |
1014 | } | |
1015 | } | |
1016 | /* we are now at a leaf device */ | |
1017 | xhci_free_virt_device(xhci, slot_id); | |
1018 | } | |
1019 | ||
3ffbba95 SS |
1020 | int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, |
1021 | struct usb_device *udev, gfp_t flags) | |
1022 | { | |
3ffbba95 | 1023 | struct xhci_virt_device *dev; |
63a0d9ab | 1024 | int i; |
3ffbba95 SS |
1025 | |
1026 | /* Slot ID 0 is reserved */ | |
1027 | if (slot_id == 0 || xhci->devs[slot_id]) { | |
1028 | xhci_warn(xhci, "Bad Slot ID %d\n", slot_id); | |
1029 | return 0; | |
1030 | } | |
1031 | ||
1032 | xhci->devs[slot_id] = kzalloc(sizeof(*xhci->devs[slot_id]), flags); | |
1033 | if (!xhci->devs[slot_id]) | |
1034 | return 0; | |
1035 | dev = xhci->devs[slot_id]; | |
1036 | ||
d115b048 JY |
1037 | /* Allocate the (output) device context that will be used in the HC. */ |
1038 | dev->out_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_DEVICE, flags); | |
3ffbba95 SS |
1039 | if (!dev->out_ctx) |
1040 | goto fail; | |
d115b048 | 1041 | |
700e2052 | 1042 | xhci_dbg(xhci, "Slot %d output ctx = 0x%llx (dma)\n", slot_id, |
d115b048 | 1043 | (unsigned long long)dev->out_ctx->dma); |
3ffbba95 SS |
1044 | |
1045 | /* Allocate the (input) device context for address device command */ | |
d115b048 | 1046 | dev->in_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT, flags); |
3ffbba95 SS |
1047 | if (!dev->in_ctx) |
1048 | goto fail; | |
d115b048 | 1049 | |
700e2052 | 1050 | xhci_dbg(xhci, "Slot %d input ctx = 0x%llx (dma)\n", slot_id, |
d115b048 | 1051 | (unsigned long long)dev->in_ctx->dma); |
3ffbba95 | 1052 | |
6f5165cf SS |
1053 | /* Initialize the cancellation list and watchdog timers for each ep */ |
1054 | for (i = 0; i < 31; i++) { | |
1055 | xhci_init_endpoint_timer(xhci, &dev->eps[i]); | |
63a0d9ab | 1056 | INIT_LIST_HEAD(&dev->eps[i].cancelled_td_list); |
2e27980e | 1057 | INIT_LIST_HEAD(&dev->eps[i].bw_endpoint_list); |
6f5165cf | 1058 | } |
63a0d9ab | 1059 | |
3ffbba95 | 1060 | /* Allocate endpoint 0 ring */ |
f9c589e1 | 1061 | dev->eps[0].ring = xhci_ring_alloc(xhci, 2, 1, TYPE_CTRL, 0, flags); |
63a0d9ab | 1062 | if (!dev->eps[0].ring) |
3ffbba95 SS |
1063 | goto fail; |
1064 | ||
74f9fe21 SS |
1065 | /* Allocate pointers to the ring cache */ |
1066 | dev->ring_cache = kzalloc( | |
1067 | sizeof(struct xhci_ring *)*XHCI_MAX_RINGS_CACHED, | |
1068 | flags); | |
1069 | if (!dev->ring_cache) | |
1070 | goto fail; | |
1071 | dev->num_rings_cached = 0; | |
1072 | ||
64927730 | 1073 | dev->udev = udev; |
f94e0186 | 1074 | |
28c2d2ef | 1075 | /* Point to output device context in dcbaa. */ |
28ccd296 | 1076 | xhci->dcbaa->dev_context_ptrs[slot_id] = cpu_to_le64(dev->out_ctx->dma); |
700e2052 | 1077 | xhci_dbg(xhci, "Set slot id %d dcbaa entry %p to 0x%llx\n", |
28ccd296 ME |
1078 | slot_id, |
1079 | &xhci->dcbaa->dev_context_ptrs[slot_id], | |
f5960b69 | 1080 | le64_to_cpu(xhci->dcbaa->dev_context_ptrs[slot_id])); |
3ffbba95 | 1081 | |
a711edee FB |
1082 | trace_xhci_alloc_virt_device(dev); |
1083 | ||
3ffbba95 SS |
1084 | return 1; |
1085 | fail: | |
1086 | xhci_free_virt_device(xhci, slot_id); | |
1087 | return 0; | |
1088 | } | |
1089 | ||
2d1ee590 SS |
1090 | void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci, |
1091 | struct usb_device *udev) | |
1092 | { | |
1093 | struct xhci_virt_device *virt_dev; | |
1094 | struct xhci_ep_ctx *ep0_ctx; | |
1095 | struct xhci_ring *ep_ring; | |
1096 | ||
1097 | virt_dev = xhci->devs[udev->slot_id]; | |
1098 | ep0_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, 0); | |
1099 | ep_ring = virt_dev->eps[0].ring; | |
1100 | /* | |
1101 | * FIXME we don't keep track of the dequeue pointer very well after a | |
1102 | * Set TR dequeue pointer, so we're setting the dequeue pointer of the | |
1103 | * host to our enqueue pointer. This should only be called after a | |
1104 | * configured device has reset, so all control transfers should have | |
1105 | * been completed or cancelled before the reset. | |
1106 | */ | |
28ccd296 ME |
1107 | ep0_ctx->deq = cpu_to_le64(xhci_trb_virt_to_dma(ep_ring->enq_seg, |
1108 | ep_ring->enqueue) | |
1109 | | ep_ring->cycle_state); | |
2d1ee590 SS |
1110 | } |
1111 | ||
f6ff0ac8 SS |
1112 | /* |
1113 | * The xHCI roothub may have ports of differing speeds in any order in the port | |
1114 | * status registers. xhci->port_array provides an array of the port speed for | |
1115 | * each offset into the port status registers. | |
1116 | * | |
1117 | * The xHCI hardware wants to know the roothub port number that the USB device | |
1118 | * is attached to (or the roothub port its ancestor hub is attached to). All we | |
1119 | * know is the index of that port under either the USB 2.0 or the USB 3.0 | |
1120 | * roothub, but that doesn't give us the real index into the HW port status | |
3f5eb141 | 1121 | * registers. Call xhci_find_raw_port_number() to get real index. |
f6ff0ac8 SS |
1122 | */ |
1123 | static u32 xhci_find_real_port_number(struct xhci_hcd *xhci, | |
1124 | struct usb_device *udev) | |
1125 | { | |
1126 | struct usb_device *top_dev; | |
3f5eb141 LT |
1127 | struct usb_hcd *hcd; |
1128 | ||
0caf6b33 | 1129 | if (udev->speed >= USB_SPEED_SUPER) |
3f5eb141 LT |
1130 | hcd = xhci->shared_hcd; |
1131 | else | |
1132 | hcd = xhci->main_hcd; | |
f6ff0ac8 SS |
1133 | |
1134 | for (top_dev = udev; top_dev->parent && top_dev->parent->parent; | |
1135 | top_dev = top_dev->parent) | |
1136 | /* Found device below root hub */; | |
f6ff0ac8 | 1137 | |
3f5eb141 | 1138 | return xhci_find_raw_port_number(hcd, top_dev->portnum); |
f6ff0ac8 SS |
1139 | } |
1140 | ||
3ffbba95 SS |
1141 | /* Setup an xHCI virtual device for a Set Address command */ |
1142 | int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev) | |
1143 | { | |
1144 | struct xhci_virt_device *dev; | |
1145 | struct xhci_ep_ctx *ep0_ctx; | |
d115b048 | 1146 | struct xhci_slot_ctx *slot_ctx; |
f6ff0ac8 | 1147 | u32 port_num; |
bd18fd5c | 1148 | u32 max_packets; |
f6ff0ac8 | 1149 | struct usb_device *top_dev; |
3ffbba95 SS |
1150 | |
1151 | dev = xhci->devs[udev->slot_id]; | |
1152 | /* Slot ID 0 is reserved */ | |
1153 | if (udev->slot_id == 0 || !dev) { | |
1154 | xhci_warn(xhci, "Slot ID %d is not assigned to this device\n", | |
1155 | udev->slot_id); | |
1156 | return -EINVAL; | |
1157 | } | |
d115b048 | 1158 | ep0_ctx = xhci_get_ep_ctx(xhci, dev->in_ctx, 0); |
d115b048 | 1159 | slot_ctx = xhci_get_slot_ctx(xhci, dev->in_ctx); |
3ffbba95 | 1160 | |
3ffbba95 | 1161 | /* 3) Only the control endpoint is valid - one endpoint context */ |
f5960b69 | 1162 | slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1) | udev->route); |
3ffbba95 | 1163 | switch (udev->speed) { |
0caf6b33 | 1164 | case USB_SPEED_SUPER_PLUS: |
d7854041 MN |
1165 | slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_SSP); |
1166 | max_packets = MAX_PACKET(512); | |
1167 | break; | |
3ffbba95 | 1168 | case USB_SPEED_SUPER: |
f5960b69 | 1169 | slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_SS); |
bd18fd5c | 1170 | max_packets = MAX_PACKET(512); |
3ffbba95 SS |
1171 | break; |
1172 | case USB_SPEED_HIGH: | |
f5960b69 | 1173 | slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_HS); |
bd18fd5c | 1174 | max_packets = MAX_PACKET(64); |
3ffbba95 | 1175 | break; |
bd18fd5c | 1176 | /* USB core guesses at a 64-byte max packet first for FS devices */ |
3ffbba95 | 1177 | case USB_SPEED_FULL: |
f5960b69 | 1178 | slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_FS); |
bd18fd5c | 1179 | max_packets = MAX_PACKET(64); |
3ffbba95 SS |
1180 | break; |
1181 | case USB_SPEED_LOW: | |
f5960b69 | 1182 | slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_LS); |
bd18fd5c | 1183 | max_packets = MAX_PACKET(8); |
3ffbba95 | 1184 | break; |
551cdbbe | 1185 | case USB_SPEED_WIRELESS: |
3ffbba95 SS |
1186 | xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n"); |
1187 | return -EINVAL; | |
1188 | break; | |
1189 | default: | |
1190 | /* Speed was set earlier, this shouldn't happen. */ | |
bd18fd5c | 1191 | return -EINVAL; |
3ffbba95 SS |
1192 | } |
1193 | /* Find the root hub port this device is under */ | |
f6ff0ac8 SS |
1194 | port_num = xhci_find_real_port_number(xhci, udev); |
1195 | if (!port_num) | |
1196 | return -EINVAL; | |
f5960b69 | 1197 | slot_ctx->dev_info2 |= cpu_to_le32(ROOT_HUB_PORT(port_num)); |
f6ff0ac8 | 1198 | /* Set the port number in the virtual_device to the faked port number */ |
3ffbba95 SS |
1199 | for (top_dev = udev; top_dev->parent && top_dev->parent->parent; |
1200 | top_dev = top_dev->parent) | |
1201 | /* Found device below root hub */; | |
fe30182c | 1202 | dev->fake_port = top_dev->portnum; |
66381755 | 1203 | dev->real_port = port_num; |
f6ff0ac8 | 1204 | xhci_dbg(xhci, "Set root hub portnum to %d\n", port_num); |
fe30182c | 1205 | xhci_dbg(xhci, "Set fake root hub portnum to %d\n", dev->fake_port); |
3ffbba95 | 1206 | |
839c817c SS |
1207 | /* Find the right bandwidth table that this device will be a part of. |
1208 | * If this is a full speed device attached directly to a root port (or a | |
1209 | * decendent of one), it counts as a primary bandwidth domain, not a | |
1210 | * secondary bandwidth domain under a TT. An xhci_tt_info structure | |
1211 | * will never be created for the HS root hub. | |
1212 | */ | |
1213 | if (!udev->tt || !udev->tt->hub->parent) { | |
1214 | dev->bw_table = &xhci->rh_bw[port_num - 1].bw_table; | |
1215 | } else { | |
1216 | struct xhci_root_port_bw_info *rh_bw; | |
1217 | struct xhci_tt_bw_info *tt_bw; | |
1218 | ||
1219 | rh_bw = &xhci->rh_bw[port_num - 1]; | |
1220 | /* Find the right TT. */ | |
1221 | list_for_each_entry(tt_bw, &rh_bw->tts, tt_list) { | |
1222 | if (tt_bw->slot_id != udev->tt->hub->slot_id) | |
1223 | continue; | |
1224 | ||
1225 | if (!dev->udev->tt->multi || | |
1226 | (udev->tt->multi && | |
1227 | tt_bw->ttport == dev->udev->ttport)) { | |
1228 | dev->bw_table = &tt_bw->bw_table; | |
1229 | dev->tt_info = tt_bw; | |
1230 | break; | |
1231 | } | |
1232 | } | |
1233 | if (!dev->tt_info) | |
1234 | xhci_warn(xhci, "WARN: Didn't find a matching TT\n"); | |
1235 | } | |
1236 | ||
aa1b13ef SS |
1237 | /* Is this a LS/FS device under an external HS hub? */ |
1238 | if (udev->tt && udev->tt->hub->parent) { | |
28ccd296 ME |
1239 | slot_ctx->tt_info = cpu_to_le32(udev->tt->hub->slot_id | |
1240 | (udev->ttport << 8)); | |
07b6de10 | 1241 | if (udev->tt->multi) |
28ccd296 | 1242 | slot_ctx->dev_info |= cpu_to_le32(DEV_MTT); |
3ffbba95 | 1243 | } |
700e2052 | 1244 | xhci_dbg(xhci, "udev->tt = %p\n", udev->tt); |
3ffbba95 SS |
1245 | xhci_dbg(xhci, "udev->ttport = 0x%x\n", udev->ttport); |
1246 | ||
1247 | /* Step 4 - ring already allocated */ | |
1248 | /* Step 5 */ | |
28ccd296 | 1249 | ep0_ctx->ep_info2 = cpu_to_le32(EP_TYPE(CTRL_EP)); |
bd18fd5c | 1250 | |
3ffbba95 | 1251 | /* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */ |
bd18fd5c MN |
1252 | ep0_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(0) | ERROR_COUNT(3) | |
1253 | max_packets); | |
3ffbba95 | 1254 | |
28ccd296 ME |
1255 | ep0_ctx->deq = cpu_to_le64(dev->eps[0].ring->first_seg->dma | |
1256 | dev->eps[0].ring->cycle_state); | |
3ffbba95 | 1257 | |
a711edee FB |
1258 | trace_xhci_setup_addressable_virt_device(dev); |
1259 | ||
3ffbba95 SS |
1260 | /* Steps 7 and 8 were done in xhci_alloc_virt_device() */ |
1261 | ||
1262 | return 0; | |
1263 | } | |
1264 | ||
dfa49c4a DT |
1265 | /* |
1266 | * Convert interval expressed as 2^(bInterval - 1) == interval into | |
1267 | * straight exponent value 2^n == interval. | |
1268 | * | |
1269 | */ | |
1270 | static unsigned int xhci_parse_exponent_interval(struct usb_device *udev, | |
1271 | struct usb_host_endpoint *ep) | |
1272 | { | |
1273 | unsigned int interval; | |
1274 | ||
1275 | interval = clamp_val(ep->desc.bInterval, 1, 16) - 1; | |
1276 | if (interval != ep->desc.bInterval - 1) | |
1277 | dev_warn(&udev->dev, | |
cd3c18ba | 1278 | "ep %#x - rounding interval to %d %sframes\n", |
dfa49c4a | 1279 | ep->desc.bEndpointAddress, |
cd3c18ba DT |
1280 | 1 << interval, |
1281 | udev->speed == USB_SPEED_FULL ? "" : "micro"); | |
1282 | ||
1283 | if (udev->speed == USB_SPEED_FULL) { | |
1284 | /* | |
1285 | * Full speed isoc endpoints specify interval in frames, | |
1286 | * not microframes. We are using microframes everywhere, | |
1287 | * so adjust accordingly. | |
1288 | */ | |
1289 | interval += 3; /* 1 frame = 2^3 uframes */ | |
1290 | } | |
dfa49c4a DT |
1291 | |
1292 | return interval; | |
1293 | } | |
1294 | ||
1295 | /* | |
340a3504 | 1296 | * Convert bInterval expressed in microframes (in 1-255 range) to exponent of |
dfa49c4a DT |
1297 | * microframes, rounded down to nearest power of 2. |
1298 | */ | |
340a3504 SS |
1299 | static unsigned int xhci_microframes_to_exponent(struct usb_device *udev, |
1300 | struct usb_host_endpoint *ep, unsigned int desc_interval, | |
1301 | unsigned int min_exponent, unsigned int max_exponent) | |
dfa49c4a DT |
1302 | { |
1303 | unsigned int interval; | |
1304 | ||
340a3504 SS |
1305 | interval = fls(desc_interval) - 1; |
1306 | interval = clamp_val(interval, min_exponent, max_exponent); | |
1307 | if ((1 << interval) != desc_interval) | |
a5da9568 | 1308 | dev_dbg(&udev->dev, |
dfa49c4a DT |
1309 | "ep %#x - rounding interval to %d microframes, ep desc says %d microframes\n", |
1310 | ep->desc.bEndpointAddress, | |
1311 | 1 << interval, | |
340a3504 | 1312 | desc_interval); |
dfa49c4a DT |
1313 | |
1314 | return interval; | |
1315 | } | |
1316 | ||
340a3504 SS |
1317 | static unsigned int xhci_parse_microframe_interval(struct usb_device *udev, |
1318 | struct usb_host_endpoint *ep) | |
1319 | { | |
55c1945e SS |
1320 | if (ep->desc.bInterval == 0) |
1321 | return 0; | |
340a3504 SS |
1322 | return xhci_microframes_to_exponent(udev, ep, |
1323 | ep->desc.bInterval, 0, 15); | |
1324 | } | |
1325 | ||
1326 | ||
1327 | static unsigned int xhci_parse_frame_interval(struct usb_device *udev, | |
1328 | struct usb_host_endpoint *ep) | |
1329 | { | |
1330 | return xhci_microframes_to_exponent(udev, ep, | |
1331 | ep->desc.bInterval * 8, 3, 10); | |
1332 | } | |
1333 | ||
f94e0186 SS |
1334 | /* Return the polling or NAK interval. |
1335 | * | |
1336 | * The polling interval is expressed in "microframes". If xHCI's Interval field | |
1337 | * is set to N, it will service the endpoint every 2^(Interval)*125us. | |
1338 | * | |
1339 | * The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval | |
1340 | * is set to 0. | |
1341 | */ | |
575688e1 | 1342 | static unsigned int xhci_get_endpoint_interval(struct usb_device *udev, |
f94e0186 SS |
1343 | struct usb_host_endpoint *ep) |
1344 | { | |
1345 | unsigned int interval = 0; | |
1346 | ||
1347 | switch (udev->speed) { | |
1348 | case USB_SPEED_HIGH: | |
1349 | /* Max NAK rate */ | |
1350 | if (usb_endpoint_xfer_control(&ep->desc) || | |
dfa49c4a | 1351 | usb_endpoint_xfer_bulk(&ep->desc)) { |
340a3504 | 1352 | interval = xhci_parse_microframe_interval(udev, ep); |
dfa49c4a DT |
1353 | break; |
1354 | } | |
f94e0186 | 1355 | /* Fall through - SS and HS isoc/int have same decoding */ |
dfa49c4a | 1356 | |
0caf6b33 | 1357 | case USB_SPEED_SUPER_PLUS: |
f94e0186 SS |
1358 | case USB_SPEED_SUPER: |
1359 | if (usb_endpoint_xfer_int(&ep->desc) || | |
dfa49c4a DT |
1360 | usb_endpoint_xfer_isoc(&ep->desc)) { |
1361 | interval = xhci_parse_exponent_interval(udev, ep); | |
f94e0186 SS |
1362 | } |
1363 | break; | |
dfa49c4a | 1364 | |
f94e0186 | 1365 | case USB_SPEED_FULL: |
b513d447 | 1366 | if (usb_endpoint_xfer_isoc(&ep->desc)) { |
dfa49c4a DT |
1367 | interval = xhci_parse_exponent_interval(udev, ep); |
1368 | break; | |
1369 | } | |
1370 | /* | |
b513d447 | 1371 | * Fall through for interrupt endpoint interval decoding |
dfa49c4a DT |
1372 | * since it uses the same rules as low speed interrupt |
1373 | * endpoints. | |
1374 | */ | |
1375 | ||
f94e0186 SS |
1376 | case USB_SPEED_LOW: |
1377 | if (usb_endpoint_xfer_int(&ep->desc) || | |
dfa49c4a DT |
1378 | usb_endpoint_xfer_isoc(&ep->desc)) { |
1379 | ||
1380 | interval = xhci_parse_frame_interval(udev, ep); | |
f94e0186 SS |
1381 | } |
1382 | break; | |
dfa49c4a | 1383 | |
f94e0186 SS |
1384 | default: |
1385 | BUG(); | |
1386 | } | |
def4e6f7 | 1387 | return interval; |
f94e0186 SS |
1388 | } |
1389 | ||
c30c791c | 1390 | /* The "Mult" field in the endpoint context is only set for SuperSpeed isoc eps. |
1cf62246 SS |
1391 | * High speed endpoint descriptors can define "the number of additional |
1392 | * transaction opportunities per microframe", but that goes in the Max Burst | |
1393 | * endpoint context field. | |
1394 | */ | |
575688e1 | 1395 | static u32 xhci_get_endpoint_mult(struct usb_device *udev, |
1cf62246 SS |
1396 | struct usb_host_endpoint *ep) |
1397 | { | |
0caf6b33 | 1398 | if (udev->speed < USB_SPEED_SUPER || |
c30c791c | 1399 | !usb_endpoint_xfer_isoc(&ep->desc)) |
1cf62246 | 1400 | return 0; |
842f1690 | 1401 | return ep->ss_ep_comp.bmAttributes; |
1cf62246 SS |
1402 | } |
1403 | ||
def4e6f7 MN |
1404 | static u32 xhci_get_endpoint_max_burst(struct usb_device *udev, |
1405 | struct usb_host_endpoint *ep) | |
1406 | { | |
1407 | /* Super speed and Plus have max burst in ep companion desc */ | |
1408 | if (udev->speed >= USB_SPEED_SUPER) | |
1409 | return ep->ss_ep_comp.bMaxBurst; | |
1410 | ||
1411 | if (udev->speed == USB_SPEED_HIGH && | |
1412 | (usb_endpoint_xfer_isoc(&ep->desc) || | |
1413 | usb_endpoint_xfer_int(&ep->desc))) | |
dcf5228c | 1414 | return usb_endpoint_maxp_mult(&ep->desc) - 1; |
def4e6f7 MN |
1415 | |
1416 | return 0; | |
1417 | } | |
1418 | ||
4daf9df5 | 1419 | static u32 xhci_get_endpoint_type(struct usb_host_endpoint *ep) |
f94e0186 SS |
1420 | { |
1421 | int in; | |
f94e0186 SS |
1422 | |
1423 | in = usb_endpoint_dir_in(&ep->desc); | |
def4e6f7 | 1424 | |
c0e625c4 FB |
1425 | switch (usb_endpoint_type(&ep->desc)) { |
1426 | case USB_ENDPOINT_XFER_CONTROL: | |
def4e6f7 | 1427 | return CTRL_EP; |
c0e625c4 | 1428 | case USB_ENDPOINT_XFER_BULK: |
def4e6f7 | 1429 | return in ? BULK_IN_EP : BULK_OUT_EP; |
c0e625c4 | 1430 | case USB_ENDPOINT_XFER_ISOC: |
def4e6f7 | 1431 | return in ? ISOC_IN_EP : ISOC_OUT_EP; |
c0e625c4 | 1432 | case USB_ENDPOINT_XFER_INT: |
def4e6f7 | 1433 | return in ? INT_IN_EP : INT_OUT_EP; |
c0e625c4 | 1434 | } |
def4e6f7 | 1435 | return 0; |
f94e0186 SS |
1436 | } |
1437 | ||
9238f25d SS |
1438 | /* Return the maximum endpoint service interval time (ESIT) payload. |
1439 | * Basically, this is the maxpacket size, multiplied by the burst size | |
1440 | * and mult size. | |
1441 | */ | |
4daf9df5 | 1442 | static u32 xhci_get_max_esit_payload(struct usb_device *udev, |
9238f25d SS |
1443 | struct usb_host_endpoint *ep) |
1444 | { | |
1445 | int max_burst; | |
1446 | int max_packet; | |
1447 | ||
1448 | /* Only applies for interrupt or isochronous endpoints */ | |
1449 | if (usb_endpoint_xfer_control(&ep->desc) || | |
1450 | usb_endpoint_xfer_bulk(&ep->desc)) | |
1451 | return 0; | |
1452 | ||
8ef8a9f5 MN |
1453 | /* SuperSpeedPlus Isoc ep sending over 48k per esit */ |
1454 | if ((udev->speed >= USB_SPEED_SUPER_PLUS) && | |
1455 | USB_SS_SSP_ISOC_COMP(ep->ss_ep_comp.bmAttributes)) | |
1456 | return le32_to_cpu(ep->ssp_isoc_ep_comp.dwBytesPerInterval); | |
1457 | /* SuperSpeed or SuperSpeedPlus Isoc ep with less than 48k per esit */ | |
1458 | else if (udev->speed >= USB_SPEED_SUPER) | |
64b3c304 | 1459 | return le16_to_cpu(ep->ss_ep_comp.wBytesPerInterval); |
9238f25d | 1460 | |
734d3ddd | 1461 | max_packet = usb_endpoint_maxp(&ep->desc); |
dcf5228c | 1462 | max_burst = usb_endpoint_maxp_mult(&ep->desc); |
9238f25d | 1463 | /* A 0 in max burst means 1 transfer per ESIT */ |
dcf5228c | 1464 | return max_packet * max_burst; |
9238f25d SS |
1465 | } |
1466 | ||
8df75f42 SS |
1467 | /* Set up an endpoint with one ring segment. Do not allocate stream rings. |
1468 | * Drivers will have to call usb_alloc_streams() to do that. | |
1469 | */ | |
f94e0186 SS |
1470 | int xhci_endpoint_init(struct xhci_hcd *xhci, |
1471 | struct xhci_virt_device *virt_dev, | |
1472 | struct usb_device *udev, | |
f88ba78d SS |
1473 | struct usb_host_endpoint *ep, |
1474 | gfp_t mem_flags) | |
f94e0186 SS |
1475 | { |
1476 | unsigned int ep_index; | |
1477 | struct xhci_ep_ctx *ep_ctx; | |
1478 | struct xhci_ring *ep_ring; | |
1479 | unsigned int max_packet; | |
def4e6f7 | 1480 | enum xhci_ring_type ring_type; |
9238f25d | 1481 | u32 max_esit_payload; |
17d65554 | 1482 | u32 endpoint_type; |
def4e6f7 MN |
1483 | unsigned int max_burst; |
1484 | unsigned int interval; | |
1485 | unsigned int mult; | |
1486 | unsigned int avg_trb_len; | |
1487 | unsigned int err_count = 0; | |
f94e0186 SS |
1488 | |
1489 | ep_index = xhci_get_endpoint_index(&ep->desc); | |
d115b048 | 1490 | ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index); |
f94e0186 | 1491 | |
4daf9df5 | 1492 | endpoint_type = xhci_get_endpoint_type(ep); |
17d65554 MN |
1493 | if (!endpoint_type) |
1494 | return -EINVAL; | |
17d65554 | 1495 | |
def4e6f7 | 1496 | ring_type = usb_endpoint_type(&ep->desc); |
f94e0186 | 1497 | |
def4e6f7 MN |
1498 | /* |
1499 | * Get values to fill the endpoint context, mostly from ep descriptor. | |
1500 | * The average TRB buffer lengt for bulk endpoints is unclear as we | |
1501 | * have no clue on scatter gather list entry size. For Isoc and Int, | |
1502 | * set it to max available. See xHCI 1.1 spec 4.14.1.1 for details. | |
1503 | */ | |
1504 | max_esit_payload = xhci_get_max_esit_payload(udev, ep); | |
1505 | interval = xhci_get_endpoint_interval(udev, ep); | |
69307ccb RQ |
1506 | |
1507 | /* Periodic endpoint bInterval limit quirk */ | |
1508 | if (usb_endpoint_xfer_int(&ep->desc) || | |
1509 | usb_endpoint_xfer_isoc(&ep->desc)) { | |
1510 | if ((xhci->quirks & XHCI_LIMIT_ENDPOINT_INTERVAL_7) && | |
1511 | udev->speed >= USB_SPEED_HIGH && | |
1512 | interval >= 7) { | |
1513 | interval = 6; | |
1514 | } | |
1515 | } | |
1516 | ||
def4e6f7 | 1517 | mult = xhci_get_endpoint_mult(udev, ep); |
734d3ddd | 1518 | max_packet = usb_endpoint_maxp(&ep->desc); |
def4e6f7 MN |
1519 | max_burst = xhci_get_endpoint_max_burst(udev, ep); |
1520 | avg_trb_len = max_esit_payload; | |
f94e0186 SS |
1521 | |
1522 | /* FIXME dig Mult and streams info out of ep companion desc */ | |
1523 | ||
def4e6f7 | 1524 | /* Allow 3 retries for everything but isoc, set CErr = 3 */ |
f94e0186 | 1525 | if (!usb_endpoint_xfer_isoc(&ep->desc)) |
def4e6f7 MN |
1526 | err_count = 3; |
1527 | /* Some devices get this wrong */ | |
1528 | if (usb_endpoint_xfer_bulk(&ep->desc) && udev->speed == USB_SPEED_HIGH) | |
1529 | max_packet = 512; | |
1530 | /* xHCI 1.0 and 1.1 indicates that ctrl ep avg TRB Length should be 8 */ | |
dca77945 | 1531 | if (usb_endpoint_xfer_control(&ep->desc) && xhci->hci_version >= 0x100) |
def4e6f7 | 1532 | avg_trb_len = 8; |
8ef8a9f5 MN |
1533 | /* xhci 1.1 with LEC support doesn't use mult field, use RsvdZ */ |
1534 | if ((xhci->hci_version > 0x100) && HCC2_LEC(xhci->hcc_params2)) | |
1535 | mult = 0; | |
def4e6f7 | 1536 | |
f9c589e1 MN |
1537 | /* Set up the endpoint ring */ |
1538 | virt_dev->eps[ep_index].new_ring = | |
1539 | xhci_ring_alloc(xhci, 2, 1, ring_type, max_packet, mem_flags); | |
1540 | if (!virt_dev->eps[ep_index].new_ring) { | |
1541 | /* Attempt to use the ring cache */ | |
1542 | if (virt_dev->num_rings_cached == 0) | |
1543 | return -ENOMEM; | |
1544 | virt_dev->num_rings_cached--; | |
1545 | virt_dev->eps[ep_index].new_ring = | |
1546 | virt_dev->ring_cache[virt_dev->num_rings_cached]; | |
1547 | virt_dev->ring_cache[virt_dev->num_rings_cached] = NULL; | |
1548 | xhci_reinit_cached_ring(xhci, virt_dev->eps[ep_index].new_ring, | |
1549 | 1, ring_type); | |
1550 | } | |
1551 | virt_dev->eps[ep_index].skip = false; | |
1552 | ep_ring = virt_dev->eps[ep_index].new_ring; | |
1553 | ||
def4e6f7 | 1554 | /* Fill the endpoint context */ |
8ef8a9f5 MN |
1555 | ep_ctx->ep_info = cpu_to_le32(EP_MAX_ESIT_PAYLOAD_HI(max_esit_payload) | |
1556 | EP_INTERVAL(interval) | | |
def4e6f7 MN |
1557 | EP_MULT(mult)); |
1558 | ep_ctx->ep_info2 = cpu_to_le32(EP_TYPE(endpoint_type) | | |
1559 | MAX_PACKET(max_packet) | | |
1560 | MAX_BURST(max_burst) | | |
1561 | ERROR_COUNT(err_count)); | |
1562 | ep_ctx->deq = cpu_to_le64(ep_ring->first_seg->dma | | |
1563 | ep_ring->cycle_state); | |
1564 | ||
1565 | ep_ctx->tx_info = cpu_to_le32(EP_MAX_ESIT_PAYLOAD_LO(max_esit_payload) | | |
1566 | EP_AVG_TRB_LENGTH(avg_trb_len)); | |
9238f25d | 1567 | |
f94e0186 SS |
1568 | /* FIXME Debug endpoint context */ |
1569 | return 0; | |
1570 | } | |
1571 | ||
1572 | void xhci_endpoint_zero(struct xhci_hcd *xhci, | |
1573 | struct xhci_virt_device *virt_dev, | |
1574 | struct usb_host_endpoint *ep) | |
1575 | { | |
1576 | unsigned int ep_index; | |
1577 | struct xhci_ep_ctx *ep_ctx; | |
1578 | ||
1579 | ep_index = xhci_get_endpoint_index(&ep->desc); | |
d115b048 | 1580 | ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index); |
f94e0186 SS |
1581 | |
1582 | ep_ctx->ep_info = 0; | |
1583 | ep_ctx->ep_info2 = 0; | |
8e595a5d | 1584 | ep_ctx->deq = 0; |
f94e0186 SS |
1585 | ep_ctx->tx_info = 0; |
1586 | /* Don't free the endpoint ring until the set interface or configuration | |
1587 | * request succeeds. | |
1588 | */ | |
1589 | } | |
1590 | ||
9af5d71d SS |
1591 | void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info) |
1592 | { | |
1593 | bw_info->ep_interval = 0; | |
1594 | bw_info->mult = 0; | |
1595 | bw_info->num_packets = 0; | |
1596 | bw_info->max_packet_size = 0; | |
1597 | bw_info->type = 0; | |
1598 | bw_info->max_esit_payload = 0; | |
1599 | } | |
1600 | ||
1601 | void xhci_update_bw_info(struct xhci_hcd *xhci, | |
1602 | struct xhci_container_ctx *in_ctx, | |
1603 | struct xhci_input_control_ctx *ctrl_ctx, | |
1604 | struct xhci_virt_device *virt_dev) | |
1605 | { | |
1606 | struct xhci_bw_info *bw_info; | |
1607 | struct xhci_ep_ctx *ep_ctx; | |
1608 | unsigned int ep_type; | |
1609 | int i; | |
1610 | ||
98871e94 | 1611 | for (i = 1; i < 31; i++) { |
9af5d71d SS |
1612 | bw_info = &virt_dev->eps[i].bw_info; |
1613 | ||
1614 | /* We can't tell what endpoint type is being dropped, but | |
1615 | * unconditionally clearing the bandwidth info for non-periodic | |
1616 | * endpoints should be harmless because the info will never be | |
1617 | * set in the first place. | |
1618 | */ | |
1619 | if (!EP_IS_ADDED(ctrl_ctx, i) && EP_IS_DROPPED(ctrl_ctx, i)) { | |
1620 | /* Dropped endpoint */ | |
1621 | xhci_clear_endpoint_bw_info(bw_info); | |
1622 | continue; | |
1623 | } | |
1624 | ||
1625 | if (EP_IS_ADDED(ctrl_ctx, i)) { | |
1626 | ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, i); | |
1627 | ep_type = CTX_TO_EP_TYPE(le32_to_cpu(ep_ctx->ep_info2)); | |
1628 | ||
1629 | /* Ignore non-periodic endpoints */ | |
1630 | if (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP && | |
1631 | ep_type != ISOC_IN_EP && | |
1632 | ep_type != INT_IN_EP) | |
1633 | continue; | |
1634 | ||
1635 | /* Added or changed endpoint */ | |
1636 | bw_info->ep_interval = CTX_TO_EP_INTERVAL( | |
1637 | le32_to_cpu(ep_ctx->ep_info)); | |
170c0263 SS |
1638 | /* Number of packets and mult are zero-based in the |
1639 | * input context, but we want one-based for the | |
1640 | * interval table. | |
9af5d71d | 1641 | */ |
170c0263 SS |
1642 | bw_info->mult = CTX_TO_EP_MULT( |
1643 | le32_to_cpu(ep_ctx->ep_info)) + 1; | |
9af5d71d SS |
1644 | bw_info->num_packets = CTX_TO_MAX_BURST( |
1645 | le32_to_cpu(ep_ctx->ep_info2)) + 1; | |
1646 | bw_info->max_packet_size = MAX_PACKET_DECODED( | |
1647 | le32_to_cpu(ep_ctx->ep_info2)); | |
1648 | bw_info->type = ep_type; | |
1649 | bw_info->max_esit_payload = CTX_TO_MAX_ESIT_PAYLOAD( | |
1650 | le32_to_cpu(ep_ctx->tx_info)); | |
1651 | } | |
1652 | } | |
1653 | } | |
1654 | ||
f2217e8e SS |
1655 | /* Copy output xhci_ep_ctx to the input xhci_ep_ctx copy. |
1656 | * Useful when you want to change one particular aspect of the endpoint and then | |
1657 | * issue a configure endpoint command. | |
1658 | */ | |
1659 | void xhci_endpoint_copy(struct xhci_hcd *xhci, | |
913a8a34 SS |
1660 | struct xhci_container_ctx *in_ctx, |
1661 | struct xhci_container_ctx *out_ctx, | |
1662 | unsigned int ep_index) | |
f2217e8e SS |
1663 | { |
1664 | struct xhci_ep_ctx *out_ep_ctx; | |
1665 | struct xhci_ep_ctx *in_ep_ctx; | |
1666 | ||
913a8a34 SS |
1667 | out_ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index); |
1668 | in_ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index); | |
f2217e8e SS |
1669 | |
1670 | in_ep_ctx->ep_info = out_ep_ctx->ep_info; | |
1671 | in_ep_ctx->ep_info2 = out_ep_ctx->ep_info2; | |
1672 | in_ep_ctx->deq = out_ep_ctx->deq; | |
1673 | in_ep_ctx->tx_info = out_ep_ctx->tx_info; | |
1674 | } | |
1675 | ||
1676 | /* Copy output xhci_slot_ctx to the input xhci_slot_ctx. | |
1677 | * Useful when you want to change one particular aspect of the endpoint and then | |
1678 | * issue a configure endpoint command. Only the context entries field matters, | |
1679 | * but we'll copy the whole thing anyway. | |
1680 | */ | |
913a8a34 SS |
1681 | void xhci_slot_copy(struct xhci_hcd *xhci, |
1682 | struct xhci_container_ctx *in_ctx, | |
1683 | struct xhci_container_ctx *out_ctx) | |
f2217e8e SS |
1684 | { |
1685 | struct xhci_slot_ctx *in_slot_ctx; | |
1686 | struct xhci_slot_ctx *out_slot_ctx; | |
1687 | ||
913a8a34 SS |
1688 | in_slot_ctx = xhci_get_slot_ctx(xhci, in_ctx); |
1689 | out_slot_ctx = xhci_get_slot_ctx(xhci, out_ctx); | |
f2217e8e SS |
1690 | |
1691 | in_slot_ctx->dev_info = out_slot_ctx->dev_info; | |
1692 | in_slot_ctx->dev_info2 = out_slot_ctx->dev_info2; | |
1693 | in_slot_ctx->tt_info = out_slot_ctx->tt_info; | |
1694 | in_slot_ctx->dev_state = out_slot_ctx->dev_state; | |
1695 | } | |
1696 | ||
254c80a3 JY |
1697 | /* Set up the scratchpad buffer array and scratchpad buffers, if needed. */ |
1698 | static int scratchpad_alloc(struct xhci_hcd *xhci, gfp_t flags) | |
1699 | { | |
1700 | int i; | |
4c39d4b9 | 1701 | struct device *dev = xhci_to_hcd(xhci)->self.sysdev; |
254c80a3 JY |
1702 | int num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2); |
1703 | ||
d195fcff XR |
1704 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
1705 | "Allocating %d scratchpad buffers", num_sp); | |
254c80a3 JY |
1706 | |
1707 | if (!num_sp) | |
1708 | return 0; | |
1709 | ||
1710 | xhci->scratchpad = kzalloc(sizeof(*xhci->scratchpad), flags); | |
1711 | if (!xhci->scratchpad) | |
1712 | goto fail_sp; | |
1713 | ||
22d45f01 | 1714 | xhci->scratchpad->sp_array = dma_alloc_coherent(dev, |
254c80a3 | 1715 | num_sp * sizeof(u64), |
22d45f01 | 1716 | &xhci->scratchpad->sp_dma, flags); |
254c80a3 JY |
1717 | if (!xhci->scratchpad->sp_array) |
1718 | goto fail_sp2; | |
1719 | ||
1720 | xhci->scratchpad->sp_buffers = kzalloc(sizeof(void *) * num_sp, flags); | |
1721 | if (!xhci->scratchpad->sp_buffers) | |
1722 | goto fail_sp3; | |
1723 | ||
28ccd296 | 1724 | xhci->dcbaa->dev_context_ptrs[0] = cpu_to_le64(xhci->scratchpad->sp_dma); |
254c80a3 JY |
1725 | for (i = 0; i < num_sp; i++) { |
1726 | dma_addr_t dma; | |
7480d912 | 1727 | void *buf = dma_zalloc_coherent(dev, xhci->page_size, &dma, |
22d45f01 | 1728 | flags); |
254c80a3 | 1729 | if (!buf) |
314eaf7d | 1730 | goto fail_sp4; |
254c80a3 JY |
1731 | |
1732 | xhci->scratchpad->sp_array[i] = dma; | |
1733 | xhci->scratchpad->sp_buffers[i] = buf; | |
254c80a3 JY |
1734 | } |
1735 | ||
1736 | return 0; | |
1737 | ||
314eaf7d | 1738 | fail_sp4: |
254c80a3 | 1739 | for (i = i - 1; i >= 0; i--) { |
22d45f01 | 1740 | dma_free_coherent(dev, xhci->page_size, |
254c80a3 | 1741 | xhci->scratchpad->sp_buffers[i], |
314eaf7d | 1742 | xhci->scratchpad->sp_array[i]); |
254c80a3 | 1743 | } |
254c80a3 | 1744 | |
254c80a3 JY |
1745 | kfree(xhci->scratchpad->sp_buffers); |
1746 | ||
1747 | fail_sp3: | |
22d45f01 | 1748 | dma_free_coherent(dev, num_sp * sizeof(u64), |
254c80a3 JY |
1749 | xhci->scratchpad->sp_array, |
1750 | xhci->scratchpad->sp_dma); | |
1751 | ||
1752 | fail_sp2: | |
1753 | kfree(xhci->scratchpad); | |
1754 | xhci->scratchpad = NULL; | |
1755 | ||
1756 | fail_sp: | |
1757 | return -ENOMEM; | |
1758 | } | |
1759 | ||
1760 | static void scratchpad_free(struct xhci_hcd *xhci) | |
1761 | { | |
1762 | int num_sp; | |
1763 | int i; | |
4c39d4b9 | 1764 | struct device *dev = xhci_to_hcd(xhci)->self.sysdev; |
254c80a3 JY |
1765 | |
1766 | if (!xhci->scratchpad) | |
1767 | return; | |
1768 | ||
1769 | num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2); | |
1770 | ||
1771 | for (i = 0; i < num_sp; i++) { | |
2a100047 | 1772 | dma_free_coherent(dev, xhci->page_size, |
254c80a3 | 1773 | xhci->scratchpad->sp_buffers[i], |
314eaf7d | 1774 | xhci->scratchpad->sp_array[i]); |
254c80a3 | 1775 | } |
254c80a3 | 1776 | kfree(xhci->scratchpad->sp_buffers); |
2a100047 | 1777 | dma_free_coherent(dev, num_sp * sizeof(u64), |
254c80a3 JY |
1778 | xhci->scratchpad->sp_array, |
1779 | xhci->scratchpad->sp_dma); | |
1780 | kfree(xhci->scratchpad); | |
1781 | xhci->scratchpad = NULL; | |
1782 | } | |
1783 | ||
913a8a34 | 1784 | struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci, |
a1d78c16 SS |
1785 | bool allocate_in_ctx, bool allocate_completion, |
1786 | gfp_t mem_flags) | |
913a8a34 SS |
1787 | { |
1788 | struct xhci_command *command; | |
1789 | ||
1790 | command = kzalloc(sizeof(*command), mem_flags); | |
1791 | if (!command) | |
1792 | return NULL; | |
1793 | ||
a1d78c16 SS |
1794 | if (allocate_in_ctx) { |
1795 | command->in_ctx = | |
1796 | xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT, | |
1797 | mem_flags); | |
1798 | if (!command->in_ctx) { | |
1799 | kfree(command); | |
1800 | return NULL; | |
1801 | } | |
06e18291 | 1802 | } |
913a8a34 SS |
1803 | |
1804 | if (allocate_completion) { | |
1805 | command->completion = | |
1806 | kzalloc(sizeof(struct completion), mem_flags); | |
1807 | if (!command->completion) { | |
1808 | xhci_free_container_ctx(xhci, command->in_ctx); | |
06e18291 | 1809 | kfree(command); |
913a8a34 SS |
1810 | return NULL; |
1811 | } | |
1812 | init_completion(command->completion); | |
1813 | } | |
1814 | ||
1815 | command->status = 0; | |
1816 | INIT_LIST_HEAD(&command->cmd_list); | |
1817 | return command; | |
1818 | } | |
1819 | ||
4daf9df5 | 1820 | void xhci_urb_free_priv(struct urb_priv *urb_priv) |
8e51adcc | 1821 | { |
7e64b037 | 1822 | kfree(urb_priv); |
8e51adcc AX |
1823 | } |
1824 | ||
913a8a34 SS |
1825 | void xhci_free_command(struct xhci_hcd *xhci, |
1826 | struct xhci_command *command) | |
1827 | { | |
1828 | xhci_free_container_ctx(xhci, | |
1829 | command->in_ctx); | |
1830 | kfree(command->completion); | |
1831 | kfree(command); | |
1832 | } | |
1833 | ||
66d4eadd SS |
1834 | void xhci_mem_cleanup(struct xhci_hcd *xhci) |
1835 | { | |
4c39d4b9 | 1836 | struct device *dev = xhci_to_hcd(xhci)->self.sysdev; |
0ebbab37 | 1837 | int size; |
32f1d2c5 | 1838 | int i, j, num_ports; |
0ebbab37 | 1839 | |
cb4d5ce5 | 1840 | cancel_delayed_work_sync(&xhci->cmd_timer); |
c311e391 | 1841 | |
0ebbab37 | 1842 | /* Free the Event Ring Segment Table and the actual Event Ring */ |
0ebbab37 SS |
1843 | size = sizeof(struct xhci_erst_entry)*(xhci->erst.num_entries); |
1844 | if (xhci->erst.entries) | |
2a100047 | 1845 | dma_free_coherent(dev, size, |
0ebbab37 SS |
1846 | xhci->erst.entries, xhci->erst.erst_dma_addr); |
1847 | xhci->erst.entries = NULL; | |
d195fcff | 1848 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed ERST"); |
0ebbab37 SS |
1849 | if (xhci->event_ring) |
1850 | xhci_ring_free(xhci, xhci->event_ring); | |
1851 | xhci->event_ring = NULL; | |
d195fcff | 1852 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed event ring"); |
0ebbab37 | 1853 | |
dbc33303 SS |
1854 | if (xhci->lpm_command) |
1855 | xhci_free_command(xhci, xhci->lpm_command); | |
0eda06c7 | 1856 | xhci->lpm_command = NULL; |
0ebbab37 SS |
1857 | if (xhci->cmd_ring) |
1858 | xhci_ring_free(xhci, xhci->cmd_ring); | |
1859 | xhci->cmd_ring = NULL; | |
d195fcff | 1860 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed command ring"); |
c9aa1a2d | 1861 | xhci_cleanup_command_queue(xhci); |
3ffbba95 | 1862 | |
5dc2808c | 1863 | num_ports = HCS_MAX_PORTS(xhci->hcs_params1); |
c207e7c5 | 1864 | for (i = 0; i < num_ports && xhci->rh_bw; i++) { |
5dc2808c MN |
1865 | struct xhci_interval_bw_table *bwt = &xhci->rh_bw[i].bw_table; |
1866 | for (j = 0; j < XHCI_MAX_INTERVAL; j++) { | |
1867 | struct list_head *ep = &bwt->interval_bw[j].endpoints; | |
1868 | while (!list_empty(ep)) | |
1869 | list_del_init(ep->next); | |
1870 | } | |
1871 | } | |
1872 | ||
ee8665e2 MN |
1873 | for (i = HCS_MAX_SLOTS(xhci->hcs_params1); i > 0; i--) |
1874 | xhci_free_virt_devices_depth_first(xhci, i); | |
3ffbba95 | 1875 | |
c7360b34 | 1876 | dma_pool_destroy(xhci->segment_pool); |
0ebbab37 | 1877 | xhci->segment_pool = NULL; |
d195fcff | 1878 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed segment pool"); |
3ffbba95 | 1879 | |
c7360b34 | 1880 | dma_pool_destroy(xhci->device_pool); |
3ffbba95 | 1881 | xhci->device_pool = NULL; |
d195fcff | 1882 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed device context pool"); |
3ffbba95 | 1883 | |
c7360b34 | 1884 | dma_pool_destroy(xhci->small_streams_pool); |
8df75f42 | 1885 | xhci->small_streams_pool = NULL; |
d195fcff XR |
1886 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
1887 | "Freed small stream array pool"); | |
8df75f42 | 1888 | |
c7360b34 | 1889 | dma_pool_destroy(xhci->medium_streams_pool); |
8df75f42 | 1890 | xhci->medium_streams_pool = NULL; |
d195fcff XR |
1891 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
1892 | "Freed medium stream array pool"); | |
8df75f42 | 1893 | |
a74588f9 | 1894 | if (xhci->dcbaa) |
2a100047 | 1895 | dma_free_coherent(dev, sizeof(*xhci->dcbaa), |
a74588f9 SS |
1896 | xhci->dcbaa, xhci->dcbaa->dma); |
1897 | xhci->dcbaa = NULL; | |
3ffbba95 | 1898 | |
5294bea4 | 1899 | scratchpad_free(xhci); |
da6699ce | 1900 | |
88696ae4 VM |
1901 | if (!xhci->rh_bw) |
1902 | goto no_bw; | |
1903 | ||
32f1d2c5 TI |
1904 | for (i = 0; i < num_ports; i++) { |
1905 | struct xhci_tt_bw_info *tt, *n; | |
1906 | list_for_each_entry_safe(tt, n, &xhci->rh_bw[i].tts, tt_list) { | |
1907 | list_del(&tt->tt_list); | |
1908 | kfree(tt); | |
1909 | } | |
f8a9e72d ON |
1910 | } |
1911 | ||
88696ae4 | 1912 | no_bw: |
127329d7 | 1913 | xhci->cmd_ring_reserved_trbs = 0; |
da6699ce SS |
1914 | xhci->num_usb2_ports = 0; |
1915 | xhci->num_usb3_ports = 0; | |
f8a9e72d | 1916 | xhci->num_active_eps = 0; |
da6699ce SS |
1917 | kfree(xhci->usb2_ports); |
1918 | kfree(xhci->usb3_ports); | |
1919 | kfree(xhci->port_array); | |
839c817c | 1920 | kfree(xhci->rh_bw); |
b630d4b9 | 1921 | kfree(xhci->ext_caps); |
da6699ce | 1922 | |
71504062 LB |
1923 | xhci->usb2_ports = NULL; |
1924 | xhci->usb3_ports = NULL; | |
1925 | xhci->port_array = NULL; | |
1926 | xhci->rh_bw = NULL; | |
1927 | xhci->ext_caps = NULL; | |
1928 | ||
66d4eadd SS |
1929 | xhci->page_size = 0; |
1930 | xhci->page_shift = 0; | |
20b67cf5 | 1931 | xhci->bus_state[0].bus_suspended = 0; |
f6ff0ac8 | 1932 | xhci->bus_state[1].bus_suspended = 0; |
66d4eadd SS |
1933 | } |
1934 | ||
6648f29d SS |
1935 | static int xhci_test_trb_in_td(struct xhci_hcd *xhci, |
1936 | struct xhci_segment *input_seg, | |
1937 | union xhci_trb *start_trb, | |
1938 | union xhci_trb *end_trb, | |
1939 | dma_addr_t input_dma, | |
1940 | struct xhci_segment *result_seg, | |
1941 | char *test_name, int test_number) | |
1942 | { | |
1943 | unsigned long long start_dma; | |
1944 | unsigned long long end_dma; | |
1945 | struct xhci_segment *seg; | |
1946 | ||
1947 | start_dma = xhci_trb_virt_to_dma(input_seg, start_trb); | |
1948 | end_dma = xhci_trb_virt_to_dma(input_seg, end_trb); | |
1949 | ||
cffb9be8 | 1950 | seg = trb_in_td(xhci, input_seg, start_trb, end_trb, input_dma, false); |
6648f29d SS |
1951 | if (seg != result_seg) { |
1952 | xhci_warn(xhci, "WARN: %s TRB math test %d failed!\n", | |
1953 | test_name, test_number); | |
1954 | xhci_warn(xhci, "Tested TRB math w/ seg %p and " | |
1955 | "input DMA 0x%llx\n", | |
1956 | input_seg, | |
1957 | (unsigned long long) input_dma); | |
1958 | xhci_warn(xhci, "starting TRB %p (0x%llx DMA), " | |
1959 | "ending TRB %p (0x%llx DMA)\n", | |
1960 | start_trb, start_dma, | |
1961 | end_trb, end_dma); | |
1962 | xhci_warn(xhci, "Expected seg %p, got seg %p\n", | |
1963 | result_seg, seg); | |
cffb9be8 HG |
1964 | trb_in_td(xhci, input_seg, start_trb, end_trb, input_dma, |
1965 | true); | |
6648f29d SS |
1966 | return -1; |
1967 | } | |
1968 | return 0; | |
1969 | } | |
1970 | ||
1971 | /* TRB math checks for xhci_trb_in_td(), using the command and event rings. */ | |
4daf9df5 | 1972 | static int xhci_check_trb_in_td_math(struct xhci_hcd *xhci) |
6648f29d SS |
1973 | { |
1974 | struct { | |
1975 | dma_addr_t input_dma; | |
1976 | struct xhci_segment *result_seg; | |
1977 | } simple_test_vector [] = { | |
1978 | /* A zeroed DMA field should fail */ | |
1979 | { 0, NULL }, | |
1980 | /* One TRB before the ring start should fail */ | |
1981 | { xhci->event_ring->first_seg->dma - 16, NULL }, | |
1982 | /* One byte before the ring start should fail */ | |
1983 | { xhci->event_ring->first_seg->dma - 1, NULL }, | |
1984 | /* Starting TRB should succeed */ | |
1985 | { xhci->event_ring->first_seg->dma, xhci->event_ring->first_seg }, | |
1986 | /* Ending TRB should succeed */ | |
1987 | { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16, | |
1988 | xhci->event_ring->first_seg }, | |
1989 | /* One byte after the ring end should fail */ | |
1990 | { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16 + 1, NULL }, | |
1991 | /* One TRB after the ring end should fail */ | |
1992 | { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT)*16, NULL }, | |
1993 | /* An address of all ones should fail */ | |
1994 | { (dma_addr_t) (~0), NULL }, | |
1995 | }; | |
1996 | struct { | |
1997 | struct xhci_segment *input_seg; | |
1998 | union xhci_trb *start_trb; | |
1999 | union xhci_trb *end_trb; | |
2000 | dma_addr_t input_dma; | |
2001 | struct xhci_segment *result_seg; | |
2002 | } complex_test_vector [] = { | |
2003 | /* Test feeding a valid DMA address from a different ring */ | |
2004 | { .input_seg = xhci->event_ring->first_seg, | |
2005 | .start_trb = xhci->event_ring->first_seg->trbs, | |
2006 | .end_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1], | |
2007 | .input_dma = xhci->cmd_ring->first_seg->dma, | |
2008 | .result_seg = NULL, | |
2009 | }, | |
2010 | /* Test feeding a valid end TRB from a different ring */ | |
2011 | { .input_seg = xhci->event_ring->first_seg, | |
2012 | .start_trb = xhci->event_ring->first_seg->trbs, | |
2013 | .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1], | |
2014 | .input_dma = xhci->cmd_ring->first_seg->dma, | |
2015 | .result_seg = NULL, | |
2016 | }, | |
2017 | /* Test feeding a valid start and end TRB from a different ring */ | |
2018 | { .input_seg = xhci->event_ring->first_seg, | |
2019 | .start_trb = xhci->cmd_ring->first_seg->trbs, | |
2020 | .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1], | |
2021 | .input_dma = xhci->cmd_ring->first_seg->dma, | |
2022 | .result_seg = NULL, | |
2023 | }, | |
2024 | /* TRB in this ring, but after this TD */ | |
2025 | { .input_seg = xhci->event_ring->first_seg, | |
2026 | .start_trb = &xhci->event_ring->first_seg->trbs[0], | |
2027 | .end_trb = &xhci->event_ring->first_seg->trbs[3], | |
2028 | .input_dma = xhci->event_ring->first_seg->dma + 4*16, | |
2029 | .result_seg = NULL, | |
2030 | }, | |
2031 | /* TRB in this ring, but before this TD */ | |
2032 | { .input_seg = xhci->event_ring->first_seg, | |
2033 | .start_trb = &xhci->event_ring->first_seg->trbs[3], | |
2034 | .end_trb = &xhci->event_ring->first_seg->trbs[6], | |
2035 | .input_dma = xhci->event_ring->first_seg->dma + 2*16, | |
2036 | .result_seg = NULL, | |
2037 | }, | |
2038 | /* TRB in this ring, but after this wrapped TD */ | |
2039 | { .input_seg = xhci->event_ring->first_seg, | |
2040 | .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3], | |
2041 | .end_trb = &xhci->event_ring->first_seg->trbs[1], | |
2042 | .input_dma = xhci->event_ring->first_seg->dma + 2*16, | |
2043 | .result_seg = NULL, | |
2044 | }, | |
2045 | /* TRB in this ring, but before this wrapped TD */ | |
2046 | { .input_seg = xhci->event_ring->first_seg, | |
2047 | .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3], | |
2048 | .end_trb = &xhci->event_ring->first_seg->trbs[1], | |
2049 | .input_dma = xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 4)*16, | |
2050 | .result_seg = NULL, | |
2051 | }, | |
2052 | /* TRB not in this ring, and we have a wrapped TD */ | |
2053 | { .input_seg = xhci->event_ring->first_seg, | |
2054 | .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3], | |
2055 | .end_trb = &xhci->event_ring->first_seg->trbs[1], | |
2056 | .input_dma = xhci->cmd_ring->first_seg->dma + 2*16, | |
2057 | .result_seg = NULL, | |
2058 | }, | |
2059 | }; | |
2060 | ||
2061 | unsigned int num_tests; | |
2062 | int i, ret; | |
2063 | ||
e10fa478 | 2064 | num_tests = ARRAY_SIZE(simple_test_vector); |
6648f29d SS |
2065 | for (i = 0; i < num_tests; i++) { |
2066 | ret = xhci_test_trb_in_td(xhci, | |
2067 | xhci->event_ring->first_seg, | |
2068 | xhci->event_ring->first_seg->trbs, | |
2069 | &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1], | |
2070 | simple_test_vector[i].input_dma, | |
2071 | simple_test_vector[i].result_seg, | |
2072 | "Simple", i); | |
2073 | if (ret < 0) | |
2074 | return ret; | |
2075 | } | |
2076 | ||
e10fa478 | 2077 | num_tests = ARRAY_SIZE(complex_test_vector); |
6648f29d SS |
2078 | for (i = 0; i < num_tests; i++) { |
2079 | ret = xhci_test_trb_in_td(xhci, | |
2080 | complex_test_vector[i].input_seg, | |
2081 | complex_test_vector[i].start_trb, | |
2082 | complex_test_vector[i].end_trb, | |
2083 | complex_test_vector[i].input_dma, | |
2084 | complex_test_vector[i].result_seg, | |
2085 | "Complex", i); | |
2086 | if (ret < 0) | |
2087 | return ret; | |
2088 | } | |
2089 | xhci_dbg(xhci, "TRB math tests passed.\n"); | |
2090 | return 0; | |
2091 | } | |
2092 | ||
257d585a SS |
2093 | static void xhci_set_hc_event_deq(struct xhci_hcd *xhci) |
2094 | { | |
2095 | u64 temp; | |
2096 | dma_addr_t deq; | |
2097 | ||
2098 | deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg, | |
2099 | xhci->event_ring->dequeue); | |
2100 | if (deq == 0 && !in_interrupt()) | |
2101 | xhci_warn(xhci, "WARN something wrong with SW event ring " | |
2102 | "dequeue ptr.\n"); | |
2103 | /* Update HC event ring dequeue pointer */ | |
f7b2e403 | 2104 | temp = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); |
257d585a SS |
2105 | temp &= ERST_PTR_MASK; |
2106 | /* Don't clear the EHB bit (which is RW1C) because | |
2107 | * there might be more events to service. | |
2108 | */ | |
2109 | temp &= ~ERST_EHB; | |
d195fcff XR |
2110 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2111 | "// Write event ring dequeue pointer, " | |
2112 | "preserving EHB bit"); | |
477632df | 2113 | xhci_write_64(xhci, ((u64) deq & (u64) ~ERST_PTR_MASK) | temp, |
257d585a SS |
2114 | &xhci->ir_set->erst_dequeue); |
2115 | } | |
2116 | ||
da6699ce | 2117 | static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int num_ports, |
d5ddcdf4 | 2118 | __le32 __iomem *addr, int max_caps) |
da6699ce SS |
2119 | { |
2120 | u32 temp, port_offset, port_count; | |
2121 | int i; | |
d5ddcdf4 | 2122 | u8 major_revision; |
47189098 | 2123 | struct xhci_hub *rhub; |
da6699ce | 2124 | |
47189098 | 2125 | temp = readl(addr); |
d5ddcdf4 | 2126 | major_revision = XHCI_EXT_PORT_MAJOR(temp); |
47189098 | 2127 | |
d5ddcdf4 | 2128 | if (major_revision == 0x03) { |
47189098 | 2129 | rhub = &xhci->usb3_rhub; |
d5ddcdf4 | 2130 | } else if (major_revision <= 0x02) { |
47189098 MN |
2131 | rhub = &xhci->usb2_rhub; |
2132 | } else { | |
da6699ce SS |
2133 | xhci_warn(xhci, "Ignoring unknown port speed, " |
2134 | "Ext Cap %p, revision = 0x%x\n", | |
2135 | addr, major_revision); | |
2136 | /* Ignoring port protocol we can't understand. FIXME */ | |
2137 | return; | |
2138 | } | |
47189098 MN |
2139 | rhub->maj_rev = XHCI_EXT_PORT_MAJOR(temp); |
2140 | rhub->min_rev = XHCI_EXT_PORT_MINOR(temp); | |
da6699ce SS |
2141 | |
2142 | /* Port offset and count in the third dword, see section 7.2 */ | |
b0ba9720 | 2143 | temp = readl(addr + 2); |
da6699ce SS |
2144 | port_offset = XHCI_EXT_PORT_OFF(temp); |
2145 | port_count = XHCI_EXT_PORT_COUNT(temp); | |
d195fcff XR |
2146 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2147 | "Ext Cap %p, port offset = %u, " | |
2148 | "count = %u, revision = 0x%x", | |
da6699ce SS |
2149 | addr, port_offset, port_count, major_revision); |
2150 | /* Port count includes the current port offset */ | |
2151 | if (port_offset == 0 || (port_offset + port_count - 1) > num_ports) | |
2152 | /* WTF? "Valid values are ‘1’ to MaxPorts" */ | |
2153 | return; | |
fc71ff75 | 2154 | |
47189098 MN |
2155 | rhub->psi_count = XHCI_EXT_PORT_PSIC(temp); |
2156 | if (rhub->psi_count) { | |
2157 | rhub->psi = kcalloc(rhub->psi_count, sizeof(*rhub->psi), | |
2158 | GFP_KERNEL); | |
2159 | if (!rhub->psi) | |
2160 | rhub->psi_count = 0; | |
2161 | ||
2162 | rhub->psi_uid_count++; | |
2163 | for (i = 0; i < rhub->psi_count; i++) { | |
2164 | rhub->psi[i] = readl(addr + 4 + i); | |
2165 | ||
2166 | /* count unique ID values, two consecutive entries can | |
2167 | * have the same ID if link is assymetric | |
2168 | */ | |
2169 | if (i && (XHCI_EXT_PORT_PSIV(rhub->psi[i]) != | |
2170 | XHCI_EXT_PORT_PSIV(rhub->psi[i - 1]))) | |
2171 | rhub->psi_uid_count++; | |
2172 | ||
2173 | xhci_dbg(xhci, "PSIV:%d PSIE:%d PLT:%d PFD:%d LP:%d PSIM:%d\n", | |
2174 | XHCI_EXT_PORT_PSIV(rhub->psi[i]), | |
2175 | XHCI_EXT_PORT_PSIE(rhub->psi[i]), | |
2176 | XHCI_EXT_PORT_PLT(rhub->psi[i]), | |
2177 | XHCI_EXT_PORT_PFD(rhub->psi[i]), | |
2178 | XHCI_EXT_PORT_LP(rhub->psi[i]), | |
2179 | XHCI_EXT_PORT_PSIM(rhub->psi[i])); | |
2180 | } | |
2181 | } | |
b630d4b9 MN |
2182 | /* cache usb2 port capabilities */ |
2183 | if (major_revision < 0x03 && xhci->num_ext_caps < max_caps) | |
2184 | xhci->ext_caps[xhci->num_ext_caps++] = temp; | |
2185 | ||
fc71ff75 AX |
2186 | /* Check the host's USB2 LPM capability */ |
2187 | if ((xhci->hci_version == 0x96) && (major_revision != 0x03) && | |
2188 | (temp & XHCI_L1C)) { | |
d195fcff XR |
2189 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2190 | "xHCI 0.96: support USB2 software lpm"); | |
fc71ff75 AX |
2191 | xhci->sw_lpm_support = 1; |
2192 | } | |
2193 | ||
2194 | if ((xhci->hci_version >= 0x100) && (major_revision != 0x03)) { | |
d195fcff XR |
2195 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2196 | "xHCI 1.0: support USB2 software lpm"); | |
fc71ff75 AX |
2197 | xhci->sw_lpm_support = 1; |
2198 | if (temp & XHCI_HLC) { | |
d195fcff XR |
2199 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2200 | "xHCI 1.0: support USB2 hardware lpm"); | |
fc71ff75 AX |
2201 | xhci->hw_lpm_support = 1; |
2202 | } | |
2203 | } | |
2204 | ||
da6699ce SS |
2205 | port_offset--; |
2206 | for (i = port_offset; i < (port_offset + port_count); i++) { | |
2207 | /* Duplicate entry. Ignore the port if the revisions differ. */ | |
2208 | if (xhci->port_array[i] != 0) { | |
2209 | xhci_warn(xhci, "Duplicate port entry, Ext Cap %p," | |
2210 | " port %u\n", addr, i); | |
2211 | xhci_warn(xhci, "Port was marked as USB %u, " | |
2212 | "duplicated as USB %u\n", | |
2213 | xhci->port_array[i], major_revision); | |
2214 | /* Only adjust the roothub port counts if we haven't | |
2215 | * found a similar duplicate. | |
2216 | */ | |
2217 | if (xhci->port_array[i] != major_revision && | |
22e04870 | 2218 | xhci->port_array[i] != DUPLICATE_ENTRY) { |
da6699ce SS |
2219 | if (xhci->port_array[i] == 0x03) |
2220 | xhci->num_usb3_ports--; | |
2221 | else | |
2222 | xhci->num_usb2_ports--; | |
22e04870 | 2223 | xhci->port_array[i] = DUPLICATE_ENTRY; |
da6699ce SS |
2224 | } |
2225 | /* FIXME: Should we disable the port? */ | |
f8bbeabc | 2226 | continue; |
da6699ce SS |
2227 | } |
2228 | xhci->port_array[i] = major_revision; | |
2229 | if (major_revision == 0x03) | |
2230 | xhci->num_usb3_ports++; | |
2231 | else | |
2232 | xhci->num_usb2_ports++; | |
2233 | } | |
2234 | /* FIXME: Should we disable ports not in the Extended Capabilities? */ | |
2235 | } | |
2236 | ||
2237 | /* | |
2238 | * Scan the Extended Capabilities for the "Supported Protocol Capabilities" that | |
2239 | * specify what speeds each port is supposed to be. We can't count on the port | |
2240 | * speed bits in the PORTSC register being correct until a device is connected, | |
2241 | * but we need to set up the two fake roothubs with the correct number of USB | |
2242 | * 3.0 and USB 2.0 ports at host controller initialization time. | |
2243 | */ | |
2244 | static int xhci_setup_port_arrays(struct xhci_hcd *xhci, gfp_t flags) | |
2245 | { | |
d5ddcdf4 MN |
2246 | void __iomem *base; |
2247 | u32 offset; | |
da6699ce | 2248 | unsigned int num_ports; |
2e27980e | 2249 | int i, j, port_index; |
b630d4b9 | 2250 | int cap_count = 0; |
d5ddcdf4 | 2251 | u32 cap_start; |
da6699ce SS |
2252 | |
2253 | num_ports = HCS_MAX_PORTS(xhci->hcs_params1); | |
2254 | xhci->port_array = kzalloc(sizeof(*xhci->port_array)*num_ports, flags); | |
2255 | if (!xhci->port_array) | |
2256 | return -ENOMEM; | |
2257 | ||
839c817c SS |
2258 | xhci->rh_bw = kzalloc(sizeof(*xhci->rh_bw)*num_ports, flags); |
2259 | if (!xhci->rh_bw) | |
2260 | return -ENOMEM; | |
2e27980e SS |
2261 | for (i = 0; i < num_ports; i++) { |
2262 | struct xhci_interval_bw_table *bw_table; | |
2263 | ||
839c817c | 2264 | INIT_LIST_HEAD(&xhci->rh_bw[i].tts); |
2e27980e SS |
2265 | bw_table = &xhci->rh_bw[i].bw_table; |
2266 | for (j = 0; j < XHCI_MAX_INTERVAL; j++) | |
2267 | INIT_LIST_HEAD(&bw_table->interval_bw[j].endpoints); | |
2268 | } | |
d5ddcdf4 | 2269 | base = &xhci->cap_regs->hc_capbase; |
839c817c | 2270 | |
d5ddcdf4 MN |
2271 | cap_start = xhci_find_next_ext_cap(base, 0, XHCI_EXT_CAPS_PROTOCOL); |
2272 | if (!cap_start) { | |
2273 | xhci_err(xhci, "No Extended Capability registers, unable to set up roothub\n"); | |
2274 | return -ENODEV; | |
2275 | } | |
b630d4b9 | 2276 | |
d5ddcdf4 | 2277 | offset = cap_start; |
b630d4b9 | 2278 | /* count extended protocol capability entries for later caching */ |
d5ddcdf4 MN |
2279 | while (offset) { |
2280 | cap_count++; | |
2281 | offset = xhci_find_next_ext_cap(base, offset, | |
2282 | XHCI_EXT_CAPS_PROTOCOL); | |
2283 | } | |
b630d4b9 MN |
2284 | |
2285 | xhci->ext_caps = kzalloc(sizeof(*xhci->ext_caps) * cap_count, flags); | |
2286 | if (!xhci->ext_caps) | |
2287 | return -ENOMEM; | |
2288 | ||
d5ddcdf4 MN |
2289 | offset = cap_start; |
2290 | ||
2291 | while (offset) { | |
2292 | xhci_add_in_port(xhci, num_ports, base + offset, cap_count); | |
2293 | if (xhci->num_usb2_ports + xhci->num_usb3_ports == num_ports) | |
da6699ce | 2294 | break; |
d5ddcdf4 MN |
2295 | offset = xhci_find_next_ext_cap(base, offset, |
2296 | XHCI_EXT_CAPS_PROTOCOL); | |
da6699ce SS |
2297 | } |
2298 | ||
2299 | if (xhci->num_usb2_ports == 0 && xhci->num_usb3_ports == 0) { | |
2300 | xhci_warn(xhci, "No ports on the roothubs?\n"); | |
2301 | return -ENODEV; | |
2302 | } | |
d195fcff XR |
2303 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2304 | "Found %u USB 2.0 ports and %u USB 3.0 ports.", | |
da6699ce | 2305 | xhci->num_usb2_ports, xhci->num_usb3_ports); |
d30b2a20 SS |
2306 | |
2307 | /* Place limits on the number of roothub ports so that the hub | |
2308 | * descriptors aren't longer than the USB core will allocate. | |
2309 | */ | |
5120a266 | 2310 | if (xhci->num_usb3_ports > USB_SS_MAXPORTS) { |
d195fcff | 2311 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
5120a266 JH |
2312 | "Limiting USB 3.0 roothub ports to %u.", |
2313 | USB_SS_MAXPORTS); | |
2314 | xhci->num_usb3_ports = USB_SS_MAXPORTS; | |
d30b2a20 SS |
2315 | } |
2316 | if (xhci->num_usb2_ports > USB_MAXCHILDREN) { | |
d195fcff XR |
2317 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2318 | "Limiting USB 2.0 roothub ports to %u.", | |
d30b2a20 SS |
2319 | USB_MAXCHILDREN); |
2320 | xhci->num_usb2_ports = USB_MAXCHILDREN; | |
2321 | } | |
2322 | ||
da6699ce SS |
2323 | /* |
2324 | * Note we could have all USB 3.0 ports, or all USB 2.0 ports. | |
2325 | * Not sure how the USB core will handle a hub with no ports... | |
2326 | */ | |
2327 | if (xhci->num_usb2_ports) { | |
2328 | xhci->usb2_ports = kmalloc(sizeof(*xhci->usb2_ports)* | |
2329 | xhci->num_usb2_ports, flags); | |
2330 | if (!xhci->usb2_ports) | |
2331 | return -ENOMEM; | |
2332 | ||
2333 | port_index = 0; | |
f8bbeabc SS |
2334 | for (i = 0; i < num_ports; i++) { |
2335 | if (xhci->port_array[i] == 0x03 || | |
2336 | xhci->port_array[i] == 0 || | |
22e04870 | 2337 | xhci->port_array[i] == DUPLICATE_ENTRY) |
f8bbeabc SS |
2338 | continue; |
2339 | ||
2340 | xhci->usb2_ports[port_index] = | |
2341 | &xhci->op_regs->port_status_base + | |
2342 | NUM_PORT_REGS*i; | |
d195fcff XR |
2343 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2344 | "USB 2.0 port at index %u, " | |
2345 | "addr = %p", i, | |
f8bbeabc SS |
2346 | xhci->usb2_ports[port_index]); |
2347 | port_index++; | |
d30b2a20 SS |
2348 | if (port_index == xhci->num_usb2_ports) |
2349 | break; | |
f8bbeabc | 2350 | } |
da6699ce SS |
2351 | } |
2352 | if (xhci->num_usb3_ports) { | |
2353 | xhci->usb3_ports = kmalloc(sizeof(*xhci->usb3_ports)* | |
2354 | xhci->num_usb3_ports, flags); | |
2355 | if (!xhci->usb3_ports) | |
2356 | return -ENOMEM; | |
2357 | ||
2358 | port_index = 0; | |
2359 | for (i = 0; i < num_ports; i++) | |
2360 | if (xhci->port_array[i] == 0x03) { | |
2361 | xhci->usb3_ports[port_index] = | |
2362 | &xhci->op_regs->port_status_base + | |
2363 | NUM_PORT_REGS*i; | |
d195fcff XR |
2364 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2365 | "USB 3.0 port at index %u, " | |
2366 | "addr = %p", i, | |
da6699ce SS |
2367 | xhci->usb3_ports[port_index]); |
2368 | port_index++; | |
d30b2a20 SS |
2369 | if (port_index == xhci->num_usb3_ports) |
2370 | break; | |
da6699ce SS |
2371 | } |
2372 | } | |
2373 | return 0; | |
2374 | } | |
6648f29d | 2375 | |
66d4eadd SS |
2376 | int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags) |
2377 | { | |
0ebbab37 | 2378 | dma_addr_t dma; |
4c39d4b9 | 2379 | struct device *dev = xhci_to_hcd(xhci)->self.sysdev; |
66d4eadd | 2380 | unsigned int val, val2; |
8e595a5d | 2381 | u64 val_64; |
0ebbab37 | 2382 | struct xhci_segment *seg; |
623bef9e | 2383 | u32 page_size, temp; |
66d4eadd SS |
2384 | int i; |
2385 | ||
c9aa1a2d | 2386 | INIT_LIST_HEAD(&xhci->cmd_list); |
331de00a | 2387 | |
cb4d5ce5 OH |
2388 | /* init command timeout work */ |
2389 | INIT_DELAYED_WORK(&xhci->cmd_timer, xhci_handle_command_timeout); | |
1c111b6c | 2390 | init_completion(&xhci->cmd_ring_stop_completion); |
cc8e4fc0 | 2391 | |
b0ba9720 | 2392 | page_size = readl(&xhci->op_regs->page_size); |
d195fcff XR |
2393 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2394 | "Supported page size register = 0x%x", page_size); | |
66d4eadd SS |
2395 | for (i = 0; i < 16; i++) { |
2396 | if ((0x1 & page_size) != 0) | |
2397 | break; | |
2398 | page_size = page_size >> 1; | |
2399 | } | |
2400 | if (i < 16) | |
d195fcff XR |
2401 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2402 | "Supported page size of %iK", (1 << (i+12)) / 1024); | |
66d4eadd SS |
2403 | else |
2404 | xhci_warn(xhci, "WARN: no supported page size\n"); | |
2405 | /* Use 4K pages, since that's common and the minimum the HC supports */ | |
2406 | xhci->page_shift = 12; | |
2407 | xhci->page_size = 1 << xhci->page_shift; | |
d195fcff XR |
2408 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2409 | "HCD page size set to %iK", xhci->page_size / 1024); | |
66d4eadd SS |
2410 | |
2411 | /* | |
2412 | * Program the Number of Device Slots Enabled field in the CONFIG | |
2413 | * register with the max value of slots the HC can handle. | |
2414 | */ | |
b0ba9720 | 2415 | val = HCS_MAX_SLOTS(readl(&xhci->cap_regs->hcs_params1)); |
d195fcff XR |
2416 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2417 | "// xHC can handle at most %d device slots.", val); | |
b0ba9720 | 2418 | val2 = readl(&xhci->op_regs->config_reg); |
66d4eadd | 2419 | val |= (val2 & ~HCS_SLOTS_MASK); |
d195fcff XR |
2420 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2421 | "// Setting Max device slots reg = 0x%x.", val); | |
204b7793 | 2422 | writel(val, &xhci->op_regs->config_reg); |
66d4eadd | 2423 | |
a74588f9 | 2424 | /* |
724e882d | 2425 | * xHCI section 5.4.6 - doorbell array must be |
a74588f9 SS |
2426 | * "physically contiguous and 64-byte (cache line) aligned". |
2427 | */ | |
22d45f01 | 2428 | xhci->dcbaa = dma_alloc_coherent(dev, sizeof(*xhci->dcbaa), &dma, |
c95a9f83 | 2429 | flags); |
a74588f9 SS |
2430 | if (!xhci->dcbaa) |
2431 | goto fail; | |
2432 | memset(xhci->dcbaa, 0, sizeof *(xhci->dcbaa)); | |
2433 | xhci->dcbaa->dma = dma; | |
d195fcff XR |
2434 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2435 | "// Device context base array address = 0x%llx (DMA), %p (virt)", | |
700e2052 | 2436 | (unsigned long long)xhci->dcbaa->dma, xhci->dcbaa); |
477632df | 2437 | xhci_write_64(xhci, dma, &xhci->op_regs->dcbaa_ptr); |
a74588f9 | 2438 | |
0ebbab37 SS |
2439 | /* |
2440 | * Initialize the ring segment pool. The ring must be a contiguous | |
2441 | * structure comprised of TRBs. The TRBs must be 16 byte aligned, | |
84c1e40f HG |
2442 | * however, the command ring segment needs 64-byte aligned segments |
2443 | * and our use of dma addresses in the trb_address_map radix tree needs | |
2444 | * TRB_SEGMENT_SIZE alignment, so we pick the greater alignment need. | |
0ebbab37 SS |
2445 | */ |
2446 | xhci->segment_pool = dma_pool_create("xHCI ring segments", dev, | |
84c1e40f | 2447 | TRB_SEGMENT_SIZE, TRB_SEGMENT_SIZE, xhci->page_size); |
d115b048 | 2448 | |
3ffbba95 | 2449 | /* See Table 46 and Note on Figure 55 */ |
3ffbba95 | 2450 | xhci->device_pool = dma_pool_create("xHCI input/output contexts", dev, |
d115b048 | 2451 | 2112, 64, xhci->page_size); |
3ffbba95 | 2452 | if (!xhci->segment_pool || !xhci->device_pool) |
0ebbab37 SS |
2453 | goto fail; |
2454 | ||
8df75f42 SS |
2455 | /* Linear stream context arrays don't have any boundary restrictions, |
2456 | * and only need to be 16-byte aligned. | |
2457 | */ | |
2458 | xhci->small_streams_pool = | |
2459 | dma_pool_create("xHCI 256 byte stream ctx arrays", | |
2460 | dev, SMALL_STREAM_ARRAY_SIZE, 16, 0); | |
2461 | xhci->medium_streams_pool = | |
2462 | dma_pool_create("xHCI 1KB stream ctx arrays", | |
2463 | dev, MEDIUM_STREAM_ARRAY_SIZE, 16, 0); | |
2464 | /* Any stream context array bigger than MEDIUM_STREAM_ARRAY_SIZE | |
22d45f01 | 2465 | * will be allocated with dma_alloc_coherent() |
8df75f42 SS |
2466 | */ |
2467 | ||
2468 | if (!xhci->small_streams_pool || !xhci->medium_streams_pool) | |
2469 | goto fail; | |
2470 | ||
0ebbab37 | 2471 | /* Set up the command ring to have one segments for now. */ |
f9c589e1 | 2472 | xhci->cmd_ring = xhci_ring_alloc(xhci, 1, 1, TYPE_COMMAND, 0, flags); |
0ebbab37 SS |
2473 | if (!xhci->cmd_ring) |
2474 | goto fail; | |
d195fcff XR |
2475 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2476 | "Allocated command ring at %p", xhci->cmd_ring); | |
2477 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "First segment DMA is 0x%llx", | |
700e2052 | 2478 | (unsigned long long)xhci->cmd_ring->first_seg->dma); |
0ebbab37 SS |
2479 | |
2480 | /* Set the address in the Command Ring Control register */ | |
f7b2e403 | 2481 | val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring); |
8e595a5d SS |
2482 | val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) | |
2483 | (xhci->cmd_ring->first_seg->dma & (u64) ~CMD_RING_RSVD_BITS) | | |
0ebbab37 | 2484 | xhci->cmd_ring->cycle_state; |
d195fcff | 2485 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
6fc091fb | 2486 | "// Setting command ring address to 0x%016llx", val_64); |
477632df | 2487 | xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring); |
0ebbab37 SS |
2488 | xhci_dbg_cmd_ptrs(xhci); |
2489 | ||
dbc33303 SS |
2490 | xhci->lpm_command = xhci_alloc_command(xhci, true, true, flags); |
2491 | if (!xhci->lpm_command) | |
2492 | goto fail; | |
2493 | ||
2494 | /* Reserve one command ring TRB for disabling LPM. | |
2495 | * Since the USB core grabs the shared usb_bus bandwidth mutex before | |
2496 | * disabling LPM, we only need to reserve one TRB for all devices. | |
2497 | */ | |
2498 | xhci->cmd_ring_reserved_trbs++; | |
2499 | ||
b0ba9720 | 2500 | val = readl(&xhci->cap_regs->db_off); |
0ebbab37 | 2501 | val &= DBOFF_MASK; |
d195fcff XR |
2502 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2503 | "// Doorbell array is located at offset 0x%x" | |
2504 | " from cap regs base addr", val); | |
c50a00f8 | 2505 | xhci->dba = (void __iomem *) xhci->cap_regs + val; |
0ebbab37 SS |
2506 | xhci_dbg_regs(xhci); |
2507 | xhci_print_run_regs(xhci); | |
2508 | /* Set ir_set to interrupt register set 0 */ | |
c50a00f8 | 2509 | xhci->ir_set = &xhci->run_regs->ir_set[0]; |
0ebbab37 SS |
2510 | |
2511 | /* | |
2512 | * Event ring setup: Allocate a normal ring, but also setup | |
2513 | * the event ring segment table (ERST). Section 4.9.3. | |
2514 | */ | |
d195fcff | 2515 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Allocating event ring"); |
186a7ef1 | 2516 | xhci->event_ring = xhci_ring_alloc(xhci, ERST_NUM_SEGS, 1, TYPE_EVENT, |
f9c589e1 | 2517 | 0, flags); |
0ebbab37 SS |
2518 | if (!xhci->event_ring) |
2519 | goto fail; | |
4daf9df5 | 2520 | if (xhci_check_trb_in_td_math(xhci) < 0) |
6648f29d | 2521 | goto fail; |
0ebbab37 | 2522 | |
22d45f01 SAS |
2523 | xhci->erst.entries = dma_alloc_coherent(dev, |
2524 | sizeof(struct xhci_erst_entry) * ERST_NUM_SEGS, &dma, | |
c95a9f83 | 2525 | flags); |
0ebbab37 SS |
2526 | if (!xhci->erst.entries) |
2527 | goto fail; | |
d195fcff XR |
2528 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2529 | "// Allocated event ring segment table at 0x%llx", | |
700e2052 | 2530 | (unsigned long long)dma); |
0ebbab37 SS |
2531 | |
2532 | memset(xhci->erst.entries, 0, sizeof(struct xhci_erst_entry)*ERST_NUM_SEGS); | |
2533 | xhci->erst.num_entries = ERST_NUM_SEGS; | |
2534 | xhci->erst.erst_dma_addr = dma; | |
d195fcff XR |
2535 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2536 | "Set ERST to 0; private num segs = %i, virt addr = %p, dma addr = 0x%llx", | |
0ebbab37 | 2537 | xhci->erst.num_entries, |
700e2052 GKH |
2538 | xhci->erst.entries, |
2539 | (unsigned long long)xhci->erst.erst_dma_addr); | |
0ebbab37 SS |
2540 | |
2541 | /* set ring base address and size for each segment table entry */ | |
2542 | for (val = 0, seg = xhci->event_ring->first_seg; val < ERST_NUM_SEGS; val++) { | |
2543 | struct xhci_erst_entry *entry = &xhci->erst.entries[val]; | |
28ccd296 ME |
2544 | entry->seg_addr = cpu_to_le64(seg->dma); |
2545 | entry->seg_size = cpu_to_le32(TRBS_PER_SEGMENT); | |
0ebbab37 SS |
2546 | entry->rsvd = 0; |
2547 | seg = seg->next; | |
2548 | } | |
2549 | ||
2550 | /* set ERST count with the number of entries in the segment table */ | |
b0ba9720 | 2551 | val = readl(&xhci->ir_set->erst_size); |
0ebbab37 SS |
2552 | val &= ERST_SIZE_MASK; |
2553 | val |= ERST_NUM_SEGS; | |
d195fcff XR |
2554 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2555 | "// Write ERST size = %i to ir_set 0 (some bits preserved)", | |
0ebbab37 | 2556 | val); |
204b7793 | 2557 | writel(val, &xhci->ir_set->erst_size); |
0ebbab37 | 2558 | |
d195fcff XR |
2559 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2560 | "// Set ERST entries to point to event ring."); | |
0ebbab37 | 2561 | /* set the segment table base address */ |
d195fcff XR |
2562 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2563 | "// Set ERST base address for ir_set 0 = 0x%llx", | |
700e2052 | 2564 | (unsigned long long)xhci->erst.erst_dma_addr); |
f7b2e403 | 2565 | val_64 = xhci_read_64(xhci, &xhci->ir_set->erst_base); |
8e595a5d SS |
2566 | val_64 &= ERST_PTR_MASK; |
2567 | val_64 |= (xhci->erst.erst_dma_addr & (u64) ~ERST_PTR_MASK); | |
477632df | 2568 | xhci_write_64(xhci, val_64, &xhci->ir_set->erst_base); |
0ebbab37 SS |
2569 | |
2570 | /* Set the event ring dequeue address */ | |
23e3be11 | 2571 | xhci_set_hc_event_deq(xhci); |
d195fcff XR |
2572 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2573 | "Wrote ERST address to ir_set 0."); | |
09ece30e | 2574 | xhci_print_ir_set(xhci, 0); |
0ebbab37 SS |
2575 | |
2576 | /* | |
2577 | * XXX: Might need to set the Interrupter Moderation Register to | |
2578 | * something other than the default (~1ms minimum between interrupts). | |
2579 | * See section 5.5.1.2. | |
2580 | */ | |
98871e94 | 2581 | for (i = 0; i < MAX_HC_SLOTS; i++) |
326b4810 | 2582 | xhci->devs[i] = NULL; |
98871e94 | 2583 | for (i = 0; i < USB_MAXCHILDREN; i++) { |
20b67cf5 | 2584 | xhci->bus_state[0].resume_done[i] = 0; |
f6ff0ac8 | 2585 | xhci->bus_state[1].resume_done[i] = 0; |
8b3d4570 SS |
2586 | /* Only the USB 2.0 completions will ever be used. */ |
2587 | init_completion(&xhci->bus_state[1].rexit_done[i]); | |
f6ff0ac8 | 2588 | } |
66d4eadd | 2589 | |
254c80a3 JY |
2590 | if (scratchpad_alloc(xhci, flags)) |
2591 | goto fail; | |
da6699ce SS |
2592 | if (xhci_setup_port_arrays(xhci, flags)) |
2593 | goto fail; | |
254c80a3 | 2594 | |
623bef9e SS |
2595 | /* Enable USB 3.0 device notifications for function remote wake, which |
2596 | * is necessary for allowing USB 3.0 devices to do remote wakeup from | |
2597 | * U3 (device suspend). | |
2598 | */ | |
b0ba9720 | 2599 | temp = readl(&xhci->op_regs->dev_notification); |
623bef9e SS |
2600 | temp &= ~DEV_NOTE_MASK; |
2601 | temp |= DEV_NOTE_FWAKE; | |
204b7793 | 2602 | writel(temp, &xhci->op_regs->dev_notification); |
623bef9e | 2603 | |
66d4eadd | 2604 | return 0; |
254c80a3 | 2605 | |
66d4eadd | 2606 | fail: |
159e1fcc SS |
2607 | xhci_halt(xhci); |
2608 | xhci_reset(xhci); | |
66d4eadd SS |
2609 | xhci_mem_cleanup(xhci); |
2610 | return -ENOMEM; | |
2611 | } |