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Commit | Line | Data |
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5fd54ace | 1 | // SPDX-License-Identifier: GPL-2.0 |
66d4eadd SS |
2 | /* |
3 | * xHCI host controller driver | |
4 | * | |
5 | * Copyright (C) 2008 Intel Corp. | |
6 | * | |
7 | * Author: Sarah Sharp | |
8 | * Some code borrowed from the Linux EHCI driver. | |
66d4eadd SS |
9 | */ |
10 | ||
11 | #include <linux/usb.h> | |
0ebbab37 | 12 | #include <linux/pci.h> |
5a0e3ad6 | 13 | #include <linux/slab.h> |
527c6d7f | 14 | #include <linux/dmapool.h> |
008eb957 | 15 | #include <linux/dma-mapping.h> |
66d4eadd SS |
16 | |
17 | #include "xhci.h" | |
3a7fa5be | 18 | #include "xhci-trace.h" |
02b6fdc2 | 19 | #include "xhci-debugfs.h" |
66d4eadd | 20 | |
0ebbab37 SS |
21 | /* |
22 | * Allocates a generic ring segment from the ring pool, sets the dma address, | |
23 | * initializes the segment to zero, and sets the private next pointer to NULL. | |
24 | * | |
25 | * Section 4.11.1.1: | |
26 | * "All components of all Command and Transfer TRBs shall be initialized to '0'" | |
27 | */ | |
186a7ef1 | 28 | static struct xhci_segment *xhci_segment_alloc(struct xhci_hcd *xhci, |
f9c589e1 MN |
29 | unsigned int cycle_state, |
30 | unsigned int max_packet, | |
31 | gfp_t flags) | |
0ebbab37 SS |
32 | { |
33 | struct xhci_segment *seg; | |
34 | dma_addr_t dma; | |
186a7ef1 | 35 | int i; |
a965315e | 36 | struct device *dev = xhci_to_hcd(xhci)->self.sysdev; |
0ebbab37 | 37 | |
a965315e | 38 | seg = kzalloc_node(sizeof(*seg), flags, dev_to_node(dev)); |
0ebbab37 | 39 | if (!seg) |
326b4810 | 40 | return NULL; |
0ebbab37 | 41 | |
84c1eeb0 | 42 | seg->trbs = dma_pool_zalloc(xhci->segment_pool, flags, &dma); |
0ebbab37 SS |
43 | if (!seg->trbs) { |
44 | kfree(seg); | |
326b4810 | 45 | return NULL; |
0ebbab37 | 46 | } |
0ebbab37 | 47 | |
f9c589e1 | 48 | if (max_packet) { |
a965315e AW |
49 | seg->bounce_buf = kzalloc_node(max_packet, flags, |
50 | dev_to_node(dev)); | |
f9c589e1 MN |
51 | if (!seg->bounce_buf) { |
52 | dma_pool_free(xhci->segment_pool, seg->trbs, dma); | |
53 | kfree(seg); | |
54 | return NULL; | |
55 | } | |
56 | } | |
186a7ef1 AX |
57 | /* If the cycle state is 0, set the cycle bit to 1 for all the TRBs */ |
58 | if (cycle_state == 0) { | |
59 | for (i = 0; i < TRBS_PER_SEGMENT; i++) | |
58719487 | 60 | seg->trbs[i].link.control |= cpu_to_le32(TRB_CYCLE); |
186a7ef1 | 61 | } |
0ebbab37 SS |
62 | seg->dma = dma; |
63 | seg->next = NULL; | |
64 | ||
65 | return seg; | |
66 | } | |
67 | ||
68 | static void xhci_segment_free(struct xhci_hcd *xhci, struct xhci_segment *seg) | |
69 | { | |
0ebbab37 | 70 | if (seg->trbs) { |
0ebbab37 SS |
71 | dma_pool_free(xhci->segment_pool, seg->trbs, seg->dma); |
72 | seg->trbs = NULL; | |
73 | } | |
f9c589e1 | 74 | kfree(seg->bounce_buf); |
0ebbab37 SS |
75 | kfree(seg); |
76 | } | |
77 | ||
70d43601 AX |
78 | static void xhci_free_segments_for_ring(struct xhci_hcd *xhci, |
79 | struct xhci_segment *first) | |
80 | { | |
81 | struct xhci_segment *seg; | |
82 | ||
83 | seg = first->next; | |
84 | while (seg != first) { | |
85 | struct xhci_segment *next = seg->next; | |
86 | xhci_segment_free(xhci, seg); | |
87 | seg = next; | |
88 | } | |
89 | xhci_segment_free(xhci, first); | |
90 | } | |
91 | ||
0ebbab37 SS |
92 | /* |
93 | * Make the prev segment point to the next segment. | |
94 | * | |
95 | * Change the last TRB in the prev segment to be a Link TRB which points to the | |
96 | * DMA address of the next segment. The caller needs to set any Link TRB | |
97 | * related flags, such as End TRB, Toggle Cycle, and no snoop. | |
98 | */ | |
e3bc8004 MN |
99 | static void xhci_link_segments(struct xhci_segment *prev, |
100 | struct xhci_segment *next, | |
101 | enum xhci_ring_type type, bool chain_links) | |
0ebbab37 SS |
102 | { |
103 | u32 val; | |
104 | ||
105 | if (!prev || !next) | |
106 | return; | |
107 | prev->next = next; | |
3b72fca0 | 108 | if (type != TYPE_EVENT) { |
f5960b69 ME |
109 | prev->trbs[TRBS_PER_SEGMENT-1].link.segment_ptr = |
110 | cpu_to_le64(next->dma); | |
0ebbab37 SS |
111 | |
112 | /* Set the last TRB in the segment to have a TRB type ID of Link TRB */ | |
28ccd296 | 113 | val = le32_to_cpu(prev->trbs[TRBS_PER_SEGMENT-1].link.control); |
0ebbab37 SS |
114 | val &= ~TRB_TYPE_BITMASK; |
115 | val |= TRB_TYPE(TRB_LINK); | |
e3bc8004 | 116 | if (chain_links) |
b0567b3f | 117 | val |= TRB_CHAIN; |
28ccd296 | 118 | prev->trbs[TRBS_PER_SEGMENT-1].link.control = cpu_to_le32(val); |
0ebbab37 | 119 | } |
0ebbab37 SS |
120 | } |
121 | ||
8dfec614 AX |
122 | /* |
123 | * Link the ring to the new segments. | |
124 | * Set Toggle Cycle for the new ring if needed. | |
125 | */ | |
126 | static void xhci_link_rings(struct xhci_hcd *xhci, struct xhci_ring *ring, | |
127 | struct xhci_segment *first, struct xhci_segment *last, | |
128 | unsigned int num_segs) | |
129 | { | |
130 | struct xhci_segment *next; | |
e3bc8004 | 131 | bool chain_links; |
8dfec614 AX |
132 | |
133 | if (!ring || !first || !last) | |
134 | return; | |
135 | ||
e3bc8004 MN |
136 | /* Set chain bit for 0.95 hosts, and for isoc rings on AMD 0.96 host */ |
137 | chain_links = !!(xhci_link_trb_quirk(xhci) || | |
138 | (ring->type == TYPE_ISOC && | |
139 | (xhci->quirks & XHCI_AMD_0x96_HOST))); | |
140 | ||
8dfec614 | 141 | next = ring->enq_seg->next; |
e3bc8004 MN |
142 | xhci_link_segments(ring->enq_seg, first, ring->type, chain_links); |
143 | xhci_link_segments(last, next, ring->type, chain_links); | |
8dfec614 AX |
144 | ring->num_segs += num_segs; |
145 | ring->num_trbs_free += (TRBS_PER_SEGMENT - 1) * num_segs; | |
146 | ||
147 | if (ring->type != TYPE_EVENT && ring->enq_seg == ring->last_seg) { | |
148 | ring->last_seg->trbs[TRBS_PER_SEGMENT-1].link.control | |
149 | &= ~cpu_to_le32(LINK_TOGGLE); | |
150 | last->trbs[TRBS_PER_SEGMENT-1].link.control | |
151 | |= cpu_to_le32(LINK_TOGGLE); | |
152 | ring->last_seg = last; | |
153 | } | |
154 | } | |
155 | ||
15341303 GH |
156 | /* |
157 | * We need a radix tree for mapping physical addresses of TRBs to which stream | |
158 | * ID they belong to. We need to do this because the host controller won't tell | |
159 | * us which stream ring the TRB came from. We could store the stream ID in an | |
160 | * event data TRB, but that doesn't help us for the cancellation case, since the | |
161 | * endpoint may stop before it reaches that event data TRB. | |
162 | * | |
163 | * The radix tree maps the upper portion of the TRB DMA address to a ring | |
164 | * segment that has the same upper portion of DMA addresses. For example, say I | |
84c1e40f | 165 | * have segments of size 1KB, that are always 1KB aligned. A segment may |
15341303 GH |
166 | * start at 0x10c91000 and end at 0x10c913f0. If I use the upper 10 bits, the |
167 | * key to the stream ID is 0x43244. I can use the DMA address of the TRB to | |
168 | * pass the radix tree a key to get the right stream ID: | |
169 | * | |
170 | * 0x10c90fff >> 10 = 0x43243 | |
171 | * 0x10c912c0 >> 10 = 0x43244 | |
172 | * 0x10c91400 >> 10 = 0x43245 | |
173 | * | |
174 | * Obviously, only those TRBs with DMA addresses that are within the segment | |
175 | * will make the radix tree return the stream ID for that ring. | |
176 | * | |
177 | * Caveats for the radix tree: | |
178 | * | |
179 | * The radix tree uses an unsigned long as a key pair. On 32-bit systems, an | |
180 | * unsigned long will be 32-bits; on a 64-bit system an unsigned long will be | |
181 | * 64-bits. Since we only request 32-bit DMA addresses, we can use that as the | |
182 | * key on 32-bit or 64-bit systems (it would also be fine if we asked for 64-bit | |
183 | * PCI DMA addresses on a 64-bit system). There might be a problem on 32-bit | |
184 | * extended systems (where the DMA address can be bigger than 32-bits), | |
185 | * if we allow the PCI dma mask to be bigger than 32-bits. So don't do that. | |
186 | */ | |
d5734223 SS |
187 | static int xhci_insert_segment_mapping(struct radix_tree_root *trb_address_map, |
188 | struct xhci_ring *ring, | |
189 | struct xhci_segment *seg, | |
190 | gfp_t mem_flags) | |
15341303 | 191 | { |
15341303 GH |
192 | unsigned long key; |
193 | int ret; | |
194 | ||
d5734223 SS |
195 | key = (unsigned long)(seg->dma >> TRB_SEGMENT_SHIFT); |
196 | /* Skip any segments that were already added. */ | |
197 | if (radix_tree_lookup(trb_address_map, key)) | |
15341303 GH |
198 | return 0; |
199 | ||
d5734223 SS |
200 | ret = radix_tree_maybe_preload(mem_flags); |
201 | if (ret) | |
202 | return ret; | |
203 | ret = radix_tree_insert(trb_address_map, | |
204 | key, ring); | |
205 | radix_tree_preload_end(); | |
206 | return ret; | |
207 | } | |
15341303 | 208 | |
d5734223 SS |
209 | static void xhci_remove_segment_mapping(struct radix_tree_root *trb_address_map, |
210 | struct xhci_segment *seg) | |
211 | { | |
212 | unsigned long key; | |
213 | ||
214 | key = (unsigned long)(seg->dma >> TRB_SEGMENT_SHIFT); | |
215 | if (radix_tree_lookup(trb_address_map, key)) | |
216 | radix_tree_delete(trb_address_map, key); | |
217 | } | |
218 | ||
219 | static int xhci_update_stream_segment_mapping( | |
220 | struct radix_tree_root *trb_address_map, | |
221 | struct xhci_ring *ring, | |
222 | struct xhci_segment *first_seg, | |
223 | struct xhci_segment *last_seg, | |
224 | gfp_t mem_flags) | |
225 | { | |
226 | struct xhci_segment *seg; | |
227 | struct xhci_segment *failed_seg; | |
228 | int ret; | |
229 | ||
230 | if (WARN_ON_ONCE(trb_address_map == NULL)) | |
231 | return 0; | |
232 | ||
233 | seg = first_seg; | |
234 | do { | |
235 | ret = xhci_insert_segment_mapping(trb_address_map, | |
236 | ring, seg, mem_flags); | |
15341303 | 237 | if (ret) |
d5734223 SS |
238 | goto remove_streams; |
239 | if (seg == last_seg) | |
240 | return 0; | |
15341303 | 241 | seg = seg->next; |
d5734223 | 242 | } while (seg != first_seg); |
15341303 GH |
243 | |
244 | return 0; | |
d5734223 SS |
245 | |
246 | remove_streams: | |
247 | failed_seg = seg; | |
248 | seg = first_seg; | |
249 | do { | |
250 | xhci_remove_segment_mapping(trb_address_map, seg); | |
251 | if (seg == failed_seg) | |
252 | return ret; | |
253 | seg = seg->next; | |
254 | } while (seg != first_seg); | |
255 | ||
256 | return ret; | |
15341303 GH |
257 | } |
258 | ||
259 | static void xhci_remove_stream_mapping(struct xhci_ring *ring) | |
260 | { | |
261 | struct xhci_segment *seg; | |
15341303 GH |
262 | |
263 | if (WARN_ON_ONCE(ring->trb_address_map == NULL)) | |
264 | return; | |
265 | ||
266 | seg = ring->first_seg; | |
267 | do { | |
d5734223 | 268 | xhci_remove_segment_mapping(ring->trb_address_map, seg); |
15341303 GH |
269 | seg = seg->next; |
270 | } while (seg != ring->first_seg); | |
271 | } | |
272 | ||
d5734223 SS |
273 | static int xhci_update_stream_mapping(struct xhci_ring *ring, gfp_t mem_flags) |
274 | { | |
275 | return xhci_update_stream_segment_mapping(ring->trb_address_map, ring, | |
276 | ring->first_seg, ring->last_seg, mem_flags); | |
277 | } | |
278 | ||
0ebbab37 | 279 | /* XXX: Do we need the hcd structure in all these functions? */ |
f94e0186 | 280 | void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring) |
0ebbab37 | 281 | { |
0e6c7f74 | 282 | if (!ring) |
0ebbab37 | 283 | return; |
70d43601 | 284 | |
b2d6edbb LB |
285 | trace_xhci_ring_free(ring); |
286 | ||
15341303 GH |
287 | if (ring->first_seg) { |
288 | if (ring->type == TYPE_STREAM) | |
289 | xhci_remove_stream_mapping(ring); | |
70d43601 | 290 | xhci_free_segments_for_ring(xhci, ring->first_seg); |
15341303 | 291 | } |
70d43601 | 292 | |
0ebbab37 SS |
293 | kfree(ring); |
294 | } | |
295 | ||
ac286428 MN |
296 | void xhci_initialize_ring_info(struct xhci_ring *ring, |
297 | unsigned int cycle_state) | |
74f9fe21 SS |
298 | { |
299 | /* The ring is empty, so the enqueue pointer == dequeue pointer */ | |
300 | ring->enqueue = ring->first_seg->trbs; | |
301 | ring->enq_seg = ring->first_seg; | |
302 | ring->dequeue = ring->enqueue; | |
303 | ring->deq_seg = ring->first_seg; | |
304 | /* The ring is initialized to 0. The producer must write 1 to the cycle | |
305 | * bit to handover ownership of the TRB, so PCS = 1. The consumer must | |
306 | * compare CCS to the cycle bit to check ownership, so CCS = 1. | |
186a7ef1 AX |
307 | * |
308 | * New rings are initialized with cycle state equal to 1; if we are | |
309 | * handling ring expansion, set the cycle state equal to the old ring. | |
74f9fe21 | 310 | */ |
186a7ef1 | 311 | ring->cycle_state = cycle_state; |
b008df60 AX |
312 | |
313 | /* | |
314 | * Each segment has a link TRB, and leave an extra TRB for SW | |
315 | * accounting purpose | |
316 | */ | |
317 | ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1; | |
74f9fe21 SS |
318 | } |
319 | ||
70d43601 AX |
320 | /* Allocate segments and link them for a ring */ |
321 | static int xhci_alloc_segments_for_ring(struct xhci_hcd *xhci, | |
322 | struct xhci_segment **first, struct xhci_segment **last, | |
186a7ef1 | 323 | unsigned int num_segs, unsigned int cycle_state, |
f9c589e1 | 324 | enum xhci_ring_type type, unsigned int max_packet, gfp_t flags) |
70d43601 AX |
325 | { |
326 | struct xhci_segment *prev; | |
e3bc8004 MN |
327 | bool chain_links; |
328 | ||
329 | /* Set chain bit for 0.95 hosts, and for isoc rings on AMD 0.96 host */ | |
330 | chain_links = !!(xhci_link_trb_quirk(xhci) || | |
331 | (type == TYPE_ISOC && | |
332 | (xhci->quirks & XHCI_AMD_0x96_HOST))); | |
70d43601 | 333 | |
f9c589e1 | 334 | prev = xhci_segment_alloc(xhci, cycle_state, max_packet, flags); |
70d43601 AX |
335 | if (!prev) |
336 | return -ENOMEM; | |
337 | num_segs--; | |
338 | ||
339 | *first = prev; | |
340 | while (num_segs > 0) { | |
341 | struct xhci_segment *next; | |
342 | ||
f9c589e1 | 343 | next = xhci_segment_alloc(xhci, cycle_state, max_packet, flags); |
70d43601 | 344 | if (!next) { |
68e5254a JW |
345 | prev = *first; |
346 | while (prev) { | |
347 | next = prev->next; | |
348 | xhci_segment_free(xhci, prev); | |
349 | prev = next; | |
350 | } | |
70d43601 AX |
351 | return -ENOMEM; |
352 | } | |
e3bc8004 | 353 | xhci_link_segments(prev, next, type, chain_links); |
70d43601 AX |
354 | |
355 | prev = next; | |
356 | num_segs--; | |
357 | } | |
e3bc8004 | 358 | xhci_link_segments(prev, *first, type, chain_links); |
70d43601 AX |
359 | *last = prev; |
360 | ||
361 | return 0; | |
362 | } | |
363 | ||
c3fa4e04 | 364 | /* |
0ebbab37 SS |
365 | * Create a new ring with zero or more segments. |
366 | * | |
367 | * Link each segment together into a ring. | |
368 | * Set the end flag and the cycle toggle bit on the last segment. | |
369 | * See section 4.9.1 and figures 15 and 16. | |
370 | */ | |
67d2ea9f | 371 | struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci, |
186a7ef1 | 372 | unsigned int num_segs, unsigned int cycle_state, |
f9c589e1 | 373 | enum xhci_ring_type type, unsigned int max_packet, gfp_t flags) |
0ebbab37 SS |
374 | { |
375 | struct xhci_ring *ring; | |
70d43601 | 376 | int ret; |
a965315e | 377 | struct device *dev = xhci_to_hcd(xhci)->self.sysdev; |
0ebbab37 | 378 | |
a965315e | 379 | ring = kzalloc_node(sizeof(*ring), flags, dev_to_node(dev)); |
0ebbab37 | 380 | if (!ring) |
326b4810 | 381 | return NULL; |
0ebbab37 | 382 | |
3fe4fe08 | 383 | ring->num_segs = num_segs; |
f9c589e1 | 384 | ring->bounce_buf_len = max_packet; |
d0e96f5a | 385 | INIT_LIST_HEAD(&ring->td_list); |
3b72fca0 | 386 | ring->type = type; |
0ebbab37 SS |
387 | if (num_segs == 0) |
388 | return ring; | |
389 | ||
70d43601 | 390 | ret = xhci_alloc_segments_for_ring(xhci, &ring->first_seg, |
f9c589e1 MN |
391 | &ring->last_seg, num_segs, cycle_state, type, |
392 | max_packet, flags); | |
70d43601 | 393 | if (ret) |
0ebbab37 | 394 | goto fail; |
0ebbab37 | 395 | |
3b72fca0 AX |
396 | /* Only event ring does not use link TRB */ |
397 | if (type != TYPE_EVENT) { | |
0ebbab37 | 398 | /* See section 4.9.2.1 and 6.4.4.1 */ |
70d43601 | 399 | ring->last_seg->trbs[TRBS_PER_SEGMENT - 1].link.control |= |
f5960b69 | 400 | cpu_to_le32(LINK_TOGGLE); |
0ebbab37 | 401 | } |
186a7ef1 | 402 | xhci_initialize_ring_info(ring, cycle_state); |
b2d6edbb | 403 | trace_xhci_ring_alloc(ring); |
0ebbab37 SS |
404 | return ring; |
405 | ||
406 | fail: | |
68e5254a | 407 | kfree(ring); |
326b4810 | 408 | return NULL; |
0ebbab37 SS |
409 | } |
410 | ||
c5628a2a | 411 | void xhci_free_endpoint_ring(struct xhci_hcd *xhci, |
412566bd SS |
412 | struct xhci_virt_device *virt_dev, |
413 | unsigned int ep_index) | |
414 | { | |
c5628a2a | 415 | xhci_ring_free(xhci, virt_dev->eps[ep_index].ring); |
412566bd SS |
416 | virt_dev->eps[ep_index].ring = NULL; |
417 | } | |
418 | ||
8dfec614 AX |
419 | /* |
420 | * Expand an existing ring. | |
c5628a2a | 421 | * Allocate a new ring which has same segment numbers and link the two rings. |
8dfec614 AX |
422 | */ |
423 | int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring, | |
424 | unsigned int num_trbs, gfp_t flags) | |
425 | { | |
426 | struct xhci_segment *first; | |
427 | struct xhci_segment *last; | |
428 | unsigned int num_segs; | |
429 | unsigned int num_segs_needed; | |
430 | int ret; | |
431 | ||
432 | num_segs_needed = (num_trbs + (TRBS_PER_SEGMENT - 1) - 1) / | |
433 | (TRBS_PER_SEGMENT - 1); | |
434 | ||
435 | /* Allocate number of segments we needed, or double the ring size */ | |
436 | num_segs = ring->num_segs > num_segs_needed ? | |
437 | ring->num_segs : num_segs_needed; | |
438 | ||
439 | ret = xhci_alloc_segments_for_ring(xhci, &first, &last, | |
f9c589e1 MN |
440 | num_segs, ring->cycle_state, ring->type, |
441 | ring->bounce_buf_len, flags); | |
8dfec614 AX |
442 | if (ret) |
443 | return -ENOMEM; | |
444 | ||
d5734223 SS |
445 | if (ring->type == TYPE_STREAM) |
446 | ret = xhci_update_stream_segment_mapping(ring->trb_address_map, | |
447 | ring, first, last, flags); | |
448 | if (ret) { | |
449 | struct xhci_segment *next; | |
450 | do { | |
451 | next = first->next; | |
452 | xhci_segment_free(xhci, first); | |
453 | if (first == last) | |
454 | break; | |
455 | first = next; | |
456 | } while (true); | |
457 | return ret; | |
458 | } | |
459 | ||
8dfec614 | 460 | xhci_link_rings(xhci, ring, first, last, num_segs); |
b2d6edbb | 461 | trace_xhci_ring_expansion(ring); |
68ffb011 XR |
462 | xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion, |
463 | "ring expansion succeed, now has %d segments", | |
8dfec614 AX |
464 | ring->num_segs); |
465 | ||
466 | return 0; | |
467 | } | |
468 | ||
67d2ea9f | 469 | struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci, |
d115b048 JY |
470 | int type, gfp_t flags) |
471 | { | |
29f9d54b | 472 | struct xhci_container_ctx *ctx; |
a965315e | 473 | struct device *dev = xhci_to_hcd(xhci)->self.sysdev; |
29f9d54b SS |
474 | |
475 | if ((type != XHCI_CTX_TYPE_DEVICE) && (type != XHCI_CTX_TYPE_INPUT)) | |
476 | return NULL; | |
477 | ||
a965315e | 478 | ctx = kzalloc_node(sizeof(*ctx), flags, dev_to_node(dev)); |
d115b048 JY |
479 | if (!ctx) |
480 | return NULL; | |
481 | ||
d115b048 JY |
482 | ctx->type = type; |
483 | ctx->size = HCC_64BYTE_CONTEXT(xhci->hcc_params) ? 2048 : 1024; | |
484 | if (type == XHCI_CTX_TYPE_INPUT) | |
485 | ctx->size += CTX_SIZE(xhci->hcc_params); | |
486 | ||
84c1eeb0 | 487 | ctx->bytes = dma_pool_zalloc(xhci->device_pool, flags, &ctx->dma); |
025f880c MN |
488 | if (!ctx->bytes) { |
489 | kfree(ctx); | |
490 | return NULL; | |
491 | } | |
d115b048 JY |
492 | return ctx; |
493 | } | |
494 | ||
67d2ea9f | 495 | void xhci_free_container_ctx(struct xhci_hcd *xhci, |
d115b048 JY |
496 | struct xhci_container_ctx *ctx) |
497 | { | |
a1d78c16 SS |
498 | if (!ctx) |
499 | return; | |
d115b048 JY |
500 | dma_pool_free(xhci->device_pool, ctx->bytes, ctx->dma); |
501 | kfree(ctx); | |
502 | } | |
503 | ||
4daf9df5 | 504 | struct xhci_input_control_ctx *xhci_get_input_control_ctx( |
d115b048 JY |
505 | struct xhci_container_ctx *ctx) |
506 | { | |
92f8e767 SS |
507 | if (ctx->type != XHCI_CTX_TYPE_INPUT) |
508 | return NULL; | |
509 | ||
d115b048 JY |
510 | return (struct xhci_input_control_ctx *)ctx->bytes; |
511 | } | |
512 | ||
513 | struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, | |
514 | struct xhci_container_ctx *ctx) | |
515 | { | |
516 | if (ctx->type == XHCI_CTX_TYPE_DEVICE) | |
517 | return (struct xhci_slot_ctx *)ctx->bytes; | |
518 | ||
519 | return (struct xhci_slot_ctx *) | |
520 | (ctx->bytes + CTX_SIZE(xhci->hcc_params)); | |
521 | } | |
522 | ||
523 | struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, | |
524 | struct xhci_container_ctx *ctx, | |
525 | unsigned int ep_index) | |
526 | { | |
527 | /* increment ep index by offset of start of ep ctx array */ | |
528 | ep_index++; | |
529 | if (ctx->type == XHCI_CTX_TYPE_INPUT) | |
530 | ep_index++; | |
531 | ||
532 | return (struct xhci_ep_ctx *) | |
533 | (ctx->bytes + (ep_index * CTX_SIZE(xhci->hcc_params))); | |
534 | } | |
535 | ||
8df75f42 SS |
536 | |
537 | /***************** Streams structures manipulation *************************/ | |
538 | ||
8212a49d | 539 | static void xhci_free_stream_ctx(struct xhci_hcd *xhci, |
8df75f42 SS |
540 | unsigned int num_stream_ctxs, |
541 | struct xhci_stream_ctx *stream_ctx, dma_addr_t dma) | |
542 | { | |
4c39d4b9 | 543 | struct device *dev = xhci_to_hcd(xhci)->self.sysdev; |
ee4aa54b | 544 | size_t size = sizeof(struct xhci_stream_ctx) * num_stream_ctxs; |
8df75f42 | 545 | |
ee4aa54b HG |
546 | if (size > MEDIUM_STREAM_ARRAY_SIZE) |
547 | dma_free_coherent(dev, size, | |
8df75f42 | 548 | stream_ctx, dma); |
ee4aa54b | 549 | else if (size <= SMALL_STREAM_ARRAY_SIZE) |
8df75f42 SS |
550 | return dma_pool_free(xhci->small_streams_pool, |
551 | stream_ctx, dma); | |
552 | else | |
553 | return dma_pool_free(xhci->medium_streams_pool, | |
554 | stream_ctx, dma); | |
555 | } | |
556 | ||
557 | /* | |
558 | * The stream context array for each endpoint with bulk streams enabled can | |
559 | * vary in size, based on: | |
560 | * - how many streams the endpoint supports, | |
561 | * - the maximum primary stream array size the host controller supports, | |
562 | * - and how many streams the device driver asks for. | |
563 | * | |
564 | * The stream context array must be a power of 2, and can be as small as | |
565 | * 64 bytes or as large as 1MB. | |
566 | */ | |
8212a49d | 567 | static struct xhci_stream_ctx *xhci_alloc_stream_ctx(struct xhci_hcd *xhci, |
8df75f42 SS |
568 | unsigned int num_stream_ctxs, dma_addr_t *dma, |
569 | gfp_t mem_flags) | |
570 | { | |
4c39d4b9 | 571 | struct device *dev = xhci_to_hcd(xhci)->self.sysdev; |
ee4aa54b | 572 | size_t size = sizeof(struct xhci_stream_ctx) * num_stream_ctxs; |
8df75f42 | 573 | |
ee4aa54b HG |
574 | if (size > MEDIUM_STREAM_ARRAY_SIZE) |
575 | return dma_alloc_coherent(dev, size, | |
22d45f01 | 576 | dma, mem_flags); |
ee4aa54b | 577 | else if (size <= SMALL_STREAM_ARRAY_SIZE) |
8df75f42 SS |
578 | return dma_pool_alloc(xhci->small_streams_pool, |
579 | mem_flags, dma); | |
580 | else | |
581 | return dma_pool_alloc(xhci->medium_streams_pool, | |
582 | mem_flags, dma); | |
583 | } | |
584 | ||
e9df17eb SS |
585 | struct xhci_ring *xhci_dma_to_transfer_ring( |
586 | struct xhci_virt_ep *ep, | |
587 | u64 address) | |
588 | { | |
589 | if (ep->ep_state & EP_HAS_STREAMS) | |
590 | return radix_tree_lookup(&ep->stream_info->trb_address_map, | |
eb8ccd2b | 591 | address >> TRB_SEGMENT_SHIFT); |
e9df17eb SS |
592 | return ep->ring; |
593 | } | |
594 | ||
e9df17eb SS |
595 | struct xhci_ring *xhci_stream_id_to_ring( |
596 | struct xhci_virt_device *dev, | |
597 | unsigned int ep_index, | |
598 | unsigned int stream_id) | |
599 | { | |
600 | struct xhci_virt_ep *ep = &dev->eps[ep_index]; | |
601 | ||
602 | if (stream_id == 0) | |
603 | return ep->ring; | |
604 | if (!ep->stream_info) | |
605 | return NULL; | |
606 | ||
313db3d6 | 607 | if (stream_id >= ep->stream_info->num_streams) |
e9df17eb SS |
608 | return NULL; |
609 | return ep->stream_info->stream_rings[stream_id]; | |
610 | } | |
611 | ||
8df75f42 SS |
612 | /* |
613 | * Change an endpoint's internal structure so it supports stream IDs. The | |
614 | * number of requested streams includes stream 0, which cannot be used by device | |
615 | * drivers. | |
616 | * | |
617 | * The number of stream contexts in the stream context array may be bigger than | |
618 | * the number of streams the driver wants to use. This is because the number of | |
619 | * stream context array entries must be a power of two. | |
8df75f42 SS |
620 | */ |
621 | struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci, | |
622 | unsigned int num_stream_ctxs, | |
f9c589e1 MN |
623 | unsigned int num_streams, |
624 | unsigned int max_packet, gfp_t mem_flags) | |
8df75f42 SS |
625 | { |
626 | struct xhci_stream_info *stream_info; | |
627 | u32 cur_stream; | |
628 | struct xhci_ring *cur_ring; | |
8df75f42 SS |
629 | u64 addr; |
630 | int ret; | |
a965315e | 631 | struct device *dev = xhci_to_hcd(xhci)->self.sysdev; |
8df75f42 SS |
632 | |
633 | xhci_dbg(xhci, "Allocating %u streams and %u " | |
634 | "stream context array entries.\n", | |
635 | num_streams, num_stream_ctxs); | |
636 | if (xhci->cmd_ring_reserved_trbs == MAX_RSVD_CMD_TRBS) { | |
637 | xhci_dbg(xhci, "Command ring has no reserved TRBs available\n"); | |
638 | return NULL; | |
639 | } | |
640 | xhci->cmd_ring_reserved_trbs++; | |
641 | ||
a965315e AW |
642 | stream_info = kzalloc_node(sizeof(*stream_info), mem_flags, |
643 | dev_to_node(dev)); | |
8df75f42 SS |
644 | if (!stream_info) |
645 | goto cleanup_trbs; | |
646 | ||
647 | stream_info->num_streams = num_streams; | |
648 | stream_info->num_stream_ctxs = num_stream_ctxs; | |
649 | ||
650 | /* Initialize the array of virtual pointers to stream rings. */ | |
a965315e AW |
651 | stream_info->stream_rings = kcalloc_node( |
652 | num_streams, sizeof(struct xhci_ring *), mem_flags, | |
653 | dev_to_node(dev)); | |
8df75f42 SS |
654 | if (!stream_info->stream_rings) |
655 | goto cleanup_info; | |
656 | ||
657 | /* Initialize the array of DMA addresses for stream rings for the HW. */ | |
658 | stream_info->stream_ctx_array = xhci_alloc_stream_ctx(xhci, | |
659 | num_stream_ctxs, &stream_info->ctx_array_dma, | |
660 | mem_flags); | |
661 | if (!stream_info->stream_ctx_array) | |
662 | goto cleanup_ctx; | |
663 | memset(stream_info->stream_ctx_array, 0, | |
664 | sizeof(struct xhci_stream_ctx)*num_stream_ctxs); | |
665 | ||
666 | /* Allocate everything needed to free the stream rings later */ | |
667 | stream_info->free_streams_command = | |
14d49b7a | 668 | xhci_alloc_command_with_ctx(xhci, true, mem_flags); |
8df75f42 SS |
669 | if (!stream_info->free_streams_command) |
670 | goto cleanup_ctx; | |
671 | ||
672 | INIT_RADIX_TREE(&stream_info->trb_address_map, GFP_ATOMIC); | |
673 | ||
674 | /* Allocate rings for all the streams that the driver will use, | |
675 | * and add their segment DMA addresses to the radix tree. | |
676 | * Stream 0 is reserved. | |
677 | */ | |
f9c589e1 | 678 | |
8df75f42 SS |
679 | for (cur_stream = 1; cur_stream < num_streams; cur_stream++) { |
680 | stream_info->stream_rings[cur_stream] = | |
f9c589e1 MN |
681 | xhci_ring_alloc(xhci, 2, 1, TYPE_STREAM, max_packet, |
682 | mem_flags); | |
8df75f42 SS |
683 | cur_ring = stream_info->stream_rings[cur_stream]; |
684 | if (!cur_ring) | |
685 | goto cleanup_rings; | |
e9df17eb | 686 | cur_ring->stream_id = cur_stream; |
15341303 | 687 | cur_ring->trb_address_map = &stream_info->trb_address_map; |
8df75f42 SS |
688 | /* Set deq ptr, cycle bit, and stream context type */ |
689 | addr = cur_ring->first_seg->dma | | |
690 | SCT_FOR_CTX(SCT_PRI_TR) | | |
691 | cur_ring->cycle_state; | |
f5960b69 ME |
692 | stream_info->stream_ctx_array[cur_stream].stream_ring = |
693 | cpu_to_le64(addr); | |
8df75f42 SS |
694 | xhci_dbg(xhci, "Setting stream %d ring ptr to 0x%08llx\n", |
695 | cur_stream, (unsigned long long) addr); | |
696 | ||
15341303 | 697 | ret = xhci_update_stream_mapping(cur_ring, mem_flags); |
8df75f42 SS |
698 | if (ret) { |
699 | xhci_ring_free(xhci, cur_ring); | |
700 | stream_info->stream_rings[cur_stream] = NULL; | |
701 | goto cleanup_rings; | |
702 | } | |
703 | } | |
704 | /* Leave the other unused stream ring pointers in the stream context | |
705 | * array initialized to zero. This will cause the xHC to give us an | |
706 | * error if the device asks for a stream ID we don't have setup (if it | |
707 | * was any other way, the host controller would assume the ring is | |
708 | * "empty" and wait forever for data to be queued to that stream ID). | |
709 | */ | |
8df75f42 SS |
710 | |
711 | return stream_info; | |
712 | ||
713 | cleanup_rings: | |
714 | for (cur_stream = 1; cur_stream < num_streams; cur_stream++) { | |
715 | cur_ring = stream_info->stream_rings[cur_stream]; | |
716 | if (cur_ring) { | |
8df75f42 SS |
717 | xhci_ring_free(xhci, cur_ring); |
718 | stream_info->stream_rings[cur_stream] = NULL; | |
719 | } | |
720 | } | |
721 | xhci_free_command(xhci, stream_info->free_streams_command); | |
722 | cleanup_ctx: | |
723 | kfree(stream_info->stream_rings); | |
724 | cleanup_info: | |
725 | kfree(stream_info); | |
726 | cleanup_trbs: | |
727 | xhci->cmd_ring_reserved_trbs--; | |
728 | return NULL; | |
729 | } | |
730 | /* | |
731 | * Sets the MaxPStreams field and the Linear Stream Array field. | |
732 | * Sets the dequeue pointer to the stream context array. | |
733 | */ | |
734 | void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci, | |
735 | struct xhci_ep_ctx *ep_ctx, | |
736 | struct xhci_stream_info *stream_info) | |
737 | { | |
738 | u32 max_primary_streams; | |
739 | /* MaxPStreams is the number of stream context array entries, not the | |
740 | * number we're actually using. Must be in 2^(MaxPstreams + 1) format. | |
741 | * fls(0) = 0, fls(0x1) = 1, fls(0x10) = 2, fls(0x100) = 3, etc. | |
742 | */ | |
743 | max_primary_streams = fls(stream_info->num_stream_ctxs) - 2; | |
3a7fa5be XR |
744 | xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, |
745 | "Setting number of stream ctx array entries to %u", | |
8df75f42 | 746 | 1 << (max_primary_streams + 1)); |
28ccd296 ME |
747 | ep_ctx->ep_info &= cpu_to_le32(~EP_MAXPSTREAMS_MASK); |
748 | ep_ctx->ep_info |= cpu_to_le32(EP_MAXPSTREAMS(max_primary_streams) | |
749 | | EP_HAS_LSA); | |
750 | ep_ctx->deq = cpu_to_le64(stream_info->ctx_array_dma); | |
8df75f42 SS |
751 | } |
752 | ||
753 | /* | |
754 | * Sets the MaxPStreams field and the Linear Stream Array field to 0. | |
755 | * Reinstalls the "normal" endpoint ring (at its previous dequeue mark, | |
756 | * not at the beginning of the ring). | |
757 | */ | |
4daf9df5 | 758 | void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx *ep_ctx, |
8df75f42 SS |
759 | struct xhci_virt_ep *ep) |
760 | { | |
761 | dma_addr_t addr; | |
28ccd296 | 762 | ep_ctx->ep_info &= cpu_to_le32(~(EP_MAXPSTREAMS_MASK | EP_HAS_LSA)); |
8df75f42 | 763 | addr = xhci_trb_virt_to_dma(ep->ring->deq_seg, ep->ring->dequeue); |
28ccd296 | 764 | ep_ctx->deq = cpu_to_le64(addr | ep->ring->cycle_state); |
8df75f42 SS |
765 | } |
766 | ||
767 | /* Frees all stream contexts associated with the endpoint, | |
768 | * | |
769 | * Caller should fix the endpoint context streams fields. | |
770 | */ | |
771 | void xhci_free_stream_info(struct xhci_hcd *xhci, | |
772 | struct xhci_stream_info *stream_info) | |
773 | { | |
774 | int cur_stream; | |
775 | struct xhci_ring *cur_ring; | |
8df75f42 SS |
776 | |
777 | if (!stream_info) | |
778 | return; | |
779 | ||
780 | for (cur_stream = 1; cur_stream < stream_info->num_streams; | |
781 | cur_stream++) { | |
782 | cur_ring = stream_info->stream_rings[cur_stream]; | |
783 | if (cur_ring) { | |
8df75f42 SS |
784 | xhci_ring_free(xhci, cur_ring); |
785 | stream_info->stream_rings[cur_stream] = NULL; | |
786 | } | |
787 | } | |
788 | xhci_free_command(xhci, stream_info->free_streams_command); | |
789 | xhci->cmd_ring_reserved_trbs--; | |
790 | if (stream_info->stream_ctx_array) | |
791 | xhci_free_stream_ctx(xhci, | |
792 | stream_info->num_stream_ctxs, | |
793 | stream_info->stream_ctx_array, | |
794 | stream_info->ctx_array_dma); | |
795 | ||
0d3703be | 796 | kfree(stream_info->stream_rings); |
8df75f42 SS |
797 | kfree(stream_info); |
798 | } | |
799 | ||
800 | ||
801 | /***************** Device context manipulation *************************/ | |
802 | ||
6f5165cf SS |
803 | static void xhci_init_endpoint_timer(struct xhci_hcd *xhci, |
804 | struct xhci_virt_ep *ep) | |
805 | { | |
66a45503 KC |
806 | timer_setup(&ep->stop_cmd_timer, xhci_stop_endpoint_command_watchdog, |
807 | 0); | |
6f5165cf SS |
808 | ep->xhci = xhci; |
809 | } | |
810 | ||
839c817c SS |
811 | static void xhci_free_tt_info(struct xhci_hcd *xhci, |
812 | struct xhci_virt_device *virt_dev, | |
813 | int slot_id) | |
814 | { | |
839c817c | 815 | struct list_head *tt_list_head; |
46ed8f00 TI |
816 | struct xhci_tt_bw_info *tt_info, *next; |
817 | bool slot_found = false; | |
839c817c SS |
818 | |
819 | /* If the device never made it past the Set Address stage, | |
820 | * it may not have the real_port set correctly. | |
821 | */ | |
822 | if (virt_dev->real_port == 0 || | |
823 | virt_dev->real_port > HCS_MAX_PORTS(xhci->hcs_params1)) { | |
824 | xhci_dbg(xhci, "Bad real port.\n"); | |
825 | return; | |
826 | } | |
827 | ||
828 | tt_list_head = &(xhci->rh_bw[virt_dev->real_port - 1].tts); | |
46ed8f00 TI |
829 | list_for_each_entry_safe(tt_info, next, tt_list_head, tt_list) { |
830 | /* Multi-TT hubs will have more than one entry */ | |
831 | if (tt_info->slot_id == slot_id) { | |
832 | slot_found = true; | |
833 | list_del(&tt_info->tt_list); | |
834 | kfree(tt_info); | |
835 | } else if (slot_found) { | |
839c817c | 836 | break; |
46ed8f00 | 837 | } |
839c817c | 838 | } |
839c817c SS |
839 | } |
840 | ||
841 | int xhci_alloc_tt_info(struct xhci_hcd *xhci, | |
842 | struct xhci_virt_device *virt_dev, | |
843 | struct usb_device *hdev, | |
844 | struct usb_tt *tt, gfp_t mem_flags) | |
845 | { | |
846 | struct xhci_tt_bw_info *tt_info; | |
847 | unsigned int num_ports; | |
848 | int i, j; | |
a965315e | 849 | struct device *dev = xhci_to_hcd(xhci)->self.sysdev; |
839c817c SS |
850 | |
851 | if (!tt->multi) | |
852 | num_ports = 1; | |
853 | else | |
854 | num_ports = hdev->maxchild; | |
855 | ||
856 | for (i = 0; i < num_ports; i++, tt_info++) { | |
857 | struct xhci_interval_bw_table *bw_table; | |
858 | ||
a965315e AW |
859 | tt_info = kzalloc_node(sizeof(*tt_info), mem_flags, |
860 | dev_to_node(dev)); | |
839c817c SS |
861 | if (!tt_info) |
862 | goto free_tts; | |
863 | INIT_LIST_HEAD(&tt_info->tt_list); | |
864 | list_add(&tt_info->tt_list, | |
865 | &xhci->rh_bw[virt_dev->real_port - 1].tts); | |
866 | tt_info->slot_id = virt_dev->udev->slot_id; | |
867 | if (tt->multi) | |
868 | tt_info->ttport = i+1; | |
869 | bw_table = &tt_info->bw_table; | |
870 | for (j = 0; j < XHCI_MAX_INTERVAL; j++) | |
871 | INIT_LIST_HEAD(&bw_table->interval_bw[j].endpoints); | |
872 | } | |
873 | return 0; | |
874 | ||
875 | free_tts: | |
876 | xhci_free_tt_info(xhci, virt_dev, virt_dev->udev->slot_id); | |
877 | return -ENOMEM; | |
878 | } | |
879 | ||
880 | ||
881 | /* All the xhci_tds in the ring's TD list should be freed at this point. | |
882 | * Should be called with xhci->lock held if there is any chance the TT lists | |
883 | * will be manipulated by the configure endpoint, allocate device, or update | |
884 | * hub functions while this function is removing the TT entries from the list. | |
885 | */ | |
3ffbba95 SS |
886 | void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id) |
887 | { | |
888 | struct xhci_virt_device *dev; | |
889 | int i; | |
2e27980e | 890 | int old_active_eps = 0; |
3ffbba95 SS |
891 | |
892 | /* Slot ID 0 is reserved */ | |
893 | if (slot_id == 0 || !xhci->devs[slot_id]) | |
894 | return; | |
895 | ||
896 | dev = xhci->devs[slot_id]; | |
a711edee | 897 | |
8e595a5d | 898 | xhci->dcbaa->dev_context_ptrs[slot_id] = 0; |
3ffbba95 SS |
899 | if (!dev) |
900 | return; | |
901 | ||
d850c165 ZX |
902 | trace_xhci_free_virt_device(dev); |
903 | ||
2e27980e SS |
904 | if (dev->tt_info) |
905 | old_active_eps = dev->tt_info->active_eps; | |
906 | ||
98871e94 | 907 | for (i = 0; i < 31; i++) { |
63a0d9ab SS |
908 | if (dev->eps[i].ring) |
909 | xhci_ring_free(xhci, dev->eps[i].ring); | |
8df75f42 SS |
910 | if (dev->eps[i].stream_info) |
911 | xhci_free_stream_info(xhci, | |
912 | dev->eps[i].stream_info); | |
2e27980e SS |
913 | /* Endpoints on the TT/root port lists should have been removed |
914 | * when usb_disable_device() was called for the device. | |
915 | * We can't drop them anyway, because the udev might have gone | |
916 | * away by this point, and we can't tell what speed it was. | |
917 | */ | |
918 | if (!list_empty(&dev->eps[i].bw_endpoint_list)) | |
919 | xhci_warn(xhci, "Slot %u endpoint %u " | |
920 | "not removed from BW list!\n", | |
921 | slot_id, i); | |
8df75f42 | 922 | } |
839c817c SS |
923 | /* If this is a hub, free the TT(s) from the TT list */ |
924 | xhci_free_tt_info(xhci, dev, slot_id); | |
2e27980e SS |
925 | /* If necessary, update the number of active TTs on this root port */ |
926 | xhci_update_tt_active_eps(xhci, dev, old_active_eps); | |
3ffbba95 SS |
927 | |
928 | if (dev->in_ctx) | |
d115b048 | 929 | xhci_free_container_ctx(xhci, dev->in_ctx); |
3ffbba95 | 930 | if (dev->out_ctx) |
d115b048 JY |
931 | xhci_free_container_ctx(xhci, dev->out_ctx); |
932 | ||
a400efe4 MN |
933 | if (dev->udev && dev->udev->slot_id) |
934 | dev->udev->slot_id = 0; | |
3ffbba95 | 935 | kfree(xhci->devs[slot_id]); |
326b4810 | 936 | xhci->devs[slot_id] = NULL; |
3ffbba95 SS |
937 | } |
938 | ||
ee8665e2 MN |
939 | /* |
940 | * Free a virt_device structure. | |
941 | * If the virt_device added a tt_info (a hub) and has children pointing to | |
942 | * that tt_info, then free the child first. Recursive. | |
943 | * We can't rely on udev at this point to find child-parent relationships. | |
944 | */ | |
4ee925df | 945 | static void xhci_free_virt_devices_depth_first(struct xhci_hcd *xhci, int slot_id) |
ee8665e2 MN |
946 | { |
947 | struct xhci_virt_device *vdev; | |
948 | struct list_head *tt_list_head; | |
949 | struct xhci_tt_bw_info *tt_info, *next; | |
950 | int i; | |
951 | ||
952 | vdev = xhci->devs[slot_id]; | |
953 | if (!vdev) | |
954 | return; | |
955 | ||
80e45769 YC |
956 | if (vdev->real_port == 0 || |
957 | vdev->real_port > HCS_MAX_PORTS(xhci->hcs_params1)) { | |
958 | xhci_dbg(xhci, "Bad vdev->real_port.\n"); | |
959 | goto out; | |
960 | } | |
961 | ||
ee8665e2 MN |
962 | tt_list_head = &(xhci->rh_bw[vdev->real_port - 1].tts); |
963 | list_for_each_entry_safe(tt_info, next, tt_list_head, tt_list) { | |
964 | /* is this a hub device that added a tt_info to the tts list */ | |
965 | if (tt_info->slot_id == slot_id) { | |
966 | /* are any devices using this tt_info? */ | |
967 | for (i = 1; i < HCS_MAX_SLOTS(xhci->hcs_params1); i++) { | |
968 | vdev = xhci->devs[i]; | |
969 | if (vdev && (vdev->tt_info == tt_info)) | |
970 | xhci_free_virt_devices_depth_first( | |
971 | xhci, i); | |
972 | } | |
973 | } | |
974 | } | |
80e45769 | 975 | out: |
ee8665e2 | 976 | /* we are now at a leaf device */ |
02b6fdc2 | 977 | xhci_debugfs_remove_slot(xhci, slot_id); |
ee8665e2 MN |
978 | xhci_free_virt_device(xhci, slot_id); |
979 | } | |
980 | ||
3ffbba95 SS |
981 | int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, |
982 | struct usb_device *udev, gfp_t flags) | |
983 | { | |
3ffbba95 | 984 | struct xhci_virt_device *dev; |
63a0d9ab | 985 | int i; |
3ffbba95 SS |
986 | |
987 | /* Slot ID 0 is reserved */ | |
988 | if (slot_id == 0 || xhci->devs[slot_id]) { | |
989 | xhci_warn(xhci, "Bad Slot ID %d\n", slot_id); | |
990 | return 0; | |
991 | } | |
992 | ||
5d9b70f7 MN |
993 | dev = kzalloc(sizeof(*dev), flags); |
994 | if (!dev) | |
3ffbba95 | 995 | return 0; |
3ffbba95 | 996 | |
d115b048 JY |
997 | /* Allocate the (output) device context that will be used in the HC. */ |
998 | dev->out_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_DEVICE, flags); | |
3ffbba95 SS |
999 | if (!dev->out_ctx) |
1000 | goto fail; | |
d115b048 | 1001 | |
700e2052 | 1002 | xhci_dbg(xhci, "Slot %d output ctx = 0x%llx (dma)\n", slot_id, |
d115b048 | 1003 | (unsigned long long)dev->out_ctx->dma); |
3ffbba95 SS |
1004 | |
1005 | /* Allocate the (input) device context for address device command */ | |
d115b048 | 1006 | dev->in_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT, flags); |
3ffbba95 SS |
1007 | if (!dev->in_ctx) |
1008 | goto fail; | |
d115b048 | 1009 | |
700e2052 | 1010 | xhci_dbg(xhci, "Slot %d input ctx = 0x%llx (dma)\n", slot_id, |
d115b048 | 1011 | (unsigned long long)dev->in_ctx->dma); |
3ffbba95 | 1012 | |
6f5165cf SS |
1013 | /* Initialize the cancellation list and watchdog timers for each ep */ |
1014 | for (i = 0; i < 31; i++) { | |
1015 | xhci_init_endpoint_timer(xhci, &dev->eps[i]); | |
63a0d9ab | 1016 | INIT_LIST_HEAD(&dev->eps[i].cancelled_td_list); |
2e27980e | 1017 | INIT_LIST_HEAD(&dev->eps[i].bw_endpoint_list); |
6f5165cf | 1018 | } |
63a0d9ab | 1019 | |
3ffbba95 | 1020 | /* Allocate endpoint 0 ring */ |
f9c589e1 | 1021 | dev->eps[0].ring = xhci_ring_alloc(xhci, 2, 1, TYPE_CTRL, 0, flags); |
63a0d9ab | 1022 | if (!dev->eps[0].ring) |
3ffbba95 SS |
1023 | goto fail; |
1024 | ||
64927730 | 1025 | dev->udev = udev; |
f94e0186 | 1026 | |
28c2d2ef | 1027 | /* Point to output device context in dcbaa. */ |
28ccd296 | 1028 | xhci->dcbaa->dev_context_ptrs[slot_id] = cpu_to_le64(dev->out_ctx->dma); |
700e2052 | 1029 | xhci_dbg(xhci, "Set slot id %d dcbaa entry %p to 0x%llx\n", |
28ccd296 ME |
1030 | slot_id, |
1031 | &xhci->dcbaa->dev_context_ptrs[slot_id], | |
f5960b69 | 1032 | le64_to_cpu(xhci->dcbaa->dev_context_ptrs[slot_id])); |
3ffbba95 | 1033 | |
a711edee FB |
1034 | trace_xhci_alloc_virt_device(dev); |
1035 | ||
5d9b70f7 MN |
1036 | xhci->devs[slot_id] = dev; |
1037 | ||
3ffbba95 SS |
1038 | return 1; |
1039 | fail: | |
5d9b70f7 MN |
1040 | |
1041 | if (dev->in_ctx) | |
1042 | xhci_free_container_ctx(xhci, dev->in_ctx); | |
1043 | if (dev->out_ctx) | |
1044 | xhci_free_container_ctx(xhci, dev->out_ctx); | |
1045 | kfree(dev); | |
1046 | ||
3ffbba95 SS |
1047 | return 0; |
1048 | } | |
1049 | ||
2d1ee590 SS |
1050 | void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci, |
1051 | struct usb_device *udev) | |
1052 | { | |
1053 | struct xhci_virt_device *virt_dev; | |
1054 | struct xhci_ep_ctx *ep0_ctx; | |
1055 | struct xhci_ring *ep_ring; | |
1056 | ||
1057 | virt_dev = xhci->devs[udev->slot_id]; | |
1058 | ep0_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, 0); | |
1059 | ep_ring = virt_dev->eps[0].ring; | |
1060 | /* | |
1061 | * FIXME we don't keep track of the dequeue pointer very well after a | |
1062 | * Set TR dequeue pointer, so we're setting the dequeue pointer of the | |
1063 | * host to our enqueue pointer. This should only be called after a | |
1064 | * configured device has reset, so all control transfers should have | |
1065 | * been completed or cancelled before the reset. | |
1066 | */ | |
28ccd296 ME |
1067 | ep0_ctx->deq = cpu_to_le64(xhci_trb_virt_to_dma(ep_ring->enq_seg, |
1068 | ep_ring->enqueue) | |
1069 | | ep_ring->cycle_state); | |
2d1ee590 SS |
1070 | } |
1071 | ||
f6ff0ac8 SS |
1072 | /* |
1073 | * The xHCI roothub may have ports of differing speeds in any order in the port | |
07f76190 | 1074 | * status registers. |
f6ff0ac8 SS |
1075 | * |
1076 | * The xHCI hardware wants to know the roothub port number that the USB device | |
1077 | * is attached to (or the roothub port its ancestor hub is attached to). All we | |
1078 | * know is the index of that port under either the USB 2.0 or the USB 3.0 | |
1079 | * roothub, but that doesn't give us the real index into the HW port status | |
3f5eb141 | 1080 | * registers. Call xhci_find_raw_port_number() to get real index. |
f6ff0ac8 SS |
1081 | */ |
1082 | static u32 xhci_find_real_port_number(struct xhci_hcd *xhci, | |
1083 | struct usb_device *udev) | |
1084 | { | |
1085 | struct usb_device *top_dev; | |
3f5eb141 LT |
1086 | struct usb_hcd *hcd; |
1087 | ||
0caf6b33 | 1088 | if (udev->speed >= USB_SPEED_SUPER) |
3f5eb141 LT |
1089 | hcd = xhci->shared_hcd; |
1090 | else | |
1091 | hcd = xhci->main_hcd; | |
f6ff0ac8 SS |
1092 | |
1093 | for (top_dev = udev; top_dev->parent && top_dev->parent->parent; | |
1094 | top_dev = top_dev->parent) | |
1095 | /* Found device below root hub */; | |
f6ff0ac8 | 1096 | |
3f5eb141 | 1097 | return xhci_find_raw_port_number(hcd, top_dev->portnum); |
f6ff0ac8 SS |
1098 | } |
1099 | ||
3ffbba95 SS |
1100 | /* Setup an xHCI virtual device for a Set Address command */ |
1101 | int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev) | |
1102 | { | |
1103 | struct xhci_virt_device *dev; | |
1104 | struct xhci_ep_ctx *ep0_ctx; | |
d115b048 | 1105 | struct xhci_slot_ctx *slot_ctx; |
f6ff0ac8 | 1106 | u32 port_num; |
bd18fd5c | 1107 | u32 max_packets; |
f6ff0ac8 | 1108 | struct usb_device *top_dev; |
3ffbba95 SS |
1109 | |
1110 | dev = xhci->devs[udev->slot_id]; | |
1111 | /* Slot ID 0 is reserved */ | |
1112 | if (udev->slot_id == 0 || !dev) { | |
1113 | xhci_warn(xhci, "Slot ID %d is not assigned to this device\n", | |
1114 | udev->slot_id); | |
1115 | return -EINVAL; | |
1116 | } | |
d115b048 | 1117 | ep0_ctx = xhci_get_ep_ctx(xhci, dev->in_ctx, 0); |
d115b048 | 1118 | slot_ctx = xhci_get_slot_ctx(xhci, dev->in_ctx); |
3ffbba95 | 1119 | |
3ffbba95 | 1120 | /* 3) Only the control endpoint is valid - one endpoint context */ |
f5960b69 | 1121 | slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1) | udev->route); |
3ffbba95 | 1122 | switch (udev->speed) { |
0caf6b33 | 1123 | case USB_SPEED_SUPER_PLUS: |
d7854041 MN |
1124 | slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_SSP); |
1125 | max_packets = MAX_PACKET(512); | |
1126 | break; | |
3ffbba95 | 1127 | case USB_SPEED_SUPER: |
f5960b69 | 1128 | slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_SS); |
bd18fd5c | 1129 | max_packets = MAX_PACKET(512); |
3ffbba95 SS |
1130 | break; |
1131 | case USB_SPEED_HIGH: | |
f5960b69 | 1132 | slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_HS); |
bd18fd5c | 1133 | max_packets = MAX_PACKET(64); |
3ffbba95 | 1134 | break; |
bd18fd5c | 1135 | /* USB core guesses at a 64-byte max packet first for FS devices */ |
3ffbba95 | 1136 | case USB_SPEED_FULL: |
f5960b69 | 1137 | slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_FS); |
bd18fd5c | 1138 | max_packets = MAX_PACKET(64); |
3ffbba95 SS |
1139 | break; |
1140 | case USB_SPEED_LOW: | |
f5960b69 | 1141 | slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_LS); |
bd18fd5c | 1142 | max_packets = MAX_PACKET(8); |
3ffbba95 | 1143 | break; |
551cdbbe | 1144 | case USB_SPEED_WIRELESS: |
3ffbba95 SS |
1145 | xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n"); |
1146 | return -EINVAL; | |
3ffbba95 SS |
1147 | default: |
1148 | /* Speed was set earlier, this shouldn't happen. */ | |
bd18fd5c | 1149 | return -EINVAL; |
3ffbba95 SS |
1150 | } |
1151 | /* Find the root hub port this device is under */ | |
f6ff0ac8 SS |
1152 | port_num = xhci_find_real_port_number(xhci, udev); |
1153 | if (!port_num) | |
1154 | return -EINVAL; | |
f5960b69 | 1155 | slot_ctx->dev_info2 |= cpu_to_le32(ROOT_HUB_PORT(port_num)); |
f6ff0ac8 | 1156 | /* Set the port number in the virtual_device to the faked port number */ |
3ffbba95 SS |
1157 | for (top_dev = udev; top_dev->parent && top_dev->parent->parent; |
1158 | top_dev = top_dev->parent) | |
1159 | /* Found device below root hub */; | |
fe30182c | 1160 | dev->fake_port = top_dev->portnum; |
66381755 | 1161 | dev->real_port = port_num; |
f6ff0ac8 | 1162 | xhci_dbg(xhci, "Set root hub portnum to %d\n", port_num); |
fe30182c | 1163 | xhci_dbg(xhci, "Set fake root hub portnum to %d\n", dev->fake_port); |
3ffbba95 | 1164 | |
839c817c SS |
1165 | /* Find the right bandwidth table that this device will be a part of. |
1166 | * If this is a full speed device attached directly to a root port (or a | |
1167 | * decendent of one), it counts as a primary bandwidth domain, not a | |
1168 | * secondary bandwidth domain under a TT. An xhci_tt_info structure | |
1169 | * will never be created for the HS root hub. | |
1170 | */ | |
1171 | if (!udev->tt || !udev->tt->hub->parent) { | |
1172 | dev->bw_table = &xhci->rh_bw[port_num - 1].bw_table; | |
1173 | } else { | |
1174 | struct xhci_root_port_bw_info *rh_bw; | |
1175 | struct xhci_tt_bw_info *tt_bw; | |
1176 | ||
1177 | rh_bw = &xhci->rh_bw[port_num - 1]; | |
1178 | /* Find the right TT. */ | |
1179 | list_for_each_entry(tt_bw, &rh_bw->tts, tt_list) { | |
1180 | if (tt_bw->slot_id != udev->tt->hub->slot_id) | |
1181 | continue; | |
1182 | ||
1183 | if (!dev->udev->tt->multi || | |
1184 | (udev->tt->multi && | |
1185 | tt_bw->ttport == dev->udev->ttport)) { | |
1186 | dev->bw_table = &tt_bw->bw_table; | |
1187 | dev->tt_info = tt_bw; | |
1188 | break; | |
1189 | } | |
1190 | } | |
1191 | if (!dev->tt_info) | |
1192 | xhci_warn(xhci, "WARN: Didn't find a matching TT\n"); | |
1193 | } | |
1194 | ||
aa1b13ef SS |
1195 | /* Is this a LS/FS device under an external HS hub? */ |
1196 | if (udev->tt && udev->tt->hub->parent) { | |
28ccd296 ME |
1197 | slot_ctx->tt_info = cpu_to_le32(udev->tt->hub->slot_id | |
1198 | (udev->ttport << 8)); | |
07b6de10 | 1199 | if (udev->tt->multi) |
28ccd296 | 1200 | slot_ctx->dev_info |= cpu_to_le32(DEV_MTT); |
3ffbba95 | 1201 | } |
700e2052 | 1202 | xhci_dbg(xhci, "udev->tt = %p\n", udev->tt); |
3ffbba95 SS |
1203 | xhci_dbg(xhci, "udev->ttport = 0x%x\n", udev->ttport); |
1204 | ||
1205 | /* Step 4 - ring already allocated */ | |
1206 | /* Step 5 */ | |
28ccd296 | 1207 | ep0_ctx->ep_info2 = cpu_to_le32(EP_TYPE(CTRL_EP)); |
bd18fd5c | 1208 | |
3ffbba95 | 1209 | /* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */ |
bd18fd5c MN |
1210 | ep0_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(0) | ERROR_COUNT(3) | |
1211 | max_packets); | |
3ffbba95 | 1212 | |
28ccd296 ME |
1213 | ep0_ctx->deq = cpu_to_le64(dev->eps[0].ring->first_seg->dma | |
1214 | dev->eps[0].ring->cycle_state); | |
3ffbba95 | 1215 | |
a711edee FB |
1216 | trace_xhci_setup_addressable_virt_device(dev); |
1217 | ||
3ffbba95 SS |
1218 | /* Steps 7 and 8 were done in xhci_alloc_virt_device() */ |
1219 | ||
1220 | return 0; | |
1221 | } | |
1222 | ||
dfa49c4a DT |
1223 | /* |
1224 | * Convert interval expressed as 2^(bInterval - 1) == interval into | |
1225 | * straight exponent value 2^n == interval. | |
1226 | * | |
1227 | */ | |
1228 | static unsigned int xhci_parse_exponent_interval(struct usb_device *udev, | |
1229 | struct usb_host_endpoint *ep) | |
1230 | { | |
1231 | unsigned int interval; | |
1232 | ||
1233 | interval = clamp_val(ep->desc.bInterval, 1, 16) - 1; | |
1234 | if (interval != ep->desc.bInterval - 1) | |
1235 | dev_warn(&udev->dev, | |
cd3c18ba | 1236 | "ep %#x - rounding interval to %d %sframes\n", |
dfa49c4a | 1237 | ep->desc.bEndpointAddress, |
cd3c18ba DT |
1238 | 1 << interval, |
1239 | udev->speed == USB_SPEED_FULL ? "" : "micro"); | |
1240 | ||
1241 | if (udev->speed == USB_SPEED_FULL) { | |
1242 | /* | |
1243 | * Full speed isoc endpoints specify interval in frames, | |
1244 | * not microframes. We are using microframes everywhere, | |
1245 | * so adjust accordingly. | |
1246 | */ | |
1247 | interval += 3; /* 1 frame = 2^3 uframes */ | |
1248 | } | |
dfa49c4a DT |
1249 | |
1250 | return interval; | |
1251 | } | |
1252 | ||
1253 | /* | |
340a3504 | 1254 | * Convert bInterval expressed in microframes (in 1-255 range) to exponent of |
dfa49c4a DT |
1255 | * microframes, rounded down to nearest power of 2. |
1256 | */ | |
340a3504 SS |
1257 | static unsigned int xhci_microframes_to_exponent(struct usb_device *udev, |
1258 | struct usb_host_endpoint *ep, unsigned int desc_interval, | |
1259 | unsigned int min_exponent, unsigned int max_exponent) | |
dfa49c4a DT |
1260 | { |
1261 | unsigned int interval; | |
1262 | ||
340a3504 SS |
1263 | interval = fls(desc_interval) - 1; |
1264 | interval = clamp_val(interval, min_exponent, max_exponent); | |
1265 | if ((1 << interval) != desc_interval) | |
a5da9568 | 1266 | dev_dbg(&udev->dev, |
dfa49c4a DT |
1267 | "ep %#x - rounding interval to %d microframes, ep desc says %d microframes\n", |
1268 | ep->desc.bEndpointAddress, | |
1269 | 1 << interval, | |
340a3504 | 1270 | desc_interval); |
dfa49c4a DT |
1271 | |
1272 | return interval; | |
1273 | } | |
1274 | ||
340a3504 SS |
1275 | static unsigned int xhci_parse_microframe_interval(struct usb_device *udev, |
1276 | struct usb_host_endpoint *ep) | |
1277 | { | |
55c1945e SS |
1278 | if (ep->desc.bInterval == 0) |
1279 | return 0; | |
340a3504 SS |
1280 | return xhci_microframes_to_exponent(udev, ep, |
1281 | ep->desc.bInterval, 0, 15); | |
1282 | } | |
1283 | ||
1284 | ||
1285 | static unsigned int xhci_parse_frame_interval(struct usb_device *udev, | |
1286 | struct usb_host_endpoint *ep) | |
1287 | { | |
1288 | return xhci_microframes_to_exponent(udev, ep, | |
1289 | ep->desc.bInterval * 8, 3, 10); | |
1290 | } | |
1291 | ||
f94e0186 SS |
1292 | /* Return the polling or NAK interval. |
1293 | * | |
1294 | * The polling interval is expressed in "microframes". If xHCI's Interval field | |
1295 | * is set to N, it will service the endpoint every 2^(Interval)*125us. | |
1296 | * | |
1297 | * The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval | |
1298 | * is set to 0. | |
1299 | */ | |
575688e1 | 1300 | static unsigned int xhci_get_endpoint_interval(struct usb_device *udev, |
f94e0186 SS |
1301 | struct usb_host_endpoint *ep) |
1302 | { | |
1303 | unsigned int interval = 0; | |
1304 | ||
1305 | switch (udev->speed) { | |
1306 | case USB_SPEED_HIGH: | |
1307 | /* Max NAK rate */ | |
1308 | if (usb_endpoint_xfer_control(&ep->desc) || | |
dfa49c4a | 1309 | usb_endpoint_xfer_bulk(&ep->desc)) { |
340a3504 | 1310 | interval = xhci_parse_microframe_interval(udev, ep); |
dfa49c4a DT |
1311 | break; |
1312 | } | |
df561f66 | 1313 | fallthrough; /* SS and HS isoc/int have same decoding */ |
dfa49c4a | 1314 | |
0caf6b33 | 1315 | case USB_SPEED_SUPER_PLUS: |
f94e0186 SS |
1316 | case USB_SPEED_SUPER: |
1317 | if (usb_endpoint_xfer_int(&ep->desc) || | |
dfa49c4a DT |
1318 | usb_endpoint_xfer_isoc(&ep->desc)) { |
1319 | interval = xhci_parse_exponent_interval(udev, ep); | |
f94e0186 SS |
1320 | } |
1321 | break; | |
dfa49c4a | 1322 | |
f94e0186 | 1323 | case USB_SPEED_FULL: |
b513d447 | 1324 | if (usb_endpoint_xfer_isoc(&ep->desc)) { |
dfa49c4a DT |
1325 | interval = xhci_parse_exponent_interval(udev, ep); |
1326 | break; | |
1327 | } | |
1328 | /* | |
b513d447 | 1329 | * Fall through for interrupt endpoint interval decoding |
dfa49c4a DT |
1330 | * since it uses the same rules as low speed interrupt |
1331 | * endpoints. | |
1332 | */ | |
df561f66 | 1333 | fallthrough; |
dfa49c4a | 1334 | |
f94e0186 SS |
1335 | case USB_SPEED_LOW: |
1336 | if (usb_endpoint_xfer_int(&ep->desc) || | |
dfa49c4a DT |
1337 | usb_endpoint_xfer_isoc(&ep->desc)) { |
1338 | ||
1339 | interval = xhci_parse_frame_interval(udev, ep); | |
f94e0186 SS |
1340 | } |
1341 | break; | |
dfa49c4a | 1342 | |
f94e0186 SS |
1343 | default: |
1344 | BUG(); | |
1345 | } | |
def4e6f7 | 1346 | return interval; |
f94e0186 SS |
1347 | } |
1348 | ||
c30c791c | 1349 | /* The "Mult" field in the endpoint context is only set for SuperSpeed isoc eps. |
1cf62246 SS |
1350 | * High speed endpoint descriptors can define "the number of additional |
1351 | * transaction opportunities per microframe", but that goes in the Max Burst | |
1352 | * endpoint context field. | |
1353 | */ | |
575688e1 | 1354 | static u32 xhci_get_endpoint_mult(struct usb_device *udev, |
1cf62246 SS |
1355 | struct usb_host_endpoint *ep) |
1356 | { | |
0caf6b33 | 1357 | if (udev->speed < USB_SPEED_SUPER || |
c30c791c | 1358 | !usb_endpoint_xfer_isoc(&ep->desc)) |
1cf62246 | 1359 | return 0; |
842f1690 | 1360 | return ep->ss_ep_comp.bmAttributes; |
1cf62246 SS |
1361 | } |
1362 | ||
def4e6f7 MN |
1363 | static u32 xhci_get_endpoint_max_burst(struct usb_device *udev, |
1364 | struct usb_host_endpoint *ep) | |
1365 | { | |
1366 | /* Super speed and Plus have max burst in ep companion desc */ | |
1367 | if (udev->speed >= USB_SPEED_SUPER) | |
1368 | return ep->ss_ep_comp.bMaxBurst; | |
1369 | ||
1370 | if (udev->speed == USB_SPEED_HIGH && | |
1371 | (usb_endpoint_xfer_isoc(&ep->desc) || | |
1372 | usb_endpoint_xfer_int(&ep->desc))) | |
dcf5228c | 1373 | return usb_endpoint_maxp_mult(&ep->desc) - 1; |
def4e6f7 MN |
1374 | |
1375 | return 0; | |
1376 | } | |
1377 | ||
4daf9df5 | 1378 | static u32 xhci_get_endpoint_type(struct usb_host_endpoint *ep) |
f94e0186 SS |
1379 | { |
1380 | int in; | |
f94e0186 SS |
1381 | |
1382 | in = usb_endpoint_dir_in(&ep->desc); | |
def4e6f7 | 1383 | |
c0e625c4 FB |
1384 | switch (usb_endpoint_type(&ep->desc)) { |
1385 | case USB_ENDPOINT_XFER_CONTROL: | |
def4e6f7 | 1386 | return CTRL_EP; |
c0e625c4 | 1387 | case USB_ENDPOINT_XFER_BULK: |
def4e6f7 | 1388 | return in ? BULK_IN_EP : BULK_OUT_EP; |
c0e625c4 | 1389 | case USB_ENDPOINT_XFER_ISOC: |
def4e6f7 | 1390 | return in ? ISOC_IN_EP : ISOC_OUT_EP; |
c0e625c4 | 1391 | case USB_ENDPOINT_XFER_INT: |
def4e6f7 | 1392 | return in ? INT_IN_EP : INT_OUT_EP; |
c0e625c4 | 1393 | } |
def4e6f7 | 1394 | return 0; |
f94e0186 SS |
1395 | } |
1396 | ||
9238f25d SS |
1397 | /* Return the maximum endpoint service interval time (ESIT) payload. |
1398 | * Basically, this is the maxpacket size, multiplied by the burst size | |
1399 | * and mult size. | |
1400 | */ | |
4daf9df5 | 1401 | static u32 xhci_get_max_esit_payload(struct usb_device *udev, |
9238f25d SS |
1402 | struct usb_host_endpoint *ep) |
1403 | { | |
1404 | int max_burst; | |
1405 | int max_packet; | |
1406 | ||
1407 | /* Only applies for interrupt or isochronous endpoints */ | |
1408 | if (usb_endpoint_xfer_control(&ep->desc) || | |
1409 | usb_endpoint_xfer_bulk(&ep->desc)) | |
1410 | return 0; | |
1411 | ||
8ef8a9f5 MN |
1412 | /* SuperSpeedPlus Isoc ep sending over 48k per esit */ |
1413 | if ((udev->speed >= USB_SPEED_SUPER_PLUS) && | |
1414 | USB_SS_SSP_ISOC_COMP(ep->ss_ep_comp.bmAttributes)) | |
1415 | return le32_to_cpu(ep->ssp_isoc_ep_comp.dwBytesPerInterval); | |
1416 | /* SuperSpeed or SuperSpeedPlus Isoc ep with less than 48k per esit */ | |
1417 | else if (udev->speed >= USB_SPEED_SUPER) | |
64b3c304 | 1418 | return le16_to_cpu(ep->ss_ep_comp.wBytesPerInterval); |
9238f25d | 1419 | |
734d3ddd | 1420 | max_packet = usb_endpoint_maxp(&ep->desc); |
dcf5228c | 1421 | max_burst = usb_endpoint_maxp_mult(&ep->desc); |
9238f25d | 1422 | /* A 0 in max burst means 1 transfer per ESIT */ |
dcf5228c | 1423 | return max_packet * max_burst; |
9238f25d SS |
1424 | } |
1425 | ||
8df75f42 SS |
1426 | /* Set up an endpoint with one ring segment. Do not allocate stream rings. |
1427 | * Drivers will have to call usb_alloc_streams() to do that. | |
1428 | */ | |
f94e0186 SS |
1429 | int xhci_endpoint_init(struct xhci_hcd *xhci, |
1430 | struct xhci_virt_device *virt_dev, | |
1431 | struct usb_device *udev, | |
f88ba78d SS |
1432 | struct usb_host_endpoint *ep, |
1433 | gfp_t mem_flags) | |
f94e0186 SS |
1434 | { |
1435 | unsigned int ep_index; | |
1436 | struct xhci_ep_ctx *ep_ctx; | |
1437 | struct xhci_ring *ep_ring; | |
1438 | unsigned int max_packet; | |
def4e6f7 | 1439 | enum xhci_ring_type ring_type; |
9238f25d | 1440 | u32 max_esit_payload; |
17d65554 | 1441 | u32 endpoint_type; |
def4e6f7 MN |
1442 | unsigned int max_burst; |
1443 | unsigned int interval; | |
1444 | unsigned int mult; | |
1445 | unsigned int avg_trb_len; | |
1446 | unsigned int err_count = 0; | |
f94e0186 SS |
1447 | |
1448 | ep_index = xhci_get_endpoint_index(&ep->desc); | |
d115b048 | 1449 | ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index); |
f94e0186 | 1450 | |
4daf9df5 | 1451 | endpoint_type = xhci_get_endpoint_type(ep); |
17d65554 MN |
1452 | if (!endpoint_type) |
1453 | return -EINVAL; | |
17d65554 | 1454 | |
def4e6f7 | 1455 | ring_type = usb_endpoint_type(&ep->desc); |
f94e0186 | 1456 | |
def4e6f7 MN |
1457 | /* |
1458 | * Get values to fill the endpoint context, mostly from ep descriptor. | |
1459 | * The average TRB buffer lengt for bulk endpoints is unclear as we | |
1460 | * have no clue on scatter gather list entry size. For Isoc and Int, | |
1461 | * set it to max available. See xHCI 1.1 spec 4.14.1.1 for details. | |
1462 | */ | |
1463 | max_esit_payload = xhci_get_max_esit_payload(udev, ep); | |
1464 | interval = xhci_get_endpoint_interval(udev, ep); | |
69307ccb RQ |
1465 | |
1466 | /* Periodic endpoint bInterval limit quirk */ | |
1467 | if (usb_endpoint_xfer_int(&ep->desc) || | |
1468 | usb_endpoint_xfer_isoc(&ep->desc)) { | |
1469 | if ((xhci->quirks & XHCI_LIMIT_ENDPOINT_INTERVAL_7) && | |
1470 | udev->speed >= USB_SPEED_HIGH && | |
1471 | interval >= 7) { | |
1472 | interval = 6; | |
1473 | } | |
1474 | } | |
1475 | ||
def4e6f7 | 1476 | mult = xhci_get_endpoint_mult(udev, ep); |
734d3ddd | 1477 | max_packet = usb_endpoint_maxp(&ep->desc); |
def4e6f7 MN |
1478 | max_burst = xhci_get_endpoint_max_burst(udev, ep); |
1479 | avg_trb_len = max_esit_payload; | |
f94e0186 SS |
1480 | |
1481 | /* FIXME dig Mult and streams info out of ep companion desc */ | |
1482 | ||
def4e6f7 | 1483 | /* Allow 3 retries for everything but isoc, set CErr = 3 */ |
f94e0186 | 1484 | if (!usb_endpoint_xfer_isoc(&ep->desc)) |
def4e6f7 | 1485 | err_count = 3; |
f148b9f4 MN |
1486 | /* HS bulk max packet should be 512, FS bulk supports 8, 16, 32 or 64 */ |
1487 | if (usb_endpoint_xfer_bulk(&ep->desc)) { | |
1488 | if (udev->speed == USB_SPEED_HIGH) | |
1489 | max_packet = 512; | |
1490 | if (udev->speed == USB_SPEED_FULL) { | |
1491 | max_packet = rounddown_pow_of_two(max_packet); | |
1492 | max_packet = clamp_val(max_packet, 8, 64); | |
1493 | } | |
1494 | } | |
def4e6f7 | 1495 | /* xHCI 1.0 and 1.1 indicates that ctrl ep avg TRB Length should be 8 */ |
dca77945 | 1496 | if (usb_endpoint_xfer_control(&ep->desc) && xhci->hci_version >= 0x100) |
def4e6f7 | 1497 | avg_trb_len = 8; |
8ef8a9f5 MN |
1498 | /* xhci 1.1 with LEC support doesn't use mult field, use RsvdZ */ |
1499 | if ((xhci->hci_version > 0x100) && HCC2_LEC(xhci->hcc_params2)) | |
1500 | mult = 0; | |
def4e6f7 | 1501 | |
f9c589e1 MN |
1502 | /* Set up the endpoint ring */ |
1503 | virt_dev->eps[ep_index].new_ring = | |
1504 | xhci_ring_alloc(xhci, 2, 1, ring_type, max_packet, mem_flags); | |
c5628a2a MN |
1505 | if (!virt_dev->eps[ep_index].new_ring) |
1506 | return -ENOMEM; | |
1507 | ||
f9c589e1 MN |
1508 | virt_dev->eps[ep_index].skip = false; |
1509 | ep_ring = virt_dev->eps[ep_index].new_ring; | |
1510 | ||
def4e6f7 | 1511 | /* Fill the endpoint context */ |
8ef8a9f5 MN |
1512 | ep_ctx->ep_info = cpu_to_le32(EP_MAX_ESIT_PAYLOAD_HI(max_esit_payload) | |
1513 | EP_INTERVAL(interval) | | |
def4e6f7 MN |
1514 | EP_MULT(mult)); |
1515 | ep_ctx->ep_info2 = cpu_to_le32(EP_TYPE(endpoint_type) | | |
1516 | MAX_PACKET(max_packet) | | |
1517 | MAX_BURST(max_burst) | | |
1518 | ERROR_COUNT(err_count)); | |
1519 | ep_ctx->deq = cpu_to_le64(ep_ring->first_seg->dma | | |
1520 | ep_ring->cycle_state); | |
1521 | ||
1522 | ep_ctx->tx_info = cpu_to_le32(EP_MAX_ESIT_PAYLOAD_LO(max_esit_payload) | | |
1523 | EP_AVG_TRB_LENGTH(avg_trb_len)); | |
9238f25d | 1524 | |
f94e0186 SS |
1525 | return 0; |
1526 | } | |
1527 | ||
1528 | void xhci_endpoint_zero(struct xhci_hcd *xhci, | |
1529 | struct xhci_virt_device *virt_dev, | |
1530 | struct usb_host_endpoint *ep) | |
1531 | { | |
1532 | unsigned int ep_index; | |
1533 | struct xhci_ep_ctx *ep_ctx; | |
1534 | ||
1535 | ep_index = xhci_get_endpoint_index(&ep->desc); | |
d115b048 | 1536 | ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index); |
f94e0186 SS |
1537 | |
1538 | ep_ctx->ep_info = 0; | |
1539 | ep_ctx->ep_info2 = 0; | |
8e595a5d | 1540 | ep_ctx->deq = 0; |
f94e0186 SS |
1541 | ep_ctx->tx_info = 0; |
1542 | /* Don't free the endpoint ring until the set interface or configuration | |
1543 | * request succeeds. | |
1544 | */ | |
1545 | } | |
1546 | ||
9af5d71d SS |
1547 | void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info) |
1548 | { | |
1549 | bw_info->ep_interval = 0; | |
1550 | bw_info->mult = 0; | |
1551 | bw_info->num_packets = 0; | |
1552 | bw_info->max_packet_size = 0; | |
1553 | bw_info->type = 0; | |
1554 | bw_info->max_esit_payload = 0; | |
1555 | } | |
1556 | ||
1557 | void xhci_update_bw_info(struct xhci_hcd *xhci, | |
1558 | struct xhci_container_ctx *in_ctx, | |
1559 | struct xhci_input_control_ctx *ctrl_ctx, | |
1560 | struct xhci_virt_device *virt_dev) | |
1561 | { | |
1562 | struct xhci_bw_info *bw_info; | |
1563 | struct xhci_ep_ctx *ep_ctx; | |
1564 | unsigned int ep_type; | |
1565 | int i; | |
1566 | ||
98871e94 | 1567 | for (i = 1; i < 31; i++) { |
9af5d71d SS |
1568 | bw_info = &virt_dev->eps[i].bw_info; |
1569 | ||
1570 | /* We can't tell what endpoint type is being dropped, but | |
1571 | * unconditionally clearing the bandwidth info for non-periodic | |
1572 | * endpoints should be harmless because the info will never be | |
1573 | * set in the first place. | |
1574 | */ | |
1575 | if (!EP_IS_ADDED(ctrl_ctx, i) && EP_IS_DROPPED(ctrl_ctx, i)) { | |
1576 | /* Dropped endpoint */ | |
1577 | xhci_clear_endpoint_bw_info(bw_info); | |
1578 | continue; | |
1579 | } | |
1580 | ||
1581 | if (EP_IS_ADDED(ctrl_ctx, i)) { | |
1582 | ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, i); | |
1583 | ep_type = CTX_TO_EP_TYPE(le32_to_cpu(ep_ctx->ep_info2)); | |
1584 | ||
1585 | /* Ignore non-periodic endpoints */ | |
1586 | if (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP && | |
1587 | ep_type != ISOC_IN_EP && | |
1588 | ep_type != INT_IN_EP) | |
1589 | continue; | |
1590 | ||
1591 | /* Added or changed endpoint */ | |
1592 | bw_info->ep_interval = CTX_TO_EP_INTERVAL( | |
1593 | le32_to_cpu(ep_ctx->ep_info)); | |
170c0263 SS |
1594 | /* Number of packets and mult are zero-based in the |
1595 | * input context, but we want one-based for the | |
1596 | * interval table. | |
9af5d71d | 1597 | */ |
170c0263 SS |
1598 | bw_info->mult = CTX_TO_EP_MULT( |
1599 | le32_to_cpu(ep_ctx->ep_info)) + 1; | |
9af5d71d SS |
1600 | bw_info->num_packets = CTX_TO_MAX_BURST( |
1601 | le32_to_cpu(ep_ctx->ep_info2)) + 1; | |
1602 | bw_info->max_packet_size = MAX_PACKET_DECODED( | |
1603 | le32_to_cpu(ep_ctx->ep_info2)); | |
1604 | bw_info->type = ep_type; | |
1605 | bw_info->max_esit_payload = CTX_TO_MAX_ESIT_PAYLOAD( | |
1606 | le32_to_cpu(ep_ctx->tx_info)); | |
1607 | } | |
1608 | } | |
1609 | } | |
1610 | ||
f2217e8e SS |
1611 | /* Copy output xhci_ep_ctx to the input xhci_ep_ctx copy. |
1612 | * Useful when you want to change one particular aspect of the endpoint and then | |
1613 | * issue a configure endpoint command. | |
1614 | */ | |
1615 | void xhci_endpoint_copy(struct xhci_hcd *xhci, | |
913a8a34 SS |
1616 | struct xhci_container_ctx *in_ctx, |
1617 | struct xhci_container_ctx *out_ctx, | |
1618 | unsigned int ep_index) | |
f2217e8e SS |
1619 | { |
1620 | struct xhci_ep_ctx *out_ep_ctx; | |
1621 | struct xhci_ep_ctx *in_ep_ctx; | |
1622 | ||
913a8a34 SS |
1623 | out_ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index); |
1624 | in_ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index); | |
f2217e8e SS |
1625 | |
1626 | in_ep_ctx->ep_info = out_ep_ctx->ep_info; | |
1627 | in_ep_ctx->ep_info2 = out_ep_ctx->ep_info2; | |
1628 | in_ep_ctx->deq = out_ep_ctx->deq; | |
1629 | in_ep_ctx->tx_info = out_ep_ctx->tx_info; | |
0a3b5330 CY |
1630 | if (xhci->quirks & XHCI_MTK_HOST) { |
1631 | in_ep_ctx->reserved[0] = out_ep_ctx->reserved[0]; | |
1632 | in_ep_ctx->reserved[1] = out_ep_ctx->reserved[1]; | |
1633 | } | |
f2217e8e SS |
1634 | } |
1635 | ||
1636 | /* Copy output xhci_slot_ctx to the input xhci_slot_ctx. | |
1637 | * Useful when you want to change one particular aspect of the endpoint and then | |
1638 | * issue a configure endpoint command. Only the context entries field matters, | |
1639 | * but we'll copy the whole thing anyway. | |
1640 | */ | |
913a8a34 SS |
1641 | void xhci_slot_copy(struct xhci_hcd *xhci, |
1642 | struct xhci_container_ctx *in_ctx, | |
1643 | struct xhci_container_ctx *out_ctx) | |
f2217e8e SS |
1644 | { |
1645 | struct xhci_slot_ctx *in_slot_ctx; | |
1646 | struct xhci_slot_ctx *out_slot_ctx; | |
1647 | ||
913a8a34 SS |
1648 | in_slot_ctx = xhci_get_slot_ctx(xhci, in_ctx); |
1649 | out_slot_ctx = xhci_get_slot_ctx(xhci, out_ctx); | |
f2217e8e SS |
1650 | |
1651 | in_slot_ctx->dev_info = out_slot_ctx->dev_info; | |
1652 | in_slot_ctx->dev_info2 = out_slot_ctx->dev_info2; | |
1653 | in_slot_ctx->tt_info = out_slot_ctx->tt_info; | |
1654 | in_slot_ctx->dev_state = out_slot_ctx->dev_state; | |
1655 | } | |
1656 | ||
254c80a3 JY |
1657 | /* Set up the scratchpad buffer array and scratchpad buffers, if needed. */ |
1658 | static int scratchpad_alloc(struct xhci_hcd *xhci, gfp_t flags) | |
1659 | { | |
1660 | int i; | |
4c39d4b9 | 1661 | struct device *dev = xhci_to_hcd(xhci)->self.sysdev; |
254c80a3 JY |
1662 | int num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2); |
1663 | ||
d195fcff XR |
1664 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
1665 | "Allocating %d scratchpad buffers", num_sp); | |
254c80a3 JY |
1666 | |
1667 | if (!num_sp) | |
1668 | return 0; | |
1669 | ||
a965315e AW |
1670 | xhci->scratchpad = kzalloc_node(sizeof(*xhci->scratchpad), flags, |
1671 | dev_to_node(dev)); | |
254c80a3 JY |
1672 | if (!xhci->scratchpad) |
1673 | goto fail_sp; | |
1674 | ||
22d45f01 | 1675 | xhci->scratchpad->sp_array = dma_alloc_coherent(dev, |
254c80a3 | 1676 | num_sp * sizeof(u64), |
22d45f01 | 1677 | &xhci->scratchpad->sp_dma, flags); |
254c80a3 JY |
1678 | if (!xhci->scratchpad->sp_array) |
1679 | goto fail_sp2; | |
1680 | ||
a965315e AW |
1681 | xhci->scratchpad->sp_buffers = kcalloc_node(num_sp, sizeof(void *), |
1682 | flags, dev_to_node(dev)); | |
254c80a3 JY |
1683 | if (!xhci->scratchpad->sp_buffers) |
1684 | goto fail_sp3; | |
1685 | ||
28ccd296 | 1686 | xhci->dcbaa->dev_context_ptrs[0] = cpu_to_le64(xhci->scratchpad->sp_dma); |
254c80a3 JY |
1687 | for (i = 0; i < num_sp; i++) { |
1688 | dma_addr_t dma; | |
750afb08 LC |
1689 | void *buf = dma_alloc_coherent(dev, xhci->page_size, &dma, |
1690 | flags); | |
254c80a3 | 1691 | if (!buf) |
314eaf7d | 1692 | goto fail_sp4; |
254c80a3 JY |
1693 | |
1694 | xhci->scratchpad->sp_array[i] = dma; | |
1695 | xhci->scratchpad->sp_buffers[i] = buf; | |
254c80a3 JY |
1696 | } |
1697 | ||
1698 | return 0; | |
1699 | ||
314eaf7d | 1700 | fail_sp4: |
254c80a3 | 1701 | for (i = i - 1; i >= 0; i--) { |
22d45f01 | 1702 | dma_free_coherent(dev, xhci->page_size, |
254c80a3 | 1703 | xhci->scratchpad->sp_buffers[i], |
314eaf7d | 1704 | xhci->scratchpad->sp_array[i]); |
254c80a3 | 1705 | } |
254c80a3 | 1706 | |
254c80a3 JY |
1707 | kfree(xhci->scratchpad->sp_buffers); |
1708 | ||
1709 | fail_sp3: | |
22d45f01 | 1710 | dma_free_coherent(dev, num_sp * sizeof(u64), |
254c80a3 JY |
1711 | xhci->scratchpad->sp_array, |
1712 | xhci->scratchpad->sp_dma); | |
1713 | ||
1714 | fail_sp2: | |
1715 | kfree(xhci->scratchpad); | |
1716 | xhci->scratchpad = NULL; | |
1717 | ||
1718 | fail_sp: | |
1719 | return -ENOMEM; | |
1720 | } | |
1721 | ||
1722 | static void scratchpad_free(struct xhci_hcd *xhci) | |
1723 | { | |
1724 | int num_sp; | |
1725 | int i; | |
4c39d4b9 | 1726 | struct device *dev = xhci_to_hcd(xhci)->self.sysdev; |
254c80a3 JY |
1727 | |
1728 | if (!xhci->scratchpad) | |
1729 | return; | |
1730 | ||
1731 | num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2); | |
1732 | ||
1733 | for (i = 0; i < num_sp; i++) { | |
2a100047 | 1734 | dma_free_coherent(dev, xhci->page_size, |
254c80a3 | 1735 | xhci->scratchpad->sp_buffers[i], |
314eaf7d | 1736 | xhci->scratchpad->sp_array[i]); |
254c80a3 | 1737 | } |
254c80a3 | 1738 | kfree(xhci->scratchpad->sp_buffers); |
2a100047 | 1739 | dma_free_coherent(dev, num_sp * sizeof(u64), |
254c80a3 JY |
1740 | xhci->scratchpad->sp_array, |
1741 | xhci->scratchpad->sp_dma); | |
1742 | kfree(xhci->scratchpad); | |
1743 | xhci->scratchpad = NULL; | |
1744 | } | |
1745 | ||
913a8a34 | 1746 | struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci, |
103afda0 | 1747 | bool allocate_completion, gfp_t mem_flags) |
913a8a34 SS |
1748 | { |
1749 | struct xhci_command *command; | |
a965315e | 1750 | struct device *dev = xhci_to_hcd(xhci)->self.sysdev; |
913a8a34 | 1751 | |
a965315e | 1752 | command = kzalloc_node(sizeof(*command), mem_flags, dev_to_node(dev)); |
913a8a34 SS |
1753 | if (!command) |
1754 | return NULL; | |
1755 | ||
913a8a34 SS |
1756 | if (allocate_completion) { |
1757 | command->completion = | |
a965315e AW |
1758 | kzalloc_node(sizeof(struct completion), mem_flags, |
1759 | dev_to_node(dev)); | |
913a8a34 | 1760 | if (!command->completion) { |
06e18291 | 1761 | kfree(command); |
913a8a34 SS |
1762 | return NULL; |
1763 | } | |
1764 | init_completion(command->completion); | |
1765 | } | |
1766 | ||
1767 | command->status = 0; | |
1768 | INIT_LIST_HEAD(&command->cmd_list); | |
1769 | return command; | |
1770 | } | |
1771 | ||
14d49b7a MN |
1772 | struct xhci_command *xhci_alloc_command_with_ctx(struct xhci_hcd *xhci, |
1773 | bool allocate_completion, gfp_t mem_flags) | |
1774 | { | |
1775 | struct xhci_command *command; | |
1776 | ||
103afda0 | 1777 | command = xhci_alloc_command(xhci, allocate_completion, mem_flags); |
14d49b7a MN |
1778 | if (!command) |
1779 | return NULL; | |
1780 | ||
1781 | command->in_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT, | |
1782 | mem_flags); | |
1783 | if (!command->in_ctx) { | |
1784 | kfree(command->completion); | |
1785 | kfree(command); | |
1786 | return NULL; | |
1787 | } | |
1788 | return command; | |
1789 | } | |
1790 | ||
4daf9df5 | 1791 | void xhci_urb_free_priv(struct urb_priv *urb_priv) |
8e51adcc | 1792 | { |
7e64b037 | 1793 | kfree(urb_priv); |
8e51adcc AX |
1794 | } |
1795 | ||
913a8a34 SS |
1796 | void xhci_free_command(struct xhci_hcd *xhci, |
1797 | struct xhci_command *command) | |
1798 | { | |
1799 | xhci_free_container_ctx(xhci, | |
1800 | command->in_ctx); | |
1801 | kfree(command->completion); | |
1802 | kfree(command); | |
1803 | } | |
1804 | ||
67d2ea9f LB |
1805 | int xhci_alloc_erst(struct xhci_hcd *xhci, |
1806 | struct xhci_ring *evt_ring, | |
1807 | struct xhci_erst *erst, | |
1808 | gfp_t flags) | |
1809 | { | |
1810 | size_t size; | |
1811 | unsigned int val; | |
1812 | struct xhci_segment *seg; | |
1813 | struct xhci_erst_entry *entry; | |
1814 | ||
1815 | size = sizeof(struct xhci_erst_entry) * evt_ring->num_segs; | |
750afb08 LC |
1816 | erst->entries = dma_alloc_coherent(xhci_to_hcd(xhci)->self.sysdev, |
1817 | size, &erst->erst_dma_addr, flags); | |
67d2ea9f LB |
1818 | if (!erst->entries) |
1819 | return -ENOMEM; | |
1820 | ||
67d2ea9f LB |
1821 | erst->num_entries = evt_ring->num_segs; |
1822 | ||
1823 | seg = evt_ring->first_seg; | |
1824 | for (val = 0; val < evt_ring->num_segs; val++) { | |
1825 | entry = &erst->entries[val]; | |
1826 | entry->seg_addr = cpu_to_le64(seg->dma); | |
1827 | entry->seg_size = cpu_to_le32(TRBS_PER_SEGMENT); | |
1828 | entry->rsvd = 0; | |
1829 | seg = seg->next; | |
1830 | } | |
1831 | ||
1832 | return 0; | |
1833 | } | |
1834 | ||
1835 | void xhci_free_erst(struct xhci_hcd *xhci, struct xhci_erst *erst) | |
1836 | { | |
1837 | size_t size; | |
1838 | struct device *dev = xhci_to_hcd(xhci)->self.sysdev; | |
1839 | ||
1840 | size = sizeof(struct xhci_erst_entry) * (erst->num_entries); | |
1841 | if (erst->entries) | |
1842 | dma_free_coherent(dev, size, | |
1843 | erst->entries, | |
1844 | erst->erst_dma_addr); | |
1845 | erst->entries = NULL; | |
1846 | } | |
1847 | ||
66d4eadd SS |
1848 | void xhci_mem_cleanup(struct xhci_hcd *xhci) |
1849 | { | |
4c39d4b9 | 1850 | struct device *dev = xhci_to_hcd(xhci)->self.sysdev; |
32f1d2c5 | 1851 | int i, j, num_ports; |
0ebbab37 | 1852 | |
cb4d5ce5 | 1853 | cancel_delayed_work_sync(&xhci->cmd_timer); |
c311e391 | 1854 | |
67d2ea9f LB |
1855 | xhci_free_erst(xhci, &xhci->erst); |
1856 | ||
0ebbab37 SS |
1857 | if (xhci->event_ring) |
1858 | xhci_ring_free(xhci, xhci->event_ring); | |
1859 | xhci->event_ring = NULL; | |
d195fcff | 1860 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed event ring"); |
0ebbab37 | 1861 | |
dbc33303 SS |
1862 | if (xhci->lpm_command) |
1863 | xhci_free_command(xhci, xhci->lpm_command); | |
0eda06c7 | 1864 | xhci->lpm_command = NULL; |
0ebbab37 SS |
1865 | if (xhci->cmd_ring) |
1866 | xhci_ring_free(xhci, xhci->cmd_ring); | |
1867 | xhci->cmd_ring = NULL; | |
d195fcff | 1868 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed command ring"); |
c9aa1a2d | 1869 | xhci_cleanup_command_queue(xhci); |
3ffbba95 | 1870 | |
5dc2808c | 1871 | num_ports = HCS_MAX_PORTS(xhci->hcs_params1); |
c207e7c5 | 1872 | for (i = 0; i < num_ports && xhci->rh_bw; i++) { |
5dc2808c MN |
1873 | struct xhci_interval_bw_table *bwt = &xhci->rh_bw[i].bw_table; |
1874 | for (j = 0; j < XHCI_MAX_INTERVAL; j++) { | |
1875 | struct list_head *ep = &bwt->interval_bw[j].endpoints; | |
1876 | while (!list_empty(ep)) | |
1877 | list_del_init(ep->next); | |
1878 | } | |
1879 | } | |
1880 | ||
ee8665e2 MN |
1881 | for (i = HCS_MAX_SLOTS(xhci->hcs_params1); i > 0; i--) |
1882 | xhci_free_virt_devices_depth_first(xhci, i); | |
3ffbba95 | 1883 | |
c7360b34 | 1884 | dma_pool_destroy(xhci->segment_pool); |
0ebbab37 | 1885 | xhci->segment_pool = NULL; |
d195fcff | 1886 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed segment pool"); |
3ffbba95 | 1887 | |
c7360b34 | 1888 | dma_pool_destroy(xhci->device_pool); |
3ffbba95 | 1889 | xhci->device_pool = NULL; |
d195fcff | 1890 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed device context pool"); |
3ffbba95 | 1891 | |
c7360b34 | 1892 | dma_pool_destroy(xhci->small_streams_pool); |
8df75f42 | 1893 | xhci->small_streams_pool = NULL; |
d195fcff XR |
1894 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
1895 | "Freed small stream array pool"); | |
8df75f42 | 1896 | |
c7360b34 | 1897 | dma_pool_destroy(xhci->medium_streams_pool); |
8df75f42 | 1898 | xhci->medium_streams_pool = NULL; |
d195fcff XR |
1899 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
1900 | "Freed medium stream array pool"); | |
8df75f42 | 1901 | |
a74588f9 | 1902 | if (xhci->dcbaa) |
2a100047 | 1903 | dma_free_coherent(dev, sizeof(*xhci->dcbaa), |
a74588f9 SS |
1904 | xhci->dcbaa, xhci->dcbaa->dma); |
1905 | xhci->dcbaa = NULL; | |
3ffbba95 | 1906 | |
5294bea4 | 1907 | scratchpad_free(xhci); |
da6699ce | 1908 | |
88696ae4 VM |
1909 | if (!xhci->rh_bw) |
1910 | goto no_bw; | |
1911 | ||
32f1d2c5 TI |
1912 | for (i = 0; i < num_ports; i++) { |
1913 | struct xhci_tt_bw_info *tt, *n; | |
1914 | list_for_each_entry_safe(tt, n, &xhci->rh_bw[i].tts, tt_list) { | |
1915 | list_del(&tt->tt_list); | |
1916 | kfree(tt); | |
1917 | } | |
f8a9e72d ON |
1918 | } |
1919 | ||
88696ae4 | 1920 | no_bw: |
127329d7 | 1921 | xhci->cmd_ring_reserved_trbs = 0; |
bcaa9d5c MN |
1922 | xhci->usb2_rhub.num_ports = 0; |
1923 | xhci->usb3_rhub.num_ports = 0; | |
f8a9e72d | 1924 | xhci->num_active_eps = 0; |
bcaa9d5c MN |
1925 | kfree(xhci->usb2_rhub.ports); |
1926 | kfree(xhci->usb3_rhub.ports); | |
1927 | kfree(xhci->hw_ports); | |
839c817c | 1928 | kfree(xhci->rh_bw); |
b630d4b9 | 1929 | kfree(xhci->ext_caps); |
cf0ee7c6 MN |
1930 | for (i = 0; i < xhci->num_port_caps; i++) |
1931 | kfree(xhci->port_caps[i].psi); | |
1932 | kfree(xhci->port_caps); | |
1933 | xhci->num_port_caps = 0; | |
da6699ce | 1934 | |
bcaa9d5c MN |
1935 | xhci->usb2_rhub.ports = NULL; |
1936 | xhci->usb3_rhub.ports = NULL; | |
1937 | xhci->hw_ports = NULL; | |
71504062 LB |
1938 | xhci->rh_bw = NULL; |
1939 | xhci->ext_caps = NULL; | |
1940 | ||
66d4eadd SS |
1941 | xhci->page_size = 0; |
1942 | xhci->page_shift = 0; | |
f6187f42 MN |
1943 | xhci->usb2_rhub.bus_state.bus_suspended = 0; |
1944 | xhci->usb3_rhub.bus_state.bus_suspended = 0; | |
66d4eadd SS |
1945 | } |
1946 | ||
6648f29d SS |
1947 | static int xhci_test_trb_in_td(struct xhci_hcd *xhci, |
1948 | struct xhci_segment *input_seg, | |
1949 | union xhci_trb *start_trb, | |
1950 | union xhci_trb *end_trb, | |
1951 | dma_addr_t input_dma, | |
1952 | struct xhci_segment *result_seg, | |
1953 | char *test_name, int test_number) | |
1954 | { | |
1955 | unsigned long long start_dma; | |
1956 | unsigned long long end_dma; | |
1957 | struct xhci_segment *seg; | |
1958 | ||
1959 | start_dma = xhci_trb_virt_to_dma(input_seg, start_trb); | |
1960 | end_dma = xhci_trb_virt_to_dma(input_seg, end_trb); | |
1961 | ||
cffb9be8 | 1962 | seg = trb_in_td(xhci, input_seg, start_trb, end_trb, input_dma, false); |
6648f29d SS |
1963 | if (seg != result_seg) { |
1964 | xhci_warn(xhci, "WARN: %s TRB math test %d failed!\n", | |
1965 | test_name, test_number); | |
1966 | xhci_warn(xhci, "Tested TRB math w/ seg %p and " | |
1967 | "input DMA 0x%llx\n", | |
1968 | input_seg, | |
1969 | (unsigned long long) input_dma); | |
1970 | xhci_warn(xhci, "starting TRB %p (0x%llx DMA), " | |
1971 | "ending TRB %p (0x%llx DMA)\n", | |
1972 | start_trb, start_dma, | |
1973 | end_trb, end_dma); | |
1974 | xhci_warn(xhci, "Expected seg %p, got seg %p\n", | |
1975 | result_seg, seg); | |
cffb9be8 HG |
1976 | trb_in_td(xhci, input_seg, start_trb, end_trb, input_dma, |
1977 | true); | |
6648f29d SS |
1978 | return -1; |
1979 | } | |
1980 | return 0; | |
1981 | } | |
1982 | ||
1983 | /* TRB math checks for xhci_trb_in_td(), using the command and event rings. */ | |
4daf9df5 | 1984 | static int xhci_check_trb_in_td_math(struct xhci_hcd *xhci) |
6648f29d SS |
1985 | { |
1986 | struct { | |
1987 | dma_addr_t input_dma; | |
1988 | struct xhci_segment *result_seg; | |
1989 | } simple_test_vector [] = { | |
1990 | /* A zeroed DMA field should fail */ | |
1991 | { 0, NULL }, | |
1992 | /* One TRB before the ring start should fail */ | |
1993 | { xhci->event_ring->first_seg->dma - 16, NULL }, | |
1994 | /* One byte before the ring start should fail */ | |
1995 | { xhci->event_ring->first_seg->dma - 1, NULL }, | |
1996 | /* Starting TRB should succeed */ | |
1997 | { xhci->event_ring->first_seg->dma, xhci->event_ring->first_seg }, | |
1998 | /* Ending TRB should succeed */ | |
1999 | { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16, | |
2000 | xhci->event_ring->first_seg }, | |
2001 | /* One byte after the ring end should fail */ | |
2002 | { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16 + 1, NULL }, | |
2003 | /* One TRB after the ring end should fail */ | |
2004 | { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT)*16, NULL }, | |
2005 | /* An address of all ones should fail */ | |
2006 | { (dma_addr_t) (~0), NULL }, | |
2007 | }; | |
2008 | struct { | |
2009 | struct xhci_segment *input_seg; | |
2010 | union xhci_trb *start_trb; | |
2011 | union xhci_trb *end_trb; | |
2012 | dma_addr_t input_dma; | |
2013 | struct xhci_segment *result_seg; | |
2014 | } complex_test_vector [] = { | |
2015 | /* Test feeding a valid DMA address from a different ring */ | |
2016 | { .input_seg = xhci->event_ring->first_seg, | |
2017 | .start_trb = xhci->event_ring->first_seg->trbs, | |
2018 | .end_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1], | |
2019 | .input_dma = xhci->cmd_ring->first_seg->dma, | |
2020 | .result_seg = NULL, | |
2021 | }, | |
2022 | /* Test feeding a valid end TRB from a different ring */ | |
2023 | { .input_seg = xhci->event_ring->first_seg, | |
2024 | .start_trb = xhci->event_ring->first_seg->trbs, | |
2025 | .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1], | |
2026 | .input_dma = xhci->cmd_ring->first_seg->dma, | |
2027 | .result_seg = NULL, | |
2028 | }, | |
2029 | /* Test feeding a valid start and end TRB from a different ring */ | |
2030 | { .input_seg = xhci->event_ring->first_seg, | |
2031 | .start_trb = xhci->cmd_ring->first_seg->trbs, | |
2032 | .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1], | |
2033 | .input_dma = xhci->cmd_ring->first_seg->dma, | |
2034 | .result_seg = NULL, | |
2035 | }, | |
2036 | /* TRB in this ring, but after this TD */ | |
2037 | { .input_seg = xhci->event_ring->first_seg, | |
2038 | .start_trb = &xhci->event_ring->first_seg->trbs[0], | |
2039 | .end_trb = &xhci->event_ring->first_seg->trbs[3], | |
2040 | .input_dma = xhci->event_ring->first_seg->dma + 4*16, | |
2041 | .result_seg = NULL, | |
2042 | }, | |
2043 | /* TRB in this ring, but before this TD */ | |
2044 | { .input_seg = xhci->event_ring->first_seg, | |
2045 | .start_trb = &xhci->event_ring->first_seg->trbs[3], | |
2046 | .end_trb = &xhci->event_ring->first_seg->trbs[6], | |
2047 | .input_dma = xhci->event_ring->first_seg->dma + 2*16, | |
2048 | .result_seg = NULL, | |
2049 | }, | |
2050 | /* TRB in this ring, but after this wrapped TD */ | |
2051 | { .input_seg = xhci->event_ring->first_seg, | |
2052 | .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3], | |
2053 | .end_trb = &xhci->event_ring->first_seg->trbs[1], | |
2054 | .input_dma = xhci->event_ring->first_seg->dma + 2*16, | |
2055 | .result_seg = NULL, | |
2056 | }, | |
2057 | /* TRB in this ring, but before this wrapped TD */ | |
2058 | { .input_seg = xhci->event_ring->first_seg, | |
2059 | .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3], | |
2060 | .end_trb = &xhci->event_ring->first_seg->trbs[1], | |
2061 | .input_dma = xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 4)*16, | |
2062 | .result_seg = NULL, | |
2063 | }, | |
2064 | /* TRB not in this ring, and we have a wrapped TD */ | |
2065 | { .input_seg = xhci->event_ring->first_seg, | |
2066 | .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3], | |
2067 | .end_trb = &xhci->event_ring->first_seg->trbs[1], | |
2068 | .input_dma = xhci->cmd_ring->first_seg->dma + 2*16, | |
2069 | .result_seg = NULL, | |
2070 | }, | |
2071 | }; | |
2072 | ||
2073 | unsigned int num_tests; | |
2074 | int i, ret; | |
2075 | ||
e10fa478 | 2076 | num_tests = ARRAY_SIZE(simple_test_vector); |
6648f29d SS |
2077 | for (i = 0; i < num_tests; i++) { |
2078 | ret = xhci_test_trb_in_td(xhci, | |
2079 | xhci->event_ring->first_seg, | |
2080 | xhci->event_ring->first_seg->trbs, | |
2081 | &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1], | |
2082 | simple_test_vector[i].input_dma, | |
2083 | simple_test_vector[i].result_seg, | |
2084 | "Simple", i); | |
2085 | if (ret < 0) | |
2086 | return ret; | |
2087 | } | |
2088 | ||
e10fa478 | 2089 | num_tests = ARRAY_SIZE(complex_test_vector); |
6648f29d SS |
2090 | for (i = 0; i < num_tests; i++) { |
2091 | ret = xhci_test_trb_in_td(xhci, | |
2092 | complex_test_vector[i].input_seg, | |
2093 | complex_test_vector[i].start_trb, | |
2094 | complex_test_vector[i].end_trb, | |
2095 | complex_test_vector[i].input_dma, | |
2096 | complex_test_vector[i].result_seg, | |
2097 | "Complex", i); | |
2098 | if (ret < 0) | |
2099 | return ret; | |
2100 | } | |
2101 | xhci_dbg(xhci, "TRB math tests passed.\n"); | |
2102 | return 0; | |
2103 | } | |
2104 | ||
257d585a SS |
2105 | static void xhci_set_hc_event_deq(struct xhci_hcd *xhci) |
2106 | { | |
2107 | u64 temp; | |
2108 | dma_addr_t deq; | |
2109 | ||
2110 | deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg, | |
2111 | xhci->event_ring->dequeue); | |
96eea587 | 2112 | if (!deq) |
257d585a SS |
2113 | xhci_warn(xhci, "WARN something wrong with SW event ring " |
2114 | "dequeue ptr.\n"); | |
2115 | /* Update HC event ring dequeue pointer */ | |
f7b2e403 | 2116 | temp = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); |
257d585a SS |
2117 | temp &= ERST_PTR_MASK; |
2118 | /* Don't clear the EHB bit (which is RW1C) because | |
2119 | * there might be more events to service. | |
2120 | */ | |
2121 | temp &= ~ERST_EHB; | |
d195fcff XR |
2122 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2123 | "// Write event ring dequeue pointer, " | |
2124 | "preserving EHB bit"); | |
477632df | 2125 | xhci_write_64(xhci, ((u64) deq & (u64) ~ERST_PTR_MASK) | temp, |
257d585a SS |
2126 | &xhci->ir_set->erst_dequeue); |
2127 | } | |
2128 | ||
da6699ce | 2129 | static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int num_ports, |
d5ddcdf4 | 2130 | __le32 __iomem *addr, int max_caps) |
da6699ce SS |
2131 | { |
2132 | u32 temp, port_offset, port_count; | |
2133 | int i; | |
b72eb843 | 2134 | u8 major_revision, minor_revision; |
47189098 | 2135 | struct xhci_hub *rhub; |
a965315e | 2136 | struct device *dev = xhci_to_hcd(xhci)->self.sysdev; |
cf0ee7c6 | 2137 | struct xhci_port_cap *port_cap; |
da6699ce | 2138 | |
47189098 | 2139 | temp = readl(addr); |
d5ddcdf4 | 2140 | major_revision = XHCI_EXT_PORT_MAJOR(temp); |
b72eb843 | 2141 | minor_revision = XHCI_EXT_PORT_MINOR(temp); |
47189098 | 2142 | |
d5ddcdf4 | 2143 | if (major_revision == 0x03) { |
47189098 | 2144 | rhub = &xhci->usb3_rhub; |
628a55ff TN |
2145 | /* |
2146 | * Some hosts incorrectly use sub-minor version for minor | |
2147 | * version (i.e. 0x02 instead of 0x20 for bcdUSB 0x320 and 0x01 | |
2148 | * for bcdUSB 0x310). Since there is no USB release with sub | |
2149 | * minor version 0x301 to 0x309, we can assume that they are | |
2150 | * incorrect and fix it here. | |
2151 | */ | |
2152 | if (minor_revision > 0x00 && minor_revision < 0x10) | |
2153 | minor_revision <<= 4; | |
d5ddcdf4 | 2154 | } else if (major_revision <= 0x02) { |
47189098 MN |
2155 | rhub = &xhci->usb2_rhub; |
2156 | } else { | |
da6699ce SS |
2157 | xhci_warn(xhci, "Ignoring unknown port speed, " |
2158 | "Ext Cap %p, revision = 0x%x\n", | |
2159 | addr, major_revision); | |
2160 | /* Ignoring port protocol we can't understand. FIXME */ | |
2161 | return; | |
2162 | } | |
47189098 | 2163 | rhub->maj_rev = XHCI_EXT_PORT_MAJOR(temp); |
b72eb843 YT |
2164 | |
2165 | if (rhub->min_rev < minor_revision) | |
2166 | rhub->min_rev = minor_revision; | |
da6699ce SS |
2167 | |
2168 | /* Port offset and count in the third dword, see section 7.2 */ | |
b0ba9720 | 2169 | temp = readl(addr + 2); |
da6699ce SS |
2170 | port_offset = XHCI_EXT_PORT_OFF(temp); |
2171 | port_count = XHCI_EXT_PORT_COUNT(temp); | |
d195fcff XR |
2172 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2173 | "Ext Cap %p, port offset = %u, " | |
2174 | "count = %u, revision = 0x%x", | |
da6699ce SS |
2175 | addr, port_offset, port_count, major_revision); |
2176 | /* Port count includes the current port offset */ | |
2177 | if (port_offset == 0 || (port_offset + port_count - 1) > num_ports) | |
2178 | /* WTF? "Valid values are ‘1’ to MaxPorts" */ | |
2179 | return; | |
fc71ff75 | 2180 | |
cf0ee7c6 MN |
2181 | port_cap = &xhci->port_caps[xhci->num_port_caps++]; |
2182 | if (xhci->num_port_caps > max_caps) | |
2183 | return; | |
2184 | ||
2185 | port_cap->maj_rev = major_revision; | |
2186 | port_cap->min_rev = minor_revision; | |
2187 | port_cap->psi_count = XHCI_EXT_PORT_PSIC(temp); | |
2188 | ||
2189 | if (port_cap->psi_count) { | |
2190 | port_cap->psi = kcalloc_node(port_cap->psi_count, | |
2191 | sizeof(*port_cap->psi), | |
2192 | GFP_KERNEL, dev_to_node(dev)); | |
2193 | if (!port_cap->psi) | |
2194 | port_cap->psi_count = 0; | |
47189098 | 2195 | |
cf0ee7c6 MN |
2196 | port_cap->psi_uid_count++; |
2197 | for (i = 0; i < port_cap->psi_count; i++) { | |
2198 | port_cap->psi[i] = readl(addr + 4 + i); | |
47189098 MN |
2199 | |
2200 | /* count unique ID values, two consecutive entries can | |
2201 | * have the same ID if link is assymetric | |
2202 | */ | |
cf0ee7c6 MN |
2203 | if (i && (XHCI_EXT_PORT_PSIV(port_cap->psi[i]) != |
2204 | XHCI_EXT_PORT_PSIV(port_cap->psi[i - 1]))) | |
2205 | port_cap->psi_uid_count++; | |
47189098 MN |
2206 | |
2207 | xhci_dbg(xhci, "PSIV:%d PSIE:%d PLT:%d PFD:%d LP:%d PSIM:%d\n", | |
cf0ee7c6 MN |
2208 | XHCI_EXT_PORT_PSIV(port_cap->psi[i]), |
2209 | XHCI_EXT_PORT_PSIE(port_cap->psi[i]), | |
2210 | XHCI_EXT_PORT_PLT(port_cap->psi[i]), | |
2211 | XHCI_EXT_PORT_PFD(port_cap->psi[i]), | |
2212 | XHCI_EXT_PORT_LP(port_cap->psi[i]), | |
2213 | XHCI_EXT_PORT_PSIM(port_cap->psi[i])); | |
47189098 MN |
2214 | } |
2215 | } | |
b630d4b9 MN |
2216 | /* cache usb2 port capabilities */ |
2217 | if (major_revision < 0x03 && xhci->num_ext_caps < max_caps) | |
2218 | xhci->ext_caps[xhci->num_ext_caps++] = temp; | |
2219 | ||
f1fd62a6 ZT |
2220 | if ((xhci->hci_version >= 0x100) && (major_revision != 0x03) && |
2221 | (temp & XHCI_HLC)) { | |
d195fcff | 2222 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
f1fd62a6 ZT |
2223 | "xHCI 1.0: support USB2 hardware lpm"); |
2224 | xhci->hw_lpm_support = 1; | |
fc71ff75 AX |
2225 | } |
2226 | ||
da6699ce SS |
2227 | port_offset--; |
2228 | for (i = port_offset; i < (port_offset + port_count); i++) { | |
bcaa9d5c | 2229 | struct xhci_port *hw_port = &xhci->hw_ports[i]; |
da6699ce | 2230 | /* Duplicate entry. Ignore the port if the revisions differ. */ |
07f76190 | 2231 | if (hw_port->rhub) { |
da6699ce SS |
2232 | xhci_warn(xhci, "Duplicate port entry, Ext Cap %p," |
2233 | " port %u\n", addr, i); | |
2234 | xhci_warn(xhci, "Port was marked as USB %u, " | |
2235 | "duplicated as USB %u\n", | |
07f76190 | 2236 | hw_port->rhub->maj_rev, major_revision); |
da6699ce SS |
2237 | /* Only adjust the roothub port counts if we haven't |
2238 | * found a similar duplicate. | |
2239 | */ | |
bcaa9d5c MN |
2240 | if (hw_port->rhub != rhub && |
2241 | hw_port->hcd_portnum != DUPLICATE_ENTRY) { | |
2242 | hw_port->rhub->num_ports--; | |
2243 | hw_port->hcd_portnum = DUPLICATE_ENTRY; | |
2244 | } | |
f8bbeabc | 2245 | continue; |
da6699ce | 2246 | } |
bcaa9d5c | 2247 | hw_port->rhub = rhub; |
cf0ee7c6 | 2248 | hw_port->port_cap = port_cap; |
bcaa9d5c | 2249 | rhub->num_ports++; |
da6699ce SS |
2250 | } |
2251 | /* FIXME: Should we disable ports not in the Extended Capabilities? */ | |
2252 | } | |
2253 | ||
bcaa9d5c MN |
2254 | static void xhci_create_rhub_port_array(struct xhci_hcd *xhci, |
2255 | struct xhci_hub *rhub, gfp_t flags) | |
2256 | { | |
2257 | int port_index = 0; | |
2258 | int i; | |
a965315e | 2259 | struct device *dev = xhci_to_hcd(xhci)->self.sysdev; |
bcaa9d5c MN |
2260 | |
2261 | if (!rhub->num_ports) | |
2262 | return; | |
a75e2d60 CIK |
2263 | rhub->ports = kcalloc_node(rhub->num_ports, sizeof(*rhub->ports), |
2264 | flags, dev_to_node(dev)); | |
a8b55f84 MN |
2265 | if (!rhub->ports) |
2266 | return; | |
2267 | ||
bcaa9d5c MN |
2268 | for (i = 0; i < HCS_MAX_PORTS(xhci->hcs_params1); i++) { |
2269 | if (xhci->hw_ports[i].rhub != rhub || | |
2270 | xhci->hw_ports[i].hcd_portnum == DUPLICATE_ENTRY) | |
2271 | continue; | |
2272 | xhci->hw_ports[i].hcd_portnum = port_index; | |
2273 | rhub->ports[port_index] = &xhci->hw_ports[i]; | |
2274 | port_index++; | |
2275 | if (port_index == rhub->num_ports) | |
2276 | break; | |
2277 | } | |
2278 | } | |
2279 | ||
da6699ce SS |
2280 | /* |
2281 | * Scan the Extended Capabilities for the "Supported Protocol Capabilities" that | |
2282 | * specify what speeds each port is supposed to be. We can't count on the port | |
2283 | * speed bits in the PORTSC register being correct until a device is connected, | |
2284 | * but we need to set up the two fake roothubs with the correct number of USB | |
2285 | * 3.0 and USB 2.0 ports at host controller initialization time. | |
2286 | */ | |
2287 | static int xhci_setup_port_arrays(struct xhci_hcd *xhci, gfp_t flags) | |
2288 | { | |
d5ddcdf4 MN |
2289 | void __iomem *base; |
2290 | u32 offset; | |
da6699ce | 2291 | unsigned int num_ports; |
07f76190 | 2292 | int i, j; |
b630d4b9 | 2293 | int cap_count = 0; |
d5ddcdf4 | 2294 | u32 cap_start; |
a965315e | 2295 | struct device *dev = xhci_to_hcd(xhci)->self.sysdev; |
da6699ce SS |
2296 | |
2297 | num_ports = HCS_MAX_PORTS(xhci->hcs_params1); | |
a965315e AW |
2298 | xhci->hw_ports = kcalloc_node(num_ports, sizeof(*xhci->hw_ports), |
2299 | flags, dev_to_node(dev)); | |
07f76190 | 2300 | if (!xhci->hw_ports) |
da6699ce SS |
2301 | return -ENOMEM; |
2302 | ||
bcaa9d5c MN |
2303 | for (i = 0; i < num_ports; i++) { |
2304 | xhci->hw_ports[i].addr = &xhci->op_regs->port_status_base + | |
2305 | NUM_PORT_REGS * i; | |
2306 | xhci->hw_ports[i].hw_portnum = i; | |
2307 | } | |
2308 | ||
590b5b7d KC |
2309 | xhci->rh_bw = kcalloc_node(num_ports, sizeof(*xhci->rh_bw), flags, |
2310 | dev_to_node(dev)); | |
839c817c SS |
2311 | if (!xhci->rh_bw) |
2312 | return -ENOMEM; | |
2e27980e SS |
2313 | for (i = 0; i < num_ports; i++) { |
2314 | struct xhci_interval_bw_table *bw_table; | |
2315 | ||
839c817c | 2316 | INIT_LIST_HEAD(&xhci->rh_bw[i].tts); |
2e27980e SS |
2317 | bw_table = &xhci->rh_bw[i].bw_table; |
2318 | for (j = 0; j < XHCI_MAX_INTERVAL; j++) | |
2319 | INIT_LIST_HEAD(&bw_table->interval_bw[j].endpoints); | |
2320 | } | |
d5ddcdf4 | 2321 | base = &xhci->cap_regs->hc_capbase; |
839c817c | 2322 | |
d5ddcdf4 MN |
2323 | cap_start = xhci_find_next_ext_cap(base, 0, XHCI_EXT_CAPS_PROTOCOL); |
2324 | if (!cap_start) { | |
2325 | xhci_err(xhci, "No Extended Capability registers, unable to set up roothub\n"); | |
2326 | return -ENODEV; | |
2327 | } | |
b630d4b9 | 2328 | |
d5ddcdf4 | 2329 | offset = cap_start; |
b630d4b9 | 2330 | /* count extended protocol capability entries for later caching */ |
d5ddcdf4 MN |
2331 | while (offset) { |
2332 | cap_count++; | |
2333 | offset = xhci_find_next_ext_cap(base, offset, | |
2334 | XHCI_EXT_CAPS_PROTOCOL); | |
2335 | } | |
b630d4b9 | 2336 | |
a965315e AW |
2337 | xhci->ext_caps = kcalloc_node(cap_count, sizeof(*xhci->ext_caps), |
2338 | flags, dev_to_node(dev)); | |
b630d4b9 MN |
2339 | if (!xhci->ext_caps) |
2340 | return -ENOMEM; | |
2341 | ||
cf0ee7c6 MN |
2342 | xhci->port_caps = kcalloc_node(cap_count, sizeof(*xhci->port_caps), |
2343 | flags, dev_to_node(dev)); | |
2344 | if (!xhci->port_caps) | |
2345 | return -ENOMEM; | |
2346 | ||
d5ddcdf4 MN |
2347 | offset = cap_start; |
2348 | ||
2349 | while (offset) { | |
2350 | xhci_add_in_port(xhci, num_ports, base + offset, cap_count); | |
bcaa9d5c MN |
2351 | if (xhci->usb2_rhub.num_ports + xhci->usb3_rhub.num_ports == |
2352 | num_ports) | |
2353 | break; | |
d5ddcdf4 MN |
2354 | offset = xhci_find_next_ext_cap(base, offset, |
2355 | XHCI_EXT_CAPS_PROTOCOL); | |
da6699ce | 2356 | } |
bcaa9d5c MN |
2357 | if (xhci->usb2_rhub.num_ports == 0 && xhci->usb3_rhub.num_ports == 0) { |
2358 | xhci_warn(xhci, "No ports on the roothubs?\n"); | |
2359 | return -ENODEV; | |
2360 | } | |
d195fcff | 2361 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
07f76190 MN |
2362 | "Found %u USB 2.0 ports and %u USB 3.0 ports.", |
2363 | xhci->usb2_rhub.num_ports, xhci->usb3_rhub.num_ports); | |
d30b2a20 SS |
2364 | |
2365 | /* Place limits on the number of roothub ports so that the hub | |
2366 | * descriptors aren't longer than the USB core will allocate. | |
2367 | */ | |
07f76190 | 2368 | if (xhci->usb3_rhub.num_ports > USB_SS_MAXPORTS) { |
d195fcff | 2369 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
5120a266 JH |
2370 | "Limiting USB 3.0 roothub ports to %u.", |
2371 | USB_SS_MAXPORTS); | |
07f76190 | 2372 | xhci->usb3_rhub.num_ports = USB_SS_MAXPORTS; |
d30b2a20 | 2373 | } |
07f76190 | 2374 | if (xhci->usb2_rhub.num_ports > USB_MAXCHILDREN) { |
d195fcff XR |
2375 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2376 | "Limiting USB 2.0 roothub ports to %u.", | |
d30b2a20 | 2377 | USB_MAXCHILDREN); |
07f76190 | 2378 | xhci->usb2_rhub.num_ports = USB_MAXCHILDREN; |
d30b2a20 SS |
2379 | } |
2380 | ||
da6699ce SS |
2381 | /* |
2382 | * Note we could have all USB 3.0 ports, or all USB 2.0 ports. | |
2383 | * Not sure how the USB core will handle a hub with no ports... | |
2384 | */ | |
bcaa9d5c MN |
2385 | |
2386 | xhci_create_rhub_port_array(xhci, &xhci->usb2_rhub, flags); | |
2387 | xhci_create_rhub_port_array(xhci, &xhci->usb3_rhub, flags); | |
2388 | ||
da6699ce SS |
2389 | return 0; |
2390 | } | |
6648f29d | 2391 | |
66d4eadd SS |
2392 | int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags) |
2393 | { | |
0ebbab37 | 2394 | dma_addr_t dma; |
4c39d4b9 | 2395 | struct device *dev = xhci_to_hcd(xhci)->self.sysdev; |
66d4eadd | 2396 | unsigned int val, val2; |
8e595a5d | 2397 | u64 val_64; |
67d2ea9f LB |
2398 | u32 page_size, temp; |
2399 | int i, ret; | |
66d4eadd | 2400 | |
c9aa1a2d | 2401 | INIT_LIST_HEAD(&xhci->cmd_list); |
331de00a | 2402 | |
cb4d5ce5 OH |
2403 | /* init command timeout work */ |
2404 | INIT_DELAYED_WORK(&xhci->cmd_timer, xhci_handle_command_timeout); | |
1c111b6c | 2405 | init_completion(&xhci->cmd_ring_stop_completion); |
cc8e4fc0 | 2406 | |
b0ba9720 | 2407 | page_size = readl(&xhci->op_regs->page_size); |
d195fcff XR |
2408 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2409 | "Supported page size register = 0x%x", page_size); | |
66d4eadd SS |
2410 | for (i = 0; i < 16; i++) { |
2411 | if ((0x1 & page_size) != 0) | |
2412 | break; | |
2413 | page_size = page_size >> 1; | |
2414 | } | |
2415 | if (i < 16) | |
d195fcff XR |
2416 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2417 | "Supported page size of %iK", (1 << (i+12)) / 1024); | |
66d4eadd SS |
2418 | else |
2419 | xhci_warn(xhci, "WARN: no supported page size\n"); | |
2420 | /* Use 4K pages, since that's common and the minimum the HC supports */ | |
2421 | xhci->page_shift = 12; | |
2422 | xhci->page_size = 1 << xhci->page_shift; | |
d195fcff XR |
2423 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2424 | "HCD page size set to %iK", xhci->page_size / 1024); | |
66d4eadd SS |
2425 | |
2426 | /* | |
2427 | * Program the Number of Device Slots Enabled field in the CONFIG | |
2428 | * register with the max value of slots the HC can handle. | |
2429 | */ | |
b0ba9720 | 2430 | val = HCS_MAX_SLOTS(readl(&xhci->cap_regs->hcs_params1)); |
d195fcff XR |
2431 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2432 | "// xHC can handle at most %d device slots.", val); | |
b0ba9720 | 2433 | val2 = readl(&xhci->op_regs->config_reg); |
66d4eadd | 2434 | val |= (val2 & ~HCS_SLOTS_MASK); |
d195fcff XR |
2435 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2436 | "// Setting Max device slots reg = 0x%x.", val); | |
204b7793 | 2437 | writel(val, &xhci->op_regs->config_reg); |
66d4eadd | 2438 | |
a74588f9 | 2439 | /* |
724e882d | 2440 | * xHCI section 5.4.6 - doorbell array must be |
a74588f9 SS |
2441 | * "physically contiguous and 64-byte (cache line) aligned". |
2442 | */ | |
22d45f01 | 2443 | xhci->dcbaa = dma_alloc_coherent(dev, sizeof(*xhci->dcbaa), &dma, |
c95a9f83 | 2444 | flags); |
a74588f9 SS |
2445 | if (!xhci->dcbaa) |
2446 | goto fail; | |
a74588f9 | 2447 | xhci->dcbaa->dma = dma; |
d195fcff XR |
2448 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2449 | "// Device context base array address = 0x%llx (DMA), %p (virt)", | |
700e2052 | 2450 | (unsigned long long)xhci->dcbaa->dma, xhci->dcbaa); |
477632df | 2451 | xhci_write_64(xhci, dma, &xhci->op_regs->dcbaa_ptr); |
a74588f9 | 2452 | |
0ebbab37 SS |
2453 | /* |
2454 | * Initialize the ring segment pool. The ring must be a contiguous | |
2455 | * structure comprised of TRBs. The TRBs must be 16 byte aligned, | |
84c1e40f HG |
2456 | * however, the command ring segment needs 64-byte aligned segments |
2457 | * and our use of dma addresses in the trb_address_map radix tree needs | |
2458 | * TRB_SEGMENT_SIZE alignment, so we pick the greater alignment need. | |
0ebbab37 SS |
2459 | */ |
2460 | xhci->segment_pool = dma_pool_create("xHCI ring segments", dev, | |
84c1e40f | 2461 | TRB_SEGMENT_SIZE, TRB_SEGMENT_SIZE, xhci->page_size); |
d115b048 | 2462 | |
3ffbba95 | 2463 | /* See Table 46 and Note on Figure 55 */ |
3ffbba95 | 2464 | xhci->device_pool = dma_pool_create("xHCI input/output contexts", dev, |
d115b048 | 2465 | 2112, 64, xhci->page_size); |
3ffbba95 | 2466 | if (!xhci->segment_pool || !xhci->device_pool) |
0ebbab37 SS |
2467 | goto fail; |
2468 | ||
8df75f42 SS |
2469 | /* Linear stream context arrays don't have any boundary restrictions, |
2470 | * and only need to be 16-byte aligned. | |
2471 | */ | |
2472 | xhci->small_streams_pool = | |
2473 | dma_pool_create("xHCI 256 byte stream ctx arrays", | |
2474 | dev, SMALL_STREAM_ARRAY_SIZE, 16, 0); | |
2475 | xhci->medium_streams_pool = | |
2476 | dma_pool_create("xHCI 1KB stream ctx arrays", | |
2477 | dev, MEDIUM_STREAM_ARRAY_SIZE, 16, 0); | |
2478 | /* Any stream context array bigger than MEDIUM_STREAM_ARRAY_SIZE | |
22d45f01 | 2479 | * will be allocated with dma_alloc_coherent() |
8df75f42 SS |
2480 | */ |
2481 | ||
2482 | if (!xhci->small_streams_pool || !xhci->medium_streams_pool) | |
2483 | goto fail; | |
2484 | ||
0ebbab37 | 2485 | /* Set up the command ring to have one segments for now. */ |
f9c589e1 | 2486 | xhci->cmd_ring = xhci_ring_alloc(xhci, 1, 1, TYPE_COMMAND, 0, flags); |
0ebbab37 SS |
2487 | if (!xhci->cmd_ring) |
2488 | goto fail; | |
d195fcff XR |
2489 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2490 | "Allocated command ring at %p", xhci->cmd_ring); | |
2491 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "First segment DMA is 0x%llx", | |
700e2052 | 2492 | (unsigned long long)xhci->cmd_ring->first_seg->dma); |
0ebbab37 SS |
2493 | |
2494 | /* Set the address in the Command Ring Control register */ | |
f7b2e403 | 2495 | val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring); |
8e595a5d SS |
2496 | val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) | |
2497 | (xhci->cmd_ring->first_seg->dma & (u64) ~CMD_RING_RSVD_BITS) | | |
0ebbab37 | 2498 | xhci->cmd_ring->cycle_state; |
d195fcff | 2499 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
6fc091fb | 2500 | "// Setting command ring address to 0x%016llx", val_64); |
477632df | 2501 | xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring); |
0ebbab37 | 2502 | |
14d49b7a | 2503 | xhci->lpm_command = xhci_alloc_command_with_ctx(xhci, true, flags); |
dbc33303 SS |
2504 | if (!xhci->lpm_command) |
2505 | goto fail; | |
2506 | ||
2507 | /* Reserve one command ring TRB for disabling LPM. | |
2508 | * Since the USB core grabs the shared usb_bus bandwidth mutex before | |
2509 | * disabling LPM, we only need to reserve one TRB for all devices. | |
2510 | */ | |
2511 | xhci->cmd_ring_reserved_trbs++; | |
2512 | ||
b0ba9720 | 2513 | val = readl(&xhci->cap_regs->db_off); |
0ebbab37 | 2514 | val &= DBOFF_MASK; |
d195fcff XR |
2515 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2516 | "// Doorbell array is located at offset 0x%x" | |
2517 | " from cap regs base addr", val); | |
c50a00f8 | 2518 | xhci->dba = (void __iomem *) xhci->cap_regs + val; |
0ebbab37 | 2519 | /* Set ir_set to interrupt register set 0 */ |
c50a00f8 | 2520 | xhci->ir_set = &xhci->run_regs->ir_set[0]; |
0ebbab37 SS |
2521 | |
2522 | /* | |
2523 | * Event ring setup: Allocate a normal ring, but also setup | |
2524 | * the event ring segment table (ERST). Section 4.9.3. | |
2525 | */ | |
d195fcff | 2526 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Allocating event ring"); |
186a7ef1 | 2527 | xhci->event_ring = xhci_ring_alloc(xhci, ERST_NUM_SEGS, 1, TYPE_EVENT, |
f9c589e1 | 2528 | 0, flags); |
0ebbab37 SS |
2529 | if (!xhci->event_ring) |
2530 | goto fail; | |
4daf9df5 | 2531 | if (xhci_check_trb_in_td_math(xhci) < 0) |
6648f29d | 2532 | goto fail; |
0ebbab37 | 2533 | |
67d2ea9f LB |
2534 | ret = xhci_alloc_erst(xhci, xhci->event_ring, &xhci->erst, flags); |
2535 | if (ret) | |
0ebbab37 | 2536 | goto fail; |
0ebbab37 SS |
2537 | |
2538 | /* set ERST count with the number of entries in the segment table */ | |
b0ba9720 | 2539 | val = readl(&xhci->ir_set->erst_size); |
0ebbab37 SS |
2540 | val &= ERST_SIZE_MASK; |
2541 | val |= ERST_NUM_SEGS; | |
d195fcff XR |
2542 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2543 | "// Write ERST size = %i to ir_set 0 (some bits preserved)", | |
0ebbab37 | 2544 | val); |
204b7793 | 2545 | writel(val, &xhci->ir_set->erst_size); |
0ebbab37 | 2546 | |
d195fcff XR |
2547 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2548 | "// Set ERST entries to point to event ring."); | |
0ebbab37 | 2549 | /* set the segment table base address */ |
d195fcff XR |
2550 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2551 | "// Set ERST base address for ir_set 0 = 0x%llx", | |
700e2052 | 2552 | (unsigned long long)xhci->erst.erst_dma_addr); |
f7b2e403 | 2553 | val_64 = xhci_read_64(xhci, &xhci->ir_set->erst_base); |
8e595a5d SS |
2554 | val_64 &= ERST_PTR_MASK; |
2555 | val_64 |= (xhci->erst.erst_dma_addr & (u64) ~ERST_PTR_MASK); | |
477632df | 2556 | xhci_write_64(xhci, val_64, &xhci->ir_set->erst_base); |
0ebbab37 SS |
2557 | |
2558 | /* Set the event ring dequeue address */ | |
23e3be11 | 2559 | xhci_set_hc_event_deq(xhci); |
d195fcff XR |
2560 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2561 | "Wrote ERST address to ir_set 0."); | |
0ebbab37 SS |
2562 | |
2563 | /* | |
2564 | * XXX: Might need to set the Interrupter Moderation Register to | |
2565 | * something other than the default (~1ms minimum between interrupts). | |
2566 | * See section 5.5.1.2. | |
2567 | */ | |
98871e94 | 2568 | for (i = 0; i < MAX_HC_SLOTS; i++) |
326b4810 | 2569 | xhci->devs[i] = NULL; |
98871e94 | 2570 | for (i = 0; i < USB_MAXCHILDREN; i++) { |
f6187f42 MN |
2571 | xhci->usb2_rhub.bus_state.resume_done[i] = 0; |
2572 | xhci->usb3_rhub.bus_state.resume_done[i] = 0; | |
8b3d4570 | 2573 | /* Only the USB 2.0 completions will ever be used. */ |
f6187f42 | 2574 | init_completion(&xhci->usb2_rhub.bus_state.rexit_done[i]); |
0200b9f7 | 2575 | init_completion(&xhci->usb3_rhub.bus_state.u3exit_done[i]); |
f6ff0ac8 | 2576 | } |
66d4eadd | 2577 | |
254c80a3 JY |
2578 | if (scratchpad_alloc(xhci, flags)) |
2579 | goto fail; | |
da6699ce SS |
2580 | if (xhci_setup_port_arrays(xhci, flags)) |
2581 | goto fail; | |
254c80a3 | 2582 | |
623bef9e SS |
2583 | /* Enable USB 3.0 device notifications for function remote wake, which |
2584 | * is necessary for allowing USB 3.0 devices to do remote wakeup from | |
2585 | * U3 (device suspend). | |
2586 | */ | |
b0ba9720 | 2587 | temp = readl(&xhci->op_regs->dev_notification); |
623bef9e SS |
2588 | temp &= ~DEV_NOTE_MASK; |
2589 | temp |= DEV_NOTE_FWAKE; | |
204b7793 | 2590 | writel(temp, &xhci->op_regs->dev_notification); |
623bef9e | 2591 | |
66d4eadd | 2592 | return 0; |
254c80a3 | 2593 | |
66d4eadd | 2594 | fail: |
159e1fcc SS |
2595 | xhci_halt(xhci); |
2596 | xhci_reset(xhci); | |
66d4eadd SS |
2597 | xhci_mem_cleanup(xhci); |
2598 | return -ENOMEM; | |
2599 | } |