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0cbd4b34 CY |
1 | /* |
2 | * MediaTek xHCI Host Controller Driver | |
3 | * | |
4 | * Copyright (c) 2015 MediaTek Inc. | |
5 | * Author: | |
6 | * Chunfeng Yun <chunfeng.yun@mediatek.com> | |
7 | * | |
8 | * This software is licensed under the terms of the GNU General Public | |
9 | * License version 2, as published by the Free Software Foundation, and | |
10 | * may be copied, distributed, and modified under those terms. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | */ | |
18 | ||
19 | #include <linux/clk.h> | |
20 | #include <linux/dma-mapping.h> | |
21 | #include <linux/iopoll.h> | |
22 | #include <linux/kernel.h> | |
23 | #include <linux/mfd/syscon.h> | |
24 | #include <linux/module.h> | |
25 | #include <linux/of.h> | |
26 | #include <linux/phy/phy.h> | |
27 | #include <linux/platform_device.h> | |
28 | #include <linux/pm_runtime.h> | |
29 | #include <linux/regmap.h> | |
30 | #include <linux/regulator/consumer.h> | |
31 | ||
32 | #include "xhci.h" | |
33 | #include "xhci-mtk.h" | |
34 | ||
35 | /* ip_pw_ctrl0 register */ | |
36 | #define CTRL0_IP_SW_RST BIT(0) | |
37 | ||
38 | /* ip_pw_ctrl1 register */ | |
39 | #define CTRL1_IP_HOST_PDN BIT(0) | |
40 | ||
41 | /* ip_pw_ctrl2 register */ | |
42 | #define CTRL2_IP_DEV_PDN BIT(0) | |
43 | ||
44 | /* ip_pw_sts1 register */ | |
45 | #define STS1_IP_SLEEP_STS BIT(30) | |
46 | #define STS1_XHCI_RST BIT(11) | |
47 | #define STS1_SYS125_RST BIT(10) | |
48 | #define STS1_REF_RST BIT(8) | |
49 | #define STS1_SYSPLL_STABLE BIT(0) | |
50 | ||
51 | /* ip_xhci_cap register */ | |
52 | #define CAP_U3_PORT_NUM(p) ((p) & 0xff) | |
53 | #define CAP_U2_PORT_NUM(p) (((p) >> 8) & 0xff) | |
54 | ||
55 | /* u3_ctrl_p register */ | |
56 | #define CTRL_U3_PORT_HOST_SEL BIT(2) | |
57 | #define CTRL_U3_PORT_PDN BIT(1) | |
58 | #define CTRL_U3_PORT_DIS BIT(0) | |
59 | ||
60 | /* u2_ctrl_p register */ | |
61 | #define CTRL_U2_PORT_HOST_SEL BIT(2) | |
62 | #define CTRL_U2_PORT_PDN BIT(1) | |
63 | #define CTRL_U2_PORT_DIS BIT(0) | |
64 | ||
65 | /* u2_phy_pll register */ | |
66 | #define CTRL_U2_FORCE_PLL_STB BIT(28) | |
67 | ||
68 | #define PERI_WK_CTRL0 0x400 | |
69 | #define UWK_CTR0_0P_LS_PE BIT(8) /* posedge */ | |
70 | #define UWK_CTR0_0P_LS_NE BIT(7) /* negedge for 0p linestate*/ | |
71 | #define UWK_CTL1_1P_LS_C(x) (((x) & 0xf) << 1) | |
72 | #define UWK_CTL1_1P_LS_E BIT(0) | |
73 | ||
74 | #define PERI_WK_CTRL1 0x404 | |
75 | #define UWK_CTL1_IS_C(x) (((x) & 0xf) << 26) | |
76 | #define UWK_CTL1_IS_E BIT(25) | |
77 | #define UWK_CTL1_0P_LS_C(x) (((x) & 0xf) << 21) | |
78 | #define UWK_CTL1_0P_LS_E BIT(20) | |
79 | #define UWK_CTL1_IDDIG_C(x) (((x) & 0xf) << 11) /* cycle debounce */ | |
80 | #define UWK_CTL1_IDDIG_E BIT(10) /* enable debounce */ | |
81 | #define UWK_CTL1_IDDIG_P BIT(9) /* polarity */ | |
82 | #define UWK_CTL1_0P_LS_P BIT(7) | |
83 | #define UWK_CTL1_IS_P BIT(6) /* polarity for ip sleep */ | |
84 | ||
85 | enum ssusb_wakeup_src { | |
86 | SSUSB_WK_IP_SLEEP = 1, | |
87 | SSUSB_WK_LINE_STATE = 2, | |
88 | }; | |
89 | ||
90 | static int xhci_mtk_host_enable(struct xhci_hcd_mtk *mtk) | |
91 | { | |
92 | struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs; | |
93 | u32 value, check_val; | |
94 | int ret; | |
95 | int i; | |
96 | ||
065d48cf CY |
97 | if (!mtk->has_ippc) |
98 | return 0; | |
99 | ||
0cbd4b34 CY |
100 | /* power on host ip */ |
101 | value = readl(&ippc->ip_pw_ctr1); | |
102 | value &= ~CTRL1_IP_HOST_PDN; | |
103 | writel(value, &ippc->ip_pw_ctr1); | |
104 | ||
105 | /* power on and enable all u3 ports */ | |
106 | for (i = 0; i < mtk->num_u3_ports; i++) { | |
107 | value = readl(&ippc->u3_ctrl_p[i]); | |
108 | value &= ~(CTRL_U3_PORT_PDN | CTRL_U3_PORT_DIS); | |
109 | value |= CTRL_U3_PORT_HOST_SEL; | |
110 | writel(value, &ippc->u3_ctrl_p[i]); | |
111 | } | |
112 | ||
113 | /* power on and enable all u2 ports */ | |
114 | for (i = 0; i < mtk->num_u2_ports; i++) { | |
115 | value = readl(&ippc->u2_ctrl_p[i]); | |
116 | value &= ~(CTRL_U2_PORT_PDN | CTRL_U2_PORT_DIS); | |
117 | value |= CTRL_U2_PORT_HOST_SEL; | |
118 | writel(value, &ippc->u2_ctrl_p[i]); | |
119 | } | |
120 | ||
121 | /* | |
122 | * wait for clocks to be stable, and clock domains reset to | |
123 | * be inactive after power on and enable ports | |
124 | */ | |
125 | check_val = STS1_SYSPLL_STABLE | STS1_REF_RST | | |
126 | STS1_SYS125_RST | STS1_XHCI_RST; | |
127 | ||
128 | ret = readl_poll_timeout(&ippc->ip_pw_sts1, value, | |
129 | (check_val == (value & check_val)), 100, 20000); | |
130 | if (ret) { | |
131 | dev_err(mtk->dev, "clocks are not stable (0x%x)\n", value); | |
132 | return ret; | |
133 | } | |
134 | ||
135 | return 0; | |
136 | } | |
137 | ||
138 | static int xhci_mtk_host_disable(struct xhci_hcd_mtk *mtk) | |
139 | { | |
140 | struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs; | |
141 | u32 value; | |
142 | int ret; | |
143 | int i; | |
144 | ||
065d48cf CY |
145 | if (!mtk->has_ippc) |
146 | return 0; | |
147 | ||
0cbd4b34 CY |
148 | /* power down all u3 ports */ |
149 | for (i = 0; i < mtk->num_u3_ports; i++) { | |
150 | value = readl(&ippc->u3_ctrl_p[i]); | |
151 | value |= CTRL_U3_PORT_PDN; | |
152 | writel(value, &ippc->u3_ctrl_p[i]); | |
153 | } | |
154 | ||
155 | /* power down all u2 ports */ | |
156 | for (i = 0; i < mtk->num_u2_ports; i++) { | |
157 | value = readl(&ippc->u2_ctrl_p[i]); | |
158 | value |= CTRL_U2_PORT_PDN; | |
159 | writel(value, &ippc->u2_ctrl_p[i]); | |
160 | } | |
161 | ||
162 | /* power down host ip */ | |
163 | value = readl(&ippc->ip_pw_ctr1); | |
164 | value |= CTRL1_IP_HOST_PDN; | |
165 | writel(value, &ippc->ip_pw_ctr1); | |
166 | ||
167 | /* wait for host ip to sleep */ | |
168 | ret = readl_poll_timeout(&ippc->ip_pw_sts1, value, | |
169 | (value & STS1_IP_SLEEP_STS), 100, 100000); | |
170 | if (ret) { | |
171 | dev_err(mtk->dev, "ip sleep failed!!!\n"); | |
172 | return ret; | |
173 | } | |
174 | return 0; | |
175 | } | |
176 | ||
177 | static int xhci_mtk_ssusb_config(struct xhci_hcd_mtk *mtk) | |
178 | { | |
179 | struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs; | |
180 | u32 value; | |
181 | ||
065d48cf CY |
182 | if (!mtk->has_ippc) |
183 | return 0; | |
184 | ||
0cbd4b34 CY |
185 | /* reset whole ip */ |
186 | value = readl(&ippc->ip_pw_ctr0); | |
187 | value |= CTRL0_IP_SW_RST; | |
188 | writel(value, &ippc->ip_pw_ctr0); | |
189 | udelay(1); | |
190 | value = readl(&ippc->ip_pw_ctr0); | |
191 | value &= ~CTRL0_IP_SW_RST; | |
192 | writel(value, &ippc->ip_pw_ctr0); | |
193 | ||
194 | /* | |
195 | * device ip is default power-on in fact | |
196 | * power down device ip, otherwise ip-sleep will fail | |
197 | */ | |
198 | value = readl(&ippc->ip_pw_ctr2); | |
199 | value |= CTRL2_IP_DEV_PDN; | |
200 | writel(value, &ippc->ip_pw_ctr2); | |
201 | ||
202 | value = readl(&ippc->ip_xhci_cap); | |
203 | mtk->num_u3_ports = CAP_U3_PORT_NUM(value); | |
204 | mtk->num_u2_ports = CAP_U2_PORT_NUM(value); | |
205 | dev_dbg(mtk->dev, "%s u2p:%d, u3p:%d\n", __func__, | |
206 | mtk->num_u2_ports, mtk->num_u3_ports); | |
207 | ||
208 | return xhci_mtk_host_enable(mtk); | |
209 | } | |
210 | ||
211 | static int xhci_mtk_clks_enable(struct xhci_hcd_mtk *mtk) | |
212 | { | |
213 | int ret; | |
214 | ||
9c4afd42 CY |
215 | ret = clk_prepare_enable(mtk->ref_clk); |
216 | if (ret) { | |
217 | dev_err(mtk->dev, "failed to enable ref_clk\n"); | |
218 | goto ref_clk_err; | |
219 | } | |
220 | ||
0cbd4b34 CY |
221 | ret = clk_prepare_enable(mtk->sys_clk); |
222 | if (ret) { | |
223 | dev_err(mtk->dev, "failed to enable sys_clk\n"); | |
224 | goto sys_clk_err; | |
225 | } | |
226 | ||
227 | if (mtk->wakeup_src) { | |
228 | ret = clk_prepare_enable(mtk->wk_deb_p0); | |
229 | if (ret) { | |
230 | dev_err(mtk->dev, "failed to enable wk_deb_p0\n"); | |
231 | goto usb_p0_err; | |
232 | } | |
233 | ||
234 | ret = clk_prepare_enable(mtk->wk_deb_p1); | |
235 | if (ret) { | |
236 | dev_err(mtk->dev, "failed to enable wk_deb_p1\n"); | |
237 | goto usb_p1_err; | |
238 | } | |
239 | } | |
240 | return 0; | |
241 | ||
242 | usb_p1_err: | |
243 | clk_disable_unprepare(mtk->wk_deb_p0); | |
244 | usb_p0_err: | |
245 | clk_disable_unprepare(mtk->sys_clk); | |
246 | sys_clk_err: | |
9c4afd42 CY |
247 | clk_disable_unprepare(mtk->ref_clk); |
248 | ref_clk_err: | |
0cbd4b34 CY |
249 | return -EINVAL; |
250 | } | |
251 | ||
252 | static void xhci_mtk_clks_disable(struct xhci_hcd_mtk *mtk) | |
253 | { | |
254 | if (mtk->wakeup_src) { | |
255 | clk_disable_unprepare(mtk->wk_deb_p1); | |
256 | clk_disable_unprepare(mtk->wk_deb_p0); | |
257 | } | |
258 | clk_disable_unprepare(mtk->sys_clk); | |
9c4afd42 | 259 | clk_disable_unprepare(mtk->ref_clk); |
0cbd4b34 CY |
260 | } |
261 | ||
262 | /* only clocks can be turn off for ip-sleep wakeup mode */ | |
263 | static void usb_wakeup_ip_sleep_en(struct xhci_hcd_mtk *mtk) | |
264 | { | |
265 | u32 tmp; | |
266 | struct regmap *pericfg = mtk->pericfg; | |
267 | ||
268 | regmap_read(pericfg, PERI_WK_CTRL1, &tmp); | |
269 | tmp &= ~UWK_CTL1_IS_P; | |
270 | tmp &= ~(UWK_CTL1_IS_C(0xf)); | |
271 | tmp |= UWK_CTL1_IS_C(0x8); | |
272 | regmap_write(pericfg, PERI_WK_CTRL1, tmp); | |
273 | regmap_write(pericfg, PERI_WK_CTRL1, tmp | UWK_CTL1_IS_E); | |
274 | ||
275 | regmap_read(pericfg, PERI_WK_CTRL1, &tmp); | |
276 | dev_dbg(mtk->dev, "%s(): WK_CTRL1[P6,E25,C26:29]=%#x\n", | |
277 | __func__, tmp); | |
278 | } | |
279 | ||
280 | static void usb_wakeup_ip_sleep_dis(struct xhci_hcd_mtk *mtk) | |
281 | { | |
282 | u32 tmp; | |
283 | ||
284 | regmap_read(mtk->pericfg, PERI_WK_CTRL1, &tmp); | |
285 | tmp &= ~UWK_CTL1_IS_E; | |
286 | regmap_write(mtk->pericfg, PERI_WK_CTRL1, tmp); | |
287 | } | |
288 | ||
289 | /* | |
290 | * for line-state wakeup mode, phy's power should not power-down | |
291 | * and only support cable plug in/out | |
292 | */ | |
293 | static void usb_wakeup_line_state_en(struct xhci_hcd_mtk *mtk) | |
294 | { | |
295 | u32 tmp; | |
296 | struct regmap *pericfg = mtk->pericfg; | |
297 | ||
298 | /* line-state of u2-port0 */ | |
299 | regmap_read(pericfg, PERI_WK_CTRL1, &tmp); | |
300 | tmp &= ~UWK_CTL1_0P_LS_P; | |
301 | tmp &= ~(UWK_CTL1_0P_LS_C(0xf)); | |
302 | tmp |= UWK_CTL1_0P_LS_C(0x8); | |
303 | regmap_write(pericfg, PERI_WK_CTRL1, tmp); | |
304 | regmap_read(pericfg, PERI_WK_CTRL1, &tmp); | |
305 | regmap_write(pericfg, PERI_WK_CTRL1, tmp | UWK_CTL1_0P_LS_E); | |
306 | ||
307 | /* line-state of u2-port1 */ | |
308 | regmap_read(pericfg, PERI_WK_CTRL0, &tmp); | |
309 | tmp &= ~(UWK_CTL1_1P_LS_C(0xf)); | |
310 | tmp |= UWK_CTL1_1P_LS_C(0x8); | |
311 | regmap_write(pericfg, PERI_WK_CTRL0, tmp); | |
312 | regmap_write(pericfg, PERI_WK_CTRL0, tmp | UWK_CTL1_1P_LS_E); | |
313 | } | |
314 | ||
315 | static void usb_wakeup_line_state_dis(struct xhci_hcd_mtk *mtk) | |
316 | { | |
317 | u32 tmp; | |
318 | struct regmap *pericfg = mtk->pericfg; | |
319 | ||
320 | /* line-state of u2-port0 */ | |
321 | regmap_read(pericfg, PERI_WK_CTRL1, &tmp); | |
322 | tmp &= ~UWK_CTL1_0P_LS_E; | |
323 | regmap_write(pericfg, PERI_WK_CTRL1, tmp); | |
324 | ||
325 | /* line-state of u2-port1 */ | |
326 | regmap_read(pericfg, PERI_WK_CTRL0, &tmp); | |
327 | tmp &= ~UWK_CTL1_1P_LS_E; | |
328 | regmap_write(pericfg, PERI_WK_CTRL0, tmp); | |
329 | } | |
330 | ||
331 | static void usb_wakeup_enable(struct xhci_hcd_mtk *mtk) | |
332 | { | |
333 | if (mtk->wakeup_src == SSUSB_WK_IP_SLEEP) | |
334 | usb_wakeup_ip_sleep_en(mtk); | |
335 | else if (mtk->wakeup_src == SSUSB_WK_LINE_STATE) | |
336 | usb_wakeup_line_state_en(mtk); | |
337 | } | |
338 | ||
339 | static void usb_wakeup_disable(struct xhci_hcd_mtk *mtk) | |
340 | { | |
341 | if (mtk->wakeup_src == SSUSB_WK_IP_SLEEP) | |
342 | usb_wakeup_ip_sleep_dis(mtk); | |
343 | else if (mtk->wakeup_src == SSUSB_WK_LINE_STATE) | |
344 | usb_wakeup_line_state_dis(mtk); | |
345 | } | |
346 | ||
347 | static int usb_wakeup_of_property_parse(struct xhci_hcd_mtk *mtk, | |
348 | struct device_node *dn) | |
349 | { | |
350 | struct device *dev = mtk->dev; | |
351 | ||
352 | /* | |
353 | * wakeup function is optional, so it is not an error if this property | |
354 | * does not exist, and in such case, no need to get relative | |
355 | * properties anymore. | |
356 | */ | |
357 | of_property_read_u32(dn, "mediatek,wakeup-src", &mtk->wakeup_src); | |
358 | if (!mtk->wakeup_src) | |
359 | return 0; | |
360 | ||
361 | mtk->wk_deb_p0 = devm_clk_get(dev, "wakeup_deb_p0"); | |
362 | if (IS_ERR(mtk->wk_deb_p0)) { | |
363 | dev_err(dev, "fail to get wakeup_deb_p0\n"); | |
364 | return PTR_ERR(mtk->wk_deb_p0); | |
365 | } | |
366 | ||
367 | mtk->wk_deb_p1 = devm_clk_get(dev, "wakeup_deb_p1"); | |
368 | if (IS_ERR(mtk->wk_deb_p1)) { | |
369 | dev_err(dev, "fail to get wakeup_deb_p1\n"); | |
370 | return PTR_ERR(mtk->wk_deb_p1); | |
371 | } | |
372 | ||
373 | mtk->pericfg = syscon_regmap_lookup_by_phandle(dn, | |
374 | "mediatek,syscon-wakeup"); | |
375 | if (IS_ERR(mtk->pericfg)) { | |
376 | dev_err(dev, "fail to get pericfg regs\n"); | |
377 | return PTR_ERR(mtk->pericfg); | |
378 | } | |
379 | ||
380 | return 0; | |
381 | } | |
382 | ||
383 | static int xhci_mtk_setup(struct usb_hcd *hcd); | |
384 | static const struct xhci_driver_overrides xhci_mtk_overrides __initconst = { | |
0cbd4b34 CY |
385 | .reset = xhci_mtk_setup, |
386 | }; | |
387 | ||
388 | static struct hc_driver __read_mostly xhci_mtk_hc_driver; | |
389 | ||
390 | static int xhci_mtk_phy_init(struct xhci_hcd_mtk *mtk) | |
391 | { | |
392 | int i; | |
393 | int ret; | |
394 | ||
395 | for (i = 0; i < mtk->num_phys; i++) { | |
396 | ret = phy_init(mtk->phys[i]); | |
397 | if (ret) | |
398 | goto exit_phy; | |
399 | } | |
400 | return 0; | |
401 | ||
402 | exit_phy: | |
403 | for (; i > 0; i--) | |
404 | phy_exit(mtk->phys[i - 1]); | |
405 | ||
406 | return ret; | |
407 | } | |
408 | ||
409 | static int xhci_mtk_phy_exit(struct xhci_hcd_mtk *mtk) | |
410 | { | |
411 | int i; | |
412 | ||
413 | for (i = 0; i < mtk->num_phys; i++) | |
414 | phy_exit(mtk->phys[i]); | |
415 | ||
416 | return 0; | |
417 | } | |
418 | ||
419 | static int xhci_mtk_phy_power_on(struct xhci_hcd_mtk *mtk) | |
420 | { | |
421 | int i; | |
422 | int ret; | |
423 | ||
424 | for (i = 0; i < mtk->num_phys; i++) { | |
425 | ret = phy_power_on(mtk->phys[i]); | |
426 | if (ret) | |
427 | goto power_off_phy; | |
428 | } | |
429 | return 0; | |
430 | ||
431 | power_off_phy: | |
432 | for (; i > 0; i--) | |
433 | phy_power_off(mtk->phys[i - 1]); | |
434 | ||
435 | return ret; | |
436 | } | |
437 | ||
438 | static void xhci_mtk_phy_power_off(struct xhci_hcd_mtk *mtk) | |
439 | { | |
440 | unsigned int i; | |
441 | ||
442 | for (i = 0; i < mtk->num_phys; i++) | |
443 | phy_power_off(mtk->phys[i]); | |
444 | } | |
445 | ||
446 | static int xhci_mtk_ldos_enable(struct xhci_hcd_mtk *mtk) | |
447 | { | |
448 | int ret; | |
449 | ||
450 | ret = regulator_enable(mtk->vbus); | |
451 | if (ret) { | |
452 | dev_err(mtk->dev, "failed to enable vbus\n"); | |
453 | return ret; | |
454 | } | |
455 | ||
456 | ret = regulator_enable(mtk->vusb33); | |
457 | if (ret) { | |
458 | dev_err(mtk->dev, "failed to enable vusb33\n"); | |
459 | regulator_disable(mtk->vbus); | |
460 | return ret; | |
461 | } | |
462 | return 0; | |
463 | } | |
464 | ||
465 | static void xhci_mtk_ldos_disable(struct xhci_hcd_mtk *mtk) | |
466 | { | |
467 | regulator_disable(mtk->vbus); | |
468 | regulator_disable(mtk->vusb33); | |
469 | } | |
470 | ||
471 | static void xhci_mtk_quirks(struct device *dev, struct xhci_hcd *xhci) | |
472 | { | |
473 | struct usb_hcd *hcd = xhci_to_hcd(xhci); | |
474 | struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd); | |
475 | ||
476 | /* | |
477 | * As of now platform drivers don't provide MSI support so we ensure | |
478 | * here that the generic code does not try to make a pci_dev from our | |
479 | * dev struct in order to setup MSI | |
480 | */ | |
481 | xhci->quirks |= XHCI_PLAT; | |
482 | xhci->quirks |= XHCI_MTK_HOST; | |
483 | /* | |
484 | * MTK host controller gives a spurious successful event after a | |
485 | * short transfer. Ignore it. | |
486 | */ | |
487 | xhci->quirks |= XHCI_SPURIOUS_SUCCESS; | |
488 | if (mtk->lpm_support) | |
489 | xhci->quirks |= XHCI_LPM_SUPPORT; | |
490 | } | |
491 | ||
492 | /* called during probe() after chip reset completes */ | |
493 | static int xhci_mtk_setup(struct usb_hcd *hcd) | |
494 | { | |
065d48cf | 495 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); |
0cbd4b34 CY |
496 | struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd); |
497 | int ret; | |
498 | ||
499 | if (usb_hcd_is_primary_hcd(hcd)) { | |
500 | ret = xhci_mtk_ssusb_config(mtk); | |
501 | if (ret) | |
502 | return ret; | |
065d48cf CY |
503 | } |
504 | ||
505 | ret = xhci_gen_setup(hcd, xhci_mtk_quirks); | |
506 | if (ret) | |
507 | return ret; | |
508 | ||
509 | if (usb_hcd_is_primary_hcd(hcd)) { | |
510 | mtk->num_u3_ports = xhci->num_usb3_ports; | |
511 | mtk->num_u2_ports = xhci->num_usb2_ports; | |
0cbd4b34 CY |
512 | ret = xhci_mtk_sch_init(mtk); |
513 | if (ret) | |
514 | return ret; | |
515 | } | |
516 | ||
065d48cf | 517 | return ret; |
0cbd4b34 CY |
518 | } |
519 | ||
520 | static int xhci_mtk_probe(struct platform_device *pdev) | |
521 | { | |
522 | struct device *dev = &pdev->dev; | |
523 | struct device_node *node = dev->of_node; | |
524 | struct xhci_hcd_mtk *mtk; | |
525 | const struct hc_driver *driver; | |
526 | struct xhci_hcd *xhci; | |
527 | struct resource *res; | |
528 | struct usb_hcd *hcd; | |
529 | struct phy *phy; | |
530 | int phy_num; | |
531 | int ret = -ENODEV; | |
532 | int irq; | |
533 | ||
534 | if (usb_disabled()) | |
535 | return -ENODEV; | |
536 | ||
537 | driver = &xhci_mtk_hc_driver; | |
538 | mtk = devm_kzalloc(dev, sizeof(*mtk), GFP_KERNEL); | |
539 | if (!mtk) | |
540 | return -ENOMEM; | |
541 | ||
542 | mtk->dev = dev; | |
543 | mtk->vbus = devm_regulator_get(dev, "vbus"); | |
544 | if (IS_ERR(mtk->vbus)) { | |
545 | dev_err(dev, "fail to get vbus\n"); | |
546 | return PTR_ERR(mtk->vbus); | |
547 | } | |
548 | ||
549 | mtk->vusb33 = devm_regulator_get(dev, "vusb33"); | |
550 | if (IS_ERR(mtk->vusb33)) { | |
551 | dev_err(dev, "fail to get vusb33\n"); | |
552 | return PTR_ERR(mtk->vusb33); | |
553 | } | |
554 | ||
555 | mtk->sys_clk = devm_clk_get(dev, "sys_ck"); | |
556 | if (IS_ERR(mtk->sys_clk)) { | |
557 | dev_err(dev, "fail to get sys_ck\n"); | |
558 | return PTR_ERR(mtk->sys_clk); | |
559 | } | |
560 | ||
f3c4c737 CY |
561 | /* |
562 | * reference clock is usually a "fixed-clock", make it optional | |
563 | * for backward compatibility and ignore the error if it does | |
564 | * not exist. | |
565 | */ | |
9c4afd42 CY |
566 | mtk->ref_clk = devm_clk_get(dev, "ref_ck"); |
567 | if (IS_ERR(mtk->ref_clk)) { | |
f3c4c737 CY |
568 | if (PTR_ERR(mtk->ref_clk) == -EPROBE_DEFER) |
569 | return -EPROBE_DEFER; | |
570 | ||
571 | mtk->ref_clk = NULL; | |
9c4afd42 CY |
572 | } |
573 | ||
0cbd4b34 CY |
574 | mtk->lpm_support = of_property_read_bool(node, "usb3-lpm-capable"); |
575 | ||
576 | ret = usb_wakeup_of_property_parse(mtk, node); | |
577 | if (ret) | |
578 | return ret; | |
579 | ||
580 | mtk->num_phys = of_count_phandle_with_args(node, | |
581 | "phys", "#phy-cells"); | |
582 | if (mtk->num_phys > 0) { | |
583 | mtk->phys = devm_kcalloc(dev, mtk->num_phys, | |
584 | sizeof(*mtk->phys), GFP_KERNEL); | |
585 | if (!mtk->phys) | |
586 | return -ENOMEM; | |
587 | } else { | |
588 | mtk->num_phys = 0; | |
589 | } | |
590 | pm_runtime_enable(dev); | |
591 | pm_runtime_get_sync(dev); | |
592 | device_enable_async_suspend(dev); | |
593 | ||
594 | ret = xhci_mtk_ldos_enable(mtk); | |
595 | if (ret) | |
596 | goto disable_pm; | |
597 | ||
598 | ret = xhci_mtk_clks_enable(mtk); | |
599 | if (ret) | |
600 | goto disable_ldos; | |
601 | ||
602 | irq = platform_get_irq(pdev, 0); | |
28bedb5a PB |
603 | if (irq < 0) { |
604 | ret = irq; | |
0cbd4b34 | 605 | goto disable_clk; |
28bedb5a | 606 | } |
0cbd4b34 CY |
607 | |
608 | /* Initialize dma_mask and coherent_dma_mask to 32-bits */ | |
609 | ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32)); | |
610 | if (ret) | |
611 | goto disable_clk; | |
612 | ||
613 | if (!dev->dma_mask) | |
614 | dev->dma_mask = &dev->coherent_dma_mask; | |
615 | else | |
616 | dma_set_mask(dev, DMA_BIT_MASK(32)); | |
617 | ||
618 | hcd = usb_create_hcd(driver, dev, dev_name(dev)); | |
619 | if (!hcd) { | |
620 | ret = -ENOMEM; | |
621 | goto disable_clk; | |
622 | } | |
623 | ||
624 | /* | |
625 | * USB 2.0 roothub is stored in the platform_device. | |
626 | * Swap it with mtk HCD. | |
627 | */ | |
628 | mtk->hcd = platform_get_drvdata(pdev); | |
629 | platform_set_drvdata(pdev, mtk); | |
630 | ||
065d48cf | 631 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac"); |
0cbd4b34 CY |
632 | hcd->regs = devm_ioremap_resource(dev, res); |
633 | if (IS_ERR(hcd->regs)) { | |
634 | ret = PTR_ERR(hcd->regs); | |
635 | goto put_usb2_hcd; | |
636 | } | |
637 | hcd->rsrc_start = res->start; | |
638 | hcd->rsrc_len = resource_size(res); | |
639 | ||
065d48cf CY |
640 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ippc"); |
641 | if (res) { /* ippc register is optional */ | |
642 | mtk->ippc_regs = devm_ioremap_resource(dev, res); | |
643 | if (IS_ERR(mtk->ippc_regs)) { | |
644 | ret = PTR_ERR(mtk->ippc_regs); | |
645 | goto put_usb2_hcd; | |
646 | } | |
647 | mtk->has_ippc = true; | |
648 | } else { | |
649 | mtk->has_ippc = false; | |
0cbd4b34 CY |
650 | } |
651 | ||
652 | for (phy_num = 0; phy_num < mtk->num_phys; phy_num++) { | |
653 | phy = devm_of_phy_get_by_index(dev, node, phy_num); | |
654 | if (IS_ERR(phy)) { | |
655 | ret = PTR_ERR(phy); | |
656 | goto put_usb2_hcd; | |
657 | } | |
658 | mtk->phys[phy_num] = phy; | |
659 | } | |
660 | ||
661 | ret = xhci_mtk_phy_init(mtk); | |
662 | if (ret) | |
663 | goto put_usb2_hcd; | |
664 | ||
665 | ret = xhci_mtk_phy_power_on(mtk); | |
666 | if (ret) | |
667 | goto exit_phys; | |
668 | ||
669 | device_init_wakeup(dev, true); | |
670 | ||
671 | xhci = hcd_to_xhci(hcd); | |
672 | xhci->main_hcd = hcd; | |
673 | xhci->shared_hcd = usb_create_shared_hcd(driver, dev, | |
674 | dev_name(dev), hcd); | |
675 | if (!xhci->shared_hcd) { | |
676 | ret = -ENOMEM; | |
677 | goto power_off_phys; | |
678 | } | |
679 | ||
0cbd4b34 CY |
680 | ret = usb_add_hcd(hcd, irq, IRQF_SHARED); |
681 | if (ret) | |
682 | goto put_usb3_hcd; | |
683 | ||
94a631d9 CY |
684 | if (HCC_MAX_PSA(xhci->hcc_params) >= 4) |
685 | xhci->shared_hcd->can_do_streams = 1; | |
686 | ||
0cbd4b34 CY |
687 | ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED); |
688 | if (ret) | |
689 | goto dealloc_usb2_hcd; | |
690 | ||
691 | return 0; | |
692 | ||
693 | dealloc_usb2_hcd: | |
694 | usb_remove_hcd(hcd); | |
695 | ||
696 | put_usb3_hcd: | |
697 | xhci_mtk_sch_exit(mtk); | |
698 | usb_put_hcd(xhci->shared_hcd); | |
699 | ||
700 | power_off_phys: | |
701 | xhci_mtk_phy_power_off(mtk); | |
702 | device_init_wakeup(dev, false); | |
703 | ||
704 | exit_phys: | |
705 | xhci_mtk_phy_exit(mtk); | |
706 | ||
707 | put_usb2_hcd: | |
708 | usb_put_hcd(hcd); | |
709 | ||
710 | disable_clk: | |
711 | xhci_mtk_clks_disable(mtk); | |
712 | ||
713 | disable_ldos: | |
714 | xhci_mtk_ldos_disable(mtk); | |
715 | ||
716 | disable_pm: | |
717 | pm_runtime_put_sync(dev); | |
718 | pm_runtime_disable(dev); | |
719 | return ret; | |
720 | } | |
721 | ||
722 | static int xhci_mtk_remove(struct platform_device *dev) | |
723 | { | |
724 | struct xhci_hcd_mtk *mtk = platform_get_drvdata(dev); | |
725 | struct usb_hcd *hcd = mtk->hcd; | |
726 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
727 | ||
728 | usb_remove_hcd(xhci->shared_hcd); | |
729 | xhci_mtk_phy_power_off(mtk); | |
730 | xhci_mtk_phy_exit(mtk); | |
731 | device_init_wakeup(&dev->dev, false); | |
732 | ||
733 | usb_remove_hcd(hcd); | |
734 | usb_put_hcd(xhci->shared_hcd); | |
735 | usb_put_hcd(hcd); | |
736 | xhci_mtk_sch_exit(mtk); | |
737 | xhci_mtk_clks_disable(mtk); | |
738 | xhci_mtk_ldos_disable(mtk); | |
739 | pm_runtime_put_sync(&dev->dev); | |
740 | pm_runtime_disable(&dev->dev); | |
741 | ||
742 | return 0; | |
743 | } | |
744 | ||
882fa27f CY |
745 | /* |
746 | * if ip sleep fails, and all clocks are disabled, access register will hang | |
747 | * AHB bus, so stop polling roothubs to avoid regs access on bus suspend. | |
748 | * and no need to check whether ip sleep failed or not; this will cause SPM | |
749 | * to wake up system immediately after system suspend complete if ip sleep | |
750 | * fails, it is what we wanted. | |
751 | */ | |
8dac5300 | 752 | static int __maybe_unused xhci_mtk_suspend(struct device *dev) |
0cbd4b34 CY |
753 | { |
754 | struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev); | |
882fa27f CY |
755 | struct usb_hcd *hcd = mtk->hcd; |
756 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
757 | ||
758 | xhci_dbg(xhci, "%s: stop port polling\n", __func__); | |
759 | clear_bit(HCD_FLAG_POLL_RH, &hcd->flags); | |
760 | del_timer_sync(&hcd->rh_timer); | |
761 | clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags); | |
762 | del_timer_sync(&xhci->shared_hcd->rh_timer); | |
0cbd4b34 CY |
763 | |
764 | xhci_mtk_host_disable(mtk); | |
765 | xhci_mtk_phy_power_off(mtk); | |
766 | xhci_mtk_clks_disable(mtk); | |
767 | usb_wakeup_enable(mtk); | |
768 | return 0; | |
769 | } | |
770 | ||
8dac5300 | 771 | static int __maybe_unused xhci_mtk_resume(struct device *dev) |
0cbd4b34 CY |
772 | { |
773 | struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev); | |
882fa27f CY |
774 | struct usb_hcd *hcd = mtk->hcd; |
775 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
0cbd4b34 CY |
776 | |
777 | usb_wakeup_disable(mtk); | |
778 | xhci_mtk_clks_enable(mtk); | |
779 | xhci_mtk_phy_power_on(mtk); | |
780 | xhci_mtk_host_enable(mtk); | |
882fa27f CY |
781 | |
782 | xhci_dbg(xhci, "%s: restart port polling\n", __func__); | |
783 | set_bit(HCD_FLAG_POLL_RH, &hcd->flags); | |
784 | usb_hcd_poll_rh_status(hcd); | |
785 | set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags); | |
786 | usb_hcd_poll_rh_status(xhci->shared_hcd); | |
0cbd4b34 CY |
787 | return 0; |
788 | } | |
789 | ||
790 | static const struct dev_pm_ops xhci_mtk_pm_ops = { | |
791 | SET_SYSTEM_SLEEP_PM_OPS(xhci_mtk_suspend, xhci_mtk_resume) | |
792 | }; | |
8dac5300 | 793 | #define DEV_PM_OPS IS_ENABLED(CONFIG_PM) ? &xhci_mtk_pm_ops : NULL |
0cbd4b34 CY |
794 | |
795 | #ifdef CONFIG_OF | |
796 | static const struct of_device_id mtk_xhci_of_match[] = { | |
797 | { .compatible = "mediatek,mt8173-xhci"}, | |
798 | { }, | |
799 | }; | |
800 | MODULE_DEVICE_TABLE(of, mtk_xhci_of_match); | |
801 | #endif | |
802 | ||
803 | static struct platform_driver mtk_xhci_driver = { | |
804 | .probe = xhci_mtk_probe, | |
805 | .remove = xhci_mtk_remove, | |
806 | .driver = { | |
807 | .name = "xhci-mtk", | |
808 | .pm = DEV_PM_OPS, | |
809 | .of_match_table = of_match_ptr(mtk_xhci_of_match), | |
810 | }, | |
811 | }; | |
812 | MODULE_ALIAS("platform:xhci-mtk"); | |
813 | ||
814 | static int __init xhci_mtk_init(void) | |
815 | { | |
816 | xhci_init_driver(&xhci_mtk_hc_driver, &xhci_mtk_overrides); | |
817 | return platform_driver_register(&mtk_xhci_driver); | |
818 | } | |
819 | module_init(xhci_mtk_init); | |
820 | ||
821 | static void __exit xhci_mtk_exit(void) | |
822 | { | |
823 | platform_driver_unregister(&mtk_xhci_driver); | |
824 | } | |
825 | module_exit(xhci_mtk_exit); | |
826 | ||
827 | MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>"); | |
828 | MODULE_DESCRIPTION("MediaTek xHCI Host Controller Driver"); | |
829 | MODULE_LICENSE("GPL v2"); |