[mirror_ubuntu-bionic-kernel.git] / drivers / usb / host / xhci-pci.c

// SPDX-License-Identifier: GPL-2.0
/*
 * xHCI host controller driver PCI Bus Glue.
 *
 * Copyright (C) 2008 Intel Corp.
 *
 * Author: Sarah Sharp
 * Some code borrowed from the Linux EHCI driver.
 */

#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/acpi.h>

#include "xhci.h"
#include "xhci-trace.h"

#define SSIC_PORT_NUM		2
#define SSIC_PORT_CFG2		0x880c
#define SSIC_PORT_CFG2_OFFSET	0x30
#define PROG_DONE		(1 << 30)
#define SSIC_PORT_UNUSED	(1 << 31)

/* Device for a quirk */
#define PCI_VENDOR_ID_FRESCO_LOGIC	0x1b73
#define PCI_DEVICE_ID_FRESCO_LOGIC_PDK	0x1000
#define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009	0x1009
#define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400	0x1400

#define PCI_VENDOR_ID_ETRON		0x1b6f
#define PCI_DEVICE_ID_EJ168		0x7023

#define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI	0x8c31
#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI	0x9c31
#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI	0x9cb1
#define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI		0x22b5
#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI		0xa12f
#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI	0x9d2f
#define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI		0x0aa8
#define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI		0x1aa8
#define PCI_DEVICE_ID_INTEL_APL_XHCI			0x5aa8
#define PCI_DEVICE_ID_INTEL_DNV_XHCI			0x19d0

#define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI		0x1142

static const char hcd_name[] = "xhci_hcd";

static struct hc_driver __read_mostly xhci_pci_hc_driver;

static int xhci_pci_setup(struct usb_hcd *hcd);

static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
	.reset = xhci_pci_setup,
};

/* called after powerup, by probe or system-pm "wakeup" */
static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
{
	/*
	 * TODO: Implement finding debug ports later.
	 * TODO: see if there are any quirks that need to be added to handle
	 * new extended capabilities.
	 */

	/* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
	if (!pci_set_mwi(pdev))
		xhci_dbg(xhci, "MWI active\n");

	xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
	return 0;
}

static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
{
	struct pci_dev		*pdev = to_pci_dev(dev);

	/* Look for vendor-specific quirks */
	if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
			(pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
			 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
		if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
				pdev->revision == 0x0) {
			xhci->quirks |= XHCI_RESET_EP_QUIRK;
			xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
				"QUIRK: Fresco Logic xHC needs configure"
				" endpoint cmd after reset endpoint");
		}
		if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
				pdev->revision == 0x4) {
			xhci->quirks |= XHCI_SLOW_SUSPEND;
			xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
				"QUIRK: Fresco Logic xHC revision %u"
				"must be suspended extra slowly",
				pdev->revision);
		}
		if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
			xhci->quirks |= XHCI_BROKEN_STREAMS;
		/* Fresco Logic confirms: all revisions of this chip do not
		 * support MSI, even though some of them claim to in their PCI
		 * capabilities.
		 */
		xhci->quirks |= XHCI_BROKEN_MSI;
		xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
				"QUIRK: Fresco Logic revision %u "
				"has broken MSI implementation",
				pdev->revision);
		xhci->quirks |= XHCI_TRUST_TX_LENGTH;
	}

	if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
			pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009)
		xhci->quirks |= XHCI_BROKEN_STREAMS;

	if (pdev->vendor == PCI_VENDOR_ID_NEC)
		xhci->quirks |= XHCI_NEC_HOST;

	if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
		xhci->quirks |= XHCI_AMD_0x96_HOST;

	/* AMD PLL quirk */
	if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
		xhci->quirks |= XHCI_AMD_PLL_FIX;

	if (pdev->vendor == PCI_VENDOR_ID_AMD)
		xhci->quirks |= XHCI_TRUST_TX_LENGTH;

	if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
		xhci->quirks |= XHCI_LPM_SUPPORT;
		xhci->quirks |= XHCI_INTEL_HOST;
		xhci->quirks |= XHCI_AVOID_BEI;
	}
	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
			pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
		xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
		xhci->limit_active_eps = 64;
		xhci->quirks |= XHCI_SW_BW_CHECKING;
		/*
		 * PPT desktop boards DH77EB and DH77DF will power back on after
		 * a few seconds of being shutdown.  The fix for this is to
		 * switch the ports from xHCI to EHCI on shutdown.  We can't use
		 * DMI information to find those particular boards (since each
		 * vendor will change the board name), so we have to key off all
		 * PPT chipsets.
		 */
		xhci->quirks |= XHCI_SPURIOUS_REBOOT;
	}
	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
		(pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI ||
		 pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
		xhci->quirks |= XHCI_SPURIOUS_REBOOT;
		xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
	}
	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
		(pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
		 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
		 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
		 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
		 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI ||
		 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
		 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI)) {
		xhci->quirks |= XHCI_PME_STUCK_QUIRK;
	}
	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
		 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) {
		xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
	}
	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
	    (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
	     pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
	     pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI))
		xhci->quirks |= XHCI_MISSING_CAS;

	if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
			pdev->device == PCI_DEVICE_ID_EJ168) {
		xhci->quirks |= XHCI_RESET_ON_RESUME;
		xhci->quirks |= XHCI_TRUST_TX_LENGTH;
		xhci->quirks |= XHCI_BROKEN_STREAMS;
	}
	if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
			pdev->device == 0x0014)
		xhci->quirks |= XHCI_TRUST_TX_LENGTH;
	if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
			pdev->device == 0x0015)
		xhci->quirks |= XHCI_RESET_ON_RESUME;
	if (pdev->vendor == PCI_VENDOR_ID_VIA)
		xhci->quirks |= XHCI_RESET_ON_RESUME;

	/* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
	if (pdev->vendor == PCI_VENDOR_ID_VIA &&
			pdev->device == 0x3432)
		xhci->quirks |= XHCI_BROKEN_STREAMS;

	if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
			pdev->device == 0x1042)
		xhci->quirks |= XHCI_BROKEN_STREAMS;
	if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
			pdev->device == 0x1142)
		xhci->quirks |= XHCI_TRUST_TX_LENGTH;

	if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
		pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI)
		xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL;

	if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241)
		xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7;

	if (xhci->quirks & XHCI_RESET_ON_RESUME)
		xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
				"QUIRK: Resetting on resume");
}

#ifdef CONFIG_ACPI
static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
{
	static const guid_t intel_dsm_guid =
		GUID_INIT(0xac340cb7, 0xe901, 0x45bf,
			  0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23);
	union acpi_object *obj;

	obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1,
				NULL);
	ACPI_FREE(obj);
}
#else
static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
#endif /* CONFIG_ACPI */

/* called during probe() after chip reset completes */
static int xhci_pci_setup(struct usb_hcd *hcd)
{
	struct xhci_hcd		*xhci;
	struct pci_dev		*pdev = to_pci_dev(hcd->self.controller);
	int			retval;

	xhci = hcd_to_xhci(hcd);
	if (!xhci->sbrn)
		pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);

	retval = xhci_gen_setup(hcd, xhci_pci_quirks);
	if (retval)
		return retval;

	if (!usb_hcd_is_primary_hcd(hcd))
		return 0;

	xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);

	/* Find any debug ports */
	return xhci_pci_reinit(xhci, pdev);
}

/*
 * We need to register our own PCI probe function (instead of the USB core's
 * function) in order to create a second roothub under xHCI.
 */
static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
{
	int retval;
	struct xhci_hcd *xhci;
	struct hc_driver *driver;
	struct usb_hcd *hcd;

	driver = (struct hc_driver *)id->driver_data;

	/* For some HW implementation, a XHCI reset is just not enough... */
	if (usb_xhci_needs_pci_reset(dev)) {
		dev_info(&dev->dev, "Resetting\n");
		if (pci_reset_function_locked(dev))
			dev_warn(&dev->dev, "Reset failed");
	}

	/* Prevent runtime suspending between USB-2 and USB-3 initialization */
	pm_runtime_get_noresume(&dev->dev);

	/* Register the USB 2.0 roothub.
	 * FIXME: USB core must know to register the USB 2.0 roothub first.
	 * This is sort of silly, because we could just set the HCD driver flags
	 * to say USB 2.0, but I'm not sure what the implications would be in
	 * the other parts of the HCD code.
	 */
	retval = usb_hcd_pci_probe(dev, id);

	if (retval)
		goto put_runtime_pm;

	/* USB 2.0 roothub is stored in the PCI device now. */
	hcd = dev_get_drvdata(&dev->dev);
	xhci = hcd_to_xhci(hcd);
	xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
				pci_name(dev), hcd);
	if (!xhci->shared_hcd) {
		retval = -ENOMEM;
		goto dealloc_usb2_hcd;
	}

	retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
			IRQF_SHARED);
	if (retval)
		goto put_usb3_hcd;
	/* Roothub already marked as USB 3.0 speed */

	if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
			HCC_MAX_PSA(xhci->hcc_params) >= 4)
		xhci->shared_hcd->can_do_streams = 1;

	if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
		xhci_pme_acpi_rtd3_enable(dev);

	/* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
	pm_runtime_put_noidle(&dev->dev);

	return 0;

put_usb3_hcd:
	usb_put_hcd(xhci->shared_hcd);
dealloc_usb2_hcd:
	usb_hcd_pci_remove(dev);
put_runtime_pm:
	pm_runtime_put_noidle(&dev->dev);
	return retval;
}

static void xhci_pci_remove(struct pci_dev *dev)
{
	struct xhci_hcd *xhci;

	xhci = hcd_to_xhci(pci_get_drvdata(dev));
	xhci->xhc_state |= XHCI_STATE_REMOVING;
	if (xhci->shared_hcd) {
		usb_remove_hcd(xhci->shared_hcd);
		usb_put_hcd(xhci->shared_hcd);
	}

	/* Workaround for spurious wakeups at shutdown with HSW */
	if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
		pci_set_power_state(dev, PCI_D3hot);

	usb_hcd_pci_remove(dev);
}

#ifdef CONFIG_PM
/*
 * In some Intel xHCI controllers, in order to get D3 working,
 * through a vendor specific SSIC CONFIG register at offset 0x883c,
 * SSIC PORT need to be marked as "unused" before putting xHCI
 * into D3. After D3 exit, the SSIC port need to be marked as "used".
 * Without this change, xHCI might not enter D3 state.
 */
static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
{
	struct xhci_hcd	*xhci = hcd_to_xhci(hcd);
	u32 val;
	void __iomem *reg;
	int i;

	for (i = 0; i < SSIC_PORT_NUM; i++) {
		reg = (void __iomem *) xhci->cap_regs +
				SSIC_PORT_CFG2 +
				i * SSIC_PORT_CFG2_OFFSET;

		/* Notify SSIC that SSIC profile programming is not done. */
		val = readl(reg) & ~PROG_DONE;
		writel(val, reg);

		/* Mark SSIC port as unused(suspend) or used(resume) */
		val = readl(reg);
		if (suspend)
			val |= SSIC_PORT_UNUSED;
		else
			val &= ~SSIC_PORT_UNUSED;
		writel(val, reg);

		/* Notify SSIC that SSIC profile programming is done */
		val = readl(reg) | PROG_DONE;
		writel(val, reg);
		readl(reg);
	}
}

/*
 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
 */
static void xhci_pme_quirk(struct usb_hcd *hcd)
{
	struct xhci_hcd	*xhci = hcd_to_xhci(hcd);
	void __iomem *reg;
	u32 val;

	reg = (void __iomem *) xhci->cap_regs + 0x80a4;
	val = readl(reg);
	writel(val | BIT(28), reg);
	readl(reg);
}

static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
{
	struct xhci_hcd	*xhci = hcd_to_xhci(hcd);
	struct pci_dev		*pdev = to_pci_dev(hcd->self.controller);
	int			ret;

	/*
	 * Systems with the TI redriver that loses port status change events
	 * need to have the registers polled during D3, so avoid D3cold.
	 */
	if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
		pci_d3cold_disable(pdev);

	if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
		xhci_pme_quirk(hcd);

	if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
		xhci_ssic_port_unused_quirk(hcd, true);

	ret = xhci_suspend(xhci, do_wakeup);
	if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
		xhci_ssic_port_unused_quirk(hcd, false);

	return ret;
}

static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
{
	struct xhci_hcd		*xhci = hcd_to_xhci(hcd);
	struct pci_dev		*pdev = to_pci_dev(hcd->self.controller);
	int			retval = 0;

	/* The BIOS on systems with the Intel Panther Point chipset may or may
	 * not support xHCI natively.  That means that during system resume, it
	 * may switch the ports back to EHCI so that users can use their
	 * keyboard to select a kernel from GRUB after resume from hibernate.
	 *
	 * The BIOS is supposed to remember whether the OS had xHCI ports
	 * enabled before resume, and switch the ports back to xHCI when the
	 * BIOS/OS semaphore is written, but we all know we can't trust BIOS
	 * writers.
	 *
	 * Unconditionally switch the ports back to xHCI after a system resume.
	 * It should not matter whether the EHCI or xHCI controller is
	 * resumed first. It's enough to do the switchover in xHCI because
	 * USB core won't notice anything as the hub driver doesn't start
	 * running again until after all the devices (including both EHCI and
	 * xHCI host controllers) have been resumed.
	 */

	if (pdev->vendor == PCI_VENDOR_ID_INTEL)
		usb_enable_intel_xhci_ports(pdev);

	if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
		xhci_ssic_port_unused_quirk(hcd, false);

	if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
		xhci_pme_quirk(hcd);

	retval = xhci_resume(xhci, hibernated);
	return retval;
}
#endif /* CONFIG_PM */

/*-------------------------------------------------------------------------*/

/* PCI driver selection metadata; PCI hotplugging uses this */
static const struct pci_device_id pci_ids[] = { {
	/* handle any USB 3.0 xHCI controller */
	PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
	.driver_data =	(unsigned long) &xhci_pci_hc_driver,
	},
	{ /* end: all zeroes */ }
};
MODULE_DEVICE_TABLE(pci, pci_ids);

/* pci driver glue; this is a "new style" PCI driver module */
static struct pci_driver xhci_pci_driver = {
	.name =		(char *) hcd_name,
	.id_table =	pci_ids,

	.probe =	xhci_pci_probe,
	.remove =	xhci_pci_remove,
	/* suspend and resume implemented later */

	.shutdown = 	usb_hcd_pci_shutdown,
#ifdef CONFIG_PM
	.driver = {
		.pm = &usb_hcd_pci_pm_ops
	},
#endif
};

static int __init xhci_pci_init(void)
{
	xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
#ifdef CONFIG_PM
	xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
	xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
#endif
	return pci_register_driver(&xhci_pci_driver);
}
module_init(xhci_pci_init);

static void __exit xhci_pci_exit(void)
{
	pci_unregister_driver(&xhci_pci_driver);
}
module_exit(xhci_pci_exit);

MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
5fd54ace	1	// SPDX-License-Identifier: GPL-2.0
66d4eadd SS	2	/*
	3	* xHCI host controller driver PCI Bus Glue.
	4	*
	5	* Copyright (C) 2008 Intel Corp.
	6	*
	7	* Author: Sarah Sharp
	8	* Some code borrowed from the Linux EHCI driver.
66d4eadd SS	9	*/
	10
	11	#include <linux/pci.h>
7fc2a616	12	#include <linux/slab.h>
6eb0de82	13	#include <linux/module.h>
c3c5819a	14	#include <linux/acpi.h>
66d4eadd SS	15
66d4eadd SS	16	#include "xhci.h"
4bdfe4c3	17	#include "xhci-trace.h"
66d4eadd	18
fa895377 LB	19	#define SSIC_PORT_NUM 2
	20	#define SSIC_PORT_CFG2 0x880c
	21	#define SSIC_PORT_CFG2_OFFSET 0x30
abce329c RM	22	#define PROG_DONE (1 << 30)
	23	#define SSIC_PORT_UNUSED (1 << 31)
	24
ac9d8fe7 SS	25	/* Device for a quirk */
	26	#define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73
	27	#define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000
d95815ba	28	#define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009
bba18e33	29	#define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400
ac9d8fe7	30
c877b3b2	31	#define PCI_VENDOR_ID_ETRON 0x1b6f
170625e9	32	#define PCI_DEVICE_ID_EJ168 0x7023
c877b3b2	33
638298dc TI	34	#define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31
638298dc TI	35	#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31
4c39135a	36	#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1
b8cb91e0 MN	37	#define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5
	38	#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f
	39	#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f
ccc04afb	40	#define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8
0d46faca	41	#define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8
346e9973	42	#define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8
a0c16630	43	#define PCI_DEVICE_ID_INTEL_DNV_XHCI 0x19d0
638298dc	44
9da5a109 JC	45	#define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142
9da5a109 JC	46
66d4eadd SS	47	static const char hcd_name[] = "xhci_hcd";
66d4eadd SS	48
1885d9a3 AB	49	static struct hc_driver __read_mostly xhci_pci_hc_driver;
1885d9a3 AB	50
cd33a321 RQ	51	static int xhci_pci_setup(struct usb_hcd *hcd);
	52
	53	static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
cd33a321 RQ	54	.reset = xhci_pci_setup,
	55	};
	56
66d4eadd SS	57	/* called after powerup, by probe or system-pm "wakeup" */
	58	static int xhci_pci_reinit(struct xhci_hcd xhci, struct pci_dev pdev)
	59	{
	60	/*
	61	* TODO: Implement finding debug ports later.
	62	* TODO: see if there are any quirks that need to be added to handle
	63	* new extended capabilities.
	64	*/
	65
	66	/* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
	67	if (!pci_set_mwi(pdev))
	68	xhci_dbg(xhci, "MWI active\n");
	69
	70	xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
	71	return 0;
	72	}
	73
da3c9c4f SAS	74	static void xhci_pci_quirks(struct device dev, struct xhci_hcd xhci)
	75	{
	76	struct pci_dev *pdev = to_pci_dev(dev);
	77
ac9d8fe7 SS	78	/* Look for vendor-specific quirks */
ac9d8fe7 SS	79	if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
bba18e33 SS	80	(pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK \|\|
	81	pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
	82	if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
	83	pdev->revision == 0x0) {
ac9d8fe7	84	xhci->quirks \|= XHCI_RESET_EP_QUIRK;
4bdfe4c3 XR	85	xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
	86	"QUIRK: Fresco Logic xHC needs configure"
	87	" endpoint cmd after reset endpoint");
f5182b41	88	}
455f5892 ON	89	if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
	90	pdev->revision == 0x4) {
	91	xhci->quirks \|= XHCI_SLOW_SUSPEND;
	92	xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
	93	"QUIRK: Fresco Logic xHC revision %u"
	94	"must be suspended extra slowly",
	95	pdev->revision);
	96	}
7f5c4d63 HG	97	if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
7f5c4d63 HG	98	xhci->quirks \|= XHCI_BROKEN_STREAMS;
f5182b41 SS	99	/* Fresco Logic confirms: all revisions of this chip do not
	100	* support MSI, even though some of them claim to in their PCI
	101	* capabilities.
	102	*/
	103	xhci->quirks \|= XHCI_BROKEN_MSI;
4bdfe4c3 XR	104	xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
	105	"QUIRK: Fresco Logic revision %u "
	106	"has broken MSI implementation",
f5182b41	107	pdev->revision);
1530bbc6	108	xhci->quirks \|= XHCI_TRUST_TX_LENGTH;
ac9d8fe7	109	}
f5182b41	110
d95815ba HG	111	if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
	112	pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009)
	113	xhci->quirks \|= XHCI_BROKEN_STREAMS;
	114
0238634d SS	115	if (pdev->vendor == PCI_VENDOR_ID_NEC)
0238634d SS	116	xhci->quirks \|= XHCI_NEC_HOST;
ac9d8fe7	117
7e393a83 AX	118	if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
	119	xhci->quirks \|= XHCI_AMD_0x96_HOST;
	120
c41136b0 AX	121	/* AMD PLL quirk */
	122	if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
	123	xhci->quirks \|= XHCI_AMD_PLL_FIX;
2597fe99 HR	124
	125	if (pdev->vendor == PCI_VENDOR_ID_AMD)
	126	xhci->quirks \|= XHCI_TRUST_TX_LENGTH;
	127
e3567d2c SS	128	if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
	129	xhci->quirks \|= XHCI_LPM_SUPPORT;
	130	xhci->quirks \|= XHCI_INTEL_HOST;
227a4fd8	131	xhci->quirks \|= XHCI_AVOID_BEI;
e3567d2c	132	}
ad808333 SS	133	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
ad808333 SS	134	pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
2cf95c18 SS	135	xhci->quirks \|= XHCI_EP_LIMIT_QUIRK;
2cf95c18 SS	136	xhci->limit_active_eps = 64;
86cc558e	137	xhci->quirks \|= XHCI_SW_BW_CHECKING;
e95829f4 SS	138	/*
	139	* PPT desktop boards DH77EB and DH77DF will power back on after
	140	* a few seconds of being shutdown. The fix for this is to
	141	* switch the ports from xHCI to EHCI on shutdown. We can't use
	142	* DMI information to find those particular boards (since each
	143	* vendor will change the board name), so we have to key off all
	144	* PPT chipsets.
	145	*/
	146	xhci->quirks \|= XHCI_SPURIOUS_REBOOT;
ad808333	147	}
0a939993	148	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
4c39135a MN	149	(pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI \|\|
4c39135a MN	150	pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
c09ec25d	151	xhci->quirks \|= XHCI_SPURIOUS_REBOOT;
fd7cd061	152	xhci->quirks \|= XHCI_SPURIOUS_WAKEUP;
638298dc	153	}
b8cb91e0 MN	154	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
	155	(pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI \|\|
	156	pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI \|\|
ccc04afb	157	pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI \|\|
0d46faca	158	pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI \|\|
6c97cfc1	159	pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI \|\|
a0c16630 MN	160	pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI \|\|
a0c16630 MN	161	pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI)) {
b8cb91e0 MN	162	xhci->quirks \|= XHCI_PME_STUCK_QUIRK;
b8cb91e0 MN	163	}
7e70cbff LB	164	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
	165	pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) {
	166	xhci->quirks \|= XHCI_SSIC_PORT_UNUSED;
	167	}
346e9973 MN	168	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
346e9973 MN	169	(pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI \|\|
a0c16630 MN	170	pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI \|\|
a0c16630 MN	171	pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI))
346e9973 MN	172	xhci->quirks \|= XHCI_MISSING_CAS;
346e9973 MN	173
c877b3b2	174	if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
170625e9	175	pdev->device == PCI_DEVICE_ID_EJ168) {
c877b3b2	176	xhci->quirks \|= XHCI_RESET_ON_RESUME;
5cb7df2b	177	xhci->quirks \|= XHCI_TRUST_TX_LENGTH;
8f873c1f	178	xhci->quirks \|= XHCI_BROKEN_STREAMS;
c877b3b2	179	}
da997066 DT	180	if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
	181	pdev->device == 0x0014)
	182	xhci->quirks \|= XHCI_TRUST_TX_LENGTH;
1aa9578c	183	if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
6db249eb	184	pdev->device == 0x0015)
1aa9578c	185	xhci->quirks \|= XHCI_RESET_ON_RESUME;
457a4f61 EF	186	if (pdev->vendor == PCI_VENDOR_ID_VIA)
457a4f61 EF	187	xhci->quirks \|= XHCI_RESET_ON_RESUME;
85f4e45b	188
e21eba05 HG	189	/* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
	190	if (pdev->vendor == PCI_VENDOR_ID_VIA &&
	191	pdev->device == 0x3432)
	192	xhci->quirks \|= XHCI_BROKEN_STREAMS;
	193
2391eacb HG	194	if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
	195	pdev->device == 0x1042)
	196	xhci->quirks \|= XHCI_BROKEN_STREAMS;
d2f48f05 CL	197	if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
	198	pdev->device == 0x1142)
	199	xhci->quirks \|= XHCI_TRUST_TX_LENGTH;
2391eacb	200
9da5a109 JC	201	if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
	202	pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI)
	203	xhci->quirks \|= XHCI_ASMEDIA_MODIFY_FLOWCONTROL;
	204
69307ccb RQ	205	if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241)
	206	xhci->quirks \|= XHCI_LIMIT_ENDPOINT_INTERVAL_7;
	207
85f4e45b ON	208	if (xhci->quirks & XHCI_RESET_ON_RESUME)
	209	xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
	210	"QUIRK: Resetting on resume");
da3c9c4f	211	}
c41136b0	212
c3c5819a MN	213	#ifdef CONFIG_ACPI
	214	static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
	215	{
94116f81 AS	216	static const guid_t intel_dsm_guid =
	217	GUID_INIT(0xac340cb7, 0xe901, 0x45bf,
	218	0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23);
84ed9152 MW	219	union acpi_object *obj;
84ed9152 MW	220
94116f81	221	obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1,
84ed9152 MW	222	NULL);
84ed9152 MW	223	ACPI_FREE(obj);
c3c5819a MN	224	}
c3c5819a MN	225	#else
84ed9152	226	static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
c3c5819a MN	227	#endif /* CONFIG_ACPI */
c3c5819a MN	228
da3c9c4f SAS	229	/* called during probe() after chip reset completes */
	230	static int xhci_pci_setup(struct usb_hcd *hcd)
	231	{
	232	struct xhci_hcd *xhci;
	233	struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
	234	int retval;
66d4eadd	235
b50107bb MN	236	xhci = hcd_to_xhci(hcd);
	237	if (!xhci->sbrn)
	238	pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
	239
da3c9c4f	240	retval = xhci_gen_setup(hcd, xhci_pci_quirks);
66d4eadd	241	if (retval)
da3c9c4f	242	return retval;
006d5820	243
da3c9c4f SAS	244	if (!usb_hcd_is_primary_hcd(hcd))
da3c9c4f SAS	245	return 0;
66d4eadd	246
66d4eadd SS	247	xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
	248
	249	/* Find any debug ports */
989bad11	250	return xhci_pci_reinit(xhci, pdev);
b02d0ed6 SS	251	}
b02d0ed6 SS	252
f6ff0ac8 SS	253	/*
	254	* We need to register our own PCI probe function (instead of the USB core's
	255	* function) in order to create a second roothub under xHCI.
	256	*/
	257	static int xhci_pci_probe(struct pci_dev dev, const struct pci_device_id id)
	258	{
	259	int retval;
	260	struct xhci_hcd *xhci;
	261	struct hc_driver *driver;
	262	struct usb_hcd *hcd;
	263
	264	driver = (struct hc_driver *)id->driver_data;
bcffae77	265
8466489e MZ	266	/* For some HW implementation, a XHCI reset is just not enough... */
	267	if (usb_xhci_needs_pci_reset(dev)) {
	268	dev_info(&dev->dev, "Resetting\n");
	269	if (pci_reset_function_locked(dev))
	270	dev_warn(&dev->dev, "Reset failed");
	271	}
	272
bcffae77 MN	273	/* Prevent runtime suspending between USB-2 and USB-3 initialization */
	274	pm_runtime_get_noresume(&dev->dev);
	275
f6ff0ac8 SS	276	/* Register the USB 2.0 roothub.
	277	* FIXME: USB core must know to register the USB 2.0 roothub first.
	278	* This is sort of silly, because we could just set the HCD driver flags
	279	* to say USB 2.0, but I'm not sure what the implications would be in
	280	* the other parts of the HCD code.
	281	*/
	282	retval = usb_hcd_pci_probe(dev, id);
	283
	284	if (retval)
bcffae77	285	goto put_runtime_pm;
f6ff0ac8 SS	286
	287	/* USB 2.0 roothub is stored in the PCI device now. */
	288	hcd = dev_get_drvdata(&dev->dev);
	289	xhci = hcd_to_xhci(hcd);
	290	xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
	291	pci_name(dev), hcd);
	292	if (!xhci->shared_hcd) {
	293	retval = -ENOMEM;
	294	goto dealloc_usb2_hcd;
	295	}
	296
f6ff0ac8	297	retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
b5dd18d8	298	IRQF_SHARED);
f6ff0ac8 SS	299	if (retval)
	300	goto put_usb3_hcd;
	301	/* Roothub already marked as USB 3.0 speed */
3b3db026	302
8f873c1f HG	303	if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
8f873c1f HG	304	HCC_MAX_PSA(xhci->hcc_params) >= 4)
14aec589 ON	305	xhci->shared_hcd->can_do_streams = 1;
14aec589 ON	306
c3c5819a MN	307	if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
	308	xhci_pme_acpi_rtd3_enable(dev);
	309
bcffae77 MN	310	/* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
	311	pm_runtime_put_noidle(&dev->dev);
	312
f6ff0ac8 SS	313	return 0;
	314
	315	put_usb3_hcd:
	316	usb_put_hcd(xhci->shared_hcd);
	317	dealloc_usb2_hcd:
	318	usb_hcd_pci_remove(dev);
bcffae77 MN	319	put_runtime_pm:
bcffae77 MN	320	pm_runtime_put_noidle(&dev->dev);
f6ff0ac8 SS	321	return retval;
	322	}
	323
b02d0ed6 SS	324	static void xhci_pci_remove(struct pci_dev *dev)
	325	{
	326	struct xhci_hcd *xhci;
	327
	328	xhci = hcd_to_xhci(pci_get_drvdata(dev));
98d74f9c	329	xhci->xhc_state \|= XHCI_STATE_REMOVING;
f6ff0ac8 SS	330	if (xhci->shared_hcd) {
	331	usb_remove_hcd(xhci->shared_hcd);
	332	usb_put_hcd(xhci->shared_hcd);
	333	}
638298dc TI	334
	335	/* Workaround for spurious wakeups at shutdown with HSW */
	336	if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
	337	pci_set_power_state(dev, PCI_D3hot);
f1f6d9a8 MN	338
f1f6d9a8 MN	339	usb_hcd_pci_remove(dev);
66d4eadd SS	340	}
66d4eadd SS	341
5535b1d5	342	#ifdef CONFIG_PM
2b7627b7 TB	343	/*
	344	* In some Intel xHCI controllers, in order to get D3 working,
	345	* through a vendor specific SSIC CONFIG register at offset 0x883c,
	346	* SSIC PORT need to be marked as "unused" before putting xHCI
	347	* into D3. After D3 exit, the SSIC port need to be marked as "used".
	348	* Without this change, xHCI might not enter D3 state.
2b7627b7	349	*/
7e70cbff	350	static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
2b7627b7 TB	351	{
2b7627b7 TB	352	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2b7627b7 TB	353	u32 val;
2b7627b7 TB	354	void __iomem *reg;
fa895377	355	int i;
2b7627b7	356
7e70cbff LB	357	for (i = 0; i < SSIC_PORT_NUM; i++) {
	358	reg = (void __iomem *) xhci->cap_regs +
	359	SSIC_PORT_CFG2 +
	360	i * SSIC_PORT_CFG2_OFFSET;
	361
	362	/* Notify SSIC that SSIC profile programming is not done. */
	363	val = readl(reg) & ~PROG_DONE;
	364	writel(val, reg);
	365
	366	/* Mark SSIC port as unused(suspend) or used(resume) */
	367	val = readl(reg);
	368	if (suspend)
	369	val \|= SSIC_PORT_UNUSED;
	370	else
	371	val &= ~SSIC_PORT_UNUSED;
	372	writel(val, reg);
	373
	374	/* Notify SSIC that SSIC profile programming is done */
	375	val = readl(reg) \| PROG_DONE;
	376	writel(val, reg);
	377	readl(reg);
2b7627b7	378	}
7e70cbff LB	379	}
	380
	381	/*
	382	* Make sure PME works on some Intel xHCI controllers by writing 1 to clear
	383	* the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
	384	*/
	385	static void xhci_pme_quirk(struct usb_hcd *hcd)
	386	{
	387	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
	388	void __iomem *reg;
	389	u32 val;
2b7627b7 TB	390
	391	reg = (void __iomem *) xhci->cap_regs + 0x80a4;
	392	val = readl(reg);
	393	writel(val \| BIT(28), reg);
	394	readl(reg);
	395	}
	396
5535b1d5 AX	397	static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
	398	{
	399	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
c3897aa5	400	struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
92149c93	401	int ret;
c3897aa5 SS	402
	403	/*
	404	* Systems with the TI redriver that loses port status change events
	405	* need to have the registers polled during D3, so avoid D3cold.
	406	*/
e1cd9727	407	if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
9d26d3a8	408	pci_d3cold_disable(pdev);
5535b1d5	409
b8cb91e0	410	if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
7e70cbff LB	411	xhci_pme_quirk(hcd);
	412
	413	if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
	414	xhci_ssic_port_unused_quirk(hcd, true);
b8cb91e0	415
92149c93 LB	416	ret = xhci_suspend(xhci, do_wakeup);
	417	if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
	418	xhci_ssic_port_unused_quirk(hcd, false);
	419
	420	return ret;
5535b1d5 AX	421	}
	422
	423	static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
	424	{
	425	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
69e848c2	426	struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
5535b1d5 AX	427	int retval = 0;
5535b1d5 AX	428
69e848c2 SS	429	/* The BIOS on systems with the Intel Panther Point chipset may or may
	430	* not support xHCI natively. That means that during system resume, it
	431	* may switch the ports back to EHCI so that users can use their
	432	* keyboard to select a kernel from GRUB after resume from hibernate.
	433	*
	434	* The BIOS is supposed to remember whether the OS had xHCI ports
	435	* enabled before resume, and switch the ports back to xHCI when the
	436	* BIOS/OS semaphore is written, but we all know we can't trust BIOS
	437	* writers.
	438	*
	439	* Unconditionally switch the ports back to xHCI after a system resume.
26b76798 MN	440	* It should not matter whether the EHCI or xHCI controller is
	441	* resumed first. It's enough to do the switchover in xHCI because
	442	* USB core won't notice anything as the hub driver doesn't start
	443	* running again until after all the devices (including both EHCI and
	444	* xHCI host controllers) have been resumed.
69e848c2	445	*/
26b76798 MN	446
	447	if (pdev->vendor == PCI_VENDOR_ID_INTEL)
	448	usb_enable_intel_xhci_ports(pdev);
69e848c2	449
7e70cbff LB	450	if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
	451	xhci_ssic_port_unused_quirk(hcd, false);
	452
b8cb91e0	453	if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
7e70cbff	454	xhci_pme_quirk(hcd);
b8cb91e0	455
5535b1d5 AX	456	retval = xhci_resume(xhci, hibernated);
	457	return retval;
	458	}
	459	#endif /* CONFIG_PM */
	460
66d4eadd SS	461	/-------------------------------------------------------------------------/
	462
	463	/* PCI driver selection metadata; PCI hotplugging uses this */
	464	static const struct pci_device_id pci_ids[] = { {
	465	/* handle any USB 3.0 xHCI controller */
	466	PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
	467	.driver_data = (unsigned long) &xhci_pci_hc_driver,
	468	},
	469	{ /* end: all zeroes */ }
	470	};
	471	MODULE_DEVICE_TABLE(pci, pci_ids);
	472
	473	/* pci driver glue; this is a "new style" PCI driver module */
	474	static struct pci_driver xhci_pci_driver = {
	475	.name = (char *) hcd_name,
	476	.id_table = pci_ids,
	477
f6ff0ac8	478	.probe = xhci_pci_probe,
b02d0ed6	479	.remove = xhci_pci_remove,
66d4eadd SS	480	/* suspend and resume implemented later */
	481
	482	.shutdown = usb_hcd_pci_shutdown,
f875fdbf	483	#ifdef CONFIG_PM
5535b1d5 AX	484	.driver = {
	485	.pm = &usb_hcd_pci_pm_ops
	486	},
	487	#endif
66d4eadd SS	488	};
66d4eadd SS	489
29e409f0	490	static int __init xhci_pci_init(void)
66d4eadd	491	{
cd33a321	492	xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
1885d9a3 AB	493	#ifdef CONFIG_PM
	494	xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
	495	xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
	496	#endif
66d4eadd SS	497	return pci_register_driver(&xhci_pci_driver);
66d4eadd SS	498	}
29e409f0	499	module_init(xhci_pci_init);
66d4eadd	500
29e409f0	501	static void __exit xhci_pci_exit(void)
66d4eadd SS	502	{
	503	pci_unregister_driver(&xhci_pci_driver);
	504	}
29e409f0 AB	505	module_exit(xhci_pci_exit);
	506
	507	MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
	508	MODULE_LICENSE("GPL");