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5fd54ace | 1 | // SPDX-License-Identifier: GPL-2.0 |
66d4eadd SS |
2 | /* |
3 | * xHCI host controller driver PCI Bus Glue. | |
4 | * | |
5 | * Copyright (C) 2008 Intel Corp. | |
6 | * | |
7 | * Author: Sarah Sharp | |
8 | * Some code borrowed from the Linux EHCI driver. | |
66d4eadd SS |
9 | */ |
10 | ||
11 | #include <linux/pci.h> | |
7fc2a616 | 12 | #include <linux/slab.h> |
6eb0de82 | 13 | #include <linux/module.h> |
c3c5819a | 14 | #include <linux/acpi.h> |
66d4eadd SS |
15 | |
16 | #include "xhci.h" | |
4bdfe4c3 | 17 | #include "xhci-trace.h" |
66d4eadd | 18 | |
fa895377 LB |
19 | #define SSIC_PORT_NUM 2 |
20 | #define SSIC_PORT_CFG2 0x880c | |
21 | #define SSIC_PORT_CFG2_OFFSET 0x30 | |
abce329c RM |
22 | #define PROG_DONE (1 << 30) |
23 | #define SSIC_PORT_UNUSED (1 << 31) | |
24 | ||
ac9d8fe7 SS |
25 | /* Device for a quirk */ |
26 | #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73 | |
27 | #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000 | |
d95815ba | 28 | #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009 |
bba18e33 | 29 | #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400 |
ac9d8fe7 | 30 | |
c877b3b2 | 31 | #define PCI_VENDOR_ID_ETRON 0x1b6f |
170625e9 | 32 | #define PCI_DEVICE_ID_EJ168 0x7023 |
c877b3b2 | 33 | |
638298dc TI |
34 | #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31 |
35 | #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31 | |
4c39135a | 36 | #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1 |
b8cb91e0 MN |
37 | #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5 |
38 | #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f | |
39 | #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f | |
ccc04afb | 40 | #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8 |
0d46faca | 41 | #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8 |
346e9973 | 42 | #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8 |
a0c16630 | 43 | #define PCI_DEVICE_ID_INTEL_DNV_XHCI 0x19d0 |
638298dc | 44 | |
3ed41bce JL |
45 | #define PCI_DEVICE_ID_AMD_PROMONTORYA_4 0x43b9 |
46 | #define PCI_DEVICE_ID_AMD_PROMONTORYA_3 0x43ba | |
47 | #define PCI_DEVICE_ID_AMD_PROMONTORYA_2 0x43bb | |
48 | #define PCI_DEVICE_ID_AMD_PROMONTORYA_1 0x43bc | |
9da5a109 JC |
49 | #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142 |
50 | ||
66d4eadd SS |
51 | static const char hcd_name[] = "xhci_hcd"; |
52 | ||
1885d9a3 AB |
53 | static struct hc_driver __read_mostly xhci_pci_hc_driver; |
54 | ||
cd33a321 RQ |
55 | static int xhci_pci_setup(struct usb_hcd *hcd); |
56 | ||
57 | static const struct xhci_driver_overrides xhci_pci_overrides __initconst = { | |
cd33a321 RQ |
58 | .reset = xhci_pci_setup, |
59 | }; | |
60 | ||
66d4eadd SS |
61 | /* called after powerup, by probe or system-pm "wakeup" */ |
62 | static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev) | |
63 | { | |
64 | /* | |
65 | * TODO: Implement finding debug ports later. | |
66 | * TODO: see if there are any quirks that need to be added to handle | |
67 | * new extended capabilities. | |
68 | */ | |
69 | ||
70 | /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ | |
71 | if (!pci_set_mwi(pdev)) | |
72 | xhci_dbg(xhci, "MWI active\n"); | |
73 | ||
74 | xhci_dbg(xhci, "Finished xhci_pci_reinit\n"); | |
75 | return 0; | |
76 | } | |
77 | ||
da3c9c4f SAS |
78 | static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) |
79 | { | |
80 | struct pci_dev *pdev = to_pci_dev(dev); | |
81 | ||
ac9d8fe7 SS |
82 | /* Look for vendor-specific quirks */ |
83 | if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && | |
bba18e33 SS |
84 | (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK || |
85 | pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) { | |
86 | if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && | |
87 | pdev->revision == 0x0) { | |
ac9d8fe7 | 88 | xhci->quirks |= XHCI_RESET_EP_QUIRK; |
4bdfe4c3 XR |
89 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
90 | "QUIRK: Fresco Logic xHC needs configure" | |
91 | " endpoint cmd after reset endpoint"); | |
f5182b41 | 92 | } |
455f5892 ON |
93 | if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && |
94 | pdev->revision == 0x4) { | |
95 | xhci->quirks |= XHCI_SLOW_SUSPEND; | |
96 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, | |
97 | "QUIRK: Fresco Logic xHC revision %u" | |
98 | "must be suspended extra slowly", | |
99 | pdev->revision); | |
100 | } | |
7f5c4d63 HG |
101 | if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK) |
102 | xhci->quirks |= XHCI_BROKEN_STREAMS; | |
f5182b41 SS |
103 | /* Fresco Logic confirms: all revisions of this chip do not |
104 | * support MSI, even though some of them claim to in their PCI | |
105 | * capabilities. | |
106 | */ | |
107 | xhci->quirks |= XHCI_BROKEN_MSI; | |
4bdfe4c3 XR |
108 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
109 | "QUIRK: Fresco Logic revision %u " | |
110 | "has broken MSI implementation", | |
f5182b41 | 111 | pdev->revision); |
1530bbc6 | 112 | xhci->quirks |= XHCI_TRUST_TX_LENGTH; |
ac9d8fe7 | 113 | } |
f5182b41 | 114 | |
d95815ba HG |
115 | if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && |
116 | pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009) | |
117 | xhci->quirks |= XHCI_BROKEN_STREAMS; | |
118 | ||
0238634d SS |
119 | if (pdev->vendor == PCI_VENDOR_ID_NEC) |
120 | xhci->quirks |= XHCI_NEC_HOST; | |
ac9d8fe7 | 121 | |
7e393a83 AX |
122 | if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96) |
123 | xhci->quirks |= XHCI_AMD_0x96_HOST; | |
124 | ||
c41136b0 AX |
125 | /* AMD PLL quirk */ |
126 | if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info()) | |
127 | xhci->quirks |= XHCI_AMD_PLL_FIX; | |
2597fe99 | 128 | |
c5330b8a KHF |
129 | if (pdev->vendor == PCI_VENDOR_ID_AMD && |
130 | (pdev->device == 0x15e0 || | |
131 | pdev->device == 0x15e1 || | |
132 | pdev->device == 0x43bb)) | |
7c267cb7 KHF |
133 | xhci->quirks |= XHCI_SUSPEND_DELAY; |
134 | ||
2597fe99 HR |
135 | if (pdev->vendor == PCI_VENDOR_ID_AMD) |
136 | xhci->quirks |= XHCI_TRUST_TX_LENGTH; | |
137 | ||
3ed41bce JL |
138 | if ((pdev->vendor == PCI_VENDOR_ID_AMD) && |
139 | ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) || | |
140 | (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) || | |
141 | (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) || | |
142 | (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1))) | |
143 | xhci->quirks |= XHCI_U2_DISABLE_WAKE; | |
144 | ||
e3567d2c SS |
145 | if (pdev->vendor == PCI_VENDOR_ID_INTEL) { |
146 | xhci->quirks |= XHCI_LPM_SUPPORT; | |
147 | xhci->quirks |= XHCI_INTEL_HOST; | |
227a4fd8 | 148 | xhci->quirks |= XHCI_AVOID_BEI; |
e3567d2c | 149 | } |
ad808333 SS |
150 | if (pdev->vendor == PCI_VENDOR_ID_INTEL && |
151 | pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) { | |
2cf95c18 SS |
152 | xhci->quirks |= XHCI_EP_LIMIT_QUIRK; |
153 | xhci->limit_active_eps = 64; | |
86cc558e | 154 | xhci->quirks |= XHCI_SW_BW_CHECKING; |
e95829f4 SS |
155 | /* |
156 | * PPT desktop boards DH77EB and DH77DF will power back on after | |
157 | * a few seconds of being shutdown. The fix for this is to | |
158 | * switch the ports from xHCI to EHCI on shutdown. We can't use | |
159 | * DMI information to find those particular boards (since each | |
160 | * vendor will change the board name), so we have to key off all | |
161 | * PPT chipsets. | |
162 | */ | |
163 | xhci->quirks |= XHCI_SPURIOUS_REBOOT; | |
ad808333 | 164 | } |
0a939993 | 165 | if (pdev->vendor == PCI_VENDOR_ID_INTEL && |
4c39135a MN |
166 | (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI || |
167 | pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) { | |
c09ec25d | 168 | xhci->quirks |= XHCI_SPURIOUS_REBOOT; |
fd7cd061 | 169 | xhci->quirks |= XHCI_SPURIOUS_WAKEUP; |
638298dc | 170 | } |
b8cb91e0 MN |
171 | if (pdev->vendor == PCI_VENDOR_ID_INTEL && |
172 | (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || | |
173 | pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || | |
ccc04afb | 174 | pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || |
0d46faca | 175 | pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI || |
6c97cfc1 | 176 | pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI || |
a0c16630 MN |
177 | pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI || |
178 | pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI)) { | |
b8cb91e0 MN |
179 | xhci->quirks |= XHCI_PME_STUCK_QUIRK; |
180 | } | |
7e70cbff LB |
181 | if (pdev->vendor == PCI_VENDOR_ID_INTEL && |
182 | pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) { | |
183 | xhci->quirks |= XHCI_SSIC_PORT_UNUSED; | |
184 | } | |
346e9973 MN |
185 | if (pdev->vendor == PCI_VENDOR_ID_INTEL && |
186 | (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || | |
a0c16630 MN |
187 | pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI || |
188 | pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI)) | |
346e9973 MN |
189 | xhci->quirks |= XHCI_MISSING_CAS; |
190 | ||
c877b3b2 | 191 | if (pdev->vendor == PCI_VENDOR_ID_ETRON && |
170625e9 | 192 | pdev->device == PCI_DEVICE_ID_EJ168) { |
c877b3b2 | 193 | xhci->quirks |= XHCI_RESET_ON_RESUME; |
5cb7df2b | 194 | xhci->quirks |= XHCI_TRUST_TX_LENGTH; |
8f873c1f | 195 | xhci->quirks |= XHCI_BROKEN_STREAMS; |
c877b3b2 | 196 | } |
da997066 DT |
197 | if (pdev->vendor == PCI_VENDOR_ID_RENESAS && |
198 | pdev->device == 0x0014) | |
199 | xhci->quirks |= XHCI_TRUST_TX_LENGTH; | |
1aa9578c | 200 | if (pdev->vendor == PCI_VENDOR_ID_RENESAS && |
6db249eb | 201 | pdev->device == 0x0015) |
1aa9578c | 202 | xhci->quirks |= XHCI_RESET_ON_RESUME; |
457a4f61 EF |
203 | if (pdev->vendor == PCI_VENDOR_ID_VIA) |
204 | xhci->quirks |= XHCI_RESET_ON_RESUME; | |
85f4e45b | 205 | |
e21eba05 HG |
206 | /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */ |
207 | if (pdev->vendor == PCI_VENDOR_ID_VIA && | |
208 | pdev->device == 0x3432) | |
209 | xhci->quirks |= XHCI_BROKEN_STREAMS; | |
210 | ||
2391eacb HG |
211 | if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && |
212 | pdev->device == 0x1042) | |
213 | xhci->quirks |= XHCI_BROKEN_STREAMS; | |
d2f48f05 CL |
214 | if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && |
215 | pdev->device == 0x1142) | |
216 | xhci->quirks |= XHCI_TRUST_TX_LENGTH; | |
2391eacb | 217 | |
9da5a109 JC |
218 | if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && |
219 | pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) | |
220 | xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL; | |
221 | ||
69307ccb RQ |
222 | if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241) |
223 | xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7; | |
224 | ||
85f4e45b ON |
225 | if (xhci->quirks & XHCI_RESET_ON_RESUME) |
226 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, | |
227 | "QUIRK: Resetting on resume"); | |
da3c9c4f | 228 | } |
c41136b0 | 229 | |
c3c5819a MN |
230 | #ifdef CONFIG_ACPI |
231 | static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) | |
232 | { | |
94116f81 AS |
233 | static const guid_t intel_dsm_guid = |
234 | GUID_INIT(0xac340cb7, 0xe901, 0x45bf, | |
235 | 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23); | |
84ed9152 MW |
236 | union acpi_object *obj; |
237 | ||
94116f81 | 238 | obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1, |
84ed9152 MW |
239 | NULL); |
240 | ACPI_FREE(obj); | |
c3c5819a MN |
241 | } |
242 | #else | |
84ed9152 | 243 | static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { } |
c3c5819a MN |
244 | #endif /* CONFIG_ACPI */ |
245 | ||
da3c9c4f SAS |
246 | /* called during probe() after chip reset completes */ |
247 | static int xhci_pci_setup(struct usb_hcd *hcd) | |
248 | { | |
249 | struct xhci_hcd *xhci; | |
250 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); | |
251 | int retval; | |
66d4eadd | 252 | |
b50107bb MN |
253 | xhci = hcd_to_xhci(hcd); |
254 | if (!xhci->sbrn) | |
255 | pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn); | |
256 | ||
da3c9c4f | 257 | retval = xhci_gen_setup(hcd, xhci_pci_quirks); |
66d4eadd | 258 | if (retval) |
da3c9c4f | 259 | return retval; |
006d5820 | 260 | |
da3c9c4f SAS |
261 | if (!usb_hcd_is_primary_hcd(hcd)) |
262 | return 0; | |
66d4eadd | 263 | |
66d4eadd SS |
264 | xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn); |
265 | ||
266 | /* Find any debug ports */ | |
989bad11 | 267 | return xhci_pci_reinit(xhci, pdev); |
b02d0ed6 SS |
268 | } |
269 | ||
f6ff0ac8 SS |
270 | /* |
271 | * We need to register our own PCI probe function (instead of the USB core's | |
272 | * function) in order to create a second roothub under xHCI. | |
273 | */ | |
274 | static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) | |
275 | { | |
276 | int retval; | |
277 | struct xhci_hcd *xhci; | |
278 | struct hc_driver *driver; | |
279 | struct usb_hcd *hcd; | |
280 | ||
281 | driver = (struct hc_driver *)id->driver_data; | |
bcffae77 | 282 | |
8466489e MZ |
283 | /* For some HW implementation, a XHCI reset is just not enough... */ |
284 | if (usb_xhci_needs_pci_reset(dev)) { | |
285 | dev_info(&dev->dev, "Resetting\n"); | |
286 | if (pci_reset_function_locked(dev)) | |
287 | dev_warn(&dev->dev, "Reset failed"); | |
288 | } | |
289 | ||
bcffae77 MN |
290 | /* Prevent runtime suspending between USB-2 and USB-3 initialization */ |
291 | pm_runtime_get_noresume(&dev->dev); | |
292 | ||
f6ff0ac8 SS |
293 | /* Register the USB 2.0 roothub. |
294 | * FIXME: USB core must know to register the USB 2.0 roothub first. | |
295 | * This is sort of silly, because we could just set the HCD driver flags | |
296 | * to say USB 2.0, but I'm not sure what the implications would be in | |
297 | * the other parts of the HCD code. | |
298 | */ | |
299 | retval = usb_hcd_pci_probe(dev, id); | |
300 | ||
301 | if (retval) | |
bcffae77 | 302 | goto put_runtime_pm; |
f6ff0ac8 SS |
303 | |
304 | /* USB 2.0 roothub is stored in the PCI device now. */ | |
305 | hcd = dev_get_drvdata(&dev->dev); | |
306 | xhci = hcd_to_xhci(hcd); | |
307 | xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev, | |
308 | pci_name(dev), hcd); | |
309 | if (!xhci->shared_hcd) { | |
310 | retval = -ENOMEM; | |
311 | goto dealloc_usb2_hcd; | |
312 | } | |
313 | ||
f6ff0ac8 | 314 | retval = usb_add_hcd(xhci->shared_hcd, dev->irq, |
b5dd18d8 | 315 | IRQF_SHARED); |
f6ff0ac8 SS |
316 | if (retval) |
317 | goto put_usb3_hcd; | |
318 | /* Roothub already marked as USB 3.0 speed */ | |
3b3db026 | 319 | |
8f873c1f HG |
320 | if (!(xhci->quirks & XHCI_BROKEN_STREAMS) && |
321 | HCC_MAX_PSA(xhci->hcc_params) >= 4) | |
14aec589 ON |
322 | xhci->shared_hcd->can_do_streams = 1; |
323 | ||
c3c5819a MN |
324 | if (xhci->quirks & XHCI_PME_STUCK_QUIRK) |
325 | xhci_pme_acpi_rtd3_enable(dev); | |
326 | ||
bcffae77 MN |
327 | /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */ |
328 | pm_runtime_put_noidle(&dev->dev); | |
329 | ||
f6ff0ac8 SS |
330 | return 0; |
331 | ||
332 | put_usb3_hcd: | |
333 | usb_put_hcd(xhci->shared_hcd); | |
334 | dealloc_usb2_hcd: | |
335 | usb_hcd_pci_remove(dev); | |
bcffae77 MN |
336 | put_runtime_pm: |
337 | pm_runtime_put_noidle(&dev->dev); | |
f6ff0ac8 SS |
338 | return retval; |
339 | } | |
340 | ||
b02d0ed6 SS |
341 | static void xhci_pci_remove(struct pci_dev *dev) |
342 | { | |
343 | struct xhci_hcd *xhci; | |
344 | ||
345 | xhci = hcd_to_xhci(pci_get_drvdata(dev)); | |
98d74f9c | 346 | xhci->xhc_state |= XHCI_STATE_REMOVING; |
f6ff0ac8 SS |
347 | if (xhci->shared_hcd) { |
348 | usb_remove_hcd(xhci->shared_hcd); | |
349 | usb_put_hcd(xhci->shared_hcd); | |
350 | } | |
638298dc TI |
351 | |
352 | /* Workaround for spurious wakeups at shutdown with HSW */ | |
353 | if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) | |
354 | pci_set_power_state(dev, PCI_D3hot); | |
f1f6d9a8 MN |
355 | |
356 | usb_hcd_pci_remove(dev); | |
66d4eadd SS |
357 | } |
358 | ||
5535b1d5 | 359 | #ifdef CONFIG_PM |
2b7627b7 TB |
360 | /* |
361 | * In some Intel xHCI controllers, in order to get D3 working, | |
362 | * through a vendor specific SSIC CONFIG register at offset 0x883c, | |
363 | * SSIC PORT need to be marked as "unused" before putting xHCI | |
364 | * into D3. After D3 exit, the SSIC port need to be marked as "used". | |
365 | * Without this change, xHCI might not enter D3 state. | |
2b7627b7 | 366 | */ |
7e70cbff | 367 | static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend) |
2b7627b7 TB |
368 | { |
369 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
2b7627b7 TB |
370 | u32 val; |
371 | void __iomem *reg; | |
fa895377 | 372 | int i; |
2b7627b7 | 373 | |
7e70cbff LB |
374 | for (i = 0; i < SSIC_PORT_NUM; i++) { |
375 | reg = (void __iomem *) xhci->cap_regs + | |
376 | SSIC_PORT_CFG2 + | |
377 | i * SSIC_PORT_CFG2_OFFSET; | |
378 | ||
379 | /* Notify SSIC that SSIC profile programming is not done. */ | |
380 | val = readl(reg) & ~PROG_DONE; | |
381 | writel(val, reg); | |
382 | ||
383 | /* Mark SSIC port as unused(suspend) or used(resume) */ | |
384 | val = readl(reg); | |
385 | if (suspend) | |
386 | val |= SSIC_PORT_UNUSED; | |
387 | else | |
388 | val &= ~SSIC_PORT_UNUSED; | |
389 | writel(val, reg); | |
390 | ||
391 | /* Notify SSIC that SSIC profile programming is done */ | |
392 | val = readl(reg) | PROG_DONE; | |
393 | writel(val, reg); | |
394 | readl(reg); | |
2b7627b7 | 395 | } |
7e70cbff LB |
396 | } |
397 | ||
398 | /* | |
399 | * Make sure PME works on some Intel xHCI controllers by writing 1 to clear | |
400 | * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4 | |
401 | */ | |
402 | static void xhci_pme_quirk(struct usb_hcd *hcd) | |
403 | { | |
404 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
405 | void __iomem *reg; | |
406 | u32 val; | |
2b7627b7 TB |
407 | |
408 | reg = (void __iomem *) xhci->cap_regs + 0x80a4; | |
409 | val = readl(reg); | |
410 | writel(val | BIT(28), reg); | |
411 | readl(reg); | |
412 | } | |
413 | ||
5535b1d5 AX |
414 | static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) |
415 | { | |
416 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
c3897aa5 | 417 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); |
92149c93 | 418 | int ret; |
c3897aa5 SS |
419 | |
420 | /* | |
421 | * Systems with the TI redriver that loses port status change events | |
422 | * need to have the registers polled during D3, so avoid D3cold. | |
423 | */ | |
e1cd9727 | 424 | if (xhci->quirks & XHCI_COMP_MODE_QUIRK) |
9d26d3a8 | 425 | pci_d3cold_disable(pdev); |
5535b1d5 | 426 | |
b8cb91e0 | 427 | if (xhci->quirks & XHCI_PME_STUCK_QUIRK) |
7e70cbff LB |
428 | xhci_pme_quirk(hcd); |
429 | ||
430 | if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) | |
431 | xhci_ssic_port_unused_quirk(hcd, true); | |
b8cb91e0 | 432 | |
92149c93 LB |
433 | ret = xhci_suspend(xhci, do_wakeup); |
434 | if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED)) | |
435 | xhci_ssic_port_unused_quirk(hcd, false); | |
436 | ||
437 | return ret; | |
5535b1d5 AX |
438 | } |
439 | ||
440 | static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated) | |
441 | { | |
442 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
69e848c2 | 443 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); |
5535b1d5 AX |
444 | int retval = 0; |
445 | ||
69e848c2 SS |
446 | /* The BIOS on systems with the Intel Panther Point chipset may or may |
447 | * not support xHCI natively. That means that during system resume, it | |
448 | * may switch the ports back to EHCI so that users can use their | |
449 | * keyboard to select a kernel from GRUB after resume from hibernate. | |
450 | * | |
451 | * The BIOS is supposed to remember whether the OS had xHCI ports | |
452 | * enabled before resume, and switch the ports back to xHCI when the | |
453 | * BIOS/OS semaphore is written, but we all know we can't trust BIOS | |
454 | * writers. | |
455 | * | |
456 | * Unconditionally switch the ports back to xHCI after a system resume. | |
26b76798 MN |
457 | * It should not matter whether the EHCI or xHCI controller is |
458 | * resumed first. It's enough to do the switchover in xHCI because | |
459 | * USB core won't notice anything as the hub driver doesn't start | |
460 | * running again until after all the devices (including both EHCI and | |
461 | * xHCI host controllers) have been resumed. | |
69e848c2 | 462 | */ |
26b76798 MN |
463 | |
464 | if (pdev->vendor == PCI_VENDOR_ID_INTEL) | |
465 | usb_enable_intel_xhci_ports(pdev); | |
69e848c2 | 466 | |
7e70cbff LB |
467 | if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) |
468 | xhci_ssic_port_unused_quirk(hcd, false); | |
469 | ||
b8cb91e0 | 470 | if (xhci->quirks & XHCI_PME_STUCK_QUIRK) |
7e70cbff | 471 | xhci_pme_quirk(hcd); |
b8cb91e0 | 472 | |
5535b1d5 AX |
473 | retval = xhci_resume(xhci, hibernated); |
474 | return retval; | |
475 | } | |
476 | #endif /* CONFIG_PM */ | |
477 | ||
66d4eadd SS |
478 | /*-------------------------------------------------------------------------*/ |
479 | ||
480 | /* PCI driver selection metadata; PCI hotplugging uses this */ | |
481 | static const struct pci_device_id pci_ids[] = { { | |
482 | /* handle any USB 3.0 xHCI controller */ | |
483 | PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0), | |
484 | .driver_data = (unsigned long) &xhci_pci_hc_driver, | |
485 | }, | |
486 | { /* end: all zeroes */ } | |
487 | }; | |
488 | MODULE_DEVICE_TABLE(pci, pci_ids); | |
489 | ||
490 | /* pci driver glue; this is a "new style" PCI driver module */ | |
491 | static struct pci_driver xhci_pci_driver = { | |
492 | .name = (char *) hcd_name, | |
493 | .id_table = pci_ids, | |
494 | ||
f6ff0ac8 | 495 | .probe = xhci_pci_probe, |
b02d0ed6 | 496 | .remove = xhci_pci_remove, |
66d4eadd SS |
497 | /* suspend and resume implemented later */ |
498 | ||
499 | .shutdown = usb_hcd_pci_shutdown, | |
f875fdbf | 500 | #ifdef CONFIG_PM |
5535b1d5 AX |
501 | .driver = { |
502 | .pm = &usb_hcd_pci_pm_ops | |
503 | }, | |
504 | #endif | |
66d4eadd SS |
505 | }; |
506 | ||
29e409f0 | 507 | static int __init xhci_pci_init(void) |
66d4eadd | 508 | { |
cd33a321 | 509 | xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides); |
1885d9a3 AB |
510 | #ifdef CONFIG_PM |
511 | xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend; | |
512 | xhci_pci_hc_driver.pci_resume = xhci_pci_resume; | |
513 | #endif | |
66d4eadd SS |
514 | return pci_register_driver(&xhci_pci_driver); |
515 | } | |
29e409f0 | 516 | module_init(xhci_pci_init); |
66d4eadd | 517 | |
29e409f0 | 518 | static void __exit xhci_pci_exit(void) |
66d4eadd SS |
519 | { |
520 | pci_unregister_driver(&xhci_pci_driver); | |
521 | } | |
29e409f0 AB |
522 | module_exit(xhci_pci_exit); |
523 | ||
524 | MODULE_DESCRIPTION("xHCI PCI Host Controller Driver"); | |
525 | MODULE_LICENSE("GPL"); |