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66d4eadd SS |
1 | /* |
2 | * xHCI host controller driver PCI Bus Glue. | |
3 | * | |
4 | * Copyright (C) 2008 Intel Corp. | |
5 | * | |
6 | * Author: Sarah Sharp | |
7 | * Some code borrowed from the Linux EHCI driver. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | * for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software Foundation, | |
20 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
23 | #include <linux/pci.h> | |
7fc2a616 | 24 | #include <linux/slab.h> |
6eb0de82 | 25 | #include <linux/module.h> |
66d4eadd SS |
26 | |
27 | #include "xhci.h" | |
28 | ||
ac9d8fe7 SS |
29 | /* Device for a quirk */ |
30 | #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73 | |
31 | #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000 | |
32 | ||
c877b3b2 ML |
33 | #define PCI_VENDOR_ID_ETRON 0x1b6f |
34 | #define PCI_DEVICE_ID_ASROCK_P67 0x7023 | |
35 | ||
66d4eadd SS |
36 | static const char hcd_name[] = "xhci_hcd"; |
37 | ||
38 | /* called after powerup, by probe or system-pm "wakeup" */ | |
39 | static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev) | |
40 | { | |
41 | /* | |
42 | * TODO: Implement finding debug ports later. | |
43 | * TODO: see if there are any quirks that need to be added to handle | |
44 | * new extended capabilities. | |
45 | */ | |
46 | ||
47 | /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ | |
48 | if (!pci_set_mwi(pdev)) | |
49 | xhci_dbg(xhci, "MWI active\n"); | |
50 | ||
51 | xhci_dbg(xhci, "Finished xhci_pci_reinit\n"); | |
52 | return 0; | |
53 | } | |
54 | ||
da3c9c4f SAS |
55 | static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) |
56 | { | |
57 | struct pci_dev *pdev = to_pci_dev(dev); | |
58 | ||
ac9d8fe7 SS |
59 | /* Look for vendor-specific quirks */ |
60 | if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && | |
f5182b41 SS |
61 | pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK) { |
62 | if (pdev->revision == 0x0) { | |
ac9d8fe7 SS |
63 | xhci->quirks |= XHCI_RESET_EP_QUIRK; |
64 | xhci_dbg(xhci, "QUIRK: Fresco Logic xHC needs configure" | |
65 | " endpoint cmd after reset endpoint\n"); | |
f5182b41 SS |
66 | } |
67 | /* Fresco Logic confirms: all revisions of this chip do not | |
68 | * support MSI, even though some of them claim to in their PCI | |
69 | * capabilities. | |
70 | */ | |
71 | xhci->quirks |= XHCI_BROKEN_MSI; | |
72 | xhci_dbg(xhci, "QUIRK: Fresco Logic revision %u " | |
73 | "has broken MSI implementation\n", | |
74 | pdev->revision); | |
1530bbc6 | 75 | xhci->quirks |= XHCI_TRUST_TX_LENGTH; |
ac9d8fe7 | 76 | } |
f5182b41 | 77 | |
0238634d SS |
78 | if (pdev->vendor == PCI_VENDOR_ID_NEC) |
79 | xhci->quirks |= XHCI_NEC_HOST; | |
ac9d8fe7 | 80 | |
7e393a83 AX |
81 | if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96) |
82 | xhci->quirks |= XHCI_AMD_0x96_HOST; | |
83 | ||
c41136b0 AX |
84 | /* AMD PLL quirk */ |
85 | if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info()) | |
86 | xhci->quirks |= XHCI_AMD_PLL_FIX; | |
e3567d2c SS |
87 | if (pdev->vendor == PCI_VENDOR_ID_INTEL) { |
88 | xhci->quirks |= XHCI_LPM_SUPPORT; | |
89 | xhci->quirks |= XHCI_INTEL_HOST; | |
90 | } | |
ad808333 SS |
91 | if (pdev->vendor == PCI_VENDOR_ID_INTEL && |
92 | pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) { | |
93 | xhci->quirks |= XHCI_SPURIOUS_SUCCESS; | |
2cf95c18 SS |
94 | xhci->quirks |= XHCI_EP_LIMIT_QUIRK; |
95 | xhci->limit_active_eps = 64; | |
86cc558e | 96 | xhci->quirks |= XHCI_SW_BW_CHECKING; |
ad808333 | 97 | } |
c877b3b2 ML |
98 | if (pdev->vendor == PCI_VENDOR_ID_ETRON && |
99 | pdev->device == PCI_DEVICE_ID_ASROCK_P67) { | |
100 | xhci->quirks |= XHCI_RESET_ON_RESUME; | |
101 | xhci_dbg(xhci, "QUIRK: Resetting on resume\n"); | |
5cb7df2b | 102 | xhci->quirks |= XHCI_TRUST_TX_LENGTH; |
c877b3b2 | 103 | } |
457a4f61 EF |
104 | if (pdev->vendor == PCI_VENDOR_ID_VIA) |
105 | xhci->quirks |= XHCI_RESET_ON_RESUME; | |
da3c9c4f | 106 | } |
c41136b0 | 107 | |
da3c9c4f SAS |
108 | /* called during probe() after chip reset completes */ |
109 | static int xhci_pci_setup(struct usb_hcd *hcd) | |
110 | { | |
111 | struct xhci_hcd *xhci; | |
112 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); | |
113 | int retval; | |
66d4eadd | 114 | |
da3c9c4f | 115 | retval = xhci_gen_setup(hcd, xhci_pci_quirks); |
66d4eadd | 116 | if (retval) |
da3c9c4f | 117 | return retval; |
006d5820 | 118 | |
da3c9c4f SAS |
119 | xhci = hcd_to_xhci(hcd); |
120 | if (!usb_hcd_is_primary_hcd(hcd)) | |
121 | return 0; | |
66d4eadd SS |
122 | |
123 | pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn); | |
124 | xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn); | |
125 | ||
126 | /* Find any debug ports */ | |
b02d0ed6 SS |
127 | retval = xhci_pci_reinit(xhci, pdev); |
128 | if (!retval) | |
129 | return retval; | |
130 | ||
b02d0ed6 SS |
131 | kfree(xhci); |
132 | return retval; | |
133 | } | |
134 | ||
f6ff0ac8 SS |
135 | /* |
136 | * We need to register our own PCI probe function (instead of the USB core's | |
137 | * function) in order to create a second roothub under xHCI. | |
138 | */ | |
139 | static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) | |
140 | { | |
141 | int retval; | |
142 | struct xhci_hcd *xhci; | |
143 | struct hc_driver *driver; | |
144 | struct usb_hcd *hcd; | |
145 | ||
146 | driver = (struct hc_driver *)id->driver_data; | |
147 | /* Register the USB 2.0 roothub. | |
148 | * FIXME: USB core must know to register the USB 2.0 roothub first. | |
149 | * This is sort of silly, because we could just set the HCD driver flags | |
150 | * to say USB 2.0, but I'm not sure what the implications would be in | |
151 | * the other parts of the HCD code. | |
152 | */ | |
153 | retval = usb_hcd_pci_probe(dev, id); | |
154 | ||
155 | if (retval) | |
156 | return retval; | |
157 | ||
158 | /* USB 2.0 roothub is stored in the PCI device now. */ | |
159 | hcd = dev_get_drvdata(&dev->dev); | |
160 | xhci = hcd_to_xhci(hcd); | |
161 | xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev, | |
162 | pci_name(dev), hcd); | |
163 | if (!xhci->shared_hcd) { | |
164 | retval = -ENOMEM; | |
165 | goto dealloc_usb2_hcd; | |
166 | } | |
167 | ||
168 | /* Set the xHCI pointer before xhci_pci_setup() (aka hcd_driver.reset) | |
169 | * is called by usb_add_hcd(). | |
170 | */ | |
171 | *((struct xhci_hcd **) xhci->shared_hcd->hcd_priv) = xhci; | |
172 | ||
173 | retval = usb_add_hcd(xhci->shared_hcd, dev->irq, | |
b5dd18d8 | 174 | IRQF_SHARED); |
f6ff0ac8 SS |
175 | if (retval) |
176 | goto put_usb3_hcd; | |
177 | /* Roothub already marked as USB 3.0 speed */ | |
3b3db026 SS |
178 | |
179 | /* We know the LPM timeout algorithms for this host, let the USB core | |
180 | * enable and disable LPM for devices under the USB 3.0 roothub. | |
181 | */ | |
182 | if (xhci->quirks & XHCI_LPM_SUPPORT) | |
183 | hcd_to_bus(xhci->shared_hcd)->root_hub->lpm_capable = 1; | |
184 | ||
f6ff0ac8 SS |
185 | return 0; |
186 | ||
187 | put_usb3_hcd: | |
188 | usb_put_hcd(xhci->shared_hcd); | |
189 | dealloc_usb2_hcd: | |
190 | usb_hcd_pci_remove(dev); | |
191 | return retval; | |
192 | } | |
193 | ||
b02d0ed6 SS |
194 | static void xhci_pci_remove(struct pci_dev *dev) |
195 | { | |
196 | struct xhci_hcd *xhci; | |
197 | ||
198 | xhci = hcd_to_xhci(pci_get_drvdata(dev)); | |
f6ff0ac8 SS |
199 | if (xhci->shared_hcd) { |
200 | usb_remove_hcd(xhci->shared_hcd); | |
201 | usb_put_hcd(xhci->shared_hcd); | |
202 | } | |
b02d0ed6 SS |
203 | usb_hcd_pci_remove(dev); |
204 | kfree(xhci); | |
66d4eadd SS |
205 | } |
206 | ||
5535b1d5 AX |
207 | #ifdef CONFIG_PM |
208 | static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) | |
209 | { | |
210 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
211 | int retval = 0; | |
212 | ||
b3209379 SS |
213 | if (hcd->state != HC_STATE_SUSPENDED || |
214 | xhci->shared_hcd->state != HC_STATE_SUSPENDED) | |
5535b1d5 AX |
215 | return -EINVAL; |
216 | ||
217 | retval = xhci_suspend(xhci); | |
218 | ||
219 | return retval; | |
220 | } | |
221 | ||
222 | static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated) | |
223 | { | |
224 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
69e848c2 | 225 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); |
5535b1d5 AX |
226 | int retval = 0; |
227 | ||
69e848c2 SS |
228 | /* The BIOS on systems with the Intel Panther Point chipset may or may |
229 | * not support xHCI natively. That means that during system resume, it | |
230 | * may switch the ports back to EHCI so that users can use their | |
231 | * keyboard to select a kernel from GRUB after resume from hibernate. | |
232 | * | |
233 | * The BIOS is supposed to remember whether the OS had xHCI ports | |
234 | * enabled before resume, and switch the ports back to xHCI when the | |
235 | * BIOS/OS semaphore is written, but we all know we can't trust BIOS | |
236 | * writers. | |
237 | * | |
238 | * Unconditionally switch the ports back to xHCI after a system resume. | |
239 | * We can't tell whether the EHCI or xHCI controller will be resumed | |
240 | * first, so we have to do the port switchover in both drivers. Writing | |
241 | * a '1' to the port switchover registers should have no effect if the | |
242 | * port was already switched over. | |
243 | */ | |
244 | if (usb_is_intel_switchable_xhci(pdev)) | |
245 | usb_enable_xhci_ports(pdev); | |
246 | ||
5535b1d5 AX |
247 | retval = xhci_resume(xhci, hibernated); |
248 | return retval; | |
249 | } | |
250 | #endif /* CONFIG_PM */ | |
251 | ||
66d4eadd SS |
252 | static const struct hc_driver xhci_pci_hc_driver = { |
253 | .description = hcd_name, | |
254 | .product_desc = "xHCI Host Controller", | |
b02d0ed6 | 255 | .hcd_priv_size = sizeof(struct xhci_hcd *), |
66d4eadd SS |
256 | |
257 | /* | |
258 | * generic hardware linkage | |
259 | */ | |
7f84eef0 | 260 | .irq = xhci_irq, |
f6ff0ac8 | 261 | .flags = HCD_MEMORY | HCD_USB3 | HCD_SHARED, |
66d4eadd SS |
262 | |
263 | /* | |
264 | * basic lifecycle operations | |
265 | */ | |
266 | .reset = xhci_pci_setup, | |
267 | .start = xhci_run, | |
5535b1d5 AX |
268 | #ifdef CONFIG_PM |
269 | .pci_suspend = xhci_pci_suspend, | |
270 | .pci_resume = xhci_pci_resume, | |
271 | #endif | |
66d4eadd SS |
272 | .stop = xhci_stop, |
273 | .shutdown = xhci_shutdown, | |
274 | ||
3ffbba95 SS |
275 | /* |
276 | * managing i/o requests and associated device resources | |
277 | */ | |
d0e96f5a SS |
278 | .urb_enqueue = xhci_urb_enqueue, |
279 | .urb_dequeue = xhci_urb_dequeue, | |
3ffbba95 SS |
280 | .alloc_dev = xhci_alloc_dev, |
281 | .free_dev = xhci_free_dev, | |
eab1cafc SS |
282 | .alloc_streams = xhci_alloc_streams, |
283 | .free_streams = xhci_free_streams, | |
f94e0186 SS |
284 | .add_endpoint = xhci_add_endpoint, |
285 | .drop_endpoint = xhci_drop_endpoint, | |
a1587d97 | 286 | .endpoint_reset = xhci_endpoint_reset, |
f94e0186 SS |
287 | .check_bandwidth = xhci_check_bandwidth, |
288 | .reset_bandwidth = xhci_reset_bandwidth, | |
3ffbba95 | 289 | .address_device = xhci_address_device, |
b356b7c7 | 290 | .update_hub_device = xhci_update_hub_device, |
f0615c45 | 291 | .reset_device = xhci_discover_or_reset_device, |
3ffbba95 | 292 | |
66d4eadd SS |
293 | /* |
294 | * scheduling support | |
295 | */ | |
296 | .get_frame_number = xhci_get_frame, | |
297 | ||
0f2a7930 SS |
298 | /* Root hub support */ |
299 | .hub_control = xhci_hub_control, | |
300 | .hub_status_data = xhci_hub_status_data, | |
9777e3ce AX |
301 | .bus_suspend = xhci_bus_suspend, |
302 | .bus_resume = xhci_bus_resume, | |
9574323c AX |
303 | /* |
304 | * call back when device connected and addressed | |
305 | */ | |
306 | .update_device = xhci_update_device, | |
65580b43 | 307 | .set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm, |
3b3db026 SS |
308 | .enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout, |
309 | .disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout, | |
66d4eadd SS |
310 | }; |
311 | ||
312 | /*-------------------------------------------------------------------------*/ | |
313 | ||
314 | /* PCI driver selection metadata; PCI hotplugging uses this */ | |
315 | static const struct pci_device_id pci_ids[] = { { | |
316 | /* handle any USB 3.0 xHCI controller */ | |
317 | PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0), | |
318 | .driver_data = (unsigned long) &xhci_pci_hc_driver, | |
319 | }, | |
320 | { /* end: all zeroes */ } | |
321 | }; | |
322 | MODULE_DEVICE_TABLE(pci, pci_ids); | |
323 | ||
324 | /* pci driver glue; this is a "new style" PCI driver module */ | |
325 | static struct pci_driver xhci_pci_driver = { | |
326 | .name = (char *) hcd_name, | |
327 | .id_table = pci_ids, | |
328 | ||
f6ff0ac8 | 329 | .probe = xhci_pci_probe, |
b02d0ed6 | 330 | .remove = xhci_pci_remove, |
66d4eadd SS |
331 | /* suspend and resume implemented later */ |
332 | ||
333 | .shutdown = usb_hcd_pci_shutdown, | |
5535b1d5 AX |
334 | #ifdef CONFIG_PM_SLEEP |
335 | .driver = { | |
336 | .pm = &usb_hcd_pci_pm_ops | |
337 | }, | |
338 | #endif | |
66d4eadd SS |
339 | }; |
340 | ||
0cc47d54 | 341 | int __init xhci_register_pci(void) |
66d4eadd SS |
342 | { |
343 | return pci_register_driver(&xhci_pci_driver); | |
344 | } | |
345 | ||
a46c46a1 | 346 | void xhci_unregister_pci(void) |
66d4eadd SS |
347 | { |
348 | pci_unregister_driver(&xhci_pci_driver); | |
349 | } |