[mirror_ubuntu-bionic-kernel.git] / drivers / usb / host / xhci-pci.c

/*
 * xHCI host controller driver PCI Bus Glue.
 *
 * Copyright (C) 2008 Intel Corp.
 *
 * Author: Sarah Sharp
 * Some code borrowed from the Linux EHCI driver.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
 * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 * for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software Foundation,
 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/acpi.h>

#include "xhci.h"
#include "xhci-trace.h"

#define SSIC_PORT_NUM		2
#define SSIC_PORT_CFG2		0x880c
#define SSIC_PORT_CFG2_OFFSET	0x30
#define PROG_DONE		(1 << 30)
#define SSIC_PORT_UNUSED	(1 << 31)

/* Device for a quirk */
#define PCI_VENDOR_ID_FRESCO_LOGIC	0x1b73
#define PCI_DEVICE_ID_FRESCO_LOGIC_PDK	0x1000
#define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009	0x1009
#define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400	0x1400

#define PCI_VENDOR_ID_ETRON		0x1b6f
#define PCI_DEVICE_ID_EJ168		0x7023

#define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI	0x8c31
#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI	0x9c31
#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI	0x9cb1
#define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI		0x22b5
#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI		0xa12f
#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI	0x9d2f
#define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI		0x0aa8
#define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI		0x1aa8
#define PCI_DEVICE_ID_INTEL_APL_XHCI			0x5aa8
#define PCI_DEVICE_ID_INTEL_DNV_XHCI			0x19d0

#define PCI_DEVICE_ID_AMD_PROMONTORYA_4			0x43b9
#define PCI_DEVICE_ID_AMD_PROMONTORYA_3			0x43ba
#define PCI_DEVICE_ID_AMD_PROMONTORYA_2			0x43bb
#define PCI_DEVICE_ID_AMD_PROMONTORYA_1			0x43bc

#define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI		0x1142

static const char hcd_name[] = "xhci_hcd";

static struct hc_driver __read_mostly xhci_pci_hc_driver;

static int xhci_pci_setup(struct usb_hcd *hcd);

static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
	.reset = xhci_pci_setup,
};

/* called after powerup, by probe or system-pm "wakeup" */
static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
{
	/*
	 * TODO: Implement finding debug ports later.
	 * TODO: see if there are any quirks that need to be added to handle
	 * new extended capabilities.
	 */

	/* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
	if (!pci_set_mwi(pdev))
		xhci_dbg(xhci, "MWI active\n");

	xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
	return 0;
}

static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
{
	struct pci_dev		*pdev = to_pci_dev(dev);

	/* Look for vendor-specific quirks */
	if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
			(pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
			 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
		if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
				pdev->revision == 0x0) {
			xhci->quirks |= XHCI_RESET_EP_QUIRK;
			xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
				"QUIRK: Fresco Logic xHC needs configure"
				" endpoint cmd after reset endpoint");
		}
		if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
				pdev->revision == 0x4) {
			xhci->quirks |= XHCI_SLOW_SUSPEND;
			xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
				"QUIRK: Fresco Logic xHC revision %u"
				"must be suspended extra slowly",
				pdev->revision);
		}
		if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
			xhci->quirks |= XHCI_BROKEN_STREAMS;
		/* Fresco Logic confirms: all revisions of this chip do not
		 * support MSI, even though some of them claim to in their PCI
		 * capabilities.
		 */
		xhci->quirks |= XHCI_BROKEN_MSI;
		xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
				"QUIRK: Fresco Logic revision %u "
				"has broken MSI implementation",
				pdev->revision);
		xhci->quirks |= XHCI_TRUST_TX_LENGTH;
	}

	if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
			pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009)
		xhci->quirks |= XHCI_BROKEN_STREAMS;

	if (pdev->vendor == PCI_VENDOR_ID_NEC)
		xhci->quirks |= XHCI_NEC_HOST;

	if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
		xhci->quirks |= XHCI_AMD_0x96_HOST;

	/* AMD PLL quirk */
	if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
		xhci->quirks |= XHCI_AMD_PLL_FIX;

	if (pdev->vendor == PCI_VENDOR_ID_AMD)
		xhci->quirks |= XHCI_TRUST_TX_LENGTH;

	if ((pdev->vendor == PCI_VENDOR_ID_AMD) &&
		((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) ||
		(pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) ||
		(pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) ||
		(pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1)))
		xhci->quirks |= XHCI_U2_DISABLE_WAKE;

	if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
		xhci->quirks |= XHCI_LPM_SUPPORT;
		xhci->quirks |= XHCI_INTEL_HOST;
		xhci->quirks |= XHCI_AVOID_BEI;
	}
	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
			pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
		xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
		xhci->limit_active_eps = 64;
		xhci->quirks |= XHCI_SW_BW_CHECKING;
		/*
		 * PPT desktop boards DH77EB and DH77DF will power back on after
		 * a few seconds of being shutdown.  The fix for this is to
		 * switch the ports from xHCI to EHCI on shutdown.  We can't use
		 * DMI information to find those particular boards (since each
		 * vendor will change the board name), so we have to key off all
		 * PPT chipsets.
		 */
		xhci->quirks |= XHCI_SPURIOUS_REBOOT;
	}
	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
		(pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI ||
		 pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
		xhci->quirks |= XHCI_SPURIOUS_REBOOT;
		xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
	}
	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
		(pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
		 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
		 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
		 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
		 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI ||
		 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
		 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI)) {
		xhci->quirks |= XHCI_PME_STUCK_QUIRK;
	}
	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
		 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) {
		xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
	}
	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
	    (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
	     pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
	     pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI))
		xhci->quirks |= XHCI_MISSING_CAS;

	if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
			pdev->device == PCI_DEVICE_ID_EJ168) {
		xhci->quirks |= XHCI_RESET_ON_RESUME;
		xhci->quirks |= XHCI_TRUST_TX_LENGTH;
		xhci->quirks |= XHCI_BROKEN_STREAMS;
	}
	if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
			pdev->device == 0x0015)
		xhci->quirks |= XHCI_RESET_ON_RESUME;
	if (pdev->vendor == PCI_VENDOR_ID_VIA)
		xhci->quirks |= XHCI_RESET_ON_RESUME;

	/* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
	if (pdev->vendor == PCI_VENDOR_ID_VIA &&
			pdev->device == 0x3432)
		xhci->quirks |= XHCI_BROKEN_STREAMS;

	if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
			pdev->device == 0x1042)
		xhci->quirks |= XHCI_BROKEN_STREAMS;
	if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
			pdev->device == 0x1142)
		xhci->quirks |= XHCI_TRUST_TX_LENGTH;

	if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
		pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI)
		xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL;

	if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241)
		xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7;

	if (xhci->quirks & XHCI_RESET_ON_RESUME)
		xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
				"QUIRK: Resetting on resume");
}

#ifdef CONFIG_ACPI
static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
{
	static const guid_t intel_dsm_guid =
		GUID_INIT(0xac340cb7, 0xe901, 0x45bf,
			  0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23);
	union acpi_object *obj;

	obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1,
				NULL);
	ACPI_FREE(obj);
}
#else
static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
#endif /* CONFIG_ACPI */

/* called during probe() after chip reset completes */
static int xhci_pci_setup(struct usb_hcd *hcd)
{
	struct xhci_hcd		*xhci;
	struct pci_dev		*pdev = to_pci_dev(hcd->self.controller);
	int			retval;

	xhci = hcd_to_xhci(hcd);
	if (!xhci->sbrn)
		pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);

	retval = xhci_gen_setup(hcd, xhci_pci_quirks);
	if (retval)
		return retval;

	if (!usb_hcd_is_primary_hcd(hcd))
		return 0;

	xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);

	/* Find any debug ports */
	return xhci_pci_reinit(xhci, pdev);
}

/*
 * We need to register our own PCI probe function (instead of the USB core's
 * function) in order to create a second roothub under xHCI.
 */
static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
{
	int retval;
	struct xhci_hcd *xhci;
	struct hc_driver *driver;
	struct usb_hcd *hcd;

	driver = (struct hc_driver *)id->driver_data;

	/* Prevent runtime suspending between USB-2 and USB-3 initialization */
	pm_runtime_get_noresume(&dev->dev);

	/* Register the USB 2.0 roothub.
	 * FIXME: USB core must know to register the USB 2.0 roothub first.
	 * This is sort of silly, because we could just set the HCD driver flags
	 * to say USB 2.0, but I'm not sure what the implications would be in
	 * the other parts of the HCD code.
	 */
	retval = usb_hcd_pci_probe(dev, id);

	if (retval)
		goto put_runtime_pm;

	/* USB 2.0 roothub is stored in the PCI device now. */
	hcd = dev_get_drvdata(&dev->dev);
	xhci = hcd_to_xhci(hcd);
	xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
				pci_name(dev), hcd);
	if (!xhci->shared_hcd) {
		retval = -ENOMEM;
		goto dealloc_usb2_hcd;
	}

	retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
			IRQF_SHARED);
	if (retval)
		goto put_usb3_hcd;
	/* Roothub already marked as USB 3.0 speed */

	if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
			HCC_MAX_PSA(xhci->hcc_params) >= 4)
		xhci->shared_hcd->can_do_streams = 1;

	if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
		xhci_pme_acpi_rtd3_enable(dev);

	/* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
	pm_runtime_put_noidle(&dev->dev);

	return 0;

put_usb3_hcd:
	usb_put_hcd(xhci->shared_hcd);
dealloc_usb2_hcd:
	usb_hcd_pci_remove(dev);
put_runtime_pm:
	pm_runtime_put_noidle(&dev->dev);
	return retval;
}

static void xhci_pci_remove(struct pci_dev *dev)
{
	struct xhci_hcd *xhci;

	xhci = hcd_to_xhci(pci_get_drvdata(dev));
	xhci->xhc_state |= XHCI_STATE_REMOVING;
	if (xhci->shared_hcd) {
		usb_remove_hcd(xhci->shared_hcd);
		usb_put_hcd(xhci->shared_hcd);
	}

	/* Workaround for spurious wakeups at shutdown with HSW */
	if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
		pci_set_power_state(dev, PCI_D3hot);

	usb_hcd_pci_remove(dev);
}

#ifdef CONFIG_PM
/*
 * In some Intel xHCI controllers, in order to get D3 working,
 * through a vendor specific SSIC CONFIG register at offset 0x883c,
 * SSIC PORT need to be marked as "unused" before putting xHCI
 * into D3. After D3 exit, the SSIC port need to be marked as "used".
 * Without this change, xHCI might not enter D3 state.
 */
static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
{
	struct xhci_hcd	*xhci = hcd_to_xhci(hcd);
	u32 val;
	void __iomem *reg;
	int i;

	for (i = 0; i < SSIC_PORT_NUM; i++) {
		reg = (void __iomem *) xhci->cap_regs +
				SSIC_PORT_CFG2 +
				i * SSIC_PORT_CFG2_OFFSET;

		/* Notify SSIC that SSIC profile programming is not done. */
		val = readl(reg) & ~PROG_DONE;
		writel(val, reg);

		/* Mark SSIC port as unused(suspend) or used(resume) */
		val = readl(reg);
		if (suspend)
			val |= SSIC_PORT_UNUSED;
		else
			val &= ~SSIC_PORT_UNUSED;
		writel(val, reg);

		/* Notify SSIC that SSIC profile programming is done */
		val = readl(reg) | PROG_DONE;
		writel(val, reg);
		readl(reg);
	}
}

/*
 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
 */
static void xhci_pme_quirk(struct usb_hcd *hcd)
{
	struct xhci_hcd	*xhci = hcd_to_xhci(hcd);
	void __iomem *reg;
	u32 val;

	reg = (void __iomem *) xhci->cap_regs + 0x80a4;
	val = readl(reg);
	writel(val | BIT(28), reg);
	readl(reg);
}

static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
{
	struct xhci_hcd	*xhci = hcd_to_xhci(hcd);
	struct pci_dev		*pdev = to_pci_dev(hcd->self.controller);
	int			ret;

	/*
	 * Systems with the TI redriver that loses port status change events
	 * need to have the registers polled during D3, so avoid D3cold.
	 */
	if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
		pci_d3cold_disable(pdev);

	if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
		xhci_pme_quirk(hcd);

	if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
		xhci_ssic_port_unused_quirk(hcd, true);

	ret = xhci_suspend(xhci, do_wakeup);
	if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
		xhci_ssic_port_unused_quirk(hcd, false);

	return ret;
}

static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
{
	struct xhci_hcd		*xhci = hcd_to_xhci(hcd);
	struct pci_dev		*pdev = to_pci_dev(hcd->self.controller);
	int			retval = 0;

	/* The BIOS on systems with the Intel Panther Point chipset may or may
	 * not support xHCI natively.  That means that during system resume, it
	 * may switch the ports back to EHCI so that users can use their
	 * keyboard to select a kernel from GRUB after resume from hibernate.
	 *
	 * The BIOS is supposed to remember whether the OS had xHCI ports
	 * enabled before resume, and switch the ports back to xHCI when the
	 * BIOS/OS semaphore is written, but we all know we can't trust BIOS
	 * writers.
	 *
	 * Unconditionally switch the ports back to xHCI after a system resume.
	 * It should not matter whether the EHCI or xHCI controller is
	 * resumed first. It's enough to do the switchover in xHCI because
	 * USB core won't notice anything as the hub driver doesn't start
	 * running again until after all the devices (including both EHCI and
	 * xHCI host controllers) have been resumed.
	 */

	if (pdev->vendor == PCI_VENDOR_ID_INTEL)
		usb_enable_intel_xhci_ports(pdev);

	if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
		xhci_ssic_port_unused_quirk(hcd, false);

	if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
		xhci_pme_quirk(hcd);

	retval = xhci_resume(xhci, hibernated);
	return retval;
}
#endif /* CONFIG_PM */

/*-------------------------------------------------------------------------*/

/* PCI driver selection metadata; PCI hotplugging uses this */
static const struct pci_device_id pci_ids[] = { {
	/* handle any USB 3.0 xHCI controller */
	PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
	.driver_data =	(unsigned long) &xhci_pci_hc_driver,
	},
	{ /* end: all zeroes */ }
};
MODULE_DEVICE_TABLE(pci, pci_ids);

/* pci driver glue; this is a "new style" PCI driver module */
static struct pci_driver xhci_pci_driver = {
	.name =		(char *) hcd_name,
	.id_table =	pci_ids,

	.probe =	xhci_pci_probe,
	.remove =	xhci_pci_remove,
	/* suspend and resume implemented later */

	.shutdown = 	usb_hcd_pci_shutdown,
#ifdef CONFIG_PM
	.driver = {
		.pm = &usb_hcd_pci_pm_ops
	},
#endif
};

static int __init xhci_pci_init(void)
{
	xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
#ifdef CONFIG_PM
	xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
	xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
#endif
	return pci_register_driver(&xhci_pci_driver);
}
module_init(xhci_pci_init);

static void __exit xhci_pci_exit(void)
{
	pci_unregister_driver(&xhci_pci_driver);
}
module_exit(xhci_pci_exit);

MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
66d4eadd SS	1	/*
	2	* xHCI host controller driver PCI Bus Glue.
	3	*
	4	* Copyright (C) 2008 Intel Corp.
	5	*
	6	* Author: Sarah Sharp
	7	* Some code borrowed from the Linux EHCI driver.
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*
	13	* This program is distributed in the hope that it will be useful, but
	14	* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	15	* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	16	* for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software Foundation,
	20	* Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	21	*/
	22
	23	#include <linux/pci.h>
7fc2a616	24	#include <linux/slab.h>
6eb0de82	25	#include <linux/module.h>
c3c5819a	26	#include <linux/acpi.h>
66d4eadd SS	27
66d4eadd SS	28	#include "xhci.h"
4bdfe4c3	29	#include "xhci-trace.h"
66d4eadd	30
fa895377 LB	31	#define SSIC_PORT_NUM 2
	32	#define SSIC_PORT_CFG2 0x880c
	33	#define SSIC_PORT_CFG2_OFFSET 0x30
abce329c RM	34	#define PROG_DONE (1 << 30)
	35	#define SSIC_PORT_UNUSED (1 << 31)
	36
ac9d8fe7 SS	37	/* Device for a quirk */
	38	#define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73
	39	#define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000
d95815ba	40	#define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009
bba18e33	41	#define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400
ac9d8fe7	42
c877b3b2	43	#define PCI_VENDOR_ID_ETRON 0x1b6f
170625e9	44	#define PCI_DEVICE_ID_EJ168 0x7023
c877b3b2	45
638298dc TI	46	#define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31
638298dc TI	47	#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31
4c39135a	48	#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1
b8cb91e0 MN	49	#define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5
	50	#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f
	51	#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f
ccc04afb	52	#define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8
0d46faca	53	#define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8
346e9973	54	#define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8
a0c16630	55	#define PCI_DEVICE_ID_INTEL_DNV_XHCI 0x19d0
638298dc	56
dec08194 JC	57	#define PCI_DEVICE_ID_AMD_PROMONTORYA_4 0x43b9
	58	#define PCI_DEVICE_ID_AMD_PROMONTORYA_3 0x43ba
	59	#define PCI_DEVICE_ID_AMD_PROMONTORYA_2 0x43bb
	60	#define PCI_DEVICE_ID_AMD_PROMONTORYA_1 0x43bc
	61
9da5a109 JC	62	#define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142
9da5a109 JC	63
66d4eadd SS	64	static const char hcd_name[] = "xhci_hcd";
66d4eadd SS	65
1885d9a3 AB	66	static struct hc_driver __read_mostly xhci_pci_hc_driver;
1885d9a3 AB	67
cd33a321 RQ	68	static int xhci_pci_setup(struct usb_hcd *hcd);
	69
	70	static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
cd33a321 RQ	71	.reset = xhci_pci_setup,
	72	};
	73
66d4eadd SS	74	/* called after powerup, by probe or system-pm "wakeup" */
	75	static int xhci_pci_reinit(struct xhci_hcd xhci, struct pci_dev pdev)
	76	{
	77	/*
	78	* TODO: Implement finding debug ports later.
	79	* TODO: see if there are any quirks that need to be added to handle
	80	* new extended capabilities.
	81	*/
	82
	83	/* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
	84	if (!pci_set_mwi(pdev))
	85	xhci_dbg(xhci, "MWI active\n");
	86
	87	xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
	88	return 0;
	89	}
	90
da3c9c4f SAS	91	static void xhci_pci_quirks(struct device dev, struct xhci_hcd xhci)
	92	{
	93	struct pci_dev *pdev = to_pci_dev(dev);
	94
ac9d8fe7 SS	95	/* Look for vendor-specific quirks */
ac9d8fe7 SS	96	if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
bba18e33 SS	97	(pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK \|\|
	98	pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
	99	if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
	100	pdev->revision == 0x0) {
ac9d8fe7	101	xhci->quirks \|= XHCI_RESET_EP_QUIRK;
4bdfe4c3 XR	102	xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
	103	"QUIRK: Fresco Logic xHC needs configure"
	104	" endpoint cmd after reset endpoint");
f5182b41	105	}
455f5892 ON	106	if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
	107	pdev->revision == 0x4) {
	108	xhci->quirks \|= XHCI_SLOW_SUSPEND;
	109	xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
	110	"QUIRK: Fresco Logic xHC revision %u"
	111	"must be suspended extra slowly",
	112	pdev->revision);
	113	}
7f5c4d63 HG	114	if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
7f5c4d63 HG	115	xhci->quirks \|= XHCI_BROKEN_STREAMS;
f5182b41 SS	116	/* Fresco Logic confirms: all revisions of this chip do not
	117	* support MSI, even though some of them claim to in their PCI
	118	* capabilities.
	119	*/
	120	xhci->quirks \|= XHCI_BROKEN_MSI;
4bdfe4c3 XR	121	xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
	122	"QUIRK: Fresco Logic revision %u "
	123	"has broken MSI implementation",
f5182b41	124	pdev->revision);
1530bbc6	125	xhci->quirks \|= XHCI_TRUST_TX_LENGTH;
ac9d8fe7	126	}
f5182b41	127
d95815ba HG	128	if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
	129	pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009)
	130	xhci->quirks \|= XHCI_BROKEN_STREAMS;
	131
0238634d SS	132	if (pdev->vendor == PCI_VENDOR_ID_NEC)
0238634d SS	133	xhci->quirks \|= XHCI_NEC_HOST;
ac9d8fe7	134
7e393a83 AX	135	if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
	136	xhci->quirks \|= XHCI_AMD_0x96_HOST;
	137
c41136b0 AX	138	/* AMD PLL quirk */
	139	if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
	140	xhci->quirks \|= XHCI_AMD_PLL_FIX;
2597fe99 HR	141
	142	if (pdev->vendor == PCI_VENDOR_ID_AMD)
	143	xhci->quirks \|= XHCI_TRUST_TX_LENGTH;
	144
dec08194 JC	145	if ((pdev->vendor == PCI_VENDOR_ID_AMD) &&
	146	((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) \|\|
	147	(pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) \|\|
	148	(pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) \|\|
	149	(pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1)))
	150	xhci->quirks \|= XHCI_U2_DISABLE_WAKE;
	151
e3567d2c SS	152	if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
	153	xhci->quirks \|= XHCI_LPM_SUPPORT;
	154	xhci->quirks \|= XHCI_INTEL_HOST;
227a4fd8	155	xhci->quirks \|= XHCI_AVOID_BEI;
e3567d2c	156	}
ad808333 SS	157	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
ad808333 SS	158	pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
2cf95c18 SS	159	xhci->quirks \|= XHCI_EP_LIMIT_QUIRK;
2cf95c18 SS	160	xhci->limit_active_eps = 64;
86cc558e	161	xhci->quirks \|= XHCI_SW_BW_CHECKING;
e95829f4 SS	162	/*
	163	* PPT desktop boards DH77EB and DH77DF will power back on after
	164	* a few seconds of being shutdown. The fix for this is to
	165	* switch the ports from xHCI to EHCI on shutdown. We can't use
	166	* DMI information to find those particular boards (since each
	167	* vendor will change the board name), so we have to key off all
	168	* PPT chipsets.
	169	*/
	170	xhci->quirks \|= XHCI_SPURIOUS_REBOOT;
ad808333	171	}
0a939993	172	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
4c39135a MN	173	(pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI \|\|
4c39135a MN	174	pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
c09ec25d	175	xhci->quirks \|= XHCI_SPURIOUS_REBOOT;
fd7cd061	176	xhci->quirks \|= XHCI_SPURIOUS_WAKEUP;
638298dc	177	}
b8cb91e0 MN	178	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
	179	(pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI \|\|
	180	pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI \|\|
ccc04afb	181	pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI \|\|
0d46faca	182	pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI \|\|
6c97cfc1	183	pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI \|\|
a0c16630 MN	184	pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI \|\|
a0c16630 MN	185	pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI)) {
b8cb91e0 MN	186	xhci->quirks \|= XHCI_PME_STUCK_QUIRK;
b8cb91e0 MN	187	}
7e70cbff LB	188	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
	189	pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) {
	190	xhci->quirks \|= XHCI_SSIC_PORT_UNUSED;
	191	}
346e9973 MN	192	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
346e9973 MN	193	(pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI \|\|
a0c16630 MN	194	pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI \|\|
a0c16630 MN	195	pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI))
346e9973 MN	196	xhci->quirks \|= XHCI_MISSING_CAS;
346e9973 MN	197
c877b3b2	198	if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
170625e9	199	pdev->device == PCI_DEVICE_ID_EJ168) {
c877b3b2	200	xhci->quirks \|= XHCI_RESET_ON_RESUME;
5cb7df2b	201	xhci->quirks \|= XHCI_TRUST_TX_LENGTH;
8f873c1f	202	xhci->quirks \|= XHCI_BROKEN_STREAMS;
c877b3b2	203	}
1aa9578c	204	if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
6db249eb	205	pdev->device == 0x0015)
1aa9578c	206	xhci->quirks \|= XHCI_RESET_ON_RESUME;
457a4f61 EF	207	if (pdev->vendor == PCI_VENDOR_ID_VIA)
457a4f61 EF	208	xhci->quirks \|= XHCI_RESET_ON_RESUME;
85f4e45b	209
e21eba05 HG	210	/* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
	211	if (pdev->vendor == PCI_VENDOR_ID_VIA &&
	212	pdev->device == 0x3432)
	213	xhci->quirks \|= XHCI_BROKEN_STREAMS;
	214
2391eacb HG	215	if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
	216	pdev->device == 0x1042)
	217	xhci->quirks \|= XHCI_BROKEN_STREAMS;
d2f48f05 CL	218	if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
	219	pdev->device == 0x1142)
	220	xhci->quirks \|= XHCI_TRUST_TX_LENGTH;
2391eacb	221
9da5a109 JC	222	if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
	223	pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI)
	224	xhci->quirks \|= XHCI_ASMEDIA_MODIFY_FLOWCONTROL;
	225
69307ccb RQ	226	if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241)
	227	xhci->quirks \|= XHCI_LIMIT_ENDPOINT_INTERVAL_7;
	228
85f4e45b ON	229	if (xhci->quirks & XHCI_RESET_ON_RESUME)
	230	xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
	231	"QUIRK: Resetting on resume");
da3c9c4f	232	}
c41136b0	233
c3c5819a MN	234	#ifdef CONFIG_ACPI
	235	static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
	236	{
94116f81 AS	237	static const guid_t intel_dsm_guid =
	238	GUID_INIT(0xac340cb7, 0xe901, 0x45bf,
	239	0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23);
84ed9152 MW	240	union acpi_object *obj;
84ed9152 MW	241
94116f81	242	obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1,
84ed9152 MW	243	NULL);
84ed9152 MW	244	ACPI_FREE(obj);
c3c5819a MN	245	}
c3c5819a MN	246	#else
84ed9152	247	static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
c3c5819a MN	248	#endif /* CONFIG_ACPI */
c3c5819a MN	249
da3c9c4f SAS	250	/* called during probe() after chip reset completes */
	251	static int xhci_pci_setup(struct usb_hcd *hcd)
	252	{
	253	struct xhci_hcd *xhci;
	254	struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
	255	int retval;
66d4eadd	256
b50107bb MN	257	xhci = hcd_to_xhci(hcd);
	258	if (!xhci->sbrn)
	259	pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
	260
da3c9c4f	261	retval = xhci_gen_setup(hcd, xhci_pci_quirks);
66d4eadd	262	if (retval)
da3c9c4f	263	return retval;
006d5820	264
da3c9c4f SAS	265	if (!usb_hcd_is_primary_hcd(hcd))
da3c9c4f SAS	266	return 0;
66d4eadd	267
66d4eadd SS	268	xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
	269
	270	/* Find any debug ports */
989bad11	271	return xhci_pci_reinit(xhci, pdev);
b02d0ed6 SS	272	}
b02d0ed6 SS	273
f6ff0ac8 SS	274	/*
	275	* We need to register our own PCI probe function (instead of the USB core's
	276	* function) in order to create a second roothub under xHCI.
	277	*/
	278	static int xhci_pci_probe(struct pci_dev dev, const struct pci_device_id id)
	279	{
	280	int retval;
	281	struct xhci_hcd *xhci;
	282	struct hc_driver *driver;
	283	struct usb_hcd *hcd;
	284
	285	driver = (struct hc_driver *)id->driver_data;
bcffae77 MN	286
	287	/* Prevent runtime suspending between USB-2 and USB-3 initialization */
	288	pm_runtime_get_noresume(&dev->dev);
	289
f6ff0ac8 SS	290	/* Register the USB 2.0 roothub.
	291	* FIXME: USB core must know to register the USB 2.0 roothub first.
	292	* This is sort of silly, because we could just set the HCD driver flags
	293	* to say USB 2.0, but I'm not sure what the implications would be in
	294	* the other parts of the HCD code.
	295	*/
	296	retval = usb_hcd_pci_probe(dev, id);
	297
	298	if (retval)
bcffae77	299	goto put_runtime_pm;
f6ff0ac8 SS	300
	301	/* USB 2.0 roothub is stored in the PCI device now. */
	302	hcd = dev_get_drvdata(&dev->dev);
	303	xhci = hcd_to_xhci(hcd);
	304	xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
	305	pci_name(dev), hcd);
	306	if (!xhci->shared_hcd) {
	307	retval = -ENOMEM;
	308	goto dealloc_usb2_hcd;
	309	}
	310
f6ff0ac8	311	retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
b5dd18d8	312	IRQF_SHARED);
f6ff0ac8 SS	313	if (retval)
	314	goto put_usb3_hcd;
	315	/* Roothub already marked as USB 3.0 speed */
3b3db026	316
8f873c1f HG	317	if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
8f873c1f HG	318	HCC_MAX_PSA(xhci->hcc_params) >= 4)
14aec589 ON	319	xhci->shared_hcd->can_do_streams = 1;
14aec589 ON	320
c3c5819a MN	321	if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
	322	xhci_pme_acpi_rtd3_enable(dev);
	323
bcffae77 MN	324	/* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
	325	pm_runtime_put_noidle(&dev->dev);
	326
f6ff0ac8 SS	327	return 0;
	328
	329	put_usb3_hcd:
	330	usb_put_hcd(xhci->shared_hcd);
	331	dealloc_usb2_hcd:
	332	usb_hcd_pci_remove(dev);
bcffae77 MN	333	put_runtime_pm:
bcffae77 MN	334	pm_runtime_put_noidle(&dev->dev);
f6ff0ac8 SS	335	return retval;
	336	}
	337
b02d0ed6 SS	338	static void xhci_pci_remove(struct pci_dev *dev)
	339	{
	340	struct xhci_hcd *xhci;
	341
	342	xhci = hcd_to_xhci(pci_get_drvdata(dev));
98d74f9c	343	xhci->xhc_state \|= XHCI_STATE_REMOVING;
f6ff0ac8 SS	344	if (xhci->shared_hcd) {
	345	usb_remove_hcd(xhci->shared_hcd);
	346	usb_put_hcd(xhci->shared_hcd);
	347	}
638298dc TI	348
	349	/* Workaround for spurious wakeups at shutdown with HSW */
	350	if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
	351	pci_set_power_state(dev, PCI_D3hot);
f1f6d9a8 MN	352
f1f6d9a8 MN	353	usb_hcd_pci_remove(dev);
66d4eadd SS	354	}
66d4eadd SS	355
5535b1d5	356	#ifdef CONFIG_PM
2b7627b7 TB	357	/*
	358	* In some Intel xHCI controllers, in order to get D3 working,
	359	* through a vendor specific SSIC CONFIG register at offset 0x883c,
	360	* SSIC PORT need to be marked as "unused" before putting xHCI
	361	* into D3. After D3 exit, the SSIC port need to be marked as "used".
	362	* Without this change, xHCI might not enter D3 state.
2b7627b7	363	*/
7e70cbff	364	static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
2b7627b7 TB	365	{
2b7627b7 TB	366	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2b7627b7 TB	367	u32 val;
2b7627b7 TB	368	void __iomem *reg;
fa895377	369	int i;
2b7627b7	370
7e70cbff LB	371	for (i = 0; i < SSIC_PORT_NUM; i++) {
	372	reg = (void __iomem *) xhci->cap_regs +
	373	SSIC_PORT_CFG2 +
	374	i * SSIC_PORT_CFG2_OFFSET;
	375
	376	/* Notify SSIC that SSIC profile programming is not done. */
	377	val = readl(reg) & ~PROG_DONE;
	378	writel(val, reg);
	379
	380	/* Mark SSIC port as unused(suspend) or used(resume) */
	381	val = readl(reg);
	382	if (suspend)
	383	val \|= SSIC_PORT_UNUSED;
	384	else
	385	val &= ~SSIC_PORT_UNUSED;
	386	writel(val, reg);
	387
	388	/* Notify SSIC that SSIC profile programming is done */
	389	val = readl(reg) \| PROG_DONE;
	390	writel(val, reg);
	391	readl(reg);
2b7627b7	392	}
7e70cbff LB	393	}
	394
	395	/*
	396	* Make sure PME works on some Intel xHCI controllers by writing 1 to clear
	397	* the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
	398	*/
	399	static void xhci_pme_quirk(struct usb_hcd *hcd)
	400	{
	401	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
	402	void __iomem *reg;
	403	u32 val;
2b7627b7 TB	404
	405	reg = (void __iomem *) xhci->cap_regs + 0x80a4;
	406	val = readl(reg);
	407	writel(val \| BIT(28), reg);
	408	readl(reg);
	409	}
	410
5535b1d5 AX	411	static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
	412	{
	413	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
c3897aa5	414	struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
92149c93	415	int ret;
c3897aa5 SS	416
	417	/*
	418	* Systems with the TI redriver that loses port status change events
	419	* need to have the registers polled during D3, so avoid D3cold.
	420	*/
e1cd9727	421	if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
9d26d3a8	422	pci_d3cold_disable(pdev);
5535b1d5	423
b8cb91e0	424	if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
7e70cbff LB	425	xhci_pme_quirk(hcd);
	426
	427	if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
	428	xhci_ssic_port_unused_quirk(hcd, true);
b8cb91e0	429
92149c93 LB	430	ret = xhci_suspend(xhci, do_wakeup);
	431	if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
	432	xhci_ssic_port_unused_quirk(hcd, false);
	433
	434	return ret;
5535b1d5 AX	435	}
	436
	437	static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
	438	{
	439	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
69e848c2	440	struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
5535b1d5 AX	441	int retval = 0;
5535b1d5 AX	442
69e848c2 SS	443	/* The BIOS on systems with the Intel Panther Point chipset may or may
	444	* not support xHCI natively. That means that during system resume, it
	445	* may switch the ports back to EHCI so that users can use their
	446	* keyboard to select a kernel from GRUB after resume from hibernate.
	447	*
	448	* The BIOS is supposed to remember whether the OS had xHCI ports
	449	* enabled before resume, and switch the ports back to xHCI when the
	450	* BIOS/OS semaphore is written, but we all know we can't trust BIOS
	451	* writers.
	452	*
	453	* Unconditionally switch the ports back to xHCI after a system resume.
26b76798 MN	454	* It should not matter whether the EHCI or xHCI controller is
	455	* resumed first. It's enough to do the switchover in xHCI because
	456	* USB core won't notice anything as the hub driver doesn't start
	457	* running again until after all the devices (including both EHCI and
	458	* xHCI host controllers) have been resumed.
69e848c2	459	*/
26b76798 MN	460
	461	if (pdev->vendor == PCI_VENDOR_ID_INTEL)
	462	usb_enable_intel_xhci_ports(pdev);
69e848c2	463
7e70cbff LB	464	if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
	465	xhci_ssic_port_unused_quirk(hcd, false);
	466
b8cb91e0	467	if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
7e70cbff	468	xhci_pme_quirk(hcd);
b8cb91e0	469
5535b1d5 AX	470	retval = xhci_resume(xhci, hibernated);
	471	return retval;
	472	}
	473	#endif /* CONFIG_PM */
	474
66d4eadd SS	475	/-------------------------------------------------------------------------/
	476
	477	/* PCI driver selection metadata; PCI hotplugging uses this */
	478	static const struct pci_device_id pci_ids[] = { {
	479	/* handle any USB 3.0 xHCI controller */
	480	PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
	481	.driver_data = (unsigned long) &xhci_pci_hc_driver,
	482	},
	483	{ /* end: all zeroes */ }
	484	};
	485	MODULE_DEVICE_TABLE(pci, pci_ids);
	486
	487	/* pci driver glue; this is a "new style" PCI driver module */
	488	static struct pci_driver xhci_pci_driver = {
	489	.name = (char *) hcd_name,
	490	.id_table = pci_ids,
	491
f6ff0ac8	492	.probe = xhci_pci_probe,
b02d0ed6	493	.remove = xhci_pci_remove,
66d4eadd SS	494	/* suspend and resume implemented later */
	495
	496	.shutdown = usb_hcd_pci_shutdown,
f875fdbf	497	#ifdef CONFIG_PM
5535b1d5 AX	498	.driver = {
	499	.pm = &usb_hcd_pci_pm_ops
	500	},
	501	#endif
66d4eadd SS	502	};
66d4eadd SS	503
29e409f0	504	static int __init xhci_pci_init(void)
66d4eadd	505	{
cd33a321	506	xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
1885d9a3 AB	507	#ifdef CONFIG_PM
	508	xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
	509	xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
	510	#endif
66d4eadd SS	511	return pci_register_driver(&xhci_pci_driver);
66d4eadd SS	512	}
29e409f0	513	module_init(xhci_pci_init);
66d4eadd	514
29e409f0	515	static void __exit xhci_pci_exit(void)
66d4eadd SS	516	{
	517	pci_unregister_driver(&xhci_pci_driver);
	518	}
29e409f0 AB	519	module_exit(xhci_pci_exit);
	520
	521	MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
	522	MODULE_LICENSE("GPL");