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Commit | Line | Data |
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66d4eadd SS |
1 | /* |
2 | * xHCI host controller driver PCI Bus Glue. | |
3 | * | |
4 | * Copyright (C) 2008 Intel Corp. | |
5 | * | |
6 | * Author: Sarah Sharp | |
7 | * Some code borrowed from the Linux EHCI driver. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | * for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software Foundation, | |
20 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
23 | #include <linux/pci.h> | |
7fc2a616 | 24 | #include <linux/slab.h> |
6eb0de82 | 25 | #include <linux/module.h> |
66d4eadd SS |
26 | |
27 | #include "xhci.h" | |
4bdfe4c3 | 28 | #include "xhci-trace.h" |
66d4eadd | 29 | |
ac9d8fe7 SS |
30 | /* Device for a quirk */ |
31 | #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73 | |
32 | #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000 | |
bba18e33 | 33 | #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400 |
ac9d8fe7 | 34 | |
c877b3b2 | 35 | #define PCI_VENDOR_ID_ETRON 0x1b6f |
170625e9 | 36 | #define PCI_DEVICE_ID_EJ168 0x7023 |
c877b3b2 | 37 | |
638298dc TI |
38 | #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31 |
39 | #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31 | |
40 | ||
66d4eadd SS |
41 | static const char hcd_name[] = "xhci_hcd"; |
42 | ||
1885d9a3 AB |
43 | static struct hc_driver __read_mostly xhci_pci_hc_driver; |
44 | ||
66d4eadd SS |
45 | /* called after powerup, by probe or system-pm "wakeup" */ |
46 | static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev) | |
47 | { | |
48 | /* | |
49 | * TODO: Implement finding debug ports later. | |
50 | * TODO: see if there are any quirks that need to be added to handle | |
51 | * new extended capabilities. | |
52 | */ | |
53 | ||
54 | /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ | |
55 | if (!pci_set_mwi(pdev)) | |
56 | xhci_dbg(xhci, "MWI active\n"); | |
57 | ||
58 | xhci_dbg(xhci, "Finished xhci_pci_reinit\n"); | |
59 | return 0; | |
60 | } | |
61 | ||
da3c9c4f SAS |
62 | static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) |
63 | { | |
64 | struct pci_dev *pdev = to_pci_dev(dev); | |
65 | ||
ac9d8fe7 SS |
66 | /* Look for vendor-specific quirks */ |
67 | if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && | |
bba18e33 SS |
68 | (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK || |
69 | pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) { | |
70 | if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && | |
71 | pdev->revision == 0x0) { | |
ac9d8fe7 | 72 | xhci->quirks |= XHCI_RESET_EP_QUIRK; |
4bdfe4c3 XR |
73 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
74 | "QUIRK: Fresco Logic xHC needs configure" | |
75 | " endpoint cmd after reset endpoint"); | |
f5182b41 | 76 | } |
455f5892 ON |
77 | if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && |
78 | pdev->revision == 0x4) { | |
79 | xhci->quirks |= XHCI_SLOW_SUSPEND; | |
80 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, | |
81 | "QUIRK: Fresco Logic xHC revision %u" | |
82 | "must be suspended extra slowly", | |
83 | pdev->revision); | |
84 | } | |
f5182b41 SS |
85 | /* Fresco Logic confirms: all revisions of this chip do not |
86 | * support MSI, even though some of them claim to in their PCI | |
87 | * capabilities. | |
88 | */ | |
89 | xhci->quirks |= XHCI_BROKEN_MSI; | |
4bdfe4c3 XR |
90 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
91 | "QUIRK: Fresco Logic revision %u " | |
92 | "has broken MSI implementation", | |
f5182b41 | 93 | pdev->revision); |
1530bbc6 | 94 | xhci->quirks |= XHCI_TRUST_TX_LENGTH; |
ac9d8fe7 | 95 | } |
f5182b41 | 96 | |
0238634d SS |
97 | if (pdev->vendor == PCI_VENDOR_ID_NEC) |
98 | xhci->quirks |= XHCI_NEC_HOST; | |
ac9d8fe7 | 99 | |
7e393a83 AX |
100 | if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96) |
101 | xhci->quirks |= XHCI_AMD_0x96_HOST; | |
102 | ||
c41136b0 AX |
103 | /* AMD PLL quirk */ |
104 | if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info()) | |
105 | xhci->quirks |= XHCI_AMD_PLL_FIX; | |
2597fe99 HR |
106 | |
107 | if (pdev->vendor == PCI_VENDOR_ID_AMD) | |
108 | xhci->quirks |= XHCI_TRUST_TX_LENGTH; | |
109 | ||
e3567d2c SS |
110 | if (pdev->vendor == PCI_VENDOR_ID_INTEL) { |
111 | xhci->quirks |= XHCI_LPM_SUPPORT; | |
112 | xhci->quirks |= XHCI_INTEL_HOST; | |
113 | } | |
ad808333 SS |
114 | if (pdev->vendor == PCI_VENDOR_ID_INTEL && |
115 | pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) { | |
2cf95c18 SS |
116 | xhci->quirks |= XHCI_EP_LIMIT_QUIRK; |
117 | xhci->limit_active_eps = 64; | |
86cc558e | 118 | xhci->quirks |= XHCI_SW_BW_CHECKING; |
e95829f4 SS |
119 | /* |
120 | * PPT desktop boards DH77EB and DH77DF will power back on after | |
121 | * a few seconds of being shutdown. The fix for this is to | |
122 | * switch the ports from xHCI to EHCI on shutdown. We can't use | |
123 | * DMI information to find those particular boards (since each | |
124 | * vendor will change the board name), so we have to key off all | |
125 | * PPT chipsets. | |
126 | */ | |
127 | xhci->quirks |= XHCI_SPURIOUS_REBOOT; | |
80fab3b2 | 128 | xhci->quirks |= XHCI_AVOID_BEI; |
ad808333 | 129 | } |
0a939993 DT |
130 | if (pdev->vendor == PCI_VENDOR_ID_INTEL && |
131 | pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI) { | |
c09ec25d | 132 | xhci->quirks |= XHCI_SPURIOUS_REBOOT; |
638298dc | 133 | } |
c877b3b2 | 134 | if (pdev->vendor == PCI_VENDOR_ID_ETRON && |
170625e9 | 135 | pdev->device == PCI_DEVICE_ID_EJ168) { |
c877b3b2 | 136 | xhci->quirks |= XHCI_RESET_ON_RESUME; |
5cb7df2b | 137 | xhci->quirks |= XHCI_TRUST_TX_LENGTH; |
8f873c1f | 138 | xhci->quirks |= XHCI_BROKEN_STREAMS; |
c877b3b2 | 139 | } |
1aa9578c | 140 | if (pdev->vendor == PCI_VENDOR_ID_RENESAS && |
6db249eb | 141 | pdev->device == 0x0015) |
1aa9578c | 142 | xhci->quirks |= XHCI_RESET_ON_RESUME; |
457a4f61 EF |
143 | if (pdev->vendor == PCI_VENDOR_ID_VIA) |
144 | xhci->quirks |= XHCI_RESET_ON_RESUME; | |
85f4e45b | 145 | |
e21eba05 HG |
146 | /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */ |
147 | if (pdev->vendor == PCI_VENDOR_ID_VIA && | |
148 | pdev->device == 0x3432) | |
149 | xhci->quirks |= XHCI_BROKEN_STREAMS; | |
150 | ||
2391eacb HG |
151 | if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && |
152 | pdev->device == 0x1042) | |
153 | xhci->quirks |= XHCI_BROKEN_STREAMS; | |
154 | ||
85f4e45b ON |
155 | if (xhci->quirks & XHCI_RESET_ON_RESUME) |
156 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, | |
157 | "QUIRK: Resetting on resume"); | |
da3c9c4f | 158 | } |
c41136b0 | 159 | |
da3c9c4f SAS |
160 | /* called during probe() after chip reset completes */ |
161 | static int xhci_pci_setup(struct usb_hcd *hcd) | |
162 | { | |
163 | struct xhci_hcd *xhci; | |
164 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); | |
165 | int retval; | |
66d4eadd | 166 | |
da3c9c4f | 167 | retval = xhci_gen_setup(hcd, xhci_pci_quirks); |
66d4eadd | 168 | if (retval) |
da3c9c4f | 169 | return retval; |
006d5820 | 170 | |
da3c9c4f SAS |
171 | xhci = hcd_to_xhci(hcd); |
172 | if (!usb_hcd_is_primary_hcd(hcd)) | |
173 | return 0; | |
66d4eadd SS |
174 | |
175 | pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn); | |
176 | xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn); | |
177 | ||
178 | /* Find any debug ports */ | |
b02d0ed6 SS |
179 | retval = xhci_pci_reinit(xhci, pdev); |
180 | if (!retval) | |
181 | return retval; | |
182 | ||
b02d0ed6 SS |
183 | kfree(xhci); |
184 | return retval; | |
185 | } | |
186 | ||
f6ff0ac8 SS |
187 | /* |
188 | * We need to register our own PCI probe function (instead of the USB core's | |
189 | * function) in order to create a second roothub under xHCI. | |
190 | */ | |
191 | static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) | |
192 | { | |
193 | int retval; | |
194 | struct xhci_hcd *xhci; | |
195 | struct hc_driver *driver; | |
196 | struct usb_hcd *hcd; | |
197 | ||
198 | driver = (struct hc_driver *)id->driver_data; | |
bcffae77 MN |
199 | |
200 | /* Prevent runtime suspending between USB-2 and USB-3 initialization */ | |
201 | pm_runtime_get_noresume(&dev->dev); | |
202 | ||
f6ff0ac8 SS |
203 | /* Register the USB 2.0 roothub. |
204 | * FIXME: USB core must know to register the USB 2.0 roothub first. | |
205 | * This is sort of silly, because we could just set the HCD driver flags | |
206 | * to say USB 2.0, but I'm not sure what the implications would be in | |
207 | * the other parts of the HCD code. | |
208 | */ | |
209 | retval = usb_hcd_pci_probe(dev, id); | |
210 | ||
211 | if (retval) | |
bcffae77 | 212 | goto put_runtime_pm; |
f6ff0ac8 SS |
213 | |
214 | /* USB 2.0 roothub is stored in the PCI device now. */ | |
215 | hcd = dev_get_drvdata(&dev->dev); | |
216 | xhci = hcd_to_xhci(hcd); | |
217 | xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev, | |
218 | pci_name(dev), hcd); | |
219 | if (!xhci->shared_hcd) { | |
220 | retval = -ENOMEM; | |
221 | goto dealloc_usb2_hcd; | |
222 | } | |
223 | ||
224 | /* Set the xHCI pointer before xhci_pci_setup() (aka hcd_driver.reset) | |
225 | * is called by usb_add_hcd(). | |
226 | */ | |
227 | *((struct xhci_hcd **) xhci->shared_hcd->hcd_priv) = xhci; | |
228 | ||
229 | retval = usb_add_hcd(xhci->shared_hcd, dev->irq, | |
b5dd18d8 | 230 | IRQF_SHARED); |
f6ff0ac8 SS |
231 | if (retval) |
232 | goto put_usb3_hcd; | |
233 | /* Roothub already marked as USB 3.0 speed */ | |
3b3db026 | 234 | |
8f873c1f HG |
235 | if (!(xhci->quirks & XHCI_BROKEN_STREAMS) && |
236 | HCC_MAX_PSA(xhci->hcc_params) >= 4) | |
14aec589 ON |
237 | xhci->shared_hcd->can_do_streams = 1; |
238 | ||
bcffae77 MN |
239 | /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */ |
240 | pm_runtime_put_noidle(&dev->dev); | |
241 | ||
f6ff0ac8 SS |
242 | return 0; |
243 | ||
244 | put_usb3_hcd: | |
245 | usb_put_hcd(xhci->shared_hcd); | |
246 | dealloc_usb2_hcd: | |
247 | usb_hcd_pci_remove(dev); | |
bcffae77 MN |
248 | put_runtime_pm: |
249 | pm_runtime_put_noidle(&dev->dev); | |
f6ff0ac8 SS |
250 | return retval; |
251 | } | |
252 | ||
b02d0ed6 SS |
253 | static void xhci_pci_remove(struct pci_dev *dev) |
254 | { | |
255 | struct xhci_hcd *xhci; | |
256 | ||
257 | xhci = hcd_to_xhci(pci_get_drvdata(dev)); | |
f6ff0ac8 SS |
258 | if (xhci->shared_hcd) { |
259 | usb_remove_hcd(xhci->shared_hcd); | |
260 | usb_put_hcd(xhci->shared_hcd); | |
261 | } | |
b02d0ed6 | 262 | usb_hcd_pci_remove(dev); |
638298dc TI |
263 | |
264 | /* Workaround for spurious wakeups at shutdown with HSW */ | |
265 | if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) | |
266 | pci_set_power_state(dev, PCI_D3hot); | |
267 | ||
b02d0ed6 | 268 | kfree(xhci); |
66d4eadd SS |
269 | } |
270 | ||
5535b1d5 AX |
271 | #ifdef CONFIG_PM |
272 | static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) | |
273 | { | |
274 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
c3897aa5 SS |
275 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); |
276 | ||
277 | /* | |
278 | * Systems with the TI redriver that loses port status change events | |
279 | * need to have the registers polled during D3, so avoid D3cold. | |
280 | */ | |
e1cd9727 | 281 | if (xhci->quirks & XHCI_COMP_MODE_QUIRK) |
c3897aa5 | 282 | pdev->no_d3cold = true; |
5535b1d5 | 283 | |
a1377e53 | 284 | return xhci_suspend(xhci, do_wakeup); |
5535b1d5 AX |
285 | } |
286 | ||
287 | static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated) | |
288 | { | |
289 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
69e848c2 | 290 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); |
5535b1d5 AX |
291 | int retval = 0; |
292 | ||
69e848c2 SS |
293 | /* The BIOS on systems with the Intel Panther Point chipset may or may |
294 | * not support xHCI natively. That means that during system resume, it | |
295 | * may switch the ports back to EHCI so that users can use their | |
296 | * keyboard to select a kernel from GRUB after resume from hibernate. | |
297 | * | |
298 | * The BIOS is supposed to remember whether the OS had xHCI ports | |
299 | * enabled before resume, and switch the ports back to xHCI when the | |
300 | * BIOS/OS semaphore is written, but we all know we can't trust BIOS | |
301 | * writers. | |
302 | * | |
303 | * Unconditionally switch the ports back to xHCI after a system resume. | |
26b76798 MN |
304 | * It should not matter whether the EHCI or xHCI controller is |
305 | * resumed first. It's enough to do the switchover in xHCI because | |
306 | * USB core won't notice anything as the hub driver doesn't start | |
307 | * running again until after all the devices (including both EHCI and | |
308 | * xHCI host controllers) have been resumed. | |
69e848c2 | 309 | */ |
26b76798 MN |
310 | |
311 | if (pdev->vendor == PCI_VENDOR_ID_INTEL) | |
312 | usb_enable_intel_xhci_ports(pdev); | |
69e848c2 | 313 | |
5535b1d5 AX |
314 | retval = xhci_resume(xhci, hibernated); |
315 | return retval; | |
316 | } | |
317 | #endif /* CONFIG_PM */ | |
318 | ||
66d4eadd SS |
319 | /*-------------------------------------------------------------------------*/ |
320 | ||
321 | /* PCI driver selection metadata; PCI hotplugging uses this */ | |
322 | static const struct pci_device_id pci_ids[] = { { | |
323 | /* handle any USB 3.0 xHCI controller */ | |
324 | PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0), | |
325 | .driver_data = (unsigned long) &xhci_pci_hc_driver, | |
326 | }, | |
327 | { /* end: all zeroes */ } | |
328 | }; | |
329 | MODULE_DEVICE_TABLE(pci, pci_ids); | |
330 | ||
331 | /* pci driver glue; this is a "new style" PCI driver module */ | |
332 | static struct pci_driver xhci_pci_driver = { | |
333 | .name = (char *) hcd_name, | |
334 | .id_table = pci_ids, | |
335 | ||
f6ff0ac8 | 336 | .probe = xhci_pci_probe, |
b02d0ed6 | 337 | .remove = xhci_pci_remove, |
66d4eadd SS |
338 | /* suspend and resume implemented later */ |
339 | ||
340 | .shutdown = usb_hcd_pci_shutdown, | |
f875fdbf | 341 | #ifdef CONFIG_PM |
5535b1d5 AX |
342 | .driver = { |
343 | .pm = &usb_hcd_pci_pm_ops | |
344 | }, | |
345 | #endif | |
66d4eadd SS |
346 | }; |
347 | ||
29e409f0 | 348 | static int __init xhci_pci_init(void) |
66d4eadd | 349 | { |
1885d9a3 AB |
350 | xhci_init_driver(&xhci_pci_hc_driver, xhci_pci_setup); |
351 | #ifdef CONFIG_PM | |
352 | xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend; | |
353 | xhci_pci_hc_driver.pci_resume = xhci_pci_resume; | |
354 | #endif | |
66d4eadd SS |
355 | return pci_register_driver(&xhci_pci_driver); |
356 | } | |
29e409f0 | 357 | module_init(xhci_pci_init); |
66d4eadd | 358 | |
29e409f0 | 359 | static void __exit xhci_pci_exit(void) |
66d4eadd SS |
360 | { |
361 | pci_unregister_driver(&xhci_pci_driver); | |
362 | } | |
29e409f0 AB |
363 | module_exit(xhci_pci_exit); |
364 | ||
365 | MODULE_DESCRIPTION("xHCI PCI Host Controller Driver"); | |
366 | MODULE_LICENSE("GPL"); |