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Commit | Line | Data |
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66d4eadd SS |
1 | /* |
2 | * xHCI host controller driver PCI Bus Glue. | |
3 | * | |
4 | * Copyright (C) 2008 Intel Corp. | |
5 | * | |
6 | * Author: Sarah Sharp | |
7 | * Some code borrowed from the Linux EHCI driver. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | * for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software Foundation, | |
20 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
23 | #include <linux/pci.h> | |
7fc2a616 | 24 | #include <linux/slab.h> |
6eb0de82 | 25 | #include <linux/module.h> |
c3c5819a | 26 | #include <linux/acpi.h> |
66d4eadd SS |
27 | |
28 | #include "xhci.h" | |
4bdfe4c3 | 29 | #include "xhci-trace.h" |
66d4eadd | 30 | |
fa895377 LB |
31 | #define SSIC_PORT_NUM 2 |
32 | #define SSIC_PORT_CFG2 0x880c | |
33 | #define SSIC_PORT_CFG2_OFFSET 0x30 | |
abce329c RM |
34 | #define PROG_DONE (1 << 30) |
35 | #define SSIC_PORT_UNUSED (1 << 31) | |
36 | ||
ac9d8fe7 SS |
37 | /* Device for a quirk */ |
38 | #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73 | |
39 | #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000 | |
d95815ba | 40 | #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009 |
bba18e33 | 41 | #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400 |
ac9d8fe7 | 42 | |
c877b3b2 | 43 | #define PCI_VENDOR_ID_ETRON 0x1b6f |
170625e9 | 44 | #define PCI_DEVICE_ID_EJ168 0x7023 |
c877b3b2 | 45 | |
638298dc TI |
46 | #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31 |
47 | #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31 | |
4c39135a | 48 | #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1 |
b8cb91e0 MN |
49 | #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5 |
50 | #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f | |
51 | #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f | |
ccc04afb | 52 | #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8 |
0d46faca | 53 | #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8 |
346e9973 | 54 | #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8 |
a0c16630 | 55 | #define PCI_DEVICE_ID_INTEL_DNV_XHCI 0x19d0 |
638298dc | 56 | |
66d4eadd SS |
57 | static const char hcd_name[] = "xhci_hcd"; |
58 | ||
1885d9a3 AB |
59 | static struct hc_driver __read_mostly xhci_pci_hc_driver; |
60 | ||
cd33a321 RQ |
61 | static int xhci_pci_setup(struct usb_hcd *hcd); |
62 | ||
63 | static const struct xhci_driver_overrides xhci_pci_overrides __initconst = { | |
cd33a321 RQ |
64 | .reset = xhci_pci_setup, |
65 | }; | |
66 | ||
66d4eadd SS |
67 | /* called after powerup, by probe or system-pm "wakeup" */ |
68 | static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev) | |
69 | { | |
70 | /* | |
71 | * TODO: Implement finding debug ports later. | |
72 | * TODO: see if there are any quirks that need to be added to handle | |
73 | * new extended capabilities. | |
74 | */ | |
75 | ||
76 | /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ | |
77 | if (!pci_set_mwi(pdev)) | |
78 | xhci_dbg(xhci, "MWI active\n"); | |
79 | ||
80 | xhci_dbg(xhci, "Finished xhci_pci_reinit\n"); | |
81 | return 0; | |
82 | } | |
83 | ||
da3c9c4f SAS |
84 | static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) |
85 | { | |
86 | struct pci_dev *pdev = to_pci_dev(dev); | |
87 | ||
ac9d8fe7 SS |
88 | /* Look for vendor-specific quirks */ |
89 | if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && | |
bba18e33 SS |
90 | (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK || |
91 | pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) { | |
92 | if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && | |
93 | pdev->revision == 0x0) { | |
ac9d8fe7 | 94 | xhci->quirks |= XHCI_RESET_EP_QUIRK; |
4bdfe4c3 XR |
95 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
96 | "QUIRK: Fresco Logic xHC needs configure" | |
97 | " endpoint cmd after reset endpoint"); | |
f5182b41 | 98 | } |
455f5892 ON |
99 | if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && |
100 | pdev->revision == 0x4) { | |
101 | xhci->quirks |= XHCI_SLOW_SUSPEND; | |
102 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, | |
103 | "QUIRK: Fresco Logic xHC revision %u" | |
104 | "must be suspended extra slowly", | |
105 | pdev->revision); | |
106 | } | |
7f5c4d63 HG |
107 | if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK) |
108 | xhci->quirks |= XHCI_BROKEN_STREAMS; | |
f5182b41 SS |
109 | /* Fresco Logic confirms: all revisions of this chip do not |
110 | * support MSI, even though some of them claim to in their PCI | |
111 | * capabilities. | |
112 | */ | |
113 | xhci->quirks |= XHCI_BROKEN_MSI; | |
4bdfe4c3 XR |
114 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
115 | "QUIRK: Fresco Logic revision %u " | |
116 | "has broken MSI implementation", | |
f5182b41 | 117 | pdev->revision); |
1530bbc6 | 118 | xhci->quirks |= XHCI_TRUST_TX_LENGTH; |
ac9d8fe7 | 119 | } |
f5182b41 | 120 | |
d95815ba HG |
121 | if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && |
122 | pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009) | |
123 | xhci->quirks |= XHCI_BROKEN_STREAMS; | |
124 | ||
0238634d SS |
125 | if (pdev->vendor == PCI_VENDOR_ID_NEC) |
126 | xhci->quirks |= XHCI_NEC_HOST; | |
ac9d8fe7 | 127 | |
7e393a83 AX |
128 | if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96) |
129 | xhci->quirks |= XHCI_AMD_0x96_HOST; | |
130 | ||
c41136b0 AX |
131 | /* AMD PLL quirk */ |
132 | if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info()) | |
133 | xhci->quirks |= XHCI_AMD_PLL_FIX; | |
2597fe99 HR |
134 | |
135 | if (pdev->vendor == PCI_VENDOR_ID_AMD) | |
136 | xhci->quirks |= XHCI_TRUST_TX_LENGTH; | |
137 | ||
e3567d2c SS |
138 | if (pdev->vendor == PCI_VENDOR_ID_INTEL) { |
139 | xhci->quirks |= XHCI_LPM_SUPPORT; | |
140 | xhci->quirks |= XHCI_INTEL_HOST; | |
227a4fd8 | 141 | xhci->quirks |= XHCI_AVOID_BEI; |
e3567d2c | 142 | } |
ad808333 SS |
143 | if (pdev->vendor == PCI_VENDOR_ID_INTEL && |
144 | pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) { | |
2cf95c18 SS |
145 | xhci->quirks |= XHCI_EP_LIMIT_QUIRK; |
146 | xhci->limit_active_eps = 64; | |
86cc558e | 147 | xhci->quirks |= XHCI_SW_BW_CHECKING; |
e95829f4 SS |
148 | /* |
149 | * PPT desktop boards DH77EB and DH77DF will power back on after | |
150 | * a few seconds of being shutdown. The fix for this is to | |
151 | * switch the ports from xHCI to EHCI on shutdown. We can't use | |
152 | * DMI information to find those particular boards (since each | |
153 | * vendor will change the board name), so we have to key off all | |
154 | * PPT chipsets. | |
155 | */ | |
156 | xhci->quirks |= XHCI_SPURIOUS_REBOOT; | |
ad808333 | 157 | } |
0a939993 | 158 | if (pdev->vendor == PCI_VENDOR_ID_INTEL && |
4c39135a MN |
159 | (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI || |
160 | pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) { | |
c09ec25d | 161 | xhci->quirks |= XHCI_SPURIOUS_REBOOT; |
fd7cd061 | 162 | xhci->quirks |= XHCI_SPURIOUS_WAKEUP; |
638298dc | 163 | } |
b8cb91e0 MN |
164 | if (pdev->vendor == PCI_VENDOR_ID_INTEL && |
165 | (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || | |
166 | pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || | |
ccc04afb | 167 | pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || |
0d46faca | 168 | pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI || |
6c97cfc1 | 169 | pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI || |
a0c16630 MN |
170 | pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI || |
171 | pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI)) { | |
b8cb91e0 MN |
172 | xhci->quirks |= XHCI_PME_STUCK_QUIRK; |
173 | } | |
7e70cbff LB |
174 | if (pdev->vendor == PCI_VENDOR_ID_INTEL && |
175 | pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) { | |
176 | xhci->quirks |= XHCI_SSIC_PORT_UNUSED; | |
177 | } | |
346e9973 MN |
178 | if (pdev->vendor == PCI_VENDOR_ID_INTEL && |
179 | (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || | |
a0c16630 MN |
180 | pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI || |
181 | pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI)) | |
346e9973 MN |
182 | xhci->quirks |= XHCI_MISSING_CAS; |
183 | ||
c877b3b2 | 184 | if (pdev->vendor == PCI_VENDOR_ID_ETRON && |
170625e9 | 185 | pdev->device == PCI_DEVICE_ID_EJ168) { |
c877b3b2 | 186 | xhci->quirks |= XHCI_RESET_ON_RESUME; |
5cb7df2b | 187 | xhci->quirks |= XHCI_TRUST_TX_LENGTH; |
8f873c1f | 188 | xhci->quirks |= XHCI_BROKEN_STREAMS; |
c877b3b2 | 189 | } |
1aa9578c | 190 | if (pdev->vendor == PCI_VENDOR_ID_RENESAS && |
6db249eb | 191 | pdev->device == 0x0015) |
1aa9578c | 192 | xhci->quirks |= XHCI_RESET_ON_RESUME; |
457a4f61 EF |
193 | if (pdev->vendor == PCI_VENDOR_ID_VIA) |
194 | xhci->quirks |= XHCI_RESET_ON_RESUME; | |
85f4e45b | 195 | |
e21eba05 HG |
196 | /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */ |
197 | if (pdev->vendor == PCI_VENDOR_ID_VIA && | |
198 | pdev->device == 0x3432) | |
199 | xhci->quirks |= XHCI_BROKEN_STREAMS; | |
200 | ||
2391eacb HG |
201 | if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && |
202 | pdev->device == 0x1042) | |
203 | xhci->quirks |= XHCI_BROKEN_STREAMS; | |
d2f48f05 CL |
204 | if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && |
205 | pdev->device == 0x1142) | |
206 | xhci->quirks |= XHCI_TRUST_TX_LENGTH; | |
2391eacb | 207 | |
69307ccb RQ |
208 | if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241) |
209 | xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7; | |
210 | ||
85f4e45b ON |
211 | if (xhci->quirks & XHCI_RESET_ON_RESUME) |
212 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, | |
213 | "QUIRK: Resetting on resume"); | |
da3c9c4f | 214 | } |
c41136b0 | 215 | |
c3c5819a MN |
216 | #ifdef CONFIG_ACPI |
217 | static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) | |
218 | { | |
219 | static const u8 intel_dsm_uuid[] = { | |
220 | 0xb7, 0x0c, 0x34, 0xac, 0x01, 0xe9, 0xbf, 0x45, | |
221 | 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23, | |
222 | }; | |
84ed9152 MW |
223 | union acpi_object *obj; |
224 | ||
225 | obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), intel_dsm_uuid, 3, 1, | |
226 | NULL); | |
227 | ACPI_FREE(obj); | |
c3c5819a MN |
228 | } |
229 | #else | |
84ed9152 | 230 | static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { } |
c3c5819a MN |
231 | #endif /* CONFIG_ACPI */ |
232 | ||
da3c9c4f SAS |
233 | /* called during probe() after chip reset completes */ |
234 | static int xhci_pci_setup(struct usb_hcd *hcd) | |
235 | { | |
236 | struct xhci_hcd *xhci; | |
237 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); | |
238 | int retval; | |
66d4eadd | 239 | |
b50107bb MN |
240 | xhci = hcd_to_xhci(hcd); |
241 | if (!xhci->sbrn) | |
242 | pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn); | |
243 | ||
da3c9c4f | 244 | retval = xhci_gen_setup(hcd, xhci_pci_quirks); |
66d4eadd | 245 | if (retval) |
da3c9c4f | 246 | return retval; |
006d5820 | 247 | |
da3c9c4f SAS |
248 | if (!usb_hcd_is_primary_hcd(hcd)) |
249 | return 0; | |
66d4eadd | 250 | |
66d4eadd SS |
251 | xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn); |
252 | ||
253 | /* Find any debug ports */ | |
989bad11 | 254 | return xhci_pci_reinit(xhci, pdev); |
b02d0ed6 SS |
255 | } |
256 | ||
f6ff0ac8 SS |
257 | /* |
258 | * We need to register our own PCI probe function (instead of the USB core's | |
259 | * function) in order to create a second roothub under xHCI. | |
260 | */ | |
261 | static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) | |
262 | { | |
263 | int retval; | |
264 | struct xhci_hcd *xhci; | |
265 | struct hc_driver *driver; | |
266 | struct usb_hcd *hcd; | |
267 | ||
268 | driver = (struct hc_driver *)id->driver_data; | |
bcffae77 MN |
269 | |
270 | /* Prevent runtime suspending between USB-2 and USB-3 initialization */ | |
271 | pm_runtime_get_noresume(&dev->dev); | |
272 | ||
f6ff0ac8 SS |
273 | /* Register the USB 2.0 roothub. |
274 | * FIXME: USB core must know to register the USB 2.0 roothub first. | |
275 | * This is sort of silly, because we could just set the HCD driver flags | |
276 | * to say USB 2.0, but I'm not sure what the implications would be in | |
277 | * the other parts of the HCD code. | |
278 | */ | |
279 | retval = usb_hcd_pci_probe(dev, id); | |
280 | ||
281 | if (retval) | |
bcffae77 | 282 | goto put_runtime_pm; |
f6ff0ac8 SS |
283 | |
284 | /* USB 2.0 roothub is stored in the PCI device now. */ | |
285 | hcd = dev_get_drvdata(&dev->dev); | |
286 | xhci = hcd_to_xhci(hcd); | |
287 | xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev, | |
288 | pci_name(dev), hcd); | |
289 | if (!xhci->shared_hcd) { | |
290 | retval = -ENOMEM; | |
291 | goto dealloc_usb2_hcd; | |
292 | } | |
293 | ||
f6ff0ac8 | 294 | retval = usb_add_hcd(xhci->shared_hcd, dev->irq, |
b5dd18d8 | 295 | IRQF_SHARED); |
f6ff0ac8 SS |
296 | if (retval) |
297 | goto put_usb3_hcd; | |
298 | /* Roothub already marked as USB 3.0 speed */ | |
3b3db026 | 299 | |
8f873c1f HG |
300 | if (!(xhci->quirks & XHCI_BROKEN_STREAMS) && |
301 | HCC_MAX_PSA(xhci->hcc_params) >= 4) | |
14aec589 ON |
302 | xhci->shared_hcd->can_do_streams = 1; |
303 | ||
c3c5819a MN |
304 | if (xhci->quirks & XHCI_PME_STUCK_QUIRK) |
305 | xhci_pme_acpi_rtd3_enable(dev); | |
306 | ||
bcffae77 MN |
307 | /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */ |
308 | pm_runtime_put_noidle(&dev->dev); | |
309 | ||
f6ff0ac8 SS |
310 | return 0; |
311 | ||
312 | put_usb3_hcd: | |
313 | usb_put_hcd(xhci->shared_hcd); | |
314 | dealloc_usb2_hcd: | |
315 | usb_hcd_pci_remove(dev); | |
bcffae77 MN |
316 | put_runtime_pm: |
317 | pm_runtime_put_noidle(&dev->dev); | |
f6ff0ac8 SS |
318 | return retval; |
319 | } | |
320 | ||
b02d0ed6 SS |
321 | static void xhci_pci_remove(struct pci_dev *dev) |
322 | { | |
323 | struct xhci_hcd *xhci; | |
324 | ||
325 | xhci = hcd_to_xhci(pci_get_drvdata(dev)); | |
98d74f9c | 326 | xhci->xhc_state |= XHCI_STATE_REMOVING; |
f6ff0ac8 SS |
327 | if (xhci->shared_hcd) { |
328 | usb_remove_hcd(xhci->shared_hcd); | |
329 | usb_put_hcd(xhci->shared_hcd); | |
330 | } | |
638298dc TI |
331 | |
332 | /* Workaround for spurious wakeups at shutdown with HSW */ | |
333 | if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) | |
334 | pci_set_power_state(dev, PCI_D3hot); | |
f1f6d9a8 MN |
335 | |
336 | usb_hcd_pci_remove(dev); | |
66d4eadd SS |
337 | } |
338 | ||
5535b1d5 | 339 | #ifdef CONFIG_PM |
2b7627b7 TB |
340 | /* |
341 | * In some Intel xHCI controllers, in order to get D3 working, | |
342 | * through a vendor specific SSIC CONFIG register at offset 0x883c, | |
343 | * SSIC PORT need to be marked as "unused" before putting xHCI | |
344 | * into D3. After D3 exit, the SSIC port need to be marked as "used". | |
345 | * Without this change, xHCI might not enter D3 state. | |
2b7627b7 | 346 | */ |
7e70cbff | 347 | static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend) |
2b7627b7 TB |
348 | { |
349 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
2b7627b7 TB |
350 | u32 val; |
351 | void __iomem *reg; | |
fa895377 | 352 | int i; |
2b7627b7 | 353 | |
7e70cbff LB |
354 | for (i = 0; i < SSIC_PORT_NUM; i++) { |
355 | reg = (void __iomem *) xhci->cap_regs + | |
356 | SSIC_PORT_CFG2 + | |
357 | i * SSIC_PORT_CFG2_OFFSET; | |
358 | ||
359 | /* Notify SSIC that SSIC profile programming is not done. */ | |
360 | val = readl(reg) & ~PROG_DONE; | |
361 | writel(val, reg); | |
362 | ||
363 | /* Mark SSIC port as unused(suspend) or used(resume) */ | |
364 | val = readl(reg); | |
365 | if (suspend) | |
366 | val |= SSIC_PORT_UNUSED; | |
367 | else | |
368 | val &= ~SSIC_PORT_UNUSED; | |
369 | writel(val, reg); | |
370 | ||
371 | /* Notify SSIC that SSIC profile programming is done */ | |
372 | val = readl(reg) | PROG_DONE; | |
373 | writel(val, reg); | |
374 | readl(reg); | |
2b7627b7 | 375 | } |
7e70cbff LB |
376 | } |
377 | ||
378 | /* | |
379 | * Make sure PME works on some Intel xHCI controllers by writing 1 to clear | |
380 | * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4 | |
381 | */ | |
382 | static void xhci_pme_quirk(struct usb_hcd *hcd) | |
383 | { | |
384 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
385 | void __iomem *reg; | |
386 | u32 val; | |
2b7627b7 TB |
387 | |
388 | reg = (void __iomem *) xhci->cap_regs + 0x80a4; | |
389 | val = readl(reg); | |
390 | writel(val | BIT(28), reg); | |
391 | readl(reg); | |
392 | } | |
393 | ||
5535b1d5 AX |
394 | static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) |
395 | { | |
396 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
c3897aa5 | 397 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); |
92149c93 | 398 | int ret; |
c3897aa5 SS |
399 | |
400 | /* | |
401 | * Systems with the TI redriver that loses port status change events | |
402 | * need to have the registers polled during D3, so avoid D3cold. | |
403 | */ | |
e1cd9727 | 404 | if (xhci->quirks & XHCI_COMP_MODE_QUIRK) |
9d26d3a8 | 405 | pci_d3cold_disable(pdev); |
5535b1d5 | 406 | |
b8cb91e0 | 407 | if (xhci->quirks & XHCI_PME_STUCK_QUIRK) |
7e70cbff LB |
408 | xhci_pme_quirk(hcd); |
409 | ||
410 | if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) | |
411 | xhci_ssic_port_unused_quirk(hcd, true); | |
b8cb91e0 | 412 | |
92149c93 LB |
413 | ret = xhci_suspend(xhci, do_wakeup); |
414 | if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED)) | |
415 | xhci_ssic_port_unused_quirk(hcd, false); | |
416 | ||
417 | return ret; | |
5535b1d5 AX |
418 | } |
419 | ||
420 | static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated) | |
421 | { | |
422 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
69e848c2 | 423 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); |
5535b1d5 AX |
424 | int retval = 0; |
425 | ||
69e848c2 SS |
426 | /* The BIOS on systems with the Intel Panther Point chipset may or may |
427 | * not support xHCI natively. That means that during system resume, it | |
428 | * may switch the ports back to EHCI so that users can use their | |
429 | * keyboard to select a kernel from GRUB after resume from hibernate. | |
430 | * | |
431 | * The BIOS is supposed to remember whether the OS had xHCI ports | |
432 | * enabled before resume, and switch the ports back to xHCI when the | |
433 | * BIOS/OS semaphore is written, but we all know we can't trust BIOS | |
434 | * writers. | |
435 | * | |
436 | * Unconditionally switch the ports back to xHCI after a system resume. | |
26b76798 MN |
437 | * It should not matter whether the EHCI or xHCI controller is |
438 | * resumed first. It's enough to do the switchover in xHCI because | |
439 | * USB core won't notice anything as the hub driver doesn't start | |
440 | * running again until after all the devices (including both EHCI and | |
441 | * xHCI host controllers) have been resumed. | |
69e848c2 | 442 | */ |
26b76798 MN |
443 | |
444 | if (pdev->vendor == PCI_VENDOR_ID_INTEL) | |
445 | usb_enable_intel_xhci_ports(pdev); | |
69e848c2 | 446 | |
7e70cbff LB |
447 | if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) |
448 | xhci_ssic_port_unused_quirk(hcd, false); | |
449 | ||
b8cb91e0 | 450 | if (xhci->quirks & XHCI_PME_STUCK_QUIRK) |
7e70cbff | 451 | xhci_pme_quirk(hcd); |
b8cb91e0 | 452 | |
5535b1d5 AX |
453 | retval = xhci_resume(xhci, hibernated); |
454 | return retval; | |
455 | } | |
456 | #endif /* CONFIG_PM */ | |
457 | ||
66d4eadd SS |
458 | /*-------------------------------------------------------------------------*/ |
459 | ||
460 | /* PCI driver selection metadata; PCI hotplugging uses this */ | |
461 | static const struct pci_device_id pci_ids[] = { { | |
462 | /* handle any USB 3.0 xHCI controller */ | |
463 | PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0), | |
464 | .driver_data = (unsigned long) &xhci_pci_hc_driver, | |
465 | }, | |
466 | { /* end: all zeroes */ } | |
467 | }; | |
468 | MODULE_DEVICE_TABLE(pci, pci_ids); | |
469 | ||
470 | /* pci driver glue; this is a "new style" PCI driver module */ | |
471 | static struct pci_driver xhci_pci_driver = { | |
472 | .name = (char *) hcd_name, | |
473 | .id_table = pci_ids, | |
474 | ||
f6ff0ac8 | 475 | .probe = xhci_pci_probe, |
b02d0ed6 | 476 | .remove = xhci_pci_remove, |
66d4eadd SS |
477 | /* suspend and resume implemented later */ |
478 | ||
479 | .shutdown = usb_hcd_pci_shutdown, | |
f875fdbf | 480 | #ifdef CONFIG_PM |
5535b1d5 AX |
481 | .driver = { |
482 | .pm = &usb_hcd_pci_pm_ops | |
483 | }, | |
484 | #endif | |
66d4eadd SS |
485 | }; |
486 | ||
29e409f0 | 487 | static int __init xhci_pci_init(void) |
66d4eadd | 488 | { |
cd33a321 | 489 | xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides); |
1885d9a3 AB |
490 | #ifdef CONFIG_PM |
491 | xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend; | |
492 | xhci_pci_hc_driver.pci_resume = xhci_pci_resume; | |
493 | #endif | |
66d4eadd SS |
494 | return pci_register_driver(&xhci_pci_driver); |
495 | } | |
29e409f0 | 496 | module_init(xhci_pci_init); |
66d4eadd | 497 | |
29e409f0 | 498 | static void __exit xhci_pci_exit(void) |
66d4eadd SS |
499 | { |
500 | pci_unregister_driver(&xhci_pci_driver); | |
501 | } | |
29e409f0 AB |
502 | module_exit(xhci_pci_exit); |
503 | ||
504 | MODULE_DESCRIPTION("xHCI PCI Host Controller Driver"); | |
505 | MODULE_LICENSE("GPL"); |