[mirror_ubuntu-focal-kernel.git] / drivers / usb / host / xhci-rcar.c

// SPDX-License-Identifier: GPL-2.0
/*
 * xHCI host controller driver for R-Car SoCs
 *
 * Copyright (C) 2014 Renesas Electronics Corporation
 */

#include <linux/firmware.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/usb/phy.h>
#include <linux/sys_soc.h>

#include "xhci.h"
#include "xhci-plat.h"
#include "xhci-rcar.h"

/*
* - The V3 firmware is for almost all R-Car Gen3 (except r8a7795 ES1.x)
* - The V2 firmware is for r8a7795 ES1.x.
* - The V2 firmware is possible to use on R-Car Gen2. However, the V2 causes
*   performance degradation. So, this driver continues to use the V1 if R-Car
*   Gen2.
* - The V1 firmware is impossible to use on R-Car Gen3.
*/
MODULE_FIRMWARE(XHCI_RCAR_FIRMWARE_NAME_V1);
MODULE_FIRMWARE(XHCI_RCAR_FIRMWARE_NAME_V2);
MODULE_FIRMWARE(XHCI_RCAR_FIRMWARE_NAME_V3);

/*** Register Offset ***/
#define RCAR_USB3_AXH_STA	0x104	/* AXI Host Control Status */
#define RCAR_USB3_INT_ENA	0x224	/* Interrupt Enable */
#define RCAR_USB3_DL_CTRL	0x250	/* FW Download Control & Status */
#define RCAR_USB3_FW_DATA0	0x258	/* FW Data0 */

#define RCAR_USB3_LCLK		0xa44	/* LCLK Select */
#define RCAR_USB3_CONF1		0xa48	/* USB3.0 Configuration1 */
#define RCAR_USB3_CONF2		0xa5c	/* USB3.0 Configuration2 */
#define RCAR_USB3_CONF3		0xaa8	/* USB3.0 Configuration3 */
#define RCAR_USB3_RX_POL	0xab0	/* USB3.0 RX Polarity */
#define RCAR_USB3_TX_POL	0xab8	/* USB3.0 TX Polarity */

/*** Register Settings ***/
/* AXI Host Control Status */
#define RCAR_USB3_AXH_STA_B3_PLL_ACTIVE		0x00010000
#define RCAR_USB3_AXH_STA_B2_PLL_ACTIVE		0x00000001
#define RCAR_USB3_AXH_STA_PLL_ACTIVE_MASK (RCAR_USB3_AXH_STA_B3_PLL_ACTIVE | \
					   RCAR_USB3_AXH_STA_B2_PLL_ACTIVE)

/* Interrupt Enable */
#define RCAR_USB3_INT_XHC_ENA	0x00000001
#define RCAR_USB3_INT_PME_ENA	0x00000002
#define RCAR_USB3_INT_HSE_ENA	0x00000004
#define RCAR_USB3_INT_ENA_VAL	(RCAR_USB3_INT_XHC_ENA | \
				RCAR_USB3_INT_PME_ENA | RCAR_USB3_INT_HSE_ENA)

/* FW Download Control & Status */
#define RCAR_USB3_DL_CTRL_ENABLE	0x00000001
#define RCAR_USB3_DL_CTRL_FW_SUCCESS	0x00000010
#define RCAR_USB3_DL_CTRL_FW_SET_DATA0	0x00000100

/* LCLK Select */
#define RCAR_USB3_LCLK_ENA_VAL	0x01030001

/* USB3.0 Configuration */
#define RCAR_USB3_CONF1_VAL	0x00030204
#define RCAR_USB3_CONF2_VAL	0x00030300
#define RCAR_USB3_CONF3_VAL	0x13802007

/* USB3.0 Polarity */
#define RCAR_USB3_RX_POL_VAL	BIT(21)
#define RCAR_USB3_TX_POL_VAL	BIT(4)

/* For soc_device_attribute */
#define RCAR_XHCI_FIRMWARE_V2   BIT(0) /* FIRMWARE V2 */
#define RCAR_XHCI_FIRMWARE_V3   BIT(1) /* FIRMWARE V3 */

static const struct soc_device_attribute rcar_quirks_match[]  = {
	{
		.soc_id = "r8a7795", .revision = "ES1.*",
		.data = (void *)RCAR_XHCI_FIRMWARE_V2,
	},
	{ /* sentinel */ },
};

static void xhci_rcar_start_gen2(struct usb_hcd *hcd)
{
	/* LCLK Select */
	writel(RCAR_USB3_LCLK_ENA_VAL, hcd->regs + RCAR_USB3_LCLK);
	/* USB3.0 Configuration */
	writel(RCAR_USB3_CONF1_VAL, hcd->regs + RCAR_USB3_CONF1);
	writel(RCAR_USB3_CONF2_VAL, hcd->regs + RCAR_USB3_CONF2);
	writel(RCAR_USB3_CONF3_VAL, hcd->regs + RCAR_USB3_CONF3);
	/* USB3.0 Polarity */
	writel(RCAR_USB3_RX_POL_VAL, hcd->regs + RCAR_USB3_RX_POL);
	writel(RCAR_USB3_TX_POL_VAL, hcd->regs + RCAR_USB3_TX_POL);
}

static int xhci_rcar_is_gen2(struct device *dev)
{
	struct device_node *node = dev->of_node;

	return of_device_is_compatible(node, "renesas,xhci-r8a7790") ||
		of_device_is_compatible(node, "renesas,xhci-r8a7791") ||
		of_device_is_compatible(node, "renesas,xhci-r8a7793") ||
		of_device_is_compatible(node, "renensas,rcar-gen2-xhci");
}

static int xhci_rcar_is_gen3(struct device *dev)
{
	struct device_node *node = dev->of_node;

	return of_device_is_compatible(node, "renesas,xhci-r8a7795") ||
		of_device_is_compatible(node, "renesas,xhci-r8a7796") ||
		of_device_is_compatible(node, "renesas,rcar-gen3-xhci");
}

void xhci_rcar_start(struct usb_hcd *hcd)
{
	u32 temp;

	if (hcd->regs != NULL) {
		/* Interrupt Enable */
		temp = readl(hcd->regs + RCAR_USB3_INT_ENA);
		temp |= RCAR_USB3_INT_ENA_VAL;
		writel(temp, hcd->regs + RCAR_USB3_INT_ENA);
		if (xhci_rcar_is_gen2(hcd->self.controller))
			xhci_rcar_start_gen2(hcd);
	}
}

static int xhci_rcar_download_firmware(struct usb_hcd *hcd)
{
	struct device *dev = hcd->self.controller;
	void __iomem *regs = hcd->regs;
	struct xhci_plat_priv *priv = hcd_to_xhci_priv(hcd);
	const struct firmware *fw;
	int retval, index, j, time;
	int timeout = 10000;
	u32 data, val, temp;
	u32 quirks = 0;
	const struct soc_device_attribute *attr;
	const char *firmware_name;

	attr = soc_device_match(rcar_quirks_match);
	if (attr)
		quirks = (uintptr_t)attr->data;

	if (quirks & RCAR_XHCI_FIRMWARE_V2)
		firmware_name = XHCI_RCAR_FIRMWARE_NAME_V2;
	else if (quirks & RCAR_XHCI_FIRMWARE_V3)
		firmware_name = XHCI_RCAR_FIRMWARE_NAME_V3;
	else
		firmware_name = priv->firmware_name;

	/* request R-Car USB3.0 firmware */
	retval = request_firmware(&fw, firmware_name, dev);
	if (retval)
		return retval;

	/* download R-Car USB3.0 firmware */
	temp = readl(regs + RCAR_USB3_DL_CTRL);
	temp |= RCAR_USB3_DL_CTRL_ENABLE;
	writel(temp, regs + RCAR_USB3_DL_CTRL);

	for (index = 0; index < fw->size; index += 4) {
		/* to avoid reading beyond the end of the buffer */
		for (data = 0, j = 3; j >= 0; j--) {
			if ((j + index) < fw->size)
				data |= fw->data[index + j] << (8 * j);
		}
		writel(data, regs + RCAR_USB3_FW_DATA0);
		temp = readl(regs + RCAR_USB3_DL_CTRL);
		temp |= RCAR_USB3_DL_CTRL_FW_SET_DATA0;
		writel(temp, regs + RCAR_USB3_DL_CTRL);

		for (time = 0; time < timeout; time++) {
			val = readl(regs + RCAR_USB3_DL_CTRL);
			if ((val & RCAR_USB3_DL_CTRL_FW_SET_DATA0) == 0)
				break;
			udelay(1);
		}
		if (time == timeout) {
			retval = -ETIMEDOUT;
			break;
		}
	}

	temp = readl(regs + RCAR_USB3_DL_CTRL);
	temp &= ~RCAR_USB3_DL_CTRL_ENABLE;
	writel(temp, regs + RCAR_USB3_DL_CTRL);

	for (time = 0; time < timeout; time++) {
		val = readl(regs + RCAR_USB3_DL_CTRL);
		if (val & RCAR_USB3_DL_CTRL_FW_SUCCESS) {
			retval = 0;
			break;
		}
		udelay(1);
	}
	if (time == timeout)
		retval = -ETIMEDOUT;

	release_firmware(fw);

	return retval;
}

static bool xhci_rcar_wait_for_pll_active(struct usb_hcd *hcd)
{
	int timeout = 1000;
	u32 val, mask = RCAR_USB3_AXH_STA_PLL_ACTIVE_MASK;

	while (timeout > 0) {
		val = readl(hcd->regs + RCAR_USB3_AXH_STA);
		if ((val & mask) == mask)
			return true;
		udelay(1);
		timeout--;
	}

	return false;
}

/* This function needs to initialize a "phy" of usb before */
int xhci_rcar_init_quirk(struct usb_hcd *hcd)
{
	struct xhci_hcd *xhci = hcd_to_xhci(hcd);

	/* If hcd->regs is NULL, we don't just call the following function */
	if (!hcd->regs)
		return 0;

	/*
	 * On R-Car Gen2 and Gen3, the AC64 bit (bit 0) of HCCPARAMS1 is set
	 * to 1. However, these SoCs don't support 64-bit address memory
	 * pointers. So, this driver clears the AC64 bit of xhci->hcc_params
	 * to call dma_set_coherent_mask(dev, DMA_BIT_MASK(32)) in
	 * xhci_gen_setup().
	 *
	 * And, since the firmware/internal CPU control the USBSTS.STS_HALT
	 * and the process speed is down when the roothub port enters U3,
	 * long delay for the handshake of STS_HALT is neeed in xhci_suspend().
	 */
	if (xhci_rcar_is_gen2(hcd->self.controller) ||
			xhci_rcar_is_gen3(hcd->self.controller)) {
		xhci->quirks |= XHCI_NO_64BIT_SUPPORT | XHCI_SLOW_SUSPEND;
	}

	if (!xhci_rcar_wait_for_pll_active(hcd))
		return -ETIMEDOUT;

	xhci->quirks |= XHCI_TRUST_TX_LENGTH;
	return xhci_rcar_download_firmware(hcd);
}

int xhci_rcar_resume_quirk(struct usb_hcd *hcd)
{
	int ret;

	ret = xhci_rcar_download_firmware(hcd);
	if (!ret)
		xhci_rcar_start(hcd);

	return ret;
}
Commit	Line	Data
5fd54ace	1	// SPDX-License-Identifier: GPL-2.0
4ac8918f YS	2	/*
	3	* xHCI host controller driver for R-Car SoCs
	4	*
	5	* Copyright (C) 2014 Renesas Electronics Corporation
4ac8918f YS	6	*/
	7
	8	#include <linux/firmware.h>
	9	#include <linux/module.h>
	10	#include <linux/platform_device.h>
2dc240a3	11	#include <linux/of.h>
4ac8918f	12	#include <linux/usb/phy.h>
306b89d3	13	#include <linux/sys_soc.h>
4ac8918f YS	14
4ac8918f YS	15	#include "xhci.h"
9bf9d9d6	16	#include "xhci-plat.h"
4ac8918f YS	17	#include "xhci-rcar.h"
4ac8918f YS	18
526a240f	19	/*
ed8603e1 YS	20	* - The V3 firmware is for almost all R-Car Gen3 (except r8a7795 ES1.x)
ed8603e1 YS	21	* - The V2 firmware is for r8a7795 ES1.x.
526a240f YS	22	* - The V2 firmware is possible to use on R-Car Gen2. However, the V2 causes
	23	* performance degradation. So, this driver continues to use the V1 if R-Car
	24	* Gen2.
	25	* - The V1 firmware is impossible to use on R-Car Gen3.
	26	*/
9bf9d9d6	27	MODULE_FIRMWARE(XHCI_RCAR_FIRMWARE_NAME_V1);
526a240f	28	MODULE_FIRMWARE(XHCI_RCAR_FIRMWARE_NAME_V2);
125f0c0c	29	MODULE_FIRMWARE(XHCI_RCAR_FIRMWARE_NAME_V3);
4ac8918f YS	30
4ac8918f YS	31	/* Register Offset */
5f981073	32	#define RCAR_USB3_AXH_STA 0x104 /* AXI Host Control Status */
4ac8918f YS	33	#define RCAR_USB3_INT_ENA 0x224 /* Interrupt Enable */
	34	#define RCAR_USB3_DL_CTRL 0x250 /* FW Download Control & Status */
	35	#define RCAR_USB3_FW_DATA0 0x258 /* FW Data0 */
	36
	37	#define RCAR_USB3_LCLK 0xa44 /* LCLK Select */
	38	#define RCAR_USB3_CONF1 0xa48 /* USB3.0 Configuration1 */
	39	#define RCAR_USB3_CONF2 0xa5c /* USB3.0 Configuration2 */
	40	#define RCAR_USB3_CONF3 0xaa8 /* USB3.0 Configuration3 */
	41	#define RCAR_USB3_RX_POL 0xab0 /* USB3.0 RX Polarity */
	42	#define RCAR_USB3_TX_POL 0xab8 /* USB3.0 TX Polarity */
	43
	44	/* Register Settings */
5f981073 YS	45	/* AXI Host Control Status */
	46	#define RCAR_USB3_AXH_STA_B3_PLL_ACTIVE 0x00010000
	47	#define RCAR_USB3_AXH_STA_B2_PLL_ACTIVE 0x00000001
	48	#define RCAR_USB3_AXH_STA_PLL_ACTIVE_MASK (RCAR_USB3_AXH_STA_B3_PLL_ACTIVE \| \
	49	RCAR_USB3_AXH_STA_B2_PLL_ACTIVE)
	50
4ac8918f YS	51	/* Interrupt Enable */
	52	#define RCAR_USB3_INT_XHC_ENA 0x00000001
	53	#define RCAR_USB3_INT_PME_ENA 0x00000002
	54	#define RCAR_USB3_INT_HSE_ENA 0x00000004
	55	#define RCAR_USB3_INT_ENA_VAL (RCAR_USB3_INT_XHC_ENA \| \
	56	RCAR_USB3_INT_PME_ENA \| RCAR_USB3_INT_HSE_ENA)
	57
	58	/* FW Download Control & Status */
	59	#define RCAR_USB3_DL_CTRL_ENABLE 0x00000001
	60	#define RCAR_USB3_DL_CTRL_FW_SUCCESS 0x00000010
	61	#define RCAR_USB3_DL_CTRL_FW_SET_DATA0 0x00000100
	62
	63	/* LCLK Select */
	64	#define RCAR_USB3_LCLK_ENA_VAL 0x01030001
	65
	66	/* USB3.0 Configuration */
	67	#define RCAR_USB3_CONF1_VAL 0x00030204
	68	#define RCAR_USB3_CONF2_VAL 0x00030300
	69	#define RCAR_USB3_CONF3_VAL 0x13802007
	70
	71	/* USB3.0 Polarity */
	72	#define RCAR_USB3_RX_POL_VAL BIT(21)
	73	#define RCAR_USB3_TX_POL_VAL BIT(4)
	74
306b89d3 YS	75	/* For soc_device_attribute */
	76	#define RCAR_XHCI_FIRMWARE_V2 BIT(0) /* FIRMWARE V2 */
	77	#define RCAR_XHCI_FIRMWARE_V3 BIT(1) /* FIRMWARE V3 */
	78
	79	static const struct soc_device_attribute rcar_quirks_match[] = {
	80	{
	81	.soc_id = "r8a7795", .revision = "ES1.*",
	82	.data = (void *)RCAR_XHCI_FIRMWARE_V2,
	83	},
306b89d3 YS	84	{ /* sentinel */ },
	85	};
	86
9bf9d9d6 YS	87	static void xhci_rcar_start_gen2(struct usb_hcd *hcd)
	88	{
	89	/* LCLK Select */
	90	writel(RCAR_USB3_LCLK_ENA_VAL, hcd->regs + RCAR_USB3_LCLK);
	91	/* USB3.0 Configuration */
	92	writel(RCAR_USB3_CONF1_VAL, hcd->regs + RCAR_USB3_CONF1);
	93	writel(RCAR_USB3_CONF2_VAL, hcd->regs + RCAR_USB3_CONF2);
	94	writel(RCAR_USB3_CONF3_VAL, hcd->regs + RCAR_USB3_CONF3);
	95	/* USB3.0 Polarity */
	96	writel(RCAR_USB3_RX_POL_VAL, hcd->regs + RCAR_USB3_RX_POL);
	97	writel(RCAR_USB3_TX_POL_VAL, hcd->regs + RCAR_USB3_TX_POL);
	98	}
	99
2dc240a3 FB	100	static int xhci_rcar_is_gen2(struct device *dev)
	101	{
	102	struct device_node *node = dev->of_node;
	103
	104	return of_device_is_compatible(node, "renesas,xhci-r8a7790") \|\|
	105	of_device_is_compatible(node, "renesas,xhci-r8a7791") \|\|
	106	of_device_is_compatible(node, "renesas,xhci-r8a7793") \|\|
	107	of_device_is_compatible(node, "renensas,rcar-gen2-xhci");
	108	}
	109
	110	static int xhci_rcar_is_gen3(struct device *dev)
	111	{
	112	struct device_node *node = dev->of_node;
	113
	114	return of_device_is_compatible(node, "renesas,xhci-r8a7795") \|\|
3f1dae6b	115	of_device_is_compatible(node, "renesas,xhci-r8a7796") \|\|
2dc240a3 FB	116	of_device_is_compatible(node, "renesas,rcar-gen3-xhci");
	117	}
	118
4ac8918f YS	119	void xhci_rcar_start(struct usb_hcd *hcd)
	120	{
	121	u32 temp;
	122
	123	if (hcd->regs != NULL) {
	124	/* Interrupt Enable */
	125	temp = readl(hcd->regs + RCAR_USB3_INT_ENA);
	126	temp \|= RCAR_USB3_INT_ENA_VAL;
	127	writel(temp, hcd->regs + RCAR_USB3_INT_ENA);
2dc240a3	128	if (xhci_rcar_is_gen2(hcd->self.controller))
9bf9d9d6	129	xhci_rcar_start_gen2(hcd);
4ac8918f YS	130	}
	131	}
	132
9bf9d9d6	133	static int xhci_rcar_download_firmware(struct usb_hcd *hcd)
4ac8918f	134	{
9bf9d9d6 YS	135	struct device *dev = hcd->self.controller;
	136	void __iomem *regs = hcd->regs;
	137	struct xhci_plat_priv *priv = hcd_to_xhci_priv(hcd);
4ac8918f YS	138	const struct firmware *fw;
	139	int retval, index, j, time;
	140	int timeout = 10000;
	141	u32 data, val, temp;
306b89d3 YS	142	u32 quirks = 0;
	143	const struct soc_device_attribute *attr;
	144	const char *firmware_name;
	145
	146	attr = soc_device_match(rcar_quirks_match);
	147	if (attr)
	148	quirks = (uintptr_t)attr->data;
	149
	150	if (quirks & RCAR_XHCI_FIRMWARE_V2)
	151	firmware_name = XHCI_RCAR_FIRMWARE_NAME_V2;
	152	else if (quirks & RCAR_XHCI_FIRMWARE_V3)
	153	firmware_name = XHCI_RCAR_FIRMWARE_NAME_V3;
	154	else
	155	firmware_name = priv->firmware_name;
4ac8918f YS	156
4ac8918f YS	157	/* request R-Car USB3.0 firmware */
306b89d3	158	retval = request_firmware(&fw, firmware_name, dev);
4ac8918f YS	159	if (retval)
	160	return retval;
	161
	162	/* download R-Car USB3.0 firmware */
	163	temp = readl(regs + RCAR_USB3_DL_CTRL);
	164	temp \|= RCAR_USB3_DL_CTRL_ENABLE;
	165	writel(temp, regs + RCAR_USB3_DL_CTRL);
	166
	167	for (index = 0; index < fw->size; index += 4) {
	168	/* to avoid reading beyond the end of the buffer */
	169	for (data = 0, j = 3; j >= 0; j--) {
	170	if ((j + index) < fw->size)
	171	data \|= fw->data[index + j] << (8 * j);
	172	}
	173	writel(data, regs + RCAR_USB3_FW_DATA0);
	174	temp = readl(regs + RCAR_USB3_DL_CTRL);
	175	temp \|= RCAR_USB3_DL_CTRL_FW_SET_DATA0;
	176	writel(temp, regs + RCAR_USB3_DL_CTRL);
	177
	178	for (time = 0; time < timeout; time++) {
	179	val = readl(regs + RCAR_USB3_DL_CTRL);
	180	if ((val & RCAR_USB3_DL_CTRL_FW_SET_DATA0) == 0)
	181	break;
	182	udelay(1);
	183	}
	184	if (time == timeout) {
	185	retval = -ETIMEDOUT;
	186	break;
	187	}
	188	}
	189
	190	temp = readl(regs + RCAR_USB3_DL_CTRL);
	191	temp &= ~RCAR_USB3_DL_CTRL_ENABLE;
	192	writel(temp, regs + RCAR_USB3_DL_CTRL);
	193
	194	for (time = 0; time < timeout; time++) {
	195	val = readl(regs + RCAR_USB3_DL_CTRL);
	196	if (val & RCAR_USB3_DL_CTRL_FW_SUCCESS) {
	197	retval = 0;
	198	break;
	199	}
	200	udelay(1);
	201	}
	202	if (time == timeout)
	203	retval = -ETIMEDOUT;
	204
	205	release_firmware(fw);
	206
	207	return retval;
	208	}
	209
5f981073 YS	210	static bool xhci_rcar_wait_for_pll_active(struct usb_hcd *hcd)
	211	{
	212	int timeout = 1000;
	213	u32 val, mask = RCAR_USB3_AXH_STA_PLL_ACTIVE_MASK;
	214
	215	while (timeout > 0) {
	216	val = readl(hcd->regs + RCAR_USB3_AXH_STA);
	217	if ((val & mask) == mask)
	218	return true;
	219	udelay(1);
	220	timeout--;
	221	}
	222
	223	return false;
	224	}
	225
4ac8918f YS	226	/* This function needs to initialize a "phy" of usb before */
	227	int xhci_rcar_init_quirk(struct usb_hcd *hcd)
	228	{
2dc240a3 FB	229	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2dc240a3 FB	230
4ac8918f YS	231	/* If hcd->regs is NULL, we don't just call the following function */
	232	if (!hcd->regs)
	233	return 0;
	234
2dc240a3 FB	235	/*
	236	* On R-Car Gen2 and Gen3, the AC64 bit (bit 0) of HCCPARAMS1 is set
	237	* to 1. However, these SoCs don't support 64-bit address memory
	238	* pointers. So, this driver clears the AC64 bit of xhci->hcc_params
	239	* to call dma_set_coherent_mask(dev, DMA_BIT_MASK(32)) in
	240	* xhci_gen_setup().
783bda5e YS	241	*
	242	* And, since the firmware/internal CPU control the USBSTS.STS_HALT
	243	* and the process speed is down when the roothub port enters U3,
	244	* long delay for the handshake of STS_HALT is neeed in xhci_suspend().
2dc240a3 FB	245	*/
2dc240a3 FB	246	if (xhci_rcar_is_gen2(hcd->self.controller) \|\|
783bda5e YS	247	xhci_rcar_is_gen3(hcd->self.controller)) {
	248	xhci->quirks \|= XHCI_NO_64BIT_SUPPORT \| XHCI_SLOW_SUSPEND;
	249	}
2dc240a3	250
5f981073 YS	251	if (!xhci_rcar_wait_for_pll_active(hcd))
	252	return -ETIMEDOUT;
	253
40fc1653	254	xhci->quirks \|= XHCI_TRUST_TX_LENGTH;
9bf9d9d6	255	return xhci_rcar_download_firmware(hcd);
4ac8918f	256	}
435cc113 YS	257
	258	int xhci_rcar_resume_quirk(struct usb_hcd *hcd)
	259	{
	260	int ret;
	261
	262	ret = xhci_rcar_download_firmware(hcd);
	263	if (!ret)
	264	xhci_rcar_start(hcd);
	265
	266	return ret;
	267	}