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7f84eef0 SS |
1 | /* |
2 | * xHCI host controller driver | |
3 | * | |
4 | * Copyright (C) 2008 Intel Corp. | |
5 | * | |
6 | * Author: Sarah Sharp | |
7 | * Some code borrowed from the Linux EHCI driver. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | * for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software Foundation, | |
20 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
23 | /* | |
24 | * Ring initialization rules: | |
25 | * 1. Each segment is initialized to zero, except for link TRBs. | |
26 | * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or | |
27 | * Consumer Cycle State (CCS), depending on ring function. | |
28 | * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment. | |
29 | * | |
30 | * Ring behavior rules: | |
31 | * 1. A ring is empty if enqueue == dequeue. This means there will always be at | |
32 | * least one free TRB in the ring. This is useful if you want to turn that | |
33 | * into a link TRB and expand the ring. | |
34 | * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a | |
35 | * link TRB, then load the pointer with the address in the link TRB. If the | |
36 | * link TRB had its toggle bit set, you may need to update the ring cycle | |
37 | * state (see cycle bit rules). You may have to do this multiple times | |
38 | * until you reach a non-link TRB. | |
39 | * 3. A ring is full if enqueue++ (for the definition of increment above) | |
40 | * equals the dequeue pointer. | |
41 | * | |
42 | * Cycle bit rules: | |
43 | * 1. When a consumer increments a dequeue pointer and encounters a toggle bit | |
44 | * in a link TRB, it must toggle the ring cycle state. | |
45 | * 2. When a producer increments an enqueue pointer and encounters a toggle bit | |
46 | * in a link TRB, it must toggle the ring cycle state. | |
47 | * | |
48 | * Producer rules: | |
49 | * 1. Check if ring is full before you enqueue. | |
50 | * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing. | |
51 | * Update enqueue pointer between each write (which may update the ring | |
52 | * cycle state). | |
53 | * 3. Notify consumer. If SW is producer, it rings the doorbell for command | |
54 | * and endpoint rings. If HC is the producer for the event ring, | |
55 | * and it generates an interrupt according to interrupt modulation rules. | |
56 | * | |
57 | * Consumer rules: | |
58 | * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state, | |
59 | * the TRB is owned by the consumer. | |
60 | * 2. Update dequeue pointer (which may update the ring cycle state) and | |
61 | * continue processing TRBs until you reach a TRB which is not owned by you. | |
62 | * 3. Notify the producer. SW is the consumer for the event ring, and it | |
63 | * updates event ring dequeue pointer. HC is the consumer for the command and | |
64 | * endpoint rings; it generates events on the event ring for these. | |
65 | */ | |
66 | ||
8a96c052 | 67 | #include <linux/scatterlist.h> |
5a0e3ad6 | 68 | #include <linux/slab.h> |
7f84eef0 SS |
69 | #include "xhci.h" |
70 | ||
be88fe4f AX |
71 | static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci, |
72 | struct xhci_virt_device *virt_dev, | |
73 | struct xhci_event_cmd *event); | |
74 | ||
7f84eef0 SS |
75 | /* |
76 | * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA | |
77 | * address of the TRB. | |
78 | */ | |
23e3be11 | 79 | dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, |
7f84eef0 SS |
80 | union xhci_trb *trb) |
81 | { | |
6071d836 | 82 | unsigned long segment_offset; |
7f84eef0 | 83 | |
6071d836 | 84 | if (!seg || !trb || trb < seg->trbs) |
7f84eef0 | 85 | return 0; |
6071d836 SS |
86 | /* offset in TRBs */ |
87 | segment_offset = trb - seg->trbs; | |
88 | if (segment_offset > TRBS_PER_SEGMENT) | |
7f84eef0 | 89 | return 0; |
6071d836 | 90 | return seg->dma + (segment_offset * sizeof(*trb)); |
7f84eef0 SS |
91 | } |
92 | ||
93 | /* Does this link TRB point to the first segment in a ring, | |
94 | * or was the previous TRB the last TRB on the last segment in the ERST? | |
95 | */ | |
575688e1 | 96 | static bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring, |
7f84eef0 SS |
97 | struct xhci_segment *seg, union xhci_trb *trb) |
98 | { | |
99 | if (ring == xhci->event_ring) | |
100 | return (trb == &seg->trbs[TRBS_PER_SEGMENT]) && | |
101 | (seg->next == xhci->event_ring->first_seg); | |
102 | else | |
28ccd296 | 103 | return le32_to_cpu(trb->link.control) & LINK_TOGGLE; |
7f84eef0 SS |
104 | } |
105 | ||
106 | /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring | |
107 | * segment? I.e. would the updated event TRB pointer step off the end of the | |
108 | * event seg? | |
109 | */ | |
575688e1 | 110 | static int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring, |
7f84eef0 SS |
111 | struct xhci_segment *seg, union xhci_trb *trb) |
112 | { | |
113 | if (ring == xhci->event_ring) | |
114 | return trb == &seg->trbs[TRBS_PER_SEGMENT]; | |
115 | else | |
28ccd296 ME |
116 | return (le32_to_cpu(trb->link.control) & TRB_TYPE_BITMASK) |
117 | == TRB_TYPE(TRB_LINK); | |
7f84eef0 SS |
118 | } |
119 | ||
575688e1 | 120 | static int enqueue_is_link_trb(struct xhci_ring *ring) |
6c12db90 JY |
121 | { |
122 | struct xhci_link_trb *link = &ring->enqueue->link; | |
28ccd296 ME |
123 | return ((le32_to_cpu(link->control) & TRB_TYPE_BITMASK) == |
124 | TRB_TYPE(TRB_LINK)); | |
6c12db90 JY |
125 | } |
126 | ||
ae636747 SS |
127 | /* Updates trb to point to the next TRB in the ring, and updates seg if the next |
128 | * TRB is in a new segment. This does not skip over link TRBs, and it does not | |
129 | * effect the ring dequeue or enqueue pointers. | |
130 | */ | |
131 | static void next_trb(struct xhci_hcd *xhci, | |
132 | struct xhci_ring *ring, | |
133 | struct xhci_segment **seg, | |
134 | union xhci_trb **trb) | |
135 | { | |
136 | if (last_trb(xhci, ring, *seg, *trb)) { | |
137 | *seg = (*seg)->next; | |
138 | *trb = ((*seg)->trbs); | |
139 | } else { | |
a1669b2c | 140 | (*trb)++; |
ae636747 SS |
141 | } |
142 | } | |
143 | ||
7f84eef0 SS |
144 | /* |
145 | * See Cycle bit rules. SW is the consumer for the event ring only. | |
146 | * Don't make a ring full of link TRBs. That would be dumb and this would loop. | |
147 | */ | |
148 | static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer) | |
149 | { | |
150 | union xhci_trb *next = ++(ring->dequeue); | |
66e49d87 | 151 | unsigned long long addr; |
7f84eef0 SS |
152 | |
153 | ring->deq_updates++; | |
154 | /* Update the dequeue pointer further if that was a link TRB or we're at | |
155 | * the end of an event ring segment (which doesn't have link TRBS) | |
156 | */ | |
157 | while (last_trb(xhci, ring, ring->deq_seg, next)) { | |
158 | if (consumer && last_trb_on_last_seg(xhci, ring, ring->deq_seg, next)) { | |
159 | ring->cycle_state = (ring->cycle_state ? 0 : 1); | |
160 | if (!in_interrupt()) | |
700e2052 GKH |
161 | xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n", |
162 | ring, | |
7f84eef0 SS |
163 | (unsigned int) ring->cycle_state); |
164 | } | |
165 | ring->deq_seg = ring->deq_seg->next; | |
166 | ring->dequeue = ring->deq_seg->trbs; | |
167 | next = ring->dequeue; | |
168 | } | |
66e49d87 SS |
169 | addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue); |
170 | if (ring == xhci->event_ring) | |
171 | xhci_dbg(xhci, "Event ring deq = 0x%llx (DMA)\n", addr); | |
172 | else if (ring == xhci->cmd_ring) | |
173 | xhci_dbg(xhci, "Command ring deq = 0x%llx (DMA)\n", addr); | |
174 | else | |
175 | xhci_dbg(xhci, "Ring deq = 0x%llx (DMA)\n", addr); | |
7f84eef0 SS |
176 | } |
177 | ||
178 | /* | |
179 | * See Cycle bit rules. SW is the consumer for the event ring only. | |
180 | * Don't make a ring full of link TRBs. That would be dumb and this would loop. | |
181 | * | |
182 | * If we've just enqueued a TRB that is in the middle of a TD (meaning the | |
183 | * chain bit is set), then set the chain bit in all the following link TRBs. | |
184 | * If we've enqueued the last TRB in a TD, make sure the following link TRBs | |
185 | * have their chain bit cleared (so that each Link TRB is a separate TD). | |
186 | * | |
187 | * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit | |
b0567b3f SS |
188 | * set, but other sections talk about dealing with the chain bit set. This was |
189 | * fixed in the 0.96 specification errata, but we have to assume that all 0.95 | |
190 | * xHCI hardware can't handle the chain bit being cleared on a link TRB. | |
6cc30d85 SS |
191 | * |
192 | * @more_trbs_coming: Will you enqueue more TRBs before calling | |
193 | * prepare_transfer()? | |
7f84eef0 | 194 | */ |
6cc30d85 SS |
195 | static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring, |
196 | bool consumer, bool more_trbs_coming) | |
7f84eef0 SS |
197 | { |
198 | u32 chain; | |
199 | union xhci_trb *next; | |
66e49d87 | 200 | unsigned long long addr; |
7f84eef0 | 201 | |
28ccd296 | 202 | chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN; |
7f84eef0 SS |
203 | next = ++(ring->enqueue); |
204 | ||
205 | ring->enq_updates++; | |
206 | /* Update the dequeue pointer further if that was a link TRB or we're at | |
207 | * the end of an event ring segment (which doesn't have link TRBS) | |
208 | */ | |
209 | while (last_trb(xhci, ring, ring->enq_seg, next)) { | |
210 | if (!consumer) { | |
211 | if (ring != xhci->event_ring) { | |
6cc30d85 SS |
212 | /* |
213 | * If the caller doesn't plan on enqueueing more | |
214 | * TDs before ringing the doorbell, then we | |
215 | * don't want to give the link TRB to the | |
216 | * hardware just yet. We'll give the link TRB | |
217 | * back in prepare_ring() just before we enqueue | |
218 | * the TD at the top of the ring. | |
219 | */ | |
220 | if (!chain && !more_trbs_coming) | |
6c12db90 | 221 | break; |
6cc30d85 SS |
222 | |
223 | /* If we're not dealing with 0.95 hardware, | |
224 | * carry over the chain bit of the previous TRB | |
225 | * (which may mean the chain bit is cleared). | |
226 | */ | |
227 | if (!xhci_link_trb_quirk(xhci)) { | |
28ccd296 ME |
228 | next->link.control &= |
229 | cpu_to_le32(~TRB_CHAIN); | |
230 | next->link.control |= | |
231 | cpu_to_le32(chain); | |
b0567b3f | 232 | } |
6cc30d85 SS |
233 | /* Give this link TRB to the hardware */ |
234 | wmb(); | |
28ccd296 | 235 | next->link.control ^= cpu_to_le32(TRB_CYCLE); |
7f84eef0 SS |
236 | } |
237 | /* Toggle the cycle bit after the last ring segment. */ | |
238 | if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) { | |
239 | ring->cycle_state = (ring->cycle_state ? 0 : 1); | |
240 | if (!in_interrupt()) | |
700e2052 GKH |
241 | xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n", |
242 | ring, | |
7f84eef0 SS |
243 | (unsigned int) ring->cycle_state); |
244 | } | |
245 | } | |
246 | ring->enq_seg = ring->enq_seg->next; | |
247 | ring->enqueue = ring->enq_seg->trbs; | |
248 | next = ring->enqueue; | |
249 | } | |
66e49d87 SS |
250 | addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue); |
251 | if (ring == xhci->event_ring) | |
252 | xhci_dbg(xhci, "Event ring enq = 0x%llx (DMA)\n", addr); | |
253 | else if (ring == xhci->cmd_ring) | |
254 | xhci_dbg(xhci, "Command ring enq = 0x%llx (DMA)\n", addr); | |
255 | else | |
256 | xhci_dbg(xhci, "Ring enq = 0x%llx (DMA)\n", addr); | |
7f84eef0 SS |
257 | } |
258 | ||
259 | /* | |
260 | * Check to see if there's room to enqueue num_trbs on the ring. See rules | |
261 | * above. | |
262 | * FIXME: this would be simpler and faster if we just kept track of the number | |
263 | * of free TRBs in a ring. | |
264 | */ | |
265 | static int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring, | |
266 | unsigned int num_trbs) | |
267 | { | |
268 | int i; | |
269 | union xhci_trb *enq = ring->enqueue; | |
270 | struct xhci_segment *enq_seg = ring->enq_seg; | |
44ebd037 SS |
271 | struct xhci_segment *cur_seg; |
272 | unsigned int left_on_ring; | |
7f84eef0 | 273 | |
6c12db90 JY |
274 | /* If we are currently pointing to a link TRB, advance the |
275 | * enqueue pointer before checking for space */ | |
276 | while (last_trb(xhci, ring, enq_seg, enq)) { | |
277 | enq_seg = enq_seg->next; | |
278 | enq = enq_seg->trbs; | |
279 | } | |
280 | ||
7f84eef0 | 281 | /* Check if ring is empty */ |
44ebd037 SS |
282 | if (enq == ring->dequeue) { |
283 | /* Can't use link trbs */ | |
284 | left_on_ring = TRBS_PER_SEGMENT - 1; | |
285 | for (cur_seg = enq_seg->next; cur_seg != enq_seg; | |
286 | cur_seg = cur_seg->next) | |
287 | left_on_ring += TRBS_PER_SEGMENT - 1; | |
288 | ||
289 | /* Always need one TRB free in the ring. */ | |
290 | left_on_ring -= 1; | |
291 | if (num_trbs > left_on_ring) { | |
292 | xhci_warn(xhci, "Not enough room on ring; " | |
293 | "need %u TRBs, %u TRBs left\n", | |
294 | num_trbs, left_on_ring); | |
295 | return 0; | |
296 | } | |
7f84eef0 | 297 | return 1; |
44ebd037 | 298 | } |
7f84eef0 SS |
299 | /* Make sure there's an extra empty TRB available */ |
300 | for (i = 0; i <= num_trbs; ++i) { | |
301 | if (enq == ring->dequeue) | |
302 | return 0; | |
303 | enq++; | |
304 | while (last_trb(xhci, ring, enq_seg, enq)) { | |
305 | enq_seg = enq_seg->next; | |
306 | enq = enq_seg->trbs; | |
307 | } | |
308 | } | |
309 | return 1; | |
310 | } | |
311 | ||
7f84eef0 | 312 | /* Ring the host controller doorbell after placing a command on the ring */ |
23e3be11 | 313 | void xhci_ring_cmd_db(struct xhci_hcd *xhci) |
7f84eef0 | 314 | { |
7f84eef0 | 315 | xhci_dbg(xhci, "// Ding dong!\n"); |
50d64676 | 316 | xhci_writel(xhci, DB_VALUE_HOST, &xhci->dba->doorbell[0]); |
7f84eef0 SS |
317 | /* Flush PCI posted writes */ |
318 | xhci_readl(xhci, &xhci->dba->doorbell[0]); | |
319 | } | |
320 | ||
be88fe4f | 321 | void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, |
ae636747 | 322 | unsigned int slot_id, |
e9df17eb SS |
323 | unsigned int ep_index, |
324 | unsigned int stream_id) | |
ae636747 | 325 | { |
28ccd296 | 326 | __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id]; |
50d64676 MW |
327 | struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index]; |
328 | unsigned int ep_state = ep->ep_state; | |
ae636747 | 329 | |
ae636747 | 330 | /* Don't ring the doorbell for this endpoint if there are pending |
50d64676 | 331 | * cancellations because we don't want to interrupt processing. |
8df75f42 SS |
332 | * We don't want to restart any stream rings if there's a set dequeue |
333 | * pointer command pending because the device can choose to start any | |
334 | * stream once the endpoint is on the HW schedule. | |
335 | * FIXME - check all the stream rings for pending cancellations. | |
ae636747 | 336 | */ |
50d64676 MW |
337 | if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) || |
338 | (ep_state & EP_HALTED)) | |
339 | return; | |
340 | xhci_writel(xhci, DB_VALUE(ep_index, stream_id), db_addr); | |
341 | /* The CPU has better things to do at this point than wait for a | |
342 | * write-posting flush. It'll get there soon enough. | |
343 | */ | |
ae636747 SS |
344 | } |
345 | ||
e9df17eb SS |
346 | /* Ring the doorbell for any rings with pending URBs */ |
347 | static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci, | |
348 | unsigned int slot_id, | |
349 | unsigned int ep_index) | |
350 | { | |
351 | unsigned int stream_id; | |
352 | struct xhci_virt_ep *ep; | |
353 | ||
354 | ep = &xhci->devs[slot_id]->eps[ep_index]; | |
355 | ||
356 | /* A ring has pending URBs if its TD list is not empty */ | |
357 | if (!(ep->ep_state & EP_HAS_STREAMS)) { | |
358 | if (!(list_empty(&ep->ring->td_list))) | |
be88fe4f | 359 | xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0); |
e9df17eb SS |
360 | return; |
361 | } | |
362 | ||
363 | for (stream_id = 1; stream_id < ep->stream_info->num_streams; | |
364 | stream_id++) { | |
365 | struct xhci_stream_info *stream_info = ep->stream_info; | |
366 | if (!list_empty(&stream_info->stream_rings[stream_id]->td_list)) | |
be88fe4f AX |
367 | xhci_ring_ep_doorbell(xhci, slot_id, ep_index, |
368 | stream_id); | |
e9df17eb SS |
369 | } |
370 | } | |
371 | ||
ae636747 SS |
372 | /* |
373 | * Find the segment that trb is in. Start searching in start_seg. | |
374 | * If we must move past a segment that has a link TRB with a toggle cycle state | |
375 | * bit set, then we will toggle the value pointed at by cycle_state. | |
376 | */ | |
377 | static struct xhci_segment *find_trb_seg( | |
378 | struct xhci_segment *start_seg, | |
379 | union xhci_trb *trb, int *cycle_state) | |
380 | { | |
381 | struct xhci_segment *cur_seg = start_seg; | |
382 | struct xhci_generic_trb *generic_trb; | |
383 | ||
384 | while (cur_seg->trbs > trb || | |
385 | &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) { | |
386 | generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic; | |
28ccd296 | 387 | if (le32_to_cpu(generic_trb->field[3]) & LINK_TOGGLE) |
ba0a4d9a | 388 | *cycle_state ^= 0x1; |
ae636747 SS |
389 | cur_seg = cur_seg->next; |
390 | if (cur_seg == start_seg) | |
391 | /* Looped over the entire list. Oops! */ | |
326b4810 | 392 | return NULL; |
ae636747 SS |
393 | } |
394 | return cur_seg; | |
395 | } | |
396 | ||
021bff91 SS |
397 | |
398 | static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci, | |
399 | unsigned int slot_id, unsigned int ep_index, | |
400 | unsigned int stream_id) | |
401 | { | |
402 | struct xhci_virt_ep *ep; | |
403 | ||
404 | ep = &xhci->devs[slot_id]->eps[ep_index]; | |
405 | /* Common case: no streams */ | |
406 | if (!(ep->ep_state & EP_HAS_STREAMS)) | |
407 | return ep->ring; | |
408 | ||
409 | if (stream_id == 0) { | |
410 | xhci_warn(xhci, | |
411 | "WARN: Slot ID %u, ep index %u has streams, " | |
412 | "but URB has no stream ID.\n", | |
413 | slot_id, ep_index); | |
414 | return NULL; | |
415 | } | |
416 | ||
417 | if (stream_id < ep->stream_info->num_streams) | |
418 | return ep->stream_info->stream_rings[stream_id]; | |
419 | ||
420 | xhci_warn(xhci, | |
421 | "WARN: Slot ID %u, ep index %u has " | |
422 | "stream IDs 1 to %u allocated, " | |
423 | "but stream ID %u is requested.\n", | |
424 | slot_id, ep_index, | |
425 | ep->stream_info->num_streams - 1, | |
426 | stream_id); | |
427 | return NULL; | |
428 | } | |
429 | ||
430 | /* Get the right ring for the given URB. | |
431 | * If the endpoint supports streams, boundary check the URB's stream ID. | |
432 | * If the endpoint doesn't support streams, return the singular endpoint ring. | |
433 | */ | |
434 | static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci, | |
435 | struct urb *urb) | |
436 | { | |
437 | return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id, | |
438 | xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id); | |
439 | } | |
440 | ||
ae636747 SS |
441 | /* |
442 | * Move the xHC's endpoint ring dequeue pointer past cur_td. | |
443 | * Record the new state of the xHC's endpoint ring dequeue segment, | |
444 | * dequeue pointer, and new consumer cycle state in state. | |
445 | * Update our internal representation of the ring's dequeue pointer. | |
446 | * | |
447 | * We do this in three jumps: | |
448 | * - First we update our new ring state to be the same as when the xHC stopped. | |
449 | * - Then we traverse the ring to find the segment that contains | |
450 | * the last TRB in the TD. We toggle the xHC's new cycle state when we pass | |
451 | * any link TRBs with the toggle cycle bit set. | |
452 | * - Finally we move the dequeue state one TRB further, toggling the cycle bit | |
453 | * if we've moved it past a link TRB with the toggle cycle bit set. | |
28ccd296 ME |
454 | * |
455 | * Some of the uses of xhci_generic_trb are grotty, but if they're done | |
456 | * with correct __le32 accesses they should work fine. Only users of this are | |
457 | * in here. | |
ae636747 | 458 | */ |
c92bcfa7 | 459 | void xhci_find_new_dequeue_state(struct xhci_hcd *xhci, |
ae636747 | 460 | unsigned int slot_id, unsigned int ep_index, |
e9df17eb SS |
461 | unsigned int stream_id, struct xhci_td *cur_td, |
462 | struct xhci_dequeue_state *state) | |
ae636747 SS |
463 | { |
464 | struct xhci_virt_device *dev = xhci->devs[slot_id]; | |
e9df17eb | 465 | struct xhci_ring *ep_ring; |
ae636747 | 466 | struct xhci_generic_trb *trb; |
d115b048 | 467 | struct xhci_ep_ctx *ep_ctx; |
c92bcfa7 | 468 | dma_addr_t addr; |
ae636747 | 469 | |
e9df17eb SS |
470 | ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id, |
471 | ep_index, stream_id); | |
472 | if (!ep_ring) { | |
473 | xhci_warn(xhci, "WARN can't find new dequeue state " | |
474 | "for invalid stream ID %u.\n", | |
475 | stream_id); | |
476 | return; | |
477 | } | |
ae636747 | 478 | state->new_cycle_state = 0; |
c92bcfa7 | 479 | xhci_dbg(xhci, "Finding segment containing stopped TRB.\n"); |
ae636747 | 480 | state->new_deq_seg = find_trb_seg(cur_td->start_seg, |
63a0d9ab | 481 | dev->eps[ep_index].stopped_trb, |
ae636747 | 482 | &state->new_cycle_state); |
68e41c5d PZ |
483 | if (!state->new_deq_seg) { |
484 | WARN_ON(1); | |
485 | return; | |
486 | } | |
487 | ||
ae636747 | 488 | /* Dig out the cycle state saved by the xHC during the stop ep cmd */ |
c92bcfa7 | 489 | xhci_dbg(xhci, "Finding endpoint context\n"); |
d115b048 | 490 | ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index); |
28ccd296 | 491 | state->new_cycle_state = 0x1 & le64_to_cpu(ep_ctx->deq); |
ae636747 SS |
492 | |
493 | state->new_deq_ptr = cur_td->last_trb; | |
c92bcfa7 | 494 | xhci_dbg(xhci, "Finding segment containing last TRB in TD.\n"); |
ae636747 SS |
495 | state->new_deq_seg = find_trb_seg(state->new_deq_seg, |
496 | state->new_deq_ptr, | |
497 | &state->new_cycle_state); | |
68e41c5d PZ |
498 | if (!state->new_deq_seg) { |
499 | WARN_ON(1); | |
500 | return; | |
501 | } | |
ae636747 SS |
502 | |
503 | trb = &state->new_deq_ptr->generic; | |
28ccd296 ME |
504 | if ((le32_to_cpu(trb->field[3]) & TRB_TYPE_BITMASK) == |
505 | TRB_TYPE(TRB_LINK) && (le32_to_cpu(trb->field[3]) & LINK_TOGGLE)) | |
ba0a4d9a | 506 | state->new_cycle_state ^= 0x1; |
ae636747 SS |
507 | next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr); |
508 | ||
01a1fdb9 SS |
509 | /* |
510 | * If there is only one segment in a ring, find_trb_seg()'s while loop | |
511 | * will not run, and it will return before it has a chance to see if it | |
512 | * needs to toggle the cycle bit. It can't tell if the stalled transfer | |
513 | * ended just before the link TRB on a one-segment ring, or if the TD | |
514 | * wrapped around the top of the ring, because it doesn't have the TD in | |
515 | * question. Look for the one-segment case where stalled TRB's address | |
516 | * is greater than the new dequeue pointer address. | |
517 | */ | |
518 | if (ep_ring->first_seg == ep_ring->first_seg->next && | |
519 | state->new_deq_ptr < dev->eps[ep_index].stopped_trb) | |
520 | state->new_cycle_state ^= 0x1; | |
521 | xhci_dbg(xhci, "Cycle state = 0x%x\n", state->new_cycle_state); | |
522 | ||
ae636747 | 523 | /* Don't update the ring cycle state for the producer (us). */ |
c92bcfa7 SS |
524 | xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n", |
525 | state->new_deq_seg); | |
526 | addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr); | |
527 | xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n", | |
528 | (unsigned long long) addr); | |
ae636747 SS |
529 | } |
530 | ||
23e3be11 | 531 | static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring, |
ae636747 SS |
532 | struct xhci_td *cur_td) |
533 | { | |
534 | struct xhci_segment *cur_seg; | |
535 | union xhci_trb *cur_trb; | |
536 | ||
537 | for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb; | |
538 | true; | |
539 | next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) { | |
28ccd296 ME |
540 | if ((le32_to_cpu(cur_trb->generic.field[3]) & TRB_TYPE_BITMASK) |
541 | == TRB_TYPE(TRB_LINK)) { | |
ae636747 SS |
542 | /* Unchain any chained Link TRBs, but |
543 | * leave the pointers intact. | |
544 | */ | |
28ccd296 | 545 | cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN); |
ae636747 | 546 | xhci_dbg(xhci, "Cancel (unchain) link TRB\n"); |
700e2052 GKH |
547 | xhci_dbg(xhci, "Address = %p (0x%llx dma); " |
548 | "in seg %p (0x%llx dma)\n", | |
549 | cur_trb, | |
23e3be11 | 550 | (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb), |
700e2052 GKH |
551 | cur_seg, |
552 | (unsigned long long)cur_seg->dma); | |
ae636747 SS |
553 | } else { |
554 | cur_trb->generic.field[0] = 0; | |
555 | cur_trb->generic.field[1] = 0; | |
556 | cur_trb->generic.field[2] = 0; | |
557 | /* Preserve only the cycle bit of this TRB */ | |
28ccd296 ME |
558 | cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE); |
559 | cur_trb->generic.field[3] |= cpu_to_le32( | |
560 | TRB_TYPE(TRB_TR_NOOP)); | |
700e2052 GKH |
561 | xhci_dbg(xhci, "Cancel TRB %p (0x%llx dma) " |
562 | "in seg %p (0x%llx dma)\n", | |
563 | cur_trb, | |
23e3be11 | 564 | (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb), |
700e2052 GKH |
565 | cur_seg, |
566 | (unsigned long long)cur_seg->dma); | |
ae636747 SS |
567 | } |
568 | if (cur_trb == cur_td->last_trb) | |
569 | break; | |
570 | } | |
571 | } | |
572 | ||
573 | static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id, | |
e9df17eb SS |
574 | unsigned int ep_index, unsigned int stream_id, |
575 | struct xhci_segment *deq_seg, | |
ae636747 SS |
576 | union xhci_trb *deq_ptr, u32 cycle_state); |
577 | ||
c92bcfa7 | 578 | void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci, |
63a0d9ab | 579 | unsigned int slot_id, unsigned int ep_index, |
e9df17eb | 580 | unsigned int stream_id, |
63a0d9ab | 581 | struct xhci_dequeue_state *deq_state) |
c92bcfa7 | 582 | { |
63a0d9ab SS |
583 | struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index]; |
584 | ||
c92bcfa7 SS |
585 | xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), " |
586 | "new deq ptr = %p (0x%llx dma), new cycle = %u\n", | |
587 | deq_state->new_deq_seg, | |
588 | (unsigned long long)deq_state->new_deq_seg->dma, | |
589 | deq_state->new_deq_ptr, | |
590 | (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr), | |
591 | deq_state->new_cycle_state); | |
e9df17eb | 592 | queue_set_tr_deq(xhci, slot_id, ep_index, stream_id, |
c92bcfa7 SS |
593 | deq_state->new_deq_seg, |
594 | deq_state->new_deq_ptr, | |
595 | (u32) deq_state->new_cycle_state); | |
596 | /* Stop the TD queueing code from ringing the doorbell until | |
597 | * this command completes. The HC won't set the dequeue pointer | |
598 | * if the ring is running, and ringing the doorbell starts the | |
599 | * ring running. | |
600 | */ | |
63a0d9ab | 601 | ep->ep_state |= SET_DEQ_PENDING; |
c92bcfa7 SS |
602 | } |
603 | ||
575688e1 | 604 | static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci, |
6f5165cf SS |
605 | struct xhci_virt_ep *ep) |
606 | { | |
607 | ep->ep_state &= ~EP_HALT_PENDING; | |
608 | /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the | |
609 | * timer is running on another CPU, we don't decrement stop_cmds_pending | |
610 | * (since we didn't successfully stop the watchdog timer). | |
611 | */ | |
612 | if (del_timer(&ep->stop_cmd_timer)) | |
613 | ep->stop_cmds_pending--; | |
614 | } | |
615 | ||
616 | /* Must be called with xhci->lock held in interrupt context */ | |
617 | static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci, | |
618 | struct xhci_td *cur_td, int status, char *adjective) | |
619 | { | |
214f76f7 | 620 | struct usb_hcd *hcd; |
8e51adcc AX |
621 | struct urb *urb; |
622 | struct urb_priv *urb_priv; | |
6f5165cf | 623 | |
8e51adcc AX |
624 | urb = cur_td->urb; |
625 | urb_priv = urb->hcpriv; | |
626 | urb_priv->td_cnt++; | |
214f76f7 | 627 | hcd = bus_to_hcd(urb->dev->bus); |
6f5165cf | 628 | |
8e51adcc AX |
629 | /* Only giveback urb when this is the last td in urb */ |
630 | if (urb_priv->td_cnt == urb_priv->length) { | |
c41136b0 AX |
631 | if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { |
632 | xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--; | |
633 | if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) { | |
634 | if (xhci->quirks & XHCI_AMD_PLL_FIX) | |
635 | usb_amd_quirk_pll_enable(); | |
636 | } | |
637 | } | |
8e51adcc AX |
638 | usb_hcd_unlink_urb_from_ep(hcd, urb); |
639 | xhci_dbg(xhci, "Giveback %s URB %p\n", adjective, urb); | |
640 | ||
641 | spin_unlock(&xhci->lock); | |
642 | usb_hcd_giveback_urb(hcd, urb, status); | |
643 | xhci_urb_free_priv(xhci, urb_priv); | |
644 | spin_lock(&xhci->lock); | |
645 | xhci_dbg(xhci, "%s URB given back\n", adjective); | |
646 | } | |
6f5165cf SS |
647 | } |
648 | ||
ae636747 SS |
649 | /* |
650 | * When we get a command completion for a Stop Endpoint Command, we need to | |
651 | * unlink any cancelled TDs from the ring. There are two ways to do that: | |
652 | * | |
653 | * 1. If the HW was in the middle of processing the TD that needs to be | |
654 | * cancelled, then we must move the ring's dequeue pointer past the last TRB | |
655 | * in the TD with a Set Dequeue Pointer Command. | |
656 | * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain | |
657 | * bit cleared) so that the HW will skip over them. | |
658 | */ | |
659 | static void handle_stopped_endpoint(struct xhci_hcd *xhci, | |
be88fe4f | 660 | union xhci_trb *trb, struct xhci_event_cmd *event) |
ae636747 SS |
661 | { |
662 | unsigned int slot_id; | |
663 | unsigned int ep_index; | |
be88fe4f | 664 | struct xhci_virt_device *virt_dev; |
ae636747 | 665 | struct xhci_ring *ep_ring; |
63a0d9ab | 666 | struct xhci_virt_ep *ep; |
ae636747 | 667 | struct list_head *entry; |
326b4810 | 668 | struct xhci_td *cur_td = NULL; |
ae636747 SS |
669 | struct xhci_td *last_unlinked_td; |
670 | ||
c92bcfa7 | 671 | struct xhci_dequeue_state deq_state; |
ae636747 | 672 | |
be88fe4f | 673 | if (unlikely(TRB_TO_SUSPEND_PORT( |
28ccd296 | 674 | le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])))) { |
be88fe4f | 675 | slot_id = TRB_TO_SLOT_ID( |
28ccd296 | 676 | le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])); |
be88fe4f AX |
677 | virt_dev = xhci->devs[slot_id]; |
678 | if (virt_dev) | |
679 | handle_cmd_in_cmd_wait_list(xhci, virt_dev, | |
680 | event); | |
681 | else | |
682 | xhci_warn(xhci, "Stop endpoint command " | |
683 | "completion for disabled slot %u\n", | |
684 | slot_id); | |
685 | return; | |
686 | } | |
687 | ||
ae636747 | 688 | memset(&deq_state, 0, sizeof(deq_state)); |
28ccd296 ME |
689 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3])); |
690 | ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); | |
63a0d9ab | 691 | ep = &xhci->devs[slot_id]->eps[ep_index]; |
ae636747 | 692 | |
678539cf | 693 | if (list_empty(&ep->cancelled_td_list)) { |
6f5165cf | 694 | xhci_stop_watchdog_timer_in_irq(xhci, ep); |
e9df17eb | 695 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); |
ae636747 | 696 | return; |
678539cf | 697 | } |
ae636747 SS |
698 | |
699 | /* Fix up the ep ring first, so HW stops executing cancelled TDs. | |
700 | * We have the xHCI lock, so nothing can modify this list until we drop | |
701 | * it. We're also in the event handler, so we can't get re-interrupted | |
702 | * if another Stop Endpoint command completes | |
703 | */ | |
63a0d9ab | 704 | list_for_each(entry, &ep->cancelled_td_list) { |
ae636747 | 705 | cur_td = list_entry(entry, struct xhci_td, cancelled_td_list); |
700e2052 GKH |
706 | xhci_dbg(xhci, "Cancelling TD starting at %p, 0x%llx (dma).\n", |
707 | cur_td->first_trb, | |
23e3be11 | 708 | (unsigned long long)xhci_trb_virt_to_dma(cur_td->start_seg, cur_td->first_trb)); |
e9df17eb SS |
709 | ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb); |
710 | if (!ep_ring) { | |
711 | /* This shouldn't happen unless a driver is mucking | |
712 | * with the stream ID after submission. This will | |
713 | * leave the TD on the hardware ring, and the hardware | |
714 | * will try to execute it, and may access a buffer | |
715 | * that has already been freed. In the best case, the | |
716 | * hardware will execute it, and the event handler will | |
717 | * ignore the completion event for that TD, since it was | |
718 | * removed from the td_list for that endpoint. In | |
719 | * short, don't muck with the stream ID after | |
720 | * submission. | |
721 | */ | |
722 | xhci_warn(xhci, "WARN Cancelled URB %p " | |
723 | "has invalid stream ID %u.\n", | |
724 | cur_td->urb, | |
725 | cur_td->urb->stream_id); | |
726 | goto remove_finished_td; | |
727 | } | |
ae636747 SS |
728 | /* |
729 | * If we stopped on the TD we need to cancel, then we have to | |
730 | * move the xHC endpoint ring dequeue pointer past this TD. | |
731 | */ | |
63a0d9ab | 732 | if (cur_td == ep->stopped_td) |
e9df17eb SS |
733 | xhci_find_new_dequeue_state(xhci, slot_id, ep_index, |
734 | cur_td->urb->stream_id, | |
735 | cur_td, &deq_state); | |
ae636747 SS |
736 | else |
737 | td_to_noop(xhci, ep_ring, cur_td); | |
e9df17eb | 738 | remove_finished_td: |
ae636747 SS |
739 | /* |
740 | * The event handler won't see a completion for this TD anymore, | |
741 | * so remove it from the endpoint ring's TD list. Keep it in | |
742 | * the cancelled TD list for URB completion later. | |
743 | */ | |
744 | list_del(&cur_td->td_list); | |
ae636747 SS |
745 | } |
746 | last_unlinked_td = cur_td; | |
6f5165cf | 747 | xhci_stop_watchdog_timer_in_irq(xhci, ep); |
ae636747 SS |
748 | |
749 | /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */ | |
750 | if (deq_state.new_deq_ptr && deq_state.new_deq_seg) { | |
63a0d9ab | 751 | xhci_queue_new_dequeue_state(xhci, |
e9df17eb SS |
752 | slot_id, ep_index, |
753 | ep->stopped_td->urb->stream_id, | |
754 | &deq_state); | |
ac9d8fe7 | 755 | xhci_ring_cmd_db(xhci); |
ae636747 | 756 | } else { |
e9df17eb SS |
757 | /* Otherwise ring the doorbell(s) to restart queued transfers */ |
758 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); | |
ae636747 | 759 | } |
1624ae1c SS |
760 | ep->stopped_td = NULL; |
761 | ep->stopped_trb = NULL; | |
ae636747 SS |
762 | |
763 | /* | |
764 | * Drop the lock and complete the URBs in the cancelled TD list. | |
765 | * New TDs to be cancelled might be added to the end of the list before | |
766 | * we can complete all the URBs for the TDs we already unlinked. | |
767 | * So stop when we've completed the URB for the last TD we unlinked. | |
768 | */ | |
769 | do { | |
63a0d9ab | 770 | cur_td = list_entry(ep->cancelled_td_list.next, |
ae636747 SS |
771 | struct xhci_td, cancelled_td_list); |
772 | list_del(&cur_td->cancelled_td_list); | |
773 | ||
774 | /* Clean up the cancelled URB */ | |
ae636747 SS |
775 | /* Doesn't matter what we pass for status, since the core will |
776 | * just overwrite it (because the URB has been unlinked). | |
777 | */ | |
6f5165cf | 778 | xhci_giveback_urb_in_irq(xhci, cur_td, 0, "cancelled"); |
ae636747 | 779 | |
6f5165cf SS |
780 | /* Stop processing the cancelled list if the watchdog timer is |
781 | * running. | |
782 | */ | |
783 | if (xhci->xhc_state & XHCI_STATE_DYING) | |
784 | return; | |
ae636747 SS |
785 | } while (cur_td != last_unlinked_td); |
786 | ||
787 | /* Return to the event handler with xhci->lock re-acquired */ | |
788 | } | |
789 | ||
6f5165cf SS |
790 | /* Watchdog timer function for when a stop endpoint command fails to complete. |
791 | * In this case, we assume the host controller is broken or dying or dead. The | |
792 | * host may still be completing some other events, so we have to be careful to | |
793 | * let the event ring handler and the URB dequeueing/enqueueing functions know | |
794 | * through xhci->state. | |
795 | * | |
796 | * The timer may also fire if the host takes a very long time to respond to the | |
797 | * command, and the stop endpoint command completion handler cannot delete the | |
798 | * timer before the timer function is called. Another endpoint cancellation may | |
799 | * sneak in before the timer function can grab the lock, and that may queue | |
800 | * another stop endpoint command and add the timer back. So we cannot use a | |
801 | * simple flag to say whether there is a pending stop endpoint command for a | |
802 | * particular endpoint. | |
803 | * | |
804 | * Instead we use a combination of that flag and a counter for the number of | |
805 | * pending stop endpoint commands. If the timer is the tail end of the last | |
806 | * stop endpoint command, and the endpoint's command is still pending, we assume | |
807 | * the host is dying. | |
808 | */ | |
809 | void xhci_stop_endpoint_command_watchdog(unsigned long arg) | |
810 | { | |
811 | struct xhci_hcd *xhci; | |
812 | struct xhci_virt_ep *ep; | |
813 | struct xhci_virt_ep *temp_ep; | |
814 | struct xhci_ring *ring; | |
815 | struct xhci_td *cur_td; | |
816 | int ret, i, j; | |
817 | ||
818 | ep = (struct xhci_virt_ep *) arg; | |
819 | xhci = ep->xhci; | |
820 | ||
821 | spin_lock(&xhci->lock); | |
822 | ||
823 | ep->stop_cmds_pending--; | |
824 | if (xhci->xhc_state & XHCI_STATE_DYING) { | |
825 | xhci_dbg(xhci, "Stop EP timer ran, but another timer marked " | |
826 | "xHCI as DYING, exiting.\n"); | |
827 | spin_unlock(&xhci->lock); | |
828 | return; | |
829 | } | |
830 | if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) { | |
831 | xhci_dbg(xhci, "Stop EP timer ran, but no command pending, " | |
832 | "exiting.\n"); | |
833 | spin_unlock(&xhci->lock); | |
834 | return; | |
835 | } | |
836 | ||
837 | xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n"); | |
838 | xhci_warn(xhci, "Assuming host is dying, halting host.\n"); | |
839 | /* Oops, HC is dead or dying or at least not responding to the stop | |
840 | * endpoint command. | |
841 | */ | |
842 | xhci->xhc_state |= XHCI_STATE_DYING; | |
843 | /* Disable interrupts from the host controller and start halting it */ | |
844 | xhci_quiesce(xhci); | |
845 | spin_unlock(&xhci->lock); | |
846 | ||
847 | ret = xhci_halt(xhci); | |
848 | ||
849 | spin_lock(&xhci->lock); | |
850 | if (ret < 0) { | |
851 | /* This is bad; the host is not responding to commands and it's | |
852 | * not allowing itself to be halted. At least interrupts are | |
ac04e6ff | 853 | * disabled. If we call usb_hc_died(), it will attempt to |
6f5165cf SS |
854 | * disconnect all device drivers under this host. Those |
855 | * disconnect() methods will wait for all URBs to be unlinked, | |
856 | * so we must complete them. | |
857 | */ | |
858 | xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n"); | |
859 | xhci_warn(xhci, "Completing active URBs anyway.\n"); | |
860 | /* We could turn all TDs on the rings to no-ops. This won't | |
861 | * help if the host has cached part of the ring, and is slow if | |
862 | * we want to preserve the cycle bit. Skip it and hope the host | |
863 | * doesn't touch the memory. | |
864 | */ | |
865 | } | |
866 | for (i = 0; i < MAX_HC_SLOTS; i++) { | |
867 | if (!xhci->devs[i]) | |
868 | continue; | |
869 | for (j = 0; j < 31; j++) { | |
870 | temp_ep = &xhci->devs[i]->eps[j]; | |
871 | ring = temp_ep->ring; | |
872 | if (!ring) | |
873 | continue; | |
874 | xhci_dbg(xhci, "Killing URBs for slot ID %u, " | |
875 | "ep index %u\n", i, j); | |
876 | while (!list_empty(&ring->td_list)) { | |
877 | cur_td = list_first_entry(&ring->td_list, | |
878 | struct xhci_td, | |
879 | td_list); | |
880 | list_del(&cur_td->td_list); | |
881 | if (!list_empty(&cur_td->cancelled_td_list)) | |
882 | list_del(&cur_td->cancelled_td_list); | |
883 | xhci_giveback_urb_in_irq(xhci, cur_td, | |
884 | -ESHUTDOWN, "killed"); | |
885 | } | |
886 | while (!list_empty(&temp_ep->cancelled_td_list)) { | |
887 | cur_td = list_first_entry( | |
888 | &temp_ep->cancelled_td_list, | |
889 | struct xhci_td, | |
890 | cancelled_td_list); | |
891 | list_del(&cur_td->cancelled_td_list); | |
892 | xhci_giveback_urb_in_irq(xhci, cur_td, | |
893 | -ESHUTDOWN, "killed"); | |
894 | } | |
895 | } | |
896 | } | |
897 | spin_unlock(&xhci->lock); | |
6f5165cf | 898 | xhci_dbg(xhci, "Calling usb_hc_died()\n"); |
f6ff0ac8 | 899 | usb_hc_died(xhci_to_hcd(xhci)->primary_hcd); |
6f5165cf SS |
900 | xhci_dbg(xhci, "xHCI host controller is dead.\n"); |
901 | } | |
902 | ||
ae636747 SS |
903 | /* |
904 | * When we get a completion for a Set Transfer Ring Dequeue Pointer command, | |
905 | * we need to clear the set deq pending flag in the endpoint ring state, so that | |
906 | * the TD queueing code can ring the doorbell again. We also need to ring the | |
907 | * endpoint doorbell to restart the ring, but only if there aren't more | |
908 | * cancellations pending. | |
909 | */ | |
910 | static void handle_set_deq_completion(struct xhci_hcd *xhci, | |
911 | struct xhci_event_cmd *event, | |
912 | union xhci_trb *trb) | |
913 | { | |
914 | unsigned int slot_id; | |
915 | unsigned int ep_index; | |
e9df17eb | 916 | unsigned int stream_id; |
ae636747 SS |
917 | struct xhci_ring *ep_ring; |
918 | struct xhci_virt_device *dev; | |
d115b048 JY |
919 | struct xhci_ep_ctx *ep_ctx; |
920 | struct xhci_slot_ctx *slot_ctx; | |
ae636747 | 921 | |
28ccd296 ME |
922 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3])); |
923 | ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); | |
924 | stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2])); | |
ae636747 | 925 | dev = xhci->devs[slot_id]; |
e9df17eb SS |
926 | |
927 | ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id); | |
928 | if (!ep_ring) { | |
929 | xhci_warn(xhci, "WARN Set TR deq ptr command for " | |
930 | "freed stream ID %u\n", | |
931 | stream_id); | |
932 | /* XXX: Harmless??? */ | |
933 | dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING; | |
934 | return; | |
935 | } | |
936 | ||
d115b048 JY |
937 | ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index); |
938 | slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx); | |
ae636747 | 939 | |
28ccd296 | 940 | if (GET_COMP_CODE(le32_to_cpu(event->status)) != COMP_SUCCESS) { |
ae636747 SS |
941 | unsigned int ep_state; |
942 | unsigned int slot_state; | |
943 | ||
28ccd296 | 944 | switch (GET_COMP_CODE(le32_to_cpu(event->status))) { |
ae636747 SS |
945 | case COMP_TRB_ERR: |
946 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because " | |
947 | "of stream ID configuration\n"); | |
948 | break; | |
949 | case COMP_CTX_STATE: | |
950 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due " | |
951 | "to incorrect slot or ep state.\n"); | |
28ccd296 | 952 | ep_state = le32_to_cpu(ep_ctx->ep_info); |
ae636747 | 953 | ep_state &= EP_STATE_MASK; |
28ccd296 | 954 | slot_state = le32_to_cpu(slot_ctx->dev_state); |
ae636747 SS |
955 | slot_state = GET_SLOT_STATE(slot_state); |
956 | xhci_dbg(xhci, "Slot state = %u, EP state = %u\n", | |
957 | slot_state, ep_state); | |
958 | break; | |
959 | case COMP_EBADSLT: | |
960 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because " | |
961 | "slot %u was not enabled.\n", slot_id); | |
962 | break; | |
963 | default: | |
964 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown " | |
965 | "completion code of %u.\n", | |
28ccd296 | 966 | GET_COMP_CODE(le32_to_cpu(event->status))); |
ae636747 SS |
967 | break; |
968 | } | |
969 | /* OK what do we do now? The endpoint state is hosed, and we | |
970 | * should never get to this point if the synchronization between | |
971 | * queueing, and endpoint state are correct. This might happen | |
972 | * if the device gets disconnected after we've finished | |
973 | * cancelling URBs, which might not be an error... | |
974 | */ | |
975 | } else { | |
8e595a5d | 976 | xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n", |
28ccd296 | 977 | le64_to_cpu(ep_ctx->deq)); |
bf161e85 | 978 | if (xhci_trb_virt_to_dma(dev->eps[ep_index].queued_deq_seg, |
28ccd296 ME |
979 | dev->eps[ep_index].queued_deq_ptr) == |
980 | (le64_to_cpu(ep_ctx->deq) & ~(EP_CTX_CYCLE_MASK))) { | |
bf161e85 SS |
981 | /* Update the ring's dequeue segment and dequeue pointer |
982 | * to reflect the new position. | |
983 | */ | |
984 | ep_ring->deq_seg = dev->eps[ep_index].queued_deq_seg; | |
985 | ep_ring->dequeue = dev->eps[ep_index].queued_deq_ptr; | |
986 | } else { | |
987 | xhci_warn(xhci, "Mismatch between completed Set TR Deq " | |
988 | "Ptr command & xHCI internal state.\n"); | |
989 | xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n", | |
990 | dev->eps[ep_index].queued_deq_seg, | |
991 | dev->eps[ep_index].queued_deq_ptr); | |
992 | } | |
ae636747 SS |
993 | } |
994 | ||
63a0d9ab | 995 | dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING; |
bf161e85 SS |
996 | dev->eps[ep_index].queued_deq_seg = NULL; |
997 | dev->eps[ep_index].queued_deq_ptr = NULL; | |
e9df17eb SS |
998 | /* Restart any rings with pending URBs */ |
999 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); | |
ae636747 SS |
1000 | } |
1001 | ||
a1587d97 SS |
1002 | static void handle_reset_ep_completion(struct xhci_hcd *xhci, |
1003 | struct xhci_event_cmd *event, | |
1004 | union xhci_trb *trb) | |
1005 | { | |
1006 | int slot_id; | |
1007 | unsigned int ep_index; | |
1008 | ||
28ccd296 ME |
1009 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3])); |
1010 | ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); | |
a1587d97 SS |
1011 | /* This command will only fail if the endpoint wasn't halted, |
1012 | * but we don't care. | |
1013 | */ | |
1014 | xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n", | |
28ccd296 | 1015 | (unsigned int) GET_COMP_CODE(le32_to_cpu(event->status))); |
a1587d97 | 1016 | |
ac9d8fe7 SS |
1017 | /* HW with the reset endpoint quirk needs to have a configure endpoint |
1018 | * command complete before the endpoint can be used. Queue that here | |
1019 | * because the HW can't handle two commands being queued in a row. | |
1020 | */ | |
1021 | if (xhci->quirks & XHCI_RESET_EP_QUIRK) { | |
1022 | xhci_dbg(xhci, "Queueing configure endpoint command\n"); | |
1023 | xhci_queue_configure_endpoint(xhci, | |
913a8a34 SS |
1024 | xhci->devs[slot_id]->in_ctx->dma, slot_id, |
1025 | false); | |
ac9d8fe7 SS |
1026 | xhci_ring_cmd_db(xhci); |
1027 | } else { | |
e9df17eb | 1028 | /* Clear our internal halted state and restart the ring(s) */ |
63a0d9ab | 1029 | xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED; |
e9df17eb | 1030 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); |
ac9d8fe7 | 1031 | } |
a1587d97 | 1032 | } |
ae636747 | 1033 | |
a50c8aa9 SS |
1034 | /* Check to see if a command in the device's command queue matches this one. |
1035 | * Signal the completion or free the command, and return 1. Return 0 if the | |
1036 | * completed command isn't at the head of the command list. | |
1037 | */ | |
1038 | static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci, | |
1039 | struct xhci_virt_device *virt_dev, | |
1040 | struct xhci_event_cmd *event) | |
1041 | { | |
1042 | struct xhci_command *command; | |
1043 | ||
1044 | if (list_empty(&virt_dev->cmd_list)) | |
1045 | return 0; | |
1046 | ||
1047 | command = list_entry(virt_dev->cmd_list.next, | |
1048 | struct xhci_command, cmd_list); | |
1049 | if (xhci->cmd_ring->dequeue != command->command_trb) | |
1050 | return 0; | |
1051 | ||
28ccd296 | 1052 | command->status = GET_COMP_CODE(le32_to_cpu(event->status)); |
a50c8aa9 SS |
1053 | list_del(&command->cmd_list); |
1054 | if (command->completion) | |
1055 | complete(command->completion); | |
1056 | else | |
1057 | xhci_free_command(xhci, command); | |
1058 | return 1; | |
1059 | } | |
1060 | ||
7f84eef0 SS |
1061 | static void handle_cmd_completion(struct xhci_hcd *xhci, |
1062 | struct xhci_event_cmd *event) | |
1063 | { | |
28ccd296 | 1064 | int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
7f84eef0 SS |
1065 | u64 cmd_dma; |
1066 | dma_addr_t cmd_dequeue_dma; | |
ac9d8fe7 | 1067 | struct xhci_input_control_ctx *ctrl_ctx; |
913a8a34 | 1068 | struct xhci_virt_device *virt_dev; |
ac9d8fe7 SS |
1069 | unsigned int ep_index; |
1070 | struct xhci_ring *ep_ring; | |
1071 | unsigned int ep_state; | |
7f84eef0 | 1072 | |
28ccd296 | 1073 | cmd_dma = le64_to_cpu(event->cmd_trb); |
23e3be11 | 1074 | cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg, |
7f84eef0 SS |
1075 | xhci->cmd_ring->dequeue); |
1076 | /* Is the command ring deq ptr out of sync with the deq seg ptr? */ | |
1077 | if (cmd_dequeue_dma == 0) { | |
1078 | xhci->error_bitmask |= 1 << 4; | |
1079 | return; | |
1080 | } | |
1081 | /* Does the DMA address match our internal dequeue pointer address? */ | |
1082 | if (cmd_dma != (u64) cmd_dequeue_dma) { | |
1083 | xhci->error_bitmask |= 1 << 5; | |
1084 | return; | |
1085 | } | |
28ccd296 ME |
1086 | switch (le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]) |
1087 | & TRB_TYPE_BITMASK) { | |
3ffbba95 | 1088 | case TRB_TYPE(TRB_ENABLE_SLOT): |
28ccd296 | 1089 | if (GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_SUCCESS) |
3ffbba95 SS |
1090 | xhci->slot_id = slot_id; |
1091 | else | |
1092 | xhci->slot_id = 0; | |
1093 | complete(&xhci->addr_dev); | |
1094 | break; | |
1095 | case TRB_TYPE(TRB_DISABLE_SLOT): | |
1096 | if (xhci->devs[slot_id]) | |
1097 | xhci_free_virt_device(xhci, slot_id); | |
1098 | break; | |
f94e0186 | 1099 | case TRB_TYPE(TRB_CONFIG_EP): |
913a8a34 | 1100 | virt_dev = xhci->devs[slot_id]; |
a50c8aa9 | 1101 | if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event)) |
913a8a34 | 1102 | break; |
ac9d8fe7 SS |
1103 | /* |
1104 | * Configure endpoint commands can come from the USB core | |
1105 | * configuration or alt setting changes, or because the HW | |
1106 | * needed an extra configure endpoint command after a reset | |
8df75f42 SS |
1107 | * endpoint command or streams were being configured. |
1108 | * If the command was for a halted endpoint, the xHCI driver | |
1109 | * is not waiting on the configure endpoint command. | |
ac9d8fe7 SS |
1110 | */ |
1111 | ctrl_ctx = xhci_get_input_control_ctx(xhci, | |
913a8a34 | 1112 | virt_dev->in_ctx); |
ac9d8fe7 | 1113 | /* Input ctx add_flags are the endpoint index plus one */ |
28ccd296 | 1114 | ep_index = xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx->add_flags)) - 1; |
06df5729 | 1115 | /* A usb_set_interface() call directly after clearing a halted |
e9df17eb SS |
1116 | * condition may race on this quirky hardware. Not worth |
1117 | * worrying about, since this is prototype hardware. Not sure | |
1118 | * if this will work for streams, but streams support was | |
1119 | * untested on this prototype. | |
06df5729 | 1120 | */ |
ac9d8fe7 | 1121 | if (xhci->quirks & XHCI_RESET_EP_QUIRK && |
06df5729 | 1122 | ep_index != (unsigned int) -1 && |
28ccd296 ME |
1123 | le32_to_cpu(ctrl_ctx->add_flags) - SLOT_FLAG == |
1124 | le32_to_cpu(ctrl_ctx->drop_flags)) { | |
06df5729 SS |
1125 | ep_ring = xhci->devs[slot_id]->eps[ep_index].ring; |
1126 | ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state; | |
1127 | if (!(ep_state & EP_HALTED)) | |
1128 | goto bandwidth_change; | |
1129 | xhci_dbg(xhci, "Completed config ep cmd - " | |
1130 | "last ep index = %d, state = %d\n", | |
1131 | ep_index, ep_state); | |
e9df17eb | 1132 | /* Clear internal halted state and restart ring(s) */ |
63a0d9ab | 1133 | xhci->devs[slot_id]->eps[ep_index].ep_state &= |
ac9d8fe7 | 1134 | ~EP_HALTED; |
e9df17eb | 1135 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); |
06df5729 | 1136 | break; |
ac9d8fe7 | 1137 | } |
06df5729 SS |
1138 | bandwidth_change: |
1139 | xhci_dbg(xhci, "Completed config ep cmd\n"); | |
1140 | xhci->devs[slot_id]->cmd_status = | |
28ccd296 | 1141 | GET_COMP_CODE(le32_to_cpu(event->status)); |
06df5729 | 1142 | complete(&xhci->devs[slot_id]->cmd_completion); |
f94e0186 | 1143 | break; |
2d3f1fac | 1144 | case TRB_TYPE(TRB_EVAL_CONTEXT): |
ac1c1b7f SS |
1145 | virt_dev = xhci->devs[slot_id]; |
1146 | if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event)) | |
1147 | break; | |
28ccd296 | 1148 | xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status)); |
2d3f1fac SS |
1149 | complete(&xhci->devs[slot_id]->cmd_completion); |
1150 | break; | |
3ffbba95 | 1151 | case TRB_TYPE(TRB_ADDR_DEV): |
28ccd296 | 1152 | xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status)); |
3ffbba95 SS |
1153 | complete(&xhci->addr_dev); |
1154 | break; | |
ae636747 | 1155 | case TRB_TYPE(TRB_STOP_RING): |
be88fe4f | 1156 | handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue, event); |
ae636747 SS |
1157 | break; |
1158 | case TRB_TYPE(TRB_SET_DEQ): | |
1159 | handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue); | |
1160 | break; | |
7f84eef0 | 1161 | case TRB_TYPE(TRB_CMD_NOOP): |
7f84eef0 | 1162 | break; |
a1587d97 SS |
1163 | case TRB_TYPE(TRB_RESET_EP): |
1164 | handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue); | |
1165 | break; | |
2a8f82c4 SS |
1166 | case TRB_TYPE(TRB_RESET_DEV): |
1167 | xhci_dbg(xhci, "Completed reset device command.\n"); | |
1168 | slot_id = TRB_TO_SLOT_ID( | |
28ccd296 | 1169 | le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])); |
2a8f82c4 SS |
1170 | virt_dev = xhci->devs[slot_id]; |
1171 | if (virt_dev) | |
1172 | handle_cmd_in_cmd_wait_list(xhci, virt_dev, event); | |
1173 | else | |
1174 | xhci_warn(xhci, "Reset device command completion " | |
1175 | "for disabled slot %u\n", slot_id); | |
1176 | break; | |
0238634d SS |
1177 | case TRB_TYPE(TRB_NEC_GET_FW): |
1178 | if (!(xhci->quirks & XHCI_NEC_HOST)) { | |
1179 | xhci->error_bitmask |= 1 << 6; | |
1180 | break; | |
1181 | } | |
1182 | xhci_dbg(xhci, "NEC firmware version %2x.%02x\n", | |
28ccd296 ME |
1183 | NEC_FW_MAJOR(le32_to_cpu(event->status)), |
1184 | NEC_FW_MINOR(le32_to_cpu(event->status))); | |
0238634d | 1185 | break; |
7f84eef0 SS |
1186 | default: |
1187 | /* Skip over unknown commands on the event ring */ | |
1188 | xhci->error_bitmask |= 1 << 6; | |
1189 | break; | |
1190 | } | |
1191 | inc_deq(xhci, xhci->cmd_ring, false); | |
1192 | } | |
1193 | ||
0238634d SS |
1194 | static void handle_vendor_event(struct xhci_hcd *xhci, |
1195 | union xhci_trb *event) | |
1196 | { | |
1197 | u32 trb_type; | |
1198 | ||
28ccd296 | 1199 | trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3])); |
0238634d SS |
1200 | xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type); |
1201 | if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST)) | |
1202 | handle_cmd_completion(xhci, &event->event_cmd); | |
1203 | } | |
1204 | ||
f6ff0ac8 SS |
1205 | /* @port_id: the one-based port ID from the hardware (indexed from array of all |
1206 | * port registers -- USB 3.0 and USB 2.0). | |
1207 | * | |
1208 | * Returns a zero-based port number, which is suitable for indexing into each of | |
1209 | * the split roothubs' port arrays and bus state arrays. | |
1210 | */ | |
1211 | static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd, | |
1212 | struct xhci_hcd *xhci, u32 port_id) | |
1213 | { | |
1214 | unsigned int i; | |
1215 | unsigned int num_similar_speed_ports = 0; | |
1216 | ||
1217 | /* port_id from the hardware is 1-based, but port_array[], usb3_ports[], | |
1218 | * and usb2_ports are 0-based indexes. Count the number of similar | |
1219 | * speed ports, up to 1 port before this port. | |
1220 | */ | |
1221 | for (i = 0; i < (port_id - 1); i++) { | |
1222 | u8 port_speed = xhci->port_array[i]; | |
1223 | ||
1224 | /* | |
1225 | * Skip ports that don't have known speeds, or have duplicate | |
1226 | * Extended Capabilities port speed entries. | |
1227 | */ | |
22e04870 | 1228 | if (port_speed == 0 || port_speed == DUPLICATE_ENTRY) |
f6ff0ac8 SS |
1229 | continue; |
1230 | ||
1231 | /* | |
1232 | * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and | |
1233 | * 1.1 ports are under the USB 2.0 hub. If the port speed | |
1234 | * matches the device speed, it's a similar speed port. | |
1235 | */ | |
1236 | if ((port_speed == 0x03) == (hcd->speed == HCD_USB3)) | |
1237 | num_similar_speed_ports++; | |
1238 | } | |
1239 | return num_similar_speed_ports; | |
1240 | } | |
1241 | ||
0f2a7930 SS |
1242 | static void handle_port_status(struct xhci_hcd *xhci, |
1243 | union xhci_trb *event) | |
1244 | { | |
f6ff0ac8 | 1245 | struct usb_hcd *hcd; |
0f2a7930 | 1246 | u32 port_id; |
56192531 | 1247 | u32 temp, temp1; |
518e848e | 1248 | int max_ports; |
56192531 | 1249 | int slot_id; |
5308a91b | 1250 | unsigned int faked_port_index; |
f6ff0ac8 | 1251 | u8 major_revision; |
20b67cf5 | 1252 | struct xhci_bus_state *bus_state; |
28ccd296 | 1253 | __le32 __iomem **port_array; |
386139d7 | 1254 | bool bogus_port_status = false; |
0f2a7930 SS |
1255 | |
1256 | /* Port status change events always have a successful completion code */ | |
28ccd296 | 1257 | if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) { |
0f2a7930 SS |
1258 | xhci_warn(xhci, "WARN: xHC returned failed port status event\n"); |
1259 | xhci->error_bitmask |= 1 << 8; | |
1260 | } | |
28ccd296 | 1261 | port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0])); |
0f2a7930 SS |
1262 | xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id); |
1263 | ||
518e848e SS |
1264 | max_ports = HCS_MAX_PORTS(xhci->hcs_params1); |
1265 | if ((port_id <= 0) || (port_id > max_ports)) { | |
56192531 | 1266 | xhci_warn(xhci, "Invalid port id %d\n", port_id); |
386139d7 | 1267 | bogus_port_status = true; |
56192531 AX |
1268 | goto cleanup; |
1269 | } | |
1270 | ||
f6ff0ac8 SS |
1271 | /* Figure out which usb_hcd this port is attached to: |
1272 | * is it a USB 3.0 port or a USB 2.0/1.1 port? | |
1273 | */ | |
1274 | major_revision = xhci->port_array[port_id - 1]; | |
1275 | if (major_revision == 0) { | |
1276 | xhci_warn(xhci, "Event for port %u not in " | |
1277 | "Extended Capabilities, ignoring.\n", | |
1278 | port_id); | |
386139d7 | 1279 | bogus_port_status = true; |
f6ff0ac8 | 1280 | goto cleanup; |
5308a91b | 1281 | } |
22e04870 | 1282 | if (major_revision == DUPLICATE_ENTRY) { |
f6ff0ac8 SS |
1283 | xhci_warn(xhci, "Event for port %u duplicated in" |
1284 | "Extended Capabilities, ignoring.\n", | |
1285 | port_id); | |
386139d7 | 1286 | bogus_port_status = true; |
f6ff0ac8 SS |
1287 | goto cleanup; |
1288 | } | |
1289 | ||
1290 | /* | |
1291 | * Hardware port IDs reported by a Port Status Change Event include USB | |
1292 | * 3.0 and USB 2.0 ports. We want to check if the port has reported a | |
1293 | * resume event, but we first need to translate the hardware port ID | |
1294 | * into the index into the ports on the correct split roothub, and the | |
1295 | * correct bus_state structure. | |
1296 | */ | |
1297 | /* Find the right roothub. */ | |
1298 | hcd = xhci_to_hcd(xhci); | |
1299 | if ((major_revision == 0x03) != (hcd->speed == HCD_USB3)) | |
1300 | hcd = xhci->shared_hcd; | |
1301 | bus_state = &xhci->bus_state[hcd_index(hcd)]; | |
1302 | if (hcd->speed == HCD_USB3) | |
1303 | port_array = xhci->usb3_ports; | |
1304 | else | |
1305 | port_array = xhci->usb2_ports; | |
1306 | /* Find the faked port hub number */ | |
1307 | faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci, | |
1308 | port_id); | |
5308a91b | 1309 | |
5308a91b | 1310 | temp = xhci_readl(xhci, port_array[faked_port_index]); |
7111ebc9 | 1311 | if (hcd->state == HC_STATE_SUSPENDED) { |
56192531 AX |
1312 | xhci_dbg(xhci, "resume root hub\n"); |
1313 | usb_hcd_resume_root_hub(hcd); | |
1314 | } | |
1315 | ||
1316 | if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) { | |
1317 | xhci_dbg(xhci, "port resume event for port %d\n", port_id); | |
1318 | ||
1319 | temp1 = xhci_readl(xhci, &xhci->op_regs->command); | |
1320 | if (!(temp1 & CMD_RUN)) { | |
1321 | xhci_warn(xhci, "xHC is not running.\n"); | |
1322 | goto cleanup; | |
1323 | } | |
1324 | ||
1325 | if (DEV_SUPERSPEED(temp)) { | |
1326 | xhci_dbg(xhci, "resume SS port %d\n", port_id); | |
1327 | temp = xhci_port_state_to_neutral(temp); | |
1328 | temp &= ~PORT_PLS_MASK; | |
1329 | temp |= PORT_LINK_STROBE | XDEV_U0; | |
5308a91b | 1330 | xhci_writel(xhci, temp, port_array[faked_port_index]); |
5233630f SS |
1331 | slot_id = xhci_find_slot_id_by_port(hcd, xhci, |
1332 | faked_port_index); | |
56192531 AX |
1333 | if (!slot_id) { |
1334 | xhci_dbg(xhci, "slot_id is zero\n"); | |
1335 | goto cleanup; | |
1336 | } | |
1337 | xhci_ring_device(xhci, slot_id); | |
1338 | xhci_dbg(xhci, "resume SS port %d finished\n", port_id); | |
1339 | /* Clear PORT_PLC */ | |
5308a91b | 1340 | temp = xhci_readl(xhci, port_array[faked_port_index]); |
56192531 AX |
1341 | temp = xhci_port_state_to_neutral(temp); |
1342 | temp |= PORT_PLC; | |
5308a91b | 1343 | xhci_writel(xhci, temp, port_array[faked_port_index]); |
56192531 AX |
1344 | } else { |
1345 | xhci_dbg(xhci, "resume HS port %d\n", port_id); | |
f6ff0ac8 | 1346 | bus_state->resume_done[faked_port_index] = jiffies + |
56192531 AX |
1347 | msecs_to_jiffies(20); |
1348 | mod_timer(&hcd->rh_timer, | |
f6ff0ac8 | 1349 | bus_state->resume_done[faked_port_index]); |
56192531 AX |
1350 | /* Do the rest in GetPortStatus */ |
1351 | } | |
1352 | } | |
1353 | ||
1354 | cleanup: | |
0f2a7930 SS |
1355 | /* Update event ring dequeue pointer before dropping the lock */ |
1356 | inc_deq(xhci, xhci->event_ring, true); | |
0f2a7930 | 1357 | |
386139d7 SS |
1358 | /* Don't make the USB core poll the roothub if we got a bad port status |
1359 | * change event. Besides, at that point we can't tell which roothub | |
1360 | * (USB 2.0 or USB 3.0) to kick. | |
1361 | */ | |
1362 | if (bogus_port_status) | |
1363 | return; | |
1364 | ||
0f2a7930 SS |
1365 | spin_unlock(&xhci->lock); |
1366 | /* Pass this up to the core */ | |
f6ff0ac8 | 1367 | usb_hcd_poll_rh_status(hcd); |
0f2a7930 SS |
1368 | spin_lock(&xhci->lock); |
1369 | } | |
1370 | ||
d0e96f5a SS |
1371 | /* |
1372 | * This TD is defined by the TRBs starting at start_trb in start_seg and ending | |
1373 | * at end_trb, which may be in another segment. If the suspect DMA address is a | |
1374 | * TRB in this TD, this function returns that TRB's segment. Otherwise it | |
1375 | * returns 0. | |
1376 | */ | |
6648f29d | 1377 | struct xhci_segment *trb_in_td(struct xhci_segment *start_seg, |
d0e96f5a SS |
1378 | union xhci_trb *start_trb, |
1379 | union xhci_trb *end_trb, | |
1380 | dma_addr_t suspect_dma) | |
1381 | { | |
1382 | dma_addr_t start_dma; | |
1383 | dma_addr_t end_seg_dma; | |
1384 | dma_addr_t end_trb_dma; | |
1385 | struct xhci_segment *cur_seg; | |
1386 | ||
23e3be11 | 1387 | start_dma = xhci_trb_virt_to_dma(start_seg, start_trb); |
d0e96f5a SS |
1388 | cur_seg = start_seg; |
1389 | ||
1390 | do { | |
2fa88daa | 1391 | if (start_dma == 0) |
326b4810 | 1392 | return NULL; |
ae636747 | 1393 | /* We may get an event for a Link TRB in the middle of a TD */ |
23e3be11 | 1394 | end_seg_dma = xhci_trb_virt_to_dma(cur_seg, |
2fa88daa | 1395 | &cur_seg->trbs[TRBS_PER_SEGMENT - 1]); |
d0e96f5a | 1396 | /* If the end TRB isn't in this segment, this is set to 0 */ |
23e3be11 | 1397 | end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb); |
d0e96f5a SS |
1398 | |
1399 | if (end_trb_dma > 0) { | |
1400 | /* The end TRB is in this segment, so suspect should be here */ | |
1401 | if (start_dma <= end_trb_dma) { | |
1402 | if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma) | |
1403 | return cur_seg; | |
1404 | } else { | |
1405 | /* Case for one segment with | |
1406 | * a TD wrapped around to the top | |
1407 | */ | |
1408 | if ((suspect_dma >= start_dma && | |
1409 | suspect_dma <= end_seg_dma) || | |
1410 | (suspect_dma >= cur_seg->dma && | |
1411 | suspect_dma <= end_trb_dma)) | |
1412 | return cur_seg; | |
1413 | } | |
326b4810 | 1414 | return NULL; |
d0e96f5a SS |
1415 | } else { |
1416 | /* Might still be somewhere in this segment */ | |
1417 | if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma) | |
1418 | return cur_seg; | |
1419 | } | |
1420 | cur_seg = cur_seg->next; | |
23e3be11 | 1421 | start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]); |
2fa88daa | 1422 | } while (cur_seg != start_seg); |
d0e96f5a | 1423 | |
326b4810 | 1424 | return NULL; |
d0e96f5a SS |
1425 | } |
1426 | ||
bcef3fd5 SS |
1427 | static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci, |
1428 | unsigned int slot_id, unsigned int ep_index, | |
e9df17eb | 1429 | unsigned int stream_id, |
bcef3fd5 SS |
1430 | struct xhci_td *td, union xhci_trb *event_trb) |
1431 | { | |
1432 | struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index]; | |
1433 | ep->ep_state |= EP_HALTED; | |
1434 | ep->stopped_td = td; | |
1435 | ep->stopped_trb = event_trb; | |
e9df17eb | 1436 | ep->stopped_stream = stream_id; |
1624ae1c | 1437 | |
bcef3fd5 SS |
1438 | xhci_queue_reset_ep(xhci, slot_id, ep_index); |
1439 | xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index); | |
1624ae1c SS |
1440 | |
1441 | ep->stopped_td = NULL; | |
1442 | ep->stopped_trb = NULL; | |
5e5cf6fc | 1443 | ep->stopped_stream = 0; |
1624ae1c | 1444 | |
bcef3fd5 SS |
1445 | xhci_ring_cmd_db(xhci); |
1446 | } | |
1447 | ||
1448 | /* Check if an error has halted the endpoint ring. The class driver will | |
1449 | * cleanup the halt for a non-default control endpoint if we indicate a stall. | |
1450 | * However, a babble and other errors also halt the endpoint ring, and the class | |
1451 | * driver won't clear the halt in that case, so we need to issue a Set Transfer | |
1452 | * Ring Dequeue Pointer command manually. | |
1453 | */ | |
1454 | static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci, | |
1455 | struct xhci_ep_ctx *ep_ctx, | |
1456 | unsigned int trb_comp_code) | |
1457 | { | |
1458 | /* TRB completion codes that may require a manual halt cleanup */ | |
1459 | if (trb_comp_code == COMP_TX_ERR || | |
1460 | trb_comp_code == COMP_BABBLE || | |
1461 | trb_comp_code == COMP_SPLIT_ERR) | |
1462 | /* The 0.96 spec says a babbling control endpoint | |
1463 | * is not halted. The 0.96 spec says it is. Some HW | |
1464 | * claims to be 0.95 compliant, but it halts the control | |
1465 | * endpoint anyway. Check if a babble halted the | |
1466 | * endpoint. | |
1467 | */ | |
28ccd296 | 1468 | if ((le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) == EP_STATE_HALTED) |
bcef3fd5 SS |
1469 | return 1; |
1470 | ||
1471 | return 0; | |
1472 | } | |
1473 | ||
b45b5069 SS |
1474 | int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code) |
1475 | { | |
1476 | if (trb_comp_code >= 224 && trb_comp_code <= 255) { | |
1477 | /* Vendor defined "informational" completion code, | |
1478 | * treat as not-an-error. | |
1479 | */ | |
1480 | xhci_dbg(xhci, "Vendor defined info completion code %u\n", | |
1481 | trb_comp_code); | |
1482 | xhci_dbg(xhci, "Treating code as success.\n"); | |
1483 | return 1; | |
1484 | } | |
1485 | return 0; | |
1486 | } | |
1487 | ||
4422da61 AX |
1488 | /* |
1489 | * Finish the td processing, remove the td from td list; | |
1490 | * Return 1 if the urb can be given back. | |
1491 | */ | |
1492 | static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td, | |
1493 | union xhci_trb *event_trb, struct xhci_transfer_event *event, | |
1494 | struct xhci_virt_ep *ep, int *status, bool skip) | |
1495 | { | |
1496 | struct xhci_virt_device *xdev; | |
1497 | struct xhci_ring *ep_ring; | |
1498 | unsigned int slot_id; | |
1499 | int ep_index; | |
1500 | struct urb *urb = NULL; | |
1501 | struct xhci_ep_ctx *ep_ctx; | |
1502 | int ret = 0; | |
8e51adcc | 1503 | struct urb_priv *urb_priv; |
4422da61 AX |
1504 | u32 trb_comp_code; |
1505 | ||
28ccd296 | 1506 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
4422da61 | 1507 | xdev = xhci->devs[slot_id]; |
28ccd296 ME |
1508 | ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1; |
1509 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); | |
4422da61 | 1510 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
28ccd296 | 1511 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); |
4422da61 AX |
1512 | |
1513 | if (skip) | |
1514 | goto td_cleanup; | |
1515 | ||
1516 | if (trb_comp_code == COMP_STOP_INVAL || | |
1517 | trb_comp_code == COMP_STOP) { | |
1518 | /* The Endpoint Stop Command completion will take care of any | |
1519 | * stopped TDs. A stopped TD may be restarted, so don't update | |
1520 | * the ring dequeue pointer or take this TD off any lists yet. | |
1521 | */ | |
1522 | ep->stopped_td = td; | |
1523 | ep->stopped_trb = event_trb; | |
1524 | return 0; | |
1525 | } else { | |
1526 | if (trb_comp_code == COMP_STALL) { | |
1527 | /* The transfer is completed from the driver's | |
1528 | * perspective, but we need to issue a set dequeue | |
1529 | * command for this stalled endpoint to move the dequeue | |
1530 | * pointer past the TD. We can't do that here because | |
1531 | * the halt condition must be cleared first. Let the | |
1532 | * USB class driver clear the stall later. | |
1533 | */ | |
1534 | ep->stopped_td = td; | |
1535 | ep->stopped_trb = event_trb; | |
1536 | ep->stopped_stream = ep_ring->stream_id; | |
1537 | } else if (xhci_requires_manual_halt_cleanup(xhci, | |
1538 | ep_ctx, trb_comp_code)) { | |
1539 | /* Other types of errors halt the endpoint, but the | |
1540 | * class driver doesn't call usb_reset_endpoint() unless | |
1541 | * the error is -EPIPE. Clear the halted status in the | |
1542 | * xHCI hardware manually. | |
1543 | */ | |
1544 | xhci_cleanup_halted_endpoint(xhci, | |
1545 | slot_id, ep_index, ep_ring->stream_id, | |
1546 | td, event_trb); | |
1547 | } else { | |
1548 | /* Update ring dequeue pointer */ | |
1549 | while (ep_ring->dequeue != td->last_trb) | |
1550 | inc_deq(xhci, ep_ring, false); | |
1551 | inc_deq(xhci, ep_ring, false); | |
1552 | } | |
1553 | ||
1554 | td_cleanup: | |
1555 | /* Clean up the endpoint's TD list */ | |
1556 | urb = td->urb; | |
8e51adcc | 1557 | urb_priv = urb->hcpriv; |
4422da61 AX |
1558 | |
1559 | /* Do one last check of the actual transfer length. | |
1560 | * If the host controller said we transferred more data than | |
1561 | * the buffer length, urb->actual_length will be a very big | |
1562 | * number (since it's unsigned). Play it safe and say we didn't | |
1563 | * transfer anything. | |
1564 | */ | |
1565 | if (urb->actual_length > urb->transfer_buffer_length) { | |
1566 | xhci_warn(xhci, "URB transfer length is wrong, " | |
1567 | "xHC issue? req. len = %u, " | |
1568 | "act. len = %u\n", | |
1569 | urb->transfer_buffer_length, | |
1570 | urb->actual_length); | |
1571 | urb->actual_length = 0; | |
1572 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) | |
1573 | *status = -EREMOTEIO; | |
1574 | else | |
1575 | *status = 0; | |
1576 | } | |
1577 | list_del(&td->td_list); | |
1578 | /* Was this TD slated to be cancelled but completed anyway? */ | |
1579 | if (!list_empty(&td->cancelled_td_list)) | |
1580 | list_del(&td->cancelled_td_list); | |
1581 | ||
8e51adcc AX |
1582 | urb_priv->td_cnt++; |
1583 | /* Giveback the urb when all the tds are completed */ | |
c41136b0 | 1584 | if (urb_priv->td_cnt == urb_priv->length) { |
8e51adcc | 1585 | ret = 1; |
c41136b0 AX |
1586 | if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { |
1587 | xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--; | |
1588 | if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs | |
1589 | == 0) { | |
1590 | if (xhci->quirks & XHCI_AMD_PLL_FIX) | |
1591 | usb_amd_quirk_pll_enable(); | |
1592 | } | |
1593 | } | |
1594 | } | |
4422da61 AX |
1595 | } |
1596 | ||
1597 | return ret; | |
1598 | } | |
1599 | ||
8af56be1 AX |
1600 | /* |
1601 | * Process control tds, update urb status and actual_length. | |
1602 | */ | |
1603 | static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td, | |
1604 | union xhci_trb *event_trb, struct xhci_transfer_event *event, | |
1605 | struct xhci_virt_ep *ep, int *status) | |
1606 | { | |
1607 | struct xhci_virt_device *xdev; | |
1608 | struct xhci_ring *ep_ring; | |
1609 | unsigned int slot_id; | |
1610 | int ep_index; | |
1611 | struct xhci_ep_ctx *ep_ctx; | |
1612 | u32 trb_comp_code; | |
1613 | ||
28ccd296 | 1614 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
8af56be1 | 1615 | xdev = xhci->devs[slot_id]; |
28ccd296 ME |
1616 | ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1; |
1617 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); | |
8af56be1 | 1618 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
28ccd296 | 1619 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); |
8af56be1 AX |
1620 | |
1621 | xhci_debug_trb(xhci, xhci->event_ring->dequeue); | |
1622 | switch (trb_comp_code) { | |
1623 | case COMP_SUCCESS: | |
1624 | if (event_trb == ep_ring->dequeue) { | |
1625 | xhci_warn(xhci, "WARN: Success on ctrl setup TRB " | |
1626 | "without IOC set??\n"); | |
1627 | *status = -ESHUTDOWN; | |
1628 | } else if (event_trb != td->last_trb) { | |
1629 | xhci_warn(xhci, "WARN: Success on ctrl data TRB " | |
1630 | "without IOC set??\n"); | |
1631 | *status = -ESHUTDOWN; | |
1632 | } else { | |
1633 | xhci_dbg(xhci, "Successful control transfer!\n"); | |
1634 | *status = 0; | |
1635 | } | |
1636 | break; | |
1637 | case COMP_SHORT_TX: | |
1638 | xhci_warn(xhci, "WARN: short transfer on control ep\n"); | |
1639 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) | |
1640 | *status = -EREMOTEIO; | |
1641 | else | |
1642 | *status = 0; | |
1643 | break; | |
1644 | default: | |
1645 | if (!xhci_requires_manual_halt_cleanup(xhci, | |
1646 | ep_ctx, trb_comp_code)) | |
1647 | break; | |
1648 | xhci_dbg(xhci, "TRB error code %u, " | |
1649 | "halted endpoint index = %u\n", | |
1650 | trb_comp_code, ep_index); | |
1651 | /* else fall through */ | |
1652 | case COMP_STALL: | |
1653 | /* Did we transfer part of the data (middle) phase? */ | |
1654 | if (event_trb != ep_ring->dequeue && | |
1655 | event_trb != td->last_trb) | |
1656 | td->urb->actual_length = | |
1657 | td->urb->transfer_buffer_length | |
28ccd296 | 1658 | - TRB_LEN(le32_to_cpu(event->transfer_len)); |
8af56be1 AX |
1659 | else |
1660 | td->urb->actual_length = 0; | |
1661 | ||
1662 | xhci_cleanup_halted_endpoint(xhci, | |
1663 | slot_id, ep_index, 0, td, event_trb); | |
1664 | return finish_td(xhci, td, event_trb, event, ep, status, true); | |
1665 | } | |
1666 | /* | |
1667 | * Did we transfer any data, despite the errors that might have | |
1668 | * happened? I.e. did we get past the setup stage? | |
1669 | */ | |
1670 | if (event_trb != ep_ring->dequeue) { | |
1671 | /* The event was for the status stage */ | |
1672 | if (event_trb == td->last_trb) { | |
1673 | if (td->urb->actual_length != 0) { | |
1674 | /* Don't overwrite a previously set error code | |
1675 | */ | |
1676 | if ((*status == -EINPROGRESS || *status == 0) && | |
1677 | (td->urb->transfer_flags | |
1678 | & URB_SHORT_NOT_OK)) | |
1679 | /* Did we already see a short data | |
1680 | * stage? */ | |
1681 | *status = -EREMOTEIO; | |
1682 | } else { | |
1683 | td->urb->actual_length = | |
1684 | td->urb->transfer_buffer_length; | |
1685 | } | |
1686 | } else { | |
1687 | /* Maybe the event was for the data stage? */ | |
1688 | if (trb_comp_code != COMP_STOP_INVAL) { | |
1689 | /* We didn't stop on a link TRB in the middle */ | |
1690 | td->urb->actual_length = | |
1691 | td->urb->transfer_buffer_length - | |
28ccd296 | 1692 | TRB_LEN(le32_to_cpu(event->transfer_len)); |
8af56be1 AX |
1693 | xhci_dbg(xhci, "Waiting for status " |
1694 | "stage event\n"); | |
1695 | return 0; | |
1696 | } | |
1697 | } | |
1698 | } | |
1699 | ||
1700 | return finish_td(xhci, td, event_trb, event, ep, status, false); | |
1701 | } | |
1702 | ||
04e51901 AX |
1703 | /* |
1704 | * Process isochronous tds, update urb packet status and actual_length. | |
1705 | */ | |
1706 | static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td, | |
1707 | union xhci_trb *event_trb, struct xhci_transfer_event *event, | |
1708 | struct xhci_virt_ep *ep, int *status) | |
1709 | { | |
1710 | struct xhci_ring *ep_ring; | |
1711 | struct urb_priv *urb_priv; | |
1712 | int idx; | |
1713 | int len = 0; | |
04e51901 AX |
1714 | union xhci_trb *cur_trb; |
1715 | struct xhci_segment *cur_seg; | |
926008c9 | 1716 | struct usb_iso_packet_descriptor *frame; |
04e51901 | 1717 | u32 trb_comp_code; |
926008c9 | 1718 | bool skip_td = false; |
04e51901 | 1719 | |
28ccd296 ME |
1720 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); |
1721 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); | |
04e51901 AX |
1722 | urb_priv = td->urb->hcpriv; |
1723 | idx = urb_priv->td_cnt; | |
926008c9 | 1724 | frame = &td->urb->iso_frame_desc[idx]; |
04e51901 | 1725 | |
926008c9 DT |
1726 | /* handle completion code */ |
1727 | switch (trb_comp_code) { | |
1728 | case COMP_SUCCESS: | |
1729 | frame->status = 0; | |
1730 | xhci_dbg(xhci, "Successful isoc transfer!\n"); | |
1731 | break; | |
1732 | case COMP_SHORT_TX: | |
1733 | frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ? | |
1734 | -EREMOTEIO : 0; | |
1735 | break; | |
1736 | case COMP_BW_OVER: | |
1737 | frame->status = -ECOMM; | |
1738 | skip_td = true; | |
1739 | break; | |
1740 | case COMP_BUFF_OVER: | |
1741 | case COMP_BABBLE: | |
1742 | frame->status = -EOVERFLOW; | |
1743 | skip_td = true; | |
1744 | break; | |
1745 | case COMP_STALL: | |
1746 | frame->status = -EPROTO; | |
1747 | skip_td = true; | |
1748 | break; | |
1749 | case COMP_STOP: | |
1750 | case COMP_STOP_INVAL: | |
1751 | break; | |
1752 | default: | |
1753 | frame->status = -1; | |
1754 | break; | |
04e51901 AX |
1755 | } |
1756 | ||
926008c9 DT |
1757 | if (trb_comp_code == COMP_SUCCESS || skip_td) { |
1758 | frame->actual_length = frame->length; | |
1759 | td->urb->actual_length += frame->length; | |
04e51901 AX |
1760 | } else { |
1761 | for (cur_trb = ep_ring->dequeue, | |
1762 | cur_seg = ep_ring->deq_seg; cur_trb != event_trb; | |
1763 | next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) { | |
28ccd296 | 1764 | if ((le32_to_cpu(cur_trb->generic.field[3]) & |
04e51901 | 1765 | TRB_TYPE_BITMASK) != TRB_TYPE(TRB_TR_NOOP) && |
28ccd296 | 1766 | (le32_to_cpu(cur_trb->generic.field[3]) & |
04e51901 | 1767 | TRB_TYPE_BITMASK) != TRB_TYPE(TRB_LINK)) |
28ccd296 | 1768 | len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])); |
04e51901 | 1769 | } |
28ccd296 ME |
1770 | len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) - |
1771 | TRB_LEN(le32_to_cpu(event->transfer_len)); | |
04e51901 AX |
1772 | |
1773 | if (trb_comp_code != COMP_STOP_INVAL) { | |
926008c9 | 1774 | frame->actual_length = len; |
04e51901 AX |
1775 | td->urb->actual_length += len; |
1776 | } | |
1777 | } | |
1778 | ||
1779 | if ((idx == urb_priv->length - 1) && *status == -EINPROGRESS) | |
1780 | *status = 0; | |
1781 | ||
1782 | return finish_td(xhci, td, event_trb, event, ep, status, false); | |
1783 | } | |
1784 | ||
926008c9 DT |
1785 | static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td, |
1786 | struct xhci_transfer_event *event, | |
1787 | struct xhci_virt_ep *ep, int *status) | |
1788 | { | |
1789 | struct xhci_ring *ep_ring; | |
1790 | struct urb_priv *urb_priv; | |
1791 | struct usb_iso_packet_descriptor *frame; | |
1792 | int idx; | |
1793 | ||
1794 | ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer); | |
1795 | urb_priv = td->urb->hcpriv; | |
1796 | idx = urb_priv->td_cnt; | |
1797 | frame = &td->urb->iso_frame_desc[idx]; | |
1798 | ||
1799 | /* The transfer is partly done */ | |
1800 | *status = -EXDEV; | |
1801 | frame->status = -EXDEV; | |
1802 | ||
1803 | /* calc actual length */ | |
1804 | frame->actual_length = 0; | |
1805 | ||
1806 | /* Update ring dequeue pointer */ | |
1807 | while (ep_ring->dequeue != td->last_trb) | |
1808 | inc_deq(xhci, ep_ring, false); | |
1809 | inc_deq(xhci, ep_ring, false); | |
1810 | ||
1811 | return finish_td(xhci, td, NULL, event, ep, status, true); | |
1812 | } | |
1813 | ||
22405ed2 AX |
1814 | /* |
1815 | * Process bulk and interrupt tds, update urb status and actual_length. | |
1816 | */ | |
1817 | static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td, | |
1818 | union xhci_trb *event_trb, struct xhci_transfer_event *event, | |
1819 | struct xhci_virt_ep *ep, int *status) | |
1820 | { | |
1821 | struct xhci_ring *ep_ring; | |
1822 | union xhci_trb *cur_trb; | |
1823 | struct xhci_segment *cur_seg; | |
1824 | u32 trb_comp_code; | |
1825 | ||
28ccd296 ME |
1826 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); |
1827 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); | |
22405ed2 AX |
1828 | |
1829 | switch (trb_comp_code) { | |
1830 | case COMP_SUCCESS: | |
1831 | /* Double check that the HW transferred everything. */ | |
1832 | if (event_trb != td->last_trb) { | |
1833 | xhci_warn(xhci, "WARN Successful completion " | |
1834 | "on short TX\n"); | |
1835 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) | |
1836 | *status = -EREMOTEIO; | |
1837 | else | |
1838 | *status = 0; | |
1839 | } else { | |
1840 | if (usb_endpoint_xfer_bulk(&td->urb->ep->desc)) | |
1841 | xhci_dbg(xhci, "Successful bulk " | |
1842 | "transfer!\n"); | |
1843 | else | |
1844 | xhci_dbg(xhci, "Successful interrupt " | |
1845 | "transfer!\n"); | |
1846 | *status = 0; | |
1847 | } | |
1848 | break; | |
1849 | case COMP_SHORT_TX: | |
1850 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) | |
1851 | *status = -EREMOTEIO; | |
1852 | else | |
1853 | *status = 0; | |
1854 | break; | |
1855 | default: | |
1856 | /* Others already handled above */ | |
1857 | break; | |
1858 | } | |
f2c565e2 | 1859 | xhci_dbg(xhci, "ep %#x - asked for %d bytes, " |
22405ed2 AX |
1860 | "%d bytes untransferred\n", |
1861 | td->urb->ep->desc.bEndpointAddress, | |
1862 | td->urb->transfer_buffer_length, | |
28ccd296 | 1863 | TRB_LEN(le32_to_cpu(event->transfer_len))); |
22405ed2 AX |
1864 | /* Fast path - was this the last TRB in the TD for this URB? */ |
1865 | if (event_trb == td->last_trb) { | |
28ccd296 | 1866 | if (TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) { |
22405ed2 AX |
1867 | td->urb->actual_length = |
1868 | td->urb->transfer_buffer_length - | |
28ccd296 | 1869 | TRB_LEN(le32_to_cpu(event->transfer_len)); |
22405ed2 AX |
1870 | if (td->urb->transfer_buffer_length < |
1871 | td->urb->actual_length) { | |
1872 | xhci_warn(xhci, "HC gave bad length " | |
1873 | "of %d bytes left\n", | |
28ccd296 | 1874 | TRB_LEN(le32_to_cpu(event->transfer_len))); |
22405ed2 AX |
1875 | td->urb->actual_length = 0; |
1876 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) | |
1877 | *status = -EREMOTEIO; | |
1878 | else | |
1879 | *status = 0; | |
1880 | } | |
1881 | /* Don't overwrite a previously set error code */ | |
1882 | if (*status == -EINPROGRESS) { | |
1883 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) | |
1884 | *status = -EREMOTEIO; | |
1885 | else | |
1886 | *status = 0; | |
1887 | } | |
1888 | } else { | |
1889 | td->urb->actual_length = | |
1890 | td->urb->transfer_buffer_length; | |
1891 | /* Ignore a short packet completion if the | |
1892 | * untransferred length was zero. | |
1893 | */ | |
1894 | if (*status == -EREMOTEIO) | |
1895 | *status = 0; | |
1896 | } | |
1897 | } else { | |
1898 | /* Slow path - walk the list, starting from the dequeue | |
1899 | * pointer, to get the actual length transferred. | |
1900 | */ | |
1901 | td->urb->actual_length = 0; | |
1902 | for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg; | |
1903 | cur_trb != event_trb; | |
1904 | next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) { | |
28ccd296 | 1905 | if ((le32_to_cpu(cur_trb->generic.field[3]) & |
22405ed2 | 1906 | TRB_TYPE_BITMASK) != TRB_TYPE(TRB_TR_NOOP) && |
28ccd296 | 1907 | (le32_to_cpu(cur_trb->generic.field[3]) & |
22405ed2 AX |
1908 | TRB_TYPE_BITMASK) != TRB_TYPE(TRB_LINK)) |
1909 | td->urb->actual_length += | |
28ccd296 | 1910 | TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])); |
22405ed2 AX |
1911 | } |
1912 | /* If the ring didn't stop on a Link or No-op TRB, add | |
1913 | * in the actual bytes transferred from the Normal TRB | |
1914 | */ | |
1915 | if (trb_comp_code != COMP_STOP_INVAL) | |
1916 | td->urb->actual_length += | |
28ccd296 ME |
1917 | TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) - |
1918 | TRB_LEN(le32_to_cpu(event->transfer_len)); | |
22405ed2 AX |
1919 | } |
1920 | ||
1921 | return finish_td(xhci, td, event_trb, event, ep, status, false); | |
1922 | } | |
1923 | ||
d0e96f5a SS |
1924 | /* |
1925 | * If this function returns an error condition, it means it got a Transfer | |
1926 | * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address. | |
1927 | * At this point, the host controller is probably hosed and should be reset. | |
1928 | */ | |
1929 | static int handle_tx_event(struct xhci_hcd *xhci, | |
1930 | struct xhci_transfer_event *event) | |
1931 | { | |
1932 | struct xhci_virt_device *xdev; | |
63a0d9ab | 1933 | struct xhci_virt_ep *ep; |
d0e96f5a | 1934 | struct xhci_ring *ep_ring; |
82d1009f | 1935 | unsigned int slot_id; |
d0e96f5a | 1936 | int ep_index; |
326b4810 | 1937 | struct xhci_td *td = NULL; |
d0e96f5a SS |
1938 | dma_addr_t event_dma; |
1939 | struct xhci_segment *event_seg; | |
1940 | union xhci_trb *event_trb; | |
326b4810 | 1941 | struct urb *urb = NULL; |
d0e96f5a | 1942 | int status = -EINPROGRESS; |
8e51adcc | 1943 | struct urb_priv *urb_priv; |
d115b048 | 1944 | struct xhci_ep_ctx *ep_ctx; |
66d1eebc | 1945 | u32 trb_comp_code; |
4422da61 | 1946 | int ret = 0; |
d0e96f5a | 1947 | |
28ccd296 | 1948 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
82d1009f | 1949 | xdev = xhci->devs[slot_id]; |
d0e96f5a SS |
1950 | if (!xdev) { |
1951 | xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n"); | |
1952 | return -ENODEV; | |
1953 | } | |
1954 | ||
1955 | /* Endpoint ID is 1 based, our index is zero based */ | |
28ccd296 | 1956 | ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1; |
66e49d87 | 1957 | xhci_dbg(xhci, "%s - ep index = %d\n", __func__, ep_index); |
63a0d9ab | 1958 | ep = &xdev->eps[ep_index]; |
28ccd296 | 1959 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); |
d115b048 | 1960 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
986a92d4 | 1961 | if (!ep_ring || |
28ccd296 ME |
1962 | (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) == |
1963 | EP_STATE_DISABLED) { | |
e9df17eb SS |
1964 | xhci_err(xhci, "ERROR Transfer event for disabled endpoint " |
1965 | "or incorrect stream ring\n"); | |
d0e96f5a SS |
1966 | return -ENODEV; |
1967 | } | |
1968 | ||
28ccd296 ME |
1969 | event_dma = le64_to_cpu(event->buffer); |
1970 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); | |
986a92d4 | 1971 | /* Look for common error cases */ |
66d1eebc | 1972 | switch (trb_comp_code) { |
b10de142 SS |
1973 | /* Skip codes that require special handling depending on |
1974 | * transfer type | |
1975 | */ | |
1976 | case COMP_SUCCESS: | |
1977 | case COMP_SHORT_TX: | |
1978 | break; | |
ae636747 SS |
1979 | case COMP_STOP: |
1980 | xhci_dbg(xhci, "Stopped on Transfer TRB\n"); | |
1981 | break; | |
1982 | case COMP_STOP_INVAL: | |
1983 | xhci_dbg(xhci, "Stopped on No-op or Link TRB\n"); | |
1984 | break; | |
b10de142 SS |
1985 | case COMP_STALL: |
1986 | xhci_warn(xhci, "WARN: Stalled endpoint\n"); | |
63a0d9ab | 1987 | ep->ep_state |= EP_HALTED; |
b10de142 SS |
1988 | status = -EPIPE; |
1989 | break; | |
1990 | case COMP_TRB_ERR: | |
1991 | xhci_warn(xhci, "WARN: TRB error on endpoint\n"); | |
1992 | status = -EILSEQ; | |
1993 | break; | |
ec74e403 | 1994 | case COMP_SPLIT_ERR: |
b10de142 SS |
1995 | case COMP_TX_ERR: |
1996 | xhci_warn(xhci, "WARN: transfer error on endpoint\n"); | |
1997 | status = -EPROTO; | |
1998 | break; | |
4a73143c SS |
1999 | case COMP_BABBLE: |
2000 | xhci_warn(xhci, "WARN: babble error on endpoint\n"); | |
2001 | status = -EOVERFLOW; | |
2002 | break; | |
b10de142 SS |
2003 | case COMP_DB_ERR: |
2004 | xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n"); | |
2005 | status = -ENOSR; | |
2006 | break; | |
986a92d4 AX |
2007 | case COMP_BW_OVER: |
2008 | xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n"); | |
2009 | break; | |
2010 | case COMP_BUFF_OVER: | |
2011 | xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n"); | |
2012 | break; | |
2013 | case COMP_UNDERRUN: | |
2014 | /* | |
2015 | * When the Isoch ring is empty, the xHC will generate | |
2016 | * a Ring Overrun Event for IN Isoch endpoint or Ring | |
2017 | * Underrun Event for OUT Isoch endpoint. | |
2018 | */ | |
2019 | xhci_dbg(xhci, "underrun event on endpoint\n"); | |
2020 | if (!list_empty(&ep_ring->td_list)) | |
2021 | xhci_dbg(xhci, "Underrun Event for slot %d ep %d " | |
2022 | "still with TDs queued?\n", | |
28ccd296 ME |
2023 | TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), |
2024 | ep_index); | |
986a92d4 AX |
2025 | goto cleanup; |
2026 | case COMP_OVERRUN: | |
2027 | xhci_dbg(xhci, "overrun event on endpoint\n"); | |
2028 | if (!list_empty(&ep_ring->td_list)) | |
2029 | xhci_dbg(xhci, "Overrun Event for slot %d ep %d " | |
2030 | "still with TDs queued?\n", | |
28ccd296 ME |
2031 | TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), |
2032 | ep_index); | |
986a92d4 | 2033 | goto cleanup; |
d18240db AX |
2034 | case COMP_MISSED_INT: |
2035 | /* | |
2036 | * When encounter missed service error, one or more isoc tds | |
2037 | * may be missed by xHC. | |
2038 | * Set skip flag of the ep_ring; Complete the missed tds as | |
2039 | * short transfer when process the ep_ring next time. | |
2040 | */ | |
2041 | ep->skip = true; | |
2042 | xhci_dbg(xhci, "Miss service interval error, set skip flag\n"); | |
2043 | goto cleanup; | |
b10de142 | 2044 | default: |
b45b5069 | 2045 | if (xhci_is_vendor_info_code(xhci, trb_comp_code)) { |
5ad6a529 SS |
2046 | status = 0; |
2047 | break; | |
2048 | } | |
986a92d4 AX |
2049 | xhci_warn(xhci, "ERROR Unknown event condition, HC probably " |
2050 | "busted\n"); | |
2051 | goto cleanup; | |
2052 | } | |
2053 | ||
d18240db AX |
2054 | do { |
2055 | /* This TRB should be in the TD at the head of this ring's | |
2056 | * TD list. | |
2057 | */ | |
2058 | if (list_empty(&ep_ring->td_list)) { | |
2059 | xhci_warn(xhci, "WARN Event TRB for slot %d ep %d " | |
2060 | "with no TDs queued?\n", | |
28ccd296 ME |
2061 | TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), |
2062 | ep_index); | |
d18240db | 2063 | xhci_dbg(xhci, "Event TRB with TRB type ID %u\n", |
28ccd296 ME |
2064 | (unsigned int) (le32_to_cpu(event->flags) |
2065 | & TRB_TYPE_BITMASK)>>10); | |
d18240db AX |
2066 | xhci_print_trb_offsets(xhci, (union xhci_trb *) event); |
2067 | if (ep->skip) { | |
2068 | ep->skip = false; | |
2069 | xhci_dbg(xhci, "td_list is empty while skip " | |
2070 | "flag set. Clear skip flag.\n"); | |
2071 | } | |
2072 | ret = 0; | |
2073 | goto cleanup; | |
2074 | } | |
986a92d4 | 2075 | |
d18240db | 2076 | td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list); |
926008c9 | 2077 | |
d18240db AX |
2078 | /* Is this a TRB in the currently executing TD? */ |
2079 | event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue, | |
2080 | td->last_trb, event_dma); | |
926008c9 DT |
2081 | if (!event_seg) { |
2082 | if (!ep->skip || | |
2083 | !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) { | |
2084 | /* HC is busted, give up! */ | |
2085 | xhci_err(xhci, | |
2086 | "ERROR Transfer event TRB DMA ptr not " | |
2087 | "part of current TD\n"); | |
2088 | return -ESHUTDOWN; | |
2089 | } | |
2090 | ||
2091 | ret = skip_isoc_td(xhci, td, event, ep, &status); | |
2092 | goto cleanup; | |
2093 | } | |
2094 | ||
2095 | if (ep->skip) { | |
d18240db AX |
2096 | xhci_dbg(xhci, "Found td. Clear skip flag.\n"); |
2097 | ep->skip = false; | |
2098 | } | |
678539cf | 2099 | |
926008c9 DT |
2100 | event_trb = &event_seg->trbs[(event_dma - event_seg->dma) / |
2101 | sizeof(*event_trb)]; | |
2102 | /* | |
2103 | * No-op TRB should not trigger interrupts. | |
2104 | * If event_trb is a no-op TRB, it means the | |
2105 | * corresponding TD has been cancelled. Just ignore | |
2106 | * the TD. | |
2107 | */ | |
28ccd296 ME |
2108 | if ((le32_to_cpu(event_trb->generic.field[3]) |
2109 | & TRB_TYPE_BITMASK) | |
926008c9 DT |
2110 | == TRB_TYPE(TRB_TR_NOOP)) { |
2111 | xhci_dbg(xhci, | |
2112 | "event_trb is a no-op TRB. Skip it\n"); | |
2113 | goto cleanup; | |
d18240db | 2114 | } |
4422da61 | 2115 | |
d18240db AX |
2116 | /* Now update the urb's actual_length and give back to |
2117 | * the core | |
82d1009f | 2118 | */ |
d18240db AX |
2119 | if (usb_endpoint_xfer_control(&td->urb->ep->desc)) |
2120 | ret = process_ctrl_td(xhci, td, event_trb, event, ep, | |
2121 | &status); | |
04e51901 AX |
2122 | else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc)) |
2123 | ret = process_isoc_td(xhci, td, event_trb, event, ep, | |
2124 | &status); | |
d18240db AX |
2125 | else |
2126 | ret = process_bulk_intr_td(xhci, td, event_trb, event, | |
2127 | ep, &status); | |
2128 | ||
2129 | cleanup: | |
2130 | /* | |
2131 | * Do not update event ring dequeue pointer if ep->skip is set. | |
2132 | * Will roll back to continue process missed tds. | |
2133 | */ | |
2134 | if (trb_comp_code == COMP_MISSED_INT || !ep->skip) { | |
2135 | inc_deq(xhci, xhci->event_ring, true); | |
d18240db AX |
2136 | } |
2137 | ||
2138 | if (ret) { | |
2139 | urb = td->urb; | |
8e51adcc | 2140 | urb_priv = urb->hcpriv; |
d18240db AX |
2141 | /* Leave the TD around for the reset endpoint function |
2142 | * to use(but only if it's not a control endpoint, | |
2143 | * since we already queued the Set TR dequeue pointer | |
2144 | * command for stalled control endpoints). | |
2145 | */ | |
2146 | if (usb_endpoint_xfer_control(&urb->ep->desc) || | |
2147 | (trb_comp_code != COMP_STALL && | |
2148 | trb_comp_code != COMP_BABBLE)) | |
8e51adcc | 2149 | xhci_urb_free_priv(xhci, urb_priv); |
d18240db | 2150 | |
214f76f7 | 2151 | usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb); |
d18240db AX |
2152 | xhci_dbg(xhci, "Giveback URB %p, len = %d, " |
2153 | "status = %d\n", | |
2154 | urb, urb->actual_length, status); | |
2155 | spin_unlock(&xhci->lock); | |
214f76f7 | 2156 | usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status); |
d18240db AX |
2157 | spin_lock(&xhci->lock); |
2158 | } | |
2159 | ||
2160 | /* | |
2161 | * If ep->skip is set, it means there are missed tds on the | |
2162 | * endpoint ring need to take care of. | |
2163 | * Process them as short transfer until reach the td pointed by | |
2164 | * the event. | |
2165 | */ | |
2166 | } while (ep->skip && trb_comp_code != COMP_MISSED_INT); | |
2167 | ||
d0e96f5a SS |
2168 | return 0; |
2169 | } | |
2170 | ||
0f2a7930 SS |
2171 | /* |
2172 | * This function handles all OS-owned events on the event ring. It may drop | |
2173 | * xhci->lock between event processing (e.g. to pass up port status changes). | |
9dee9a21 ME |
2174 | * Returns >0 for "possibly more events to process" (caller should call again), |
2175 | * otherwise 0 if done. In future, <0 returns should indicate error code. | |
0f2a7930 | 2176 | */ |
9dee9a21 | 2177 | static int xhci_handle_event(struct xhci_hcd *xhci) |
7f84eef0 SS |
2178 | { |
2179 | union xhci_trb *event; | |
0f2a7930 | 2180 | int update_ptrs = 1; |
d0e96f5a | 2181 | int ret; |
7f84eef0 | 2182 | |
66e49d87 | 2183 | xhci_dbg(xhci, "In %s\n", __func__); |
7f84eef0 SS |
2184 | if (!xhci->event_ring || !xhci->event_ring->dequeue) { |
2185 | xhci->error_bitmask |= 1 << 1; | |
9dee9a21 | 2186 | return 0; |
7f84eef0 SS |
2187 | } |
2188 | ||
2189 | event = xhci->event_ring->dequeue; | |
2190 | /* Does the HC or OS own the TRB? */ | |
28ccd296 ME |
2191 | if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) != |
2192 | xhci->event_ring->cycle_state) { | |
7f84eef0 | 2193 | xhci->error_bitmask |= 1 << 2; |
9dee9a21 | 2194 | return 0; |
7f84eef0 | 2195 | } |
66e49d87 | 2196 | xhci_dbg(xhci, "%s - OS owns TRB\n", __func__); |
7f84eef0 | 2197 | |
92a3da41 ME |
2198 | /* |
2199 | * Barrier between reading the TRB_CYCLE (valid) flag above and any | |
2200 | * speculative reads of the event's flags/data below. | |
2201 | */ | |
2202 | rmb(); | |
0f2a7930 | 2203 | /* FIXME: Handle more event types. */ |
28ccd296 | 2204 | switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) { |
7f84eef0 | 2205 | case TRB_TYPE(TRB_COMPLETION): |
66e49d87 | 2206 | xhci_dbg(xhci, "%s - calling handle_cmd_completion\n", __func__); |
7f84eef0 | 2207 | handle_cmd_completion(xhci, &event->event_cmd); |
66e49d87 | 2208 | xhci_dbg(xhci, "%s - returned from handle_cmd_completion\n", __func__); |
7f84eef0 | 2209 | break; |
0f2a7930 | 2210 | case TRB_TYPE(TRB_PORT_STATUS): |
66e49d87 | 2211 | xhci_dbg(xhci, "%s - calling handle_port_status\n", __func__); |
0f2a7930 | 2212 | handle_port_status(xhci, event); |
66e49d87 | 2213 | xhci_dbg(xhci, "%s - returned from handle_port_status\n", __func__); |
0f2a7930 SS |
2214 | update_ptrs = 0; |
2215 | break; | |
d0e96f5a | 2216 | case TRB_TYPE(TRB_TRANSFER): |
66e49d87 | 2217 | xhci_dbg(xhci, "%s - calling handle_tx_event\n", __func__); |
d0e96f5a | 2218 | ret = handle_tx_event(xhci, &event->trans_event); |
66e49d87 | 2219 | xhci_dbg(xhci, "%s - returned from handle_tx_event\n", __func__); |
d0e96f5a SS |
2220 | if (ret < 0) |
2221 | xhci->error_bitmask |= 1 << 9; | |
2222 | else | |
2223 | update_ptrs = 0; | |
2224 | break; | |
7f84eef0 | 2225 | default: |
28ccd296 ME |
2226 | if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >= |
2227 | TRB_TYPE(48)) | |
0238634d SS |
2228 | handle_vendor_event(xhci, event); |
2229 | else | |
2230 | xhci->error_bitmask |= 1 << 3; | |
7f84eef0 | 2231 | } |
6f5165cf SS |
2232 | /* Any of the above functions may drop and re-acquire the lock, so check |
2233 | * to make sure a watchdog timer didn't mark the host as non-responsive. | |
2234 | */ | |
2235 | if (xhci->xhc_state & XHCI_STATE_DYING) { | |
2236 | xhci_dbg(xhci, "xHCI host dying, returning from " | |
2237 | "event handler.\n"); | |
9dee9a21 | 2238 | return 0; |
6f5165cf | 2239 | } |
7f84eef0 | 2240 | |
c06d68b8 SS |
2241 | if (update_ptrs) |
2242 | /* Update SW event ring dequeue pointer */ | |
0f2a7930 | 2243 | inc_deq(xhci, xhci->event_ring, true); |
c06d68b8 | 2244 | |
9dee9a21 ME |
2245 | /* Are there more items on the event ring? Caller will call us again to |
2246 | * check. | |
2247 | */ | |
2248 | return 1; | |
7f84eef0 | 2249 | } |
9032cd52 SS |
2250 | |
2251 | /* | |
2252 | * xHCI spec says we can get an interrupt, and if the HC has an error condition, | |
2253 | * we might get bad data out of the event ring. Section 4.10.2.7 has a list of | |
2254 | * indicators of an event TRB error, but we check the status *first* to be safe. | |
2255 | */ | |
2256 | irqreturn_t xhci_irq(struct usb_hcd *hcd) | |
2257 | { | |
2258 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
c21599a3 | 2259 | u32 status; |
9032cd52 | 2260 | union xhci_trb *trb; |
bda53145 | 2261 | u64 temp_64; |
c06d68b8 SS |
2262 | union xhci_trb *event_ring_deq; |
2263 | dma_addr_t deq; | |
9032cd52 SS |
2264 | |
2265 | spin_lock(&xhci->lock); | |
2266 | trb = xhci->event_ring->dequeue; | |
2267 | /* Check if the xHC generated the interrupt, or the irq is shared */ | |
27e0dd4d | 2268 | status = xhci_readl(xhci, &xhci->op_regs->status); |
c21599a3 | 2269 | if (status == 0xffffffff) |
9032cd52 SS |
2270 | goto hw_died; |
2271 | ||
c21599a3 | 2272 | if (!(status & STS_EINT)) { |
9032cd52 | 2273 | spin_unlock(&xhci->lock); |
9032cd52 SS |
2274 | return IRQ_NONE; |
2275 | } | |
27e0dd4d | 2276 | xhci_dbg(xhci, "op reg status = %08x\n", status); |
9032cd52 SS |
2277 | xhci_dbg(xhci, "Event ring dequeue ptr:\n"); |
2278 | xhci_dbg(xhci, "@%llx %08x %08x %08x %08x\n", | |
28ccd296 ME |
2279 | (unsigned long long) |
2280 | xhci_trb_virt_to_dma(xhci->event_ring->deq_seg, trb), | |
2281 | lower_32_bits(le64_to_cpu(trb->link.segment_ptr)), | |
2282 | upper_32_bits(le64_to_cpu(trb->link.segment_ptr)), | |
2283 | (unsigned int) le32_to_cpu(trb->link.intr_target), | |
2284 | (unsigned int) le32_to_cpu(trb->link.control)); | |
9032cd52 | 2285 | |
27e0dd4d | 2286 | if (status & STS_FATAL) { |
9032cd52 SS |
2287 | xhci_warn(xhci, "WARNING: Host System Error\n"); |
2288 | xhci_halt(xhci); | |
2289 | hw_died: | |
9032cd52 SS |
2290 | spin_unlock(&xhci->lock); |
2291 | return -ESHUTDOWN; | |
2292 | } | |
2293 | ||
bda53145 SS |
2294 | /* |
2295 | * Clear the op reg interrupt status first, | |
2296 | * so we can receive interrupts from other MSI-X interrupters. | |
2297 | * Write 1 to clear the interrupt status. | |
2298 | */ | |
27e0dd4d SS |
2299 | status |= STS_EINT; |
2300 | xhci_writel(xhci, status, &xhci->op_regs->status); | |
bda53145 SS |
2301 | /* FIXME when MSI-X is supported and there are multiple vectors */ |
2302 | /* Clear the MSI-X event interrupt status */ | |
2303 | ||
c21599a3 SS |
2304 | if (hcd->irq != -1) { |
2305 | u32 irq_pending; | |
2306 | /* Acknowledge the PCI interrupt */ | |
2307 | irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending); | |
2308 | irq_pending |= 0x3; | |
2309 | xhci_writel(xhci, irq_pending, &xhci->ir_set->irq_pending); | |
2310 | } | |
bda53145 | 2311 | |
c06d68b8 | 2312 | if (xhci->xhc_state & XHCI_STATE_DYING) { |
bda53145 SS |
2313 | xhci_dbg(xhci, "xHCI dying, ignoring interrupt. " |
2314 | "Shouldn't IRQs be disabled?\n"); | |
c06d68b8 SS |
2315 | /* Clear the event handler busy flag (RW1C); |
2316 | * the event ring should be empty. | |
bda53145 | 2317 | */ |
c06d68b8 SS |
2318 | temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); |
2319 | xhci_write_64(xhci, temp_64 | ERST_EHB, | |
2320 | &xhci->ir_set->erst_dequeue); | |
2321 | spin_unlock(&xhci->lock); | |
2322 | ||
2323 | return IRQ_HANDLED; | |
2324 | } | |
2325 | ||
2326 | event_ring_deq = xhci->event_ring->dequeue; | |
2327 | /* FIXME this should be a delayed service routine | |
2328 | * that clears the EHB. | |
2329 | */ | |
9dee9a21 | 2330 | while (xhci_handle_event(xhci) > 0) {} |
bda53145 | 2331 | |
bda53145 | 2332 | temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); |
c06d68b8 SS |
2333 | /* If necessary, update the HW's version of the event ring deq ptr. */ |
2334 | if (event_ring_deq != xhci->event_ring->dequeue) { | |
2335 | deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg, | |
2336 | xhci->event_ring->dequeue); | |
2337 | if (deq == 0) | |
2338 | xhci_warn(xhci, "WARN something wrong with SW event " | |
2339 | "ring dequeue ptr.\n"); | |
2340 | /* Update HC event ring dequeue pointer */ | |
2341 | temp_64 &= ERST_PTR_MASK; | |
2342 | temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK); | |
2343 | } | |
2344 | ||
2345 | /* Clear the event handler busy flag (RW1C); event ring is empty. */ | |
2346 | temp_64 |= ERST_EHB; | |
2347 | xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue); | |
2348 | ||
9032cd52 SS |
2349 | spin_unlock(&xhci->lock); |
2350 | ||
2351 | return IRQ_HANDLED; | |
2352 | } | |
2353 | ||
2354 | irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd) | |
2355 | { | |
2356 | irqreturn_t ret; | |
b3209379 | 2357 | struct xhci_hcd *xhci; |
9032cd52 | 2358 | |
b3209379 | 2359 | xhci = hcd_to_xhci(hcd); |
9032cd52 | 2360 | set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags); |
b3209379 SS |
2361 | if (xhci->shared_hcd) |
2362 | set_bit(HCD_FLAG_SAW_IRQ, &xhci->shared_hcd->flags); | |
9032cd52 SS |
2363 | |
2364 | ret = xhci_irq(hcd); | |
2365 | ||
2366 | return ret; | |
2367 | } | |
7f84eef0 | 2368 | |
d0e96f5a SS |
2369 | /**** Endpoint Ring Operations ****/ |
2370 | ||
7f84eef0 SS |
2371 | /* |
2372 | * Generic function for queueing a TRB on a ring. | |
2373 | * The caller must have checked to make sure there's room on the ring. | |
6cc30d85 SS |
2374 | * |
2375 | * @more_trbs_coming: Will you enqueue more TRBs before calling | |
2376 | * prepare_transfer()? | |
7f84eef0 SS |
2377 | */ |
2378 | static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring, | |
6cc30d85 | 2379 | bool consumer, bool more_trbs_coming, |
7f84eef0 SS |
2380 | u32 field1, u32 field2, u32 field3, u32 field4) |
2381 | { | |
2382 | struct xhci_generic_trb *trb; | |
2383 | ||
2384 | trb = &ring->enqueue->generic; | |
28ccd296 ME |
2385 | trb->field[0] = cpu_to_le32(field1); |
2386 | trb->field[1] = cpu_to_le32(field2); | |
2387 | trb->field[2] = cpu_to_le32(field3); | |
2388 | trb->field[3] = cpu_to_le32(field4); | |
6cc30d85 | 2389 | inc_enq(xhci, ring, consumer, more_trbs_coming); |
7f84eef0 SS |
2390 | } |
2391 | ||
d0e96f5a SS |
2392 | /* |
2393 | * Does various checks on the endpoint ring, and makes it ready to queue num_trbs. | |
2394 | * FIXME allocate segments if the ring is full. | |
2395 | */ | |
2396 | static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring, | |
2397 | u32 ep_state, unsigned int num_trbs, gfp_t mem_flags) | |
2398 | { | |
2399 | /* Make sure the endpoint has been added to xHC schedule */ | |
2400 | xhci_dbg(xhci, "Endpoint state = 0x%x\n", ep_state); | |
2401 | switch (ep_state) { | |
2402 | case EP_STATE_DISABLED: | |
2403 | /* | |
2404 | * USB core changed config/interfaces without notifying us, | |
2405 | * or hardware is reporting the wrong state. | |
2406 | */ | |
2407 | xhci_warn(xhci, "WARN urb submitted to disabled ep\n"); | |
2408 | return -ENOENT; | |
d0e96f5a | 2409 | case EP_STATE_ERROR: |
c92bcfa7 | 2410 | xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n"); |
d0e96f5a SS |
2411 | /* FIXME event handling code for error needs to clear it */ |
2412 | /* XXX not sure if this should be -ENOENT or not */ | |
2413 | return -EINVAL; | |
c92bcfa7 SS |
2414 | case EP_STATE_HALTED: |
2415 | xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n"); | |
d0e96f5a SS |
2416 | case EP_STATE_STOPPED: |
2417 | case EP_STATE_RUNNING: | |
2418 | break; | |
2419 | default: | |
2420 | xhci_err(xhci, "ERROR unknown endpoint state for ep\n"); | |
2421 | /* | |
2422 | * FIXME issue Configure Endpoint command to try to get the HC | |
2423 | * back into a known state. | |
2424 | */ | |
2425 | return -EINVAL; | |
2426 | } | |
2427 | if (!room_on_ring(xhci, ep_ring, num_trbs)) { | |
2428 | /* FIXME allocate more room */ | |
2429 | xhci_err(xhci, "ERROR no room on ep ring\n"); | |
2430 | return -ENOMEM; | |
2431 | } | |
6c12db90 JY |
2432 | |
2433 | if (enqueue_is_link_trb(ep_ring)) { | |
2434 | struct xhci_ring *ring = ep_ring; | |
2435 | union xhci_trb *next; | |
6c12db90 JY |
2436 | |
2437 | xhci_dbg(xhci, "prepare_ring: pointing to link trb\n"); | |
2438 | next = ring->enqueue; | |
2439 | ||
2440 | while (last_trb(xhci, ring, ring->enq_seg, next)) { | |
6c12db90 JY |
2441 | /* If we're not dealing with 0.95 hardware, |
2442 | * clear the chain bit. | |
2443 | */ | |
2444 | if (!xhci_link_trb_quirk(xhci)) | |
28ccd296 | 2445 | next->link.control &= cpu_to_le32(~TRB_CHAIN); |
6c12db90 | 2446 | else |
28ccd296 | 2447 | next->link.control |= cpu_to_le32(TRB_CHAIN); |
6c12db90 JY |
2448 | |
2449 | wmb(); | |
28ccd296 | 2450 | next->link.control ^= cpu_to_le32((u32) TRB_CYCLE); |
6c12db90 JY |
2451 | |
2452 | /* Toggle the cycle bit after the last ring segment. */ | |
2453 | if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) { | |
2454 | ring->cycle_state = (ring->cycle_state ? 0 : 1); | |
2455 | if (!in_interrupt()) { | |
2456 | xhci_dbg(xhci, "queue_trb: Toggle cycle " | |
2457 | "state for ring %p = %i\n", | |
2458 | ring, (unsigned int)ring->cycle_state); | |
2459 | } | |
2460 | } | |
2461 | ring->enq_seg = ring->enq_seg->next; | |
2462 | ring->enqueue = ring->enq_seg->trbs; | |
2463 | next = ring->enqueue; | |
2464 | } | |
2465 | } | |
2466 | ||
d0e96f5a SS |
2467 | return 0; |
2468 | } | |
2469 | ||
23e3be11 | 2470 | static int prepare_transfer(struct xhci_hcd *xhci, |
d0e96f5a SS |
2471 | struct xhci_virt_device *xdev, |
2472 | unsigned int ep_index, | |
e9df17eb | 2473 | unsigned int stream_id, |
d0e96f5a SS |
2474 | unsigned int num_trbs, |
2475 | struct urb *urb, | |
8e51adcc | 2476 | unsigned int td_index, |
d0e96f5a SS |
2477 | gfp_t mem_flags) |
2478 | { | |
2479 | int ret; | |
8e51adcc AX |
2480 | struct urb_priv *urb_priv; |
2481 | struct xhci_td *td; | |
e9df17eb | 2482 | struct xhci_ring *ep_ring; |
d115b048 | 2483 | struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
e9df17eb SS |
2484 | |
2485 | ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id); | |
2486 | if (!ep_ring) { | |
2487 | xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n", | |
2488 | stream_id); | |
2489 | return -EINVAL; | |
2490 | } | |
2491 | ||
2492 | ret = prepare_ring(xhci, ep_ring, | |
28ccd296 ME |
2493 | le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK, |
2494 | num_trbs, mem_flags); | |
d0e96f5a SS |
2495 | if (ret) |
2496 | return ret; | |
d0e96f5a | 2497 | |
8e51adcc AX |
2498 | urb_priv = urb->hcpriv; |
2499 | td = urb_priv->td[td_index]; | |
2500 | ||
2501 | INIT_LIST_HEAD(&td->td_list); | |
2502 | INIT_LIST_HEAD(&td->cancelled_td_list); | |
2503 | ||
2504 | if (td_index == 0) { | |
214f76f7 | 2505 | ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb); |
8e51adcc AX |
2506 | if (unlikely(ret)) { |
2507 | xhci_urb_free_priv(xhci, urb_priv); | |
2508 | urb->hcpriv = NULL; | |
2509 | return ret; | |
2510 | } | |
d0e96f5a SS |
2511 | } |
2512 | ||
8e51adcc | 2513 | td->urb = urb; |
d0e96f5a | 2514 | /* Add this TD to the tail of the endpoint ring's TD list */ |
8e51adcc AX |
2515 | list_add_tail(&td->td_list, &ep_ring->td_list); |
2516 | td->start_seg = ep_ring->enq_seg; | |
2517 | td->first_trb = ep_ring->enqueue; | |
2518 | ||
2519 | urb_priv->td[td_index] = td; | |
d0e96f5a SS |
2520 | |
2521 | return 0; | |
2522 | } | |
2523 | ||
23e3be11 | 2524 | static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb) |
8a96c052 SS |
2525 | { |
2526 | int num_sgs, num_trbs, running_total, temp, i; | |
2527 | struct scatterlist *sg; | |
2528 | ||
2529 | sg = NULL; | |
2530 | num_sgs = urb->num_sgs; | |
2531 | temp = urb->transfer_buffer_length; | |
2532 | ||
2533 | xhci_dbg(xhci, "count sg list trbs: \n"); | |
2534 | num_trbs = 0; | |
910f8d0c | 2535 | for_each_sg(urb->sg, sg, num_sgs, i) { |
8a96c052 SS |
2536 | unsigned int previous_total_trbs = num_trbs; |
2537 | unsigned int len = sg_dma_len(sg); | |
2538 | ||
2539 | /* Scatter gather list entries may cross 64KB boundaries */ | |
2540 | running_total = TRB_MAX_BUFF_SIZE - | |
a2490187 | 2541 | (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1)); |
5807795b | 2542 | running_total &= TRB_MAX_BUFF_SIZE - 1; |
8a96c052 SS |
2543 | if (running_total != 0) |
2544 | num_trbs++; | |
2545 | ||
2546 | /* How many more 64KB chunks to transfer, how many more TRBs? */ | |
bcd2fde0 | 2547 | while (running_total < sg_dma_len(sg) && running_total < temp) { |
8a96c052 SS |
2548 | num_trbs++; |
2549 | running_total += TRB_MAX_BUFF_SIZE; | |
2550 | } | |
700e2052 GKH |
2551 | xhci_dbg(xhci, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n", |
2552 | i, (unsigned long long)sg_dma_address(sg), | |
2553 | len, len, num_trbs - previous_total_trbs); | |
8a96c052 SS |
2554 | |
2555 | len = min_t(int, len, temp); | |
2556 | temp -= len; | |
2557 | if (temp == 0) | |
2558 | break; | |
2559 | } | |
2560 | xhci_dbg(xhci, "\n"); | |
2561 | if (!in_interrupt()) | |
f2c565e2 AX |
2562 | xhci_dbg(xhci, "ep %#x - urb len = %d, sglist used, " |
2563 | "num_trbs = %d\n", | |
8a96c052 SS |
2564 | urb->ep->desc.bEndpointAddress, |
2565 | urb->transfer_buffer_length, | |
2566 | num_trbs); | |
2567 | return num_trbs; | |
2568 | } | |
2569 | ||
23e3be11 | 2570 | static void check_trb_math(struct urb *urb, int num_trbs, int running_total) |
8a96c052 SS |
2571 | { |
2572 | if (num_trbs != 0) | |
a2490187 | 2573 | dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of " |
8a96c052 SS |
2574 | "TRBs, %d left\n", __func__, |
2575 | urb->ep->desc.bEndpointAddress, num_trbs); | |
2576 | if (running_total != urb->transfer_buffer_length) | |
a2490187 | 2577 | dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, " |
8a96c052 SS |
2578 | "queued %#x (%d), asked for %#x (%d)\n", |
2579 | __func__, | |
2580 | urb->ep->desc.bEndpointAddress, | |
2581 | running_total, running_total, | |
2582 | urb->transfer_buffer_length, | |
2583 | urb->transfer_buffer_length); | |
2584 | } | |
2585 | ||
23e3be11 | 2586 | static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id, |
e9df17eb | 2587 | unsigned int ep_index, unsigned int stream_id, int start_cycle, |
e1eab2e0 | 2588 | struct xhci_generic_trb *start_trb) |
8a96c052 | 2589 | { |
8a96c052 SS |
2590 | /* |
2591 | * Pass all the TRBs to the hardware at once and make sure this write | |
2592 | * isn't reordered. | |
2593 | */ | |
2594 | wmb(); | |
50f7b52a | 2595 | if (start_cycle) |
28ccd296 | 2596 | start_trb->field[3] |= cpu_to_le32(start_cycle); |
50f7b52a | 2597 | else |
28ccd296 | 2598 | start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE); |
be88fe4f | 2599 | xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id); |
8a96c052 SS |
2600 | } |
2601 | ||
624defa1 SS |
2602 | /* |
2603 | * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt | |
2604 | * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD | |
2605 | * (comprised of sg list entries) can take several service intervals to | |
2606 | * transmit. | |
2607 | */ | |
2608 | int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |
2609 | struct urb *urb, int slot_id, unsigned int ep_index) | |
2610 | { | |
2611 | struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, | |
2612 | xhci->devs[slot_id]->out_ctx, ep_index); | |
2613 | int xhci_interval; | |
2614 | int ep_interval; | |
2615 | ||
28ccd296 | 2616 | xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info)); |
624defa1 SS |
2617 | ep_interval = urb->interval; |
2618 | /* Convert to microframes */ | |
2619 | if (urb->dev->speed == USB_SPEED_LOW || | |
2620 | urb->dev->speed == USB_SPEED_FULL) | |
2621 | ep_interval *= 8; | |
2622 | /* FIXME change this to a warning and a suggestion to use the new API | |
2623 | * to set the polling interval (once the API is added). | |
2624 | */ | |
2625 | if (xhci_interval != ep_interval) { | |
7961acd7 | 2626 | if (printk_ratelimit()) |
624defa1 SS |
2627 | dev_dbg(&urb->dev->dev, "Driver uses different interval" |
2628 | " (%d microframe%s) than xHCI " | |
2629 | "(%d microframe%s)\n", | |
2630 | ep_interval, | |
2631 | ep_interval == 1 ? "" : "s", | |
2632 | xhci_interval, | |
2633 | xhci_interval == 1 ? "" : "s"); | |
2634 | urb->interval = xhci_interval; | |
2635 | /* Convert back to frames for LS/FS devices */ | |
2636 | if (urb->dev->speed == USB_SPEED_LOW || | |
2637 | urb->dev->speed == USB_SPEED_FULL) | |
2638 | urb->interval /= 8; | |
2639 | } | |
2640 | return xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index); | |
2641 | } | |
2642 | ||
04dd950d SS |
2643 | /* |
2644 | * The TD size is the number of bytes remaining in the TD (including this TRB), | |
2645 | * right shifted by 10. | |
2646 | * It must fit in bits 21:17, so it can't be bigger than 31. | |
2647 | */ | |
2648 | static u32 xhci_td_remainder(unsigned int remainder) | |
2649 | { | |
2650 | u32 max = (1 << (21 - 17 + 1)) - 1; | |
2651 | ||
2652 | if ((remainder >> 10) >= max) | |
2653 | return max << 17; | |
2654 | else | |
2655 | return (remainder >> 10) << 17; | |
2656 | } | |
2657 | ||
23e3be11 | 2658 | static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags, |
8a96c052 SS |
2659 | struct urb *urb, int slot_id, unsigned int ep_index) |
2660 | { | |
2661 | struct xhci_ring *ep_ring; | |
2662 | unsigned int num_trbs; | |
8e51adcc | 2663 | struct urb_priv *urb_priv; |
8a96c052 SS |
2664 | struct xhci_td *td; |
2665 | struct scatterlist *sg; | |
2666 | int num_sgs; | |
2667 | int trb_buff_len, this_sg_len, running_total; | |
2668 | bool first_trb; | |
2669 | u64 addr; | |
6cc30d85 | 2670 | bool more_trbs_coming; |
8a96c052 SS |
2671 | |
2672 | struct xhci_generic_trb *start_trb; | |
2673 | int start_cycle; | |
2674 | ||
e9df17eb SS |
2675 | ep_ring = xhci_urb_to_transfer_ring(xhci, urb); |
2676 | if (!ep_ring) | |
2677 | return -EINVAL; | |
2678 | ||
8a96c052 SS |
2679 | num_trbs = count_sg_trbs_needed(xhci, urb); |
2680 | num_sgs = urb->num_sgs; | |
2681 | ||
23e3be11 | 2682 | trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id], |
e9df17eb | 2683 | ep_index, urb->stream_id, |
8e51adcc | 2684 | num_trbs, urb, 0, mem_flags); |
8a96c052 SS |
2685 | if (trb_buff_len < 0) |
2686 | return trb_buff_len; | |
8e51adcc AX |
2687 | |
2688 | urb_priv = urb->hcpriv; | |
2689 | td = urb_priv->td[0]; | |
2690 | ||
8a96c052 SS |
2691 | /* |
2692 | * Don't give the first TRB to the hardware (by toggling the cycle bit) | |
2693 | * until we've finished creating all the other TRBs. The ring's cycle | |
2694 | * state may change as we enqueue the other TRBs, so save it too. | |
2695 | */ | |
2696 | start_trb = &ep_ring->enqueue->generic; | |
2697 | start_cycle = ep_ring->cycle_state; | |
2698 | ||
2699 | running_total = 0; | |
2700 | /* | |
2701 | * How much data is in the first TRB? | |
2702 | * | |
2703 | * There are three forces at work for TRB buffer pointers and lengths: | |
2704 | * 1. We don't want to walk off the end of this sg-list entry buffer. | |
2705 | * 2. The transfer length that the driver requested may be smaller than | |
2706 | * the amount of memory allocated for this scatter-gather list. | |
2707 | * 3. TRBs buffers can't cross 64KB boundaries. | |
2708 | */ | |
910f8d0c | 2709 | sg = urb->sg; |
8a96c052 SS |
2710 | addr = (u64) sg_dma_address(sg); |
2711 | this_sg_len = sg_dma_len(sg); | |
a2490187 | 2712 | trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1)); |
8a96c052 SS |
2713 | trb_buff_len = min_t(int, trb_buff_len, this_sg_len); |
2714 | if (trb_buff_len > urb->transfer_buffer_length) | |
2715 | trb_buff_len = urb->transfer_buffer_length; | |
2716 | xhci_dbg(xhci, "First length to xfer from 1st sglist entry = %u\n", | |
2717 | trb_buff_len); | |
2718 | ||
2719 | first_trb = true; | |
2720 | /* Queue the first TRB, even if it's zero-length */ | |
2721 | do { | |
2722 | u32 field = 0; | |
f9dc68fe | 2723 | u32 length_field = 0; |
04dd950d | 2724 | u32 remainder = 0; |
8a96c052 SS |
2725 | |
2726 | /* Don't change the cycle bit of the first TRB until later */ | |
50f7b52a | 2727 | if (first_trb) { |
8a96c052 | 2728 | first_trb = false; |
50f7b52a AX |
2729 | if (start_cycle == 0) |
2730 | field |= 0x1; | |
2731 | } else | |
8a96c052 SS |
2732 | field |= ep_ring->cycle_state; |
2733 | ||
2734 | /* Chain all the TRBs together; clear the chain bit in the last | |
2735 | * TRB to indicate it's the last TRB in the chain. | |
2736 | */ | |
2737 | if (num_trbs > 1) { | |
2738 | field |= TRB_CHAIN; | |
2739 | } else { | |
2740 | /* FIXME - add check for ZERO_PACKET flag before this */ | |
2741 | td->last_trb = ep_ring->enqueue; | |
2742 | field |= TRB_IOC; | |
2743 | } | |
2744 | xhci_dbg(xhci, " sg entry: dma = %#x, len = %#x (%d), " | |
2745 | "64KB boundary at %#x, end dma = %#x\n", | |
2746 | (unsigned int) addr, trb_buff_len, trb_buff_len, | |
2747 | (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1), | |
2748 | (unsigned int) addr + trb_buff_len); | |
2749 | if (TRB_MAX_BUFF_SIZE - | |
a2490187 | 2750 | (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) { |
8a96c052 SS |
2751 | xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n"); |
2752 | xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n", | |
2753 | (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1), | |
2754 | (unsigned int) addr + trb_buff_len); | |
2755 | } | |
04dd950d SS |
2756 | remainder = xhci_td_remainder(urb->transfer_buffer_length - |
2757 | running_total) ; | |
f9dc68fe | 2758 | length_field = TRB_LEN(trb_buff_len) | |
04dd950d | 2759 | remainder | |
f9dc68fe | 2760 | TRB_INTR_TARGET(0); |
6cc30d85 SS |
2761 | if (num_trbs > 1) |
2762 | more_trbs_coming = true; | |
2763 | else | |
2764 | more_trbs_coming = false; | |
2765 | queue_trb(xhci, ep_ring, false, more_trbs_coming, | |
8e595a5d SS |
2766 | lower_32_bits(addr), |
2767 | upper_32_bits(addr), | |
f9dc68fe | 2768 | length_field, |
8a96c052 SS |
2769 | /* We always want to know if the TRB was short, |
2770 | * or we won't get an event when it completes. | |
2771 | * (Unless we use event data TRBs, which are a | |
2772 | * waste of space and HC resources.) | |
2773 | */ | |
2774 | field | TRB_ISP | TRB_TYPE(TRB_NORMAL)); | |
2775 | --num_trbs; | |
2776 | running_total += trb_buff_len; | |
2777 | ||
2778 | /* Calculate length for next transfer -- | |
2779 | * Are we done queueing all the TRBs for this sg entry? | |
2780 | */ | |
2781 | this_sg_len -= trb_buff_len; | |
2782 | if (this_sg_len == 0) { | |
2783 | --num_sgs; | |
2784 | if (num_sgs == 0) | |
2785 | break; | |
2786 | sg = sg_next(sg); | |
2787 | addr = (u64) sg_dma_address(sg); | |
2788 | this_sg_len = sg_dma_len(sg); | |
2789 | } else { | |
2790 | addr += trb_buff_len; | |
2791 | } | |
2792 | ||
2793 | trb_buff_len = TRB_MAX_BUFF_SIZE - | |
a2490187 | 2794 | (addr & (TRB_MAX_BUFF_SIZE - 1)); |
8a96c052 SS |
2795 | trb_buff_len = min_t(int, trb_buff_len, this_sg_len); |
2796 | if (running_total + trb_buff_len > urb->transfer_buffer_length) | |
2797 | trb_buff_len = | |
2798 | urb->transfer_buffer_length - running_total; | |
2799 | } while (running_total < urb->transfer_buffer_length); | |
2800 | ||
2801 | check_trb_math(urb, num_trbs, running_total); | |
e9df17eb | 2802 | giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, |
e1eab2e0 | 2803 | start_cycle, start_trb); |
8a96c052 SS |
2804 | return 0; |
2805 | } | |
2806 | ||
b10de142 | 2807 | /* This is very similar to what ehci-q.c qtd_fill() does */ |
23e3be11 | 2808 | int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, |
b10de142 SS |
2809 | struct urb *urb, int slot_id, unsigned int ep_index) |
2810 | { | |
2811 | struct xhci_ring *ep_ring; | |
8e51adcc | 2812 | struct urb_priv *urb_priv; |
b10de142 SS |
2813 | struct xhci_td *td; |
2814 | int num_trbs; | |
2815 | struct xhci_generic_trb *start_trb; | |
2816 | bool first_trb; | |
6cc30d85 | 2817 | bool more_trbs_coming; |
b10de142 | 2818 | int start_cycle; |
f9dc68fe | 2819 | u32 field, length_field; |
b10de142 SS |
2820 | |
2821 | int running_total, trb_buff_len, ret; | |
2822 | u64 addr; | |
2823 | ||
ff9c895f | 2824 | if (urb->num_sgs) |
8a96c052 SS |
2825 | return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index); |
2826 | ||
e9df17eb SS |
2827 | ep_ring = xhci_urb_to_transfer_ring(xhci, urb); |
2828 | if (!ep_ring) | |
2829 | return -EINVAL; | |
b10de142 SS |
2830 | |
2831 | num_trbs = 0; | |
2832 | /* How much data is (potentially) left before the 64KB boundary? */ | |
2833 | running_total = TRB_MAX_BUFF_SIZE - | |
a2490187 | 2834 | (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1)); |
5807795b | 2835 | running_total &= TRB_MAX_BUFF_SIZE - 1; |
b10de142 SS |
2836 | |
2837 | /* If there's some data on this 64KB chunk, or we have to send a | |
2838 | * zero-length transfer, we need at least one TRB | |
2839 | */ | |
2840 | if (running_total != 0 || urb->transfer_buffer_length == 0) | |
2841 | num_trbs++; | |
2842 | /* How many more 64KB chunks to transfer, how many more TRBs? */ | |
2843 | while (running_total < urb->transfer_buffer_length) { | |
2844 | num_trbs++; | |
2845 | running_total += TRB_MAX_BUFF_SIZE; | |
2846 | } | |
2847 | /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */ | |
2848 | ||
2849 | if (!in_interrupt()) | |
f2c565e2 AX |
2850 | xhci_dbg(xhci, "ep %#x - urb len = %#x (%d), " |
2851 | "addr = %#llx, num_trbs = %d\n", | |
b10de142 | 2852 | urb->ep->desc.bEndpointAddress, |
8a96c052 SS |
2853 | urb->transfer_buffer_length, |
2854 | urb->transfer_buffer_length, | |
700e2052 | 2855 | (unsigned long long)urb->transfer_dma, |
b10de142 | 2856 | num_trbs); |
8a96c052 | 2857 | |
e9df17eb SS |
2858 | ret = prepare_transfer(xhci, xhci->devs[slot_id], |
2859 | ep_index, urb->stream_id, | |
8e51adcc | 2860 | num_trbs, urb, 0, mem_flags); |
b10de142 SS |
2861 | if (ret < 0) |
2862 | return ret; | |
2863 | ||
8e51adcc AX |
2864 | urb_priv = urb->hcpriv; |
2865 | td = urb_priv->td[0]; | |
2866 | ||
b10de142 SS |
2867 | /* |
2868 | * Don't give the first TRB to the hardware (by toggling the cycle bit) | |
2869 | * until we've finished creating all the other TRBs. The ring's cycle | |
2870 | * state may change as we enqueue the other TRBs, so save it too. | |
2871 | */ | |
2872 | start_trb = &ep_ring->enqueue->generic; | |
2873 | start_cycle = ep_ring->cycle_state; | |
2874 | ||
2875 | running_total = 0; | |
2876 | /* How much data is in the first TRB? */ | |
2877 | addr = (u64) urb->transfer_dma; | |
2878 | trb_buff_len = TRB_MAX_BUFF_SIZE - | |
a2490187 PZ |
2879 | (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1)); |
2880 | if (trb_buff_len > urb->transfer_buffer_length) | |
b10de142 SS |
2881 | trb_buff_len = urb->transfer_buffer_length; |
2882 | ||
2883 | first_trb = true; | |
2884 | ||
2885 | /* Queue the first TRB, even if it's zero-length */ | |
2886 | do { | |
04dd950d | 2887 | u32 remainder = 0; |
b10de142 SS |
2888 | field = 0; |
2889 | ||
2890 | /* Don't change the cycle bit of the first TRB until later */ | |
50f7b52a | 2891 | if (first_trb) { |
b10de142 | 2892 | first_trb = false; |
50f7b52a AX |
2893 | if (start_cycle == 0) |
2894 | field |= 0x1; | |
2895 | } else | |
b10de142 SS |
2896 | field |= ep_ring->cycle_state; |
2897 | ||
2898 | /* Chain all the TRBs together; clear the chain bit in the last | |
2899 | * TRB to indicate it's the last TRB in the chain. | |
2900 | */ | |
2901 | if (num_trbs > 1) { | |
2902 | field |= TRB_CHAIN; | |
2903 | } else { | |
2904 | /* FIXME - add check for ZERO_PACKET flag before this */ | |
2905 | td->last_trb = ep_ring->enqueue; | |
2906 | field |= TRB_IOC; | |
2907 | } | |
04dd950d SS |
2908 | remainder = xhci_td_remainder(urb->transfer_buffer_length - |
2909 | running_total); | |
f9dc68fe | 2910 | length_field = TRB_LEN(trb_buff_len) | |
04dd950d | 2911 | remainder | |
f9dc68fe | 2912 | TRB_INTR_TARGET(0); |
6cc30d85 SS |
2913 | if (num_trbs > 1) |
2914 | more_trbs_coming = true; | |
2915 | else | |
2916 | more_trbs_coming = false; | |
2917 | queue_trb(xhci, ep_ring, false, more_trbs_coming, | |
8e595a5d SS |
2918 | lower_32_bits(addr), |
2919 | upper_32_bits(addr), | |
f9dc68fe | 2920 | length_field, |
b10de142 SS |
2921 | /* We always want to know if the TRB was short, |
2922 | * or we won't get an event when it completes. | |
2923 | * (Unless we use event data TRBs, which are a | |
2924 | * waste of space and HC resources.) | |
2925 | */ | |
2926 | field | TRB_ISP | TRB_TYPE(TRB_NORMAL)); | |
2927 | --num_trbs; | |
2928 | running_total += trb_buff_len; | |
2929 | ||
2930 | /* Calculate length for next transfer */ | |
2931 | addr += trb_buff_len; | |
2932 | trb_buff_len = urb->transfer_buffer_length - running_total; | |
2933 | if (trb_buff_len > TRB_MAX_BUFF_SIZE) | |
2934 | trb_buff_len = TRB_MAX_BUFF_SIZE; | |
2935 | } while (running_total < urb->transfer_buffer_length); | |
2936 | ||
8a96c052 | 2937 | check_trb_math(urb, num_trbs, running_total); |
e9df17eb | 2938 | giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, |
e1eab2e0 | 2939 | start_cycle, start_trb); |
b10de142 SS |
2940 | return 0; |
2941 | } | |
2942 | ||
d0e96f5a | 2943 | /* Caller must have locked xhci->lock */ |
23e3be11 | 2944 | int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, |
d0e96f5a SS |
2945 | struct urb *urb, int slot_id, unsigned int ep_index) |
2946 | { | |
2947 | struct xhci_ring *ep_ring; | |
2948 | int num_trbs; | |
2949 | int ret; | |
2950 | struct usb_ctrlrequest *setup; | |
2951 | struct xhci_generic_trb *start_trb; | |
2952 | int start_cycle; | |
f9dc68fe | 2953 | u32 field, length_field; |
8e51adcc | 2954 | struct urb_priv *urb_priv; |
d0e96f5a SS |
2955 | struct xhci_td *td; |
2956 | ||
e9df17eb SS |
2957 | ep_ring = xhci_urb_to_transfer_ring(xhci, urb); |
2958 | if (!ep_ring) | |
2959 | return -EINVAL; | |
d0e96f5a SS |
2960 | |
2961 | /* | |
2962 | * Need to copy setup packet into setup TRB, so we can't use the setup | |
2963 | * DMA address. | |
2964 | */ | |
2965 | if (!urb->setup_packet) | |
2966 | return -EINVAL; | |
2967 | ||
2968 | if (!in_interrupt()) | |
2969 | xhci_dbg(xhci, "Queueing ctrl tx for slot id %d, ep %d\n", | |
2970 | slot_id, ep_index); | |
2971 | /* 1 TRB for setup, 1 for status */ | |
2972 | num_trbs = 2; | |
2973 | /* | |
2974 | * Don't need to check if we need additional event data and normal TRBs, | |
2975 | * since data in control transfers will never get bigger than 16MB | |
2976 | * XXX: can we get a buffer that crosses 64KB boundaries? | |
2977 | */ | |
2978 | if (urb->transfer_buffer_length > 0) | |
2979 | num_trbs++; | |
e9df17eb SS |
2980 | ret = prepare_transfer(xhci, xhci->devs[slot_id], |
2981 | ep_index, urb->stream_id, | |
8e51adcc | 2982 | num_trbs, urb, 0, mem_flags); |
d0e96f5a SS |
2983 | if (ret < 0) |
2984 | return ret; | |
2985 | ||
8e51adcc AX |
2986 | urb_priv = urb->hcpriv; |
2987 | td = urb_priv->td[0]; | |
2988 | ||
d0e96f5a SS |
2989 | /* |
2990 | * Don't give the first TRB to the hardware (by toggling the cycle bit) | |
2991 | * until we've finished creating all the other TRBs. The ring's cycle | |
2992 | * state may change as we enqueue the other TRBs, so save it too. | |
2993 | */ | |
2994 | start_trb = &ep_ring->enqueue->generic; | |
2995 | start_cycle = ep_ring->cycle_state; | |
2996 | ||
2997 | /* Queue setup TRB - see section 6.4.1.2.1 */ | |
2998 | /* FIXME better way to translate setup_packet into two u32 fields? */ | |
2999 | setup = (struct usb_ctrlrequest *) urb->setup_packet; | |
50f7b52a AX |
3000 | field = 0; |
3001 | field |= TRB_IDT | TRB_TYPE(TRB_SETUP); | |
3002 | if (start_cycle == 0) | |
3003 | field |= 0x1; | |
6cc30d85 | 3004 | queue_trb(xhci, ep_ring, false, true, |
28ccd296 ME |
3005 | setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16, |
3006 | le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16, | |
3007 | TRB_LEN(8) | TRB_INTR_TARGET(0), | |
3008 | /* Immediate data in pointer */ | |
3009 | field); | |
d0e96f5a SS |
3010 | |
3011 | /* If there's data, queue data TRBs */ | |
3012 | field = 0; | |
f9dc68fe | 3013 | length_field = TRB_LEN(urb->transfer_buffer_length) | |
04dd950d | 3014 | xhci_td_remainder(urb->transfer_buffer_length) | |
f9dc68fe | 3015 | TRB_INTR_TARGET(0); |
d0e96f5a SS |
3016 | if (urb->transfer_buffer_length > 0) { |
3017 | if (setup->bRequestType & USB_DIR_IN) | |
3018 | field |= TRB_DIR_IN; | |
6cc30d85 | 3019 | queue_trb(xhci, ep_ring, false, true, |
d0e96f5a SS |
3020 | lower_32_bits(urb->transfer_dma), |
3021 | upper_32_bits(urb->transfer_dma), | |
f9dc68fe | 3022 | length_field, |
d0e96f5a SS |
3023 | /* Event on short tx */ |
3024 | field | TRB_ISP | TRB_TYPE(TRB_DATA) | ep_ring->cycle_state); | |
3025 | } | |
3026 | ||
3027 | /* Save the DMA address of the last TRB in the TD */ | |
3028 | td->last_trb = ep_ring->enqueue; | |
3029 | ||
3030 | /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */ | |
3031 | /* If the device sent data, the status stage is an OUT transfer */ | |
3032 | if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN) | |
3033 | field = 0; | |
3034 | else | |
3035 | field = TRB_DIR_IN; | |
6cc30d85 | 3036 | queue_trb(xhci, ep_ring, false, false, |
d0e96f5a SS |
3037 | 0, |
3038 | 0, | |
3039 | TRB_INTR_TARGET(0), | |
3040 | /* Event on completion */ | |
3041 | field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state); | |
3042 | ||
e9df17eb | 3043 | giveback_first_trb(xhci, slot_id, ep_index, 0, |
e1eab2e0 | 3044 | start_cycle, start_trb); |
d0e96f5a SS |
3045 | return 0; |
3046 | } | |
3047 | ||
04e51901 AX |
3048 | static int count_isoc_trbs_needed(struct xhci_hcd *xhci, |
3049 | struct urb *urb, int i) | |
3050 | { | |
3051 | int num_trbs = 0; | |
3052 | u64 addr, td_len, running_total; | |
3053 | ||
3054 | addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset); | |
3055 | td_len = urb->iso_frame_desc[i].length; | |
3056 | ||
a2490187 | 3057 | running_total = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1)); |
5807795b | 3058 | running_total &= TRB_MAX_BUFF_SIZE - 1; |
04e51901 AX |
3059 | if (running_total != 0) |
3060 | num_trbs++; | |
3061 | ||
3062 | while (running_total < td_len) { | |
3063 | num_trbs++; | |
3064 | running_total += TRB_MAX_BUFF_SIZE; | |
3065 | } | |
3066 | ||
3067 | return num_trbs; | |
3068 | } | |
3069 | ||
3070 | /* This is for isoc transfer */ | |
3071 | static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |
3072 | struct urb *urb, int slot_id, unsigned int ep_index) | |
3073 | { | |
3074 | struct xhci_ring *ep_ring; | |
3075 | struct urb_priv *urb_priv; | |
3076 | struct xhci_td *td; | |
3077 | int num_tds, trbs_per_td; | |
3078 | struct xhci_generic_trb *start_trb; | |
3079 | bool first_trb; | |
3080 | int start_cycle; | |
3081 | u32 field, length_field; | |
3082 | int running_total, trb_buff_len, td_len, td_remain_len, ret; | |
3083 | u64 start_addr, addr; | |
3084 | int i, j; | |
47cbf692 | 3085 | bool more_trbs_coming; |
04e51901 AX |
3086 | |
3087 | ep_ring = xhci->devs[slot_id]->eps[ep_index].ring; | |
3088 | ||
3089 | num_tds = urb->number_of_packets; | |
3090 | if (num_tds < 1) { | |
3091 | xhci_dbg(xhci, "Isoc URB with zero packets?\n"); | |
3092 | return -EINVAL; | |
3093 | } | |
3094 | ||
3095 | if (!in_interrupt()) | |
f2c565e2 | 3096 | xhci_dbg(xhci, "ep %#x - urb len = %#x (%d)," |
04e51901 AX |
3097 | " addr = %#llx, num_tds = %d\n", |
3098 | urb->ep->desc.bEndpointAddress, | |
3099 | urb->transfer_buffer_length, | |
3100 | urb->transfer_buffer_length, | |
3101 | (unsigned long long)urb->transfer_dma, | |
3102 | num_tds); | |
3103 | ||
3104 | start_addr = (u64) urb->transfer_dma; | |
3105 | start_trb = &ep_ring->enqueue->generic; | |
3106 | start_cycle = ep_ring->cycle_state; | |
3107 | ||
3108 | /* Queue the first TRB, even if it's zero-length */ | |
3109 | for (i = 0; i < num_tds; i++) { | |
3110 | first_trb = true; | |
3111 | ||
3112 | running_total = 0; | |
3113 | addr = start_addr + urb->iso_frame_desc[i].offset; | |
3114 | td_len = urb->iso_frame_desc[i].length; | |
3115 | td_remain_len = td_len; | |
3116 | ||
3117 | trbs_per_td = count_isoc_trbs_needed(xhci, urb, i); | |
3118 | ||
3119 | ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index, | |
3120 | urb->stream_id, trbs_per_td, urb, i, mem_flags); | |
3121 | if (ret < 0) | |
3122 | return ret; | |
3123 | ||
3124 | urb_priv = urb->hcpriv; | |
3125 | td = urb_priv->td[i]; | |
3126 | ||
3127 | for (j = 0; j < trbs_per_td; j++) { | |
3128 | u32 remainder = 0; | |
3129 | field = 0; | |
3130 | ||
3131 | if (first_trb) { | |
3132 | /* Queue the isoc TRB */ | |
3133 | field |= TRB_TYPE(TRB_ISOC); | |
3134 | /* Assume URB_ISO_ASAP is set */ | |
3135 | field |= TRB_SIA; | |
50f7b52a AX |
3136 | if (i == 0) { |
3137 | if (start_cycle == 0) | |
3138 | field |= 0x1; | |
3139 | } else | |
04e51901 AX |
3140 | field |= ep_ring->cycle_state; |
3141 | first_trb = false; | |
3142 | } else { | |
3143 | /* Queue other normal TRBs */ | |
3144 | field |= TRB_TYPE(TRB_NORMAL); | |
3145 | field |= ep_ring->cycle_state; | |
3146 | } | |
3147 | ||
3148 | /* Chain all the TRBs together; clear the chain bit in | |
3149 | * the last TRB to indicate it's the last TRB in the | |
3150 | * chain. | |
3151 | */ | |
3152 | if (j < trbs_per_td - 1) { | |
3153 | field |= TRB_CHAIN; | |
47cbf692 | 3154 | more_trbs_coming = true; |
04e51901 AX |
3155 | } else { |
3156 | td->last_trb = ep_ring->enqueue; | |
3157 | field |= TRB_IOC; | |
47cbf692 | 3158 | more_trbs_coming = false; |
04e51901 AX |
3159 | } |
3160 | ||
3161 | /* Calculate TRB length */ | |
3162 | trb_buff_len = TRB_MAX_BUFF_SIZE - | |
3163 | (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1)); | |
3164 | if (trb_buff_len > td_remain_len) | |
3165 | trb_buff_len = td_remain_len; | |
3166 | ||
3167 | remainder = xhci_td_remainder(td_len - running_total); | |
3168 | length_field = TRB_LEN(trb_buff_len) | | |
3169 | remainder | | |
3170 | TRB_INTR_TARGET(0); | |
47cbf692 | 3171 | queue_trb(xhci, ep_ring, false, more_trbs_coming, |
04e51901 AX |
3172 | lower_32_bits(addr), |
3173 | upper_32_bits(addr), | |
3174 | length_field, | |
3175 | /* We always want to know if the TRB was short, | |
3176 | * or we won't get an event when it completes. | |
3177 | * (Unless we use event data TRBs, which are a | |
3178 | * waste of space and HC resources.) | |
3179 | */ | |
3180 | field | TRB_ISP); | |
3181 | running_total += trb_buff_len; | |
3182 | ||
3183 | addr += trb_buff_len; | |
3184 | td_remain_len -= trb_buff_len; | |
3185 | } | |
3186 | ||
3187 | /* Check TD length */ | |
3188 | if (running_total != td_len) { | |
3189 | xhci_err(xhci, "ISOC TD length unmatch\n"); | |
3190 | return -EINVAL; | |
3191 | } | |
3192 | } | |
3193 | ||
c41136b0 AX |
3194 | if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) { |
3195 | if (xhci->quirks & XHCI_AMD_PLL_FIX) | |
3196 | usb_amd_quirk_pll_disable(); | |
3197 | } | |
3198 | xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++; | |
3199 | ||
e1eab2e0 AX |
3200 | giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, |
3201 | start_cycle, start_trb); | |
04e51901 AX |
3202 | return 0; |
3203 | } | |
3204 | ||
3205 | /* | |
3206 | * Check transfer ring to guarantee there is enough room for the urb. | |
3207 | * Update ISO URB start_frame and interval. | |
3208 | * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to | |
3209 | * update the urb->start_frame by now. | |
3210 | * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input. | |
3211 | */ | |
3212 | int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags, | |
3213 | struct urb *urb, int slot_id, unsigned int ep_index) | |
3214 | { | |
3215 | struct xhci_virt_device *xdev; | |
3216 | struct xhci_ring *ep_ring; | |
3217 | struct xhci_ep_ctx *ep_ctx; | |
3218 | int start_frame; | |
3219 | int xhci_interval; | |
3220 | int ep_interval; | |
3221 | int num_tds, num_trbs, i; | |
3222 | int ret; | |
3223 | ||
3224 | xdev = xhci->devs[slot_id]; | |
3225 | ep_ring = xdev->eps[ep_index].ring; | |
3226 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); | |
3227 | ||
3228 | num_trbs = 0; | |
3229 | num_tds = urb->number_of_packets; | |
3230 | for (i = 0; i < num_tds; i++) | |
3231 | num_trbs += count_isoc_trbs_needed(xhci, urb, i); | |
3232 | ||
3233 | /* Check the ring to guarantee there is enough room for the whole urb. | |
3234 | * Do not insert any td of the urb to the ring if the check failed. | |
3235 | */ | |
28ccd296 ME |
3236 | ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK, |
3237 | num_trbs, mem_flags); | |
04e51901 AX |
3238 | if (ret) |
3239 | return ret; | |
3240 | ||
3241 | start_frame = xhci_readl(xhci, &xhci->run_regs->microframe_index); | |
3242 | start_frame &= 0x3fff; | |
3243 | ||
3244 | urb->start_frame = start_frame; | |
3245 | if (urb->dev->speed == USB_SPEED_LOW || | |
3246 | urb->dev->speed == USB_SPEED_FULL) | |
3247 | urb->start_frame >>= 3; | |
3248 | ||
28ccd296 | 3249 | xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info)); |
04e51901 AX |
3250 | ep_interval = urb->interval; |
3251 | /* Convert to microframes */ | |
3252 | if (urb->dev->speed == USB_SPEED_LOW || | |
3253 | urb->dev->speed == USB_SPEED_FULL) | |
3254 | ep_interval *= 8; | |
3255 | /* FIXME change this to a warning and a suggestion to use the new API | |
3256 | * to set the polling interval (once the API is added). | |
3257 | */ | |
3258 | if (xhci_interval != ep_interval) { | |
7961acd7 | 3259 | if (printk_ratelimit()) |
04e51901 AX |
3260 | dev_dbg(&urb->dev->dev, "Driver uses different interval" |
3261 | " (%d microframe%s) than xHCI " | |
3262 | "(%d microframe%s)\n", | |
3263 | ep_interval, | |
3264 | ep_interval == 1 ? "" : "s", | |
3265 | xhci_interval, | |
3266 | xhci_interval == 1 ? "" : "s"); | |
3267 | urb->interval = xhci_interval; | |
3268 | /* Convert back to frames for LS/FS devices */ | |
3269 | if (urb->dev->speed == USB_SPEED_LOW || | |
3270 | urb->dev->speed == USB_SPEED_FULL) | |
3271 | urb->interval /= 8; | |
3272 | } | |
3273 | return xhci_queue_isoc_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index); | |
3274 | } | |
3275 | ||
d0e96f5a SS |
3276 | /**** Command Ring Operations ****/ |
3277 | ||
913a8a34 SS |
3278 | /* Generic function for queueing a command TRB on the command ring. |
3279 | * Check to make sure there's room on the command ring for one command TRB. | |
3280 | * Also check that there's room reserved for commands that must not fail. | |
3281 | * If this is a command that must not fail, meaning command_must_succeed = TRUE, | |
3282 | * then only check for the number of reserved spots. | |
3283 | * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB | |
3284 | * because the command event handler may want to resubmit a failed command. | |
3285 | */ | |
3286 | static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2, | |
3287 | u32 field3, u32 field4, bool command_must_succeed) | |
7f84eef0 | 3288 | { |
913a8a34 | 3289 | int reserved_trbs = xhci->cmd_ring_reserved_trbs; |
d1dc908a SS |
3290 | int ret; |
3291 | ||
913a8a34 SS |
3292 | if (!command_must_succeed) |
3293 | reserved_trbs++; | |
3294 | ||
d1dc908a SS |
3295 | ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING, |
3296 | reserved_trbs, GFP_ATOMIC); | |
3297 | if (ret < 0) { | |
3298 | xhci_err(xhci, "ERR: No room for command on command ring\n"); | |
913a8a34 SS |
3299 | if (command_must_succeed) |
3300 | xhci_err(xhci, "ERR: Reserved TRB counting for " | |
3301 | "unfailable commands failed.\n"); | |
d1dc908a | 3302 | return ret; |
7f84eef0 | 3303 | } |
6cc30d85 | 3304 | queue_trb(xhci, xhci->cmd_ring, false, false, field1, field2, field3, |
7f84eef0 SS |
3305 | field4 | xhci->cmd_ring->cycle_state); |
3306 | return 0; | |
3307 | } | |
3308 | ||
3ffbba95 | 3309 | /* Queue a slot enable or disable request on the command ring */ |
23e3be11 | 3310 | int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id) |
3ffbba95 SS |
3311 | { |
3312 | return queue_command(xhci, 0, 0, 0, | |
913a8a34 | 3313 | TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false); |
3ffbba95 SS |
3314 | } |
3315 | ||
3316 | /* Queue an address device command TRB */ | |
23e3be11 SS |
3317 | int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, |
3318 | u32 slot_id) | |
3ffbba95 | 3319 | { |
8e595a5d SS |
3320 | return queue_command(xhci, lower_32_bits(in_ctx_ptr), |
3321 | upper_32_bits(in_ctx_ptr), 0, | |
913a8a34 | 3322 | TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id), |
2a8f82c4 SS |
3323 | false); |
3324 | } | |
3325 | ||
0238634d SS |
3326 | int xhci_queue_vendor_command(struct xhci_hcd *xhci, |
3327 | u32 field1, u32 field2, u32 field3, u32 field4) | |
3328 | { | |
3329 | return queue_command(xhci, field1, field2, field3, field4, false); | |
3330 | } | |
3331 | ||
2a8f82c4 SS |
3332 | /* Queue a reset device command TRB */ |
3333 | int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id) | |
3334 | { | |
3335 | return queue_command(xhci, 0, 0, 0, | |
3336 | TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id), | |
913a8a34 | 3337 | false); |
3ffbba95 | 3338 | } |
f94e0186 SS |
3339 | |
3340 | /* Queue a configure endpoint command TRB */ | |
23e3be11 | 3341 | int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, |
913a8a34 | 3342 | u32 slot_id, bool command_must_succeed) |
f94e0186 | 3343 | { |
8e595a5d SS |
3344 | return queue_command(xhci, lower_32_bits(in_ctx_ptr), |
3345 | upper_32_bits(in_ctx_ptr), 0, | |
913a8a34 SS |
3346 | TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id), |
3347 | command_must_succeed); | |
f94e0186 | 3348 | } |
ae636747 | 3349 | |
f2217e8e SS |
3350 | /* Queue an evaluate context command TRB */ |
3351 | int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, | |
3352 | u32 slot_id) | |
3353 | { | |
3354 | return queue_command(xhci, lower_32_bits(in_ctx_ptr), | |
3355 | upper_32_bits(in_ctx_ptr), 0, | |
913a8a34 SS |
3356 | TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id), |
3357 | false); | |
f2217e8e SS |
3358 | } |
3359 | ||
be88fe4f AX |
3360 | /* |
3361 | * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop | |
3362 | * activity on an endpoint that is about to be suspended. | |
3363 | */ | |
23e3be11 | 3364 | int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id, |
be88fe4f | 3365 | unsigned int ep_index, int suspend) |
ae636747 SS |
3366 | { |
3367 | u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); | |
3368 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); | |
3369 | u32 type = TRB_TYPE(TRB_STOP_RING); | |
be88fe4f | 3370 | u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend); |
ae636747 SS |
3371 | |
3372 | return queue_command(xhci, 0, 0, 0, | |
be88fe4f | 3373 | trb_slot_id | trb_ep_index | type | trb_suspend, false); |
ae636747 SS |
3374 | } |
3375 | ||
3376 | /* Set Transfer Ring Dequeue Pointer command. | |
3377 | * This should not be used for endpoints that have streams enabled. | |
3378 | */ | |
3379 | static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id, | |
e9df17eb SS |
3380 | unsigned int ep_index, unsigned int stream_id, |
3381 | struct xhci_segment *deq_seg, | |
ae636747 SS |
3382 | union xhci_trb *deq_ptr, u32 cycle_state) |
3383 | { | |
3384 | dma_addr_t addr; | |
3385 | u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); | |
3386 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); | |
e9df17eb | 3387 | u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id); |
ae636747 | 3388 | u32 type = TRB_TYPE(TRB_SET_DEQ); |
bf161e85 | 3389 | struct xhci_virt_ep *ep; |
ae636747 | 3390 | |
23e3be11 | 3391 | addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr); |
c92bcfa7 | 3392 | if (addr == 0) { |
ae636747 | 3393 | xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n"); |
700e2052 GKH |
3394 | xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n", |
3395 | deq_seg, deq_ptr); | |
c92bcfa7 SS |
3396 | return 0; |
3397 | } | |
bf161e85 SS |
3398 | ep = &xhci->devs[slot_id]->eps[ep_index]; |
3399 | if ((ep->ep_state & SET_DEQ_PENDING)) { | |
3400 | xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n"); | |
3401 | xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n"); | |
3402 | return 0; | |
3403 | } | |
3404 | ep->queued_deq_seg = deq_seg; | |
3405 | ep->queued_deq_ptr = deq_ptr; | |
8e595a5d | 3406 | return queue_command(xhci, lower_32_bits(addr) | cycle_state, |
e9df17eb | 3407 | upper_32_bits(addr), trb_stream_id, |
913a8a34 | 3408 | trb_slot_id | trb_ep_index | type, false); |
ae636747 | 3409 | } |
a1587d97 SS |
3410 | |
3411 | int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id, | |
3412 | unsigned int ep_index) | |
3413 | { | |
3414 | u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); | |
3415 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); | |
3416 | u32 type = TRB_TYPE(TRB_RESET_EP); | |
3417 | ||
913a8a34 SS |
3418 | return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type, |
3419 | false); | |
a1587d97 | 3420 | } |