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5fd54ace | 1 | // SPDX-License-Identifier: GPL-2.0 |
7f84eef0 SS |
2 | /* |
3 | * xHCI host controller driver | |
4 | * | |
5 | * Copyright (C) 2008 Intel Corp. | |
6 | * | |
7 | * Author: Sarah Sharp | |
8 | * Some code borrowed from the Linux EHCI driver. | |
7f84eef0 SS |
9 | */ |
10 | ||
11 | /* | |
12 | * Ring initialization rules: | |
13 | * 1. Each segment is initialized to zero, except for link TRBs. | |
14 | * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or | |
15 | * Consumer Cycle State (CCS), depending on ring function. | |
16 | * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment. | |
17 | * | |
18 | * Ring behavior rules: | |
19 | * 1. A ring is empty if enqueue == dequeue. This means there will always be at | |
20 | * least one free TRB in the ring. This is useful if you want to turn that | |
21 | * into a link TRB and expand the ring. | |
22 | * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a | |
23 | * link TRB, then load the pointer with the address in the link TRB. If the | |
24 | * link TRB had its toggle bit set, you may need to update the ring cycle | |
25 | * state (see cycle bit rules). You may have to do this multiple times | |
26 | * until you reach a non-link TRB. | |
27 | * 3. A ring is full if enqueue++ (for the definition of increment above) | |
28 | * equals the dequeue pointer. | |
29 | * | |
30 | * Cycle bit rules: | |
31 | * 1. When a consumer increments a dequeue pointer and encounters a toggle bit | |
32 | * in a link TRB, it must toggle the ring cycle state. | |
33 | * 2. When a producer increments an enqueue pointer and encounters a toggle bit | |
34 | * in a link TRB, it must toggle the ring cycle state. | |
35 | * | |
36 | * Producer rules: | |
37 | * 1. Check if ring is full before you enqueue. | |
38 | * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing. | |
39 | * Update enqueue pointer between each write (which may update the ring | |
40 | * cycle state). | |
41 | * 3. Notify consumer. If SW is producer, it rings the doorbell for command | |
42 | * and endpoint rings. If HC is the producer for the event ring, | |
43 | * and it generates an interrupt according to interrupt modulation rules. | |
44 | * | |
45 | * Consumer rules: | |
46 | * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state, | |
47 | * the TRB is owned by the consumer. | |
48 | * 2. Update dequeue pointer (which may update the ring cycle state) and | |
49 | * continue processing TRBs until you reach a TRB which is not owned by you. | |
50 | * 3. Notify the producer. SW is the consumer for the event ring, and it | |
51 | * updates event ring dequeue pointer. HC is the consumer for the command and | |
52 | * endpoint rings; it generates events on the event ring for these. | |
53 | */ | |
54 | ||
8a96c052 | 55 | #include <linux/scatterlist.h> |
5a0e3ad6 | 56 | #include <linux/slab.h> |
f9c589e1 | 57 | #include <linux/dma-mapping.h> |
7f84eef0 | 58 | #include "xhci.h" |
3a7fa5be | 59 | #include "xhci-trace.h" |
7f84eef0 | 60 | |
d1dbfb94 MN |
61 | static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd, |
62 | u32 field1, u32 field2, | |
63 | u32 field3, u32 field4, bool command_must_succeed); | |
64 | ||
7f84eef0 SS |
65 | /* |
66 | * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA | |
67 | * address of the TRB. | |
68 | */ | |
23e3be11 | 69 | dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, |
7f84eef0 SS |
70 | union xhci_trb *trb) |
71 | { | |
6071d836 | 72 | unsigned long segment_offset; |
7f84eef0 | 73 | |
6071d836 | 74 | if (!seg || !trb || trb < seg->trbs) |
7f84eef0 | 75 | return 0; |
6071d836 SS |
76 | /* offset in TRBs */ |
77 | segment_offset = trb - seg->trbs; | |
7895086a | 78 | if (segment_offset >= TRBS_PER_SEGMENT) |
7f84eef0 | 79 | return 0; |
6071d836 | 80 | return seg->dma + (segment_offset * sizeof(*trb)); |
7f84eef0 SS |
81 | } |
82 | ||
0ce57499 MN |
83 | static bool trb_is_noop(union xhci_trb *trb) |
84 | { | |
85 | return TRB_TYPE_NOOP_LE32(trb->generic.field[3]); | |
86 | } | |
87 | ||
2d98ef40 MN |
88 | static bool trb_is_link(union xhci_trb *trb) |
89 | { | |
90 | return TRB_TYPE_LINK_LE32(trb->link.control); | |
91 | } | |
92 | ||
bd5e67f5 MN |
93 | static bool last_trb_on_seg(struct xhci_segment *seg, union xhci_trb *trb) |
94 | { | |
95 | return trb == &seg->trbs[TRBS_PER_SEGMENT - 1]; | |
96 | } | |
97 | ||
98 | static bool last_trb_on_ring(struct xhci_ring *ring, | |
99 | struct xhci_segment *seg, union xhci_trb *trb) | |
100 | { | |
101 | return last_trb_on_seg(seg, trb) && (seg->next == ring->first_seg); | |
102 | } | |
103 | ||
d0c77d84 MN |
104 | static bool link_trb_toggles_cycle(union xhci_trb *trb) |
105 | { | |
106 | return le32_to_cpu(trb->link.control) & LINK_TOGGLE; | |
107 | } | |
108 | ||
2a72126d MN |
109 | static bool last_td_in_urb(struct xhci_td *td) |
110 | { | |
111 | struct urb_priv *urb_priv = td->urb->hcpriv; | |
112 | ||
9ef7fbbb | 113 | return urb_priv->num_tds_done == urb_priv->num_tds; |
2a72126d MN |
114 | } |
115 | ||
116 | static void inc_td_cnt(struct urb *urb) | |
117 | { | |
118 | struct urb_priv *urb_priv = urb->hcpriv; | |
119 | ||
9ef7fbbb | 120 | urb_priv->num_tds_done++; |
2a72126d MN |
121 | } |
122 | ||
ae1e3f07 MN |
123 | static void trb_to_noop(union xhci_trb *trb, u32 noop_type) |
124 | { | |
125 | if (trb_is_link(trb)) { | |
126 | /* unchain chained link TRBs */ | |
127 | trb->link.control &= cpu_to_le32(~TRB_CHAIN); | |
128 | } else { | |
129 | trb->generic.field[0] = 0; | |
130 | trb->generic.field[1] = 0; | |
131 | trb->generic.field[2] = 0; | |
132 | /* Preserve only the cycle bit of this TRB */ | |
133 | trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE); | |
134 | trb->generic.field[3] |= cpu_to_le32(TRB_TYPE(noop_type)); | |
135 | } | |
136 | } | |
137 | ||
ae636747 SS |
138 | /* Updates trb to point to the next TRB in the ring, and updates seg if the next |
139 | * TRB is in a new segment. This does not skip over link TRBs, and it does not | |
140 | * effect the ring dequeue or enqueue pointers. | |
141 | */ | |
142 | static void next_trb(struct xhci_hcd *xhci, | |
143 | struct xhci_ring *ring, | |
144 | struct xhci_segment **seg, | |
145 | union xhci_trb **trb) | |
146 | { | |
2d98ef40 | 147 | if (trb_is_link(*trb)) { |
ae636747 SS |
148 | *seg = (*seg)->next; |
149 | *trb = ((*seg)->trbs); | |
150 | } else { | |
a1669b2c | 151 | (*trb)++; |
ae636747 SS |
152 | } |
153 | } | |
154 | ||
7f84eef0 SS |
155 | /* |
156 | * See Cycle bit rules. SW is the consumer for the event ring only. | |
7f84eef0 | 157 | */ |
67d2ea9f | 158 | void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring) |
7f84eef0 | 159 | { |
c716e8a5 MN |
160 | unsigned int link_trb_count = 0; |
161 | ||
bd5e67f5 MN |
162 | /* event ring doesn't have link trbs, check for last trb */ |
163 | if (ring->type == TYPE_EVENT) { | |
164 | if (!last_trb_on_seg(ring->deq_seg, ring->dequeue)) { | |
50d0206f | 165 | ring->dequeue++; |
49d5b05e | 166 | goto out; |
7f84eef0 | 167 | } |
bd5e67f5 MN |
168 | if (last_trb_on_ring(ring, ring->deq_seg, ring->dequeue)) |
169 | ring->cycle_state ^= 1; | |
170 | ring->deq_seg = ring->deq_seg->next; | |
171 | ring->dequeue = ring->deq_seg->trbs; | |
49d5b05e | 172 | goto out; |
bd5e67f5 MN |
173 | } |
174 | ||
175 | /* All other rings have link trbs */ | |
176 | if (!trb_is_link(ring->dequeue)) { | |
c716e8a5 MN |
177 | if (last_trb_on_seg(ring->deq_seg, ring->dequeue)) { |
178 | xhci_warn(xhci, "Missing link TRB at end of segment\n"); | |
179 | } else { | |
180 | ring->dequeue++; | |
181 | ring->num_trbs_free++; | |
182 | } | |
bd5e67f5 | 183 | } |
c716e8a5 | 184 | |
bd5e67f5 MN |
185 | while (trb_is_link(ring->dequeue)) { |
186 | ring->deq_seg = ring->deq_seg->next; | |
187 | ring->dequeue = ring->deq_seg->trbs; | |
b2d6edbb | 188 | |
c716e8a5 MN |
189 | if (link_trb_count++ > ring->num_segs) { |
190 | xhci_warn(xhci, "Ring is an endless link TRB loop\n"); | |
191 | break; | |
192 | } | |
193 | } | |
49d5b05e | 194 | out: |
b2d6edbb LB |
195 | trace_xhci_inc_deq(ring); |
196 | ||
bd5e67f5 | 197 | return; |
7f84eef0 SS |
198 | } |
199 | ||
200 | /* | |
201 | * See Cycle bit rules. SW is the consumer for the event ring only. | |
7f84eef0 SS |
202 | * |
203 | * If we've just enqueued a TRB that is in the middle of a TD (meaning the | |
204 | * chain bit is set), then set the chain bit in all the following link TRBs. | |
205 | * If we've enqueued the last TRB in a TD, make sure the following link TRBs | |
206 | * have their chain bit cleared (so that each Link TRB is a separate TD). | |
207 | * | |
208 | * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit | |
b0567b3f SS |
209 | * set, but other sections talk about dealing with the chain bit set. This was |
210 | * fixed in the 0.96 specification errata, but we have to assume that all 0.95 | |
211 | * xHCI hardware can't handle the chain bit being cleared on a link TRB. | |
6cc30d85 SS |
212 | * |
213 | * @more_trbs_coming: Will you enqueue more TRBs before calling | |
214 | * prepare_transfer()? | |
7f84eef0 | 215 | */ |
6cc30d85 | 216 | static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring, |
3b72fca0 | 217 | bool more_trbs_coming) |
7f84eef0 SS |
218 | { |
219 | u32 chain; | |
220 | union xhci_trb *next; | |
c716e8a5 | 221 | unsigned int link_trb_count = 0; |
7f84eef0 | 222 | |
28ccd296 | 223 | chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN; |
b008df60 | 224 | /* If this is not event ring, there is one less usable TRB */ |
2d98ef40 | 225 | if (!trb_is_link(ring->enqueue)) |
b008df60 | 226 | ring->num_trbs_free--; |
c716e8a5 MN |
227 | |
228 | if (last_trb_on_seg(ring->enq_seg, ring->enqueue)) { | |
229 | xhci_err(xhci, "Tried to move enqueue past ring segment\n"); | |
230 | return; | |
231 | } | |
232 | ||
7f84eef0 SS |
233 | next = ++(ring->enqueue); |
234 | ||
2251198b | 235 | /* Update the dequeue pointer further if that was a link TRB */ |
2d98ef40 | 236 | while (trb_is_link(next)) { |
6cc30d85 | 237 | |
2251198b MN |
238 | /* |
239 | * If the caller doesn't plan on enqueueing more TDs before | |
240 | * ringing the doorbell, then we don't want to give the link TRB | |
241 | * to the hardware just yet. We'll give the link TRB back in | |
242 | * prepare_ring() just before we enqueue the TD at the top of | |
243 | * the ring. | |
244 | */ | |
245 | if (!chain && !more_trbs_coming) | |
246 | break; | |
3b72fca0 | 247 | |
2251198b MN |
248 | /* If we're not dealing with 0.95 hardware or isoc rings on |
249 | * AMD 0.96 host, carry over the chain bit of the previous TRB | |
250 | * (which may mean the chain bit is cleared). | |
251 | */ | |
252 | if (!(ring->type == TYPE_ISOC && | |
253 | (xhci->quirks & XHCI_AMD_0x96_HOST)) && | |
254 | !xhci_link_trb_quirk(xhci)) { | |
255 | next->link.control &= cpu_to_le32(~TRB_CHAIN); | |
256 | next->link.control |= cpu_to_le32(chain); | |
7f84eef0 | 257 | } |
2251198b MN |
258 | /* Give this link TRB to the hardware */ |
259 | wmb(); | |
260 | next->link.control ^= cpu_to_le32(TRB_CYCLE); | |
261 | ||
262 | /* Toggle the cycle bit after the last ring segment. */ | |
d0c77d84 | 263 | if (link_trb_toggles_cycle(next)) |
2251198b MN |
264 | ring->cycle_state ^= 1; |
265 | ||
7f84eef0 SS |
266 | ring->enq_seg = ring->enq_seg->next; |
267 | ring->enqueue = ring->enq_seg->trbs; | |
268 | next = ring->enqueue; | |
c716e8a5 MN |
269 | |
270 | if (link_trb_count++ > ring->num_segs) { | |
271 | xhci_warn(xhci, "%s: Ring link TRB loop\n", __func__); | |
272 | break; | |
273 | } | |
7f84eef0 | 274 | } |
b2d6edbb LB |
275 | |
276 | trace_xhci_inc_enq(ring); | |
7f84eef0 SS |
277 | } |
278 | ||
279 | /* | |
085deb16 AX |
280 | * Check to see if there's room to enqueue num_trbs on the ring and make sure |
281 | * enqueue pointer will not advance into dequeue segment. See rules above. | |
7f84eef0 | 282 | */ |
b008df60 | 283 | static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring, |
7f84eef0 SS |
284 | unsigned int num_trbs) |
285 | { | |
085deb16 | 286 | int num_trbs_in_deq_seg; |
b008df60 | 287 | |
085deb16 AX |
288 | if (ring->num_trbs_free < num_trbs) |
289 | return 0; | |
290 | ||
291 | if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) { | |
292 | num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs; | |
293 | if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg) | |
294 | return 0; | |
295 | } | |
296 | ||
297 | return 1; | |
7f84eef0 SS |
298 | } |
299 | ||
7f84eef0 | 300 | /* Ring the host controller doorbell after placing a command on the ring */ |
23e3be11 | 301 | void xhci_ring_cmd_db(struct xhci_hcd *xhci) |
7f84eef0 | 302 | { |
c181bc5b EF |
303 | if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING)) |
304 | return; | |
305 | ||
7f84eef0 | 306 | xhci_dbg(xhci, "// Ding dong!\n"); |
58b9d71a MN |
307 | |
308 | trace_xhci_ring_host_doorbell(0, DB_VALUE_HOST); | |
309 | ||
204b7793 | 310 | writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]); |
7f84eef0 | 311 | /* Flush PCI posted writes */ |
b0ba9720 | 312 | readl(&xhci->dba->doorbell[0]); |
7f84eef0 SS |
313 | } |
314 | ||
cb4d5ce5 OH |
315 | static bool xhci_mod_cmd_timer(struct xhci_hcd *xhci, unsigned long delay) |
316 | { | |
317 | return mod_delayed_work(system_wq, &xhci->cmd_timer, delay); | |
318 | } | |
319 | ||
1c111b6c OH |
320 | static struct xhci_command *xhci_next_queued_cmd(struct xhci_hcd *xhci) |
321 | { | |
322 | return list_first_entry_or_null(&xhci->cmd_list, struct xhci_command, | |
323 | cmd_list); | |
324 | } | |
325 | ||
326 | /* | |
327 | * Turn all commands on command ring with status set to "aborted" to no-op trbs. | |
328 | * If there are other commands waiting then restart the ring and kick the timer. | |
329 | * This must be called with command ring stopped and xhci->lock held. | |
330 | */ | |
331 | static void xhci_handle_stopped_cmd_ring(struct xhci_hcd *xhci, | |
332 | struct xhci_command *cur_cmd) | |
333 | { | |
334 | struct xhci_command *i_cmd; | |
1c111b6c OH |
335 | |
336 | /* Turn all aborted commands in list to no-ops, then restart */ | |
337 | list_for_each_entry(i_cmd, &xhci->cmd_list, cmd_list) { | |
338 | ||
0b7c105a | 339 | if (i_cmd->status != COMP_COMMAND_ABORTED) |
1c111b6c OH |
340 | continue; |
341 | ||
604d02a2 | 342 | i_cmd->status = COMP_COMMAND_RING_STOPPED; |
1c111b6c OH |
343 | |
344 | xhci_dbg(xhci, "Turn aborted command %p to no-op\n", | |
345 | i_cmd->command_trb); | |
5278204c MN |
346 | |
347 | trb_to_noop(i_cmd->command_trb, TRB_CMD_NOOP); | |
1c111b6c OH |
348 | |
349 | /* | |
350 | * caller waiting for completion is called when command | |
351 | * completion event is received for these no-op commands | |
352 | */ | |
353 | } | |
354 | ||
355 | xhci->cmd_ring_state = CMD_RING_STATE_RUNNING; | |
356 | ||
357 | /* ring command ring doorbell to restart the command ring */ | |
358 | if ((xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue) && | |
359 | !(xhci->xhc_state & XHCI_STATE_DYING)) { | |
360 | xhci->current_cmd = cur_cmd; | |
361 | xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT); | |
362 | xhci_ring_cmd_db(xhci); | |
363 | } | |
364 | } | |
365 | ||
366 | /* Must be called with xhci->lock held, releases and aquires lock back */ | |
367 | static int xhci_abort_cmd_ring(struct xhci_hcd *xhci, unsigned long flags) | |
b92cc66c | 368 | { |
ff0e50d3 | 369 | u32 temp_32; |
b92cc66c EF |
370 | int ret; |
371 | ||
372 | xhci_dbg(xhci, "Abort command ring\n"); | |
373 | ||
1c111b6c | 374 | reinit_completion(&xhci->cmd_ring_stop_completion); |
3425aa03 | 375 | |
ff0e50d3 PK |
376 | /* |
377 | * The control bits like command stop, abort are located in lower | |
378 | * dword of the command ring control register. Limit the write | |
379 | * to the lower dword to avoid corrupting the command ring pointer | |
380 | * in case if the command ring is stopped by the time upper dword | |
381 | * is written. | |
382 | */ | |
383 | temp_32 = readl(&xhci->op_regs->cmd_ring); | |
384 | writel(temp_32 | CMD_RING_ABORT, &xhci->op_regs->cmd_ring); | |
b92cc66c | 385 | |
d9f11ba9 MN |
386 | /* Section 4.6.1.2 of xHCI 1.0 spec says software should also time the |
387 | * completion of the Command Abort operation. If CRR is not negated in 5 | |
388 | * seconds then driver handles it as if host died (-ENODEV). | |
389 | * In the future we should distinguish between -ENODEV and -ETIMEDOUT | |
390 | * and try to recover a -ETIMEDOUT with a host controller reset. | |
b92cc66c | 391 | */ |
dc0b177c | 392 | ret = xhci_handshake(&xhci->op_regs->cmd_ring, |
b92cc66c EF |
393 | CMD_RING_RUNNING, 0, 5 * 1000 * 1000); |
394 | if (ret < 0) { | |
d9f11ba9 | 395 | xhci_err(xhci, "Abort failed to stop command ring: %d\n", ret); |
1cc6d861 | 396 | xhci_halt(xhci); |
d9f11ba9 MN |
397 | xhci_hc_died(xhci); |
398 | return ret; | |
1c111b6c OH |
399 | } |
400 | /* | |
401 | * Writing the CMD_RING_ABORT bit should cause a cmd completion event, | |
402 | * however on some host hw the CMD_RING_RUNNING bit is correctly cleared | |
403 | * but the completion event in never sent. Wait 2 secs (arbitrary | |
404 | * number) to handle those cases after negation of CMD_RING_RUNNING. | |
405 | */ | |
406 | spin_unlock_irqrestore(&xhci->lock, flags); | |
407 | ret = wait_for_completion_timeout(&xhci->cmd_ring_stop_completion, | |
408 | msecs_to_jiffies(2000)); | |
409 | spin_lock_irqsave(&xhci->lock, flags); | |
410 | if (!ret) { | |
411 | xhci_dbg(xhci, "No stop event for abort, ring start fail?\n"); | |
412 | xhci_cleanup_command_queue(xhci); | |
413 | } else { | |
414 | xhci_handle_stopped_cmd_ring(xhci, xhci_next_queued_cmd(xhci)); | |
b92cc66c | 415 | } |
b92cc66c EF |
416 | return 0; |
417 | } | |
418 | ||
be88fe4f | 419 | void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, |
ae636747 | 420 | unsigned int slot_id, |
e9df17eb SS |
421 | unsigned int ep_index, |
422 | unsigned int stream_id) | |
ae636747 | 423 | { |
28ccd296 | 424 | __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id]; |
50d64676 MW |
425 | struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index]; |
426 | unsigned int ep_state = ep->ep_state; | |
ae636747 | 427 | |
ae636747 | 428 | /* Don't ring the doorbell for this endpoint if there are pending |
50d64676 | 429 | * cancellations because we don't want to interrupt processing. |
8df75f42 SS |
430 | * We don't want to restart any stream rings if there's a set dequeue |
431 | * pointer command pending because the device can choose to start any | |
432 | * stream once the endpoint is on the HW schedule. | |
ae636747 | 433 | */ |
9983a5fc | 434 | if ((ep_state & EP_STOP_CMD_PENDING) || (ep_state & SET_DEQ_PENDING) || |
ef513be0 | 435 | (ep_state & EP_HALTED) || (ep_state & EP_CLEARING_TT)) |
50d64676 | 436 | return; |
58b9d71a MN |
437 | |
438 | trace_xhci_ring_ep_doorbell(slot_id, DB_VALUE(ep_index, stream_id)); | |
439 | ||
204b7793 | 440 | writel(DB_VALUE(ep_index, stream_id), db_addr); |
b05dadb2 MN |
441 | /* flush the write */ |
442 | readl(db_addr); | |
ae636747 SS |
443 | } |
444 | ||
e9df17eb SS |
445 | /* Ring the doorbell for any rings with pending URBs */ |
446 | static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci, | |
447 | unsigned int slot_id, | |
448 | unsigned int ep_index) | |
449 | { | |
450 | unsigned int stream_id; | |
451 | struct xhci_virt_ep *ep; | |
452 | ||
453 | ep = &xhci->devs[slot_id]->eps[ep_index]; | |
454 | ||
455 | /* A ring has pending URBs if its TD list is not empty */ | |
456 | if (!(ep->ep_state & EP_HAS_STREAMS)) { | |
d66eaf9f | 457 | if (ep->ring && !(list_empty(&ep->ring->td_list))) |
be88fe4f | 458 | xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0); |
e9df17eb SS |
459 | return; |
460 | } | |
461 | ||
462 | for (stream_id = 1; stream_id < ep->stream_info->num_streams; | |
463 | stream_id++) { | |
464 | struct xhci_stream_info *stream_info = ep->stream_info; | |
465 | if (!list_empty(&stream_info->stream_rings[stream_id]->td_list)) | |
be88fe4f AX |
466 | xhci_ring_ep_doorbell(xhci, slot_id, ep_index, |
467 | stream_id); | |
e9df17eb SS |
468 | } |
469 | } | |
470 | ||
ef513be0 JL |
471 | void xhci_ring_doorbell_for_active_rings(struct xhci_hcd *xhci, |
472 | unsigned int slot_id, | |
473 | unsigned int ep_index) | |
474 | { | |
475 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); | |
476 | } | |
477 | ||
b1adc42d MN |
478 | static struct xhci_virt_ep *xhci_get_virt_ep(struct xhci_hcd *xhci, |
479 | unsigned int slot_id, | |
480 | unsigned int ep_index) | |
481 | { | |
482 | if (slot_id == 0 || slot_id >= MAX_HC_SLOTS) { | |
483 | xhci_warn(xhci, "Invalid slot_id %u\n", slot_id); | |
484 | return NULL; | |
485 | } | |
486 | if (ep_index >= EP_CTX_PER_DEV) { | |
487 | xhci_warn(xhci, "Invalid endpoint index %u\n", ep_index); | |
488 | return NULL; | |
489 | } | |
490 | if (!xhci->devs[slot_id]) { | |
491 | xhci_warn(xhci, "No xhci virt device for slot_id %u\n", slot_id); | |
492 | return NULL; | |
493 | } | |
494 | ||
495 | return &xhci->devs[slot_id]->eps[ep_index]; | |
496 | } | |
497 | ||
42f2890a MN |
498 | static struct xhci_ring *xhci_virt_ep_to_ring(struct xhci_hcd *xhci, |
499 | struct xhci_virt_ep *ep, | |
500 | unsigned int stream_id) | |
501 | { | |
502 | /* common case, no streams */ | |
503 | if (!(ep->ep_state & EP_HAS_STREAMS)) | |
504 | return ep->ring; | |
505 | ||
506 | if (!ep->stream_info) | |
507 | return NULL; | |
508 | ||
509 | if (stream_id == 0 || stream_id >= ep->stream_info->num_streams) { | |
510 | xhci_warn(xhci, "Invalid stream_id %u request for slot_id %u ep_index %u\n", | |
511 | stream_id, ep->vdev->slot_id, ep->ep_index); | |
512 | return NULL; | |
513 | } | |
514 | ||
515 | return ep->stream_info->stream_rings[stream_id]; | |
516 | } | |
517 | ||
75b040ec AI |
518 | /* Get the right ring for the given slot_id, ep_index and stream_id. |
519 | * If the endpoint supports streams, boundary check the URB's stream ID. | |
520 | * If the endpoint doesn't support streams, return the singular endpoint ring. | |
521 | */ | |
522 | struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci, | |
021bff91 SS |
523 | unsigned int slot_id, unsigned int ep_index, |
524 | unsigned int stream_id) | |
525 | { | |
526 | struct xhci_virt_ep *ep; | |
527 | ||
b1adc42d MN |
528 | ep = xhci_get_virt_ep(xhci, slot_id, ep_index); |
529 | if (!ep) | |
530 | return NULL; | |
531 | ||
42f2890a | 532 | return xhci_virt_ep_to_ring(xhci, ep, stream_id); |
021bff91 SS |
533 | } |
534 | ||
e6b20121 MN |
535 | |
536 | /* | |
537 | * Get the hw dequeue pointer xHC stopped on, either directly from the | |
538 | * endpoint context, or if streams are in use from the stream context. | |
539 | * The returned hw_dequeue contains the lowest four bits with cycle state | |
540 | * and possbile stream context type. | |
541 | */ | |
542 | static u64 xhci_get_hw_deq(struct xhci_hcd *xhci, struct xhci_virt_device *vdev, | |
543 | unsigned int ep_index, unsigned int stream_id) | |
544 | { | |
545 | struct xhci_ep_ctx *ep_ctx; | |
546 | struct xhci_stream_ctx *st_ctx; | |
547 | struct xhci_virt_ep *ep; | |
548 | ||
549 | ep = &vdev->eps[ep_index]; | |
550 | ||
551 | if (ep->ep_state & EP_HAS_STREAMS) { | |
552 | st_ctx = &ep->stream_info->stream_ctx_array[stream_id]; | |
553 | return le64_to_cpu(st_ctx->stream_ring); | |
554 | } | |
555 | ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index); | |
556 | return le64_to_cpu(ep_ctx->deq); | |
557 | } | |
558 | ||
d1dbfb94 MN |
559 | static int xhci_move_dequeue_past_td(struct xhci_hcd *xhci, |
560 | unsigned int slot_id, unsigned int ep_index, | |
561 | unsigned int stream_id, struct xhci_td *td) | |
562 | { | |
563 | struct xhci_virt_device *dev = xhci->devs[slot_id]; | |
564 | struct xhci_virt_ep *ep = &dev->eps[ep_index]; | |
565 | struct xhci_ring *ep_ring; | |
566 | struct xhci_command *cmd; | |
567 | struct xhci_segment *new_seg; | |
5255660b | 568 | struct xhci_segment *halted_seg = NULL; |
d1dbfb94 MN |
569 | union xhci_trb *new_deq; |
570 | int new_cycle; | |
5255660b JB |
571 | union xhci_trb *halted_trb; |
572 | int index = 0; | |
d1dbfb94 MN |
573 | dma_addr_t addr; |
574 | u64 hw_dequeue; | |
575 | bool cycle_found = false; | |
576 | bool td_last_trb_found = false; | |
577 | u32 trb_sct = 0; | |
578 | int ret; | |
579 | ||
580 | ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id, | |
581 | ep_index, stream_id); | |
582 | if (!ep_ring) { | |
583 | xhci_warn(xhci, "WARN can't find new dequeue, invalid stream ID %u\n", | |
584 | stream_id); | |
585 | return -ENODEV; | |
586 | } | |
587 | /* | |
588 | * A cancelled TD can complete with a stall if HW cached the trb. | |
589 | * In this case driver can't find td, but if the ring is empty we | |
590 | * can move the dequeue pointer to the current enqueue position. | |
591 | * We shouldn't hit this anymore as cached cancelled TRBs are given back | |
592 | * after clearing the cache, but be on the safe side and keep it anyway | |
593 | */ | |
594 | if (!td) { | |
595 | if (list_empty(&ep_ring->td_list)) { | |
596 | new_seg = ep_ring->enq_seg; | |
597 | new_deq = ep_ring->enqueue; | |
598 | new_cycle = ep_ring->cycle_state; | |
599 | xhci_dbg(xhci, "ep ring empty, Set new dequeue = enqueue"); | |
600 | goto deq_found; | |
601 | } else { | |
602 | xhci_warn(xhci, "Can't find new dequeue state, missing td\n"); | |
603 | return -EINVAL; | |
604 | } | |
605 | } | |
606 | ||
607 | hw_dequeue = xhci_get_hw_deq(xhci, dev, ep_index, stream_id); | |
608 | new_seg = ep_ring->deq_seg; | |
609 | new_deq = ep_ring->dequeue; | |
5255660b JB |
610 | |
611 | /* | |
612 | * Quirk: xHC write-back of the DCS field in the hardware dequeue | |
613 | * pointer is wrong - use the cycle state of the TRB pointed to by | |
614 | * the dequeue pointer. | |
615 | */ | |
616 | if (xhci->quirks & XHCI_EP_CTX_BROKEN_DCS && | |
617 | !(ep->ep_state & EP_HAS_STREAMS)) | |
618 | halted_seg = trb_in_td(xhci, td->start_seg, | |
619 | td->first_trb, td->last_trb, | |
620 | hw_dequeue & ~0xf, false); | |
621 | if (halted_seg) { | |
622 | index = ((dma_addr_t)(hw_dequeue & ~0xf) - halted_seg->dma) / | |
623 | sizeof(*halted_trb); | |
624 | halted_trb = &halted_seg->trbs[index]; | |
625 | new_cycle = halted_trb->generic.field[3] & 0x1; | |
626 | xhci_dbg(xhci, "Endpoint DCS = %d TRB index = %d cycle = %d\n", | |
627 | (u8)(hw_dequeue & 0x1), index, new_cycle); | |
628 | } else { | |
629 | new_cycle = hw_dequeue & 0x1; | |
630 | } | |
d1dbfb94 MN |
631 | |
632 | /* | |
633 | * We want to find the pointer, segment and cycle state of the new trb | |
634 | * (the one after current TD's last_trb). We know the cycle state at | |
635 | * hw_dequeue, so walk the ring until both hw_dequeue and last_trb are | |
636 | * found. | |
637 | */ | |
638 | do { | |
639 | if (!cycle_found && xhci_trb_virt_to_dma(new_seg, new_deq) | |
640 | == (dma_addr_t)(hw_dequeue & ~0xf)) { | |
641 | cycle_found = true; | |
642 | if (td_last_trb_found) | |
643 | break; | |
644 | } | |
645 | if (new_deq == td->last_trb) | |
646 | td_last_trb_found = true; | |
647 | ||
648 | if (cycle_found && trb_is_link(new_deq) && | |
649 | link_trb_toggles_cycle(new_deq)) | |
650 | new_cycle ^= 0x1; | |
651 | ||
652 | next_trb(xhci, ep_ring, &new_seg, &new_deq); | |
653 | ||
654 | /* Search wrapped around, bail out */ | |
655 | if (new_deq == ep->ring->dequeue) { | |
656 | xhci_err(xhci, "Error: Failed finding new dequeue state\n"); | |
657 | return -EINVAL; | |
658 | } | |
659 | ||
660 | } while (!cycle_found || !td_last_trb_found); | |
661 | ||
662 | deq_found: | |
663 | ||
664 | /* Don't update the ring cycle state for the producer (us). */ | |
665 | addr = xhci_trb_virt_to_dma(new_seg, new_deq); | |
666 | if (addr == 0) { | |
667 | xhci_warn(xhci, "Can't find dma of new dequeue ptr\n"); | |
668 | xhci_warn(xhci, "deq seg = %p, deq ptr = %p\n", new_seg, new_deq); | |
669 | return -EINVAL; | |
670 | } | |
671 | ||
672 | if ((ep->ep_state & SET_DEQ_PENDING)) { | |
673 | xhci_warn(xhci, "Set TR Deq already pending, don't submit for 0x%pad\n", | |
674 | &addr); | |
675 | return -EBUSY; | |
676 | } | |
677 | ||
678 | /* This function gets called from contexts where it cannot sleep */ | |
679 | cmd = xhci_alloc_command(xhci, false, GFP_ATOMIC); | |
680 | if (!cmd) { | |
681 | xhci_warn(xhci, "Can't alloc Set TR Deq cmd 0x%pad\n", &addr); | |
682 | return -ENOMEM; | |
683 | } | |
684 | ||
685 | if (stream_id) | |
686 | trb_sct = SCT_FOR_TRB(SCT_PRI_TR); | |
687 | ret = queue_command(xhci, cmd, | |
688 | lower_32_bits(addr) | trb_sct | new_cycle, | |
689 | upper_32_bits(addr), | |
690 | STREAM_ID_FOR_TRB(stream_id), SLOT_ID_FOR_TRB(slot_id) | | |
691 | EP_ID_FOR_TRB(ep_index) | TRB_TYPE(TRB_SET_DEQ), false); | |
692 | if (ret < 0) { | |
693 | xhci_free_command(xhci, cmd); | |
694 | return ret; | |
695 | } | |
696 | ep->queued_deq_seg = new_seg; | |
697 | ep->queued_deq_ptr = new_deq; | |
698 | ||
699 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, | |
700 | "Set TR Deq ptr 0x%llx, cycle %u\n", addr, new_cycle); | |
701 | ||
702 | /* Stop the TD queueing code from ringing the doorbell until | |
703 | * this command completes. The HC won't set the dequeue pointer | |
704 | * if the ring is running, and ringing the doorbell starts the | |
705 | * ring running. | |
706 | */ | |
707 | ep->ep_state |= SET_DEQ_PENDING; | |
708 | xhci_ring_cmd_db(xhci); | |
709 | return 0; | |
710 | } | |
711 | ||
522989a2 SS |
712 | /* flip_cycle means flip the cycle bit of all but the first and last TRB. |
713 | * (The last TRB actually points to the ring enqueue pointer, which is not part | |
714 | * of this TD.) This is used to remove partially enqueued isoc TDs from a ring. | |
715 | */ | |
23e3be11 | 716 | static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring, |
0d58a1a0 | 717 | struct xhci_td *td, bool flip_cycle) |
ae636747 | 718 | { |
0d58a1a0 MN |
719 | struct xhci_segment *seg = td->start_seg; |
720 | union xhci_trb *trb = td->first_trb; | |
721 | ||
722 | while (1) { | |
ae1e3f07 MN |
723 | trb_to_noop(trb, TRB_TR_NOOP); |
724 | ||
0d58a1a0 MN |
725 | /* flip cycle if asked to */ |
726 | if (flip_cycle && trb != td->first_trb && trb != td->last_trb) | |
727 | trb->generic.field[3] ^= cpu_to_le32(TRB_CYCLE); | |
728 | ||
729 | if (trb == td->last_trb) | |
ae636747 | 730 | break; |
0d58a1a0 MN |
731 | |
732 | next_trb(xhci, ep_ring, &seg, &trb); | |
ae636747 SS |
733 | } |
734 | } | |
735 | ||
575688e1 | 736 | static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci, |
6f5165cf SS |
737 | struct xhci_virt_ep *ep) |
738 | { | |
9983a5fc | 739 | ep->ep_state &= ~EP_STOP_CMD_PENDING; |
f9926596 MN |
740 | /* Can't del_timer_sync in interrupt */ |
741 | del_timer(&ep->stop_cmd_timer); | |
6f5165cf SS |
742 | } |
743 | ||
2a72126d MN |
744 | /* |
745 | * Must be called with xhci->lock held in interrupt context, | |
746 | * releases and re-acquires xhci->lock | |
747 | */ | |
6f5165cf | 748 | static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci, |
2a72126d | 749 | struct xhci_td *cur_td, int status) |
6f5165cf | 750 | { |
2a72126d MN |
751 | struct urb *urb = cur_td->urb; |
752 | struct urb_priv *urb_priv = urb->hcpriv; | |
753 | struct usb_hcd *hcd = bus_to_hcd(urb->dev->bus); | |
754 | ||
755 | if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { | |
756 | xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--; | |
757 | if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) { | |
758 | if (xhci->quirks & XHCI_AMD_PLL_FIX) | |
759 | usb_amd_quirk_pll_enable(); | |
c41136b0 | 760 | } |
8e51adcc | 761 | } |
446b3141 | 762 | xhci_urb_free_priv(urb_priv); |
2a72126d | 763 | usb_hcd_unlink_urb_from_ep(hcd, urb); |
5abdc2e6 | 764 | trace_xhci_urb_giveback(urb); |
7bc5d5af | 765 | usb_hcd_giveback_urb(hcd, urb, status); |
446b3141 MN |
766 | } |
767 | ||
2d6d5769 WY |
768 | static void xhci_unmap_td_bounce_buffer(struct xhci_hcd *xhci, |
769 | struct xhci_ring *ring, struct xhci_td *td) | |
f9c589e1 MN |
770 | { |
771 | struct device *dev = xhci_to_hcd(xhci)->self.controller; | |
772 | struct xhci_segment *seg = td->bounce_seg; | |
773 | struct urb *urb = td->urb; | |
597c56e3 | 774 | size_t len; |
f9c589e1 | 775 | |
f45e2a02 | 776 | if (!ring || !seg || !urb) |
f9c589e1 MN |
777 | return; |
778 | ||
779 | if (usb_urb_dir_out(urb)) { | |
780 | dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len, | |
781 | DMA_TO_DEVICE); | |
782 | return; | |
783 | } | |
784 | ||
f9c589e1 MN |
785 | dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len, |
786 | DMA_FROM_DEVICE); | |
597c56e3 | 787 | /* for in tranfers we need to copy the data from bounce to sg */ |
d4a61063 MN |
788 | if (urb->num_sgs) { |
789 | len = sg_pcopy_from_buffer(urb->sg, urb->num_sgs, seg->bounce_buf, | |
790 | seg->bounce_len, seg->bounce_offs); | |
791 | if (len != seg->bounce_len) | |
792 | xhci_warn(xhci, "WARN Wrong bounce buffer read length: %zu != %d\n", | |
793 | len, seg->bounce_len); | |
794 | } else { | |
795 | memcpy(urb->transfer_buffer + seg->bounce_offs, seg->bounce_buf, | |
796 | seg->bounce_len); | |
797 | } | |
f9c589e1 MN |
798 | seg->bounce_len = 0; |
799 | seg->bounce_offs = 0; | |
800 | } | |
801 | ||
69eaf9e7 | 802 | static int xhci_td_cleanup(struct xhci_hcd *xhci, struct xhci_td *td, |
a6ccd1fd | 803 | struct xhci_ring *ep_ring, int status) |
69eaf9e7 MN |
804 | { |
805 | struct urb *urb = NULL; | |
806 | ||
807 | /* Clean up the endpoint's TD list */ | |
808 | urb = td->urb; | |
809 | ||
810 | /* if a bounce buffer was used to align this td then unmap it */ | |
811 | xhci_unmap_td_bounce_buffer(xhci, ep_ring, td); | |
812 | ||
813 | /* Do one last check of the actual transfer length. | |
814 | * If the host controller said we transferred more data than the buffer | |
815 | * length, urb->actual_length will be a very big number (since it's | |
816 | * unsigned). Play it safe and say we didn't transfer anything. | |
817 | */ | |
818 | if (urb->actual_length > urb->transfer_buffer_length) { | |
819 | xhci_warn(xhci, "URB req %u and actual %u transfer length mismatch\n", | |
820 | urb->transfer_buffer_length, urb->actual_length); | |
821 | urb->actual_length = 0; | |
a6ccd1fd | 822 | status = 0; |
69eaf9e7 | 823 | } |
e1a29839 MN |
824 | /* TD might be removed from td_list if we are giving back a cancelled URB */ |
825 | if (!list_empty(&td->td_list)) | |
826 | list_del_init(&td->td_list); | |
827 | /* Giving back a cancelled URB, or if a slated TD completed anyway */ | |
69eaf9e7 MN |
828 | if (!list_empty(&td->cancelled_td_list)) |
829 | list_del_init(&td->cancelled_td_list); | |
830 | ||
831 | inc_td_cnt(urb); | |
832 | /* Giveback the urb when all the tds are completed */ | |
833 | if (last_td_in_urb(td)) { | |
834 | if ((urb->actual_length != urb->transfer_buffer_length && | |
835 | (urb->transfer_flags & URB_SHORT_NOT_OK)) || | |
a6ccd1fd | 836 | (status != 0 && !usb_endpoint_xfer_isoc(&urb->ep->desc))) |
69eaf9e7 MN |
837 | xhci_dbg(xhci, "Giveback URB %p, len = %d, expected = %d, status = %d\n", |
838 | urb, urb->actual_length, | |
a6ccd1fd | 839 | urb->transfer_buffer_length, status); |
69eaf9e7 MN |
840 | |
841 | /* set isoc urb status to 0 just as EHCI, UHCI, and OHCI */ | |
842 | if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) | |
a6ccd1fd MN |
843 | status = 0; |
844 | xhci_giveback_urb_in_irq(xhci, td, status); | |
69eaf9e7 MN |
845 | } |
846 | ||
847 | return 0; | |
848 | } | |
849 | ||
674f8438 MN |
850 | |
851 | /* Complete the cancelled URBs we unlinked from td_list. */ | |
852 | static void xhci_giveback_invalidated_tds(struct xhci_virt_ep *ep) | |
853 | { | |
854 | struct xhci_ring *ring; | |
855 | struct xhci_td *td, *tmp_td; | |
856 | ||
857 | list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list, | |
858 | cancelled_td_list) { | |
859 | ||
674f8438 MN |
860 | ring = xhci_urb_to_transfer_ring(ep->xhci, td->urb); |
861 | ||
0d9b9f53 MN |
862 | if (td->cancel_status == TD_CLEARED) { |
863 | xhci_dbg(ep->xhci, "%s: Giveback cancelled URB %p TD\n", | |
864 | __func__, td->urb); | |
a80c203c | 865 | xhci_td_cleanup(ep->xhci, td, ring, td->status); |
0d9b9f53 MN |
866 | } else { |
867 | xhci_dbg(ep->xhci, "%s: Keep cancelled URB %p TD as cancel_status is %d\n", | |
868 | __func__, td->urb, td->cancel_status); | |
869 | } | |
674f8438 MN |
870 | if (ep->xhci->xhc_state & XHCI_STATE_DYING) |
871 | return; | |
872 | } | |
873 | } | |
874 | ||
d8ac9500 MN |
875 | static int xhci_reset_halted_ep(struct xhci_hcd *xhci, unsigned int slot_id, |
876 | unsigned int ep_index, enum xhci_ep_reset_type reset_type) | |
877 | { | |
878 | struct xhci_command *command; | |
879 | int ret = 0; | |
880 | ||
881 | command = xhci_alloc_command(xhci, false, GFP_ATOMIC); | |
882 | if (!command) { | |
883 | ret = -ENOMEM; | |
884 | goto done; | |
885 | } | |
886 | ||
0d9b9f53 MN |
887 | xhci_dbg(xhci, "%s-reset ep %u, slot %u\n", |
888 | (reset_type == EP_HARD_RESET) ? "Hard" : "Soft", | |
889 | ep_index, slot_id); | |
890 | ||
d8ac9500 MN |
891 | ret = xhci_queue_reset_ep(xhci, command, slot_id, ep_index, reset_type); |
892 | done: | |
893 | if (ret) | |
894 | xhci_err(xhci, "ERROR queuing reset endpoint for slot %d ep_index %d, %d\n", | |
895 | slot_id, ep_index, ret); | |
896 | return ret; | |
897 | } | |
898 | ||
9b6a126a | 899 | static int xhci_handle_halted_endpoint(struct xhci_hcd *xhci, |
7c6c334e MN |
900 | struct xhci_virt_ep *ep, unsigned int stream_id, |
901 | struct xhci_td *td, | |
902 | enum xhci_ep_reset_type reset_type) | |
903 | { | |
904 | unsigned int slot_id = ep->vdev->slot_id; | |
905 | int err; | |
906 | ||
907 | /* | |
908 | * Avoid resetting endpoint if link is inactive. Can cause host hang. | |
909 | * Device will be reset soon to recover the link so don't do anything | |
910 | */ | |
911 | if (ep->vdev->flags & VDEV_PORT_ERROR) | |
9b6a126a | 912 | return -ENODEV; |
7c6c334e | 913 | |
674f8438 MN |
914 | /* add td to cancelled list and let reset ep handler take care of it */ |
915 | if (reset_type == EP_HARD_RESET) { | |
916 | ep->ep_state |= EP_HARD_CLEAR_TOGGLE; | |
917 | if (td && list_empty(&td->cancelled_td_list)) { | |
918 | list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list); | |
919 | td->cancel_status = TD_HALTED; | |
920 | } | |
921 | } | |
922 | ||
51ee4a84 | 923 | if (ep->ep_state & EP_HALTED) { |
0d9b9f53 MN |
924 | xhci_dbg(xhci, "Reset ep command for ep_index %d already pending\n", |
925 | ep->ep_index); | |
9b6a126a | 926 | return 0; |
51ee4a84 MN |
927 | } |
928 | ||
7c6c334e MN |
929 | err = xhci_reset_halted_ep(xhci, slot_id, ep->ep_index, reset_type); |
930 | if (err) | |
9b6a126a | 931 | return err; |
7c6c334e | 932 | |
51ee4a84 MN |
933 | ep->ep_state |= EP_HALTED; |
934 | ||
7c6c334e | 935 | xhci_ring_cmd_db(xhci); |
9b6a126a MN |
936 | |
937 | return 0; | |
7c6c334e MN |
938 | } |
939 | ||
4db35692 MN |
940 | /* |
941 | * Fix up the ep ring first, so HW stops executing cancelled TDs. | |
942 | * We have the xHCI lock, so nothing can modify this list until we drop it. | |
943 | * We're also in the event handler, so we can't get re-interrupted if another | |
944 | * Stop Endpoint command completes. | |
674f8438 MN |
945 | * |
946 | * only call this when ring is not in a running state | |
4db35692 MN |
947 | */ |
948 | ||
674f8438 | 949 | static int xhci_invalidate_cancelled_tds(struct xhci_virt_ep *ep) |
4db35692 MN |
950 | { |
951 | struct xhci_hcd *xhci; | |
952 | struct xhci_td *td = NULL; | |
953 | struct xhci_td *tmp_td = NULL; | |
674f8438 | 954 | struct xhci_td *cached_td = NULL; |
4db35692 MN |
955 | struct xhci_ring *ring; |
956 | u64 hw_deq; | |
674f8438 | 957 | unsigned int slot_id = ep->vdev->slot_id; |
d1dbfb94 | 958 | int err; |
4db35692 MN |
959 | |
960 | xhci = ep->xhci; | |
961 | ||
962 | list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list, cancelled_td_list) { | |
963 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, | |
0d9b9f53 MN |
964 | "Removing canceled TD starting at 0x%llx (dma) in stream %u URB %p", |
965 | (unsigned long long)xhci_trb_virt_to_dma( | |
966 | td->start_seg, td->first_trb), | |
967 | td->urb->stream_id, td->urb); | |
4db35692 MN |
968 | list_del_init(&td->td_list); |
969 | ring = xhci_urb_to_transfer_ring(xhci, td->urb); | |
970 | if (!ring) { | |
971 | xhci_warn(xhci, "WARN Cancelled URB %p has invalid stream ID %u.\n", | |
972 | td->urb, td->urb->stream_id); | |
973 | continue; | |
974 | } | |
975 | /* | |
a7f2e927 | 976 | * If a ring stopped on the TD we need to cancel then we have to |
4db35692 | 977 | * move the xHC endpoint ring dequeue pointer past this TD. |
a7f2e927 MN |
978 | * Rings halted due to STALL may show hw_deq is past the stalled |
979 | * TD, but still require a set TR Deq command to flush xHC cache. | |
4db35692 MN |
980 | */ |
981 | hw_deq = xhci_get_hw_deq(xhci, ep->vdev, ep->ep_index, | |
982 | td->urb->stream_id); | |
983 | hw_deq &= ~0xf; | |
984 | ||
94f33914 MN |
985 | if (td->cancel_status == TD_HALTED || |
986 | trb_in_td(xhci, td->start_seg, td->first_trb, td->last_trb, hw_deq, false)) { | |
674f8438 MN |
987 | switch (td->cancel_status) { |
988 | case TD_CLEARED: /* TD is already no-op */ | |
989 | case TD_CLEARING_CACHE: /* set TR deq command already queued */ | |
990 | break; | |
991 | case TD_DIRTY: /* TD is cached, clear it */ | |
992 | case TD_HALTED: | |
94f33914 MN |
993 | td->cancel_status = TD_CLEARING_CACHE; |
994 | if (cached_td) | |
995 | /* FIXME stream case, several stopped rings */ | |
996 | xhci_dbg(xhci, | |
997 | "Move dq past stream %u URB %p instead of stream %u URB %p\n", | |
998 | td->urb->stream_id, td->urb, | |
999 | cached_td->urb->stream_id, cached_td->urb); | |
674f8438 MN |
1000 | cached_td = td; |
1001 | break; | |
1002 | } | |
4db35692 MN |
1003 | } else { |
1004 | td_to_noop(xhci, ring, td, false); | |
674f8438 | 1005 | td->cancel_status = TD_CLEARED; |
4db35692 | 1006 | } |
674f8438 | 1007 | } |
d1dbfb94 | 1008 | |
94f33914 MN |
1009 | /* If there's no need to move the dequeue pointer then we're done */ |
1010 | if (!cached_td) | |
1011 | return 0; | |
1012 | ||
1013 | err = xhci_move_dequeue_past_td(xhci, slot_id, ep->ep_index, | |
1014 | cached_td->urb->stream_id, | |
1015 | cached_td); | |
1016 | if (err) { | |
1017 | /* Failed to move past cached td, just set cached TDs to no-op */ | |
1018 | list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list, cancelled_td_list) { | |
1019 | if (td->cancel_status != TD_CLEARING_CACHE) | |
1020 | continue; | |
1021 | xhci_dbg(xhci, "Failed to clear cancelled cached URB %p, mark clear anyway\n", | |
1022 | td->urb); | |
1023 | td_to_noop(xhci, ring, td, false); | |
1024 | td->cancel_status = TD_CLEARED; | |
d1dbfb94 | 1025 | } |
4db35692 MN |
1026 | } |
1027 | return 0; | |
1028 | } | |
1029 | ||
9ebf3000 MN |
1030 | /* |
1031 | * Returns the TD the endpoint ring halted on. | |
1032 | * Only call for non-running rings without streams. | |
1033 | */ | |
1034 | static struct xhci_td *find_halted_td(struct xhci_virt_ep *ep) | |
1035 | { | |
1036 | struct xhci_td *td; | |
1037 | u64 hw_deq; | |
1038 | ||
1039 | if (!list_empty(&ep->ring->td_list)) { /* Not streams compatible */ | |
1040 | hw_deq = xhci_get_hw_deq(ep->xhci, ep->vdev, ep->ep_index, 0); | |
1041 | hw_deq &= ~0xf; | |
1042 | td = list_first_entry(&ep->ring->td_list, struct xhci_td, td_list); | |
1043 | if (trb_in_td(ep->xhci, td->start_seg, td->first_trb, | |
1044 | td->last_trb, hw_deq, false)) | |
1045 | return td; | |
1046 | } | |
1047 | return NULL; | |
1048 | } | |
1049 | ||
ae636747 SS |
1050 | /* |
1051 | * When we get a command completion for a Stop Endpoint Command, we need to | |
1052 | * unlink any cancelled TDs from the ring. There are two ways to do that: | |
1053 | * | |
1054 | * 1. If the HW was in the middle of processing the TD that needs to be | |
1055 | * cancelled, then we must move the ring's dequeue pointer past the last TRB | |
1056 | * in the TD with a Set Dequeue Pointer Command. | |
1057 | * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain | |
1058 | * bit cleared) so that the HW will skip over them. | |
1059 | */ | |
b8200c94 | 1060 | static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id, |
9ebf3000 | 1061 | union xhci_trb *trb, u32 comp_code) |
ae636747 | 1062 | { |
ae636747 | 1063 | unsigned int ep_index; |
63a0d9ab | 1064 | struct xhci_virt_ep *ep; |
19a7d0d6 | 1065 | struct xhci_ep_ctx *ep_ctx; |
9ebf3000 MN |
1066 | struct xhci_td *td = NULL; |
1067 | enum xhci_ep_reset_type reset_type; | |
1174d449 | 1068 | struct xhci_command *command; |
9b6a126a | 1069 | int err; |
ae636747 | 1070 | |
bc752bde | 1071 | if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) { |
9ea1833e | 1072 | if (!xhci->devs[slot_id]) |
674f8438 MN |
1073 | xhci_warn(xhci, "Stop endpoint command completion for disabled slot %u\n", |
1074 | slot_id); | |
be88fe4f AX |
1075 | return; |
1076 | } | |
1077 | ||
28ccd296 | 1078 | ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); |
b1adc42d MN |
1079 | ep = xhci_get_virt_ep(xhci, slot_id, ep_index); |
1080 | if (!ep) | |
1081 | return; | |
1082 | ||
674f8438 | 1083 | ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index); |
ae636747 | 1084 | |
674f8438 | 1085 | trace_xhci_handle_cmd_stop_ep(ep_ctx); |
04861f83 | 1086 | |
9ebf3000 MN |
1087 | if (comp_code == COMP_CONTEXT_STATE_ERROR) { |
1088 | /* | |
1089 | * If stop endpoint command raced with a halting endpoint we need to | |
1090 | * reset the host side endpoint first. | |
1091 | * If the TD we halted on isn't cancelled the TD should be given back | |
1092 | * with a proper error code, and the ring dequeue moved past the TD. | |
1093 | * If streams case we can't find hw_deq, or the TD we halted on so do a | |
1094 | * soft reset. | |
1095 | * | |
1096 | * Proper error code is unknown here, it would be -EPIPE if device side | |
1097 | * of enadpoit halted (aka STALL), and -EPROTO if not (transaction error) | |
1098 | * We use -EPROTO, if device is stalled it should return a stall error on | |
1099 | * next transfer, which then will return -EPIPE, and device side stall is | |
1100 | * noted and cleared by class driver. | |
1101 | */ | |
1102 | switch (GET_EP_CTX_STATE(ep_ctx)) { | |
1103 | case EP_STATE_HALTED: | |
1104 | xhci_dbg(xhci, "Stop ep completion raced with stall, reset ep\n"); | |
1105 | if (ep->ep_state & EP_HAS_STREAMS) { | |
1106 | reset_type = EP_SOFT_RESET; | |
1107 | } else { | |
1108 | reset_type = EP_HARD_RESET; | |
1109 | td = find_halted_td(ep); | |
1110 | if (td) | |
1111 | td->status = -EPROTO; | |
1112 | } | |
1113 | /* reset ep, reset handler cleans up cancelled tds */ | |
9b6a126a MN |
1114 | err = xhci_handle_halted_endpoint(xhci, ep, 0, td, |
1115 | reset_type); | |
1116 | if (err) | |
1117 | break; | |
9ebf3000 | 1118 | xhci_stop_watchdog_timer_in_irq(xhci, ep); |
1174d449 MN |
1119 | return; |
1120 | case EP_STATE_RUNNING: | |
1121 | /* Race, HW handled stop ep cmd before ep was running */ | |
0d9b9f53 MN |
1122 | xhci_dbg(xhci, "Stop ep completion ctx error, ep is running\n"); |
1123 | ||
1174d449 MN |
1124 | command = xhci_alloc_command(xhci, false, GFP_ATOMIC); |
1125 | if (!command) | |
1126 | xhci_stop_watchdog_timer_in_irq(xhci, ep); | |
1127 | ||
1128 | mod_timer(&ep->stop_cmd_timer, | |
1129 | jiffies + XHCI_STOP_EP_CMD_TIMEOUT * HZ); | |
1130 | xhci_queue_stop_endpoint(xhci, command, slot_id, ep_index, 0); | |
1131 | xhci_ring_cmd_db(xhci); | |
1132 | ||
9ebf3000 MN |
1133 | return; |
1134 | default: | |
1135 | break; | |
1136 | } | |
1137 | } | |
674f8438 MN |
1138 | /* will queue a set TR deq if stopped on a cancelled, uncleared TD */ |
1139 | xhci_invalidate_cancelled_tds(ep); | |
6f5165cf | 1140 | xhci_stop_watchdog_timer_in_irq(xhci, ep); |
ae636747 | 1141 | |
674f8438 MN |
1142 | /* Otherwise ring the doorbell(s) to restart queued transfers */ |
1143 | xhci_giveback_invalidated_tds(ep); | |
1144 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); | |
ae636747 SS |
1145 | } |
1146 | ||
50e8725e SS |
1147 | static void xhci_kill_ring_urbs(struct xhci_hcd *xhci, struct xhci_ring *ring) |
1148 | { | |
1149 | struct xhci_td *cur_td; | |
a54cfae3 | 1150 | struct xhci_td *tmp; |
50e8725e | 1151 | |
a54cfae3 | 1152 | list_for_each_entry_safe(cur_td, tmp, &ring->td_list, td_list) { |
50e8725e | 1153 | list_del_init(&cur_td->td_list); |
a54cfae3 | 1154 | |
50e8725e SS |
1155 | if (!list_empty(&cur_td->cancelled_td_list)) |
1156 | list_del_init(&cur_td->cancelled_td_list); | |
f9c589e1 | 1157 | |
a60f2f2f | 1158 | xhci_unmap_td_bounce_buffer(xhci, ring, cur_td); |
2a72126d MN |
1159 | |
1160 | inc_td_cnt(cur_td->urb); | |
1161 | if (last_td_in_urb(cur_td)) | |
1162 | xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN); | |
50e8725e SS |
1163 | } |
1164 | } | |
1165 | ||
1166 | static void xhci_kill_endpoint_urbs(struct xhci_hcd *xhci, | |
1167 | int slot_id, int ep_index) | |
1168 | { | |
1169 | struct xhci_td *cur_td; | |
a54cfae3 | 1170 | struct xhci_td *tmp; |
50e8725e SS |
1171 | struct xhci_virt_ep *ep; |
1172 | struct xhci_ring *ring; | |
1173 | ||
1174 | ep = &xhci->devs[slot_id]->eps[ep_index]; | |
21d0e51b SS |
1175 | if ((ep->ep_state & EP_HAS_STREAMS) || |
1176 | (ep->ep_state & EP_GETTING_NO_STREAMS)) { | |
1177 | int stream_id; | |
1178 | ||
4b895868 | 1179 | for (stream_id = 1; stream_id < ep->stream_info->num_streams; |
21d0e51b | 1180 | stream_id++) { |
4b895868 MN |
1181 | ring = ep->stream_info->stream_rings[stream_id]; |
1182 | if (!ring) | |
1183 | continue; | |
1184 | ||
21d0e51b SS |
1185 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
1186 | "Killing URBs for slot ID %u, ep index %u, stream %u", | |
4b895868 MN |
1187 | slot_id, ep_index, stream_id); |
1188 | xhci_kill_ring_urbs(xhci, ring); | |
21d0e51b SS |
1189 | } |
1190 | } else { | |
1191 | ring = ep->ring; | |
1192 | if (!ring) | |
1193 | return; | |
1194 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, | |
1195 | "Killing URBs for slot ID %u, ep index %u", | |
1196 | slot_id, ep_index); | |
1197 | xhci_kill_ring_urbs(xhci, ring); | |
1198 | } | |
2a72126d | 1199 | |
a54cfae3 FB |
1200 | list_for_each_entry_safe(cur_td, tmp, &ep->cancelled_td_list, |
1201 | cancelled_td_list) { | |
1202 | list_del_init(&cur_td->cancelled_td_list); | |
2a72126d | 1203 | inc_td_cnt(cur_td->urb); |
a54cfae3 | 1204 | |
2a72126d MN |
1205 | if (last_td_in_urb(cur_td)) |
1206 | xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN); | |
50e8725e SS |
1207 | } |
1208 | } | |
1209 | ||
d9f11ba9 MN |
1210 | /* |
1211 | * host controller died, register read returns 0xffffffff | |
1212 | * Complete pending commands, mark them ABORTED. | |
1213 | * URBs need to be given back as usb core might be waiting with device locks | |
1214 | * held for the URBs to finish during device disconnect, blocking host remove. | |
1215 | * | |
1216 | * Call with xhci->lock held. | |
1217 | * lock is relased and re-acquired while giving back urb. | |
1218 | */ | |
1219 | void xhci_hc_died(struct xhci_hcd *xhci) | |
1220 | { | |
1221 | int i, j; | |
1222 | ||
1223 | if (xhci->xhc_state & XHCI_STATE_DYING) | |
1224 | return; | |
1225 | ||
1226 | xhci_err(xhci, "xHCI host controller not responding, assume dead\n"); | |
1227 | xhci->xhc_state |= XHCI_STATE_DYING; | |
1228 | ||
1229 | xhci_cleanup_command_queue(xhci); | |
1230 | ||
1231 | /* return any pending urbs, remove may be waiting for them */ | |
1232 | for (i = 0; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) { | |
1233 | if (!xhci->devs[i]) | |
1234 | continue; | |
1235 | for (j = 0; j < 31; j++) | |
1236 | xhci_kill_endpoint_urbs(xhci, i, j); | |
1237 | } | |
1238 | ||
1239 | /* inform usb core hc died if PCI remove isn't already handling it */ | |
1240 | if (!(xhci->xhc_state & XHCI_STATE_REMOVING)) | |
1241 | usb_hc_died(xhci_to_hcd(xhci)); | |
1242 | } | |
1243 | ||
6f5165cf SS |
1244 | /* Watchdog timer function for when a stop endpoint command fails to complete. |
1245 | * In this case, we assume the host controller is broken or dying or dead. The | |
1246 | * host may still be completing some other events, so we have to be careful to | |
1247 | * let the event ring handler and the URB dequeueing/enqueueing functions know | |
1248 | * through xhci->state. | |
1249 | * | |
1250 | * The timer may also fire if the host takes a very long time to respond to the | |
1251 | * command, and the stop endpoint command completion handler cannot delete the | |
1252 | * timer before the timer function is called. Another endpoint cancellation may | |
1253 | * sneak in before the timer function can grab the lock, and that may queue | |
1254 | * another stop endpoint command and add the timer back. So we cannot use a | |
1255 | * simple flag to say whether there is a pending stop endpoint command for a | |
1256 | * particular endpoint. | |
1257 | * | |
f9926596 MN |
1258 | * Instead we use a combination of that flag and checking if a new timer is |
1259 | * pending. | |
6f5165cf | 1260 | */ |
66a45503 | 1261 | void xhci_stop_endpoint_command_watchdog(struct timer_list *t) |
6f5165cf | 1262 | { |
66a45503 KC |
1263 | struct xhci_virt_ep *ep = from_timer(ep, t, stop_cmd_timer); |
1264 | struct xhci_hcd *xhci = ep->xhci; | |
f43d6231 | 1265 | unsigned long flags; |
9c1aa36e | 1266 | u32 usbsts; |
4843b4b5 | 1267 | char str[XHCI_MSG_MAX]; |
6f5165cf | 1268 | |
f43d6231 | 1269 | spin_lock_irqsave(&xhci->lock, flags); |
6f5165cf | 1270 | |
f9926596 MN |
1271 | /* bail out if cmd completed but raced with stop ep watchdog timer.*/ |
1272 | if (!(ep->ep_state & EP_STOP_CMD_PENDING) || | |
1273 | timer_pending(&ep->stop_cmd_timer)) { | |
f43d6231 | 1274 | spin_unlock_irqrestore(&xhci->lock, flags); |
f9926596 | 1275 | xhci_dbg(xhci, "Stop EP timer raced with cmd completion, exit"); |
6f5165cf SS |
1276 | return; |
1277 | } | |
9c1aa36e | 1278 | usbsts = readl(&xhci->op_regs->status); |
6f5165cf SS |
1279 | |
1280 | xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n"); | |
4843b4b5 | 1281 | xhci_warn(xhci, "USBSTS:%s\n", xhci_decode_usbsts(str, usbsts)); |
9c1aa36e | 1282 | |
f9926596 MN |
1283 | ep->ep_state &= ~EP_STOP_CMD_PENDING; |
1284 | ||
d9f11ba9 | 1285 | xhci_halt(xhci); |
6f5165cf | 1286 | |
d9f11ba9 MN |
1287 | /* |
1288 | * handle a stop endpoint cmd timeout as if host died (-ENODEV). | |
1289 | * In the future we could distinguish between -ENODEV and -ETIMEDOUT | |
1290 | * and try to recover a -ETIMEDOUT with a host controller reset | |
1291 | */ | |
1292 | xhci_hc_died(xhci); | |
6f5165cf | 1293 | |
f43d6231 | 1294 | spin_unlock_irqrestore(&xhci->lock, flags); |
aa50b290 XR |
1295 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
1296 | "xHCI host controller is dead."); | |
6f5165cf SS |
1297 | } |
1298 | ||
b008df60 AX |
1299 | static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci, |
1300 | struct xhci_virt_device *dev, | |
1301 | struct xhci_ring *ep_ring, | |
1302 | unsigned int ep_index) | |
1303 | { | |
1304 | union xhci_trb *dequeue_temp; | |
1305 | int num_trbs_free_temp; | |
1306 | bool revert = false; | |
1307 | ||
1308 | num_trbs_free_temp = ep_ring->num_trbs_free; | |
1309 | dequeue_temp = ep_ring->dequeue; | |
1310 | ||
0d9f78a9 SS |
1311 | /* If we get two back-to-back stalls, and the first stalled transfer |
1312 | * ends just before a link TRB, the dequeue pointer will be left on | |
1313 | * the link TRB by the code in the while loop. So we have to update | |
1314 | * the dequeue pointer one segment further, or we'll jump off | |
1315 | * the segment into la-la-land. | |
1316 | */ | |
2d98ef40 | 1317 | if (trb_is_link(ep_ring->dequeue)) { |
0d9f78a9 SS |
1318 | ep_ring->deq_seg = ep_ring->deq_seg->next; |
1319 | ep_ring->dequeue = ep_ring->deq_seg->trbs; | |
1320 | } | |
1321 | ||
b008df60 AX |
1322 | while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) { |
1323 | /* We have more usable TRBs */ | |
1324 | ep_ring->num_trbs_free++; | |
1325 | ep_ring->dequeue++; | |
2d98ef40 | 1326 | if (trb_is_link(ep_ring->dequeue)) { |
b008df60 AX |
1327 | if (ep_ring->dequeue == |
1328 | dev->eps[ep_index].queued_deq_ptr) | |
1329 | break; | |
1330 | ep_ring->deq_seg = ep_ring->deq_seg->next; | |
1331 | ep_ring->dequeue = ep_ring->deq_seg->trbs; | |
1332 | } | |
1333 | if (ep_ring->dequeue == dequeue_temp) { | |
1334 | revert = true; | |
1335 | break; | |
1336 | } | |
1337 | } | |
1338 | ||
1339 | if (revert) { | |
1340 | xhci_dbg(xhci, "Unable to find new dequeue pointer\n"); | |
1341 | ep_ring->num_trbs_free = num_trbs_free_temp; | |
1342 | } | |
1343 | } | |
1344 | ||
ae636747 SS |
1345 | /* |
1346 | * When we get a completion for a Set Transfer Ring Dequeue Pointer command, | |
1347 | * we need to clear the set deq pending flag in the endpoint ring state, so that | |
1348 | * the TD queueing code can ring the doorbell again. We also need to ring the | |
1349 | * endpoint doorbell to restart the ring, but only if there aren't more | |
1350 | * cancellations pending. | |
1351 | */ | |
b8200c94 | 1352 | static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id, |
c69a0597 | 1353 | union xhci_trb *trb, u32 cmd_comp_code) |
ae636747 | 1354 | { |
ae636747 | 1355 | unsigned int ep_index; |
e9df17eb | 1356 | unsigned int stream_id; |
ae636747 | 1357 | struct xhci_ring *ep_ring; |
9aad95e2 | 1358 | struct xhci_virt_ep *ep; |
d115b048 JY |
1359 | struct xhci_ep_ctx *ep_ctx; |
1360 | struct xhci_slot_ctx *slot_ctx; | |
674f8438 | 1361 | struct xhci_td *td, *tmp_td; |
ae636747 | 1362 | |
28ccd296 ME |
1363 | ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); |
1364 | stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2])); | |
b1adc42d MN |
1365 | ep = xhci_get_virt_ep(xhci, slot_id, ep_index); |
1366 | if (!ep) | |
1367 | return; | |
e9df17eb | 1368 | |
42f2890a | 1369 | ep_ring = xhci_virt_ep_to_ring(xhci, ep, stream_id); |
e9df17eb | 1370 | if (!ep_ring) { |
e587b8b2 | 1371 | xhci_warn(xhci, "WARN Set TR deq ptr command for freed stream ID %u\n", |
e9df17eb SS |
1372 | stream_id); |
1373 | /* XXX: Harmless??? */ | |
0d4976ec | 1374 | goto cleanup; |
e9df17eb SS |
1375 | } |
1376 | ||
b1adc42d MN |
1377 | ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index); |
1378 | slot_ctx = xhci_get_slot_ctx(xhci, ep->vdev->out_ctx); | |
19a7d0d6 FB |
1379 | trace_xhci_handle_cmd_set_deq(slot_ctx); |
1380 | trace_xhci_handle_cmd_set_deq_ep(ep_ctx); | |
ae636747 | 1381 | |
c69a0597 | 1382 | if (cmd_comp_code != COMP_SUCCESS) { |
ae636747 SS |
1383 | unsigned int ep_state; |
1384 | unsigned int slot_state; | |
1385 | ||
c69a0597 | 1386 | switch (cmd_comp_code) { |
0b7c105a | 1387 | case COMP_TRB_ERROR: |
e587b8b2 | 1388 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n"); |
ae636747 | 1389 | break; |
0b7c105a | 1390 | case COMP_CONTEXT_STATE_ERROR: |
e587b8b2 | 1391 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n"); |
5071e6b2 | 1392 | ep_state = GET_EP_CTX_STATE(ep_ctx); |
28ccd296 | 1393 | slot_state = le32_to_cpu(slot_ctx->dev_state); |
ae636747 | 1394 | slot_state = GET_SLOT_STATE(slot_state); |
aa50b290 XR |
1395 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
1396 | "Slot state = %u, EP state = %u", | |
ae636747 SS |
1397 | slot_state, ep_state); |
1398 | break; | |
0b7c105a | 1399 | case COMP_SLOT_NOT_ENABLED_ERROR: |
e587b8b2 ON |
1400 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n", |
1401 | slot_id); | |
ae636747 SS |
1402 | break; |
1403 | default: | |
e587b8b2 ON |
1404 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n", |
1405 | cmd_comp_code); | |
ae636747 SS |
1406 | break; |
1407 | } | |
1408 | /* OK what do we do now? The endpoint state is hosed, and we | |
1409 | * should never get to this point if the synchronization between | |
1410 | * queueing, and endpoint state are correct. This might happen | |
1411 | * if the device gets disconnected after we've finished | |
1412 | * cancelling URBs, which might not be an error... | |
1413 | */ | |
1414 | } else { | |
9aad95e2 HG |
1415 | u64 deq; |
1416 | /* 4.6.10 deq ptr is written to the stream ctx for streams */ | |
1417 | if (ep->ep_state & EP_HAS_STREAMS) { | |
1418 | struct xhci_stream_ctx *ctx = | |
1419 | &ep->stream_info->stream_ctx_array[stream_id]; | |
1420 | deq = le64_to_cpu(ctx->stream_ring) & SCTX_DEQ_MASK; | |
1421 | } else { | |
1422 | deq = le64_to_cpu(ep_ctx->deq) & ~EP_CTX_CYCLE_MASK; | |
1423 | } | |
aa50b290 | 1424 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
9aad95e2 HG |
1425 | "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq); |
1426 | if (xhci_trb_virt_to_dma(ep->queued_deq_seg, | |
1427 | ep->queued_deq_ptr) == deq) { | |
bf161e85 SS |
1428 | /* Update the ring's dequeue segment and dequeue pointer |
1429 | * to reflect the new position. | |
1430 | */ | |
b1adc42d | 1431 | update_ring_for_set_deq_completion(xhci, ep->vdev, |
b008df60 | 1432 | ep_ring, ep_index); |
bf161e85 | 1433 | } else { |
e587b8b2 | 1434 | xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n"); |
bf161e85 | 1435 | xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n", |
9aad95e2 | 1436 | ep->queued_deq_seg, ep->queued_deq_ptr); |
bf161e85 | 1437 | } |
ae636747 | 1438 | } |
674f8438 MN |
1439 | /* HW cached TDs cleared from cache, give them back */ |
1440 | list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list, | |
1441 | cancelled_td_list) { | |
1442 | ep_ring = xhci_urb_to_transfer_ring(ep->xhci, td->urb); | |
1443 | if (td->cancel_status == TD_CLEARING_CACHE) { | |
1444 | td->cancel_status = TD_CLEARED; | |
0d9b9f53 MN |
1445 | xhci_dbg(ep->xhci, "%s: Giveback cancelled URB %p TD\n", |
1446 | __func__, td->urb); | |
674f8438 | 1447 | xhci_td_cleanup(ep->xhci, td, ep_ring, td->status); |
0d9b9f53 MN |
1448 | } else { |
1449 | xhci_dbg(ep->xhci, "%s: Keep cancelled URB %p TD as cancel_status is %d\n", | |
1450 | __func__, td->urb, td->cancel_status); | |
674f8438 MN |
1451 | } |
1452 | } | |
0d4976ec | 1453 | cleanup: |
b1adc42d MN |
1454 | ep->ep_state &= ~SET_DEQ_PENDING; |
1455 | ep->queued_deq_seg = NULL; | |
1456 | ep->queued_deq_ptr = NULL; | |
e9df17eb SS |
1457 | /* Restart any rings with pending URBs */ |
1458 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); | |
ae636747 SS |
1459 | } |
1460 | ||
b8200c94 | 1461 | static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id, |
c69a0597 | 1462 | union xhci_trb *trb, u32 cmd_comp_code) |
a1587d97 | 1463 | { |
b1adc42d | 1464 | struct xhci_virt_ep *ep; |
19a7d0d6 | 1465 | struct xhci_ep_ctx *ep_ctx; |
a1587d97 SS |
1466 | unsigned int ep_index; |
1467 | ||
28ccd296 | 1468 | ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); |
b1adc42d MN |
1469 | ep = xhci_get_virt_ep(xhci, slot_id, ep_index); |
1470 | if (!ep) | |
1471 | return; | |
1472 | ||
1473 | ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index); | |
19a7d0d6 FB |
1474 | trace_xhci_handle_cmd_reset_ep(ep_ctx); |
1475 | ||
a1587d97 SS |
1476 | /* This command will only fail if the endpoint wasn't halted, |
1477 | * but we don't care. | |
1478 | */ | |
a0254324 | 1479 | xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep, |
c69a0597 | 1480 | "Ignoring reset ep completion code of %u", cmd_comp_code); |
a1587d97 | 1481 | |
674f8438 MN |
1482 | /* Cleanup cancelled TDs as ep is stopped. May queue a Set TR Deq cmd */ |
1483 | xhci_invalidate_cancelled_tds(ep); | |
74e0b564 | 1484 | |
674f8438 MN |
1485 | if (xhci->quirks & XHCI_RESET_EP_QUIRK) |
1486 | xhci_dbg(xhci, "Note: Removed workaround to queue config ep for this hw"); | |
1487 | /* Clear our internal halted state */ | |
1488 | ep->ep_state &= ~EP_HALTED; | |
74e0b564 | 1489 | |
674f8438 | 1490 | xhci_giveback_invalidated_tds(ep); |
f8f80be5 MN |
1491 | |
1492 | /* if this was a soft reset, then restart */ | |
1493 | if ((le32_to_cpu(trb->generic.field[3])) & TRB_TSP) | |
1494 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); | |
a1587d97 | 1495 | } |
ae636747 | 1496 | |
b244b431 | 1497 | static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id, |
c2d3d49b | 1498 | struct xhci_command *command, u32 cmd_comp_code) |
b244b431 XR |
1499 | { |
1500 | if (cmd_comp_code == COMP_SUCCESS) | |
c2d3d49b | 1501 | command->slot_id = slot_id; |
b244b431 | 1502 | else |
c2d3d49b | 1503 | command->slot_id = 0; |
b244b431 XR |
1504 | } |
1505 | ||
6c02dd14 XR |
1506 | static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id) |
1507 | { | |
1508 | struct xhci_virt_device *virt_dev; | |
19a7d0d6 | 1509 | struct xhci_slot_ctx *slot_ctx; |
6c02dd14 XR |
1510 | |
1511 | virt_dev = xhci->devs[slot_id]; | |
1512 | if (!virt_dev) | |
1513 | return; | |
19a7d0d6 FB |
1514 | |
1515 | slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx); | |
1516 | trace_xhci_handle_cmd_disable_slot(slot_ctx); | |
1517 | ||
6c02dd14 XR |
1518 | if (xhci->quirks & XHCI_EP_LIMIT_QUIRK) |
1519 | /* Delete default control endpoint resources */ | |
1520 | xhci_free_device_endpoint_resources(xhci, virt_dev, true); | |
1521 | xhci_free_virt_device(xhci, slot_id); | |
1522 | } | |
1523 | ||
6ed46d33 | 1524 | static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id, |
a1810307 | 1525 | u32 cmd_comp_code) |
6ed46d33 XR |
1526 | { |
1527 | struct xhci_virt_device *virt_dev; | |
1528 | struct xhci_input_control_ctx *ctrl_ctx; | |
19a7d0d6 | 1529 | struct xhci_ep_ctx *ep_ctx; |
6ed46d33 XR |
1530 | unsigned int ep_index; |
1531 | unsigned int ep_state; | |
1532 | u32 add_flags, drop_flags; | |
1533 | ||
6ed46d33 XR |
1534 | /* |
1535 | * Configure endpoint commands can come from the USB core | |
1536 | * configuration or alt setting changes, or because the HW | |
1537 | * needed an extra configure endpoint command after a reset | |
1538 | * endpoint command or streams were being configured. | |
1539 | * If the command was for a halted endpoint, the xHCI driver | |
1540 | * is not waiting on the configure endpoint command. | |
1541 | */ | |
9ea1833e | 1542 | virt_dev = xhci->devs[slot_id]; |
03ed579d MN |
1543 | if (!virt_dev) |
1544 | return; | |
4daf9df5 | 1545 | ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx); |
6ed46d33 XR |
1546 | if (!ctrl_ctx) { |
1547 | xhci_warn(xhci, "Could not get input context, bad type.\n"); | |
1548 | return; | |
1549 | } | |
1550 | ||
1551 | add_flags = le32_to_cpu(ctrl_ctx->add_flags); | |
1552 | drop_flags = le32_to_cpu(ctrl_ctx->drop_flags); | |
1553 | /* Input ctx add_flags are the endpoint index plus one */ | |
1554 | ep_index = xhci_last_valid_endpoint(add_flags) - 1; | |
1555 | ||
19a7d0d6 FB |
1556 | ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, ep_index); |
1557 | trace_xhci_handle_cmd_config_ep(ep_ctx); | |
1558 | ||
6ed46d33 XR |
1559 | /* A usb_set_interface() call directly after clearing a halted |
1560 | * condition may race on this quirky hardware. Not worth | |
1561 | * worrying about, since this is prototype hardware. Not sure | |
1562 | * if this will work for streams, but streams support was | |
1563 | * untested on this prototype. | |
1564 | */ | |
1565 | if (xhci->quirks & XHCI_RESET_EP_QUIRK && | |
1566 | ep_index != (unsigned int) -1 && | |
1567 | add_flags - SLOT_FLAG == drop_flags) { | |
1568 | ep_state = virt_dev->eps[ep_index].ep_state; | |
1569 | if (!(ep_state & EP_HALTED)) | |
ddba5cd0 | 1570 | return; |
6ed46d33 XR |
1571 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
1572 | "Completed config ep cmd - " | |
1573 | "last ep index = %d, state = %d", | |
1574 | ep_index, ep_state); | |
1575 | /* Clear internal halted state and restart ring(s) */ | |
1576 | virt_dev->eps[ep_index].ep_state &= ~EP_HALTED; | |
1577 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); | |
1578 | return; | |
1579 | } | |
6ed46d33 XR |
1580 | return; |
1581 | } | |
1582 | ||
19a7d0d6 FB |
1583 | static void xhci_handle_cmd_addr_dev(struct xhci_hcd *xhci, int slot_id) |
1584 | { | |
1585 | struct xhci_virt_device *vdev; | |
1586 | struct xhci_slot_ctx *slot_ctx; | |
1587 | ||
1588 | vdev = xhci->devs[slot_id]; | |
03ed579d MN |
1589 | if (!vdev) |
1590 | return; | |
19a7d0d6 FB |
1591 | slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx); |
1592 | trace_xhci_handle_cmd_addr_dev(slot_ctx); | |
1593 | } | |
1594 | ||
a1810307 | 1595 | static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id) |
f681321b | 1596 | { |
19a7d0d6 FB |
1597 | struct xhci_virt_device *vdev; |
1598 | struct xhci_slot_ctx *slot_ctx; | |
1599 | ||
1600 | vdev = xhci->devs[slot_id]; | |
03ed579d MN |
1601 | if (!vdev) { |
1602 | xhci_warn(xhci, "Reset device command completion for disabled slot %u\n", | |
1603 | slot_id); | |
1604 | return; | |
1605 | } | |
19a7d0d6 FB |
1606 | slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx); |
1607 | trace_xhci_handle_cmd_reset_dev(slot_ctx); | |
1608 | ||
f681321b | 1609 | xhci_dbg(xhci, "Completed reset device command.\n"); |
f681321b XR |
1610 | } |
1611 | ||
2c070821 XR |
1612 | static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci, |
1613 | struct xhci_event_cmd *event) | |
1614 | { | |
1615 | if (!(xhci->quirks & XHCI_NEC_HOST)) { | |
f4c8f03c | 1616 | xhci_warn(xhci, "WARN NEC_GET_FW command on non-NEC host\n"); |
2c070821 XR |
1617 | return; |
1618 | } | |
1619 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, | |
1620 | "NEC firmware version %2x.%02x", | |
1621 | NEC_FW_MAJOR(le32_to_cpu(event->status)), | |
1622 | NEC_FW_MINOR(le32_to_cpu(event->status))); | |
1623 | } | |
1624 | ||
9ea1833e | 1625 | static void xhci_complete_del_and_free_cmd(struct xhci_command *cmd, u32 status) |
c9aa1a2d MN |
1626 | { |
1627 | list_del(&cmd->cmd_list); | |
9ea1833e MN |
1628 | |
1629 | if (cmd->completion) { | |
1630 | cmd->status = status; | |
1631 | complete(cmd->completion); | |
1632 | } else { | |
c9aa1a2d | 1633 | kfree(cmd); |
9ea1833e | 1634 | } |
c9aa1a2d MN |
1635 | } |
1636 | ||
1637 | void xhci_cleanup_command_queue(struct xhci_hcd *xhci) | |
1638 | { | |
1639 | struct xhci_command *cur_cmd, *tmp_cmd; | |
d1aad52c | 1640 | xhci->current_cmd = NULL; |
c9aa1a2d | 1641 | list_for_each_entry_safe(cur_cmd, tmp_cmd, &xhci->cmd_list, cmd_list) |
0b7c105a | 1642 | xhci_complete_del_and_free_cmd(cur_cmd, COMP_COMMAND_ABORTED); |
c9aa1a2d MN |
1643 | } |
1644 | ||
cb4d5ce5 | 1645 | void xhci_handle_command_timeout(struct work_struct *work) |
c311e391 MN |
1646 | { |
1647 | struct xhci_hcd *xhci; | |
c311e391 MN |
1648 | unsigned long flags; |
1649 | u64 hw_ring_state; | |
cb4d5ce5 OH |
1650 | |
1651 | xhci = container_of(to_delayed_work(work), struct xhci_hcd, cmd_timer); | |
c311e391 | 1652 | |
c311e391 | 1653 | spin_lock_irqsave(&xhci->lock, flags); |
2b985467 | 1654 | |
a5a1b951 MN |
1655 | /* |
1656 | * If timeout work is pending, or current_cmd is NULL, it means we | |
1657 | * raced with command completion. Command is handled so just return. | |
1658 | */ | |
cb4d5ce5 | 1659 | if (!xhci->current_cmd || delayed_work_pending(&xhci->cmd_timer)) { |
2b985467 LB |
1660 | spin_unlock_irqrestore(&xhci->lock, flags); |
1661 | return; | |
c311e391 | 1662 | } |
2b985467 | 1663 | /* mark this command to be cancelled */ |
0b7c105a | 1664 | xhci->current_cmd->status = COMP_COMMAND_ABORTED; |
2b985467 | 1665 | |
c311e391 MN |
1666 | /* Make sure command ring is running before aborting it */ |
1667 | hw_ring_state = xhci_read_64(xhci, &xhci->op_regs->cmd_ring); | |
d9f11ba9 MN |
1668 | if (hw_ring_state == ~(u64)0) { |
1669 | xhci_hc_died(xhci); | |
1670 | goto time_out_completed; | |
1671 | } | |
1672 | ||
c311e391 MN |
1673 | if ((xhci->cmd_ring_state & CMD_RING_STATE_RUNNING) && |
1674 | (hw_ring_state & CMD_RING_RUNNING)) { | |
1c111b6c OH |
1675 | /* Prevent new doorbell, and start command abort */ |
1676 | xhci->cmd_ring_state = CMD_RING_STATE_ABORTED; | |
c311e391 | 1677 | xhci_dbg(xhci, "Command timeout\n"); |
d9f11ba9 | 1678 | xhci_abort_cmd_ring(xhci, flags); |
4dea7077 | 1679 | goto time_out_completed; |
c311e391 | 1680 | } |
3425aa03 | 1681 | |
1c111b6c OH |
1682 | /* host removed. Bail out */ |
1683 | if (xhci->xhc_state & XHCI_STATE_REMOVING) { | |
1684 | xhci_dbg(xhci, "host removed, ring start fail?\n"); | |
3425aa03 | 1685 | xhci_cleanup_command_queue(xhci); |
4dea7077 LB |
1686 | |
1687 | goto time_out_completed; | |
3425aa03 MN |
1688 | } |
1689 | ||
c311e391 MN |
1690 | /* command timeout on stopped ring, ring can't be aborted */ |
1691 | xhci_dbg(xhci, "Command timeout on stopped ring\n"); | |
1692 | xhci_handle_stopped_cmd_ring(xhci, xhci->current_cmd); | |
4dea7077 LB |
1693 | |
1694 | time_out_completed: | |
c311e391 MN |
1695 | spin_unlock_irqrestore(&xhci->lock, flags); |
1696 | return; | |
1697 | } | |
1698 | ||
7f84eef0 SS |
1699 | static void handle_cmd_completion(struct xhci_hcd *xhci, |
1700 | struct xhci_event_cmd *event) | |
1701 | { | |
296fcdab | 1702 | unsigned int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
7f84eef0 SS |
1703 | u64 cmd_dma; |
1704 | dma_addr_t cmd_dequeue_dma; | |
e7a79a1d | 1705 | u32 cmd_comp_code; |
9124b121 | 1706 | union xhci_trb *cmd_trb; |
c9aa1a2d | 1707 | struct xhci_command *cmd; |
b54fc46d | 1708 | u32 cmd_type; |
7f84eef0 | 1709 | |
296fcdab LKK |
1710 | if (slot_id >= MAX_HC_SLOTS) { |
1711 | xhci_warn(xhci, "Invalid slot_id %u\n", slot_id); | |
1712 | return; | |
1713 | } | |
1714 | ||
28ccd296 | 1715 | cmd_dma = le64_to_cpu(event->cmd_trb); |
9124b121 | 1716 | cmd_trb = xhci->cmd_ring->dequeue; |
a37c3f76 FB |
1717 | |
1718 | trace_xhci_handle_command(xhci->cmd_ring, &cmd_trb->generic); | |
1719 | ||
23e3be11 | 1720 | cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg, |
9124b121 | 1721 | cmd_trb); |
f4c8f03c LB |
1722 | /* |
1723 | * Check whether the completion event is for our internal kept | |
1724 | * command. | |
1725 | */ | |
1726 | if (!cmd_dequeue_dma || cmd_dma != (u64)cmd_dequeue_dma) { | |
1727 | xhci_warn(xhci, | |
1728 | "ERROR mismatched command completion event\n"); | |
7f84eef0 SS |
1729 | return; |
1730 | } | |
b63f4053 | 1731 | |
04861f83 | 1732 | cmd = list_first_entry(&xhci->cmd_list, struct xhci_command, cmd_list); |
c9aa1a2d | 1733 | |
cb4d5ce5 | 1734 | cancel_delayed_work(&xhci->cmd_timer); |
c311e391 | 1735 | |
e7a79a1d | 1736 | cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status)); |
c311e391 MN |
1737 | |
1738 | /* If CMD ring stopped we own the trbs between enqueue and dequeue */ | |
604d02a2 | 1739 | if (cmd_comp_code == COMP_COMMAND_RING_STOPPED) { |
1c111b6c | 1740 | complete_all(&xhci->cmd_ring_stop_completion); |
c311e391 MN |
1741 | return; |
1742 | } | |
33be1265 MN |
1743 | |
1744 | if (cmd->command_trb != xhci->cmd_ring->dequeue) { | |
1745 | xhci_err(xhci, | |
1746 | "Command completion event does not match command\n"); | |
1747 | return; | |
1748 | } | |
1749 | ||
c311e391 MN |
1750 | /* |
1751 | * Host aborted the command ring, check if the current command was | |
1752 | * supposed to be aborted, otherwise continue normally. | |
1753 | * The command ring is stopped now, but the xHC will issue a Command | |
1754 | * Ring Stopped event which will cause us to restart it. | |
1755 | */ | |
0b7c105a | 1756 | if (cmd_comp_code == COMP_COMMAND_ABORTED) { |
c311e391 | 1757 | xhci->cmd_ring_state = CMD_RING_STATE_STOPPED; |
0b7c105a | 1758 | if (cmd->status == COMP_COMMAND_ABORTED) { |
2a7cfdf3 BW |
1759 | if (xhci->current_cmd == cmd) |
1760 | xhci->current_cmd = NULL; | |
c311e391 | 1761 | goto event_handled; |
2a7cfdf3 | 1762 | } |
b63f4053 EF |
1763 | } |
1764 | ||
b54fc46d XR |
1765 | cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3])); |
1766 | switch (cmd_type) { | |
1767 | case TRB_ENABLE_SLOT: | |
c2d3d49b | 1768 | xhci_handle_cmd_enable_slot(xhci, slot_id, cmd, cmd_comp_code); |
3ffbba95 | 1769 | break; |
b54fc46d | 1770 | case TRB_DISABLE_SLOT: |
6c02dd14 | 1771 | xhci_handle_cmd_disable_slot(xhci, slot_id); |
3ffbba95 | 1772 | break; |
b54fc46d | 1773 | case TRB_CONFIG_EP: |
9ea1833e | 1774 | if (!cmd->completion) |
a1810307 | 1775 | xhci_handle_cmd_config_ep(xhci, slot_id, cmd_comp_code); |
f94e0186 | 1776 | break; |
b54fc46d | 1777 | case TRB_EVAL_CONTEXT: |
2d3f1fac | 1778 | break; |
b54fc46d | 1779 | case TRB_ADDR_DEV: |
19a7d0d6 | 1780 | xhci_handle_cmd_addr_dev(xhci, slot_id); |
3ffbba95 | 1781 | break; |
b54fc46d | 1782 | case TRB_STOP_RING: |
b8200c94 XR |
1783 | WARN_ON(slot_id != TRB_TO_SLOT_ID( |
1784 | le32_to_cpu(cmd_trb->generic.field[3]))); | |
a38fe338 | 1785 | if (!cmd->completion) |
9ebf3000 MN |
1786 | xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb, |
1787 | cmd_comp_code); | |
ae636747 | 1788 | break; |
b54fc46d | 1789 | case TRB_SET_DEQ: |
b8200c94 XR |
1790 | WARN_ON(slot_id != TRB_TO_SLOT_ID( |
1791 | le32_to_cpu(cmd_trb->generic.field[3]))); | |
c69a0597 | 1792 | xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code); |
ae636747 | 1793 | break; |
b54fc46d | 1794 | case TRB_CMD_NOOP: |
c311e391 | 1795 | /* Is this an aborted command turned to NO-OP? */ |
604d02a2 MN |
1796 | if (cmd->status == COMP_COMMAND_RING_STOPPED) |
1797 | cmd_comp_code = COMP_COMMAND_RING_STOPPED; | |
7f84eef0 | 1798 | break; |
b54fc46d | 1799 | case TRB_RESET_EP: |
b8200c94 XR |
1800 | WARN_ON(slot_id != TRB_TO_SLOT_ID( |
1801 | le32_to_cpu(cmd_trb->generic.field[3]))); | |
c69a0597 | 1802 | xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code); |
a1587d97 | 1803 | break; |
b54fc46d | 1804 | case TRB_RESET_DEV: |
6fcfb0d6 MN |
1805 | /* SLOT_ID field in reset device cmd completion event TRB is 0. |
1806 | * Use the SLOT_ID from the command TRB instead (xhci 4.6.11) | |
1807 | */ | |
1808 | slot_id = TRB_TO_SLOT_ID( | |
1809 | le32_to_cpu(cmd_trb->generic.field[3])); | |
a1810307 | 1810 | xhci_handle_cmd_reset_dev(xhci, slot_id); |
2a8f82c4 | 1811 | break; |
b54fc46d | 1812 | case TRB_NEC_GET_FW: |
2c070821 | 1813 | xhci_handle_cmd_nec_get_fw(xhci, event); |
0238634d | 1814 | break; |
7f84eef0 SS |
1815 | default: |
1816 | /* Skip over unknown commands on the event ring */ | |
f4c8f03c | 1817 | xhci_info(xhci, "INFO unknown command type %d\n", cmd_type); |
7f84eef0 SS |
1818 | break; |
1819 | } | |
c9aa1a2d | 1820 | |
c311e391 | 1821 | /* restart timer if this wasn't the last command */ |
daa47f21 | 1822 | if (!list_is_singular(&xhci->cmd_list)) { |
04861f83 FB |
1823 | xhci->current_cmd = list_first_entry(&cmd->cmd_list, |
1824 | struct xhci_command, cmd_list); | |
cb4d5ce5 | 1825 | xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT); |
2b985467 LB |
1826 | } else if (xhci->current_cmd == cmd) { |
1827 | xhci->current_cmd = NULL; | |
c311e391 MN |
1828 | } |
1829 | ||
1830 | event_handled: | |
9ea1833e | 1831 | xhci_complete_del_and_free_cmd(cmd, cmd_comp_code); |
c9aa1a2d | 1832 | |
3b72fca0 | 1833 | inc_deq(xhci, xhci->cmd_ring); |
7f84eef0 SS |
1834 | } |
1835 | ||
0238634d | 1836 | static void handle_vendor_event(struct xhci_hcd *xhci, |
0353810a | 1837 | union xhci_trb *event, u32 trb_type) |
0238634d | 1838 | { |
0238634d SS |
1839 | xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type); |
1840 | if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST)) | |
1841 | handle_cmd_completion(xhci, &event->event_cmd); | |
1842 | } | |
1843 | ||
623bef9e SS |
1844 | static void handle_device_notification(struct xhci_hcd *xhci, |
1845 | union xhci_trb *event) | |
1846 | { | |
1847 | u32 slot_id; | |
4ee823b8 | 1848 | struct usb_device *udev; |
623bef9e | 1849 | |
7e76ad43 | 1850 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3])); |
4ee823b8 | 1851 | if (!xhci->devs[slot_id]) { |
623bef9e SS |
1852 | xhci_warn(xhci, "Device Notification event for " |
1853 | "unused slot %u\n", slot_id); | |
4ee823b8 SS |
1854 | return; |
1855 | } | |
1856 | ||
1857 | xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n", | |
1858 | slot_id); | |
1859 | udev = xhci->devs[slot_id]->udev; | |
1860 | if (udev && udev->parent) | |
1861 | usb_wakeup_notification(udev->parent, udev->portnum); | |
623bef9e SS |
1862 | } |
1863 | ||
11644a76 CG |
1864 | /* |
1865 | * Quirk hanlder for errata seen on Cavium ThunderX2 processor XHCI | |
1866 | * Controller. | |
1867 | * As per ThunderX2errata-129 USB 2 device may come up as USB 1 | |
1868 | * If a connection to a USB 1 device is followed by another connection | |
1869 | * to a USB 2 device. | |
1870 | * | |
1871 | * Reset the PHY after the USB device is disconnected if device speed | |
1872 | * is less than HCD_USB3. | |
1873 | * Retry the reset sequence max of 4 times checking the PLL lock status. | |
1874 | * | |
1875 | */ | |
1876 | static void xhci_cavium_reset_phy_quirk(struct xhci_hcd *xhci) | |
1877 | { | |
1878 | struct usb_hcd *hcd = xhci_to_hcd(xhci); | |
1879 | u32 pll_lock_check; | |
1880 | u32 retry_count = 4; | |
1881 | ||
1882 | do { | |
1883 | /* Assert PHY reset */ | |
1884 | writel(0x6F, hcd->regs + 0x1048); | |
1885 | udelay(10); | |
1886 | /* De-assert the PHY reset */ | |
1887 | writel(0x7F, hcd->regs + 0x1048); | |
1888 | udelay(200); | |
1889 | pll_lock_check = readl(hcd->regs + 0x1070); | |
1890 | } while (!(pll_lock_check & 0x1) && --retry_count); | |
1891 | } | |
1892 | ||
0f2a7930 SS |
1893 | static void handle_port_status(struct xhci_hcd *xhci, |
1894 | union xhci_trb *event) | |
1895 | { | |
f6ff0ac8 | 1896 | struct usb_hcd *hcd; |
0f2a7930 | 1897 | u32 port_id; |
76a0f32b | 1898 | u32 portsc, cmd_reg; |
518e848e | 1899 | int max_ports; |
56192531 | 1900 | int slot_id; |
74e6ad58 | 1901 | unsigned int hcd_portnum; |
20b67cf5 | 1902 | struct xhci_bus_state *bus_state; |
386139d7 | 1903 | bool bogus_port_status = false; |
52c7755b | 1904 | struct xhci_port *port; |
0f2a7930 SS |
1905 | |
1906 | /* Port status change events always have a successful completion code */ | |
f4c8f03c LB |
1907 | if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) |
1908 | xhci_warn(xhci, | |
1909 | "WARN: xHC returned failed port status event\n"); | |
1910 | ||
28ccd296 | 1911 | port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0])); |
518e848e | 1912 | max_ports = HCS_MAX_PORTS(xhci->hcs_params1); |
d70d5a84 | 1913 | |
518e848e | 1914 | if ((port_id <= 0) || (port_id > max_ports)) { |
d70d5a84 MN |
1915 | xhci_warn(xhci, "Port change event with invalid port ID %d\n", |
1916 | port_id); | |
09ce0c0c PC |
1917 | inc_deq(xhci, xhci->event_ring); |
1918 | return; | |
56192531 AX |
1919 | } |
1920 | ||
52c7755b MN |
1921 | port = &xhci->hw_ports[port_id - 1]; |
1922 | if (!port || !port->rhub || port->hcd_portnum == DUPLICATE_ENTRY) { | |
d70d5a84 MN |
1923 | xhci_warn(xhci, "Port change event, no port for port ID %u\n", |
1924 | port_id); | |
386139d7 | 1925 | bogus_port_status = true; |
f6ff0ac8 SS |
1926 | goto cleanup; |
1927 | } | |
1928 | ||
1245374e MN |
1929 | /* We might get interrupts after shared_hcd is removed */ |
1930 | if (port->rhub == &xhci->usb3_rhub && xhci->shared_hcd == NULL) { | |
1931 | xhci_dbg(xhci, "ignore port event for removed USB3 hcd\n"); | |
1932 | bogus_port_status = true; | |
1933 | goto cleanup; | |
1934 | } | |
1935 | ||
52c7755b | 1936 | hcd = port->rhub->hcd; |
f6187f42 | 1937 | bus_state = &port->rhub->bus_state; |
74e6ad58 | 1938 | hcd_portnum = port->hcd_portnum; |
52c7755b | 1939 | portsc = readl(port->addr); |
5308a91b | 1940 | |
d70d5a84 MN |
1941 | xhci_dbg(xhci, "Port change event, %d-%d, id %d, portsc: 0x%x\n", |
1942 | hcd->self.busnum, hcd_portnum + 1, port_id, portsc); | |
1943 | ||
74e6ad58 | 1944 | trace_xhci_handle_port_status(hcd_portnum, portsc); |
8ca1358b | 1945 | |
7111ebc9 | 1946 | if (hcd->state == HC_STATE_SUSPENDED) { |
56192531 AX |
1947 | xhci_dbg(xhci, "resume root hub\n"); |
1948 | usb_hcd_resume_root_hub(hcd); | |
1949 | } | |
1950 | ||
b8c3b718 MN |
1951 | if (hcd->speed >= HCD_USB3 && |
1952 | (portsc & PORT_PLS_MASK) == XDEV_INACTIVE) { | |
1953 | slot_id = xhci_find_slot_id_by_port(hcd, xhci, hcd_portnum + 1); | |
1954 | if (slot_id && xhci->devs[slot_id]) | |
1955 | xhci->devs[slot_id]->flags |= VDEV_PORT_ERROR; | |
b8c3b718 | 1956 | } |
fac4271d | 1957 | |
76a0f32b | 1958 | if ((portsc & PORT_PLC) && (portsc & PORT_PLS_MASK) == XDEV_RESUME) { |
56192531 AX |
1959 | xhci_dbg(xhci, "port resume event for port %d\n", port_id); |
1960 | ||
76a0f32b MN |
1961 | cmd_reg = readl(&xhci->op_regs->command); |
1962 | if (!(cmd_reg & CMD_RUN)) { | |
56192531 AX |
1963 | xhci_warn(xhci, "xHC is not running.\n"); |
1964 | goto cleanup; | |
1965 | } | |
1966 | ||
76a0f32b | 1967 | if (DEV_SUPERSPEED_ANY(portsc)) { |
d93814cf | 1968 | xhci_dbg(xhci, "remote wake SS port %d\n", port_id); |
4ee823b8 SS |
1969 | /* Set a flag to say the port signaled remote wakeup, |
1970 | * so we can tell the difference between the end of | |
1971 | * device and host initiated resume. | |
1972 | */ | |
74e6ad58 | 1973 | bus_state->port_remote_wakeup |= 1 << hcd_portnum; |
eaefcf24 | 1974 | xhci_test_and_clear_bit(xhci, port, PORT_PLC); |
057d476f | 1975 | usb_hcd_start_port_resume(&hcd->self, hcd_portnum); |
6b7f40f7 | 1976 | xhci_set_link_state(xhci, port, XDEV_U0); |
d93814cf SS |
1977 | /* Need to wait until the next link state change |
1978 | * indicates the device is actually in U0. | |
1979 | */ | |
1980 | bogus_port_status = true; | |
1981 | goto cleanup; | |
74e6ad58 | 1982 | } else if (!test_bit(hcd_portnum, &bus_state->resuming_ports)) { |
56192531 | 1983 | xhci_dbg(xhci, "resume HS port %d\n", port_id); |
74e6ad58 | 1984 | bus_state->resume_done[hcd_portnum] = jiffies + |
b9e45188 | 1985 | msecs_to_jiffies(USB_RESUME_TIMEOUT); |
74e6ad58 | 1986 | set_bit(hcd_portnum, &bus_state->resuming_ports); |
0914ea66 AG |
1987 | /* Do the rest in GetPortStatus after resume time delay. |
1988 | * Avoid polling roothub status before that so that a | |
1989 | * usb device auto-resume latency around ~40ms. | |
1990 | */ | |
1991 | set_bit(HCD_FLAG_POLL_RH, &hcd->flags); | |
56192531 | 1992 | mod_timer(&hcd->rh_timer, |
74e6ad58 | 1993 | bus_state->resume_done[hcd_portnum]); |
330e2d61 | 1994 | usb_hcd_start_port_resume(&hcd->self, hcd_portnum); |
0914ea66 | 1995 | bogus_port_status = true; |
56192531 AX |
1996 | } |
1997 | } | |
d93814cf | 1998 | |
6cbcf596 MN |
1999 | if ((portsc & PORT_PLC) && |
2000 | DEV_SUPERSPEED_ANY(portsc) && | |
2001 | ((portsc & PORT_PLS_MASK) == XDEV_U0 || | |
2002 | (portsc & PORT_PLS_MASK) == XDEV_U1 || | |
2003 | (portsc & PORT_PLS_MASK) == XDEV_U2)) { | |
d93814cf | 2004 | xhci_dbg(xhci, "resume SS port %d finished\n", port_id); |
0200b9f7 | 2005 | complete(&bus_state->u3exit_done[hcd_portnum]); |
6cbcf596 | 2006 | /* We've just brought the device into U0/1/2 through either the |
4ee823b8 SS |
2007 | * Resume state after a device remote wakeup, or through the |
2008 | * U3Exit state after a host-initiated resume. If it's a device | |
2009 | * initiated remote wake, don't pass up the link state change, | |
2010 | * so the roothub behavior is consistent with external | |
2011 | * USB 3.0 hub behavior. | |
2012 | */ | |
74e6ad58 | 2013 | slot_id = xhci_find_slot_id_by_port(hcd, xhci, hcd_portnum + 1); |
d93814cf SS |
2014 | if (slot_id && xhci->devs[slot_id]) |
2015 | xhci_ring_device(xhci, slot_id); | |
74e6ad58 | 2016 | if (bus_state->port_remote_wakeup & (1 << hcd_portnum)) { |
eaefcf24 | 2017 | xhci_test_and_clear_bit(xhci, port, PORT_PLC); |
4ee823b8 | 2018 | usb_wakeup_notification(hcd->self.root_hub, |
74e6ad58 | 2019 | hcd_portnum + 1); |
4ee823b8 SS |
2020 | bogus_port_status = true; |
2021 | goto cleanup; | |
2022 | } | |
d93814cf | 2023 | } |
56192531 | 2024 | |
8b3d4570 SS |
2025 | /* |
2026 | * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or | |
2027 | * RExit to a disconnect state). If so, let the the driver know it's | |
2028 | * out of the RExit state. | |
2029 | */ | |
958c0bd8 | 2030 | if (!DEV_SUPERSPEED_ANY(portsc) && hcd->speed < HCD_USB3 && |
74e6ad58 | 2031 | test_and_clear_bit(hcd_portnum, |
8b3d4570 | 2032 | &bus_state->rexit_ports)) { |
74e6ad58 | 2033 | complete(&bus_state->rexit_done[hcd_portnum]); |
8b3d4570 SS |
2034 | bogus_port_status = true; |
2035 | goto cleanup; | |
2036 | } | |
2037 | ||
11644a76 | 2038 | if (hcd->speed < HCD_USB3) { |
eaefcf24 | 2039 | xhci_test_and_clear_bit(xhci, port, PORT_PLC); |
11644a76 CG |
2040 | if ((xhci->quirks & XHCI_RESET_PLL_ON_DISCONNECT) && |
2041 | (portsc & PORT_CSC) && !(portsc & PORT_CONNECT)) | |
2042 | xhci_cavium_reset_phy_quirk(xhci); | |
2043 | } | |
6fd45621 | 2044 | |
56192531 | 2045 | cleanup: |
0f2a7930 | 2046 | /* Update event ring dequeue pointer before dropping the lock */ |
3b72fca0 | 2047 | inc_deq(xhci, xhci->event_ring); |
0f2a7930 | 2048 | |
386139d7 SS |
2049 | /* Don't make the USB core poll the roothub if we got a bad port status |
2050 | * change event. Besides, at that point we can't tell which roothub | |
2051 | * (USB 2.0 or USB 3.0) to kick. | |
2052 | */ | |
2053 | if (bogus_port_status) | |
2054 | return; | |
2055 | ||
c52804a4 SS |
2056 | /* |
2057 | * xHCI port-status-change events occur when the "or" of all the | |
2058 | * status-change bits in the portsc register changes from 0 to 1. | |
2059 | * New status changes won't cause an event if any other change | |
2060 | * bits are still set. When an event occurs, switch over to | |
2061 | * polling to avoid losing status changes. | |
2062 | */ | |
669bc5a1 MN |
2063 | xhci_dbg(xhci, "%s: starting usb%d port polling.\n", |
2064 | __func__, hcd->self.busnum); | |
c52804a4 | 2065 | set_bit(HCD_FLAG_POLL_RH, &hcd->flags); |
0f2a7930 SS |
2066 | spin_unlock(&xhci->lock); |
2067 | /* Pass this up to the core */ | |
f6ff0ac8 | 2068 | usb_hcd_poll_rh_status(hcd); |
0f2a7930 SS |
2069 | spin_lock(&xhci->lock); |
2070 | } | |
2071 | ||
d0e96f5a SS |
2072 | /* |
2073 | * This TD is defined by the TRBs starting at start_trb in start_seg and ending | |
2074 | * at end_trb, which may be in another segment. If the suspect DMA address is a | |
2075 | * TRB in this TD, this function returns that TRB's segment. Otherwise it | |
2076 | * returns 0. | |
2077 | */ | |
cffb9be8 HG |
2078 | struct xhci_segment *trb_in_td(struct xhci_hcd *xhci, |
2079 | struct xhci_segment *start_seg, | |
d0e96f5a SS |
2080 | union xhci_trb *start_trb, |
2081 | union xhci_trb *end_trb, | |
cffb9be8 HG |
2082 | dma_addr_t suspect_dma, |
2083 | bool debug) | |
d0e96f5a SS |
2084 | { |
2085 | dma_addr_t start_dma; | |
2086 | dma_addr_t end_seg_dma; | |
2087 | dma_addr_t end_trb_dma; | |
2088 | struct xhci_segment *cur_seg; | |
2089 | ||
23e3be11 | 2090 | start_dma = xhci_trb_virt_to_dma(start_seg, start_trb); |
d0e96f5a SS |
2091 | cur_seg = start_seg; |
2092 | ||
2093 | do { | |
2fa88daa | 2094 | if (start_dma == 0) |
326b4810 | 2095 | return NULL; |
ae636747 | 2096 | /* We may get an event for a Link TRB in the middle of a TD */ |
23e3be11 | 2097 | end_seg_dma = xhci_trb_virt_to_dma(cur_seg, |
2fa88daa | 2098 | &cur_seg->trbs[TRBS_PER_SEGMENT - 1]); |
d0e96f5a | 2099 | /* If the end TRB isn't in this segment, this is set to 0 */ |
23e3be11 | 2100 | end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb); |
d0e96f5a | 2101 | |
cffb9be8 HG |
2102 | if (debug) |
2103 | xhci_warn(xhci, | |
2104 | "Looking for event-dma %016llx trb-start %016llx trb-end %016llx seg-start %016llx seg-end %016llx\n", | |
2105 | (unsigned long long)suspect_dma, | |
2106 | (unsigned long long)start_dma, | |
2107 | (unsigned long long)end_trb_dma, | |
2108 | (unsigned long long)cur_seg->dma, | |
2109 | (unsigned long long)end_seg_dma); | |
2110 | ||
d0e96f5a SS |
2111 | if (end_trb_dma > 0) { |
2112 | /* The end TRB is in this segment, so suspect should be here */ | |
2113 | if (start_dma <= end_trb_dma) { | |
2114 | if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma) | |
2115 | return cur_seg; | |
2116 | } else { | |
2117 | /* Case for one segment with | |
2118 | * a TD wrapped around to the top | |
2119 | */ | |
2120 | if ((suspect_dma >= start_dma && | |
2121 | suspect_dma <= end_seg_dma) || | |
2122 | (suspect_dma >= cur_seg->dma && | |
2123 | suspect_dma <= end_trb_dma)) | |
2124 | return cur_seg; | |
2125 | } | |
326b4810 | 2126 | return NULL; |
d0e96f5a SS |
2127 | } else { |
2128 | /* Might still be somewhere in this segment */ | |
2129 | if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma) | |
2130 | return cur_seg; | |
2131 | } | |
2132 | cur_seg = cur_seg->next; | |
23e3be11 | 2133 | start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]); |
2fa88daa | 2134 | } while (cur_seg != start_seg); |
d0e96f5a | 2135 | |
326b4810 | 2136 | return NULL; |
d0e96f5a SS |
2137 | } |
2138 | ||
ef513be0 JL |
2139 | static void xhci_clear_hub_tt_buffer(struct xhci_hcd *xhci, struct xhci_td *td, |
2140 | struct xhci_virt_ep *ep) | |
2141 | { | |
2142 | /* | |
2143 | * As part of low/full-speed endpoint-halt processing | |
2144 | * we must clear the TT buffer (USB 2.0 specification 11.17.5). | |
2145 | */ | |
2146 | if (td->urb->dev->tt && !usb_pipeint(td->urb->pipe) && | |
2147 | (td->urb->dev->tt->hub != xhci_to_hcd(xhci)->self.root_hub) && | |
2148 | !(ep->ep_state & EP_CLEARING_TT)) { | |
2149 | ep->ep_state |= EP_CLEARING_TT; | |
2150 | td->urb->ep->hcpriv = td->urb->dev; | |
2151 | if (usb_hub_clear_tt_buffer(td->urb)) | |
2152 | ep->ep_state &= ~EP_CLEARING_TT; | |
2153 | } | |
2154 | } | |
2155 | ||
bcef3fd5 SS |
2156 | /* Check if an error has halted the endpoint ring. The class driver will |
2157 | * cleanup the halt for a non-default control endpoint if we indicate a stall. | |
2158 | * However, a babble and other errors also halt the endpoint ring, and the class | |
2159 | * driver won't clear the halt in that case, so we need to issue a Set Transfer | |
2160 | * Ring Dequeue Pointer command manually. | |
2161 | */ | |
2162 | static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci, | |
2163 | struct xhci_ep_ctx *ep_ctx, | |
2164 | unsigned int trb_comp_code) | |
2165 | { | |
2166 | /* TRB completion codes that may require a manual halt cleanup */ | |
0b7c105a FB |
2167 | if (trb_comp_code == COMP_USB_TRANSACTION_ERROR || |
2168 | trb_comp_code == COMP_BABBLE_DETECTED_ERROR || | |
2169 | trb_comp_code == COMP_SPLIT_TRANSACTION_ERROR) | |
d4fc8bf5 | 2170 | /* The 0.95 spec says a babbling control endpoint |
bcef3fd5 SS |
2171 | * is not halted. The 0.96 spec says it is. Some HW |
2172 | * claims to be 0.95 compliant, but it halts the control | |
2173 | * endpoint anyway. Check if a babble halted the | |
2174 | * endpoint. | |
2175 | */ | |
5071e6b2 | 2176 | if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_HALTED) |
bcef3fd5 SS |
2177 | return 1; |
2178 | ||
2179 | return 0; | |
2180 | } | |
2181 | ||
b45b5069 SS |
2182 | int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code) |
2183 | { | |
2184 | if (trb_comp_code >= 224 && trb_comp_code <= 255) { | |
2185 | /* Vendor defined "informational" completion code, | |
2186 | * treat as not-an-error. | |
2187 | */ | |
2188 | xhci_dbg(xhci, "Vendor defined info completion code %u\n", | |
2189 | trb_comp_code); | |
2190 | xhci_dbg(xhci, "Treating code as success.\n"); | |
2191 | return 1; | |
2192 | } | |
2193 | return 0; | |
2194 | } | |
2195 | ||
e9fcb077 MN |
2196 | static int finish_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep, |
2197 | struct xhci_ring *ep_ring, struct xhci_td *td, | |
2198 | u32 trb_comp_code) | |
4422da61 | 2199 | { |
4422da61 | 2200 | struct xhci_ep_ctx *ep_ctx; |
4422da61 | 2201 | |
ab58f3bb | 2202 | ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep->ep_index); |
4422da61 | 2203 | |
3c648d3d MN |
2204 | switch (trb_comp_code) { |
2205 | case COMP_STOPPED_LENGTH_INVALID: | |
2206 | case COMP_STOPPED_SHORT_PACKET: | |
2207 | case COMP_STOPPED: | |
2208 | /* | |
2209 | * The "Stop Endpoint" completion will take care of any | |
2210 | * stopped TDs. A stopped TD may be restarted, so don't update | |
4422da61 AX |
2211 | * the ring dequeue pointer or take this TD off any lists yet. |
2212 | */ | |
4422da61 | 2213 | return 0; |
3c648d3d MN |
2214 | case COMP_USB_TRANSACTION_ERROR: |
2215 | case COMP_BABBLE_DETECTED_ERROR: | |
2216 | case COMP_SPLIT_TRANSACTION_ERROR: | |
2217 | /* | |
2218 | * If endpoint context state is not halted we might be | |
2219 | * racing with a reset endpoint command issued by a unsuccessful | |
2220 | * stop endpoint completion (context error). In that case the | |
2221 | * td should be on the cancelled list, and EP_HALTED flag set. | |
2222 | * | |
2223 | * Or then it's not halted due to the 0.95 spec stating that a | |
2224 | * babbling control endpoint should not halt. The 0.96 spec | |
2225 | * again says it should. Some HW claims to be 0.95 compliant, | |
2226 | * but it halts the control endpoint anyway. | |
2227 | */ | |
2228 | if (GET_EP_CTX_STATE(ep_ctx) != EP_STATE_HALTED) { | |
2229 | /* | |
2230 | * If EP_HALTED is set and TD is on the cancelled list | |
2231 | * the TD and dequeue pointer will be handled by reset | |
2232 | * ep command completion | |
2233 | */ | |
2234 | if ((ep->ep_state & EP_HALTED) && | |
2235 | !list_empty(&td->cancelled_td_list)) { | |
2236 | xhci_dbg(xhci, "Already resolving halted ep for 0x%llx\n", | |
2237 | (unsigned long long)xhci_trb_virt_to_dma( | |
2238 | td->start_seg, td->first_trb)); | |
2239 | return 0; | |
2240 | } | |
2241 | /* endpoint not halted, don't reset it */ | |
2242 | break; | |
2243 | } | |
2244 | /* Almost same procedure as for STALL_ERROR below */ | |
2245 | xhci_clear_hub_tt_buffer(xhci, td, ep); | |
2246 | xhci_handle_halted_endpoint(xhci, ep, ep_ring->stream_id, td, | |
2247 | EP_HARD_RESET); | |
2248 | return 0; | |
2249 | case COMP_STALL_ERROR: | |
8f97250c MN |
2250 | /* |
2251 | * xhci internal endpoint state will go to a "halt" state for | |
2252 | * any stall, including default control pipe protocol stall. | |
2253 | * To clear the host side halt we need to issue a reset endpoint | |
2254 | * command, followed by a set dequeue command to move past the | |
2255 | * TD. | |
2256 | * Class drivers clear the device side halt from a functional | |
2257 | * stall later. Hub TT buffer should only be cleared for FS/LS | |
2258 | * devices behind HS hubs for functional stalls. | |
69defe04 | 2259 | */ |
3c648d3d | 2260 | if (ep->ep_index != 0) |
8f97250c | 2261 | xhci_clear_hub_tt_buffer(xhci, td, ep); |
7c6c334e MN |
2262 | |
2263 | xhci_handle_halted_endpoint(xhci, ep, ep_ring->stream_id, td, | |
674f8438 MN |
2264 | EP_HARD_RESET); |
2265 | ||
2266 | return 0; /* xhci_handle_halted_endpoint marked td cancelled */ | |
3c648d3d MN |
2267 | default: |
2268 | break; | |
69defe04 | 2269 | } |
4422da61 | 2270 | |
3c648d3d MN |
2271 | /* Update ring dequeue pointer */ |
2272 | ep_ring->dequeue = td->last_trb; | |
2273 | ep_ring->deq_seg = td->last_trb_seg; | |
2274 | ep_ring->num_trbs_free += td->num_trbs - 1; | |
2275 | inc_deq(xhci, ep_ring); | |
2276 | ||
a6ccd1fd | 2277 | return xhci_td_cleanup(xhci, td, ep_ring, td->status); |
4422da61 AX |
2278 | } |
2279 | ||
30a65b45 MN |
2280 | /* sum trb lengths from ring dequeue up to stop_trb, _excluding_ stop_trb */ |
2281 | static int sum_trb_lengths(struct xhci_hcd *xhci, struct xhci_ring *ring, | |
2282 | union xhci_trb *stop_trb) | |
2283 | { | |
2284 | u32 sum; | |
2285 | union xhci_trb *trb = ring->dequeue; | |
2286 | struct xhci_segment *seg = ring->deq_seg; | |
2287 | ||
2288 | for (sum = 0; trb != stop_trb; next_trb(xhci, ring, &seg, &trb)) { | |
2289 | if (!trb_is_noop(trb) && !trb_is_link(trb)) | |
2290 | sum += TRB_LEN(le32_to_cpu(trb->generic.field[2])); | |
2291 | } | |
2292 | return sum; | |
2293 | } | |
2294 | ||
8af56be1 AX |
2295 | /* |
2296 | * Process control tds, update urb status and actual_length. | |
2297 | */ | |
e9fcb077 MN |
2298 | static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep, |
2299 | struct xhci_ring *ep_ring, struct xhci_td *td, | |
2300 | union xhci_trb *ep_trb, struct xhci_transfer_event *event) | |
8af56be1 | 2301 | { |
8af56be1 AX |
2302 | struct xhci_ep_ctx *ep_ctx; |
2303 | u32 trb_comp_code; | |
0b6c324c | 2304 | u32 remaining, requested; |
29fc1aa4 | 2305 | u32 trb_type; |
8af56be1 | 2306 | |
29fc1aa4 | 2307 | trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(ep_trb->generic.field[3])); |
ab58f3bb | 2308 | ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep->ep_index); |
28ccd296 | 2309 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); |
0b6c324c MN |
2310 | requested = td->urb->transfer_buffer_length; |
2311 | remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); | |
2312 | ||
8af56be1 AX |
2313 | switch (trb_comp_code) { |
2314 | case COMP_SUCCESS: | |
29fc1aa4 | 2315 | if (trb_type != TRB_STATUS) { |
0b6c324c | 2316 | xhci_warn(xhci, "WARN: Success on ctrl %s TRB without IOC set?\n", |
29fc1aa4 | 2317 | (trb_type == TRB_DATA) ? "data" : "setup"); |
a6ccd1fd | 2318 | td->status = -ESHUTDOWN; |
0b6c324c | 2319 | break; |
8af56be1 | 2320 | } |
a6ccd1fd | 2321 | td->status = 0; |
8af56be1 | 2322 | break; |
0b7c105a | 2323 | case COMP_SHORT_PACKET: |
a6ccd1fd | 2324 | td->status = 0; |
8af56be1 | 2325 | break; |
0b7c105a | 2326 | case COMP_STOPPED_SHORT_PACKET: |
29fc1aa4 | 2327 | if (trb_type == TRB_DATA || trb_type == TRB_NORMAL) |
0b6c324c | 2328 | td->urb->actual_length = remaining; |
40a3b775 | 2329 | else |
0b6c324c MN |
2330 | xhci_warn(xhci, "WARN: Stopped Short Packet on ctrl setup or status TRB\n"); |
2331 | goto finish_td; | |
0b7c105a | 2332 | case COMP_STOPPED: |
29fc1aa4 FB |
2333 | switch (trb_type) { |
2334 | case TRB_SETUP: | |
2335 | td->urb->actual_length = 0; | |
2336 | goto finish_td; | |
2337 | case TRB_DATA: | |
2338 | case TRB_NORMAL: | |
0b6c324c | 2339 | td->urb->actual_length = requested - remaining; |
29fc1aa4 | 2340 | goto finish_td; |
0ab2881a MN |
2341 | case TRB_STATUS: |
2342 | td->urb->actual_length = requested; | |
2343 | goto finish_td; | |
29fc1aa4 FB |
2344 | default: |
2345 | xhci_warn(xhci, "WARN: unexpected TRB Type %d\n", | |
2346 | trb_type); | |
2347 | goto finish_td; | |
2348 | } | |
0b7c105a | 2349 | case COMP_STOPPED_LENGTH_INVALID: |
0b6c324c | 2350 | goto finish_td; |
8af56be1 AX |
2351 | default: |
2352 | if (!xhci_requires_manual_halt_cleanup(xhci, | |
0b6c324c | 2353 | ep_ctx, trb_comp_code)) |
8af56be1 | 2354 | break; |
0b6c324c | 2355 | xhci_dbg(xhci, "TRB error %u, halted endpoint index = %u\n", |
ab58f3bb | 2356 | trb_comp_code, ep->ep_index); |
df561f66 | 2357 | fallthrough; |
0b7c105a | 2358 | case COMP_STALL_ERROR: |
8af56be1 | 2359 | /* Did we transfer part of the data (middle) phase? */ |
29fc1aa4 | 2360 | if (trb_type == TRB_DATA || trb_type == TRB_NORMAL) |
0b6c324c | 2361 | td->urb->actual_length = requested - remaining; |
22ae47e6 | 2362 | else if (!td->urb_length_set) |
8af56be1 | 2363 | td->urb->actual_length = 0; |
0b6c324c | 2364 | goto finish_td; |
8af56be1 | 2365 | } |
0b6c324c MN |
2366 | |
2367 | /* stopped at setup stage, no data transferred */ | |
29fc1aa4 | 2368 | if (trb_type == TRB_SETUP) |
0b6c324c MN |
2369 | goto finish_td; |
2370 | ||
8af56be1 | 2371 | /* |
0b6c324c MN |
2372 | * if on data stage then update the actual_length of the URB and flag it |
2373 | * as set, so it won't be overwritten in the event for the last TRB. | |
8af56be1 | 2374 | */ |
29fc1aa4 FB |
2375 | if (trb_type == TRB_DATA || |
2376 | trb_type == TRB_NORMAL) { | |
0b6c324c MN |
2377 | td->urb_length_set = true; |
2378 | td->urb->actual_length = requested - remaining; | |
2379 | xhci_dbg(xhci, "Waiting for status stage event\n"); | |
2380 | return 0; | |
8af56be1 AX |
2381 | } |
2382 | ||
0b6c324c MN |
2383 | /* at status stage */ |
2384 | if (!td->urb_length_set) | |
2385 | td->urb->actual_length = requested; | |
2386 | ||
2387 | finish_td: | |
e9fcb077 | 2388 | return finish_td(xhci, ep, ep_ring, td, trb_comp_code); |
8af56be1 AX |
2389 | } |
2390 | ||
04e51901 AX |
2391 | /* |
2392 | * Process isochronous tds, update urb packet status and actual_length. | |
2393 | */ | |
e9fcb077 MN |
2394 | static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep, |
2395 | struct xhci_ring *ep_ring, struct xhci_td *td, | |
2396 | union xhci_trb *ep_trb, struct xhci_transfer_event *event) | |
04e51901 | 2397 | { |
04e51901 AX |
2398 | struct urb_priv *urb_priv; |
2399 | int idx; | |
926008c9 | 2400 | struct usb_iso_packet_descriptor *frame; |
04e51901 | 2401 | u32 trb_comp_code; |
36da3a1d MN |
2402 | bool sum_trbs_for_length = false; |
2403 | u32 remaining, requested, ep_trb_len; | |
2404 | int short_framestatus; | |
04e51901 | 2405 | |
28ccd296 | 2406 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); |
04e51901 | 2407 | urb_priv = td->urb->hcpriv; |
9ef7fbbb | 2408 | idx = urb_priv->num_tds_done; |
926008c9 | 2409 | frame = &td->urb->iso_frame_desc[idx]; |
36da3a1d MN |
2410 | requested = frame->length; |
2411 | remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); | |
2412 | ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2])); | |
2413 | short_framestatus = td->urb->transfer_flags & URB_SHORT_NOT_OK ? | |
2414 | -EREMOTEIO : 0; | |
04e51901 | 2415 | |
926008c9 DT |
2416 | /* handle completion code */ |
2417 | switch (trb_comp_code) { | |
2418 | case COMP_SUCCESS: | |
36da3a1d MN |
2419 | if (remaining) { |
2420 | frame->status = short_framestatus; | |
2421 | if (xhci->quirks & XHCI_TRUST_TX_LENGTH) | |
2422 | sum_trbs_for_length = true; | |
1530bbc6 SS |
2423 | break; |
2424 | } | |
36da3a1d MN |
2425 | frame->status = 0; |
2426 | break; | |
0b7c105a | 2427 | case COMP_SHORT_PACKET: |
36da3a1d MN |
2428 | frame->status = short_framestatus; |
2429 | sum_trbs_for_length = true; | |
926008c9 | 2430 | break; |
0b7c105a | 2431 | case COMP_BANDWIDTH_OVERRUN_ERROR: |
926008c9 | 2432 | frame->status = -ECOMM; |
926008c9 | 2433 | break; |
0b7c105a FB |
2434 | case COMP_ISOCH_BUFFER_OVERRUN: |
2435 | case COMP_BABBLE_DETECTED_ERROR: | |
926008c9 | 2436 | frame->status = -EOVERFLOW; |
926008c9 | 2437 | break; |
0b7c105a FB |
2438 | case COMP_INCOMPATIBLE_DEVICE_ERROR: |
2439 | case COMP_STALL_ERROR: | |
d104d015 | 2440 | frame->status = -EPROTO; |
d104d015 | 2441 | break; |
0b7c105a | 2442 | case COMP_USB_TRANSACTION_ERROR: |
926008c9 | 2443 | frame->status = -EPROTO; |
f97c08ae | 2444 | if (ep_trb != td->last_trb) |
d104d015 | 2445 | return 0; |
926008c9 | 2446 | break; |
0b7c105a | 2447 | case COMP_STOPPED: |
36da3a1d MN |
2448 | sum_trbs_for_length = true; |
2449 | break; | |
0b7c105a | 2450 | case COMP_STOPPED_SHORT_PACKET: |
36da3a1d MN |
2451 | /* field normally containing residue now contains tranferred */ |
2452 | frame->status = short_framestatus; | |
2453 | requested = remaining; | |
2454 | break; | |
0b7c105a | 2455 | case COMP_STOPPED_LENGTH_INVALID: |
36da3a1d MN |
2456 | requested = 0; |
2457 | remaining = 0; | |
926008c9 DT |
2458 | break; |
2459 | default: | |
36da3a1d | 2460 | sum_trbs_for_length = true; |
926008c9 DT |
2461 | frame->status = -1; |
2462 | break; | |
04e51901 AX |
2463 | } |
2464 | ||
36da3a1d | 2465 | if (sum_trbs_for_length) |
d4dff804 | 2466 | frame->actual_length = sum_trb_lengths(xhci, ep->ring, ep_trb) + |
36da3a1d MN |
2467 | ep_trb_len - remaining; |
2468 | else | |
2469 | frame->actual_length = requested; | |
04e51901 | 2470 | |
36da3a1d | 2471 | td->urb->actual_length += frame->actual_length; |
04e51901 | 2472 | |
e9fcb077 | 2473 | return finish_td(xhci, ep, ep_ring, td, trb_comp_code); |
04e51901 AX |
2474 | } |
2475 | ||
926008c9 | 2476 | static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td, |
a6ccd1fd | 2477 | struct xhci_virt_ep *ep, int status) |
926008c9 | 2478 | { |
926008c9 DT |
2479 | struct urb_priv *urb_priv; |
2480 | struct usb_iso_packet_descriptor *frame; | |
2481 | int idx; | |
2482 | ||
926008c9 | 2483 | urb_priv = td->urb->hcpriv; |
9ef7fbbb | 2484 | idx = urb_priv->num_tds_done; |
926008c9 DT |
2485 | frame = &td->urb->iso_frame_desc[idx]; |
2486 | ||
b3df3f9c | 2487 | /* The transfer is partly done. */ |
926008c9 DT |
2488 | frame->status = -EXDEV; |
2489 | ||
2490 | /* calc actual length */ | |
2491 | frame->actual_length = 0; | |
2492 | ||
2493 | /* Update ring dequeue pointer */ | |
55f6153d MN |
2494 | ep->ring->dequeue = td->last_trb; |
2495 | ep->ring->deq_seg = td->last_trb_seg; | |
2496 | ep->ring->num_trbs_free += td->num_trbs - 1; | |
d4dff804 | 2497 | inc_deq(xhci, ep->ring); |
926008c9 | 2498 | |
d4dff804 | 2499 | return xhci_td_cleanup(xhci, td, ep->ring, status); |
926008c9 DT |
2500 | } |
2501 | ||
22405ed2 AX |
2502 | /* |
2503 | * Process bulk and interrupt tds, update urb status and actual_length. | |
2504 | */ | |
e9fcb077 MN |
2505 | static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep, |
2506 | struct xhci_ring *ep_ring, struct xhci_td *td, | |
2507 | union xhci_trb *ep_trb, struct xhci_transfer_event *event) | |
22405ed2 | 2508 | { |
f8f80be5 | 2509 | struct xhci_slot_ctx *slot_ctx; |
22405ed2 | 2510 | u32 trb_comp_code; |
f97c08ae | 2511 | u32 remaining, requested, ep_trb_len; |
22405ed2 | 2512 | |
ab58f3bb | 2513 | slot_ctx = xhci_get_slot_ctx(xhci, ep->vdev->out_ctx); |
28ccd296 | 2514 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); |
30a65b45 | 2515 | remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); |
f97c08ae | 2516 | ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2])); |
30a65b45 | 2517 | requested = td->urb->transfer_buffer_length; |
22405ed2 AX |
2518 | |
2519 | switch (trb_comp_code) { | |
2520 | case COMP_SUCCESS: | |
f8f80be5 | 2521 | ep_ring->err_count = 0; |
30a65b45 | 2522 | /* handle success with untransferred data as short packet */ |
f97c08ae | 2523 | if (ep_trb != td->last_trb || remaining) { |
52ab8685 | 2524 | xhci_warn(xhci, "WARN Successful completion on short TX\n"); |
30a65b45 MN |
2525 | xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n", |
2526 | td->urb->ep->desc.bEndpointAddress, | |
2527 | requested, remaining); | |
22405ed2 | 2528 | } |
a6ccd1fd | 2529 | td->status = 0; |
22405ed2 | 2530 | break; |
0b7c105a | 2531 | case COMP_SHORT_PACKET: |
30a65b45 MN |
2532 | xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n", |
2533 | td->urb->ep->desc.bEndpointAddress, | |
2534 | requested, remaining); | |
a6ccd1fd | 2535 | td->status = 0; |
22405ed2 | 2536 | break; |
0b7c105a | 2537 | case COMP_STOPPED_SHORT_PACKET: |
30a65b45 MN |
2538 | td->urb->actual_length = remaining; |
2539 | goto finish_td; | |
0b7c105a | 2540 | case COMP_STOPPED_LENGTH_INVALID: |
30a65b45 | 2541 | /* stopped on ep trb with invalid length, exclude it */ |
f97c08ae | 2542 | ep_trb_len = 0; |
30a65b45 MN |
2543 | remaining = 0; |
2544 | break; | |
f8f80be5 | 2545 | case COMP_USB_TRANSACTION_ERROR: |
a4a251f8 SG |
2546 | if (xhci->quirks & XHCI_NO_SOFT_RETRY || |
2547 | (ep_ring->err_count++ > MAX_SOFT_RETRY) || | |
f8f80be5 MN |
2548 | le32_to_cpu(slot_ctx->tt_info) & TT_SLOT) |
2549 | break; | |
a6ccd1fd MN |
2550 | |
2551 | td->status = 0; | |
7c6c334e MN |
2552 | |
2553 | xhci_handle_halted_endpoint(xhci, ep, ep_ring->stream_id, td, | |
2554 | EP_SOFT_RESET); | |
f8f80be5 | 2555 | return 0; |
22405ed2 | 2556 | default: |
30a65b45 | 2557 | /* do nothing */ |
22405ed2 AX |
2558 | break; |
2559 | } | |
40a3b775 | 2560 | |
f97c08ae | 2561 | if (ep_trb == td->last_trb) |
30a65b45 MN |
2562 | td->urb->actual_length = requested - remaining; |
2563 | else | |
2564 | td->urb->actual_length = | |
f97c08ae MN |
2565 | sum_trb_lengths(xhci, ep_ring, ep_trb) + |
2566 | ep_trb_len - remaining; | |
30a65b45 MN |
2567 | finish_td: |
2568 | if (remaining > requested) { | |
2569 | xhci_warn(xhci, "bad transfer trb length %d in event trb\n", | |
2570 | remaining); | |
22405ed2 | 2571 | td->urb->actual_length = 0; |
22405ed2 | 2572 | } |
e9fcb077 MN |
2573 | |
2574 | return finish_td(xhci, ep, ep_ring, td, trb_comp_code); | |
22405ed2 AX |
2575 | } |
2576 | ||
d0e96f5a SS |
2577 | /* |
2578 | * If this function returns an error condition, it means it got a Transfer | |
2579 | * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address. | |
2580 | * At this point, the host controller is probably hosed and should be reset. | |
2581 | */ | |
2582 | static int handle_tx_event(struct xhci_hcd *xhci, | |
2583 | struct xhci_transfer_event *event) | |
2584 | { | |
63a0d9ab | 2585 | struct xhci_virt_ep *ep; |
d0e96f5a | 2586 | struct xhci_ring *ep_ring; |
82d1009f | 2587 | unsigned int slot_id; |
d0e96f5a | 2588 | int ep_index; |
326b4810 | 2589 | struct xhci_td *td = NULL; |
f97c08ae MN |
2590 | dma_addr_t ep_trb_dma; |
2591 | struct xhci_segment *ep_seg; | |
2592 | union xhci_trb *ep_trb; | |
d0e96f5a | 2593 | int status = -EINPROGRESS; |
d115b048 | 2594 | struct xhci_ep_ctx *ep_ctx; |
c2d7b49f | 2595 | struct list_head *tmp; |
66d1eebc | 2596 | u32 trb_comp_code; |
c2d7b49f | 2597 | int td_num = 0; |
3b4739b8 | 2598 | bool handling_skipped_tds = false; |
d0e96f5a | 2599 | |
28ccd296 | 2600 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
b3368382 MN |
2601 | ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1; |
2602 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); | |
2603 | ep_trb_dma = le64_to_cpu(event->buffer); | |
2604 | ||
b1adc42d MN |
2605 | ep = xhci_get_virt_ep(xhci, slot_id, ep_index); |
2606 | if (!ep) { | |
2607 | xhci_err(xhci, "ERROR Invalid Transfer event\n"); | |
b3368382 MN |
2608 | goto err_out; |
2609 | } | |
2610 | ||
b3368382 | 2611 | ep_ring = xhci_dma_to_transfer_ring(ep, ep_trb_dma); |
b1adc42d | 2612 | ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index); |
b3368382 | 2613 | |
ade2e3a1 | 2614 | if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) { |
b7f769ae | 2615 | xhci_err(xhci, |
ade2e3a1 | 2616 | "ERROR Transfer event for disabled endpoint slot %u ep %u\n", |
b7f769ae | 2617 | slot_id, ep_index); |
b3368382 | 2618 | goto err_out; |
d0e96f5a SS |
2619 | } |
2620 | ||
ade2e3a1 MN |
2621 | /* Some transfer events don't always point to a trb, see xhci 4.17.4 */ |
2622 | if (!ep_ring) { | |
2623 | switch (trb_comp_code) { | |
2624 | case COMP_STALL_ERROR: | |
2625 | case COMP_USB_TRANSACTION_ERROR: | |
2626 | case COMP_INVALID_STREAM_TYPE_ERROR: | |
2627 | case COMP_INVALID_STREAM_ID_ERROR: | |
7c6c334e MN |
2628 | xhci_handle_halted_endpoint(xhci, ep, 0, NULL, |
2629 | EP_SOFT_RESET); | |
ade2e3a1 MN |
2630 | goto cleanup; |
2631 | case COMP_RING_UNDERRUN: | |
2632 | case COMP_RING_OVERRUN: | |
d9193efb | 2633 | case COMP_STOPPED_LENGTH_INVALID: |
ade2e3a1 MN |
2634 | goto cleanup; |
2635 | default: | |
2636 | xhci_err(xhci, "ERROR Transfer event for unknown stream ring slot %u ep %u\n", | |
2637 | slot_id, ep_index); | |
2638 | goto err_out; | |
2639 | } | |
2640 | } | |
2641 | ||
c2d7b49f AX |
2642 | /* Count current td numbers if ep->skip is set */ |
2643 | if (ep->skip) { | |
2644 | list_for_each(tmp, &ep_ring->td_list) | |
2645 | td_num++; | |
2646 | } | |
2647 | ||
986a92d4 | 2648 | /* Look for common error cases */ |
66d1eebc | 2649 | switch (trb_comp_code) { |
b10de142 SS |
2650 | /* Skip codes that require special handling depending on |
2651 | * transfer type | |
2652 | */ | |
2653 | case COMP_SUCCESS: | |
1c11a172 | 2654 | if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) |
1530bbc6 | 2655 | break; |
7ff11162 MN |
2656 | if (xhci->quirks & XHCI_TRUST_TX_LENGTH || |
2657 | ep_ring->last_td_was_short) | |
0b7c105a | 2658 | trb_comp_code = COMP_SHORT_PACKET; |
1530bbc6 | 2659 | else |
8202ce2e | 2660 | xhci_warn_ratelimited(xhci, |
b7f769ae ZX |
2661 | "WARN Successful completion on short TX for slot %u ep %u: needs XHCI_TRUST_TX_LENGTH quirk?\n", |
2662 | slot_id, ep_index); | |
1d6903a6 | 2663 | break; |
0b7c105a | 2664 | case COMP_SHORT_PACKET: |
b10de142 | 2665 | break; |
b3368382 | 2666 | /* Completion codes for endpoint stopped state */ |
0b7c105a | 2667 | case COMP_STOPPED: |
b7f769ae ZX |
2668 | xhci_dbg(xhci, "Stopped on Transfer TRB for slot %u ep %u\n", |
2669 | slot_id, ep_index); | |
ae636747 | 2670 | break; |
0b7c105a | 2671 | case COMP_STOPPED_LENGTH_INVALID: |
b7f769ae ZX |
2672 | xhci_dbg(xhci, |
2673 | "Stopped on No-op or Link TRB for slot %u ep %u\n", | |
2674 | slot_id, ep_index); | |
ae636747 | 2675 | break; |
0b7c105a | 2676 | case COMP_STOPPED_SHORT_PACKET: |
b7f769ae ZX |
2677 | xhci_dbg(xhci, |
2678 | "Stopped with short packet transfer detected for slot %u ep %u\n", | |
2679 | slot_id, ep_index); | |
40a3b775 | 2680 | break; |
b3368382 | 2681 | /* Completion codes for endpoint halted state */ |
0b7c105a | 2682 | case COMP_STALL_ERROR: |
b7f769ae ZX |
2683 | xhci_dbg(xhci, "Stalled endpoint for slot %u ep %u\n", slot_id, |
2684 | ep_index); | |
b10de142 SS |
2685 | status = -EPIPE; |
2686 | break; | |
0b7c105a | 2687 | case COMP_SPLIT_TRANSACTION_ERROR: |
76eac5d2 MN |
2688 | xhci_dbg(xhci, "Split transaction error for slot %u ep %u\n", |
2689 | slot_id, ep_index); | |
2690 | status = -EPROTO; | |
2691 | break; | |
0b7c105a | 2692 | case COMP_USB_TRANSACTION_ERROR: |
b7f769ae ZX |
2693 | xhci_dbg(xhci, "Transfer error for slot %u ep %u on endpoint\n", |
2694 | slot_id, ep_index); | |
b10de142 SS |
2695 | status = -EPROTO; |
2696 | break; | |
0b7c105a | 2697 | case COMP_BABBLE_DETECTED_ERROR: |
b7f769ae ZX |
2698 | xhci_dbg(xhci, "Babble error for slot %u ep %u on endpoint\n", |
2699 | slot_id, ep_index); | |
4a73143c SS |
2700 | status = -EOVERFLOW; |
2701 | break; | |
b3368382 MN |
2702 | /* Completion codes for endpoint error state */ |
2703 | case COMP_TRB_ERROR: | |
2704 | xhci_warn(xhci, | |
2705 | "WARN: TRB error for slot %u ep %u on endpoint\n", | |
2706 | slot_id, ep_index); | |
2707 | status = -EILSEQ; | |
2708 | break; | |
2709 | /* completion codes not indicating endpoint state change */ | |
0b7c105a | 2710 | case COMP_DATA_BUFFER_ERROR: |
b7f769ae ZX |
2711 | xhci_warn(xhci, |
2712 | "WARN: HC couldn't access mem fast enough for slot %u ep %u\n", | |
2713 | slot_id, ep_index); | |
b10de142 SS |
2714 | status = -ENOSR; |
2715 | break; | |
0b7c105a | 2716 | case COMP_BANDWIDTH_OVERRUN_ERROR: |
b7f769ae ZX |
2717 | xhci_warn(xhci, |
2718 | "WARN: bandwidth overrun event for slot %u ep %u on endpoint\n", | |
2719 | slot_id, ep_index); | |
986a92d4 | 2720 | break; |
0b7c105a | 2721 | case COMP_ISOCH_BUFFER_OVERRUN: |
b7f769ae ZX |
2722 | xhci_warn(xhci, |
2723 | "WARN: buffer overrun event for slot %u ep %u on endpoint", | |
2724 | slot_id, ep_index); | |
986a92d4 | 2725 | break; |
0b7c105a | 2726 | case COMP_RING_UNDERRUN: |
986a92d4 AX |
2727 | /* |
2728 | * When the Isoch ring is empty, the xHC will generate | |
2729 | * a Ring Overrun Event for IN Isoch endpoint or Ring | |
2730 | * Underrun Event for OUT Isoch endpoint. | |
2731 | */ | |
2732 | xhci_dbg(xhci, "underrun event on endpoint\n"); | |
2733 | if (!list_empty(&ep_ring->td_list)) | |
2734 | xhci_dbg(xhci, "Underrun Event for slot %d ep %d " | |
2735 | "still with TDs queued?\n", | |
28ccd296 ME |
2736 | TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), |
2737 | ep_index); | |
986a92d4 | 2738 | goto cleanup; |
0b7c105a | 2739 | case COMP_RING_OVERRUN: |
986a92d4 AX |
2740 | xhci_dbg(xhci, "overrun event on endpoint\n"); |
2741 | if (!list_empty(&ep_ring->td_list)) | |
2742 | xhci_dbg(xhci, "Overrun Event for slot %d ep %d " | |
2743 | "still with TDs queued?\n", | |
28ccd296 ME |
2744 | TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), |
2745 | ep_index); | |
986a92d4 | 2746 | goto cleanup; |
0b7c105a | 2747 | case COMP_MISSED_SERVICE_ERROR: |
d18240db AX |
2748 | /* |
2749 | * When encounter missed service error, one or more isoc tds | |
2750 | * may be missed by xHC. | |
2751 | * Set skip flag of the ep_ring; Complete the missed tds as | |
2752 | * short transfer when process the ep_ring next time. | |
2753 | */ | |
2754 | ep->skip = true; | |
b7f769ae ZX |
2755 | xhci_dbg(xhci, |
2756 | "Miss service interval error for slot %u ep %u, set skip flag\n", | |
2757 | slot_id, ep_index); | |
d18240db | 2758 | goto cleanup; |
0b7c105a | 2759 | case COMP_NO_PING_RESPONSE_ERROR: |
3b4739b8 | 2760 | ep->skip = true; |
b7f769ae ZX |
2761 | xhci_dbg(xhci, |
2762 | "No Ping response error for slot %u ep %u, Skip one Isoc TD\n", | |
2763 | slot_id, ep_index); | |
3b4739b8 | 2764 | goto cleanup; |
b3368382 MN |
2765 | |
2766 | case COMP_INCOMPATIBLE_DEVICE_ERROR: | |
2767 | /* needs disable slot command to recover */ | |
2768 | xhci_warn(xhci, | |
2769 | "WARN: detect an incompatible device for slot %u ep %u", | |
2770 | slot_id, ep_index); | |
2771 | status = -EPROTO; | |
2772 | break; | |
b10de142 | 2773 | default: |
b45b5069 | 2774 | if (xhci_is_vendor_info_code(xhci, trb_comp_code)) { |
5ad6a529 SS |
2775 | status = 0; |
2776 | break; | |
2777 | } | |
b7f769ae ZX |
2778 | xhci_warn(xhci, |
2779 | "ERROR Unknown event condition %u for slot %u ep %u , HC probably busted\n", | |
2780 | trb_comp_code, slot_id, ep_index); | |
986a92d4 AX |
2781 | goto cleanup; |
2782 | } | |
2783 | ||
d18240db AX |
2784 | do { |
2785 | /* This TRB should be in the TD at the head of this ring's | |
2786 | * TD list. | |
2787 | */ | |
2788 | if (list_empty(&ep_ring->td_list)) { | |
a83d6755 | 2789 | /* |
e4ec40ec MN |
2790 | * Don't print wanings if it's due to a stopped endpoint |
2791 | * generating an extra completion event if the device | |
2792 | * was suspended. Or, a event for the last TRB of a | |
2793 | * short TD we already got a short event for. | |
2794 | * The short TD is already removed from the TD list. | |
a83d6755 | 2795 | */ |
e4ec40ec | 2796 | |
0b7c105a | 2797 | if (!(trb_comp_code == COMP_STOPPED || |
e4ec40ec MN |
2798 | trb_comp_code == COMP_STOPPED_LENGTH_INVALID || |
2799 | ep_ring->last_td_was_short)) { | |
a83d6755 SS |
2800 | xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n", |
2801 | TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), | |
2802 | ep_index); | |
a83d6755 | 2803 | } |
d18240db AX |
2804 | if (ep->skip) { |
2805 | ep->skip = false; | |
b7f769ae ZX |
2806 | xhci_dbg(xhci, "td_list is empty while skip flag set. Clear skip flag for slot %u ep %u.\n", |
2807 | slot_id, ep_index); | |
d18240db | 2808 | } |
93ceaa80 MN |
2809 | if (trb_comp_code == COMP_STALL_ERROR || |
2810 | xhci_requires_manual_halt_cleanup(xhci, ep_ctx, | |
2811 | trb_comp_code)) { | |
7c6c334e MN |
2812 | xhci_handle_halted_endpoint(xhci, ep, |
2813 | ep_ring->stream_id, | |
2814 | NULL, | |
2815 | EP_HARD_RESET); | |
93ceaa80 | 2816 | } |
d18240db AX |
2817 | goto cleanup; |
2818 | } | |
986a92d4 | 2819 | |
c2d7b49f AX |
2820 | /* We've skipped all the TDs on the ep ring when ep->skip set */ |
2821 | if (ep->skip && td_num == 0) { | |
2822 | ep->skip = false; | |
b7f769ae ZX |
2823 | xhci_dbg(xhci, "All tds on the ep_ring skipped. Clear skip flag for slot %u ep %u.\n", |
2824 | slot_id, ep_index); | |
c2d7b49f AX |
2825 | goto cleanup; |
2826 | } | |
2827 | ||
04861f83 FB |
2828 | td = list_first_entry(&ep_ring->td_list, struct xhci_td, |
2829 | td_list); | |
c2d7b49f AX |
2830 | if (ep->skip) |
2831 | td_num--; | |
926008c9 | 2832 | |
d18240db | 2833 | /* Is this a TRB in the currently executing TD? */ |
f97c08ae MN |
2834 | ep_seg = trb_in_td(xhci, ep_ring->deq_seg, ep_ring->dequeue, |
2835 | td->last_trb, ep_trb_dma, false); | |
e1cf486d AH |
2836 | |
2837 | /* | |
2838 | * Skip the Force Stopped Event. The event_trb(event_dma) of FSE | |
2839 | * is not in the current TD pointed by ep_ring->dequeue because | |
2840 | * that the hardware dequeue pointer still at the previous TRB | |
2841 | * of the current TD. The previous TRB maybe a Link TD or the | |
2842 | * last TRB of the previous TD. The command completion handle | |
2843 | * will take care the rest. | |
2844 | */ | |
0b7c105a FB |
2845 | if (!ep_seg && (trb_comp_code == COMP_STOPPED || |
2846 | trb_comp_code == COMP_STOPPED_LENGTH_INVALID)) { | |
e1cf486d AH |
2847 | goto cleanup; |
2848 | } | |
2849 | ||
f97c08ae | 2850 | if (!ep_seg) { |
926008c9 DT |
2851 | if (!ep->skip || |
2852 | !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) { | |
ad808333 SS |
2853 | /* Some host controllers give a spurious |
2854 | * successful event after a short transfer. | |
2855 | * Ignore it. | |
2856 | */ | |
ddba5cd0 | 2857 | if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) && |
ad808333 SS |
2858 | ep_ring->last_td_was_short) { |
2859 | ep_ring->last_td_was_short = false; | |
ad808333 SS |
2860 | goto cleanup; |
2861 | } | |
926008c9 DT |
2862 | /* HC is busted, give up! */ |
2863 | xhci_err(xhci, | |
2864 | "ERROR Transfer event TRB DMA ptr not " | |
cffb9be8 HG |
2865 | "part of current TD ep_index %d " |
2866 | "comp_code %u\n", ep_index, | |
2867 | trb_comp_code); | |
2868 | trb_in_td(xhci, ep_ring->deq_seg, | |
2869 | ep_ring->dequeue, td->last_trb, | |
f97c08ae | 2870 | ep_trb_dma, true); |
926008c9 DT |
2871 | return -ESHUTDOWN; |
2872 | } | |
2873 | ||
a6ccd1fd | 2874 | skip_isoc_td(xhci, td, ep, status); |
926008c9 DT |
2875 | goto cleanup; |
2876 | } | |
0b7c105a | 2877 | if (trb_comp_code == COMP_SHORT_PACKET) |
ad808333 SS |
2878 | ep_ring->last_td_was_short = true; |
2879 | else | |
2880 | ep_ring->last_td_was_short = false; | |
926008c9 DT |
2881 | |
2882 | if (ep->skip) { | |
b7f769ae ZX |
2883 | xhci_dbg(xhci, |
2884 | "Found td. Clear skip flag for slot %u ep %u.\n", | |
2885 | slot_id, ep_index); | |
d18240db AX |
2886 | ep->skip = false; |
2887 | } | |
678539cf | 2888 | |
f97c08ae MN |
2889 | ep_trb = &ep_seg->trbs[(ep_trb_dma - ep_seg->dma) / |
2890 | sizeof(*ep_trb)]; | |
a37c3f76 FB |
2891 | |
2892 | trace_xhci_handle_transfer(ep_ring, | |
2893 | (struct xhci_generic_trb *) ep_trb); | |
2894 | ||
926008c9 | 2895 | /* |
810a624b LB |
2896 | * No-op TRB could trigger interrupts in a case where |
2897 | * a URB was killed and a STALL_ERROR happens right | |
2898 | * after the endpoint ring stopped. Reset the halted | |
2899 | * endpoint. Otherwise, the endpoint remains stalled | |
2900 | * indefinitely. | |
926008c9 | 2901 | */ |
a6ccd1fd | 2902 | |
f97c08ae | 2903 | if (trb_is_noop(ep_trb)) { |
810a624b LB |
2904 | if (trb_comp_code == COMP_STALL_ERROR || |
2905 | xhci_requires_manual_halt_cleanup(xhci, ep_ctx, | |
2906 | trb_comp_code)) | |
7c6c334e MN |
2907 | xhci_handle_halted_endpoint(xhci, ep, |
2908 | ep_ring->stream_id, | |
2909 | td, EP_HARD_RESET); | |
926008c9 | 2910 | goto cleanup; |
d18240db | 2911 | } |
4422da61 | 2912 | |
a6ccd1fd MN |
2913 | td->status = status; |
2914 | ||
0c03d89d | 2915 | /* update the urb's actual_length and give back to the core */ |
d18240db | 2916 | if (usb_endpoint_xfer_control(&td->urb->ep->desc)) |
e9fcb077 | 2917 | process_ctrl_td(xhci, ep, ep_ring, td, ep_trb, event); |
04e51901 | 2918 | else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc)) |
e9fcb077 | 2919 | process_isoc_td(xhci, ep, ep_ring, td, ep_trb, event); |
d18240db | 2920 | else |
e9fcb077 | 2921 | process_bulk_intr_td(xhci, ep, ep_ring, td, ep_trb, event); |
d18240db | 2922 | cleanup: |
3b4739b8 | 2923 | handling_skipped_tds = ep->skip && |
0b7c105a FB |
2924 | trb_comp_code != COMP_MISSED_SERVICE_ERROR && |
2925 | trb_comp_code != COMP_NO_PING_RESPONSE_ERROR; | |
3b4739b8 | 2926 | |
d18240db | 2927 | /* |
3b4739b8 MN |
2928 | * Do not update event ring dequeue pointer if we're in a loop |
2929 | * processing missed tds. | |
d18240db | 2930 | */ |
3b4739b8 | 2931 | if (!handling_skipped_tds) |
3b72fca0 | 2932 | inc_deq(xhci, xhci->event_ring); |
d18240db | 2933 | |
d18240db AX |
2934 | /* |
2935 | * If ep->skip is set, it means there are missed tds on the | |
2936 | * endpoint ring need to take care of. | |
2937 | * Process them as short transfer until reach the td pointed by | |
2938 | * the event. | |
2939 | */ | |
3b4739b8 | 2940 | } while (handling_skipped_tds); |
d18240db | 2941 | |
d0e96f5a | 2942 | return 0; |
b3368382 MN |
2943 | |
2944 | err_out: | |
2945 | xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n", | |
2946 | (unsigned long long) xhci_trb_virt_to_dma( | |
2947 | xhci->event_ring->deq_seg, | |
2948 | xhci->event_ring->dequeue), | |
2949 | lower_32_bits(le64_to_cpu(event->buffer)), | |
2950 | upper_32_bits(le64_to_cpu(event->buffer)), | |
2951 | le32_to_cpu(event->transfer_len), | |
2952 | le32_to_cpu(event->flags)); | |
2953 | return -ENODEV; | |
d0e96f5a SS |
2954 | } |
2955 | ||
0f2a7930 SS |
2956 | /* |
2957 | * This function handles all OS-owned events on the event ring. It may drop | |
2958 | * xhci->lock between event processing (e.g. to pass up port status changes). | |
9dee9a21 ME |
2959 | * Returns >0 for "possibly more events to process" (caller should call again), |
2960 | * otherwise 0 if done. In future, <0 returns should indicate error code. | |
0f2a7930 | 2961 | */ |
9dee9a21 | 2962 | static int xhci_handle_event(struct xhci_hcd *xhci) |
7f84eef0 SS |
2963 | { |
2964 | union xhci_trb *event; | |
0f2a7930 | 2965 | int update_ptrs = 1; |
0353810a | 2966 | u32 trb_type; |
d0e96f5a | 2967 | int ret; |
7f84eef0 | 2968 | |
f4c8f03c | 2969 | /* Event ring hasn't been allocated yet. */ |
7f84eef0 | 2970 | if (!xhci->event_ring || !xhci->event_ring->dequeue) { |
f4c8f03c LB |
2971 | xhci_err(xhci, "ERROR event ring not ready\n"); |
2972 | return -ENOMEM; | |
7f84eef0 SS |
2973 | } |
2974 | ||
2975 | event = xhci->event_ring->dequeue; | |
2976 | /* Does the HC or OS own the TRB? */ | |
28ccd296 | 2977 | if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) != |
f4c8f03c | 2978 | xhci->event_ring->cycle_state) |
9dee9a21 | 2979 | return 0; |
7f84eef0 | 2980 | |
a37c3f76 FB |
2981 | trace_xhci_handle_event(xhci->event_ring, &event->generic); |
2982 | ||
92a3da41 ME |
2983 | /* |
2984 | * Barrier between reading the TRB_CYCLE (valid) flag above and any | |
2985 | * speculative reads of the event's flags/data below. | |
2986 | */ | |
2987 | rmb(); | |
0353810a | 2988 | trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->event_cmd.flags)); |
0f2a7930 | 2989 | /* FIXME: Handle more event types. */ |
0353810a MN |
2990 | |
2991 | switch (trb_type) { | |
2992 | case TRB_COMPLETION: | |
7f84eef0 SS |
2993 | handle_cmd_completion(xhci, &event->event_cmd); |
2994 | break; | |
0353810a | 2995 | case TRB_PORT_STATUS: |
0f2a7930 SS |
2996 | handle_port_status(xhci, event); |
2997 | update_ptrs = 0; | |
2998 | break; | |
0353810a | 2999 | case TRB_TRANSFER: |
d0e96f5a | 3000 | ret = handle_tx_event(xhci, &event->trans_event); |
f4c8f03c | 3001 | if (ret >= 0) |
d0e96f5a SS |
3002 | update_ptrs = 0; |
3003 | break; | |
0353810a | 3004 | case TRB_DEV_NOTE: |
623bef9e SS |
3005 | handle_device_notification(xhci, event); |
3006 | break; | |
7f84eef0 | 3007 | default: |
0353810a MN |
3008 | if (trb_type >= TRB_VENDOR_DEFINED_LOW) |
3009 | handle_vendor_event(xhci, event, trb_type); | |
0238634d | 3010 | else |
0353810a | 3011 | xhci_warn(xhci, "ERROR unknown event type %d\n", trb_type); |
7f84eef0 | 3012 | } |
6f5165cf SS |
3013 | /* Any of the above functions may drop and re-acquire the lock, so check |
3014 | * to make sure a watchdog timer didn't mark the host as non-responsive. | |
3015 | */ | |
3016 | if (xhci->xhc_state & XHCI_STATE_DYING) { | |
3017 | xhci_dbg(xhci, "xHCI host dying, returning from " | |
3018 | "event handler.\n"); | |
9dee9a21 | 3019 | return 0; |
6f5165cf | 3020 | } |
7f84eef0 | 3021 | |
c06d68b8 SS |
3022 | if (update_ptrs) |
3023 | /* Update SW event ring dequeue pointer */ | |
3b72fca0 | 3024 | inc_deq(xhci, xhci->event_ring); |
c06d68b8 | 3025 | |
9dee9a21 ME |
3026 | /* Are there more items on the event ring? Caller will call us again to |
3027 | * check. | |
3028 | */ | |
3029 | return 1; | |
7f84eef0 | 3030 | } |
9032cd52 | 3031 | |
dc0ffbea PC |
3032 | /* |
3033 | * Update Event Ring Dequeue Pointer: | |
3034 | * - When all events have finished | |
3035 | * - To avoid "Event Ring Full Error" condition | |
3036 | */ | |
3037 | static void xhci_update_erst_dequeue(struct xhci_hcd *xhci, | |
3038 | union xhci_trb *event_ring_deq) | |
3039 | { | |
3040 | u64 temp_64; | |
3041 | dma_addr_t deq; | |
3042 | ||
3043 | temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); | |
3044 | /* If necessary, update the HW's version of the event ring deq ptr. */ | |
3045 | if (event_ring_deq != xhci->event_ring->dequeue) { | |
3046 | deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg, | |
3047 | xhci->event_ring->dequeue); | |
3048 | if (deq == 0) | |
3049 | xhci_warn(xhci, "WARN something wrong with SW event ring dequeue ptr\n"); | |
3050 | /* | |
3051 | * Per 4.9.4, Software writes to the ERDP register shall | |
3052 | * always advance the Event Ring Dequeue Pointer value. | |
3053 | */ | |
3054 | if ((temp_64 & (u64) ~ERST_PTR_MASK) == | |
3055 | ((u64) deq & (u64) ~ERST_PTR_MASK)) | |
3056 | return; | |
3057 | ||
3058 | /* Update HC event ring dequeue pointer */ | |
3059 | temp_64 &= ERST_PTR_MASK; | |
3060 | temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK); | |
3061 | } | |
3062 | ||
3063 | /* Clear the event handler busy flag (RW1C) */ | |
3064 | temp_64 |= ERST_EHB; | |
3065 | xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue); | |
3066 | } | |
3067 | ||
9032cd52 SS |
3068 | /* |
3069 | * xHCI spec says we can get an interrupt, and if the HC has an error condition, | |
3070 | * we might get bad data out of the event ring. Section 4.10.2.7 has a list of | |
3071 | * indicators of an event TRB error, but we check the status *first* to be safe. | |
3072 | */ | |
3073 | irqreturn_t xhci_irq(struct usb_hcd *hcd) | |
3074 | { | |
3075 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
c06d68b8 | 3076 | union xhci_trb *event_ring_deq; |
76a35293 | 3077 | irqreturn_t ret = IRQ_NONE; |
76a35293 FB |
3078 | u64 temp_64; |
3079 | u32 status; | |
dc0ffbea | 3080 | int event_loop = 0; |
9032cd52 | 3081 | |
5e712172 | 3082 | spin_lock(&xhci->lock); |
9032cd52 | 3083 | /* Check if the xHC generated the interrupt, or the irq is shared */ |
b0ba9720 | 3084 | status = readl(&xhci->op_regs->status); |
d9f11ba9 MN |
3085 | if (status == ~(u32)0) { |
3086 | xhci_hc_died(xhci); | |
76a35293 FB |
3087 | ret = IRQ_HANDLED; |
3088 | goto out; | |
9032cd52 | 3089 | } |
76a35293 FB |
3090 | |
3091 | if (!(status & STS_EINT)) | |
3092 | goto out; | |
3093 | ||
27e0dd4d | 3094 | if (status & STS_FATAL) { |
9032cd52 SS |
3095 | xhci_warn(xhci, "WARNING: Host System Error\n"); |
3096 | xhci_halt(xhci); | |
76a35293 FB |
3097 | ret = IRQ_HANDLED; |
3098 | goto out; | |
9032cd52 SS |
3099 | } |
3100 | ||
bda53145 SS |
3101 | /* |
3102 | * Clear the op reg interrupt status first, | |
3103 | * so we can receive interrupts from other MSI-X interrupters. | |
3104 | * Write 1 to clear the interrupt status. | |
3105 | */ | |
27e0dd4d | 3106 | status |= STS_EINT; |
204b7793 | 3107 | writel(status, &xhci->op_regs->status); |
bda53145 | 3108 | |
6a29beef | 3109 | if (!hcd->msi_enabled) { |
c21599a3 | 3110 | u32 irq_pending; |
b0ba9720 | 3111 | irq_pending = readl(&xhci->ir_set->irq_pending); |
4e833c0b | 3112 | irq_pending |= IMAN_IP; |
204b7793 | 3113 | writel(irq_pending, &xhci->ir_set->irq_pending); |
c21599a3 | 3114 | } |
bda53145 | 3115 | |
27a41a83 GKB |
3116 | if (xhci->xhc_state & XHCI_STATE_DYING || |
3117 | xhci->xhc_state & XHCI_STATE_HALTED) { | |
bda53145 SS |
3118 | xhci_dbg(xhci, "xHCI dying, ignoring interrupt. " |
3119 | "Shouldn't IRQs be disabled?\n"); | |
c06d68b8 SS |
3120 | /* Clear the event handler busy flag (RW1C); |
3121 | * the event ring should be empty. | |
bda53145 | 3122 | */ |
f7b2e403 | 3123 | temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); |
477632df SS |
3124 | xhci_write_64(xhci, temp_64 | ERST_EHB, |
3125 | &xhci->ir_set->erst_dequeue); | |
76a35293 FB |
3126 | ret = IRQ_HANDLED; |
3127 | goto out; | |
c06d68b8 SS |
3128 | } |
3129 | ||
3130 | event_ring_deq = xhci->event_ring->dequeue; | |
3131 | /* FIXME this should be a delayed service routine | |
3132 | * that clears the EHB. | |
3133 | */ | |
dc0ffbea PC |
3134 | while (xhci_handle_event(xhci) > 0) { |
3135 | if (event_loop++ < TRBS_PER_SEGMENT / 2) | |
3136 | continue; | |
3137 | xhci_update_erst_dequeue(xhci, event_ring_deq); | |
90d551a5 MN |
3138 | |
3139 | /* ring is half-full, force isoc trbs to interrupt more often */ | |
3140 | if (xhci->isoc_bei_interval > AVOID_BEI_INTERVAL_MIN) | |
3141 | xhci->isoc_bei_interval = xhci->isoc_bei_interval / 2; | |
3142 | ||
dc0ffbea | 3143 | event_loop = 0; |
c06d68b8 SS |
3144 | } |
3145 | ||
dc0ffbea | 3146 | xhci_update_erst_dequeue(xhci, event_ring_deq); |
76a35293 | 3147 | ret = IRQ_HANDLED; |
c06d68b8 | 3148 | |
76a35293 | 3149 | out: |
5e712172 | 3150 | spin_unlock(&xhci->lock); |
9032cd52 | 3151 | |
76a35293 | 3152 | return ret; |
9032cd52 SS |
3153 | } |
3154 | ||
851ec164 | 3155 | irqreturn_t xhci_msi_irq(int irq, void *hcd) |
9032cd52 | 3156 | { |
968b822c | 3157 | return xhci_irq(hcd); |
9032cd52 | 3158 | } |
7f84eef0 | 3159 | |
d0e96f5a SS |
3160 | /**** Endpoint Ring Operations ****/ |
3161 | ||
7f84eef0 SS |
3162 | /* |
3163 | * Generic function for queueing a TRB on a ring. | |
3164 | * The caller must have checked to make sure there's room on the ring. | |
6cc30d85 SS |
3165 | * |
3166 | * @more_trbs_coming: Will you enqueue more TRBs before calling | |
3167 | * prepare_transfer()? | |
7f84eef0 SS |
3168 | */ |
3169 | static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring, | |
3b72fca0 | 3170 | bool more_trbs_coming, |
7f84eef0 SS |
3171 | u32 field1, u32 field2, u32 field3, u32 field4) |
3172 | { | |
3173 | struct xhci_generic_trb *trb; | |
3174 | ||
3175 | trb = &ring->enqueue->generic; | |
28ccd296 ME |
3176 | trb->field[0] = cpu_to_le32(field1); |
3177 | trb->field[1] = cpu_to_le32(field2); | |
3178 | trb->field[2] = cpu_to_le32(field3); | |
576667ba MN |
3179 | /* make sure TRB is fully written before giving it to the controller */ |
3180 | wmb(); | |
28ccd296 | 3181 | trb->field[3] = cpu_to_le32(field4); |
a37c3f76 FB |
3182 | |
3183 | trace_xhci_queue_trb(ring, trb); | |
3184 | ||
3b72fca0 | 3185 | inc_enq(xhci, ring, more_trbs_coming); |
7f84eef0 SS |
3186 | } |
3187 | ||
d0e96f5a SS |
3188 | /* |
3189 | * Does various checks on the endpoint ring, and makes it ready to queue num_trbs. | |
3190 | * FIXME allocate segments if the ring is full. | |
3191 | */ | |
3192 | static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring, | |
3b72fca0 | 3193 | u32 ep_state, unsigned int num_trbs, gfp_t mem_flags) |
d0e96f5a | 3194 | { |
8dfec614 | 3195 | unsigned int num_trbs_needed; |
04d21f72 | 3196 | unsigned int link_trb_count = 0; |
8dfec614 | 3197 | |
d0e96f5a | 3198 | /* Make sure the endpoint has been added to xHC schedule */ |
d0e96f5a SS |
3199 | switch (ep_state) { |
3200 | case EP_STATE_DISABLED: | |
3201 | /* | |
3202 | * USB core changed config/interfaces without notifying us, | |
3203 | * or hardware is reporting the wrong state. | |
3204 | */ | |
3205 | xhci_warn(xhci, "WARN urb submitted to disabled ep\n"); | |
3206 | return -ENOENT; | |
d0e96f5a | 3207 | case EP_STATE_ERROR: |
c92bcfa7 | 3208 | xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n"); |
d0e96f5a SS |
3209 | /* FIXME event handling code for error needs to clear it */ |
3210 | /* XXX not sure if this should be -ENOENT or not */ | |
3211 | return -EINVAL; | |
c92bcfa7 SS |
3212 | case EP_STATE_HALTED: |
3213 | xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n"); | |
1d6903a6 | 3214 | break; |
d0e96f5a SS |
3215 | case EP_STATE_STOPPED: |
3216 | case EP_STATE_RUNNING: | |
3217 | break; | |
3218 | default: | |
3219 | xhci_err(xhci, "ERROR unknown endpoint state for ep\n"); | |
3220 | /* | |
3221 | * FIXME issue Configure Endpoint command to try to get the HC | |
3222 | * back into a known state. | |
3223 | */ | |
3224 | return -EINVAL; | |
3225 | } | |
8dfec614 AX |
3226 | |
3227 | while (1) { | |
3d4b81ed SS |
3228 | if (room_on_ring(xhci, ep_ring, num_trbs)) |
3229 | break; | |
8dfec614 AX |
3230 | |
3231 | if (ep_ring == xhci->cmd_ring) { | |
3232 | xhci_err(xhci, "Do not support expand command ring\n"); | |
3233 | return -ENOMEM; | |
3234 | } | |
3235 | ||
68ffb011 XR |
3236 | xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion, |
3237 | "ERROR no room on ep ring, try ring expansion"); | |
8dfec614 AX |
3238 | num_trbs_needed = num_trbs - ep_ring->num_trbs_free; |
3239 | if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed, | |
3240 | mem_flags)) { | |
3241 | xhci_err(xhci, "Ring expansion failed\n"); | |
3242 | return -ENOMEM; | |
3243 | } | |
261fa12b | 3244 | } |
6c12db90 | 3245 | |
d0c77d84 MN |
3246 | while (trb_is_link(ep_ring->enqueue)) { |
3247 | /* If we're not dealing with 0.95 hardware or isoc rings | |
3248 | * on AMD 0.96 host, clear the chain bit. | |
3249 | */ | |
3250 | if (!xhci_link_trb_quirk(xhci) && | |
3251 | !(ep_ring->type == TYPE_ISOC && | |
3252 | (xhci->quirks & XHCI_AMD_0x96_HOST))) | |
3253 | ep_ring->enqueue->link.control &= | |
3254 | cpu_to_le32(~TRB_CHAIN); | |
3255 | else | |
3256 | ep_ring->enqueue->link.control |= | |
3257 | cpu_to_le32(TRB_CHAIN); | |
6c12db90 | 3258 | |
d0c77d84 MN |
3259 | wmb(); |
3260 | ep_ring->enqueue->link.control ^= cpu_to_le32(TRB_CYCLE); | |
6c12db90 | 3261 | |
d0c77d84 MN |
3262 | /* Toggle the cycle bit after the last ring segment. */ |
3263 | if (link_trb_toggles_cycle(ep_ring->enqueue)) | |
3264 | ep_ring->cycle_state ^= 1; | |
6c12db90 | 3265 | |
d0c77d84 MN |
3266 | ep_ring->enq_seg = ep_ring->enq_seg->next; |
3267 | ep_ring->enqueue = ep_ring->enq_seg->trbs; | |
04d21f72 MN |
3268 | |
3269 | /* prevent infinite loop if all first trbs are link trbs */ | |
3270 | if (link_trb_count++ > ep_ring->num_segs) { | |
3271 | xhci_warn(xhci, "Ring is an endless link TRB loop\n"); | |
3272 | return -EINVAL; | |
3273 | } | |
6c12db90 | 3274 | } |
c716e8a5 MN |
3275 | |
3276 | if (last_trb_on_seg(ep_ring->enq_seg, ep_ring->enqueue)) { | |
3277 | xhci_warn(xhci, "Missing link TRB at end of ring segment\n"); | |
3278 | return -EINVAL; | |
3279 | } | |
3280 | ||
d0e96f5a SS |
3281 | return 0; |
3282 | } | |
3283 | ||
23e3be11 | 3284 | static int prepare_transfer(struct xhci_hcd *xhci, |
d0e96f5a SS |
3285 | struct xhci_virt_device *xdev, |
3286 | unsigned int ep_index, | |
e9df17eb | 3287 | unsigned int stream_id, |
d0e96f5a SS |
3288 | unsigned int num_trbs, |
3289 | struct urb *urb, | |
8e51adcc | 3290 | unsigned int td_index, |
d0e96f5a SS |
3291 | gfp_t mem_flags) |
3292 | { | |
3293 | int ret; | |
8e51adcc AX |
3294 | struct urb_priv *urb_priv; |
3295 | struct xhci_td *td; | |
e9df17eb | 3296 | struct xhci_ring *ep_ring; |
d115b048 | 3297 | struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
e9df17eb | 3298 | |
c089cada MN |
3299 | ep_ring = xhci_triad_to_transfer_ring(xhci, xdev->slot_id, ep_index, |
3300 | stream_id); | |
e9df17eb SS |
3301 | if (!ep_ring) { |
3302 | xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n", | |
3303 | stream_id); | |
3304 | return -EINVAL; | |
3305 | } | |
3306 | ||
5071e6b2 | 3307 | ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx), |
3b72fca0 | 3308 | num_trbs, mem_flags); |
d0e96f5a SS |
3309 | if (ret) |
3310 | return ret; | |
d0e96f5a | 3311 | |
8e51adcc | 3312 | urb_priv = urb->hcpriv; |
7e64b037 | 3313 | td = &urb_priv->td[td_index]; |
8e51adcc AX |
3314 | |
3315 | INIT_LIST_HEAD(&td->td_list); | |
3316 | INIT_LIST_HEAD(&td->cancelled_td_list); | |
3317 | ||
3318 | if (td_index == 0) { | |
214f76f7 | 3319 | ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb); |
d13565c1 | 3320 | if (unlikely(ret)) |
8e51adcc | 3321 | return ret; |
d0e96f5a SS |
3322 | } |
3323 | ||
8e51adcc | 3324 | td->urb = urb; |
d0e96f5a | 3325 | /* Add this TD to the tail of the endpoint ring's TD list */ |
8e51adcc AX |
3326 | list_add_tail(&td->td_list, &ep_ring->td_list); |
3327 | td->start_seg = ep_ring->enq_seg; | |
3328 | td->first_trb = ep_ring->enqueue; | |
3329 | ||
d0e96f5a SS |
3330 | return 0; |
3331 | } | |
3332 | ||
67d2ea9f | 3333 | unsigned int count_trbs(u64 addr, u64 len) |
d2510342 AI |
3334 | { |
3335 | unsigned int num_trbs; | |
3336 | ||
3337 | num_trbs = DIV_ROUND_UP(len + (addr & (TRB_MAX_BUFF_SIZE - 1)), | |
3338 | TRB_MAX_BUFF_SIZE); | |
3339 | if (num_trbs == 0) | |
3340 | num_trbs++; | |
3341 | ||
3342 | return num_trbs; | |
3343 | } | |
3344 | ||
3345 | static inline unsigned int count_trbs_needed(struct urb *urb) | |
3346 | { | |
3347 | return count_trbs(urb->transfer_dma, urb->transfer_buffer_length); | |
3348 | } | |
3349 | ||
3350 | static unsigned int count_sg_trbs_needed(struct urb *urb) | |
8a96c052 | 3351 | { |
8a96c052 | 3352 | struct scatterlist *sg; |
d2510342 | 3353 | unsigned int i, len, full_len, num_trbs = 0; |
8a96c052 | 3354 | |
d2510342 | 3355 | full_len = urb->transfer_buffer_length; |
8a96c052 | 3356 | |
d2510342 AI |
3357 | for_each_sg(urb->sg, sg, urb->num_mapped_sgs, i) { |
3358 | len = sg_dma_len(sg); | |
3359 | num_trbs += count_trbs(sg_dma_address(sg), len); | |
3360 | len = min_t(unsigned int, len, full_len); | |
3361 | full_len -= len; | |
3362 | if (full_len == 0) | |
8a96c052 SS |
3363 | break; |
3364 | } | |
d2510342 | 3365 | |
8a96c052 SS |
3366 | return num_trbs; |
3367 | } | |
3368 | ||
d2510342 AI |
3369 | static unsigned int count_isoc_trbs_needed(struct urb *urb, int i) |
3370 | { | |
3371 | u64 addr, len; | |
3372 | ||
3373 | addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset); | |
3374 | len = urb->iso_frame_desc[i].length; | |
3375 | ||
3376 | return count_trbs(addr, len); | |
3377 | } | |
3378 | ||
3379 | static void check_trb_math(struct urb *urb, int running_total) | |
8a96c052 | 3380 | { |
d2510342 | 3381 | if (unlikely(running_total != urb->transfer_buffer_length)) |
a2490187 | 3382 | dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, " |
8a96c052 SS |
3383 | "queued %#x (%d), asked for %#x (%d)\n", |
3384 | __func__, | |
3385 | urb->ep->desc.bEndpointAddress, | |
3386 | running_total, running_total, | |
3387 | urb->transfer_buffer_length, | |
3388 | urb->transfer_buffer_length); | |
3389 | } | |
3390 | ||
23e3be11 | 3391 | static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id, |
e9df17eb | 3392 | unsigned int ep_index, unsigned int stream_id, int start_cycle, |
e1eab2e0 | 3393 | struct xhci_generic_trb *start_trb) |
8a96c052 | 3394 | { |
8a96c052 SS |
3395 | /* |
3396 | * Pass all the TRBs to the hardware at once and make sure this write | |
3397 | * isn't reordered. | |
3398 | */ | |
3399 | wmb(); | |
50f7b52a | 3400 | if (start_cycle) |
28ccd296 | 3401 | start_trb->field[3] |= cpu_to_le32(start_cycle); |
50f7b52a | 3402 | else |
28ccd296 | 3403 | start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE); |
be88fe4f | 3404 | xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id); |
8a96c052 SS |
3405 | } |
3406 | ||
78140156 AI |
3407 | static void check_interval(struct xhci_hcd *xhci, struct urb *urb, |
3408 | struct xhci_ep_ctx *ep_ctx) | |
624defa1 | 3409 | { |
624defa1 SS |
3410 | int xhci_interval; |
3411 | int ep_interval; | |
3412 | ||
28ccd296 | 3413 | xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info)); |
624defa1 | 3414 | ep_interval = urb->interval; |
78140156 | 3415 | |
624defa1 SS |
3416 | /* Convert to microframes */ |
3417 | if (urb->dev->speed == USB_SPEED_LOW || | |
3418 | urb->dev->speed == USB_SPEED_FULL) | |
3419 | ep_interval *= 8; | |
78140156 | 3420 | |
624defa1 SS |
3421 | /* FIXME change this to a warning and a suggestion to use the new API |
3422 | * to set the polling interval (once the API is added). | |
3423 | */ | |
3424 | if (xhci_interval != ep_interval) { | |
0730d52a DK |
3425 | dev_dbg_ratelimited(&urb->dev->dev, |
3426 | "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n", | |
3427 | ep_interval, ep_interval == 1 ? "" : "s", | |
3428 | xhci_interval, xhci_interval == 1 ? "" : "s"); | |
624defa1 SS |
3429 | urb->interval = xhci_interval; |
3430 | /* Convert back to frames for LS/FS devices */ | |
3431 | if (urb->dev->speed == USB_SPEED_LOW || | |
3432 | urb->dev->speed == USB_SPEED_FULL) | |
3433 | urb->interval /= 8; | |
3434 | } | |
78140156 AI |
3435 | } |
3436 | ||
3437 | /* | |
3438 | * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt | |
3439 | * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD | |
3440 | * (comprised of sg list entries) can take several service intervals to | |
3441 | * transmit. | |
3442 | */ | |
3443 | int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |
3444 | struct urb *urb, int slot_id, unsigned int ep_index) | |
3445 | { | |
3446 | struct xhci_ep_ctx *ep_ctx; | |
3447 | ||
3448 | ep_ctx = xhci_get_ep_ctx(xhci, xhci->devs[slot_id]->out_ctx, ep_index); | |
3449 | check_interval(xhci, urb, ep_ctx); | |
3450 | ||
3fc8206d | 3451 | return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index); |
624defa1 SS |
3452 | } |
3453 | ||
4da6e6f2 | 3454 | /* |
4525c0a1 SS |
3455 | * For xHCI 1.0 host controllers, TD size is the number of max packet sized |
3456 | * packets remaining in the TD (*not* including this TRB). | |
4da6e6f2 SS |
3457 | * |
3458 | * Total TD packet count = total_packet_count = | |
4525c0a1 | 3459 | * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize) |
4da6e6f2 SS |
3460 | * |
3461 | * Packets transferred up to and including this TRB = packets_transferred = | |
3462 | * rounddown(total bytes transferred including this TRB / wMaxPacketSize) | |
3463 | * | |
3464 | * TD size = total_packet_count - packets_transferred | |
3465 | * | |
c840d6ce MN |
3466 | * For xHCI 0.96 and older, TD size field should be the remaining bytes |
3467 | * including this TRB, right shifted by 10 | |
3468 | * | |
3469 | * For all hosts it must fit in bits 21:17, so it can't be bigger than 31. | |
3470 | * This is taken care of in the TRB_TD_SIZE() macro | |
3471 | * | |
4525c0a1 | 3472 | * The last TRB in a TD must have the TD size set to zero. |
4da6e6f2 | 3473 | */ |
c840d6ce MN |
3474 | static u32 xhci_td_remainder(struct xhci_hcd *xhci, int transferred, |
3475 | int trb_buff_len, unsigned int td_total_len, | |
124c3937 | 3476 | struct urb *urb, bool more_trbs_coming) |
4da6e6f2 | 3477 | { |
c840d6ce MN |
3478 | u32 maxp, total_packet_count; |
3479 | ||
72b663a9 | 3480 | /* MTK xHCI 0.96 contains some features from 1.0 */ |
0cbd4b34 | 3481 | if (xhci->hci_version < 0x100 && !(xhci->quirks & XHCI_MTK_HOST)) |
c840d6ce MN |
3482 | return ((td_total_len - transferred) >> 10); |
3483 | ||
48df4a6f | 3484 | /* One TRB with a zero-length data packet. */ |
124c3937 | 3485 | if (!more_trbs_coming || (transferred == 0 && trb_buff_len == 0) || |
c840d6ce | 3486 | trb_buff_len == td_total_len) |
48df4a6f SS |
3487 | return 0; |
3488 | ||
72b663a9 CY |
3489 | /* for MTK xHCI 0.96, TD size include this TRB, but not in 1.x */ |
3490 | if ((xhci->quirks & XHCI_MTK_HOST) && (xhci->hci_version < 0x100)) | |
0cbd4b34 CY |
3491 | trb_buff_len = 0; |
3492 | ||
734d3ddd | 3493 | maxp = usb_endpoint_maxp(&urb->ep->desc); |
0cbd4b34 CY |
3494 | total_packet_count = DIV_ROUND_UP(td_total_len, maxp); |
3495 | ||
c840d6ce MN |
3496 | /* Queueing functions don't count the current TRB into transferred */ |
3497 | return (total_packet_count - ((transferred + trb_buff_len) / maxp)); | |
4da6e6f2 SS |
3498 | } |
3499 | ||
f9c589e1 | 3500 | |
474ed23a | 3501 | static int xhci_align_td(struct xhci_hcd *xhci, struct urb *urb, u32 enqd_len, |
f9c589e1 | 3502 | u32 *trb_buff_len, struct xhci_segment *seg) |
474ed23a | 3503 | { |
f9c589e1 | 3504 | struct device *dev = xhci_to_hcd(xhci)->self.controller; |
474ed23a MN |
3505 | unsigned int unalign; |
3506 | unsigned int max_pkt; | |
f9c589e1 | 3507 | u32 new_buff_len; |
597c56e3 | 3508 | size_t len; |
474ed23a | 3509 | |
734d3ddd | 3510 | max_pkt = usb_endpoint_maxp(&urb->ep->desc); |
474ed23a MN |
3511 | unalign = (enqd_len + *trb_buff_len) % max_pkt; |
3512 | ||
3513 | /* we got lucky, last normal TRB data on segment is packet aligned */ | |
3514 | if (unalign == 0) | |
3515 | return 0; | |
3516 | ||
f9c589e1 MN |
3517 | xhci_dbg(xhci, "Unaligned %d bytes, buff len %d\n", |
3518 | unalign, *trb_buff_len); | |
3519 | ||
474ed23a MN |
3520 | /* is the last nornal TRB alignable by splitting it */ |
3521 | if (*trb_buff_len > unalign) { | |
3522 | *trb_buff_len -= unalign; | |
f9c589e1 | 3523 | xhci_dbg(xhci, "split align, new buff len %d\n", *trb_buff_len); |
474ed23a MN |
3524 | return 0; |
3525 | } | |
f9c589e1 MN |
3526 | |
3527 | /* | |
3528 | * We want enqd_len + trb_buff_len to sum up to a number aligned to | |
3529 | * number which is divisible by the endpoint's wMaxPacketSize. IOW: | |
3530 | * (size of currently enqueued TRBs + remainder) % wMaxPacketSize == 0. | |
3531 | */ | |
3532 | new_buff_len = max_pkt - (enqd_len % max_pkt); | |
3533 | ||
3534 | if (new_buff_len > (urb->transfer_buffer_length - enqd_len)) | |
3535 | new_buff_len = (urb->transfer_buffer_length - enqd_len); | |
3536 | ||
3537 | /* create a max max_pkt sized bounce buffer pointed to by last trb */ | |
3538 | if (usb_urb_dir_out(urb)) { | |
d4a61063 MN |
3539 | if (urb->num_sgs) { |
3540 | len = sg_pcopy_to_buffer(urb->sg, urb->num_sgs, | |
3541 | seg->bounce_buf, new_buff_len, enqd_len); | |
3542 | if (len != new_buff_len) | |
3543 | xhci_warn(xhci, "WARN Wrong bounce buffer write length: %zu != %d\n", | |
3544 | len, new_buff_len); | |
3545 | } else { | |
3546 | memcpy(seg->bounce_buf, urb->transfer_buffer + enqd_len, new_buff_len); | |
3547 | } | |
3548 | ||
f9c589e1 MN |
3549 | seg->bounce_dma = dma_map_single(dev, seg->bounce_buf, |
3550 | max_pkt, DMA_TO_DEVICE); | |
3551 | } else { | |
3552 | seg->bounce_dma = dma_map_single(dev, seg->bounce_buf, | |
3553 | max_pkt, DMA_FROM_DEVICE); | |
3554 | } | |
3555 | ||
3556 | if (dma_mapping_error(dev, seg->bounce_dma)) { | |
3557 | /* try without aligning. Some host controllers survive */ | |
3558 | xhci_warn(xhci, "Failed mapping bounce buffer, not aligning\n"); | |
3559 | return 0; | |
3560 | } | |
3561 | *trb_buff_len = new_buff_len; | |
3562 | seg->bounce_len = new_buff_len; | |
3563 | seg->bounce_offs = enqd_len; | |
3564 | ||
3565 | xhci_dbg(xhci, "Bounce align, new buff len %d\n", *trb_buff_len); | |
3566 | ||
474ed23a MN |
3567 | return 1; |
3568 | } | |
3569 | ||
d2510342 AI |
3570 | /* This is very similar to what ehci-q.c qtd_fill() does */ |
3571 | int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |
8a96c052 SS |
3572 | struct urb *urb, int slot_id, unsigned int ep_index) |
3573 | { | |
5a5a0b1a | 3574 | struct xhci_ring *ring; |
8e51adcc | 3575 | struct urb_priv *urb_priv; |
8a96c052 | 3576 | struct xhci_td *td; |
d2510342 AI |
3577 | struct xhci_generic_trb *start_trb; |
3578 | struct scatterlist *sg = NULL; | |
5a83f04a MN |
3579 | bool more_trbs_coming = true; |
3580 | bool need_zero_pkt = false; | |
86065c27 MN |
3581 | bool first_trb = true; |
3582 | unsigned int num_trbs; | |
d2510342 | 3583 | unsigned int start_cycle, num_sgs = 0; |
86065c27 | 3584 | unsigned int enqd_len, block_len, trb_buff_len, full_len; |
f9c589e1 | 3585 | int sent_len, ret; |
d2510342 | 3586 | u32 field, length_field, remainder; |
f9c589e1 | 3587 | u64 addr, send_addr; |
8a96c052 | 3588 | |
5a5a0b1a MN |
3589 | ring = xhci_urb_to_transfer_ring(xhci, urb); |
3590 | if (!ring) | |
e9df17eb SS |
3591 | return -EINVAL; |
3592 | ||
86065c27 | 3593 | full_len = urb->transfer_buffer_length; |
d2510342 | 3594 | /* If we have scatter/gather list, we use it. */ |
2017a1e5 | 3595 | if (urb->num_sgs && !(urb->transfer_flags & URB_DMA_MAP_SINGLE)) { |
d2510342 AI |
3596 | num_sgs = urb->num_mapped_sgs; |
3597 | sg = urb->sg; | |
86065c27 MN |
3598 | addr = (u64) sg_dma_address(sg); |
3599 | block_len = sg_dma_len(sg); | |
d2510342 | 3600 | num_trbs = count_sg_trbs_needed(urb); |
86065c27 | 3601 | } else { |
d2510342 | 3602 | num_trbs = count_trbs_needed(urb); |
86065c27 MN |
3603 | addr = (u64) urb->transfer_dma; |
3604 | block_len = full_len; | |
3605 | } | |
4758dcd1 | 3606 | ret = prepare_transfer(xhci, xhci->devs[slot_id], |
e9df17eb | 3607 | ep_index, urb->stream_id, |
3b72fca0 | 3608 | num_trbs, urb, 0, mem_flags); |
d2510342 | 3609 | if (unlikely(ret < 0)) |
4758dcd1 | 3610 | return ret; |
8e51adcc AX |
3611 | |
3612 | urb_priv = urb->hcpriv; | |
4758dcd1 RA |
3613 | |
3614 | /* Deal with URB_ZERO_PACKET - need one more td/trb */ | |
9ef7fbbb | 3615 | if (urb->transfer_flags & URB_ZERO_PACKET && urb_priv->num_tds > 1) |
5a83f04a | 3616 | need_zero_pkt = true; |
4758dcd1 | 3617 | |
7e64b037 | 3618 | td = &urb_priv->td[0]; |
8e51adcc | 3619 | |
8a96c052 SS |
3620 | /* |
3621 | * Don't give the first TRB to the hardware (by toggling the cycle bit) | |
3622 | * until we've finished creating all the other TRBs. The ring's cycle | |
3623 | * state may change as we enqueue the other TRBs, so save it too. | |
3624 | */ | |
5a5a0b1a MN |
3625 | start_trb = &ring->enqueue->generic; |
3626 | start_cycle = ring->cycle_state; | |
f9c589e1 | 3627 | send_addr = addr; |
8a96c052 | 3628 | |
d2510342 | 3629 | /* Queue the TRBs, even if they are zero-length */ |
0d2daade AB |
3630 | for (enqd_len = 0; first_trb || enqd_len < full_len; |
3631 | enqd_len += trb_buff_len) { | |
d2510342 | 3632 | field = TRB_TYPE(TRB_NORMAL); |
af8b9e63 | 3633 | |
86065c27 MN |
3634 | /* TRB buffer should not cross 64KB boundaries */ |
3635 | trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr); | |
3636 | trb_buff_len = min_t(unsigned int, trb_buff_len, block_len); | |
8a96c052 | 3637 | |
86065c27 MN |
3638 | if (enqd_len + trb_buff_len > full_len) |
3639 | trb_buff_len = full_len - enqd_len; | |
b10de142 SS |
3640 | |
3641 | /* Don't change the cycle bit of the first TRB until later */ | |
86065c27 MN |
3642 | if (first_trb) { |
3643 | first_trb = false; | |
50f7b52a | 3644 | if (start_cycle == 0) |
d2510342 | 3645 | field |= TRB_CYCLE; |
50f7b52a | 3646 | } else |
5a5a0b1a | 3647 | field |= ring->cycle_state; |
b10de142 SS |
3648 | |
3649 | /* Chain all the TRBs together; clear the chain bit in the last | |
3650 | * TRB to indicate it's the last TRB in the chain. | |
3651 | */ | |
86065c27 | 3652 | if (enqd_len + trb_buff_len < full_len) { |
b10de142 | 3653 | field |= TRB_CHAIN; |
2d98ef40 | 3654 | if (trb_is_link(ring->enqueue + 1)) { |
474ed23a | 3655 | if (xhci_align_td(xhci, urb, enqd_len, |
f9c589e1 MN |
3656 | &trb_buff_len, |
3657 | ring->enq_seg)) { | |
3658 | send_addr = ring->enq_seg->bounce_dma; | |
3659 | /* assuming TD won't span 2 segs */ | |
3660 | td->bounce_seg = ring->enq_seg; | |
3661 | } | |
474ed23a | 3662 | } |
f9c589e1 MN |
3663 | } |
3664 | if (enqd_len + trb_buff_len >= full_len) { | |
3665 | field &= ~TRB_CHAIN; | |
4758dcd1 | 3666 | field |= TRB_IOC; |
124c3937 | 3667 | more_trbs_coming = false; |
5a83f04a | 3668 | td->last_trb = ring->enqueue; |
55f6153d | 3669 | td->last_trb_seg = ring->enq_seg; |
33e39350 NSJ |
3670 | if (xhci_urb_suitable_for_idt(urb)) { |
3671 | memcpy(&send_addr, urb->transfer_buffer, | |
3672 | trb_buff_len); | |
bfa3dbb3 | 3673 | le64_to_cpus(&send_addr); |
33e39350 NSJ |
3674 | field |= TRB_IDT; |
3675 | } | |
b10de142 | 3676 | } |
af8b9e63 SS |
3677 | |
3678 | /* Only set interrupt on short packet for IN endpoints */ | |
3679 | if (usb_urb_dir_in(urb)) | |
3680 | field |= TRB_ISP; | |
3681 | ||
4da6e6f2 | 3682 | /* Set the TRB length, TD size, and interrupter fields. */ |
86065c27 MN |
3683 | remainder = xhci_td_remainder(xhci, enqd_len, trb_buff_len, |
3684 | full_len, urb, more_trbs_coming); | |
3685 | ||
f9dc68fe | 3686 | length_field = TRB_LEN(trb_buff_len) | |
c840d6ce | 3687 | TRB_TD_SIZE(remainder) | |
f9dc68fe | 3688 | TRB_INTR_TARGET(0); |
4da6e6f2 | 3689 | |
124c3937 | 3690 | queue_trb(xhci, ring, more_trbs_coming | need_zero_pkt, |
f9c589e1 MN |
3691 | lower_32_bits(send_addr), |
3692 | upper_32_bits(send_addr), | |
f9dc68fe | 3693 | length_field, |
d2510342 | 3694 | field); |
55f6153d | 3695 | td->num_trbs++; |
b10de142 | 3696 | addr += trb_buff_len; |
f9c589e1 | 3697 | sent_len = trb_buff_len; |
d2510342 | 3698 | |
f9c589e1 | 3699 | while (sg && sent_len >= block_len) { |
86065c27 MN |
3700 | /* New sg entry */ |
3701 | --num_sgs; | |
f9c589e1 | 3702 | sent_len -= block_len; |
3c6f8cb9 SA |
3703 | sg = sg_next(sg); |
3704 | if (num_sgs != 0 && sg) { | |
86065c27 MN |
3705 | block_len = sg_dma_len(sg); |
3706 | addr = (u64) sg_dma_address(sg); | |
f9c589e1 | 3707 | addr += sent_len; |
d2510342 AI |
3708 | } |
3709 | } | |
f9c589e1 MN |
3710 | block_len -= sent_len; |
3711 | send_addr = addr; | |
d2510342 | 3712 | } |
b10de142 | 3713 | |
5a83f04a MN |
3714 | if (need_zero_pkt) { |
3715 | ret = prepare_transfer(xhci, xhci->devs[slot_id], | |
3716 | ep_index, urb->stream_id, | |
3717 | 1, urb, 1, mem_flags); | |
7e64b037 | 3718 | urb_priv->td[1].last_trb = ring->enqueue; |
55f6153d | 3719 | urb_priv->td[1].last_trb_seg = ring->enq_seg; |
5a83f04a MN |
3720 | field = TRB_TYPE(TRB_NORMAL) | ring->cycle_state | TRB_IOC; |
3721 | queue_trb(xhci, ring, 0, 0, 0, TRB_INTR_TARGET(0), field); | |
55f6153d | 3722 | urb_priv->td[1].num_trbs++; |
5a83f04a MN |
3723 | } |
3724 | ||
86065c27 | 3725 | check_trb_math(urb, enqd_len); |
e9df17eb | 3726 | giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, |
e1eab2e0 | 3727 | start_cycle, start_trb); |
b10de142 SS |
3728 | return 0; |
3729 | } | |
3730 | ||
d0e96f5a | 3731 | /* Caller must have locked xhci->lock */ |
23e3be11 | 3732 | int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, |
d0e96f5a SS |
3733 | struct urb *urb, int slot_id, unsigned int ep_index) |
3734 | { | |
3735 | struct xhci_ring *ep_ring; | |
3736 | int num_trbs; | |
3737 | int ret; | |
3738 | struct usb_ctrlrequest *setup; | |
3739 | struct xhci_generic_trb *start_trb; | |
3740 | int start_cycle; | |
fb79a6da | 3741 | u32 field; |
8e51adcc | 3742 | struct urb_priv *urb_priv; |
d0e96f5a SS |
3743 | struct xhci_td *td; |
3744 | ||
e9df17eb SS |
3745 | ep_ring = xhci_urb_to_transfer_ring(xhci, urb); |
3746 | if (!ep_ring) | |
3747 | return -EINVAL; | |
d0e96f5a SS |
3748 | |
3749 | /* | |
3750 | * Need to copy setup packet into setup TRB, so we can't use the setup | |
3751 | * DMA address. | |
3752 | */ | |
3753 | if (!urb->setup_packet) | |
3754 | return -EINVAL; | |
3755 | ||
d0e96f5a SS |
3756 | /* 1 TRB for setup, 1 for status */ |
3757 | num_trbs = 2; | |
3758 | /* | |
3759 | * Don't need to check if we need additional event data and normal TRBs, | |
3760 | * since data in control transfers will never get bigger than 16MB | |
3761 | * XXX: can we get a buffer that crosses 64KB boundaries? | |
3762 | */ | |
3763 | if (urb->transfer_buffer_length > 0) | |
3764 | num_trbs++; | |
e9df17eb SS |
3765 | ret = prepare_transfer(xhci, xhci->devs[slot_id], |
3766 | ep_index, urb->stream_id, | |
3b72fca0 | 3767 | num_trbs, urb, 0, mem_flags); |
d0e96f5a SS |
3768 | if (ret < 0) |
3769 | return ret; | |
3770 | ||
8e51adcc | 3771 | urb_priv = urb->hcpriv; |
7e64b037 | 3772 | td = &urb_priv->td[0]; |
55f6153d | 3773 | td->num_trbs = num_trbs; |
8e51adcc | 3774 | |
d0e96f5a SS |
3775 | /* |
3776 | * Don't give the first TRB to the hardware (by toggling the cycle bit) | |
3777 | * until we've finished creating all the other TRBs. The ring's cycle | |
3778 | * state may change as we enqueue the other TRBs, so save it too. | |
3779 | */ | |
3780 | start_trb = &ep_ring->enqueue->generic; | |
3781 | start_cycle = ep_ring->cycle_state; | |
3782 | ||
3783 | /* Queue setup TRB - see section 6.4.1.2.1 */ | |
3784 | /* FIXME better way to translate setup_packet into two u32 fields? */ | |
3785 | setup = (struct usb_ctrlrequest *) urb->setup_packet; | |
50f7b52a AX |
3786 | field = 0; |
3787 | field |= TRB_IDT | TRB_TYPE(TRB_SETUP); | |
3788 | if (start_cycle == 0) | |
3789 | field |= 0x1; | |
b83cdc8f | 3790 | |
dca77945 | 3791 | /* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */ |
0cbd4b34 | 3792 | if ((xhci->hci_version >= 0x100) || (xhci->quirks & XHCI_MTK_HOST)) { |
b83cdc8f AX |
3793 | if (urb->transfer_buffer_length > 0) { |
3794 | if (setup->bRequestType & USB_DIR_IN) | |
3795 | field |= TRB_TX_TYPE(TRB_DATA_IN); | |
3796 | else | |
3797 | field |= TRB_TX_TYPE(TRB_DATA_OUT); | |
3798 | } | |
3799 | } | |
3800 | ||
3b72fca0 | 3801 | queue_trb(xhci, ep_ring, true, |
28ccd296 ME |
3802 | setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16, |
3803 | le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16, | |
3804 | TRB_LEN(8) | TRB_INTR_TARGET(0), | |
3805 | /* Immediate data in pointer */ | |
3806 | field); | |
d0e96f5a SS |
3807 | |
3808 | /* If there's data, queue data TRBs */ | |
af8b9e63 SS |
3809 | /* Only set interrupt on short packet for IN endpoints */ |
3810 | if (usb_urb_dir_in(urb)) | |
3811 | field = TRB_ISP | TRB_TYPE(TRB_DATA); | |
3812 | else | |
3813 | field = TRB_TYPE(TRB_DATA); | |
3814 | ||
d0e96f5a | 3815 | if (urb->transfer_buffer_length > 0) { |
fb79a6da | 3816 | u32 length_field, remainder; |
13b82b74 | 3817 | u64 addr; |
fb79a6da | 3818 | |
33e39350 | 3819 | if (xhci_urb_suitable_for_idt(urb)) { |
13b82b74 | 3820 | memcpy(&addr, urb->transfer_buffer, |
33e39350 | 3821 | urb->transfer_buffer_length); |
bfa3dbb3 | 3822 | le64_to_cpus(&addr); |
33e39350 | 3823 | field |= TRB_IDT; |
13b82b74 MN |
3824 | } else { |
3825 | addr = (u64) urb->transfer_dma; | |
33e39350 NSJ |
3826 | } |
3827 | ||
fb79a6da LB |
3828 | remainder = xhci_td_remainder(xhci, 0, |
3829 | urb->transfer_buffer_length, | |
3830 | urb->transfer_buffer_length, | |
3831 | urb, 1); | |
3832 | length_field = TRB_LEN(urb->transfer_buffer_length) | | |
3833 | TRB_TD_SIZE(remainder) | | |
3834 | TRB_INTR_TARGET(0); | |
d0e96f5a SS |
3835 | if (setup->bRequestType & USB_DIR_IN) |
3836 | field |= TRB_DIR_IN; | |
3b72fca0 | 3837 | queue_trb(xhci, ep_ring, true, |
13b82b74 MN |
3838 | lower_32_bits(addr), |
3839 | upper_32_bits(addr), | |
f9dc68fe | 3840 | length_field, |
af8b9e63 | 3841 | field | ep_ring->cycle_state); |
d0e96f5a SS |
3842 | } |
3843 | ||
3844 | /* Save the DMA address of the last TRB in the TD */ | |
3845 | td->last_trb = ep_ring->enqueue; | |
55f6153d | 3846 | td->last_trb_seg = ep_ring->enq_seg; |
d0e96f5a SS |
3847 | |
3848 | /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */ | |
3849 | /* If the device sent data, the status stage is an OUT transfer */ | |
3850 | if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN) | |
3851 | field = 0; | |
3852 | else | |
3853 | field = TRB_DIR_IN; | |
3b72fca0 | 3854 | queue_trb(xhci, ep_ring, false, |
d0e96f5a SS |
3855 | 0, |
3856 | 0, | |
3857 | TRB_INTR_TARGET(0), | |
3858 | /* Event on completion */ | |
3859 | field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state); | |
3860 | ||
e9df17eb | 3861 | giveback_first_trb(xhci, slot_id, ep_index, 0, |
e1eab2e0 | 3862 | start_cycle, start_trb); |
d0e96f5a SS |
3863 | return 0; |
3864 | } | |
3865 | ||
5cd43e33 SS |
3866 | /* |
3867 | * The transfer burst count field of the isochronous TRB defines the number of | |
3868 | * bursts that are required to move all packets in this TD. Only SuperSpeed | |
3869 | * devices can burst up to bMaxBurst number of packets per service interval. | |
3870 | * This field is zero based, meaning a value of zero in the field means one | |
3871 | * burst. Basically, for everything but SuperSpeed devices, this field will be | |
3872 | * zero. Only xHCI 1.0 host controllers support this field. | |
3873 | */ | |
3874 | static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci, | |
5cd43e33 SS |
3875 | struct urb *urb, unsigned int total_packet_count) |
3876 | { | |
3877 | unsigned int max_burst; | |
3878 | ||
09c352ed | 3879 | if (xhci->hci_version < 0x100 || urb->dev->speed < USB_SPEED_SUPER) |
5cd43e33 SS |
3880 | return 0; |
3881 | ||
3882 | max_burst = urb->ep->ss_ep_comp.bMaxBurst; | |
3213b151 | 3883 | return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1; |
5cd43e33 SS |
3884 | } |
3885 | ||
b61d378f SS |
3886 | /* |
3887 | * Returns the number of packets in the last "burst" of packets. This field is | |
3888 | * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so | |
3889 | * the last burst packet count is equal to the total number of packets in the | |
3890 | * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst | |
3891 | * must contain (bMaxBurst + 1) number of packets, but the last burst can | |
3892 | * contain 1 to (bMaxBurst + 1) packets. | |
3893 | */ | |
3894 | static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci, | |
b61d378f SS |
3895 | struct urb *urb, unsigned int total_packet_count) |
3896 | { | |
3897 | unsigned int max_burst; | |
3898 | unsigned int residue; | |
3899 | ||
3900 | if (xhci->hci_version < 0x100) | |
3901 | return 0; | |
3902 | ||
09c352ed | 3903 | if (urb->dev->speed >= USB_SPEED_SUPER) { |
b61d378f SS |
3904 | /* bMaxBurst is zero based: 0 means 1 packet per burst */ |
3905 | max_burst = urb->ep->ss_ep_comp.bMaxBurst; | |
3906 | residue = total_packet_count % (max_burst + 1); | |
3907 | /* If residue is zero, the last burst contains (max_burst + 1) | |
3908 | * number of packets, but the TLBPC field is zero-based. | |
3909 | */ | |
3910 | if (residue == 0) | |
3911 | return max_burst; | |
3912 | return residue - 1; | |
b61d378f | 3913 | } |
09c352ed MN |
3914 | if (total_packet_count == 0) |
3915 | return 0; | |
3916 | return total_packet_count - 1; | |
b61d378f SS |
3917 | } |
3918 | ||
79b8094f LB |
3919 | /* |
3920 | * Calculates Frame ID field of the isochronous TRB identifies the | |
3921 | * target frame that the Interval associated with this Isochronous | |
3922 | * Transfer Descriptor will start on. Refer to 4.11.2.5 in 1.1 spec. | |
3923 | * | |
3924 | * Returns actual frame id on success, negative value on error. | |
3925 | */ | |
3926 | static int xhci_get_isoc_frame_id(struct xhci_hcd *xhci, | |
3927 | struct urb *urb, int index) | |
3928 | { | |
3929 | int start_frame, ist, ret = 0; | |
3930 | int start_frame_id, end_frame_id, current_frame_id; | |
3931 | ||
3932 | if (urb->dev->speed == USB_SPEED_LOW || | |
3933 | urb->dev->speed == USB_SPEED_FULL) | |
3934 | start_frame = urb->start_frame + index * urb->interval; | |
3935 | else | |
3936 | start_frame = (urb->start_frame + index * urb->interval) >> 3; | |
3937 | ||
3938 | /* Isochronous Scheduling Threshold (IST, bits 0~3 in HCSPARAMS2): | |
3939 | * | |
3940 | * If bit [3] of IST is cleared to '0', software can add a TRB no | |
3941 | * later than IST[2:0] Microframes before that TRB is scheduled to | |
3942 | * be executed. | |
3943 | * If bit [3] of IST is set to '1', software can add a TRB no later | |
3944 | * than IST[2:0] Frames before that TRB is scheduled to be executed. | |
3945 | */ | |
3946 | ist = HCS_IST(xhci->hcs_params2) & 0x7; | |
3947 | if (HCS_IST(xhci->hcs_params2) & (1 << 3)) | |
3948 | ist <<= 3; | |
3949 | ||
3950 | /* Software shall not schedule an Isoch TD with a Frame ID value that | |
3951 | * is less than the Start Frame ID or greater than the End Frame ID, | |
3952 | * where: | |
3953 | * | |
3954 | * End Frame ID = (Current MFINDEX register value + 895 ms.) MOD 2048 | |
3955 | * Start Frame ID = (Current MFINDEX register value + IST + 1) MOD 2048 | |
3956 | * | |
3957 | * Both the End Frame ID and Start Frame ID values are calculated | |
3958 | * in microframes. When software determines the valid Frame ID value; | |
3959 | * The End Frame ID value should be rounded down to the nearest Frame | |
3960 | * boundary, and the Start Frame ID value should be rounded up to the | |
3961 | * nearest Frame boundary. | |
3962 | */ | |
3963 | current_frame_id = readl(&xhci->run_regs->microframe_index); | |
3964 | start_frame_id = roundup(current_frame_id + ist + 1, 8); | |
3965 | end_frame_id = rounddown(current_frame_id + 895 * 8, 8); | |
3966 | ||
3967 | start_frame &= 0x7ff; | |
3968 | start_frame_id = (start_frame_id >> 3) & 0x7ff; | |
3969 | end_frame_id = (end_frame_id >> 3) & 0x7ff; | |
3970 | ||
3971 | xhci_dbg(xhci, "%s: index %d, reg 0x%x start_frame_id 0x%x, end_frame_id 0x%x, start_frame 0x%x\n", | |
3972 | __func__, index, readl(&xhci->run_regs->microframe_index), | |
3973 | start_frame_id, end_frame_id, start_frame); | |
3974 | ||
3975 | if (start_frame_id < end_frame_id) { | |
3976 | if (start_frame > end_frame_id || | |
3977 | start_frame < start_frame_id) | |
3978 | ret = -EINVAL; | |
3979 | } else if (start_frame_id > end_frame_id) { | |
3980 | if ((start_frame > end_frame_id && | |
3981 | start_frame < start_frame_id)) | |
3982 | ret = -EINVAL; | |
3983 | } else { | |
3984 | ret = -EINVAL; | |
3985 | } | |
3986 | ||
3987 | if (index == 0) { | |
3988 | if (ret == -EINVAL || start_frame == start_frame_id) { | |
3989 | start_frame = start_frame_id + 1; | |
3990 | if (urb->dev->speed == USB_SPEED_LOW || | |
3991 | urb->dev->speed == USB_SPEED_FULL) | |
3992 | urb->start_frame = start_frame; | |
3993 | else | |
3994 | urb->start_frame = start_frame << 3; | |
3995 | ret = 0; | |
3996 | } | |
3997 | } | |
3998 | ||
3999 | if (ret) { | |
4000 | xhci_warn(xhci, "Frame ID %d (reg %d, index %d) beyond range (%d, %d)\n", | |
4001 | start_frame, current_frame_id, index, | |
4002 | start_frame_id, end_frame_id); | |
4003 | xhci_warn(xhci, "Ignore frame ID field, use SIA bit instead\n"); | |
4004 | return ret; | |
4005 | } | |
4006 | ||
4007 | return start_frame; | |
4008 | } | |
4009 | ||
edc649a8 MN |
4010 | /* Check if we should generate event interrupt for a TD in an isoc URB */ |
4011 | static bool trb_block_event_intr(struct xhci_hcd *xhci, int num_tds, int i) | |
4012 | { | |
4013 | if (xhci->hci_version < 0x100) | |
4014 | return false; | |
4015 | /* always generate an event interrupt for the last TD */ | |
4016 | if (i == num_tds - 1) | |
4017 | return false; | |
4018 | /* | |
4019 | * If AVOID_BEI is set the host handles full event rings poorly, | |
4020 | * generate an event at least every 8th TD to clear the event ring | |
4021 | */ | |
4022 | if (i && xhci->quirks & XHCI_AVOID_BEI) | |
90d551a5 | 4023 | return !!(i % xhci->isoc_bei_interval); |
edc649a8 MN |
4024 | |
4025 | return true; | |
4026 | } | |
4027 | ||
04e51901 AX |
4028 | /* This is for isoc transfer */ |
4029 | static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |
4030 | struct urb *urb, int slot_id, unsigned int ep_index) | |
4031 | { | |
4032 | struct xhci_ring *ep_ring; | |
4033 | struct urb_priv *urb_priv; | |
4034 | struct xhci_td *td; | |
4035 | int num_tds, trbs_per_td; | |
4036 | struct xhci_generic_trb *start_trb; | |
4037 | bool first_trb; | |
4038 | int start_cycle; | |
4039 | u32 field, length_field; | |
4040 | int running_total, trb_buff_len, td_len, td_remain_len, ret; | |
4041 | u64 start_addr, addr; | |
4042 | int i, j; | |
47cbf692 | 4043 | bool more_trbs_coming; |
79b8094f | 4044 | struct xhci_virt_ep *xep; |
09c352ed | 4045 | int frame_id; |
04e51901 | 4046 | |
79b8094f | 4047 | xep = &xhci->devs[slot_id]->eps[ep_index]; |
04e51901 AX |
4048 | ep_ring = xhci->devs[slot_id]->eps[ep_index].ring; |
4049 | ||
4050 | num_tds = urb->number_of_packets; | |
4051 | if (num_tds < 1) { | |
4052 | xhci_dbg(xhci, "Isoc URB with zero packets?\n"); | |
4053 | return -EINVAL; | |
4054 | } | |
04e51901 AX |
4055 | start_addr = (u64) urb->transfer_dma; |
4056 | start_trb = &ep_ring->enqueue->generic; | |
4057 | start_cycle = ep_ring->cycle_state; | |
4058 | ||
522989a2 | 4059 | urb_priv = urb->hcpriv; |
09c352ed | 4060 | /* Queue the TRBs for each TD, even if they are zero-length */ |
04e51901 | 4061 | for (i = 0; i < num_tds; i++) { |
09c352ed MN |
4062 | unsigned int total_pkt_count, max_pkt; |
4063 | unsigned int burst_count, last_burst_pkt_count; | |
4064 | u32 sia_frame_id; | |
04e51901 | 4065 | |
4da6e6f2 | 4066 | first_trb = true; |
04e51901 AX |
4067 | running_total = 0; |
4068 | addr = start_addr + urb->iso_frame_desc[i].offset; | |
4069 | td_len = urb->iso_frame_desc[i].length; | |
4070 | td_remain_len = td_len; | |
734d3ddd | 4071 | max_pkt = usb_endpoint_maxp(&urb->ep->desc); |
09c352ed MN |
4072 | total_pkt_count = DIV_ROUND_UP(td_len, max_pkt); |
4073 | ||
48df4a6f | 4074 | /* A zero-length transfer still involves at least one packet. */ |
09c352ed MN |
4075 | if (total_pkt_count == 0) |
4076 | total_pkt_count++; | |
4077 | burst_count = xhci_get_burst_count(xhci, urb, total_pkt_count); | |
4078 | last_burst_pkt_count = xhci_get_last_burst_packet_count(xhci, | |
4079 | urb, total_pkt_count); | |
04e51901 | 4080 | |
d2510342 | 4081 | trbs_per_td = count_isoc_trbs_needed(urb, i); |
04e51901 AX |
4082 | |
4083 | ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index, | |
3b72fca0 | 4084 | urb->stream_id, trbs_per_td, urb, i, mem_flags); |
522989a2 SS |
4085 | if (ret < 0) { |
4086 | if (i == 0) | |
4087 | return ret; | |
4088 | goto cleanup; | |
4089 | } | |
7e64b037 | 4090 | td = &urb_priv->td[i]; |
55f6153d | 4091 | td->num_trbs = trbs_per_td; |
09c352ed MN |
4092 | /* use SIA as default, if frame id is used overwrite it */ |
4093 | sia_frame_id = TRB_SIA; | |
4094 | if (!(urb->transfer_flags & URB_ISO_ASAP) && | |
4095 | HCC_CFC(xhci->hcc_params)) { | |
4096 | frame_id = xhci_get_isoc_frame_id(xhci, urb, i); | |
4097 | if (frame_id >= 0) | |
4098 | sia_frame_id = TRB_FRAME_ID(frame_id); | |
4099 | } | |
4100 | /* | |
4101 | * Set isoc specific data for the first TRB in a TD. | |
4102 | * Prevent HW from getting the TRBs by keeping the cycle state | |
4103 | * inverted in the first TDs isoc TRB. | |
4104 | */ | |
2f6d3b65 | 4105 | field = TRB_TYPE(TRB_ISOC) | |
09c352ed MN |
4106 | TRB_TLBPC(last_burst_pkt_count) | |
4107 | sia_frame_id | | |
4108 | (i ? ep_ring->cycle_state : !start_cycle); | |
4109 | ||
2f6d3b65 MN |
4110 | /* xhci 1.1 with ETE uses TD_Size field for TBC, old is Rsvdz */ |
4111 | if (!xep->use_extended_tbc) | |
4112 | field |= TRB_TBC(burst_count); | |
4113 | ||
09c352ed | 4114 | /* fill the rest of the TRB fields, and remaining normal TRBs */ |
04e51901 AX |
4115 | for (j = 0; j < trbs_per_td; j++) { |
4116 | u32 remainder = 0; | |
09c352ed MN |
4117 | |
4118 | /* only first TRB is isoc, overwrite otherwise */ | |
4119 | if (!first_trb) | |
4120 | field = TRB_TYPE(TRB_NORMAL) | | |
4121 | ep_ring->cycle_state; | |
04e51901 | 4122 | |
af8b9e63 SS |
4123 | /* Only set interrupt on short packet for IN EPs */ |
4124 | if (usb_urb_dir_in(urb)) | |
4125 | field |= TRB_ISP; | |
4126 | ||
09c352ed | 4127 | /* Set the chain bit for all except the last TRB */ |
04e51901 | 4128 | if (j < trbs_per_td - 1) { |
47cbf692 | 4129 | more_trbs_coming = true; |
09c352ed | 4130 | field |= TRB_CHAIN; |
04e51901 | 4131 | } else { |
09c352ed | 4132 | more_trbs_coming = false; |
04e51901 | 4133 | td->last_trb = ep_ring->enqueue; |
55f6153d | 4134 | td->last_trb_seg = ep_ring->enq_seg; |
04e51901 | 4135 | field |= TRB_IOC; |
edc649a8 | 4136 | if (trb_block_event_intr(xhci, num_tds, i)) |
09c352ed | 4137 | field |= TRB_BEI; |
04e51901 | 4138 | } |
04e51901 | 4139 | /* Calculate TRB length */ |
d2510342 | 4140 | trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr); |
04e51901 AX |
4141 | if (trb_buff_len > td_remain_len) |
4142 | trb_buff_len = td_remain_len; | |
4143 | ||
4da6e6f2 | 4144 | /* Set the TRB length, TD size, & interrupter fields. */ |
c840d6ce MN |
4145 | remainder = xhci_td_remainder(xhci, running_total, |
4146 | trb_buff_len, td_len, | |
124c3937 | 4147 | urb, more_trbs_coming); |
c840d6ce | 4148 | |
04e51901 | 4149 | length_field = TRB_LEN(trb_buff_len) | |
04e51901 | 4150 | TRB_INTR_TARGET(0); |
4da6e6f2 | 4151 | |
2f6d3b65 MN |
4152 | /* xhci 1.1 with ETE uses TD Size field for TBC */ |
4153 | if (first_trb && xep->use_extended_tbc) | |
4154 | length_field |= TRB_TD_SIZE_TBC(burst_count); | |
4155 | else | |
4156 | length_field |= TRB_TD_SIZE(remainder); | |
4157 | first_trb = false; | |
4158 | ||
3b72fca0 | 4159 | queue_trb(xhci, ep_ring, more_trbs_coming, |
04e51901 AX |
4160 | lower_32_bits(addr), |
4161 | upper_32_bits(addr), | |
4162 | length_field, | |
af8b9e63 | 4163 | field); |
04e51901 AX |
4164 | running_total += trb_buff_len; |
4165 | ||
4166 | addr += trb_buff_len; | |
4167 | td_remain_len -= trb_buff_len; | |
4168 | } | |
4169 | ||
4170 | /* Check TD length */ | |
4171 | if (running_total != td_len) { | |
4172 | xhci_err(xhci, "ISOC TD length unmatch\n"); | |
cf840551 AX |
4173 | ret = -EINVAL; |
4174 | goto cleanup; | |
04e51901 AX |
4175 | } |
4176 | } | |
4177 | ||
79b8094f LB |
4178 | /* store the next frame id */ |
4179 | if (HCC_CFC(xhci->hcc_params)) | |
4180 | xep->next_frame_id = urb->start_frame + num_tds * urb->interval; | |
4181 | ||
c41136b0 AX |
4182 | if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) { |
4183 | if (xhci->quirks & XHCI_AMD_PLL_FIX) | |
4184 | usb_amd_quirk_pll_disable(); | |
4185 | } | |
4186 | xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++; | |
4187 | ||
e1eab2e0 AX |
4188 | giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, |
4189 | start_cycle, start_trb); | |
04e51901 | 4190 | return 0; |
522989a2 SS |
4191 | cleanup: |
4192 | /* Clean up a partially enqueued isoc transfer. */ | |
4193 | ||
4194 | for (i--; i >= 0; i--) | |
7e64b037 | 4195 | list_del_init(&urb_priv->td[i].td_list); |
522989a2 SS |
4196 | |
4197 | /* Use the first TD as a temporary variable to turn the TDs we've queued | |
4198 | * into No-ops with a software-owned cycle bit. That way the hardware | |
4199 | * won't accidentally start executing bogus TDs when we partially | |
4200 | * overwrite them. td->first_trb and td->start_seg are already set. | |
4201 | */ | |
7e64b037 | 4202 | urb_priv->td[0].last_trb = ep_ring->enqueue; |
522989a2 | 4203 | /* Every TRB except the first & last will have its cycle bit flipped. */ |
7e64b037 | 4204 | td_to_noop(xhci, ep_ring, &urb_priv->td[0], true); |
522989a2 SS |
4205 | |
4206 | /* Reset the ring enqueue back to the first TRB and its cycle bit. */ | |
7e64b037 MN |
4207 | ep_ring->enqueue = urb_priv->td[0].first_trb; |
4208 | ep_ring->enq_seg = urb_priv->td[0].start_seg; | |
522989a2 | 4209 | ep_ring->cycle_state = start_cycle; |
b008df60 | 4210 | ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp; |
522989a2 SS |
4211 | usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb); |
4212 | return ret; | |
04e51901 AX |
4213 | } |
4214 | ||
4215 | /* | |
4216 | * Check transfer ring to guarantee there is enough room for the urb. | |
4217 | * Update ISO URB start_frame and interval. | |
79b8094f LB |
4218 | * Update interval as xhci_queue_intr_tx does. Use xhci frame_index to |
4219 | * update urb->start_frame if URB_ISO_ASAP is set in transfer_flags or | |
4220 | * Contiguous Frame ID is not supported by HC. | |
04e51901 AX |
4221 | */ |
4222 | int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags, | |
4223 | struct urb *urb, int slot_id, unsigned int ep_index) | |
4224 | { | |
4225 | struct xhci_virt_device *xdev; | |
4226 | struct xhci_ring *ep_ring; | |
4227 | struct xhci_ep_ctx *ep_ctx; | |
4228 | int start_frame; | |
04e51901 AX |
4229 | int num_tds, num_trbs, i; |
4230 | int ret; | |
79b8094f LB |
4231 | struct xhci_virt_ep *xep; |
4232 | int ist; | |
04e51901 AX |
4233 | |
4234 | xdev = xhci->devs[slot_id]; | |
79b8094f | 4235 | xep = &xhci->devs[slot_id]->eps[ep_index]; |
04e51901 AX |
4236 | ep_ring = xdev->eps[ep_index].ring; |
4237 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); | |
4238 | ||
4239 | num_trbs = 0; | |
4240 | num_tds = urb->number_of_packets; | |
4241 | for (i = 0; i < num_tds; i++) | |
d2510342 | 4242 | num_trbs += count_isoc_trbs_needed(urb, i); |
04e51901 AX |
4243 | |
4244 | /* Check the ring to guarantee there is enough room for the whole urb. | |
4245 | * Do not insert any td of the urb to the ring if the check failed. | |
4246 | */ | |
5071e6b2 | 4247 | ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx), |
3b72fca0 | 4248 | num_trbs, mem_flags); |
04e51901 AX |
4249 | if (ret) |
4250 | return ret; | |
4251 | ||
79b8094f LB |
4252 | /* |
4253 | * Check interval value. This should be done before we start to | |
4254 | * calculate the start frame value. | |
4255 | */ | |
78140156 | 4256 | check_interval(xhci, urb, ep_ctx); |
79b8094f LB |
4257 | |
4258 | /* Calculate the start frame and put it in urb->start_frame. */ | |
42df7215 | 4259 | if (HCC_CFC(xhci->hcc_params) && !list_empty(&ep_ring->td_list)) { |
5071e6b2 | 4260 | if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_RUNNING) { |
42df7215 LB |
4261 | urb->start_frame = xep->next_frame_id; |
4262 | goto skip_start_over; | |
4263 | } | |
79b8094f LB |
4264 | } |
4265 | ||
4266 | start_frame = readl(&xhci->run_regs->microframe_index); | |
4267 | start_frame &= 0x3fff; | |
4268 | /* | |
4269 | * Round up to the next frame and consider the time before trb really | |
4270 | * gets scheduled by hardare. | |
4271 | */ | |
4272 | ist = HCS_IST(xhci->hcs_params2) & 0x7; | |
4273 | if (HCS_IST(xhci->hcs_params2) & (1 << 3)) | |
4274 | ist <<= 3; | |
4275 | start_frame += ist + XHCI_CFC_DELAY; | |
4276 | start_frame = roundup(start_frame, 8); | |
4277 | ||
4278 | /* | |
4279 | * Round up to the next ESIT (Endpoint Service Interval Time) if ESIT | |
4280 | * is greate than 8 microframes. | |
4281 | */ | |
4282 | if (urb->dev->speed == USB_SPEED_LOW || | |
4283 | urb->dev->speed == USB_SPEED_FULL) { | |
4284 | start_frame = roundup(start_frame, urb->interval << 3); | |
4285 | urb->start_frame = start_frame >> 3; | |
4286 | } else { | |
4287 | start_frame = roundup(start_frame, urb->interval); | |
4288 | urb->start_frame = start_frame; | |
4289 | } | |
4290 | ||
4291 | skip_start_over: | |
b008df60 AX |
4292 | ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free; |
4293 | ||
3fc8206d | 4294 | return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index); |
04e51901 AX |
4295 | } |
4296 | ||
d0e96f5a SS |
4297 | /**** Command Ring Operations ****/ |
4298 | ||
913a8a34 SS |
4299 | /* Generic function for queueing a command TRB on the command ring. |
4300 | * Check to make sure there's room on the command ring for one command TRB. | |
4301 | * Also check that there's room reserved for commands that must not fail. | |
4302 | * If this is a command that must not fail, meaning command_must_succeed = TRUE, | |
4303 | * then only check for the number of reserved spots. | |
4304 | * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB | |
4305 | * because the command event handler may want to resubmit a failed command. | |
4306 | */ | |
ddba5cd0 MN |
4307 | static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd, |
4308 | u32 field1, u32 field2, | |
4309 | u32 field3, u32 field4, bool command_must_succeed) | |
7f84eef0 | 4310 | { |
913a8a34 | 4311 | int reserved_trbs = xhci->cmd_ring_reserved_trbs; |
d1dc908a | 4312 | int ret; |
ad6b1d91 | 4313 | |
98d74f9c MN |
4314 | if ((xhci->xhc_state & XHCI_STATE_DYING) || |
4315 | (xhci->xhc_state & XHCI_STATE_HALTED)) { | |
ad6b1d91 | 4316 | xhci_dbg(xhci, "xHCI dying or halted, can't queue_command\n"); |
c9aa1a2d | 4317 | return -ESHUTDOWN; |
ad6b1d91 | 4318 | } |
d1dc908a | 4319 | |
913a8a34 SS |
4320 | if (!command_must_succeed) |
4321 | reserved_trbs++; | |
4322 | ||
d1dc908a | 4323 | ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING, |
3b72fca0 | 4324 | reserved_trbs, GFP_ATOMIC); |
d1dc908a SS |
4325 | if (ret < 0) { |
4326 | xhci_err(xhci, "ERR: No room for command on command ring\n"); | |
913a8a34 SS |
4327 | if (command_must_succeed) |
4328 | xhci_err(xhci, "ERR: Reserved TRB counting for " | |
4329 | "unfailable commands failed.\n"); | |
d1dc908a | 4330 | return ret; |
7f84eef0 | 4331 | } |
c9aa1a2d MN |
4332 | |
4333 | cmd->command_trb = xhci->cmd_ring->enqueue; | |
ddba5cd0 | 4334 | |
c311e391 | 4335 | /* if there are no other commands queued we start the timeout timer */ |
daa47f21 | 4336 | if (list_empty(&xhci->cmd_list)) { |
c311e391 | 4337 | xhci->current_cmd = cmd; |
cb4d5ce5 | 4338 | xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT); |
c311e391 MN |
4339 | } |
4340 | ||
daa47f21 LB |
4341 | list_add_tail(&cmd->cmd_list, &xhci->cmd_list); |
4342 | ||
3b72fca0 AX |
4343 | queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3, |
4344 | field4 | xhci->cmd_ring->cycle_state); | |
7f84eef0 SS |
4345 | return 0; |
4346 | } | |
4347 | ||
3ffbba95 | 4348 | /* Queue a slot enable or disable request on the command ring */ |
ddba5cd0 MN |
4349 | int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd, |
4350 | u32 trb_type, u32 slot_id) | |
3ffbba95 | 4351 | { |
ddba5cd0 | 4352 | return queue_command(xhci, cmd, 0, 0, 0, |
913a8a34 | 4353 | TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false); |
3ffbba95 SS |
4354 | } |
4355 | ||
4356 | /* Queue an address device command TRB */ | |
ddba5cd0 MN |
4357 | int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd, |
4358 | dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev setup) | |
3ffbba95 | 4359 | { |
ddba5cd0 | 4360 | return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr), |
8e595a5d | 4361 | upper_32_bits(in_ctx_ptr), 0, |
48fc7dbd DW |
4362 | TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id) |
4363 | | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false); | |
2a8f82c4 SS |
4364 | } |
4365 | ||
ddba5cd0 | 4366 | int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd, |
0238634d SS |
4367 | u32 field1, u32 field2, u32 field3, u32 field4) |
4368 | { | |
ddba5cd0 | 4369 | return queue_command(xhci, cmd, field1, field2, field3, field4, false); |
0238634d SS |
4370 | } |
4371 | ||
2a8f82c4 | 4372 | /* Queue a reset device command TRB */ |
ddba5cd0 MN |
4373 | int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd, |
4374 | u32 slot_id) | |
2a8f82c4 | 4375 | { |
ddba5cd0 | 4376 | return queue_command(xhci, cmd, 0, 0, 0, |
2a8f82c4 | 4377 | TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id), |
913a8a34 | 4378 | false); |
3ffbba95 | 4379 | } |
f94e0186 SS |
4380 | |
4381 | /* Queue a configure endpoint command TRB */ | |
ddba5cd0 MN |
4382 | int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, |
4383 | struct xhci_command *cmd, dma_addr_t in_ctx_ptr, | |
913a8a34 | 4384 | u32 slot_id, bool command_must_succeed) |
f94e0186 | 4385 | { |
ddba5cd0 | 4386 | return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr), |
8e595a5d | 4387 | upper_32_bits(in_ctx_ptr), 0, |
913a8a34 SS |
4388 | TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id), |
4389 | command_must_succeed); | |
f94e0186 | 4390 | } |
ae636747 | 4391 | |
f2217e8e | 4392 | /* Queue an evaluate context command TRB */ |
ddba5cd0 MN |
4393 | int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd, |
4394 | dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed) | |
f2217e8e | 4395 | { |
ddba5cd0 | 4396 | return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr), |
f2217e8e | 4397 | upper_32_bits(in_ctx_ptr), 0, |
913a8a34 | 4398 | TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id), |
4b266541 | 4399 | command_must_succeed); |
f2217e8e SS |
4400 | } |
4401 | ||
be88fe4f AX |
4402 | /* |
4403 | * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop | |
4404 | * activity on an endpoint that is about to be suspended. | |
4405 | */ | |
ddba5cd0 MN |
4406 | int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd, |
4407 | int slot_id, unsigned int ep_index, int suspend) | |
ae636747 SS |
4408 | { |
4409 | u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); | |
4410 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); | |
4411 | u32 type = TRB_TYPE(TRB_STOP_RING); | |
be88fe4f | 4412 | u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend); |
ae636747 | 4413 | |
ddba5cd0 | 4414 | return queue_command(xhci, cmd, 0, 0, 0, |
be88fe4f | 4415 | trb_slot_id | trb_ep_index | type | trb_suspend, false); |
ae636747 SS |
4416 | } |
4417 | ||
ddba5cd0 | 4418 | int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd, |
21749148 MN |
4419 | int slot_id, unsigned int ep_index, |
4420 | enum xhci_ep_reset_type reset_type) | |
a1587d97 SS |
4421 | { |
4422 | u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); | |
4423 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); | |
4424 | u32 type = TRB_TYPE(TRB_RESET_EP); | |
4425 | ||
21749148 MN |
4426 | if (reset_type == EP_SOFT_RESET) |
4427 | type |= TRB_TSP; | |
4428 | ||
ddba5cd0 MN |
4429 | return queue_command(xhci, cmd, 0, 0, 0, |
4430 | trb_slot_id | trb_ep_index | type, false); | |
a1587d97 | 4431 | } |