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Commit | Line | Data |
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7f84eef0 SS |
1 | /* |
2 | * xHCI host controller driver | |
3 | * | |
4 | * Copyright (C) 2008 Intel Corp. | |
5 | * | |
6 | * Author: Sarah Sharp | |
7 | * Some code borrowed from the Linux EHCI driver. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | * for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software Foundation, | |
20 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
23 | /* | |
24 | * Ring initialization rules: | |
25 | * 1. Each segment is initialized to zero, except for link TRBs. | |
26 | * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or | |
27 | * Consumer Cycle State (CCS), depending on ring function. | |
28 | * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment. | |
29 | * | |
30 | * Ring behavior rules: | |
31 | * 1. A ring is empty if enqueue == dequeue. This means there will always be at | |
32 | * least one free TRB in the ring. This is useful if you want to turn that | |
33 | * into a link TRB and expand the ring. | |
34 | * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a | |
35 | * link TRB, then load the pointer with the address in the link TRB. If the | |
36 | * link TRB had its toggle bit set, you may need to update the ring cycle | |
37 | * state (see cycle bit rules). You may have to do this multiple times | |
38 | * until you reach a non-link TRB. | |
39 | * 3. A ring is full if enqueue++ (for the definition of increment above) | |
40 | * equals the dequeue pointer. | |
41 | * | |
42 | * Cycle bit rules: | |
43 | * 1. When a consumer increments a dequeue pointer and encounters a toggle bit | |
44 | * in a link TRB, it must toggle the ring cycle state. | |
45 | * 2. When a producer increments an enqueue pointer and encounters a toggle bit | |
46 | * in a link TRB, it must toggle the ring cycle state. | |
47 | * | |
48 | * Producer rules: | |
49 | * 1. Check if ring is full before you enqueue. | |
50 | * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing. | |
51 | * Update enqueue pointer between each write (which may update the ring | |
52 | * cycle state). | |
53 | * 3. Notify consumer. If SW is producer, it rings the doorbell for command | |
54 | * and endpoint rings. If HC is the producer for the event ring, | |
55 | * and it generates an interrupt according to interrupt modulation rules. | |
56 | * | |
57 | * Consumer rules: | |
58 | * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state, | |
59 | * the TRB is owned by the consumer. | |
60 | * 2. Update dequeue pointer (which may update the ring cycle state) and | |
61 | * continue processing TRBs until you reach a TRB which is not owned by you. | |
62 | * 3. Notify the producer. SW is the consumer for the event ring, and it | |
63 | * updates event ring dequeue pointer. HC is the consumer for the command and | |
64 | * endpoint rings; it generates events on the event ring for these. | |
65 | */ | |
66 | ||
8a96c052 | 67 | #include <linux/scatterlist.h> |
5a0e3ad6 | 68 | #include <linux/slab.h> |
7f84eef0 | 69 | #include "xhci.h" |
3a7fa5be | 70 | #include "xhci-trace.h" |
7f84eef0 SS |
71 | |
72 | /* | |
73 | * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA | |
74 | * address of the TRB. | |
75 | */ | |
23e3be11 | 76 | dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, |
7f84eef0 SS |
77 | union xhci_trb *trb) |
78 | { | |
6071d836 | 79 | unsigned long segment_offset; |
7f84eef0 | 80 | |
6071d836 | 81 | if (!seg || !trb || trb < seg->trbs) |
7f84eef0 | 82 | return 0; |
6071d836 SS |
83 | /* offset in TRBs */ |
84 | segment_offset = trb - seg->trbs; | |
85 | if (segment_offset > TRBS_PER_SEGMENT) | |
7f84eef0 | 86 | return 0; |
6071d836 | 87 | return seg->dma + (segment_offset * sizeof(*trb)); |
7f84eef0 SS |
88 | } |
89 | ||
90 | /* Does this link TRB point to the first segment in a ring, | |
91 | * or was the previous TRB the last TRB on the last segment in the ERST? | |
92 | */ | |
575688e1 | 93 | static bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring, |
7f84eef0 SS |
94 | struct xhci_segment *seg, union xhci_trb *trb) |
95 | { | |
96 | if (ring == xhci->event_ring) | |
97 | return (trb == &seg->trbs[TRBS_PER_SEGMENT]) && | |
98 | (seg->next == xhci->event_ring->first_seg); | |
99 | else | |
28ccd296 | 100 | return le32_to_cpu(trb->link.control) & LINK_TOGGLE; |
7f84eef0 SS |
101 | } |
102 | ||
103 | /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring | |
104 | * segment? I.e. would the updated event TRB pointer step off the end of the | |
105 | * event seg? | |
106 | */ | |
575688e1 | 107 | static int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring, |
7f84eef0 SS |
108 | struct xhci_segment *seg, union xhci_trb *trb) |
109 | { | |
110 | if (ring == xhci->event_ring) | |
111 | return trb == &seg->trbs[TRBS_PER_SEGMENT]; | |
112 | else | |
f5960b69 | 113 | return TRB_TYPE_LINK_LE32(trb->link.control); |
7f84eef0 SS |
114 | } |
115 | ||
575688e1 | 116 | static int enqueue_is_link_trb(struct xhci_ring *ring) |
6c12db90 JY |
117 | { |
118 | struct xhci_link_trb *link = &ring->enqueue->link; | |
f5960b69 | 119 | return TRB_TYPE_LINK_LE32(link->control); |
6c12db90 JY |
120 | } |
121 | ||
ae636747 SS |
122 | /* Updates trb to point to the next TRB in the ring, and updates seg if the next |
123 | * TRB is in a new segment. This does not skip over link TRBs, and it does not | |
124 | * effect the ring dequeue or enqueue pointers. | |
125 | */ | |
126 | static void next_trb(struct xhci_hcd *xhci, | |
127 | struct xhci_ring *ring, | |
128 | struct xhci_segment **seg, | |
129 | union xhci_trb **trb) | |
130 | { | |
131 | if (last_trb(xhci, ring, *seg, *trb)) { | |
132 | *seg = (*seg)->next; | |
133 | *trb = ((*seg)->trbs); | |
134 | } else { | |
a1669b2c | 135 | (*trb)++; |
ae636747 SS |
136 | } |
137 | } | |
138 | ||
7f84eef0 SS |
139 | /* |
140 | * See Cycle bit rules. SW is the consumer for the event ring only. | |
141 | * Don't make a ring full of link TRBs. That would be dumb and this would loop. | |
142 | */ | |
3b72fca0 | 143 | static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring) |
7f84eef0 | 144 | { |
7f84eef0 | 145 | ring->deq_updates++; |
b008df60 | 146 | |
50d0206f SS |
147 | /* |
148 | * If this is not event ring, and the dequeue pointer | |
149 | * is not on a link TRB, there is one more usable TRB | |
150 | */ | |
b008df60 AX |
151 | if (ring->type != TYPE_EVENT && |
152 | !last_trb(xhci, ring, ring->deq_seg, ring->dequeue)) | |
153 | ring->num_trbs_free++; | |
b008df60 | 154 | |
50d0206f SS |
155 | do { |
156 | /* | |
157 | * Update the dequeue pointer further if that was a link TRB or | |
158 | * we're at the end of an event ring segment (which doesn't have | |
159 | * link TRBS) | |
160 | */ | |
161 | if (last_trb(xhci, ring, ring->deq_seg, ring->dequeue)) { | |
162 | if (ring->type == TYPE_EVENT && | |
163 | last_trb_on_last_seg(xhci, ring, | |
164 | ring->deq_seg, ring->dequeue)) { | |
4e341818 | 165 | ring->cycle_state ^= 1; |
50d0206f SS |
166 | } |
167 | ring->deq_seg = ring->deq_seg->next; | |
168 | ring->dequeue = ring->deq_seg->trbs; | |
169 | } else { | |
170 | ring->dequeue++; | |
7f84eef0 | 171 | } |
50d0206f | 172 | } while (last_trb(xhci, ring, ring->deq_seg, ring->dequeue)); |
7f84eef0 SS |
173 | } |
174 | ||
175 | /* | |
176 | * See Cycle bit rules. SW is the consumer for the event ring only. | |
177 | * Don't make a ring full of link TRBs. That would be dumb and this would loop. | |
178 | * | |
179 | * If we've just enqueued a TRB that is in the middle of a TD (meaning the | |
180 | * chain bit is set), then set the chain bit in all the following link TRBs. | |
181 | * If we've enqueued the last TRB in a TD, make sure the following link TRBs | |
182 | * have their chain bit cleared (so that each Link TRB is a separate TD). | |
183 | * | |
184 | * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit | |
b0567b3f SS |
185 | * set, but other sections talk about dealing with the chain bit set. This was |
186 | * fixed in the 0.96 specification errata, but we have to assume that all 0.95 | |
187 | * xHCI hardware can't handle the chain bit being cleared on a link TRB. | |
6cc30d85 SS |
188 | * |
189 | * @more_trbs_coming: Will you enqueue more TRBs before calling | |
190 | * prepare_transfer()? | |
7f84eef0 | 191 | */ |
6cc30d85 | 192 | static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring, |
3b72fca0 | 193 | bool more_trbs_coming) |
7f84eef0 SS |
194 | { |
195 | u32 chain; | |
196 | union xhci_trb *next; | |
197 | ||
28ccd296 | 198 | chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN; |
b008df60 AX |
199 | /* If this is not event ring, there is one less usable TRB */ |
200 | if (ring->type != TYPE_EVENT && | |
201 | !last_trb(xhci, ring, ring->enq_seg, ring->enqueue)) | |
202 | ring->num_trbs_free--; | |
7f84eef0 SS |
203 | next = ++(ring->enqueue); |
204 | ||
205 | ring->enq_updates++; | |
206 | /* Update the dequeue pointer further if that was a link TRB or we're at | |
207 | * the end of an event ring segment (which doesn't have link TRBS) | |
208 | */ | |
209 | while (last_trb(xhci, ring, ring->enq_seg, next)) { | |
3b72fca0 AX |
210 | if (ring->type != TYPE_EVENT) { |
211 | /* | |
212 | * If the caller doesn't plan on enqueueing more | |
213 | * TDs before ringing the doorbell, then we | |
214 | * don't want to give the link TRB to the | |
215 | * hardware just yet. We'll give the link TRB | |
216 | * back in prepare_ring() just before we enqueue | |
217 | * the TD at the top of the ring. | |
218 | */ | |
219 | if (!chain && !more_trbs_coming) | |
220 | break; | |
6cc30d85 | 221 | |
3b72fca0 AX |
222 | /* If we're not dealing with 0.95 hardware or |
223 | * isoc rings on AMD 0.96 host, | |
224 | * carry over the chain bit of the previous TRB | |
225 | * (which may mean the chain bit is cleared). | |
226 | */ | |
227 | if (!(ring->type == TYPE_ISOC && | |
228 | (xhci->quirks & XHCI_AMD_0x96_HOST)) | |
7e393a83 | 229 | && !xhci_link_trb_quirk(xhci)) { |
3b72fca0 AX |
230 | next->link.control &= |
231 | cpu_to_le32(~TRB_CHAIN); | |
232 | next->link.control |= | |
233 | cpu_to_le32(chain); | |
7f84eef0 | 234 | } |
3b72fca0 AX |
235 | /* Give this link TRB to the hardware */ |
236 | wmb(); | |
237 | next->link.control ^= cpu_to_le32(TRB_CYCLE); | |
238 | ||
7f84eef0 SS |
239 | /* Toggle the cycle bit after the last ring segment. */ |
240 | if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) { | |
e5401bf3 | 241 | ring->cycle_state ^= 1; |
7f84eef0 SS |
242 | } |
243 | } | |
244 | ring->enq_seg = ring->enq_seg->next; | |
245 | ring->enqueue = ring->enq_seg->trbs; | |
246 | next = ring->enqueue; | |
247 | } | |
248 | } | |
249 | ||
250 | /* | |
085deb16 AX |
251 | * Check to see if there's room to enqueue num_trbs on the ring and make sure |
252 | * enqueue pointer will not advance into dequeue segment. See rules above. | |
7f84eef0 | 253 | */ |
b008df60 | 254 | static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring, |
7f84eef0 SS |
255 | unsigned int num_trbs) |
256 | { | |
085deb16 | 257 | int num_trbs_in_deq_seg; |
b008df60 | 258 | |
085deb16 AX |
259 | if (ring->num_trbs_free < num_trbs) |
260 | return 0; | |
261 | ||
262 | if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) { | |
263 | num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs; | |
264 | if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg) | |
265 | return 0; | |
266 | } | |
267 | ||
268 | return 1; | |
7f84eef0 SS |
269 | } |
270 | ||
7f84eef0 | 271 | /* Ring the host controller doorbell after placing a command on the ring */ |
23e3be11 | 272 | void xhci_ring_cmd_db(struct xhci_hcd *xhci) |
7f84eef0 | 273 | { |
c181bc5b EF |
274 | if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING)) |
275 | return; | |
276 | ||
7f84eef0 | 277 | xhci_dbg(xhci, "// Ding dong!\n"); |
204b7793 | 278 | writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]); |
7f84eef0 | 279 | /* Flush PCI posted writes */ |
b0ba9720 | 280 | readl(&xhci->dba->doorbell[0]); |
7f84eef0 SS |
281 | } |
282 | ||
b92cc66c EF |
283 | static int xhci_abort_cmd_ring(struct xhci_hcd *xhci) |
284 | { | |
285 | u64 temp_64; | |
286 | int ret; | |
287 | ||
288 | xhci_dbg(xhci, "Abort command ring\n"); | |
289 | ||
f7b2e403 | 290 | temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring); |
b92cc66c | 291 | xhci->cmd_ring_state = CMD_RING_STATE_ABORTED; |
477632df SS |
292 | xhci_write_64(xhci, temp_64 | CMD_RING_ABORT, |
293 | &xhci->op_regs->cmd_ring); | |
b92cc66c EF |
294 | |
295 | /* Section 4.6.1.2 of xHCI 1.0 spec says software should | |
296 | * time the completion od all xHCI commands, including | |
297 | * the Command Abort operation. If software doesn't see | |
298 | * CRR negated in a timely manner (e.g. longer than 5 | |
299 | * seconds), then it should assume that the there are | |
300 | * larger problems with the xHC and assert HCRST. | |
301 | */ | |
dc0b177c | 302 | ret = xhci_handshake(&xhci->op_regs->cmd_ring, |
b92cc66c EF |
303 | CMD_RING_RUNNING, 0, 5 * 1000 * 1000); |
304 | if (ret < 0) { | |
305 | xhci_err(xhci, "Stopped the command ring failed, " | |
306 | "maybe the host is dead\n"); | |
307 | xhci->xhc_state |= XHCI_STATE_DYING; | |
308 | xhci_quiesce(xhci); | |
309 | xhci_halt(xhci); | |
310 | return -ESHUTDOWN; | |
311 | } | |
312 | ||
313 | return 0; | |
314 | } | |
315 | ||
be88fe4f | 316 | void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, |
ae636747 | 317 | unsigned int slot_id, |
e9df17eb SS |
318 | unsigned int ep_index, |
319 | unsigned int stream_id) | |
ae636747 | 320 | { |
28ccd296 | 321 | __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id]; |
50d64676 MW |
322 | struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index]; |
323 | unsigned int ep_state = ep->ep_state; | |
ae636747 | 324 | |
ae636747 | 325 | /* Don't ring the doorbell for this endpoint if there are pending |
50d64676 | 326 | * cancellations because we don't want to interrupt processing. |
8df75f42 SS |
327 | * We don't want to restart any stream rings if there's a set dequeue |
328 | * pointer command pending because the device can choose to start any | |
329 | * stream once the endpoint is on the HW schedule. | |
ae636747 | 330 | */ |
50d64676 MW |
331 | if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) || |
332 | (ep_state & EP_HALTED)) | |
333 | return; | |
204b7793 | 334 | writel(DB_VALUE(ep_index, stream_id), db_addr); |
50d64676 MW |
335 | /* The CPU has better things to do at this point than wait for a |
336 | * write-posting flush. It'll get there soon enough. | |
337 | */ | |
ae636747 SS |
338 | } |
339 | ||
e9df17eb SS |
340 | /* Ring the doorbell for any rings with pending URBs */ |
341 | static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci, | |
342 | unsigned int slot_id, | |
343 | unsigned int ep_index) | |
344 | { | |
345 | unsigned int stream_id; | |
346 | struct xhci_virt_ep *ep; | |
347 | ||
348 | ep = &xhci->devs[slot_id]->eps[ep_index]; | |
349 | ||
350 | /* A ring has pending URBs if its TD list is not empty */ | |
351 | if (!(ep->ep_state & EP_HAS_STREAMS)) { | |
d66eaf9f | 352 | if (ep->ring && !(list_empty(&ep->ring->td_list))) |
be88fe4f | 353 | xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0); |
e9df17eb SS |
354 | return; |
355 | } | |
356 | ||
357 | for (stream_id = 1; stream_id < ep->stream_info->num_streams; | |
358 | stream_id++) { | |
359 | struct xhci_stream_info *stream_info = ep->stream_info; | |
360 | if (!list_empty(&stream_info->stream_rings[stream_id]->td_list)) | |
be88fe4f AX |
361 | xhci_ring_ep_doorbell(xhci, slot_id, ep_index, |
362 | stream_id); | |
e9df17eb SS |
363 | } |
364 | } | |
365 | ||
021bff91 SS |
366 | static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci, |
367 | unsigned int slot_id, unsigned int ep_index, | |
368 | unsigned int stream_id) | |
369 | { | |
370 | struct xhci_virt_ep *ep; | |
371 | ||
372 | ep = &xhci->devs[slot_id]->eps[ep_index]; | |
373 | /* Common case: no streams */ | |
374 | if (!(ep->ep_state & EP_HAS_STREAMS)) | |
375 | return ep->ring; | |
376 | ||
377 | if (stream_id == 0) { | |
378 | xhci_warn(xhci, | |
379 | "WARN: Slot ID %u, ep index %u has streams, " | |
380 | "but URB has no stream ID.\n", | |
381 | slot_id, ep_index); | |
382 | return NULL; | |
383 | } | |
384 | ||
385 | if (stream_id < ep->stream_info->num_streams) | |
386 | return ep->stream_info->stream_rings[stream_id]; | |
387 | ||
388 | xhci_warn(xhci, | |
389 | "WARN: Slot ID %u, ep index %u has " | |
390 | "stream IDs 1 to %u allocated, " | |
391 | "but stream ID %u is requested.\n", | |
392 | slot_id, ep_index, | |
393 | ep->stream_info->num_streams - 1, | |
394 | stream_id); | |
395 | return NULL; | |
396 | } | |
397 | ||
398 | /* Get the right ring for the given URB. | |
399 | * If the endpoint supports streams, boundary check the URB's stream ID. | |
400 | * If the endpoint doesn't support streams, return the singular endpoint ring. | |
401 | */ | |
402 | static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci, | |
403 | struct urb *urb) | |
404 | { | |
405 | return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id, | |
406 | xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id); | |
407 | } | |
408 | ||
ae636747 SS |
409 | /* |
410 | * Move the xHC's endpoint ring dequeue pointer past cur_td. | |
411 | * Record the new state of the xHC's endpoint ring dequeue segment, | |
412 | * dequeue pointer, and new consumer cycle state in state. | |
413 | * Update our internal representation of the ring's dequeue pointer. | |
414 | * | |
415 | * We do this in three jumps: | |
416 | * - First we update our new ring state to be the same as when the xHC stopped. | |
417 | * - Then we traverse the ring to find the segment that contains | |
418 | * the last TRB in the TD. We toggle the xHC's new cycle state when we pass | |
419 | * any link TRBs with the toggle cycle bit set. | |
420 | * - Finally we move the dequeue state one TRB further, toggling the cycle bit | |
421 | * if we've moved it past a link TRB with the toggle cycle bit set. | |
28ccd296 ME |
422 | * |
423 | * Some of the uses of xhci_generic_trb are grotty, but if they're done | |
424 | * with correct __le32 accesses they should work fine. Only users of this are | |
425 | * in here. | |
ae636747 | 426 | */ |
c92bcfa7 | 427 | void xhci_find_new_dequeue_state(struct xhci_hcd *xhci, |
ae636747 | 428 | unsigned int slot_id, unsigned int ep_index, |
e9df17eb SS |
429 | unsigned int stream_id, struct xhci_td *cur_td, |
430 | struct xhci_dequeue_state *state) | |
ae636747 SS |
431 | { |
432 | struct xhci_virt_device *dev = xhci->devs[slot_id]; | |
c4bedb77 | 433 | struct xhci_virt_ep *ep = &dev->eps[ep_index]; |
e9df17eb | 434 | struct xhci_ring *ep_ring; |
365038d8 MN |
435 | struct xhci_segment *new_seg; |
436 | union xhci_trb *new_deq; | |
c92bcfa7 | 437 | dma_addr_t addr; |
1f81b6d2 | 438 | u64 hw_dequeue; |
365038d8 MN |
439 | bool cycle_found = false; |
440 | bool td_last_trb_found = false; | |
ae636747 | 441 | |
e9df17eb SS |
442 | ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id, |
443 | ep_index, stream_id); | |
444 | if (!ep_ring) { | |
445 | xhci_warn(xhci, "WARN can't find new dequeue state " | |
446 | "for invalid stream ID %u.\n", | |
447 | stream_id); | |
448 | return; | |
449 | } | |
68e41c5d | 450 | |
ae636747 | 451 | /* Dig out the cycle state saved by the xHC during the stop ep cmd */ |
aa50b290 XR |
452 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
453 | "Finding endpoint context"); | |
c4bedb77 HG |
454 | /* 4.6.9 the css flag is written to the stream context for streams */ |
455 | if (ep->ep_state & EP_HAS_STREAMS) { | |
456 | struct xhci_stream_ctx *ctx = | |
457 | &ep->stream_info->stream_ctx_array[stream_id]; | |
1f81b6d2 | 458 | hw_dequeue = le64_to_cpu(ctx->stream_ring); |
c4bedb77 HG |
459 | } else { |
460 | struct xhci_ep_ctx *ep_ctx | |
461 | = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index); | |
1f81b6d2 | 462 | hw_dequeue = le64_to_cpu(ep_ctx->deq); |
c4bedb77 | 463 | } |
ae636747 | 464 | |
365038d8 MN |
465 | new_seg = ep_ring->deq_seg; |
466 | new_deq = ep_ring->dequeue; | |
467 | state->new_cycle_state = hw_dequeue & 0x1; | |
468 | ||
1f81b6d2 | 469 | /* |
365038d8 MN |
470 | * We want to find the pointer, segment and cycle state of the new trb |
471 | * (the one after current TD's last_trb). We know the cycle state at | |
472 | * hw_dequeue, so walk the ring until both hw_dequeue and last_trb are | |
473 | * found. | |
1f81b6d2 | 474 | */ |
365038d8 MN |
475 | do { |
476 | if (!cycle_found && xhci_trb_virt_to_dma(new_seg, new_deq) | |
477 | == (dma_addr_t)(hw_dequeue & ~0xf)) { | |
478 | cycle_found = true; | |
479 | if (td_last_trb_found) | |
480 | break; | |
481 | } | |
482 | if (new_deq == cur_td->last_trb) | |
483 | td_last_trb_found = true; | |
1f81b6d2 | 484 | |
365038d8 MN |
485 | if (cycle_found && |
486 | TRB_TYPE_LINK_LE32(new_deq->generic.field[3]) && | |
487 | new_deq->generic.field[3] & cpu_to_le32(LINK_TOGGLE)) | |
488 | state->new_cycle_state ^= 0x1; | |
489 | ||
490 | next_trb(xhci, ep_ring, &new_seg, &new_deq); | |
491 | ||
492 | /* Search wrapped around, bail out */ | |
493 | if (new_deq == ep->ring->dequeue) { | |
494 | xhci_err(xhci, "Error: Failed finding new dequeue state\n"); | |
495 | state->new_deq_seg = NULL; | |
496 | state->new_deq_ptr = NULL; | |
497 | return; | |
498 | } | |
499 | ||
500 | } while (!cycle_found || !td_last_trb_found); | |
ae636747 | 501 | |
365038d8 MN |
502 | state->new_deq_seg = new_seg; |
503 | state->new_deq_ptr = new_deq; | |
ae636747 | 504 | |
1f81b6d2 | 505 | /* Don't update the ring cycle state for the producer (us). */ |
aa50b290 XR |
506 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
507 | "Cycle state = 0x%x", state->new_cycle_state); | |
01a1fdb9 | 508 | |
aa50b290 XR |
509 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
510 | "New dequeue segment = %p (virtual)", | |
c92bcfa7 SS |
511 | state->new_deq_seg); |
512 | addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr); | |
aa50b290 XR |
513 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
514 | "New dequeue pointer = 0x%llx (DMA)", | |
c92bcfa7 | 515 | (unsigned long long) addr); |
ae636747 SS |
516 | } |
517 | ||
522989a2 SS |
518 | /* flip_cycle means flip the cycle bit of all but the first and last TRB. |
519 | * (The last TRB actually points to the ring enqueue pointer, which is not part | |
520 | * of this TD.) This is used to remove partially enqueued isoc TDs from a ring. | |
521 | */ | |
23e3be11 | 522 | static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring, |
522989a2 | 523 | struct xhci_td *cur_td, bool flip_cycle) |
ae636747 SS |
524 | { |
525 | struct xhci_segment *cur_seg; | |
526 | union xhci_trb *cur_trb; | |
527 | ||
528 | for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb; | |
529 | true; | |
530 | next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) { | |
f5960b69 | 531 | if (TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) { |
ae636747 SS |
532 | /* Unchain any chained Link TRBs, but |
533 | * leave the pointers intact. | |
534 | */ | |
28ccd296 | 535 | cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN); |
522989a2 SS |
536 | /* Flip the cycle bit (link TRBs can't be the first |
537 | * or last TRB). | |
538 | */ | |
539 | if (flip_cycle) | |
540 | cur_trb->generic.field[3] ^= | |
541 | cpu_to_le32(TRB_CYCLE); | |
aa50b290 XR |
542 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
543 | "Cancel (unchain) link TRB"); | |
544 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, | |
545 | "Address = %p (0x%llx dma); " | |
546 | "in seg %p (0x%llx dma)", | |
700e2052 | 547 | cur_trb, |
23e3be11 | 548 | (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb), |
700e2052 GKH |
549 | cur_seg, |
550 | (unsigned long long)cur_seg->dma); | |
ae636747 SS |
551 | } else { |
552 | cur_trb->generic.field[0] = 0; | |
553 | cur_trb->generic.field[1] = 0; | |
554 | cur_trb->generic.field[2] = 0; | |
555 | /* Preserve only the cycle bit of this TRB */ | |
28ccd296 | 556 | cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE); |
522989a2 SS |
557 | /* Flip the cycle bit except on the first or last TRB */ |
558 | if (flip_cycle && cur_trb != cur_td->first_trb && | |
559 | cur_trb != cur_td->last_trb) | |
560 | cur_trb->generic.field[3] ^= | |
561 | cpu_to_le32(TRB_CYCLE); | |
28ccd296 ME |
562 | cur_trb->generic.field[3] |= cpu_to_le32( |
563 | TRB_TYPE(TRB_TR_NOOP)); | |
aa50b290 XR |
564 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
565 | "TRB to noop at offset 0x%llx", | |
79688acf SS |
566 | (unsigned long long) |
567 | xhci_trb_virt_to_dma(cur_seg, cur_trb)); | |
ae636747 SS |
568 | } |
569 | if (cur_trb == cur_td->last_trb) | |
570 | break; | |
571 | } | |
572 | } | |
573 | ||
575688e1 | 574 | static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci, |
6f5165cf SS |
575 | struct xhci_virt_ep *ep) |
576 | { | |
577 | ep->ep_state &= ~EP_HALT_PENDING; | |
578 | /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the | |
579 | * timer is running on another CPU, we don't decrement stop_cmds_pending | |
580 | * (since we didn't successfully stop the watchdog timer). | |
581 | */ | |
582 | if (del_timer(&ep->stop_cmd_timer)) | |
583 | ep->stop_cmds_pending--; | |
584 | } | |
585 | ||
586 | /* Must be called with xhci->lock held in interrupt context */ | |
587 | static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci, | |
07a37e9e | 588 | struct xhci_td *cur_td, int status) |
6f5165cf | 589 | { |
214f76f7 | 590 | struct usb_hcd *hcd; |
8e51adcc AX |
591 | struct urb *urb; |
592 | struct urb_priv *urb_priv; | |
6f5165cf | 593 | |
8e51adcc AX |
594 | urb = cur_td->urb; |
595 | urb_priv = urb->hcpriv; | |
596 | urb_priv->td_cnt++; | |
214f76f7 | 597 | hcd = bus_to_hcd(urb->dev->bus); |
6f5165cf | 598 | |
8e51adcc AX |
599 | /* Only giveback urb when this is the last td in urb */ |
600 | if (urb_priv->td_cnt == urb_priv->length) { | |
c41136b0 AX |
601 | if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { |
602 | xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--; | |
603 | if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) { | |
604 | if (xhci->quirks & XHCI_AMD_PLL_FIX) | |
605 | usb_amd_quirk_pll_enable(); | |
606 | } | |
607 | } | |
8e51adcc | 608 | usb_hcd_unlink_urb_from_ep(hcd, urb); |
8e51adcc AX |
609 | |
610 | spin_unlock(&xhci->lock); | |
611 | usb_hcd_giveback_urb(hcd, urb, status); | |
4daf9df5 | 612 | xhci_urb_free_priv(urb_priv); |
8e51adcc | 613 | spin_lock(&xhci->lock); |
8e51adcc | 614 | } |
6f5165cf SS |
615 | } |
616 | ||
ae636747 SS |
617 | /* |
618 | * When we get a command completion for a Stop Endpoint Command, we need to | |
619 | * unlink any cancelled TDs from the ring. There are two ways to do that: | |
620 | * | |
621 | * 1. If the HW was in the middle of processing the TD that needs to be | |
622 | * cancelled, then we must move the ring's dequeue pointer past the last TRB | |
623 | * in the TD with a Set Dequeue Pointer Command. | |
624 | * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain | |
625 | * bit cleared) so that the HW will skip over them. | |
626 | */ | |
b8200c94 | 627 | static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id, |
be88fe4f | 628 | union xhci_trb *trb, struct xhci_event_cmd *event) |
ae636747 | 629 | { |
ae636747 SS |
630 | unsigned int ep_index; |
631 | struct xhci_ring *ep_ring; | |
63a0d9ab | 632 | struct xhci_virt_ep *ep; |
ae636747 | 633 | struct list_head *entry; |
326b4810 | 634 | struct xhci_td *cur_td = NULL; |
ae636747 SS |
635 | struct xhci_td *last_unlinked_td; |
636 | ||
c92bcfa7 | 637 | struct xhci_dequeue_state deq_state; |
ae636747 | 638 | |
bc752bde | 639 | if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) { |
9ea1833e | 640 | if (!xhci->devs[slot_id]) |
be88fe4f AX |
641 | xhci_warn(xhci, "Stop endpoint command " |
642 | "completion for disabled slot %u\n", | |
643 | slot_id); | |
644 | return; | |
645 | } | |
646 | ||
ae636747 | 647 | memset(&deq_state, 0, sizeof(deq_state)); |
28ccd296 | 648 | ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); |
63a0d9ab | 649 | ep = &xhci->devs[slot_id]->eps[ep_index]; |
ae636747 | 650 | |
678539cf | 651 | if (list_empty(&ep->cancelled_td_list)) { |
6f5165cf | 652 | xhci_stop_watchdog_timer_in_irq(xhci, ep); |
0714a57c | 653 | ep->stopped_td = NULL; |
e9df17eb | 654 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); |
ae636747 | 655 | return; |
678539cf | 656 | } |
ae636747 SS |
657 | |
658 | /* Fix up the ep ring first, so HW stops executing cancelled TDs. | |
659 | * We have the xHCI lock, so nothing can modify this list until we drop | |
660 | * it. We're also in the event handler, so we can't get re-interrupted | |
661 | * if another Stop Endpoint command completes | |
662 | */ | |
63a0d9ab | 663 | list_for_each(entry, &ep->cancelled_td_list) { |
ae636747 | 664 | cur_td = list_entry(entry, struct xhci_td, cancelled_td_list); |
aa50b290 XR |
665 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
666 | "Removing canceled TD starting at 0x%llx (dma).", | |
79688acf SS |
667 | (unsigned long long)xhci_trb_virt_to_dma( |
668 | cur_td->start_seg, cur_td->first_trb)); | |
e9df17eb SS |
669 | ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb); |
670 | if (!ep_ring) { | |
671 | /* This shouldn't happen unless a driver is mucking | |
672 | * with the stream ID after submission. This will | |
673 | * leave the TD on the hardware ring, and the hardware | |
674 | * will try to execute it, and may access a buffer | |
675 | * that has already been freed. In the best case, the | |
676 | * hardware will execute it, and the event handler will | |
677 | * ignore the completion event for that TD, since it was | |
678 | * removed from the td_list for that endpoint. In | |
679 | * short, don't muck with the stream ID after | |
680 | * submission. | |
681 | */ | |
682 | xhci_warn(xhci, "WARN Cancelled URB %p " | |
683 | "has invalid stream ID %u.\n", | |
684 | cur_td->urb, | |
685 | cur_td->urb->stream_id); | |
686 | goto remove_finished_td; | |
687 | } | |
ae636747 SS |
688 | /* |
689 | * If we stopped on the TD we need to cancel, then we have to | |
690 | * move the xHC endpoint ring dequeue pointer past this TD. | |
691 | */ | |
63a0d9ab | 692 | if (cur_td == ep->stopped_td) |
e9df17eb SS |
693 | xhci_find_new_dequeue_state(xhci, slot_id, ep_index, |
694 | cur_td->urb->stream_id, | |
695 | cur_td, &deq_state); | |
ae636747 | 696 | else |
522989a2 | 697 | td_to_noop(xhci, ep_ring, cur_td, false); |
e9df17eb | 698 | remove_finished_td: |
ae636747 SS |
699 | /* |
700 | * The event handler won't see a completion for this TD anymore, | |
701 | * so remove it from the endpoint ring's TD list. Keep it in | |
702 | * the cancelled TD list for URB completion later. | |
703 | */ | |
585df1d9 | 704 | list_del_init(&cur_td->td_list); |
ae636747 SS |
705 | } |
706 | last_unlinked_td = cur_td; | |
6f5165cf | 707 | xhci_stop_watchdog_timer_in_irq(xhci, ep); |
ae636747 SS |
708 | |
709 | /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */ | |
710 | if (deq_state.new_deq_ptr && deq_state.new_deq_seg) { | |
1e3452e3 HG |
711 | xhci_queue_new_dequeue_state(xhci, slot_id, ep_index, |
712 | ep->stopped_td->urb->stream_id, &deq_state); | |
ac9d8fe7 | 713 | xhci_ring_cmd_db(xhci); |
ae636747 | 714 | } else { |
e9df17eb SS |
715 | /* Otherwise ring the doorbell(s) to restart queued transfers */ |
716 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); | |
ae636747 | 717 | } |
526867c3 | 718 | |
d97b4f8d | 719 | ep->stopped_td = NULL; |
ae636747 SS |
720 | |
721 | /* | |
722 | * Drop the lock and complete the URBs in the cancelled TD list. | |
723 | * New TDs to be cancelled might be added to the end of the list before | |
724 | * we can complete all the URBs for the TDs we already unlinked. | |
725 | * So stop when we've completed the URB for the last TD we unlinked. | |
726 | */ | |
727 | do { | |
63a0d9ab | 728 | cur_td = list_entry(ep->cancelled_td_list.next, |
ae636747 | 729 | struct xhci_td, cancelled_td_list); |
585df1d9 | 730 | list_del_init(&cur_td->cancelled_td_list); |
ae636747 SS |
731 | |
732 | /* Clean up the cancelled URB */ | |
ae636747 SS |
733 | /* Doesn't matter what we pass for status, since the core will |
734 | * just overwrite it (because the URB has been unlinked). | |
735 | */ | |
07a37e9e | 736 | xhci_giveback_urb_in_irq(xhci, cur_td, 0); |
ae636747 | 737 | |
6f5165cf SS |
738 | /* Stop processing the cancelled list if the watchdog timer is |
739 | * running. | |
740 | */ | |
741 | if (xhci->xhc_state & XHCI_STATE_DYING) | |
742 | return; | |
ae636747 SS |
743 | } while (cur_td != last_unlinked_td); |
744 | ||
745 | /* Return to the event handler with xhci->lock re-acquired */ | |
746 | } | |
747 | ||
50e8725e SS |
748 | static void xhci_kill_ring_urbs(struct xhci_hcd *xhci, struct xhci_ring *ring) |
749 | { | |
750 | struct xhci_td *cur_td; | |
751 | ||
752 | while (!list_empty(&ring->td_list)) { | |
753 | cur_td = list_first_entry(&ring->td_list, | |
754 | struct xhci_td, td_list); | |
755 | list_del_init(&cur_td->td_list); | |
756 | if (!list_empty(&cur_td->cancelled_td_list)) | |
757 | list_del_init(&cur_td->cancelled_td_list); | |
758 | xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN); | |
759 | } | |
760 | } | |
761 | ||
762 | static void xhci_kill_endpoint_urbs(struct xhci_hcd *xhci, | |
763 | int slot_id, int ep_index) | |
764 | { | |
765 | struct xhci_td *cur_td; | |
766 | struct xhci_virt_ep *ep; | |
767 | struct xhci_ring *ring; | |
768 | ||
769 | ep = &xhci->devs[slot_id]->eps[ep_index]; | |
21d0e51b SS |
770 | if ((ep->ep_state & EP_HAS_STREAMS) || |
771 | (ep->ep_state & EP_GETTING_NO_STREAMS)) { | |
772 | int stream_id; | |
773 | ||
774 | for (stream_id = 0; stream_id < ep->stream_info->num_streams; | |
775 | stream_id++) { | |
776 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, | |
777 | "Killing URBs for slot ID %u, ep index %u, stream %u", | |
778 | slot_id, ep_index, stream_id + 1); | |
779 | xhci_kill_ring_urbs(xhci, | |
780 | ep->stream_info->stream_rings[stream_id]); | |
781 | } | |
782 | } else { | |
783 | ring = ep->ring; | |
784 | if (!ring) | |
785 | return; | |
786 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, | |
787 | "Killing URBs for slot ID %u, ep index %u", | |
788 | slot_id, ep_index); | |
789 | xhci_kill_ring_urbs(xhci, ring); | |
790 | } | |
50e8725e SS |
791 | while (!list_empty(&ep->cancelled_td_list)) { |
792 | cur_td = list_first_entry(&ep->cancelled_td_list, | |
793 | struct xhci_td, cancelled_td_list); | |
794 | list_del_init(&cur_td->cancelled_td_list); | |
795 | xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN); | |
796 | } | |
797 | } | |
798 | ||
6f5165cf SS |
799 | /* Watchdog timer function for when a stop endpoint command fails to complete. |
800 | * In this case, we assume the host controller is broken or dying or dead. The | |
801 | * host may still be completing some other events, so we have to be careful to | |
802 | * let the event ring handler and the URB dequeueing/enqueueing functions know | |
803 | * through xhci->state. | |
804 | * | |
805 | * The timer may also fire if the host takes a very long time to respond to the | |
806 | * command, and the stop endpoint command completion handler cannot delete the | |
807 | * timer before the timer function is called. Another endpoint cancellation may | |
808 | * sneak in before the timer function can grab the lock, and that may queue | |
809 | * another stop endpoint command and add the timer back. So we cannot use a | |
810 | * simple flag to say whether there is a pending stop endpoint command for a | |
811 | * particular endpoint. | |
812 | * | |
813 | * Instead we use a combination of that flag and a counter for the number of | |
814 | * pending stop endpoint commands. If the timer is the tail end of the last | |
815 | * stop endpoint command, and the endpoint's command is still pending, we assume | |
816 | * the host is dying. | |
817 | */ | |
818 | void xhci_stop_endpoint_command_watchdog(unsigned long arg) | |
819 | { | |
820 | struct xhci_hcd *xhci; | |
821 | struct xhci_virt_ep *ep; | |
6f5165cf | 822 | int ret, i, j; |
f43d6231 | 823 | unsigned long flags; |
6f5165cf SS |
824 | |
825 | ep = (struct xhci_virt_ep *) arg; | |
826 | xhci = ep->xhci; | |
827 | ||
f43d6231 | 828 | spin_lock_irqsave(&xhci->lock, flags); |
6f5165cf SS |
829 | |
830 | ep->stop_cmds_pending--; | |
831 | if (xhci->xhc_state & XHCI_STATE_DYING) { | |
aa50b290 XR |
832 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
833 | "Stop EP timer ran, but another timer marked " | |
834 | "xHCI as DYING, exiting."); | |
f43d6231 | 835 | spin_unlock_irqrestore(&xhci->lock, flags); |
6f5165cf SS |
836 | return; |
837 | } | |
838 | if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) { | |
aa50b290 XR |
839 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
840 | "Stop EP timer ran, but no command pending, " | |
841 | "exiting."); | |
f43d6231 | 842 | spin_unlock_irqrestore(&xhci->lock, flags); |
6f5165cf SS |
843 | return; |
844 | } | |
845 | ||
846 | xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n"); | |
847 | xhci_warn(xhci, "Assuming host is dying, halting host.\n"); | |
848 | /* Oops, HC is dead or dying or at least not responding to the stop | |
849 | * endpoint command. | |
850 | */ | |
851 | xhci->xhc_state |= XHCI_STATE_DYING; | |
852 | /* Disable interrupts from the host controller and start halting it */ | |
853 | xhci_quiesce(xhci); | |
f43d6231 | 854 | spin_unlock_irqrestore(&xhci->lock, flags); |
6f5165cf SS |
855 | |
856 | ret = xhci_halt(xhci); | |
857 | ||
f43d6231 | 858 | spin_lock_irqsave(&xhci->lock, flags); |
6f5165cf SS |
859 | if (ret < 0) { |
860 | /* This is bad; the host is not responding to commands and it's | |
861 | * not allowing itself to be halted. At least interrupts are | |
ac04e6ff | 862 | * disabled. If we call usb_hc_died(), it will attempt to |
6f5165cf SS |
863 | * disconnect all device drivers under this host. Those |
864 | * disconnect() methods will wait for all URBs to be unlinked, | |
865 | * so we must complete them. | |
866 | */ | |
867 | xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n"); | |
868 | xhci_warn(xhci, "Completing active URBs anyway.\n"); | |
869 | /* We could turn all TDs on the rings to no-ops. This won't | |
870 | * help if the host has cached part of the ring, and is slow if | |
871 | * we want to preserve the cycle bit. Skip it and hope the host | |
872 | * doesn't touch the memory. | |
873 | */ | |
874 | } | |
875 | for (i = 0; i < MAX_HC_SLOTS; i++) { | |
876 | if (!xhci->devs[i]) | |
877 | continue; | |
50e8725e SS |
878 | for (j = 0; j < 31; j++) |
879 | xhci_kill_endpoint_urbs(xhci, i, j); | |
6f5165cf | 880 | } |
f43d6231 | 881 | spin_unlock_irqrestore(&xhci->lock, flags); |
aa50b290 XR |
882 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
883 | "Calling usb_hc_died()"); | |
f6ff0ac8 | 884 | usb_hc_died(xhci_to_hcd(xhci)->primary_hcd); |
aa50b290 XR |
885 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
886 | "xHCI host controller is dead."); | |
6f5165cf SS |
887 | } |
888 | ||
b008df60 AX |
889 | |
890 | static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci, | |
891 | struct xhci_virt_device *dev, | |
892 | struct xhci_ring *ep_ring, | |
893 | unsigned int ep_index) | |
894 | { | |
895 | union xhci_trb *dequeue_temp; | |
896 | int num_trbs_free_temp; | |
897 | bool revert = false; | |
898 | ||
899 | num_trbs_free_temp = ep_ring->num_trbs_free; | |
900 | dequeue_temp = ep_ring->dequeue; | |
901 | ||
0d9f78a9 SS |
902 | /* If we get two back-to-back stalls, and the first stalled transfer |
903 | * ends just before a link TRB, the dequeue pointer will be left on | |
904 | * the link TRB by the code in the while loop. So we have to update | |
905 | * the dequeue pointer one segment further, or we'll jump off | |
906 | * the segment into la-la-land. | |
907 | */ | |
908 | if (last_trb(xhci, ep_ring, ep_ring->deq_seg, ep_ring->dequeue)) { | |
909 | ep_ring->deq_seg = ep_ring->deq_seg->next; | |
910 | ep_ring->dequeue = ep_ring->deq_seg->trbs; | |
911 | } | |
912 | ||
b008df60 AX |
913 | while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) { |
914 | /* We have more usable TRBs */ | |
915 | ep_ring->num_trbs_free++; | |
916 | ep_ring->dequeue++; | |
917 | if (last_trb(xhci, ep_ring, ep_ring->deq_seg, | |
918 | ep_ring->dequeue)) { | |
919 | if (ep_ring->dequeue == | |
920 | dev->eps[ep_index].queued_deq_ptr) | |
921 | break; | |
922 | ep_ring->deq_seg = ep_ring->deq_seg->next; | |
923 | ep_ring->dequeue = ep_ring->deq_seg->trbs; | |
924 | } | |
925 | if (ep_ring->dequeue == dequeue_temp) { | |
926 | revert = true; | |
927 | break; | |
928 | } | |
929 | } | |
930 | ||
931 | if (revert) { | |
932 | xhci_dbg(xhci, "Unable to find new dequeue pointer\n"); | |
933 | ep_ring->num_trbs_free = num_trbs_free_temp; | |
934 | } | |
935 | } | |
936 | ||
ae636747 SS |
937 | /* |
938 | * When we get a completion for a Set Transfer Ring Dequeue Pointer command, | |
939 | * we need to clear the set deq pending flag in the endpoint ring state, so that | |
940 | * the TD queueing code can ring the doorbell again. We also need to ring the | |
941 | * endpoint doorbell to restart the ring, but only if there aren't more | |
942 | * cancellations pending. | |
943 | */ | |
b8200c94 | 944 | static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id, |
c69a0597 | 945 | union xhci_trb *trb, u32 cmd_comp_code) |
ae636747 | 946 | { |
ae636747 | 947 | unsigned int ep_index; |
e9df17eb | 948 | unsigned int stream_id; |
ae636747 SS |
949 | struct xhci_ring *ep_ring; |
950 | struct xhci_virt_device *dev; | |
9aad95e2 | 951 | struct xhci_virt_ep *ep; |
d115b048 JY |
952 | struct xhci_ep_ctx *ep_ctx; |
953 | struct xhci_slot_ctx *slot_ctx; | |
ae636747 | 954 | |
28ccd296 ME |
955 | ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); |
956 | stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2])); | |
ae636747 | 957 | dev = xhci->devs[slot_id]; |
9aad95e2 | 958 | ep = &dev->eps[ep_index]; |
e9df17eb SS |
959 | |
960 | ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id); | |
961 | if (!ep_ring) { | |
e587b8b2 | 962 | xhci_warn(xhci, "WARN Set TR deq ptr command for freed stream ID %u\n", |
e9df17eb SS |
963 | stream_id); |
964 | /* XXX: Harmless??? */ | |
0d4976ec | 965 | goto cleanup; |
e9df17eb SS |
966 | } |
967 | ||
d115b048 JY |
968 | ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index); |
969 | slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx); | |
ae636747 | 970 | |
c69a0597 | 971 | if (cmd_comp_code != COMP_SUCCESS) { |
ae636747 SS |
972 | unsigned int ep_state; |
973 | unsigned int slot_state; | |
974 | ||
c69a0597 | 975 | switch (cmd_comp_code) { |
ae636747 | 976 | case COMP_TRB_ERR: |
e587b8b2 | 977 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n"); |
ae636747 SS |
978 | break; |
979 | case COMP_CTX_STATE: | |
e587b8b2 | 980 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n"); |
28ccd296 | 981 | ep_state = le32_to_cpu(ep_ctx->ep_info); |
ae636747 | 982 | ep_state &= EP_STATE_MASK; |
28ccd296 | 983 | slot_state = le32_to_cpu(slot_ctx->dev_state); |
ae636747 | 984 | slot_state = GET_SLOT_STATE(slot_state); |
aa50b290 XR |
985 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
986 | "Slot state = %u, EP state = %u", | |
ae636747 SS |
987 | slot_state, ep_state); |
988 | break; | |
989 | case COMP_EBADSLT: | |
e587b8b2 ON |
990 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n", |
991 | slot_id); | |
ae636747 SS |
992 | break; |
993 | default: | |
e587b8b2 ON |
994 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n", |
995 | cmd_comp_code); | |
ae636747 SS |
996 | break; |
997 | } | |
998 | /* OK what do we do now? The endpoint state is hosed, and we | |
999 | * should never get to this point if the synchronization between | |
1000 | * queueing, and endpoint state are correct. This might happen | |
1001 | * if the device gets disconnected after we've finished | |
1002 | * cancelling URBs, which might not be an error... | |
1003 | */ | |
1004 | } else { | |
9aad95e2 HG |
1005 | u64 deq; |
1006 | /* 4.6.10 deq ptr is written to the stream ctx for streams */ | |
1007 | if (ep->ep_state & EP_HAS_STREAMS) { | |
1008 | struct xhci_stream_ctx *ctx = | |
1009 | &ep->stream_info->stream_ctx_array[stream_id]; | |
1010 | deq = le64_to_cpu(ctx->stream_ring) & SCTX_DEQ_MASK; | |
1011 | } else { | |
1012 | deq = le64_to_cpu(ep_ctx->deq) & ~EP_CTX_CYCLE_MASK; | |
1013 | } | |
aa50b290 | 1014 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
9aad95e2 HG |
1015 | "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq); |
1016 | if (xhci_trb_virt_to_dma(ep->queued_deq_seg, | |
1017 | ep->queued_deq_ptr) == deq) { | |
bf161e85 SS |
1018 | /* Update the ring's dequeue segment and dequeue pointer |
1019 | * to reflect the new position. | |
1020 | */ | |
b008df60 AX |
1021 | update_ring_for_set_deq_completion(xhci, dev, |
1022 | ep_ring, ep_index); | |
bf161e85 | 1023 | } else { |
e587b8b2 | 1024 | xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n"); |
bf161e85 | 1025 | xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n", |
9aad95e2 | 1026 | ep->queued_deq_seg, ep->queued_deq_ptr); |
bf161e85 | 1027 | } |
ae636747 SS |
1028 | } |
1029 | ||
0d4976ec | 1030 | cleanup: |
63a0d9ab | 1031 | dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING; |
bf161e85 SS |
1032 | dev->eps[ep_index].queued_deq_seg = NULL; |
1033 | dev->eps[ep_index].queued_deq_ptr = NULL; | |
e9df17eb SS |
1034 | /* Restart any rings with pending URBs */ |
1035 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); | |
ae636747 SS |
1036 | } |
1037 | ||
b8200c94 | 1038 | static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id, |
c69a0597 | 1039 | union xhci_trb *trb, u32 cmd_comp_code) |
a1587d97 | 1040 | { |
a1587d97 SS |
1041 | unsigned int ep_index; |
1042 | ||
28ccd296 | 1043 | ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); |
a1587d97 SS |
1044 | /* This command will only fail if the endpoint wasn't halted, |
1045 | * but we don't care. | |
1046 | */ | |
a0254324 | 1047 | xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep, |
c69a0597 | 1048 | "Ignoring reset ep completion code of %u", cmd_comp_code); |
a1587d97 | 1049 | |
ac9d8fe7 SS |
1050 | /* HW with the reset endpoint quirk needs to have a configure endpoint |
1051 | * command complete before the endpoint can be used. Queue that here | |
1052 | * because the HW can't handle two commands being queued in a row. | |
1053 | */ | |
1054 | if (xhci->quirks & XHCI_RESET_EP_QUIRK) { | |
ddba5cd0 MN |
1055 | struct xhci_command *command; |
1056 | command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC); | |
a0ee619f HG |
1057 | if (!command) { |
1058 | xhci_warn(xhci, "WARN Cannot submit cfg ep: ENOMEM\n"); | |
1059 | return; | |
1060 | } | |
4bdfe4c3 XR |
1061 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
1062 | "Queueing configure endpoint command"); | |
ddba5cd0 | 1063 | xhci_queue_configure_endpoint(xhci, command, |
913a8a34 SS |
1064 | xhci->devs[slot_id]->in_ctx->dma, slot_id, |
1065 | false); | |
ac9d8fe7 SS |
1066 | xhci_ring_cmd_db(xhci); |
1067 | } else { | |
c3492dbf | 1068 | /* Clear our internal halted state */ |
63a0d9ab | 1069 | xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED; |
ac9d8fe7 | 1070 | } |
a1587d97 | 1071 | } |
ae636747 | 1072 | |
b244b431 XR |
1073 | static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id, |
1074 | u32 cmd_comp_code) | |
1075 | { | |
1076 | if (cmd_comp_code == COMP_SUCCESS) | |
1077 | xhci->slot_id = slot_id; | |
1078 | else | |
1079 | xhci->slot_id = 0; | |
b244b431 XR |
1080 | } |
1081 | ||
6c02dd14 XR |
1082 | static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id) |
1083 | { | |
1084 | struct xhci_virt_device *virt_dev; | |
1085 | ||
1086 | virt_dev = xhci->devs[slot_id]; | |
1087 | if (!virt_dev) | |
1088 | return; | |
1089 | if (xhci->quirks & XHCI_EP_LIMIT_QUIRK) | |
1090 | /* Delete default control endpoint resources */ | |
1091 | xhci_free_device_endpoint_resources(xhci, virt_dev, true); | |
1092 | xhci_free_virt_device(xhci, slot_id); | |
1093 | } | |
1094 | ||
6ed46d33 XR |
1095 | static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id, |
1096 | struct xhci_event_cmd *event, u32 cmd_comp_code) | |
1097 | { | |
1098 | struct xhci_virt_device *virt_dev; | |
1099 | struct xhci_input_control_ctx *ctrl_ctx; | |
1100 | unsigned int ep_index; | |
1101 | unsigned int ep_state; | |
1102 | u32 add_flags, drop_flags; | |
1103 | ||
6ed46d33 XR |
1104 | /* |
1105 | * Configure endpoint commands can come from the USB core | |
1106 | * configuration or alt setting changes, or because the HW | |
1107 | * needed an extra configure endpoint command after a reset | |
1108 | * endpoint command or streams were being configured. | |
1109 | * If the command was for a halted endpoint, the xHCI driver | |
1110 | * is not waiting on the configure endpoint command. | |
1111 | */ | |
9ea1833e | 1112 | virt_dev = xhci->devs[slot_id]; |
4daf9df5 | 1113 | ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx); |
6ed46d33 XR |
1114 | if (!ctrl_ctx) { |
1115 | xhci_warn(xhci, "Could not get input context, bad type.\n"); | |
1116 | return; | |
1117 | } | |
1118 | ||
1119 | add_flags = le32_to_cpu(ctrl_ctx->add_flags); | |
1120 | drop_flags = le32_to_cpu(ctrl_ctx->drop_flags); | |
1121 | /* Input ctx add_flags are the endpoint index plus one */ | |
1122 | ep_index = xhci_last_valid_endpoint(add_flags) - 1; | |
1123 | ||
1124 | /* A usb_set_interface() call directly after clearing a halted | |
1125 | * condition may race on this quirky hardware. Not worth | |
1126 | * worrying about, since this is prototype hardware. Not sure | |
1127 | * if this will work for streams, but streams support was | |
1128 | * untested on this prototype. | |
1129 | */ | |
1130 | if (xhci->quirks & XHCI_RESET_EP_QUIRK && | |
1131 | ep_index != (unsigned int) -1 && | |
1132 | add_flags - SLOT_FLAG == drop_flags) { | |
1133 | ep_state = virt_dev->eps[ep_index].ep_state; | |
1134 | if (!(ep_state & EP_HALTED)) | |
ddba5cd0 | 1135 | return; |
6ed46d33 XR |
1136 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
1137 | "Completed config ep cmd - " | |
1138 | "last ep index = %d, state = %d", | |
1139 | ep_index, ep_state); | |
1140 | /* Clear internal halted state and restart ring(s) */ | |
1141 | virt_dev->eps[ep_index].ep_state &= ~EP_HALTED; | |
1142 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); | |
1143 | return; | |
1144 | } | |
6ed46d33 XR |
1145 | return; |
1146 | } | |
1147 | ||
f681321b XR |
1148 | static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id, |
1149 | struct xhci_event_cmd *event) | |
1150 | { | |
f681321b | 1151 | xhci_dbg(xhci, "Completed reset device command.\n"); |
9ea1833e | 1152 | if (!xhci->devs[slot_id]) |
f681321b XR |
1153 | xhci_warn(xhci, "Reset device command completion " |
1154 | "for disabled slot %u\n", slot_id); | |
1155 | } | |
1156 | ||
2c070821 XR |
1157 | static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci, |
1158 | struct xhci_event_cmd *event) | |
1159 | { | |
1160 | if (!(xhci->quirks & XHCI_NEC_HOST)) { | |
1161 | xhci->error_bitmask |= 1 << 6; | |
1162 | return; | |
1163 | } | |
1164 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, | |
1165 | "NEC firmware version %2x.%02x", | |
1166 | NEC_FW_MAJOR(le32_to_cpu(event->status)), | |
1167 | NEC_FW_MINOR(le32_to_cpu(event->status))); | |
1168 | } | |
1169 | ||
9ea1833e | 1170 | static void xhci_complete_del_and_free_cmd(struct xhci_command *cmd, u32 status) |
c9aa1a2d MN |
1171 | { |
1172 | list_del(&cmd->cmd_list); | |
9ea1833e MN |
1173 | |
1174 | if (cmd->completion) { | |
1175 | cmd->status = status; | |
1176 | complete(cmd->completion); | |
1177 | } else { | |
c9aa1a2d | 1178 | kfree(cmd); |
9ea1833e | 1179 | } |
c9aa1a2d MN |
1180 | } |
1181 | ||
1182 | void xhci_cleanup_command_queue(struct xhci_hcd *xhci) | |
1183 | { | |
1184 | struct xhci_command *cur_cmd, *tmp_cmd; | |
1185 | list_for_each_entry_safe(cur_cmd, tmp_cmd, &xhci->cmd_list, cmd_list) | |
9ea1833e | 1186 | xhci_complete_del_and_free_cmd(cur_cmd, COMP_CMD_ABORT); |
c9aa1a2d MN |
1187 | } |
1188 | ||
c311e391 MN |
1189 | /* |
1190 | * Turn all commands on command ring with status set to "aborted" to no-op trbs. | |
1191 | * If there are other commands waiting then restart the ring and kick the timer. | |
1192 | * This must be called with command ring stopped and xhci->lock held. | |
1193 | */ | |
1194 | static void xhci_handle_stopped_cmd_ring(struct xhci_hcd *xhci, | |
1195 | struct xhci_command *cur_cmd) | |
1196 | { | |
1197 | struct xhci_command *i_cmd, *tmp_cmd; | |
1198 | u32 cycle_state; | |
1199 | ||
1200 | /* Turn all aborted commands in list to no-ops, then restart */ | |
1201 | list_for_each_entry_safe(i_cmd, tmp_cmd, &xhci->cmd_list, | |
1202 | cmd_list) { | |
1203 | ||
1204 | if (i_cmd->status != COMP_CMD_ABORT) | |
1205 | continue; | |
1206 | ||
1207 | i_cmd->status = COMP_CMD_STOP; | |
1208 | ||
1209 | xhci_dbg(xhci, "Turn aborted command %p to no-op\n", | |
1210 | i_cmd->command_trb); | |
1211 | /* get cycle state from the original cmd trb */ | |
1212 | cycle_state = le32_to_cpu( | |
1213 | i_cmd->command_trb->generic.field[3]) & TRB_CYCLE; | |
1214 | /* modify the command trb to no-op command */ | |
1215 | i_cmd->command_trb->generic.field[0] = 0; | |
1216 | i_cmd->command_trb->generic.field[1] = 0; | |
1217 | i_cmd->command_trb->generic.field[2] = 0; | |
1218 | i_cmd->command_trb->generic.field[3] = cpu_to_le32( | |
1219 | TRB_TYPE(TRB_CMD_NOOP) | cycle_state); | |
1220 | ||
1221 | /* | |
1222 | * caller waiting for completion is called when command | |
1223 | * completion event is received for these no-op commands | |
1224 | */ | |
1225 | } | |
1226 | ||
1227 | xhci->cmd_ring_state = CMD_RING_STATE_RUNNING; | |
1228 | ||
1229 | /* ring command ring doorbell to restart the command ring */ | |
1230 | if ((xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue) && | |
1231 | !(xhci->xhc_state & XHCI_STATE_DYING)) { | |
1232 | xhci->current_cmd = cur_cmd; | |
1233 | mod_timer(&xhci->cmd_timer, jiffies + XHCI_CMD_DEFAULT_TIMEOUT); | |
1234 | xhci_ring_cmd_db(xhci); | |
1235 | } | |
1236 | return; | |
1237 | } | |
1238 | ||
1239 | ||
1240 | void xhci_handle_command_timeout(unsigned long data) | |
1241 | { | |
1242 | struct xhci_hcd *xhci; | |
1243 | int ret; | |
1244 | unsigned long flags; | |
1245 | u64 hw_ring_state; | |
1246 | struct xhci_command *cur_cmd = NULL; | |
1247 | xhci = (struct xhci_hcd *) data; | |
1248 | ||
1249 | /* mark this command to be cancelled */ | |
1250 | spin_lock_irqsave(&xhci->lock, flags); | |
1251 | if (xhci->current_cmd) { | |
1252 | cur_cmd = xhci->current_cmd; | |
1253 | cur_cmd->status = COMP_CMD_ABORT; | |
1254 | } | |
1255 | ||
1256 | ||
1257 | /* Make sure command ring is running before aborting it */ | |
1258 | hw_ring_state = xhci_read_64(xhci, &xhci->op_regs->cmd_ring); | |
1259 | if ((xhci->cmd_ring_state & CMD_RING_STATE_RUNNING) && | |
1260 | (hw_ring_state & CMD_RING_RUNNING)) { | |
1261 | ||
1262 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1263 | xhci_dbg(xhci, "Command timeout\n"); | |
1264 | ret = xhci_abort_cmd_ring(xhci); | |
1265 | if (unlikely(ret == -ESHUTDOWN)) { | |
1266 | xhci_err(xhci, "Abort command ring failed\n"); | |
1267 | xhci_cleanup_command_queue(xhci); | |
1268 | usb_hc_died(xhci_to_hcd(xhci)->primary_hcd); | |
1269 | xhci_dbg(xhci, "xHCI host controller is dead.\n"); | |
1270 | } | |
1271 | return; | |
1272 | } | |
1273 | /* command timeout on stopped ring, ring can't be aborted */ | |
1274 | xhci_dbg(xhci, "Command timeout on stopped ring\n"); | |
1275 | xhci_handle_stopped_cmd_ring(xhci, xhci->current_cmd); | |
1276 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1277 | return; | |
1278 | } | |
1279 | ||
7f84eef0 SS |
1280 | static void handle_cmd_completion(struct xhci_hcd *xhci, |
1281 | struct xhci_event_cmd *event) | |
1282 | { | |
28ccd296 | 1283 | int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
7f84eef0 SS |
1284 | u64 cmd_dma; |
1285 | dma_addr_t cmd_dequeue_dma; | |
e7a79a1d | 1286 | u32 cmd_comp_code; |
9124b121 | 1287 | union xhci_trb *cmd_trb; |
c9aa1a2d | 1288 | struct xhci_command *cmd; |
b54fc46d | 1289 | u32 cmd_type; |
7f84eef0 | 1290 | |
28ccd296 | 1291 | cmd_dma = le64_to_cpu(event->cmd_trb); |
9124b121 | 1292 | cmd_trb = xhci->cmd_ring->dequeue; |
23e3be11 | 1293 | cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg, |
9124b121 | 1294 | cmd_trb); |
7f84eef0 SS |
1295 | /* Is the command ring deq ptr out of sync with the deq seg ptr? */ |
1296 | if (cmd_dequeue_dma == 0) { | |
1297 | xhci->error_bitmask |= 1 << 4; | |
1298 | return; | |
1299 | } | |
1300 | /* Does the DMA address match our internal dequeue pointer address? */ | |
1301 | if (cmd_dma != (u64) cmd_dequeue_dma) { | |
1302 | xhci->error_bitmask |= 1 << 5; | |
1303 | return; | |
1304 | } | |
b63f4053 | 1305 | |
c9aa1a2d MN |
1306 | cmd = list_entry(xhci->cmd_list.next, struct xhci_command, cmd_list); |
1307 | ||
1308 | if (cmd->command_trb != xhci->cmd_ring->dequeue) { | |
1309 | xhci_err(xhci, | |
1310 | "Command completion event does not match command\n"); | |
1311 | return; | |
1312 | } | |
c311e391 MN |
1313 | |
1314 | del_timer(&xhci->cmd_timer); | |
1315 | ||
9124b121 | 1316 | trace_xhci_cmd_completion(cmd_trb, (struct xhci_generic_trb *) event); |
63a23b9a | 1317 | |
e7a79a1d | 1318 | cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status)); |
c311e391 MN |
1319 | |
1320 | /* If CMD ring stopped we own the trbs between enqueue and dequeue */ | |
1321 | if (cmd_comp_code == COMP_CMD_STOP) { | |
1322 | xhci_handle_stopped_cmd_ring(xhci, cmd); | |
1323 | return; | |
1324 | } | |
1325 | /* | |
1326 | * Host aborted the command ring, check if the current command was | |
1327 | * supposed to be aborted, otherwise continue normally. | |
1328 | * The command ring is stopped now, but the xHC will issue a Command | |
1329 | * Ring Stopped event which will cause us to restart it. | |
1330 | */ | |
1331 | if (cmd_comp_code == COMP_CMD_ABORT) { | |
1332 | xhci->cmd_ring_state = CMD_RING_STATE_STOPPED; | |
1333 | if (cmd->status == COMP_CMD_ABORT) | |
1334 | goto event_handled; | |
b63f4053 EF |
1335 | } |
1336 | ||
b54fc46d XR |
1337 | cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3])); |
1338 | switch (cmd_type) { | |
1339 | case TRB_ENABLE_SLOT: | |
e7a79a1d | 1340 | xhci_handle_cmd_enable_slot(xhci, slot_id, cmd_comp_code); |
3ffbba95 | 1341 | break; |
b54fc46d | 1342 | case TRB_DISABLE_SLOT: |
6c02dd14 | 1343 | xhci_handle_cmd_disable_slot(xhci, slot_id); |
3ffbba95 | 1344 | break; |
b54fc46d | 1345 | case TRB_CONFIG_EP: |
9ea1833e MN |
1346 | if (!cmd->completion) |
1347 | xhci_handle_cmd_config_ep(xhci, slot_id, event, | |
1348 | cmd_comp_code); | |
f94e0186 | 1349 | break; |
b54fc46d | 1350 | case TRB_EVAL_CONTEXT: |
2d3f1fac | 1351 | break; |
b54fc46d | 1352 | case TRB_ADDR_DEV: |
3ffbba95 | 1353 | break; |
b54fc46d | 1354 | case TRB_STOP_RING: |
b8200c94 XR |
1355 | WARN_ON(slot_id != TRB_TO_SLOT_ID( |
1356 | le32_to_cpu(cmd_trb->generic.field[3]))); | |
1357 | xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb, event); | |
ae636747 | 1358 | break; |
b54fc46d | 1359 | case TRB_SET_DEQ: |
b8200c94 XR |
1360 | WARN_ON(slot_id != TRB_TO_SLOT_ID( |
1361 | le32_to_cpu(cmd_trb->generic.field[3]))); | |
c69a0597 | 1362 | xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code); |
ae636747 | 1363 | break; |
b54fc46d | 1364 | case TRB_CMD_NOOP: |
c311e391 MN |
1365 | /* Is this an aborted command turned to NO-OP? */ |
1366 | if (cmd->status == COMP_CMD_STOP) | |
1367 | cmd_comp_code = COMP_CMD_STOP; | |
7f84eef0 | 1368 | break; |
b54fc46d | 1369 | case TRB_RESET_EP: |
b8200c94 XR |
1370 | WARN_ON(slot_id != TRB_TO_SLOT_ID( |
1371 | le32_to_cpu(cmd_trb->generic.field[3]))); | |
c69a0597 | 1372 | xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code); |
a1587d97 | 1373 | break; |
b54fc46d | 1374 | case TRB_RESET_DEV: |
6fcfb0d6 MN |
1375 | /* SLOT_ID field in reset device cmd completion event TRB is 0. |
1376 | * Use the SLOT_ID from the command TRB instead (xhci 4.6.11) | |
1377 | */ | |
1378 | slot_id = TRB_TO_SLOT_ID( | |
1379 | le32_to_cpu(cmd_trb->generic.field[3])); | |
f681321b | 1380 | xhci_handle_cmd_reset_dev(xhci, slot_id, event); |
2a8f82c4 | 1381 | break; |
b54fc46d | 1382 | case TRB_NEC_GET_FW: |
2c070821 | 1383 | xhci_handle_cmd_nec_get_fw(xhci, event); |
0238634d | 1384 | break; |
7f84eef0 SS |
1385 | default: |
1386 | /* Skip over unknown commands on the event ring */ | |
1387 | xhci->error_bitmask |= 1 << 6; | |
1388 | break; | |
1389 | } | |
c9aa1a2d | 1390 | |
c311e391 MN |
1391 | /* restart timer if this wasn't the last command */ |
1392 | if (cmd->cmd_list.next != &xhci->cmd_list) { | |
1393 | xhci->current_cmd = list_entry(cmd->cmd_list.next, | |
1394 | struct xhci_command, cmd_list); | |
1395 | mod_timer(&xhci->cmd_timer, jiffies + XHCI_CMD_DEFAULT_TIMEOUT); | |
1396 | } | |
1397 | ||
1398 | event_handled: | |
9ea1833e | 1399 | xhci_complete_del_and_free_cmd(cmd, cmd_comp_code); |
c9aa1a2d | 1400 | |
3b72fca0 | 1401 | inc_deq(xhci, xhci->cmd_ring); |
7f84eef0 SS |
1402 | } |
1403 | ||
0238634d SS |
1404 | static void handle_vendor_event(struct xhci_hcd *xhci, |
1405 | union xhci_trb *event) | |
1406 | { | |
1407 | u32 trb_type; | |
1408 | ||
28ccd296 | 1409 | trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3])); |
0238634d SS |
1410 | xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type); |
1411 | if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST)) | |
1412 | handle_cmd_completion(xhci, &event->event_cmd); | |
1413 | } | |
1414 | ||
f6ff0ac8 SS |
1415 | /* @port_id: the one-based port ID from the hardware (indexed from array of all |
1416 | * port registers -- USB 3.0 and USB 2.0). | |
1417 | * | |
1418 | * Returns a zero-based port number, which is suitable for indexing into each of | |
1419 | * the split roothubs' port arrays and bus state arrays. | |
d0cd5d48 | 1420 | * Add one to it in order to call xhci_find_slot_id_by_port. |
f6ff0ac8 SS |
1421 | */ |
1422 | static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd, | |
1423 | struct xhci_hcd *xhci, u32 port_id) | |
1424 | { | |
1425 | unsigned int i; | |
1426 | unsigned int num_similar_speed_ports = 0; | |
1427 | ||
1428 | /* port_id from the hardware is 1-based, but port_array[], usb3_ports[], | |
1429 | * and usb2_ports are 0-based indexes. Count the number of similar | |
1430 | * speed ports, up to 1 port before this port. | |
1431 | */ | |
1432 | for (i = 0; i < (port_id - 1); i++) { | |
1433 | u8 port_speed = xhci->port_array[i]; | |
1434 | ||
1435 | /* | |
1436 | * Skip ports that don't have known speeds, or have duplicate | |
1437 | * Extended Capabilities port speed entries. | |
1438 | */ | |
22e04870 | 1439 | if (port_speed == 0 || port_speed == DUPLICATE_ENTRY) |
f6ff0ac8 SS |
1440 | continue; |
1441 | ||
1442 | /* | |
1443 | * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and | |
1444 | * 1.1 ports are under the USB 2.0 hub. If the port speed | |
1445 | * matches the device speed, it's a similar speed port. | |
1446 | */ | |
1447 | if ((port_speed == 0x03) == (hcd->speed == HCD_USB3)) | |
1448 | num_similar_speed_ports++; | |
1449 | } | |
1450 | return num_similar_speed_ports; | |
1451 | } | |
1452 | ||
623bef9e SS |
1453 | static void handle_device_notification(struct xhci_hcd *xhci, |
1454 | union xhci_trb *event) | |
1455 | { | |
1456 | u32 slot_id; | |
4ee823b8 | 1457 | struct usb_device *udev; |
623bef9e | 1458 | |
7e76ad43 | 1459 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3])); |
4ee823b8 | 1460 | if (!xhci->devs[slot_id]) { |
623bef9e SS |
1461 | xhci_warn(xhci, "Device Notification event for " |
1462 | "unused slot %u\n", slot_id); | |
4ee823b8 SS |
1463 | return; |
1464 | } | |
1465 | ||
1466 | xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n", | |
1467 | slot_id); | |
1468 | udev = xhci->devs[slot_id]->udev; | |
1469 | if (udev && udev->parent) | |
1470 | usb_wakeup_notification(udev->parent, udev->portnum); | |
623bef9e SS |
1471 | } |
1472 | ||
0f2a7930 SS |
1473 | static void handle_port_status(struct xhci_hcd *xhci, |
1474 | union xhci_trb *event) | |
1475 | { | |
f6ff0ac8 | 1476 | struct usb_hcd *hcd; |
0f2a7930 | 1477 | u32 port_id; |
56192531 | 1478 | u32 temp, temp1; |
518e848e | 1479 | int max_ports; |
56192531 | 1480 | int slot_id; |
5308a91b | 1481 | unsigned int faked_port_index; |
f6ff0ac8 | 1482 | u8 major_revision; |
20b67cf5 | 1483 | struct xhci_bus_state *bus_state; |
28ccd296 | 1484 | __le32 __iomem **port_array; |
386139d7 | 1485 | bool bogus_port_status = false; |
0f2a7930 SS |
1486 | |
1487 | /* Port status change events always have a successful completion code */ | |
28ccd296 | 1488 | if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) { |
0f2a7930 SS |
1489 | xhci_warn(xhci, "WARN: xHC returned failed port status event\n"); |
1490 | xhci->error_bitmask |= 1 << 8; | |
1491 | } | |
28ccd296 | 1492 | port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0])); |
0f2a7930 SS |
1493 | xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id); |
1494 | ||
518e848e SS |
1495 | max_ports = HCS_MAX_PORTS(xhci->hcs_params1); |
1496 | if ((port_id <= 0) || (port_id > max_ports)) { | |
56192531 | 1497 | xhci_warn(xhci, "Invalid port id %d\n", port_id); |
09ce0c0c PC |
1498 | inc_deq(xhci, xhci->event_ring); |
1499 | return; | |
56192531 AX |
1500 | } |
1501 | ||
f6ff0ac8 SS |
1502 | /* Figure out which usb_hcd this port is attached to: |
1503 | * is it a USB 3.0 port or a USB 2.0/1.1 port? | |
1504 | */ | |
1505 | major_revision = xhci->port_array[port_id - 1]; | |
09ce0c0c PC |
1506 | |
1507 | /* Find the right roothub. */ | |
1508 | hcd = xhci_to_hcd(xhci); | |
1509 | if ((major_revision == 0x03) != (hcd->speed == HCD_USB3)) | |
1510 | hcd = xhci->shared_hcd; | |
1511 | ||
f6ff0ac8 SS |
1512 | if (major_revision == 0) { |
1513 | xhci_warn(xhci, "Event for port %u not in " | |
1514 | "Extended Capabilities, ignoring.\n", | |
1515 | port_id); | |
386139d7 | 1516 | bogus_port_status = true; |
f6ff0ac8 | 1517 | goto cleanup; |
5308a91b | 1518 | } |
22e04870 | 1519 | if (major_revision == DUPLICATE_ENTRY) { |
f6ff0ac8 SS |
1520 | xhci_warn(xhci, "Event for port %u duplicated in" |
1521 | "Extended Capabilities, ignoring.\n", | |
1522 | port_id); | |
386139d7 | 1523 | bogus_port_status = true; |
f6ff0ac8 SS |
1524 | goto cleanup; |
1525 | } | |
1526 | ||
1527 | /* | |
1528 | * Hardware port IDs reported by a Port Status Change Event include USB | |
1529 | * 3.0 and USB 2.0 ports. We want to check if the port has reported a | |
1530 | * resume event, but we first need to translate the hardware port ID | |
1531 | * into the index into the ports on the correct split roothub, and the | |
1532 | * correct bus_state structure. | |
1533 | */ | |
f6ff0ac8 SS |
1534 | bus_state = &xhci->bus_state[hcd_index(hcd)]; |
1535 | if (hcd->speed == HCD_USB3) | |
1536 | port_array = xhci->usb3_ports; | |
1537 | else | |
1538 | port_array = xhci->usb2_ports; | |
1539 | /* Find the faked port hub number */ | |
1540 | faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci, | |
1541 | port_id); | |
5308a91b | 1542 | |
b0ba9720 | 1543 | temp = readl(port_array[faked_port_index]); |
7111ebc9 | 1544 | if (hcd->state == HC_STATE_SUSPENDED) { |
56192531 AX |
1545 | xhci_dbg(xhci, "resume root hub\n"); |
1546 | usb_hcd_resume_root_hub(hcd); | |
1547 | } | |
1548 | ||
fac4271d ZJC |
1549 | if (hcd->speed == HCD_USB3 && (temp & PORT_PLS_MASK) == XDEV_INACTIVE) |
1550 | bus_state->port_remote_wakeup &= ~(1 << faked_port_index); | |
1551 | ||
56192531 AX |
1552 | if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) { |
1553 | xhci_dbg(xhci, "port resume event for port %d\n", port_id); | |
1554 | ||
b0ba9720 | 1555 | temp1 = readl(&xhci->op_regs->command); |
56192531 AX |
1556 | if (!(temp1 & CMD_RUN)) { |
1557 | xhci_warn(xhci, "xHC is not running.\n"); | |
1558 | goto cleanup; | |
1559 | } | |
1560 | ||
1561 | if (DEV_SUPERSPEED(temp)) { | |
d93814cf | 1562 | xhci_dbg(xhci, "remote wake SS port %d\n", port_id); |
4ee823b8 SS |
1563 | /* Set a flag to say the port signaled remote wakeup, |
1564 | * so we can tell the difference between the end of | |
1565 | * device and host initiated resume. | |
1566 | */ | |
1567 | bus_state->port_remote_wakeup |= 1 << faked_port_index; | |
d93814cf SS |
1568 | xhci_test_and_clear_bit(xhci, port_array, |
1569 | faked_port_index, PORT_PLC); | |
c9682dff AX |
1570 | xhci_set_link_state(xhci, port_array, faked_port_index, |
1571 | XDEV_U0); | |
d93814cf SS |
1572 | /* Need to wait until the next link state change |
1573 | * indicates the device is actually in U0. | |
1574 | */ | |
1575 | bogus_port_status = true; | |
1576 | goto cleanup; | |
56192531 AX |
1577 | } else { |
1578 | xhci_dbg(xhci, "resume HS port %d\n", port_id); | |
f6ff0ac8 | 1579 | bus_state->resume_done[faked_port_index] = jiffies + |
b9e45188 | 1580 | msecs_to_jiffies(USB_RESUME_TIMEOUT); |
f370b996 | 1581 | set_bit(faked_port_index, &bus_state->resuming_ports); |
56192531 | 1582 | mod_timer(&hcd->rh_timer, |
f6ff0ac8 | 1583 | bus_state->resume_done[faked_port_index]); |
56192531 AX |
1584 | /* Do the rest in GetPortStatus */ |
1585 | } | |
1586 | } | |
d93814cf SS |
1587 | |
1588 | if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_U0 && | |
1589 | DEV_SUPERSPEED(temp)) { | |
1590 | xhci_dbg(xhci, "resume SS port %d finished\n", port_id); | |
4ee823b8 SS |
1591 | /* We've just brought the device into U0 through either the |
1592 | * Resume state after a device remote wakeup, or through the | |
1593 | * U3Exit state after a host-initiated resume. If it's a device | |
1594 | * initiated remote wake, don't pass up the link state change, | |
1595 | * so the roothub behavior is consistent with external | |
1596 | * USB 3.0 hub behavior. | |
1597 | */ | |
d93814cf SS |
1598 | slot_id = xhci_find_slot_id_by_port(hcd, xhci, |
1599 | faked_port_index + 1); | |
1600 | if (slot_id && xhci->devs[slot_id]) | |
1601 | xhci_ring_device(xhci, slot_id); | |
ba7b5c22 | 1602 | if (bus_state->port_remote_wakeup & (1 << faked_port_index)) { |
4ee823b8 SS |
1603 | bus_state->port_remote_wakeup &= |
1604 | ~(1 << faked_port_index); | |
1605 | xhci_test_and_clear_bit(xhci, port_array, | |
1606 | faked_port_index, PORT_PLC); | |
1607 | usb_wakeup_notification(hcd->self.root_hub, | |
1608 | faked_port_index + 1); | |
1609 | bogus_port_status = true; | |
1610 | goto cleanup; | |
1611 | } | |
d93814cf | 1612 | } |
56192531 | 1613 | |
8b3d4570 SS |
1614 | /* |
1615 | * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or | |
1616 | * RExit to a disconnect state). If so, let the the driver know it's | |
1617 | * out of the RExit state. | |
1618 | */ | |
1619 | if (!DEV_SUPERSPEED(temp) && | |
1620 | test_and_clear_bit(faked_port_index, | |
1621 | &bus_state->rexit_ports)) { | |
1622 | complete(&bus_state->rexit_done[faked_port_index]); | |
1623 | bogus_port_status = true; | |
1624 | goto cleanup; | |
1625 | } | |
1626 | ||
6fd45621 AX |
1627 | if (hcd->speed != HCD_USB3) |
1628 | xhci_test_and_clear_bit(xhci, port_array, faked_port_index, | |
1629 | PORT_PLC); | |
1630 | ||
56192531 | 1631 | cleanup: |
0f2a7930 | 1632 | /* Update event ring dequeue pointer before dropping the lock */ |
3b72fca0 | 1633 | inc_deq(xhci, xhci->event_ring); |
0f2a7930 | 1634 | |
386139d7 SS |
1635 | /* Don't make the USB core poll the roothub if we got a bad port status |
1636 | * change event. Besides, at that point we can't tell which roothub | |
1637 | * (USB 2.0 or USB 3.0) to kick. | |
1638 | */ | |
1639 | if (bogus_port_status) | |
1640 | return; | |
1641 | ||
c52804a4 SS |
1642 | /* |
1643 | * xHCI port-status-change events occur when the "or" of all the | |
1644 | * status-change bits in the portsc register changes from 0 to 1. | |
1645 | * New status changes won't cause an event if any other change | |
1646 | * bits are still set. When an event occurs, switch over to | |
1647 | * polling to avoid losing status changes. | |
1648 | */ | |
1649 | xhci_dbg(xhci, "%s: starting port polling.\n", __func__); | |
1650 | set_bit(HCD_FLAG_POLL_RH, &hcd->flags); | |
0f2a7930 SS |
1651 | spin_unlock(&xhci->lock); |
1652 | /* Pass this up to the core */ | |
f6ff0ac8 | 1653 | usb_hcd_poll_rh_status(hcd); |
0f2a7930 SS |
1654 | spin_lock(&xhci->lock); |
1655 | } | |
1656 | ||
d0e96f5a SS |
1657 | /* |
1658 | * This TD is defined by the TRBs starting at start_trb in start_seg and ending | |
1659 | * at end_trb, which may be in another segment. If the suspect DMA address is a | |
1660 | * TRB in this TD, this function returns that TRB's segment. Otherwise it | |
1661 | * returns 0. | |
1662 | */ | |
cffb9be8 HG |
1663 | struct xhci_segment *trb_in_td(struct xhci_hcd *xhci, |
1664 | struct xhci_segment *start_seg, | |
d0e96f5a SS |
1665 | union xhci_trb *start_trb, |
1666 | union xhci_trb *end_trb, | |
cffb9be8 HG |
1667 | dma_addr_t suspect_dma, |
1668 | bool debug) | |
d0e96f5a SS |
1669 | { |
1670 | dma_addr_t start_dma; | |
1671 | dma_addr_t end_seg_dma; | |
1672 | dma_addr_t end_trb_dma; | |
1673 | struct xhci_segment *cur_seg; | |
1674 | ||
23e3be11 | 1675 | start_dma = xhci_trb_virt_to_dma(start_seg, start_trb); |
d0e96f5a SS |
1676 | cur_seg = start_seg; |
1677 | ||
1678 | do { | |
2fa88daa | 1679 | if (start_dma == 0) |
326b4810 | 1680 | return NULL; |
ae636747 | 1681 | /* We may get an event for a Link TRB in the middle of a TD */ |
23e3be11 | 1682 | end_seg_dma = xhci_trb_virt_to_dma(cur_seg, |
2fa88daa | 1683 | &cur_seg->trbs[TRBS_PER_SEGMENT - 1]); |
d0e96f5a | 1684 | /* If the end TRB isn't in this segment, this is set to 0 */ |
23e3be11 | 1685 | end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb); |
d0e96f5a | 1686 | |
cffb9be8 HG |
1687 | if (debug) |
1688 | xhci_warn(xhci, | |
1689 | "Looking for event-dma %016llx trb-start %016llx trb-end %016llx seg-start %016llx seg-end %016llx\n", | |
1690 | (unsigned long long)suspect_dma, | |
1691 | (unsigned long long)start_dma, | |
1692 | (unsigned long long)end_trb_dma, | |
1693 | (unsigned long long)cur_seg->dma, | |
1694 | (unsigned long long)end_seg_dma); | |
1695 | ||
d0e96f5a SS |
1696 | if (end_trb_dma > 0) { |
1697 | /* The end TRB is in this segment, so suspect should be here */ | |
1698 | if (start_dma <= end_trb_dma) { | |
1699 | if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma) | |
1700 | return cur_seg; | |
1701 | } else { | |
1702 | /* Case for one segment with | |
1703 | * a TD wrapped around to the top | |
1704 | */ | |
1705 | if ((suspect_dma >= start_dma && | |
1706 | suspect_dma <= end_seg_dma) || | |
1707 | (suspect_dma >= cur_seg->dma && | |
1708 | suspect_dma <= end_trb_dma)) | |
1709 | return cur_seg; | |
1710 | } | |
326b4810 | 1711 | return NULL; |
d0e96f5a SS |
1712 | } else { |
1713 | /* Might still be somewhere in this segment */ | |
1714 | if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma) | |
1715 | return cur_seg; | |
1716 | } | |
1717 | cur_seg = cur_seg->next; | |
23e3be11 | 1718 | start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]); |
2fa88daa | 1719 | } while (cur_seg != start_seg); |
d0e96f5a | 1720 | |
326b4810 | 1721 | return NULL; |
d0e96f5a SS |
1722 | } |
1723 | ||
bcef3fd5 SS |
1724 | static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci, |
1725 | unsigned int slot_id, unsigned int ep_index, | |
e9df17eb | 1726 | unsigned int stream_id, |
bcef3fd5 SS |
1727 | struct xhci_td *td, union xhci_trb *event_trb) |
1728 | { | |
1729 | struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index]; | |
ddba5cd0 MN |
1730 | struct xhci_command *command; |
1731 | command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC); | |
1732 | if (!command) | |
1733 | return; | |
1734 | ||
d0167ad2 | 1735 | ep->ep_state |= EP_HALTED; |
e9df17eb | 1736 | ep->stopped_stream = stream_id; |
1624ae1c | 1737 | |
ddba5cd0 | 1738 | xhci_queue_reset_ep(xhci, command, slot_id, ep_index); |
d97b4f8d | 1739 | xhci_cleanup_stalled_ring(xhci, ep_index, td); |
1624ae1c | 1740 | |
5e5cf6fc | 1741 | ep->stopped_stream = 0; |
1624ae1c | 1742 | |
bcef3fd5 SS |
1743 | xhci_ring_cmd_db(xhci); |
1744 | } | |
1745 | ||
1746 | /* Check if an error has halted the endpoint ring. The class driver will | |
1747 | * cleanup the halt for a non-default control endpoint if we indicate a stall. | |
1748 | * However, a babble and other errors also halt the endpoint ring, and the class | |
1749 | * driver won't clear the halt in that case, so we need to issue a Set Transfer | |
1750 | * Ring Dequeue Pointer command manually. | |
1751 | */ | |
1752 | static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci, | |
1753 | struct xhci_ep_ctx *ep_ctx, | |
1754 | unsigned int trb_comp_code) | |
1755 | { | |
1756 | /* TRB completion codes that may require a manual halt cleanup */ | |
1757 | if (trb_comp_code == COMP_TX_ERR || | |
1758 | trb_comp_code == COMP_BABBLE || | |
1759 | trb_comp_code == COMP_SPLIT_ERR) | |
1760 | /* The 0.96 spec says a babbling control endpoint | |
1761 | * is not halted. The 0.96 spec says it is. Some HW | |
1762 | * claims to be 0.95 compliant, but it halts the control | |
1763 | * endpoint anyway. Check if a babble halted the | |
1764 | * endpoint. | |
1765 | */ | |
f5960b69 ME |
1766 | if ((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) == |
1767 | cpu_to_le32(EP_STATE_HALTED)) | |
bcef3fd5 SS |
1768 | return 1; |
1769 | ||
1770 | return 0; | |
1771 | } | |
1772 | ||
b45b5069 SS |
1773 | int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code) |
1774 | { | |
1775 | if (trb_comp_code >= 224 && trb_comp_code <= 255) { | |
1776 | /* Vendor defined "informational" completion code, | |
1777 | * treat as not-an-error. | |
1778 | */ | |
1779 | xhci_dbg(xhci, "Vendor defined info completion code %u\n", | |
1780 | trb_comp_code); | |
1781 | xhci_dbg(xhci, "Treating code as success.\n"); | |
1782 | return 1; | |
1783 | } | |
1784 | return 0; | |
1785 | } | |
1786 | ||
4422da61 AX |
1787 | /* |
1788 | * Finish the td processing, remove the td from td list; | |
1789 | * Return 1 if the urb can be given back. | |
1790 | */ | |
1791 | static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td, | |
1792 | union xhci_trb *event_trb, struct xhci_transfer_event *event, | |
1793 | struct xhci_virt_ep *ep, int *status, bool skip) | |
1794 | { | |
1795 | struct xhci_virt_device *xdev; | |
1796 | struct xhci_ring *ep_ring; | |
1797 | unsigned int slot_id; | |
1798 | int ep_index; | |
1799 | struct urb *urb = NULL; | |
1800 | struct xhci_ep_ctx *ep_ctx; | |
1801 | int ret = 0; | |
8e51adcc | 1802 | struct urb_priv *urb_priv; |
4422da61 AX |
1803 | u32 trb_comp_code; |
1804 | ||
28ccd296 | 1805 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
4422da61 | 1806 | xdev = xhci->devs[slot_id]; |
28ccd296 ME |
1807 | ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1; |
1808 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); | |
4422da61 | 1809 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
28ccd296 | 1810 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); |
4422da61 AX |
1811 | |
1812 | if (skip) | |
1813 | goto td_cleanup; | |
1814 | ||
69defe04 | 1815 | if (trb_comp_code == COMP_STOP_INVAL || trb_comp_code == COMP_STOP) { |
4422da61 AX |
1816 | /* The Endpoint Stop Command completion will take care of any |
1817 | * stopped TDs. A stopped TD may be restarted, so don't update | |
1818 | * the ring dequeue pointer or take this TD off any lists yet. | |
1819 | */ | |
1820 | ep->stopped_td = td; | |
4422da61 | 1821 | return 0; |
69defe04 MN |
1822 | } |
1823 | if (trb_comp_code == COMP_STALL || | |
1824 | xhci_requires_manual_halt_cleanup(xhci, ep_ctx, | |
1825 | trb_comp_code)) { | |
1826 | /* Issue a reset endpoint command to clear the host side | |
1827 | * halt, followed by a set dequeue command to move the | |
1828 | * dequeue pointer past the TD. | |
1829 | * The class driver clears the device side halt later. | |
1830 | */ | |
1831 | xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index, | |
1832 | ep_ring->stream_id, td, event_trb); | |
4422da61 | 1833 | } else { |
69defe04 MN |
1834 | /* Update ring dequeue pointer */ |
1835 | while (ep_ring->dequeue != td->last_trb) | |
3b72fca0 | 1836 | inc_deq(xhci, ep_ring); |
69defe04 MN |
1837 | inc_deq(xhci, ep_ring); |
1838 | } | |
4422da61 AX |
1839 | |
1840 | td_cleanup: | |
69defe04 MN |
1841 | /* Clean up the endpoint's TD list */ |
1842 | urb = td->urb; | |
1843 | urb_priv = urb->hcpriv; | |
1844 | ||
1845 | /* Do one last check of the actual transfer length. | |
1846 | * If the host controller said we transferred more data than the buffer | |
1847 | * length, urb->actual_length will be a very big number (since it's | |
1848 | * unsigned). Play it safe and say we didn't transfer anything. | |
1849 | */ | |
1850 | if (urb->actual_length > urb->transfer_buffer_length) { | |
1851 | xhci_warn(xhci, "URB transfer length is wrong, xHC issue? req. len = %u, act. len = %u\n", | |
1852 | urb->transfer_buffer_length, | |
1853 | urb->actual_length); | |
1854 | urb->actual_length = 0; | |
1855 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) | |
1856 | *status = -EREMOTEIO; | |
1857 | else | |
1858 | *status = 0; | |
1859 | } | |
1860 | list_del_init(&td->td_list); | |
1861 | /* Was this TD slated to be cancelled but completed anyway? */ | |
1862 | if (!list_empty(&td->cancelled_td_list)) | |
1863 | list_del_init(&td->cancelled_td_list); | |
1864 | ||
1865 | urb_priv->td_cnt++; | |
1866 | /* Giveback the urb when all the tds are completed */ | |
1867 | if (urb_priv->td_cnt == urb_priv->length) { | |
1868 | ret = 1; | |
1869 | if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { | |
1870 | xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--; | |
1871 | if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) { | |
1872 | if (xhci->quirks & XHCI_AMD_PLL_FIX) | |
1873 | usb_amd_quirk_pll_enable(); | |
c41136b0 AX |
1874 | } |
1875 | } | |
4422da61 AX |
1876 | } |
1877 | ||
1878 | return ret; | |
1879 | } | |
1880 | ||
8af56be1 AX |
1881 | /* |
1882 | * Process control tds, update urb status and actual_length. | |
1883 | */ | |
1884 | static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td, | |
1885 | union xhci_trb *event_trb, struct xhci_transfer_event *event, | |
1886 | struct xhci_virt_ep *ep, int *status) | |
1887 | { | |
1888 | struct xhci_virt_device *xdev; | |
1889 | struct xhci_ring *ep_ring; | |
1890 | unsigned int slot_id; | |
1891 | int ep_index; | |
1892 | struct xhci_ep_ctx *ep_ctx; | |
1893 | u32 trb_comp_code; | |
1894 | ||
28ccd296 | 1895 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
8af56be1 | 1896 | xdev = xhci->devs[slot_id]; |
28ccd296 ME |
1897 | ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1; |
1898 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); | |
8af56be1 | 1899 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
28ccd296 | 1900 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); |
8af56be1 | 1901 | |
8af56be1 AX |
1902 | switch (trb_comp_code) { |
1903 | case COMP_SUCCESS: | |
1904 | if (event_trb == ep_ring->dequeue) { | |
1905 | xhci_warn(xhci, "WARN: Success on ctrl setup TRB " | |
1906 | "without IOC set??\n"); | |
1907 | *status = -ESHUTDOWN; | |
1908 | } else if (event_trb != td->last_trb) { | |
1909 | xhci_warn(xhci, "WARN: Success on ctrl data TRB " | |
1910 | "without IOC set??\n"); | |
1911 | *status = -ESHUTDOWN; | |
1912 | } else { | |
8af56be1 AX |
1913 | *status = 0; |
1914 | } | |
1915 | break; | |
1916 | case COMP_SHORT_TX: | |
8af56be1 AX |
1917 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) |
1918 | *status = -EREMOTEIO; | |
1919 | else | |
1920 | *status = 0; | |
1921 | break; | |
3abeca99 SS |
1922 | case COMP_STOP_INVAL: |
1923 | case COMP_STOP: | |
1924 | return finish_td(xhci, td, event_trb, event, ep, status, false); | |
8af56be1 AX |
1925 | default: |
1926 | if (!xhci_requires_manual_halt_cleanup(xhci, | |
1927 | ep_ctx, trb_comp_code)) | |
1928 | break; | |
1929 | xhci_dbg(xhci, "TRB error code %u, " | |
1930 | "halted endpoint index = %u\n", | |
1931 | trb_comp_code, ep_index); | |
1932 | /* else fall through */ | |
1933 | case COMP_STALL: | |
1934 | /* Did we transfer part of the data (middle) phase? */ | |
1935 | if (event_trb != ep_ring->dequeue && | |
1936 | event_trb != td->last_trb) | |
1937 | td->urb->actual_length = | |
1c11a172 VG |
1938 | td->urb->transfer_buffer_length - |
1939 | EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); | |
22ae47e6 | 1940 | else if (!td->urb_length_set) |
8af56be1 AX |
1941 | td->urb->actual_length = 0; |
1942 | ||
8e71a322 | 1943 | return finish_td(xhci, td, event_trb, event, ep, status, false); |
8af56be1 AX |
1944 | } |
1945 | /* | |
1946 | * Did we transfer any data, despite the errors that might have | |
1947 | * happened? I.e. did we get past the setup stage? | |
1948 | */ | |
1949 | if (event_trb != ep_ring->dequeue) { | |
1950 | /* The event was for the status stage */ | |
1951 | if (event_trb == td->last_trb) { | |
45ba2154 | 1952 | if (td->urb_length_set) { |
8af56be1 AX |
1953 | /* Don't overwrite a previously set error code |
1954 | */ | |
1955 | if ((*status == -EINPROGRESS || *status == 0) && | |
1956 | (td->urb->transfer_flags | |
1957 | & URB_SHORT_NOT_OK)) | |
1958 | /* Did we already see a short data | |
1959 | * stage? */ | |
1960 | *status = -EREMOTEIO; | |
1961 | } else { | |
1962 | td->urb->actual_length = | |
1963 | td->urb->transfer_buffer_length; | |
1964 | } | |
1965 | } else { | |
45ba2154 AM |
1966 | /* |
1967 | * Maybe the event was for the data stage? If so, update | |
1968 | * already the actual_length of the URB and flag it as | |
1969 | * set, so that it is not overwritten in the event for | |
1970 | * the last TRB. | |
1971 | */ | |
1972 | td->urb_length_set = true; | |
3abeca99 SS |
1973 | td->urb->actual_length = |
1974 | td->urb->transfer_buffer_length - | |
1c11a172 | 1975 | EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); |
3abeca99 SS |
1976 | xhci_dbg(xhci, "Waiting for status " |
1977 | "stage event\n"); | |
1978 | return 0; | |
8af56be1 AX |
1979 | } |
1980 | } | |
1981 | ||
1982 | return finish_td(xhci, td, event_trb, event, ep, status, false); | |
1983 | } | |
1984 | ||
04e51901 AX |
1985 | /* |
1986 | * Process isochronous tds, update urb packet status and actual_length. | |
1987 | */ | |
1988 | static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td, | |
1989 | union xhci_trb *event_trb, struct xhci_transfer_event *event, | |
1990 | struct xhci_virt_ep *ep, int *status) | |
1991 | { | |
1992 | struct xhci_ring *ep_ring; | |
1993 | struct urb_priv *urb_priv; | |
1994 | int idx; | |
1995 | int len = 0; | |
04e51901 AX |
1996 | union xhci_trb *cur_trb; |
1997 | struct xhci_segment *cur_seg; | |
926008c9 | 1998 | struct usb_iso_packet_descriptor *frame; |
04e51901 | 1999 | u32 trb_comp_code; |
926008c9 | 2000 | bool skip_td = false; |
04e51901 | 2001 | |
28ccd296 ME |
2002 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); |
2003 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); | |
04e51901 AX |
2004 | urb_priv = td->urb->hcpriv; |
2005 | idx = urb_priv->td_cnt; | |
926008c9 | 2006 | frame = &td->urb->iso_frame_desc[idx]; |
04e51901 | 2007 | |
926008c9 DT |
2008 | /* handle completion code */ |
2009 | switch (trb_comp_code) { | |
2010 | case COMP_SUCCESS: | |
1c11a172 | 2011 | if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) { |
1530bbc6 SS |
2012 | frame->status = 0; |
2013 | break; | |
2014 | } | |
2015 | if ((xhci->quirks & XHCI_TRUST_TX_LENGTH)) | |
2016 | trb_comp_code = COMP_SHORT_TX; | |
926008c9 DT |
2017 | case COMP_SHORT_TX: |
2018 | frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ? | |
2019 | -EREMOTEIO : 0; | |
2020 | break; | |
2021 | case COMP_BW_OVER: | |
2022 | frame->status = -ECOMM; | |
2023 | skip_td = true; | |
2024 | break; | |
2025 | case COMP_BUFF_OVER: | |
2026 | case COMP_BABBLE: | |
2027 | frame->status = -EOVERFLOW; | |
2028 | skip_td = true; | |
2029 | break; | |
f6ba6fe2 | 2030 | case COMP_DEV_ERR: |
926008c9 | 2031 | case COMP_STALL: |
d104d015 MN |
2032 | frame->status = -EPROTO; |
2033 | skip_td = true; | |
2034 | break; | |
9c745995 | 2035 | case COMP_TX_ERR: |
926008c9 | 2036 | frame->status = -EPROTO; |
d104d015 MN |
2037 | if (event_trb != td->last_trb) |
2038 | return 0; | |
926008c9 DT |
2039 | skip_td = true; |
2040 | break; | |
2041 | case COMP_STOP: | |
2042 | case COMP_STOP_INVAL: | |
2043 | break; | |
2044 | default: | |
2045 | frame->status = -1; | |
2046 | break; | |
04e51901 AX |
2047 | } |
2048 | ||
926008c9 DT |
2049 | if (trb_comp_code == COMP_SUCCESS || skip_td) { |
2050 | frame->actual_length = frame->length; | |
2051 | td->urb->actual_length += frame->length; | |
04e51901 AX |
2052 | } else { |
2053 | for (cur_trb = ep_ring->dequeue, | |
2054 | cur_seg = ep_ring->deq_seg; cur_trb != event_trb; | |
2055 | next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) { | |
f5960b69 ME |
2056 | if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) && |
2057 | !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) | |
28ccd296 | 2058 | len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])); |
04e51901 | 2059 | } |
28ccd296 | 2060 | len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) - |
1c11a172 | 2061 | EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); |
04e51901 AX |
2062 | |
2063 | if (trb_comp_code != COMP_STOP_INVAL) { | |
926008c9 | 2064 | frame->actual_length = len; |
04e51901 AX |
2065 | td->urb->actual_length += len; |
2066 | } | |
2067 | } | |
2068 | ||
04e51901 AX |
2069 | return finish_td(xhci, td, event_trb, event, ep, status, false); |
2070 | } | |
2071 | ||
926008c9 DT |
2072 | static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td, |
2073 | struct xhci_transfer_event *event, | |
2074 | struct xhci_virt_ep *ep, int *status) | |
2075 | { | |
2076 | struct xhci_ring *ep_ring; | |
2077 | struct urb_priv *urb_priv; | |
2078 | struct usb_iso_packet_descriptor *frame; | |
2079 | int idx; | |
2080 | ||
f6975314 | 2081 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); |
926008c9 DT |
2082 | urb_priv = td->urb->hcpriv; |
2083 | idx = urb_priv->td_cnt; | |
2084 | frame = &td->urb->iso_frame_desc[idx]; | |
2085 | ||
b3df3f9c | 2086 | /* The transfer is partly done. */ |
926008c9 DT |
2087 | frame->status = -EXDEV; |
2088 | ||
2089 | /* calc actual length */ | |
2090 | frame->actual_length = 0; | |
2091 | ||
2092 | /* Update ring dequeue pointer */ | |
2093 | while (ep_ring->dequeue != td->last_trb) | |
3b72fca0 AX |
2094 | inc_deq(xhci, ep_ring); |
2095 | inc_deq(xhci, ep_ring); | |
926008c9 DT |
2096 | |
2097 | return finish_td(xhci, td, NULL, event, ep, status, true); | |
2098 | } | |
2099 | ||
22405ed2 AX |
2100 | /* |
2101 | * Process bulk and interrupt tds, update urb status and actual_length. | |
2102 | */ | |
2103 | static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td, | |
2104 | union xhci_trb *event_trb, struct xhci_transfer_event *event, | |
2105 | struct xhci_virt_ep *ep, int *status) | |
2106 | { | |
2107 | struct xhci_ring *ep_ring; | |
2108 | union xhci_trb *cur_trb; | |
2109 | struct xhci_segment *cur_seg; | |
2110 | u32 trb_comp_code; | |
2111 | ||
28ccd296 ME |
2112 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); |
2113 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); | |
22405ed2 AX |
2114 | |
2115 | switch (trb_comp_code) { | |
2116 | case COMP_SUCCESS: | |
2117 | /* Double check that the HW transferred everything. */ | |
1530bbc6 | 2118 | if (event_trb != td->last_trb || |
1c11a172 | 2119 | EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) { |
22405ed2 AX |
2120 | xhci_warn(xhci, "WARN Successful completion " |
2121 | "on short TX\n"); | |
2122 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) | |
2123 | *status = -EREMOTEIO; | |
2124 | else | |
2125 | *status = 0; | |
1530bbc6 SS |
2126 | if ((xhci->quirks & XHCI_TRUST_TX_LENGTH)) |
2127 | trb_comp_code = COMP_SHORT_TX; | |
22405ed2 | 2128 | } else { |
22405ed2 AX |
2129 | *status = 0; |
2130 | } | |
2131 | break; | |
2132 | case COMP_SHORT_TX: | |
2133 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) | |
2134 | *status = -EREMOTEIO; | |
2135 | else | |
2136 | *status = 0; | |
2137 | break; | |
2138 | default: | |
2139 | /* Others already handled above */ | |
2140 | break; | |
2141 | } | |
f444ff27 SS |
2142 | if (trb_comp_code == COMP_SHORT_TX) |
2143 | xhci_dbg(xhci, "ep %#x - asked for %d bytes, " | |
2144 | "%d bytes untransferred\n", | |
2145 | td->urb->ep->desc.bEndpointAddress, | |
2146 | td->urb->transfer_buffer_length, | |
1c11a172 | 2147 | EVENT_TRB_LEN(le32_to_cpu(event->transfer_len))); |
22405ed2 AX |
2148 | /* Fast path - was this the last TRB in the TD for this URB? */ |
2149 | if (event_trb == td->last_trb) { | |
1c11a172 | 2150 | if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) { |
22405ed2 AX |
2151 | td->urb->actual_length = |
2152 | td->urb->transfer_buffer_length - | |
1c11a172 | 2153 | EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); |
22405ed2 AX |
2154 | if (td->urb->transfer_buffer_length < |
2155 | td->urb->actual_length) { | |
2156 | xhci_warn(xhci, "HC gave bad length " | |
2157 | "of %d bytes left\n", | |
1c11a172 | 2158 | EVENT_TRB_LEN(le32_to_cpu(event->transfer_len))); |
22405ed2 AX |
2159 | td->urb->actual_length = 0; |
2160 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) | |
2161 | *status = -EREMOTEIO; | |
2162 | else | |
2163 | *status = 0; | |
2164 | } | |
2165 | /* Don't overwrite a previously set error code */ | |
2166 | if (*status == -EINPROGRESS) { | |
2167 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) | |
2168 | *status = -EREMOTEIO; | |
2169 | else | |
2170 | *status = 0; | |
2171 | } | |
2172 | } else { | |
2173 | td->urb->actual_length = | |
2174 | td->urb->transfer_buffer_length; | |
2175 | /* Ignore a short packet completion if the | |
2176 | * untransferred length was zero. | |
2177 | */ | |
2178 | if (*status == -EREMOTEIO) | |
2179 | *status = 0; | |
2180 | } | |
2181 | } else { | |
2182 | /* Slow path - walk the list, starting from the dequeue | |
2183 | * pointer, to get the actual length transferred. | |
2184 | */ | |
2185 | td->urb->actual_length = 0; | |
2186 | for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg; | |
2187 | cur_trb != event_trb; | |
2188 | next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) { | |
f5960b69 ME |
2189 | if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) && |
2190 | !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) | |
22405ed2 | 2191 | td->urb->actual_length += |
28ccd296 | 2192 | TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])); |
22405ed2 AX |
2193 | } |
2194 | /* If the ring didn't stop on a Link or No-op TRB, add | |
2195 | * in the actual bytes transferred from the Normal TRB | |
2196 | */ | |
2197 | if (trb_comp_code != COMP_STOP_INVAL) | |
2198 | td->urb->actual_length += | |
28ccd296 | 2199 | TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) - |
1c11a172 | 2200 | EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); |
22405ed2 AX |
2201 | } |
2202 | ||
2203 | return finish_td(xhci, td, event_trb, event, ep, status, false); | |
2204 | } | |
2205 | ||
d0e96f5a SS |
2206 | /* |
2207 | * If this function returns an error condition, it means it got a Transfer | |
2208 | * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address. | |
2209 | * At this point, the host controller is probably hosed and should be reset. | |
2210 | */ | |
2211 | static int handle_tx_event(struct xhci_hcd *xhci, | |
2212 | struct xhci_transfer_event *event) | |
ed384bd3 FB |
2213 | __releases(&xhci->lock) |
2214 | __acquires(&xhci->lock) | |
d0e96f5a SS |
2215 | { |
2216 | struct xhci_virt_device *xdev; | |
63a0d9ab | 2217 | struct xhci_virt_ep *ep; |
d0e96f5a | 2218 | struct xhci_ring *ep_ring; |
82d1009f | 2219 | unsigned int slot_id; |
d0e96f5a | 2220 | int ep_index; |
326b4810 | 2221 | struct xhci_td *td = NULL; |
d0e96f5a SS |
2222 | dma_addr_t event_dma; |
2223 | struct xhci_segment *event_seg; | |
2224 | union xhci_trb *event_trb; | |
326b4810 | 2225 | struct urb *urb = NULL; |
d0e96f5a | 2226 | int status = -EINPROGRESS; |
8e51adcc | 2227 | struct urb_priv *urb_priv; |
d115b048 | 2228 | struct xhci_ep_ctx *ep_ctx; |
c2d7b49f | 2229 | struct list_head *tmp; |
66d1eebc | 2230 | u32 trb_comp_code; |
4422da61 | 2231 | int ret = 0; |
c2d7b49f | 2232 | int td_num = 0; |
d0e96f5a | 2233 | |
28ccd296 | 2234 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
82d1009f | 2235 | xdev = xhci->devs[slot_id]; |
d0e96f5a SS |
2236 | if (!xdev) { |
2237 | xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n"); | |
9258c0b2 | 2238 | xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n", |
e910b440 SS |
2239 | (unsigned long long) xhci_trb_virt_to_dma( |
2240 | xhci->event_ring->deq_seg, | |
9258c0b2 SS |
2241 | xhci->event_ring->dequeue), |
2242 | lower_32_bits(le64_to_cpu(event->buffer)), | |
2243 | upper_32_bits(le64_to_cpu(event->buffer)), | |
2244 | le32_to_cpu(event->transfer_len), | |
2245 | le32_to_cpu(event->flags)); | |
2246 | xhci_dbg(xhci, "Event ring:\n"); | |
2247 | xhci_debug_segment(xhci, xhci->event_ring->deq_seg); | |
d0e96f5a SS |
2248 | return -ENODEV; |
2249 | } | |
2250 | ||
2251 | /* Endpoint ID is 1 based, our index is zero based */ | |
28ccd296 | 2252 | ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1; |
63a0d9ab | 2253 | ep = &xdev->eps[ep_index]; |
28ccd296 | 2254 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); |
d115b048 | 2255 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
986a92d4 | 2256 | if (!ep_ring || |
28ccd296 ME |
2257 | (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) == |
2258 | EP_STATE_DISABLED) { | |
e9df17eb SS |
2259 | xhci_err(xhci, "ERROR Transfer event for disabled endpoint " |
2260 | "or incorrect stream ring\n"); | |
9258c0b2 | 2261 | xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n", |
e910b440 SS |
2262 | (unsigned long long) xhci_trb_virt_to_dma( |
2263 | xhci->event_ring->deq_seg, | |
9258c0b2 SS |
2264 | xhci->event_ring->dequeue), |
2265 | lower_32_bits(le64_to_cpu(event->buffer)), | |
2266 | upper_32_bits(le64_to_cpu(event->buffer)), | |
2267 | le32_to_cpu(event->transfer_len), | |
2268 | le32_to_cpu(event->flags)); | |
2269 | xhci_dbg(xhci, "Event ring:\n"); | |
2270 | xhci_debug_segment(xhci, xhci->event_ring->deq_seg); | |
d0e96f5a SS |
2271 | return -ENODEV; |
2272 | } | |
2273 | ||
c2d7b49f AX |
2274 | /* Count current td numbers if ep->skip is set */ |
2275 | if (ep->skip) { | |
2276 | list_for_each(tmp, &ep_ring->td_list) | |
2277 | td_num++; | |
2278 | } | |
2279 | ||
28ccd296 ME |
2280 | event_dma = le64_to_cpu(event->buffer); |
2281 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); | |
986a92d4 | 2282 | /* Look for common error cases */ |
66d1eebc | 2283 | switch (trb_comp_code) { |
b10de142 SS |
2284 | /* Skip codes that require special handling depending on |
2285 | * transfer type | |
2286 | */ | |
2287 | case COMP_SUCCESS: | |
1c11a172 | 2288 | if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) |
1530bbc6 SS |
2289 | break; |
2290 | if (xhci->quirks & XHCI_TRUST_TX_LENGTH) | |
2291 | trb_comp_code = COMP_SHORT_TX; | |
2292 | else | |
8202ce2e SS |
2293 | xhci_warn_ratelimited(xhci, |
2294 | "WARN Successful completion on short TX: needs XHCI_TRUST_TX_LENGTH quirk?\n"); | |
b10de142 SS |
2295 | case COMP_SHORT_TX: |
2296 | break; | |
ae636747 SS |
2297 | case COMP_STOP: |
2298 | xhci_dbg(xhci, "Stopped on Transfer TRB\n"); | |
2299 | break; | |
2300 | case COMP_STOP_INVAL: | |
2301 | xhci_dbg(xhci, "Stopped on No-op or Link TRB\n"); | |
2302 | break; | |
b10de142 | 2303 | case COMP_STALL: |
2a9227a5 | 2304 | xhci_dbg(xhci, "Stalled endpoint\n"); |
63a0d9ab | 2305 | ep->ep_state |= EP_HALTED; |
b10de142 SS |
2306 | status = -EPIPE; |
2307 | break; | |
2308 | case COMP_TRB_ERR: | |
2309 | xhci_warn(xhci, "WARN: TRB error on endpoint\n"); | |
2310 | status = -EILSEQ; | |
2311 | break; | |
ec74e403 | 2312 | case COMP_SPLIT_ERR: |
b10de142 | 2313 | case COMP_TX_ERR: |
2a9227a5 | 2314 | xhci_dbg(xhci, "Transfer error on endpoint\n"); |
b10de142 SS |
2315 | status = -EPROTO; |
2316 | break; | |
4a73143c | 2317 | case COMP_BABBLE: |
2a9227a5 | 2318 | xhci_dbg(xhci, "Babble error on endpoint\n"); |
4a73143c SS |
2319 | status = -EOVERFLOW; |
2320 | break; | |
b10de142 SS |
2321 | case COMP_DB_ERR: |
2322 | xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n"); | |
2323 | status = -ENOSR; | |
2324 | break; | |
986a92d4 AX |
2325 | case COMP_BW_OVER: |
2326 | xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n"); | |
2327 | break; | |
2328 | case COMP_BUFF_OVER: | |
2329 | xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n"); | |
2330 | break; | |
2331 | case COMP_UNDERRUN: | |
2332 | /* | |
2333 | * When the Isoch ring is empty, the xHC will generate | |
2334 | * a Ring Overrun Event for IN Isoch endpoint or Ring | |
2335 | * Underrun Event for OUT Isoch endpoint. | |
2336 | */ | |
2337 | xhci_dbg(xhci, "underrun event on endpoint\n"); | |
2338 | if (!list_empty(&ep_ring->td_list)) | |
2339 | xhci_dbg(xhci, "Underrun Event for slot %d ep %d " | |
2340 | "still with TDs queued?\n", | |
28ccd296 ME |
2341 | TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), |
2342 | ep_index); | |
986a92d4 AX |
2343 | goto cleanup; |
2344 | case COMP_OVERRUN: | |
2345 | xhci_dbg(xhci, "overrun event on endpoint\n"); | |
2346 | if (!list_empty(&ep_ring->td_list)) | |
2347 | xhci_dbg(xhci, "Overrun Event for slot %d ep %d " | |
2348 | "still with TDs queued?\n", | |
28ccd296 ME |
2349 | TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), |
2350 | ep_index); | |
986a92d4 | 2351 | goto cleanup; |
f6ba6fe2 AH |
2352 | case COMP_DEV_ERR: |
2353 | xhci_warn(xhci, "WARN: detect an incompatible device"); | |
2354 | status = -EPROTO; | |
2355 | break; | |
d18240db AX |
2356 | case COMP_MISSED_INT: |
2357 | /* | |
2358 | * When encounter missed service error, one or more isoc tds | |
2359 | * may be missed by xHC. | |
2360 | * Set skip flag of the ep_ring; Complete the missed tds as | |
2361 | * short transfer when process the ep_ring next time. | |
2362 | */ | |
2363 | ep->skip = true; | |
2364 | xhci_dbg(xhci, "Miss service interval error, set skip flag\n"); | |
2365 | goto cleanup; | |
b10de142 | 2366 | default: |
b45b5069 | 2367 | if (xhci_is_vendor_info_code(xhci, trb_comp_code)) { |
5ad6a529 SS |
2368 | status = 0; |
2369 | break; | |
2370 | } | |
86cd740a MN |
2371 | xhci_warn(xhci, "ERROR Unknown event condition %u, HC probably busted\n", |
2372 | trb_comp_code); | |
986a92d4 AX |
2373 | goto cleanup; |
2374 | } | |
2375 | ||
d18240db AX |
2376 | do { |
2377 | /* This TRB should be in the TD at the head of this ring's | |
2378 | * TD list. | |
2379 | */ | |
2380 | if (list_empty(&ep_ring->td_list)) { | |
a83d6755 SS |
2381 | /* |
2382 | * A stopped endpoint may generate an extra completion | |
2383 | * event if the device was suspended. Don't print | |
2384 | * warnings. | |
2385 | */ | |
2386 | if (!(trb_comp_code == COMP_STOP || | |
2387 | trb_comp_code == COMP_STOP_INVAL)) { | |
2388 | xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n", | |
2389 | TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), | |
2390 | ep_index); | |
2391 | xhci_dbg(xhci, "Event TRB with TRB type ID %u\n", | |
2392 | (le32_to_cpu(event->flags) & | |
2393 | TRB_TYPE_BITMASK)>>10); | |
2394 | xhci_print_trb_offsets(xhci, (union xhci_trb *) event); | |
2395 | } | |
d18240db AX |
2396 | if (ep->skip) { |
2397 | ep->skip = false; | |
2398 | xhci_dbg(xhci, "td_list is empty while skip " | |
2399 | "flag set. Clear skip flag.\n"); | |
2400 | } | |
2401 | ret = 0; | |
2402 | goto cleanup; | |
2403 | } | |
986a92d4 | 2404 | |
c2d7b49f AX |
2405 | /* We've skipped all the TDs on the ep ring when ep->skip set */ |
2406 | if (ep->skip && td_num == 0) { | |
2407 | ep->skip = false; | |
2408 | xhci_dbg(xhci, "All tds on the ep_ring skipped. " | |
2409 | "Clear skip flag.\n"); | |
2410 | ret = 0; | |
2411 | goto cleanup; | |
2412 | } | |
2413 | ||
d18240db | 2414 | td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list); |
c2d7b49f AX |
2415 | if (ep->skip) |
2416 | td_num--; | |
926008c9 | 2417 | |
d18240db | 2418 | /* Is this a TRB in the currently executing TD? */ |
cffb9be8 HG |
2419 | event_seg = trb_in_td(xhci, ep_ring->deq_seg, ep_ring->dequeue, |
2420 | td->last_trb, event_dma, false); | |
e1cf486d AH |
2421 | |
2422 | /* | |
2423 | * Skip the Force Stopped Event. The event_trb(event_dma) of FSE | |
2424 | * is not in the current TD pointed by ep_ring->dequeue because | |
2425 | * that the hardware dequeue pointer still at the previous TRB | |
2426 | * of the current TD. The previous TRB maybe a Link TD or the | |
2427 | * last TRB of the previous TD. The command completion handle | |
2428 | * will take care the rest. | |
2429 | */ | |
9a548863 HG |
2430 | if (!event_seg && (trb_comp_code == COMP_STOP || |
2431 | trb_comp_code == COMP_STOP_INVAL)) { | |
e1cf486d AH |
2432 | ret = 0; |
2433 | goto cleanup; | |
2434 | } | |
2435 | ||
926008c9 DT |
2436 | if (!event_seg) { |
2437 | if (!ep->skip || | |
2438 | !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) { | |
ad808333 SS |
2439 | /* Some host controllers give a spurious |
2440 | * successful event after a short transfer. | |
2441 | * Ignore it. | |
2442 | */ | |
ddba5cd0 | 2443 | if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) && |
ad808333 SS |
2444 | ep_ring->last_td_was_short) { |
2445 | ep_ring->last_td_was_short = false; | |
2446 | ret = 0; | |
2447 | goto cleanup; | |
2448 | } | |
926008c9 DT |
2449 | /* HC is busted, give up! */ |
2450 | xhci_err(xhci, | |
2451 | "ERROR Transfer event TRB DMA ptr not " | |
cffb9be8 HG |
2452 | "part of current TD ep_index %d " |
2453 | "comp_code %u\n", ep_index, | |
2454 | trb_comp_code); | |
2455 | trb_in_td(xhci, ep_ring->deq_seg, | |
2456 | ep_ring->dequeue, td->last_trb, | |
2457 | event_dma, true); | |
926008c9 DT |
2458 | return -ESHUTDOWN; |
2459 | } | |
2460 | ||
2461 | ret = skip_isoc_td(xhci, td, event, ep, &status); | |
2462 | goto cleanup; | |
2463 | } | |
ad808333 SS |
2464 | if (trb_comp_code == COMP_SHORT_TX) |
2465 | ep_ring->last_td_was_short = true; | |
2466 | else | |
2467 | ep_ring->last_td_was_short = false; | |
926008c9 DT |
2468 | |
2469 | if (ep->skip) { | |
d18240db AX |
2470 | xhci_dbg(xhci, "Found td. Clear skip flag.\n"); |
2471 | ep->skip = false; | |
2472 | } | |
678539cf | 2473 | |
926008c9 DT |
2474 | event_trb = &event_seg->trbs[(event_dma - event_seg->dma) / |
2475 | sizeof(*event_trb)]; | |
2476 | /* | |
2477 | * No-op TRB should not trigger interrupts. | |
2478 | * If event_trb is a no-op TRB, it means the | |
2479 | * corresponding TD has been cancelled. Just ignore | |
2480 | * the TD. | |
2481 | */ | |
f5960b69 | 2482 | if (TRB_TYPE_NOOP_LE32(event_trb->generic.field[3])) { |
926008c9 DT |
2483 | xhci_dbg(xhci, |
2484 | "event_trb is a no-op TRB. Skip it\n"); | |
2485 | goto cleanup; | |
d18240db | 2486 | } |
4422da61 | 2487 | |
d18240db AX |
2488 | /* Now update the urb's actual_length and give back to |
2489 | * the core | |
82d1009f | 2490 | */ |
d18240db AX |
2491 | if (usb_endpoint_xfer_control(&td->urb->ep->desc)) |
2492 | ret = process_ctrl_td(xhci, td, event_trb, event, ep, | |
2493 | &status); | |
04e51901 AX |
2494 | else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc)) |
2495 | ret = process_isoc_td(xhci, td, event_trb, event, ep, | |
2496 | &status); | |
d18240db AX |
2497 | else |
2498 | ret = process_bulk_intr_td(xhci, td, event_trb, event, | |
2499 | ep, &status); | |
2500 | ||
2501 | cleanup: | |
2502 | /* | |
2503 | * Do not update event ring dequeue pointer if ep->skip is set. | |
2504 | * Will roll back to continue process missed tds. | |
2505 | */ | |
2506 | if (trb_comp_code == COMP_MISSED_INT || !ep->skip) { | |
3b72fca0 | 2507 | inc_deq(xhci, xhci->event_ring); |
d18240db AX |
2508 | } |
2509 | ||
2510 | if (ret) { | |
2511 | urb = td->urb; | |
8e51adcc | 2512 | urb_priv = urb->hcpriv; |
8e71a322 | 2513 | |
4daf9df5 | 2514 | xhci_urb_free_priv(urb_priv); |
d18240db | 2515 | |
214f76f7 | 2516 | usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb); |
f444ff27 SS |
2517 | if ((urb->actual_length != urb->transfer_buffer_length && |
2518 | (urb->transfer_flags & | |
2519 | URB_SHORT_NOT_OK)) || | |
fd984d24 SS |
2520 | (status != 0 && |
2521 | !usb_endpoint_xfer_isoc(&urb->ep->desc))) | |
f444ff27 | 2522 | xhci_dbg(xhci, "Giveback URB %p, len = %d, " |
1949f9e2 | 2523 | "expected = %d, status = %d\n", |
f444ff27 SS |
2524 | urb, urb->actual_length, |
2525 | urb->transfer_buffer_length, | |
2526 | status); | |
d18240db | 2527 | spin_unlock(&xhci->lock); |
b3df3f9c SS |
2528 | /* EHCI, UHCI, and OHCI always unconditionally set the |
2529 | * urb->status of an isochronous endpoint to 0. | |
2530 | */ | |
2531 | if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) | |
2532 | status = 0; | |
214f76f7 | 2533 | usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status); |
d18240db AX |
2534 | spin_lock(&xhci->lock); |
2535 | } | |
2536 | ||
2537 | /* | |
2538 | * If ep->skip is set, it means there are missed tds on the | |
2539 | * endpoint ring need to take care of. | |
2540 | * Process them as short transfer until reach the td pointed by | |
2541 | * the event. | |
2542 | */ | |
2543 | } while (ep->skip && trb_comp_code != COMP_MISSED_INT); | |
2544 | ||
d0e96f5a SS |
2545 | return 0; |
2546 | } | |
2547 | ||
0f2a7930 SS |
2548 | /* |
2549 | * This function handles all OS-owned events on the event ring. It may drop | |
2550 | * xhci->lock between event processing (e.g. to pass up port status changes). | |
9dee9a21 ME |
2551 | * Returns >0 for "possibly more events to process" (caller should call again), |
2552 | * otherwise 0 if done. In future, <0 returns should indicate error code. | |
0f2a7930 | 2553 | */ |
9dee9a21 | 2554 | static int xhci_handle_event(struct xhci_hcd *xhci) |
7f84eef0 SS |
2555 | { |
2556 | union xhci_trb *event; | |
0f2a7930 | 2557 | int update_ptrs = 1; |
d0e96f5a | 2558 | int ret; |
7f84eef0 SS |
2559 | |
2560 | if (!xhci->event_ring || !xhci->event_ring->dequeue) { | |
2561 | xhci->error_bitmask |= 1 << 1; | |
9dee9a21 | 2562 | return 0; |
7f84eef0 SS |
2563 | } |
2564 | ||
2565 | event = xhci->event_ring->dequeue; | |
2566 | /* Does the HC or OS own the TRB? */ | |
28ccd296 ME |
2567 | if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) != |
2568 | xhci->event_ring->cycle_state) { | |
7f84eef0 | 2569 | xhci->error_bitmask |= 1 << 2; |
9dee9a21 | 2570 | return 0; |
7f84eef0 SS |
2571 | } |
2572 | ||
92a3da41 ME |
2573 | /* |
2574 | * Barrier between reading the TRB_CYCLE (valid) flag above and any | |
2575 | * speculative reads of the event's flags/data below. | |
2576 | */ | |
2577 | rmb(); | |
0f2a7930 | 2578 | /* FIXME: Handle more event types. */ |
28ccd296 | 2579 | switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) { |
7f84eef0 SS |
2580 | case TRB_TYPE(TRB_COMPLETION): |
2581 | handle_cmd_completion(xhci, &event->event_cmd); | |
2582 | break; | |
0f2a7930 SS |
2583 | case TRB_TYPE(TRB_PORT_STATUS): |
2584 | handle_port_status(xhci, event); | |
2585 | update_ptrs = 0; | |
2586 | break; | |
d0e96f5a SS |
2587 | case TRB_TYPE(TRB_TRANSFER): |
2588 | ret = handle_tx_event(xhci, &event->trans_event); | |
2589 | if (ret < 0) | |
2590 | xhci->error_bitmask |= 1 << 9; | |
2591 | else | |
2592 | update_ptrs = 0; | |
2593 | break; | |
623bef9e SS |
2594 | case TRB_TYPE(TRB_DEV_NOTE): |
2595 | handle_device_notification(xhci, event); | |
2596 | break; | |
7f84eef0 | 2597 | default: |
28ccd296 ME |
2598 | if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >= |
2599 | TRB_TYPE(48)) | |
0238634d SS |
2600 | handle_vendor_event(xhci, event); |
2601 | else | |
2602 | xhci->error_bitmask |= 1 << 3; | |
7f84eef0 | 2603 | } |
6f5165cf SS |
2604 | /* Any of the above functions may drop and re-acquire the lock, so check |
2605 | * to make sure a watchdog timer didn't mark the host as non-responsive. | |
2606 | */ | |
2607 | if (xhci->xhc_state & XHCI_STATE_DYING) { | |
2608 | xhci_dbg(xhci, "xHCI host dying, returning from " | |
2609 | "event handler.\n"); | |
9dee9a21 | 2610 | return 0; |
6f5165cf | 2611 | } |
7f84eef0 | 2612 | |
c06d68b8 SS |
2613 | if (update_ptrs) |
2614 | /* Update SW event ring dequeue pointer */ | |
3b72fca0 | 2615 | inc_deq(xhci, xhci->event_ring); |
c06d68b8 | 2616 | |
9dee9a21 ME |
2617 | /* Are there more items on the event ring? Caller will call us again to |
2618 | * check. | |
2619 | */ | |
2620 | return 1; | |
7f84eef0 | 2621 | } |
9032cd52 SS |
2622 | |
2623 | /* | |
2624 | * xHCI spec says we can get an interrupt, and if the HC has an error condition, | |
2625 | * we might get bad data out of the event ring. Section 4.10.2.7 has a list of | |
2626 | * indicators of an event TRB error, but we check the status *first* to be safe. | |
2627 | */ | |
2628 | irqreturn_t xhci_irq(struct usb_hcd *hcd) | |
2629 | { | |
2630 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
c21599a3 | 2631 | u32 status; |
bda53145 | 2632 | u64 temp_64; |
c06d68b8 SS |
2633 | union xhci_trb *event_ring_deq; |
2634 | dma_addr_t deq; | |
9032cd52 SS |
2635 | |
2636 | spin_lock(&xhci->lock); | |
9032cd52 | 2637 | /* Check if the xHC generated the interrupt, or the irq is shared */ |
b0ba9720 | 2638 | status = readl(&xhci->op_regs->status); |
c21599a3 | 2639 | if (status == 0xffffffff) |
9032cd52 SS |
2640 | goto hw_died; |
2641 | ||
c21599a3 | 2642 | if (!(status & STS_EINT)) { |
9032cd52 | 2643 | spin_unlock(&xhci->lock); |
9032cd52 SS |
2644 | return IRQ_NONE; |
2645 | } | |
27e0dd4d | 2646 | if (status & STS_FATAL) { |
9032cd52 SS |
2647 | xhci_warn(xhci, "WARNING: Host System Error\n"); |
2648 | xhci_halt(xhci); | |
2649 | hw_died: | |
9032cd52 | 2650 | spin_unlock(&xhci->lock); |
948fa135 | 2651 | return IRQ_HANDLED; |
9032cd52 SS |
2652 | } |
2653 | ||
bda53145 SS |
2654 | /* |
2655 | * Clear the op reg interrupt status first, | |
2656 | * so we can receive interrupts from other MSI-X interrupters. | |
2657 | * Write 1 to clear the interrupt status. | |
2658 | */ | |
27e0dd4d | 2659 | status |= STS_EINT; |
204b7793 | 2660 | writel(status, &xhci->op_regs->status); |
bda53145 SS |
2661 | /* FIXME when MSI-X is supported and there are multiple vectors */ |
2662 | /* Clear the MSI-X event interrupt status */ | |
2663 | ||
cd70469d | 2664 | if (hcd->irq) { |
c21599a3 SS |
2665 | u32 irq_pending; |
2666 | /* Acknowledge the PCI interrupt */ | |
b0ba9720 | 2667 | irq_pending = readl(&xhci->ir_set->irq_pending); |
4e833c0b | 2668 | irq_pending |= IMAN_IP; |
204b7793 | 2669 | writel(irq_pending, &xhci->ir_set->irq_pending); |
c21599a3 | 2670 | } |
bda53145 | 2671 | |
c06d68b8 | 2672 | if (xhci->xhc_state & XHCI_STATE_DYING) { |
bda53145 SS |
2673 | xhci_dbg(xhci, "xHCI dying, ignoring interrupt. " |
2674 | "Shouldn't IRQs be disabled?\n"); | |
c06d68b8 SS |
2675 | /* Clear the event handler busy flag (RW1C); |
2676 | * the event ring should be empty. | |
bda53145 | 2677 | */ |
f7b2e403 | 2678 | temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); |
477632df SS |
2679 | xhci_write_64(xhci, temp_64 | ERST_EHB, |
2680 | &xhci->ir_set->erst_dequeue); | |
c06d68b8 SS |
2681 | spin_unlock(&xhci->lock); |
2682 | ||
2683 | return IRQ_HANDLED; | |
2684 | } | |
2685 | ||
2686 | event_ring_deq = xhci->event_ring->dequeue; | |
2687 | /* FIXME this should be a delayed service routine | |
2688 | * that clears the EHB. | |
2689 | */ | |
9dee9a21 | 2690 | while (xhci_handle_event(xhci) > 0) {} |
bda53145 | 2691 | |
f7b2e403 | 2692 | temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); |
c06d68b8 SS |
2693 | /* If necessary, update the HW's version of the event ring deq ptr. */ |
2694 | if (event_ring_deq != xhci->event_ring->dequeue) { | |
2695 | deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg, | |
2696 | xhci->event_ring->dequeue); | |
2697 | if (deq == 0) | |
2698 | xhci_warn(xhci, "WARN something wrong with SW event " | |
2699 | "ring dequeue ptr.\n"); | |
2700 | /* Update HC event ring dequeue pointer */ | |
2701 | temp_64 &= ERST_PTR_MASK; | |
2702 | temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK); | |
2703 | } | |
2704 | ||
2705 | /* Clear the event handler busy flag (RW1C); event ring is empty. */ | |
2706 | temp_64 |= ERST_EHB; | |
477632df | 2707 | xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue); |
c06d68b8 | 2708 | |
9032cd52 SS |
2709 | spin_unlock(&xhci->lock); |
2710 | ||
2711 | return IRQ_HANDLED; | |
2712 | } | |
2713 | ||
851ec164 | 2714 | irqreturn_t xhci_msi_irq(int irq, void *hcd) |
9032cd52 | 2715 | { |
968b822c | 2716 | return xhci_irq(hcd); |
9032cd52 | 2717 | } |
7f84eef0 | 2718 | |
d0e96f5a SS |
2719 | /**** Endpoint Ring Operations ****/ |
2720 | ||
7f84eef0 SS |
2721 | /* |
2722 | * Generic function for queueing a TRB on a ring. | |
2723 | * The caller must have checked to make sure there's room on the ring. | |
6cc30d85 SS |
2724 | * |
2725 | * @more_trbs_coming: Will you enqueue more TRBs before calling | |
2726 | * prepare_transfer()? | |
7f84eef0 SS |
2727 | */ |
2728 | static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring, | |
3b72fca0 | 2729 | bool more_trbs_coming, |
7f84eef0 SS |
2730 | u32 field1, u32 field2, u32 field3, u32 field4) |
2731 | { | |
2732 | struct xhci_generic_trb *trb; | |
2733 | ||
2734 | trb = &ring->enqueue->generic; | |
28ccd296 ME |
2735 | trb->field[0] = cpu_to_le32(field1); |
2736 | trb->field[1] = cpu_to_le32(field2); | |
2737 | trb->field[2] = cpu_to_le32(field3); | |
2738 | trb->field[3] = cpu_to_le32(field4); | |
3b72fca0 | 2739 | inc_enq(xhci, ring, more_trbs_coming); |
7f84eef0 SS |
2740 | } |
2741 | ||
d0e96f5a SS |
2742 | /* |
2743 | * Does various checks on the endpoint ring, and makes it ready to queue num_trbs. | |
2744 | * FIXME allocate segments if the ring is full. | |
2745 | */ | |
2746 | static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring, | |
3b72fca0 | 2747 | u32 ep_state, unsigned int num_trbs, gfp_t mem_flags) |
d0e96f5a | 2748 | { |
8dfec614 AX |
2749 | unsigned int num_trbs_needed; |
2750 | ||
d0e96f5a | 2751 | /* Make sure the endpoint has been added to xHC schedule */ |
d0e96f5a SS |
2752 | switch (ep_state) { |
2753 | case EP_STATE_DISABLED: | |
2754 | /* | |
2755 | * USB core changed config/interfaces without notifying us, | |
2756 | * or hardware is reporting the wrong state. | |
2757 | */ | |
2758 | xhci_warn(xhci, "WARN urb submitted to disabled ep\n"); | |
2759 | return -ENOENT; | |
d0e96f5a | 2760 | case EP_STATE_ERROR: |
c92bcfa7 | 2761 | xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n"); |
d0e96f5a SS |
2762 | /* FIXME event handling code for error needs to clear it */ |
2763 | /* XXX not sure if this should be -ENOENT or not */ | |
2764 | return -EINVAL; | |
c92bcfa7 SS |
2765 | case EP_STATE_HALTED: |
2766 | xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n"); | |
d0e96f5a SS |
2767 | case EP_STATE_STOPPED: |
2768 | case EP_STATE_RUNNING: | |
2769 | break; | |
2770 | default: | |
2771 | xhci_err(xhci, "ERROR unknown endpoint state for ep\n"); | |
2772 | /* | |
2773 | * FIXME issue Configure Endpoint command to try to get the HC | |
2774 | * back into a known state. | |
2775 | */ | |
2776 | return -EINVAL; | |
2777 | } | |
8dfec614 AX |
2778 | |
2779 | while (1) { | |
3d4b81ed SS |
2780 | if (room_on_ring(xhci, ep_ring, num_trbs)) |
2781 | break; | |
8dfec614 AX |
2782 | |
2783 | if (ep_ring == xhci->cmd_ring) { | |
2784 | xhci_err(xhci, "Do not support expand command ring\n"); | |
2785 | return -ENOMEM; | |
2786 | } | |
2787 | ||
68ffb011 XR |
2788 | xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion, |
2789 | "ERROR no room on ep ring, try ring expansion"); | |
8dfec614 AX |
2790 | num_trbs_needed = num_trbs - ep_ring->num_trbs_free; |
2791 | if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed, | |
2792 | mem_flags)) { | |
2793 | xhci_err(xhci, "Ring expansion failed\n"); | |
2794 | return -ENOMEM; | |
2795 | } | |
261fa12b | 2796 | } |
6c12db90 JY |
2797 | |
2798 | if (enqueue_is_link_trb(ep_ring)) { | |
2799 | struct xhci_ring *ring = ep_ring; | |
2800 | union xhci_trb *next; | |
6c12db90 | 2801 | |
6c12db90 JY |
2802 | next = ring->enqueue; |
2803 | ||
2804 | while (last_trb(xhci, ring, ring->enq_seg, next)) { | |
7e393a83 AX |
2805 | /* If we're not dealing with 0.95 hardware or isoc rings |
2806 | * on AMD 0.96 host, clear the chain bit. | |
6c12db90 | 2807 | */ |
3b72fca0 AX |
2808 | if (!xhci_link_trb_quirk(xhci) && |
2809 | !(ring->type == TYPE_ISOC && | |
2810 | (xhci->quirks & XHCI_AMD_0x96_HOST))) | |
28ccd296 | 2811 | next->link.control &= cpu_to_le32(~TRB_CHAIN); |
6c12db90 | 2812 | else |
28ccd296 | 2813 | next->link.control |= cpu_to_le32(TRB_CHAIN); |
6c12db90 JY |
2814 | |
2815 | wmb(); | |
f5960b69 | 2816 | next->link.control ^= cpu_to_le32(TRB_CYCLE); |
6c12db90 JY |
2817 | |
2818 | /* Toggle the cycle bit after the last ring segment. */ | |
2819 | if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) { | |
e5401bf3 | 2820 | ring->cycle_state ^= 1; |
6c12db90 JY |
2821 | } |
2822 | ring->enq_seg = ring->enq_seg->next; | |
2823 | ring->enqueue = ring->enq_seg->trbs; | |
2824 | next = ring->enqueue; | |
2825 | } | |
2826 | } | |
2827 | ||
d0e96f5a SS |
2828 | return 0; |
2829 | } | |
2830 | ||
23e3be11 | 2831 | static int prepare_transfer(struct xhci_hcd *xhci, |
d0e96f5a SS |
2832 | struct xhci_virt_device *xdev, |
2833 | unsigned int ep_index, | |
e9df17eb | 2834 | unsigned int stream_id, |
d0e96f5a SS |
2835 | unsigned int num_trbs, |
2836 | struct urb *urb, | |
8e51adcc | 2837 | unsigned int td_index, |
d0e96f5a SS |
2838 | gfp_t mem_flags) |
2839 | { | |
2840 | int ret; | |
8e51adcc AX |
2841 | struct urb_priv *urb_priv; |
2842 | struct xhci_td *td; | |
e9df17eb | 2843 | struct xhci_ring *ep_ring; |
d115b048 | 2844 | struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
e9df17eb SS |
2845 | |
2846 | ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id); | |
2847 | if (!ep_ring) { | |
2848 | xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n", | |
2849 | stream_id); | |
2850 | return -EINVAL; | |
2851 | } | |
2852 | ||
2853 | ret = prepare_ring(xhci, ep_ring, | |
28ccd296 | 2854 | le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK, |
3b72fca0 | 2855 | num_trbs, mem_flags); |
d0e96f5a SS |
2856 | if (ret) |
2857 | return ret; | |
d0e96f5a | 2858 | |
8e51adcc AX |
2859 | urb_priv = urb->hcpriv; |
2860 | td = urb_priv->td[td_index]; | |
2861 | ||
2862 | INIT_LIST_HEAD(&td->td_list); | |
2863 | INIT_LIST_HEAD(&td->cancelled_td_list); | |
2864 | ||
2865 | if (td_index == 0) { | |
214f76f7 | 2866 | ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb); |
d13565c1 | 2867 | if (unlikely(ret)) |
8e51adcc | 2868 | return ret; |
d0e96f5a SS |
2869 | } |
2870 | ||
8e51adcc | 2871 | td->urb = urb; |
d0e96f5a | 2872 | /* Add this TD to the tail of the endpoint ring's TD list */ |
8e51adcc AX |
2873 | list_add_tail(&td->td_list, &ep_ring->td_list); |
2874 | td->start_seg = ep_ring->enq_seg; | |
2875 | td->first_trb = ep_ring->enqueue; | |
2876 | ||
2877 | urb_priv->td[td_index] = td; | |
d0e96f5a SS |
2878 | |
2879 | return 0; | |
2880 | } | |
2881 | ||
23e3be11 | 2882 | static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb) |
8a96c052 SS |
2883 | { |
2884 | int num_sgs, num_trbs, running_total, temp, i; | |
2885 | struct scatterlist *sg; | |
2886 | ||
2887 | sg = NULL; | |
bc677d5b | 2888 | num_sgs = urb->num_mapped_sgs; |
8a96c052 SS |
2889 | temp = urb->transfer_buffer_length; |
2890 | ||
8a96c052 | 2891 | num_trbs = 0; |
910f8d0c | 2892 | for_each_sg(urb->sg, sg, num_sgs, i) { |
8a96c052 SS |
2893 | unsigned int len = sg_dma_len(sg); |
2894 | ||
2895 | /* Scatter gather list entries may cross 64KB boundaries */ | |
2896 | running_total = TRB_MAX_BUFF_SIZE - | |
a2490187 | 2897 | (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1)); |
5807795b | 2898 | running_total &= TRB_MAX_BUFF_SIZE - 1; |
8a96c052 SS |
2899 | if (running_total != 0) |
2900 | num_trbs++; | |
2901 | ||
2902 | /* How many more 64KB chunks to transfer, how many more TRBs? */ | |
bcd2fde0 | 2903 | while (running_total < sg_dma_len(sg) && running_total < temp) { |
8a96c052 SS |
2904 | num_trbs++; |
2905 | running_total += TRB_MAX_BUFF_SIZE; | |
2906 | } | |
8a96c052 SS |
2907 | len = min_t(int, len, temp); |
2908 | temp -= len; | |
2909 | if (temp == 0) | |
2910 | break; | |
2911 | } | |
8a96c052 SS |
2912 | return num_trbs; |
2913 | } | |
2914 | ||
23e3be11 | 2915 | static void check_trb_math(struct urb *urb, int num_trbs, int running_total) |
8a96c052 SS |
2916 | { |
2917 | if (num_trbs != 0) | |
a2490187 | 2918 | dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of " |
8a96c052 SS |
2919 | "TRBs, %d left\n", __func__, |
2920 | urb->ep->desc.bEndpointAddress, num_trbs); | |
2921 | if (running_total != urb->transfer_buffer_length) | |
a2490187 | 2922 | dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, " |
8a96c052 SS |
2923 | "queued %#x (%d), asked for %#x (%d)\n", |
2924 | __func__, | |
2925 | urb->ep->desc.bEndpointAddress, | |
2926 | running_total, running_total, | |
2927 | urb->transfer_buffer_length, | |
2928 | urb->transfer_buffer_length); | |
2929 | } | |
2930 | ||
23e3be11 | 2931 | static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id, |
e9df17eb | 2932 | unsigned int ep_index, unsigned int stream_id, int start_cycle, |
e1eab2e0 | 2933 | struct xhci_generic_trb *start_trb) |
8a96c052 | 2934 | { |
8a96c052 SS |
2935 | /* |
2936 | * Pass all the TRBs to the hardware at once and make sure this write | |
2937 | * isn't reordered. | |
2938 | */ | |
2939 | wmb(); | |
50f7b52a | 2940 | if (start_cycle) |
28ccd296 | 2941 | start_trb->field[3] |= cpu_to_le32(start_cycle); |
50f7b52a | 2942 | else |
28ccd296 | 2943 | start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE); |
be88fe4f | 2944 | xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id); |
8a96c052 SS |
2945 | } |
2946 | ||
624defa1 SS |
2947 | /* |
2948 | * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt | |
2949 | * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD | |
2950 | * (comprised of sg list entries) can take several service intervals to | |
2951 | * transmit. | |
2952 | */ | |
2953 | int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |
2954 | struct urb *urb, int slot_id, unsigned int ep_index) | |
2955 | { | |
2956 | struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, | |
2957 | xhci->devs[slot_id]->out_ctx, ep_index); | |
2958 | int xhci_interval; | |
2959 | int ep_interval; | |
2960 | ||
28ccd296 | 2961 | xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info)); |
624defa1 SS |
2962 | ep_interval = urb->interval; |
2963 | /* Convert to microframes */ | |
2964 | if (urb->dev->speed == USB_SPEED_LOW || | |
2965 | urb->dev->speed == USB_SPEED_FULL) | |
2966 | ep_interval *= 8; | |
2967 | /* FIXME change this to a warning and a suggestion to use the new API | |
2968 | * to set the polling interval (once the API is added). | |
2969 | */ | |
2970 | if (xhci_interval != ep_interval) { | |
0730d52a DK |
2971 | dev_dbg_ratelimited(&urb->dev->dev, |
2972 | "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n", | |
2973 | ep_interval, ep_interval == 1 ? "" : "s", | |
2974 | xhci_interval, xhci_interval == 1 ? "" : "s"); | |
624defa1 SS |
2975 | urb->interval = xhci_interval; |
2976 | /* Convert back to frames for LS/FS devices */ | |
2977 | if (urb->dev->speed == USB_SPEED_LOW || | |
2978 | urb->dev->speed == USB_SPEED_FULL) | |
2979 | urb->interval /= 8; | |
2980 | } | |
3fc8206d | 2981 | return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index); |
624defa1 SS |
2982 | } |
2983 | ||
04dd950d SS |
2984 | /* |
2985 | * The TD size is the number of bytes remaining in the TD (including this TRB), | |
2986 | * right shifted by 10. | |
2987 | * It must fit in bits 21:17, so it can't be bigger than 31. | |
2988 | */ | |
2989 | static u32 xhci_td_remainder(unsigned int remainder) | |
2990 | { | |
2991 | u32 max = (1 << (21 - 17 + 1)) - 1; | |
2992 | ||
2993 | if ((remainder >> 10) >= max) | |
2994 | return max << 17; | |
2995 | else | |
2996 | return (remainder >> 10) << 17; | |
2997 | } | |
2998 | ||
4da6e6f2 | 2999 | /* |
4525c0a1 SS |
3000 | * For xHCI 1.0 host controllers, TD size is the number of max packet sized |
3001 | * packets remaining in the TD (*not* including this TRB). | |
4da6e6f2 SS |
3002 | * |
3003 | * Total TD packet count = total_packet_count = | |
4525c0a1 | 3004 | * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize) |
4da6e6f2 SS |
3005 | * |
3006 | * Packets transferred up to and including this TRB = packets_transferred = | |
3007 | * rounddown(total bytes transferred including this TRB / wMaxPacketSize) | |
3008 | * | |
3009 | * TD size = total_packet_count - packets_transferred | |
3010 | * | |
3011 | * It must fit in bits 21:17, so it can't be bigger than 31. | |
4525c0a1 | 3012 | * The last TRB in a TD must have the TD size set to zero. |
4da6e6f2 | 3013 | */ |
4da6e6f2 | 3014 | static u32 xhci_v1_0_td_remainder(int running_total, int trb_buff_len, |
4525c0a1 SS |
3015 | unsigned int total_packet_count, struct urb *urb, |
3016 | unsigned int num_trbs_left) | |
4da6e6f2 SS |
3017 | { |
3018 | int packets_transferred; | |
3019 | ||
48df4a6f | 3020 | /* One TRB with a zero-length data packet. */ |
4525c0a1 | 3021 | if (num_trbs_left == 0 || (running_total == 0 && trb_buff_len == 0)) |
48df4a6f SS |
3022 | return 0; |
3023 | ||
4da6e6f2 SS |
3024 | /* All the TRB queueing functions don't count the current TRB in |
3025 | * running_total. | |
3026 | */ | |
3027 | packets_transferred = (running_total + trb_buff_len) / | |
f18f8ed2 | 3028 | GET_MAX_PACKET(usb_endpoint_maxp(&urb->ep->desc)); |
4da6e6f2 | 3029 | |
4525c0a1 SS |
3030 | if ((total_packet_count - packets_transferred) > 31) |
3031 | return 31 << 17; | |
3032 | return (total_packet_count - packets_transferred) << 17; | |
4da6e6f2 SS |
3033 | } |
3034 | ||
23e3be11 | 3035 | static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags, |
8a96c052 SS |
3036 | struct urb *urb, int slot_id, unsigned int ep_index) |
3037 | { | |
3038 | struct xhci_ring *ep_ring; | |
3039 | unsigned int num_trbs; | |
8e51adcc | 3040 | struct urb_priv *urb_priv; |
8a96c052 SS |
3041 | struct xhci_td *td; |
3042 | struct scatterlist *sg; | |
3043 | int num_sgs; | |
4758dcd1 | 3044 | int trb_buff_len, this_sg_len, running_total, ret; |
4da6e6f2 | 3045 | unsigned int total_packet_count; |
4758dcd1 | 3046 | bool zero_length_needed; |
8a96c052 | 3047 | bool first_trb; |
4758dcd1 | 3048 | int last_trb_num; |
8a96c052 | 3049 | u64 addr; |
6cc30d85 | 3050 | bool more_trbs_coming; |
8a96c052 SS |
3051 | |
3052 | struct xhci_generic_trb *start_trb; | |
3053 | int start_cycle; | |
3054 | ||
e9df17eb SS |
3055 | ep_ring = xhci_urb_to_transfer_ring(xhci, urb); |
3056 | if (!ep_ring) | |
3057 | return -EINVAL; | |
3058 | ||
8a96c052 | 3059 | num_trbs = count_sg_trbs_needed(xhci, urb); |
bc677d5b | 3060 | num_sgs = urb->num_mapped_sgs; |
4525c0a1 | 3061 | total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length, |
29cc8897 | 3062 | usb_endpoint_maxp(&urb->ep->desc)); |
8a96c052 | 3063 | |
4758dcd1 | 3064 | ret = prepare_transfer(xhci, xhci->devs[slot_id], |
e9df17eb | 3065 | ep_index, urb->stream_id, |
3b72fca0 | 3066 | num_trbs, urb, 0, mem_flags); |
4758dcd1 RA |
3067 | if (ret < 0) |
3068 | return ret; | |
8e51adcc AX |
3069 | |
3070 | urb_priv = urb->hcpriv; | |
4758dcd1 RA |
3071 | |
3072 | /* Deal with URB_ZERO_PACKET - need one more td/trb */ | |
3073 | zero_length_needed = urb->transfer_flags & URB_ZERO_PACKET && | |
3074 | urb_priv->length == 2; | |
3075 | if (zero_length_needed) { | |
3076 | num_trbs++; | |
3077 | xhci_dbg(xhci, "Creating zero length td.\n"); | |
3078 | ret = prepare_transfer(xhci, xhci->devs[slot_id], | |
3079 | ep_index, urb->stream_id, | |
3080 | 1, urb, 1, mem_flags); | |
3081 | if (ret < 0) | |
3082 | return ret; | |
3083 | } | |
3084 | ||
8e51adcc AX |
3085 | td = urb_priv->td[0]; |
3086 | ||
8a96c052 SS |
3087 | /* |
3088 | * Don't give the first TRB to the hardware (by toggling the cycle bit) | |
3089 | * until we've finished creating all the other TRBs. The ring's cycle | |
3090 | * state may change as we enqueue the other TRBs, so save it too. | |
3091 | */ | |
3092 | start_trb = &ep_ring->enqueue->generic; | |
3093 | start_cycle = ep_ring->cycle_state; | |
3094 | ||
3095 | running_total = 0; | |
3096 | /* | |
3097 | * How much data is in the first TRB? | |
3098 | * | |
3099 | * There are three forces at work for TRB buffer pointers and lengths: | |
3100 | * 1. We don't want to walk off the end of this sg-list entry buffer. | |
3101 | * 2. The transfer length that the driver requested may be smaller than | |
3102 | * the amount of memory allocated for this scatter-gather list. | |
3103 | * 3. TRBs buffers can't cross 64KB boundaries. | |
3104 | */ | |
910f8d0c | 3105 | sg = urb->sg; |
8a96c052 SS |
3106 | addr = (u64) sg_dma_address(sg); |
3107 | this_sg_len = sg_dma_len(sg); | |
a2490187 | 3108 | trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1)); |
8a96c052 SS |
3109 | trb_buff_len = min_t(int, trb_buff_len, this_sg_len); |
3110 | if (trb_buff_len > urb->transfer_buffer_length) | |
3111 | trb_buff_len = urb->transfer_buffer_length; | |
8a96c052 SS |
3112 | |
3113 | first_trb = true; | |
4758dcd1 | 3114 | last_trb_num = zero_length_needed ? 2 : 1; |
8a96c052 SS |
3115 | /* Queue the first TRB, even if it's zero-length */ |
3116 | do { | |
3117 | u32 field = 0; | |
f9dc68fe | 3118 | u32 length_field = 0; |
04dd950d | 3119 | u32 remainder = 0; |
8a96c052 SS |
3120 | |
3121 | /* Don't change the cycle bit of the first TRB until later */ | |
50f7b52a | 3122 | if (first_trb) { |
8a96c052 | 3123 | first_trb = false; |
50f7b52a AX |
3124 | if (start_cycle == 0) |
3125 | field |= 0x1; | |
3126 | } else | |
8a96c052 SS |
3127 | field |= ep_ring->cycle_state; |
3128 | ||
3129 | /* Chain all the TRBs together; clear the chain bit in the last | |
3130 | * TRB to indicate it's the last TRB in the chain. | |
3131 | */ | |
4758dcd1 | 3132 | if (num_trbs > last_trb_num) { |
8a96c052 | 3133 | field |= TRB_CHAIN; |
4758dcd1 | 3134 | } else if (num_trbs == last_trb_num) { |
8a96c052 SS |
3135 | td->last_trb = ep_ring->enqueue; |
3136 | field |= TRB_IOC; | |
4758dcd1 RA |
3137 | } else if (zero_length_needed && num_trbs == 1) { |
3138 | trb_buff_len = 0; | |
3139 | urb_priv->td[1]->last_trb = ep_ring->enqueue; | |
3140 | field |= TRB_IOC; | |
8a96c052 | 3141 | } |
af8b9e63 SS |
3142 | |
3143 | /* Only set interrupt on short packet for IN endpoints */ | |
3144 | if (usb_urb_dir_in(urb)) | |
3145 | field |= TRB_ISP; | |
3146 | ||
8a96c052 | 3147 | if (TRB_MAX_BUFF_SIZE - |
a2490187 | 3148 | (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) { |
8a96c052 SS |
3149 | xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n"); |
3150 | xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n", | |
3151 | (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1), | |
3152 | (unsigned int) addr + trb_buff_len); | |
3153 | } | |
4da6e6f2 SS |
3154 | |
3155 | /* Set the TRB length, TD size, and interrupter fields. */ | |
3156 | if (xhci->hci_version < 0x100) { | |
3157 | remainder = xhci_td_remainder( | |
3158 | urb->transfer_buffer_length - | |
3159 | running_total); | |
3160 | } else { | |
3161 | remainder = xhci_v1_0_td_remainder(running_total, | |
4525c0a1 SS |
3162 | trb_buff_len, total_packet_count, urb, |
3163 | num_trbs - 1); | |
4da6e6f2 | 3164 | } |
f9dc68fe | 3165 | length_field = TRB_LEN(trb_buff_len) | |
04dd950d | 3166 | remainder | |
f9dc68fe | 3167 | TRB_INTR_TARGET(0); |
4da6e6f2 | 3168 | |
6cc30d85 SS |
3169 | if (num_trbs > 1) |
3170 | more_trbs_coming = true; | |
3171 | else | |
3172 | more_trbs_coming = false; | |
3b72fca0 | 3173 | queue_trb(xhci, ep_ring, more_trbs_coming, |
8e595a5d SS |
3174 | lower_32_bits(addr), |
3175 | upper_32_bits(addr), | |
f9dc68fe | 3176 | length_field, |
af8b9e63 | 3177 | field | TRB_TYPE(TRB_NORMAL)); |
8a96c052 SS |
3178 | --num_trbs; |
3179 | running_total += trb_buff_len; | |
3180 | ||
3181 | /* Calculate length for next transfer -- | |
3182 | * Are we done queueing all the TRBs for this sg entry? | |
3183 | */ | |
3184 | this_sg_len -= trb_buff_len; | |
3185 | if (this_sg_len == 0) { | |
3186 | --num_sgs; | |
3187 | if (num_sgs == 0) | |
3188 | break; | |
3189 | sg = sg_next(sg); | |
3190 | addr = (u64) sg_dma_address(sg); | |
3191 | this_sg_len = sg_dma_len(sg); | |
3192 | } else { | |
3193 | addr += trb_buff_len; | |
3194 | } | |
3195 | ||
3196 | trb_buff_len = TRB_MAX_BUFF_SIZE - | |
a2490187 | 3197 | (addr & (TRB_MAX_BUFF_SIZE - 1)); |
8a96c052 SS |
3198 | trb_buff_len = min_t(int, trb_buff_len, this_sg_len); |
3199 | if (running_total + trb_buff_len > urb->transfer_buffer_length) | |
3200 | trb_buff_len = | |
3201 | urb->transfer_buffer_length - running_total; | |
4758dcd1 | 3202 | } while (num_trbs > 0); |
8a96c052 SS |
3203 | |
3204 | check_trb_math(urb, num_trbs, running_total); | |
e9df17eb | 3205 | giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, |
e1eab2e0 | 3206 | start_cycle, start_trb); |
8a96c052 SS |
3207 | return 0; |
3208 | } | |
3209 | ||
b10de142 | 3210 | /* This is very similar to what ehci-q.c qtd_fill() does */ |
23e3be11 | 3211 | int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, |
b10de142 SS |
3212 | struct urb *urb, int slot_id, unsigned int ep_index) |
3213 | { | |
3214 | struct xhci_ring *ep_ring; | |
8e51adcc | 3215 | struct urb_priv *urb_priv; |
b10de142 SS |
3216 | struct xhci_td *td; |
3217 | int num_trbs; | |
3218 | struct xhci_generic_trb *start_trb; | |
3219 | bool first_trb; | |
4758dcd1 | 3220 | int last_trb_num; |
6cc30d85 | 3221 | bool more_trbs_coming; |
4758dcd1 | 3222 | bool zero_length_needed; |
b10de142 | 3223 | int start_cycle; |
f9dc68fe | 3224 | u32 field, length_field; |
b10de142 SS |
3225 | |
3226 | int running_total, trb_buff_len, ret; | |
4da6e6f2 | 3227 | unsigned int total_packet_count; |
b10de142 SS |
3228 | u64 addr; |
3229 | ||
ff9c895f | 3230 | if (urb->num_sgs) |
8a96c052 SS |
3231 | return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index); |
3232 | ||
e9df17eb SS |
3233 | ep_ring = xhci_urb_to_transfer_ring(xhci, urb); |
3234 | if (!ep_ring) | |
3235 | return -EINVAL; | |
b10de142 SS |
3236 | |
3237 | num_trbs = 0; | |
3238 | /* How much data is (potentially) left before the 64KB boundary? */ | |
3239 | running_total = TRB_MAX_BUFF_SIZE - | |
a2490187 | 3240 | (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1)); |
5807795b | 3241 | running_total &= TRB_MAX_BUFF_SIZE - 1; |
b10de142 SS |
3242 | |
3243 | /* If there's some data on this 64KB chunk, or we have to send a | |
3244 | * zero-length transfer, we need at least one TRB | |
3245 | */ | |
3246 | if (running_total != 0 || urb->transfer_buffer_length == 0) | |
3247 | num_trbs++; | |
3248 | /* How many more 64KB chunks to transfer, how many more TRBs? */ | |
3249 | while (running_total < urb->transfer_buffer_length) { | |
3250 | num_trbs++; | |
3251 | running_total += TRB_MAX_BUFF_SIZE; | |
3252 | } | |
b10de142 | 3253 | |
e9df17eb SS |
3254 | ret = prepare_transfer(xhci, xhci->devs[slot_id], |
3255 | ep_index, urb->stream_id, | |
3b72fca0 | 3256 | num_trbs, urb, 0, mem_flags); |
b10de142 SS |
3257 | if (ret < 0) |
3258 | return ret; | |
3259 | ||
8e51adcc | 3260 | urb_priv = urb->hcpriv; |
4758dcd1 RA |
3261 | |
3262 | /* Deal with URB_ZERO_PACKET - need one more td/trb */ | |
3263 | zero_length_needed = urb->transfer_flags & URB_ZERO_PACKET && | |
3264 | urb_priv->length == 2; | |
3265 | if (zero_length_needed) { | |
3266 | num_trbs++; | |
3267 | xhci_dbg(xhci, "Creating zero length td.\n"); | |
3268 | ret = prepare_transfer(xhci, xhci->devs[slot_id], | |
3269 | ep_index, urb->stream_id, | |
3270 | 1, urb, 1, mem_flags); | |
3271 | if (ret < 0) | |
3272 | return ret; | |
3273 | } | |
3274 | ||
8e51adcc AX |
3275 | td = urb_priv->td[0]; |
3276 | ||
b10de142 SS |
3277 | /* |
3278 | * Don't give the first TRB to the hardware (by toggling the cycle bit) | |
3279 | * until we've finished creating all the other TRBs. The ring's cycle | |
3280 | * state may change as we enqueue the other TRBs, so save it too. | |
3281 | */ | |
3282 | start_trb = &ep_ring->enqueue->generic; | |
3283 | start_cycle = ep_ring->cycle_state; | |
3284 | ||
3285 | running_total = 0; | |
4525c0a1 | 3286 | total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length, |
29cc8897 | 3287 | usb_endpoint_maxp(&urb->ep->desc)); |
b10de142 SS |
3288 | /* How much data is in the first TRB? */ |
3289 | addr = (u64) urb->transfer_dma; | |
3290 | trb_buff_len = TRB_MAX_BUFF_SIZE - | |
a2490187 PZ |
3291 | (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1)); |
3292 | if (trb_buff_len > urb->transfer_buffer_length) | |
b10de142 SS |
3293 | trb_buff_len = urb->transfer_buffer_length; |
3294 | ||
3295 | first_trb = true; | |
4758dcd1 | 3296 | last_trb_num = zero_length_needed ? 2 : 1; |
b10de142 SS |
3297 | /* Queue the first TRB, even if it's zero-length */ |
3298 | do { | |
04dd950d | 3299 | u32 remainder = 0; |
b10de142 SS |
3300 | field = 0; |
3301 | ||
3302 | /* Don't change the cycle bit of the first TRB until later */ | |
50f7b52a | 3303 | if (first_trb) { |
b10de142 | 3304 | first_trb = false; |
50f7b52a AX |
3305 | if (start_cycle == 0) |
3306 | field |= 0x1; | |
3307 | } else | |
b10de142 SS |
3308 | field |= ep_ring->cycle_state; |
3309 | ||
3310 | /* Chain all the TRBs together; clear the chain bit in the last | |
3311 | * TRB to indicate it's the last TRB in the chain. | |
3312 | */ | |
4758dcd1 | 3313 | if (num_trbs > last_trb_num) { |
b10de142 | 3314 | field |= TRB_CHAIN; |
4758dcd1 | 3315 | } else if (num_trbs == last_trb_num) { |
b10de142 SS |
3316 | td->last_trb = ep_ring->enqueue; |
3317 | field |= TRB_IOC; | |
4758dcd1 RA |
3318 | } else if (zero_length_needed && num_trbs == 1) { |
3319 | trb_buff_len = 0; | |
3320 | urb_priv->td[1]->last_trb = ep_ring->enqueue; | |
3321 | field |= TRB_IOC; | |
b10de142 | 3322 | } |
af8b9e63 SS |
3323 | |
3324 | /* Only set interrupt on short packet for IN endpoints */ | |
3325 | if (usb_urb_dir_in(urb)) | |
3326 | field |= TRB_ISP; | |
3327 | ||
4da6e6f2 SS |
3328 | /* Set the TRB length, TD size, and interrupter fields. */ |
3329 | if (xhci->hci_version < 0x100) { | |
3330 | remainder = xhci_td_remainder( | |
3331 | urb->transfer_buffer_length - | |
3332 | running_total); | |
3333 | } else { | |
3334 | remainder = xhci_v1_0_td_remainder(running_total, | |
4525c0a1 SS |
3335 | trb_buff_len, total_packet_count, urb, |
3336 | num_trbs - 1); | |
4da6e6f2 | 3337 | } |
f9dc68fe | 3338 | length_field = TRB_LEN(trb_buff_len) | |
04dd950d | 3339 | remainder | |
f9dc68fe | 3340 | TRB_INTR_TARGET(0); |
4da6e6f2 | 3341 | |
6cc30d85 SS |
3342 | if (num_trbs > 1) |
3343 | more_trbs_coming = true; | |
3344 | else | |
3345 | more_trbs_coming = false; | |
3b72fca0 | 3346 | queue_trb(xhci, ep_ring, more_trbs_coming, |
8e595a5d SS |
3347 | lower_32_bits(addr), |
3348 | upper_32_bits(addr), | |
f9dc68fe | 3349 | length_field, |
af8b9e63 | 3350 | field | TRB_TYPE(TRB_NORMAL)); |
b10de142 SS |
3351 | --num_trbs; |
3352 | running_total += trb_buff_len; | |
3353 | ||
3354 | /* Calculate length for next transfer */ | |
3355 | addr += trb_buff_len; | |
3356 | trb_buff_len = urb->transfer_buffer_length - running_total; | |
3357 | if (trb_buff_len > TRB_MAX_BUFF_SIZE) | |
3358 | trb_buff_len = TRB_MAX_BUFF_SIZE; | |
4758dcd1 | 3359 | } while (num_trbs > 0); |
b10de142 | 3360 | |
8a96c052 | 3361 | check_trb_math(urb, num_trbs, running_total); |
e9df17eb | 3362 | giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, |
e1eab2e0 | 3363 | start_cycle, start_trb); |
b10de142 SS |
3364 | return 0; |
3365 | } | |
3366 | ||
d0e96f5a | 3367 | /* Caller must have locked xhci->lock */ |
23e3be11 | 3368 | int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, |
d0e96f5a SS |
3369 | struct urb *urb, int slot_id, unsigned int ep_index) |
3370 | { | |
3371 | struct xhci_ring *ep_ring; | |
3372 | int num_trbs; | |
3373 | int ret; | |
3374 | struct usb_ctrlrequest *setup; | |
3375 | struct xhci_generic_trb *start_trb; | |
3376 | int start_cycle; | |
f9dc68fe | 3377 | u32 field, length_field; |
8e51adcc | 3378 | struct urb_priv *urb_priv; |
d0e96f5a SS |
3379 | struct xhci_td *td; |
3380 | ||
e9df17eb SS |
3381 | ep_ring = xhci_urb_to_transfer_ring(xhci, urb); |
3382 | if (!ep_ring) | |
3383 | return -EINVAL; | |
d0e96f5a SS |
3384 | |
3385 | /* | |
3386 | * Need to copy setup packet into setup TRB, so we can't use the setup | |
3387 | * DMA address. | |
3388 | */ | |
3389 | if (!urb->setup_packet) | |
3390 | return -EINVAL; | |
3391 | ||
d0e96f5a SS |
3392 | /* 1 TRB for setup, 1 for status */ |
3393 | num_trbs = 2; | |
3394 | /* | |
3395 | * Don't need to check if we need additional event data and normal TRBs, | |
3396 | * since data in control transfers will never get bigger than 16MB | |
3397 | * XXX: can we get a buffer that crosses 64KB boundaries? | |
3398 | */ | |
3399 | if (urb->transfer_buffer_length > 0) | |
3400 | num_trbs++; | |
e9df17eb SS |
3401 | ret = prepare_transfer(xhci, xhci->devs[slot_id], |
3402 | ep_index, urb->stream_id, | |
3b72fca0 | 3403 | num_trbs, urb, 0, mem_flags); |
d0e96f5a SS |
3404 | if (ret < 0) |
3405 | return ret; | |
3406 | ||
8e51adcc AX |
3407 | urb_priv = urb->hcpriv; |
3408 | td = urb_priv->td[0]; | |
3409 | ||
d0e96f5a SS |
3410 | /* |
3411 | * Don't give the first TRB to the hardware (by toggling the cycle bit) | |
3412 | * until we've finished creating all the other TRBs. The ring's cycle | |
3413 | * state may change as we enqueue the other TRBs, so save it too. | |
3414 | */ | |
3415 | start_trb = &ep_ring->enqueue->generic; | |
3416 | start_cycle = ep_ring->cycle_state; | |
3417 | ||
3418 | /* Queue setup TRB - see section 6.4.1.2.1 */ | |
3419 | /* FIXME better way to translate setup_packet into two u32 fields? */ | |
3420 | setup = (struct usb_ctrlrequest *) urb->setup_packet; | |
50f7b52a AX |
3421 | field = 0; |
3422 | field |= TRB_IDT | TRB_TYPE(TRB_SETUP); | |
3423 | if (start_cycle == 0) | |
3424 | field |= 0x1; | |
b83cdc8f AX |
3425 | |
3426 | /* xHCI 1.0 6.4.1.2.1: Transfer Type field */ | |
3427 | if (xhci->hci_version == 0x100) { | |
3428 | if (urb->transfer_buffer_length > 0) { | |
3429 | if (setup->bRequestType & USB_DIR_IN) | |
3430 | field |= TRB_TX_TYPE(TRB_DATA_IN); | |
3431 | else | |
3432 | field |= TRB_TX_TYPE(TRB_DATA_OUT); | |
3433 | } | |
3434 | } | |
3435 | ||
3b72fca0 | 3436 | queue_trb(xhci, ep_ring, true, |
28ccd296 ME |
3437 | setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16, |
3438 | le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16, | |
3439 | TRB_LEN(8) | TRB_INTR_TARGET(0), | |
3440 | /* Immediate data in pointer */ | |
3441 | field); | |
d0e96f5a SS |
3442 | |
3443 | /* If there's data, queue data TRBs */ | |
af8b9e63 SS |
3444 | /* Only set interrupt on short packet for IN endpoints */ |
3445 | if (usb_urb_dir_in(urb)) | |
3446 | field = TRB_ISP | TRB_TYPE(TRB_DATA); | |
3447 | else | |
3448 | field = TRB_TYPE(TRB_DATA); | |
3449 | ||
f9dc68fe | 3450 | length_field = TRB_LEN(urb->transfer_buffer_length) | |
04dd950d | 3451 | xhci_td_remainder(urb->transfer_buffer_length) | |
f9dc68fe | 3452 | TRB_INTR_TARGET(0); |
d0e96f5a SS |
3453 | if (urb->transfer_buffer_length > 0) { |
3454 | if (setup->bRequestType & USB_DIR_IN) | |
3455 | field |= TRB_DIR_IN; | |
3b72fca0 | 3456 | queue_trb(xhci, ep_ring, true, |
d0e96f5a SS |
3457 | lower_32_bits(urb->transfer_dma), |
3458 | upper_32_bits(urb->transfer_dma), | |
f9dc68fe | 3459 | length_field, |
af8b9e63 | 3460 | field | ep_ring->cycle_state); |
d0e96f5a SS |
3461 | } |
3462 | ||
3463 | /* Save the DMA address of the last TRB in the TD */ | |
3464 | td->last_trb = ep_ring->enqueue; | |
3465 | ||
3466 | /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */ | |
3467 | /* If the device sent data, the status stage is an OUT transfer */ | |
3468 | if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN) | |
3469 | field = 0; | |
3470 | else | |
3471 | field = TRB_DIR_IN; | |
3b72fca0 | 3472 | queue_trb(xhci, ep_ring, false, |
d0e96f5a SS |
3473 | 0, |
3474 | 0, | |
3475 | TRB_INTR_TARGET(0), | |
3476 | /* Event on completion */ | |
3477 | field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state); | |
3478 | ||
e9df17eb | 3479 | giveback_first_trb(xhci, slot_id, ep_index, 0, |
e1eab2e0 | 3480 | start_cycle, start_trb); |
d0e96f5a SS |
3481 | return 0; |
3482 | } | |
3483 | ||
04e51901 AX |
3484 | static int count_isoc_trbs_needed(struct xhci_hcd *xhci, |
3485 | struct urb *urb, int i) | |
3486 | { | |
3487 | int num_trbs = 0; | |
48df4a6f | 3488 | u64 addr, td_len; |
04e51901 AX |
3489 | |
3490 | addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset); | |
3491 | td_len = urb->iso_frame_desc[i].length; | |
3492 | ||
48df4a6f SS |
3493 | num_trbs = DIV_ROUND_UP(td_len + (addr & (TRB_MAX_BUFF_SIZE - 1)), |
3494 | TRB_MAX_BUFF_SIZE); | |
3495 | if (num_trbs == 0) | |
04e51901 | 3496 | num_trbs++; |
04e51901 AX |
3497 | |
3498 | return num_trbs; | |
3499 | } | |
3500 | ||
5cd43e33 SS |
3501 | /* |
3502 | * The transfer burst count field of the isochronous TRB defines the number of | |
3503 | * bursts that are required to move all packets in this TD. Only SuperSpeed | |
3504 | * devices can burst up to bMaxBurst number of packets per service interval. | |
3505 | * This field is zero based, meaning a value of zero in the field means one | |
3506 | * burst. Basically, for everything but SuperSpeed devices, this field will be | |
3507 | * zero. Only xHCI 1.0 host controllers support this field. | |
3508 | */ | |
3509 | static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci, | |
3510 | struct usb_device *udev, | |
3511 | struct urb *urb, unsigned int total_packet_count) | |
3512 | { | |
3513 | unsigned int max_burst; | |
3514 | ||
3515 | if (xhci->hci_version < 0x100 || udev->speed != USB_SPEED_SUPER) | |
3516 | return 0; | |
3517 | ||
3518 | max_burst = urb->ep->ss_ep_comp.bMaxBurst; | |
3213b151 | 3519 | return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1; |
5cd43e33 SS |
3520 | } |
3521 | ||
b61d378f SS |
3522 | /* |
3523 | * Returns the number of packets in the last "burst" of packets. This field is | |
3524 | * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so | |
3525 | * the last burst packet count is equal to the total number of packets in the | |
3526 | * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst | |
3527 | * must contain (bMaxBurst + 1) number of packets, but the last burst can | |
3528 | * contain 1 to (bMaxBurst + 1) packets. | |
3529 | */ | |
3530 | static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci, | |
3531 | struct usb_device *udev, | |
3532 | struct urb *urb, unsigned int total_packet_count) | |
3533 | { | |
3534 | unsigned int max_burst; | |
3535 | unsigned int residue; | |
3536 | ||
3537 | if (xhci->hci_version < 0x100) | |
3538 | return 0; | |
3539 | ||
3540 | switch (udev->speed) { | |
3541 | case USB_SPEED_SUPER: | |
3542 | /* bMaxBurst is zero based: 0 means 1 packet per burst */ | |
3543 | max_burst = urb->ep->ss_ep_comp.bMaxBurst; | |
3544 | residue = total_packet_count % (max_burst + 1); | |
3545 | /* If residue is zero, the last burst contains (max_burst + 1) | |
3546 | * number of packets, but the TLBPC field is zero-based. | |
3547 | */ | |
3548 | if (residue == 0) | |
3549 | return max_burst; | |
3550 | return residue - 1; | |
3551 | default: | |
3552 | if (total_packet_count == 0) | |
3553 | return 0; | |
3554 | return total_packet_count - 1; | |
3555 | } | |
3556 | } | |
3557 | ||
04e51901 AX |
3558 | /* This is for isoc transfer */ |
3559 | static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |
3560 | struct urb *urb, int slot_id, unsigned int ep_index) | |
3561 | { | |
3562 | struct xhci_ring *ep_ring; | |
3563 | struct urb_priv *urb_priv; | |
3564 | struct xhci_td *td; | |
3565 | int num_tds, trbs_per_td; | |
3566 | struct xhci_generic_trb *start_trb; | |
3567 | bool first_trb; | |
3568 | int start_cycle; | |
3569 | u32 field, length_field; | |
3570 | int running_total, trb_buff_len, td_len, td_remain_len, ret; | |
3571 | u64 start_addr, addr; | |
3572 | int i, j; | |
47cbf692 | 3573 | bool more_trbs_coming; |
04e51901 AX |
3574 | |
3575 | ep_ring = xhci->devs[slot_id]->eps[ep_index].ring; | |
3576 | ||
3577 | num_tds = urb->number_of_packets; | |
3578 | if (num_tds < 1) { | |
3579 | xhci_dbg(xhci, "Isoc URB with zero packets?\n"); | |
3580 | return -EINVAL; | |
3581 | } | |
3582 | ||
04e51901 AX |
3583 | start_addr = (u64) urb->transfer_dma; |
3584 | start_trb = &ep_ring->enqueue->generic; | |
3585 | start_cycle = ep_ring->cycle_state; | |
3586 | ||
522989a2 | 3587 | urb_priv = urb->hcpriv; |
04e51901 AX |
3588 | /* Queue the first TRB, even if it's zero-length */ |
3589 | for (i = 0; i < num_tds; i++) { | |
4da6e6f2 | 3590 | unsigned int total_packet_count; |
5cd43e33 | 3591 | unsigned int burst_count; |
b61d378f | 3592 | unsigned int residue; |
04e51901 | 3593 | |
4da6e6f2 | 3594 | first_trb = true; |
04e51901 AX |
3595 | running_total = 0; |
3596 | addr = start_addr + urb->iso_frame_desc[i].offset; | |
3597 | td_len = urb->iso_frame_desc[i].length; | |
3598 | td_remain_len = td_len; | |
4525c0a1 | 3599 | total_packet_count = DIV_ROUND_UP(td_len, |
f18f8ed2 SS |
3600 | GET_MAX_PACKET( |
3601 | usb_endpoint_maxp(&urb->ep->desc))); | |
48df4a6f SS |
3602 | /* A zero-length transfer still involves at least one packet. */ |
3603 | if (total_packet_count == 0) | |
3604 | total_packet_count++; | |
5cd43e33 SS |
3605 | burst_count = xhci_get_burst_count(xhci, urb->dev, urb, |
3606 | total_packet_count); | |
b61d378f SS |
3607 | residue = xhci_get_last_burst_packet_count(xhci, |
3608 | urb->dev, urb, total_packet_count); | |
04e51901 AX |
3609 | |
3610 | trbs_per_td = count_isoc_trbs_needed(xhci, urb, i); | |
3611 | ||
3612 | ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index, | |
3b72fca0 | 3613 | urb->stream_id, trbs_per_td, urb, i, mem_flags); |
522989a2 SS |
3614 | if (ret < 0) { |
3615 | if (i == 0) | |
3616 | return ret; | |
3617 | goto cleanup; | |
3618 | } | |
04e51901 | 3619 | |
04e51901 | 3620 | td = urb_priv->td[i]; |
04e51901 AX |
3621 | for (j = 0; j < trbs_per_td; j++) { |
3622 | u32 remainder = 0; | |
760973d2 | 3623 | field = 0; |
04e51901 AX |
3624 | |
3625 | if (first_trb) { | |
760973d2 SS |
3626 | field = TRB_TBC(burst_count) | |
3627 | TRB_TLBPC(residue); | |
04e51901 AX |
3628 | /* Queue the isoc TRB */ |
3629 | field |= TRB_TYPE(TRB_ISOC); | |
3630 | /* Assume URB_ISO_ASAP is set */ | |
3631 | field |= TRB_SIA; | |
50f7b52a AX |
3632 | if (i == 0) { |
3633 | if (start_cycle == 0) | |
3634 | field |= 0x1; | |
3635 | } else | |
04e51901 AX |
3636 | field |= ep_ring->cycle_state; |
3637 | first_trb = false; | |
3638 | } else { | |
3639 | /* Queue other normal TRBs */ | |
3640 | field |= TRB_TYPE(TRB_NORMAL); | |
3641 | field |= ep_ring->cycle_state; | |
3642 | } | |
3643 | ||
af8b9e63 SS |
3644 | /* Only set interrupt on short packet for IN EPs */ |
3645 | if (usb_urb_dir_in(urb)) | |
3646 | field |= TRB_ISP; | |
3647 | ||
04e51901 AX |
3648 | /* Chain all the TRBs together; clear the chain bit in |
3649 | * the last TRB to indicate it's the last TRB in the | |
3650 | * chain. | |
3651 | */ | |
3652 | if (j < trbs_per_td - 1) { | |
3653 | field |= TRB_CHAIN; | |
47cbf692 | 3654 | more_trbs_coming = true; |
04e51901 AX |
3655 | } else { |
3656 | td->last_trb = ep_ring->enqueue; | |
3657 | field |= TRB_IOC; | |
80fab3b2 SS |
3658 | if (xhci->hci_version == 0x100 && |
3659 | !(xhci->quirks & | |
3660 | XHCI_AVOID_BEI)) { | |
ad106f29 AX |
3661 | /* Set BEI bit except for the last td */ |
3662 | if (i < num_tds - 1) | |
3663 | field |= TRB_BEI; | |
3664 | } | |
47cbf692 | 3665 | more_trbs_coming = false; |
04e51901 AX |
3666 | } |
3667 | ||
3668 | /* Calculate TRB length */ | |
3669 | trb_buff_len = TRB_MAX_BUFF_SIZE - | |
3670 | (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1)); | |
3671 | if (trb_buff_len > td_remain_len) | |
3672 | trb_buff_len = td_remain_len; | |
3673 | ||
4da6e6f2 SS |
3674 | /* Set the TRB length, TD size, & interrupter fields. */ |
3675 | if (xhci->hci_version < 0x100) { | |
3676 | remainder = xhci_td_remainder( | |
3677 | td_len - running_total); | |
3678 | } else { | |
3679 | remainder = xhci_v1_0_td_remainder( | |
3680 | running_total, trb_buff_len, | |
4525c0a1 SS |
3681 | total_packet_count, urb, |
3682 | (trbs_per_td - j - 1)); | |
4da6e6f2 | 3683 | } |
04e51901 AX |
3684 | length_field = TRB_LEN(trb_buff_len) | |
3685 | remainder | | |
3686 | TRB_INTR_TARGET(0); | |
4da6e6f2 | 3687 | |
3b72fca0 | 3688 | queue_trb(xhci, ep_ring, more_trbs_coming, |
04e51901 AX |
3689 | lower_32_bits(addr), |
3690 | upper_32_bits(addr), | |
3691 | length_field, | |
af8b9e63 | 3692 | field); |
04e51901 AX |
3693 | running_total += trb_buff_len; |
3694 | ||
3695 | addr += trb_buff_len; | |
3696 | td_remain_len -= trb_buff_len; | |
3697 | } | |
3698 | ||
3699 | /* Check TD length */ | |
3700 | if (running_total != td_len) { | |
3701 | xhci_err(xhci, "ISOC TD length unmatch\n"); | |
cf840551 AX |
3702 | ret = -EINVAL; |
3703 | goto cleanup; | |
04e51901 AX |
3704 | } |
3705 | } | |
3706 | ||
c41136b0 AX |
3707 | if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) { |
3708 | if (xhci->quirks & XHCI_AMD_PLL_FIX) | |
3709 | usb_amd_quirk_pll_disable(); | |
3710 | } | |
3711 | xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++; | |
3712 | ||
e1eab2e0 AX |
3713 | giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, |
3714 | start_cycle, start_trb); | |
04e51901 | 3715 | return 0; |
522989a2 SS |
3716 | cleanup: |
3717 | /* Clean up a partially enqueued isoc transfer. */ | |
3718 | ||
3719 | for (i--; i >= 0; i--) | |
585df1d9 | 3720 | list_del_init(&urb_priv->td[i]->td_list); |
522989a2 SS |
3721 | |
3722 | /* Use the first TD as a temporary variable to turn the TDs we've queued | |
3723 | * into No-ops with a software-owned cycle bit. That way the hardware | |
3724 | * won't accidentally start executing bogus TDs when we partially | |
3725 | * overwrite them. td->first_trb and td->start_seg are already set. | |
3726 | */ | |
3727 | urb_priv->td[0]->last_trb = ep_ring->enqueue; | |
3728 | /* Every TRB except the first & last will have its cycle bit flipped. */ | |
3729 | td_to_noop(xhci, ep_ring, urb_priv->td[0], true); | |
3730 | ||
3731 | /* Reset the ring enqueue back to the first TRB and its cycle bit. */ | |
3732 | ep_ring->enqueue = urb_priv->td[0]->first_trb; | |
3733 | ep_ring->enq_seg = urb_priv->td[0]->start_seg; | |
3734 | ep_ring->cycle_state = start_cycle; | |
b008df60 | 3735 | ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp; |
522989a2 SS |
3736 | usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb); |
3737 | return ret; | |
04e51901 AX |
3738 | } |
3739 | ||
3740 | /* | |
3741 | * Check transfer ring to guarantee there is enough room for the urb. | |
3742 | * Update ISO URB start_frame and interval. | |
3743 | * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to | |
3744 | * update the urb->start_frame by now. | |
3745 | * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input. | |
3746 | */ | |
3747 | int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags, | |
3748 | struct urb *urb, int slot_id, unsigned int ep_index) | |
3749 | { | |
3750 | struct xhci_virt_device *xdev; | |
3751 | struct xhci_ring *ep_ring; | |
3752 | struct xhci_ep_ctx *ep_ctx; | |
3753 | int start_frame; | |
3754 | int xhci_interval; | |
3755 | int ep_interval; | |
3756 | int num_tds, num_trbs, i; | |
3757 | int ret; | |
3758 | ||
3759 | xdev = xhci->devs[slot_id]; | |
3760 | ep_ring = xdev->eps[ep_index].ring; | |
3761 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); | |
3762 | ||
3763 | num_trbs = 0; | |
3764 | num_tds = urb->number_of_packets; | |
3765 | for (i = 0; i < num_tds; i++) | |
3766 | num_trbs += count_isoc_trbs_needed(xhci, urb, i); | |
3767 | ||
3768 | /* Check the ring to guarantee there is enough room for the whole urb. | |
3769 | * Do not insert any td of the urb to the ring if the check failed. | |
3770 | */ | |
28ccd296 | 3771 | ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK, |
3b72fca0 | 3772 | num_trbs, mem_flags); |
04e51901 AX |
3773 | if (ret) |
3774 | return ret; | |
3775 | ||
b0ba9720 | 3776 | start_frame = readl(&xhci->run_regs->microframe_index); |
04e51901 AX |
3777 | start_frame &= 0x3fff; |
3778 | ||
3779 | urb->start_frame = start_frame; | |
3780 | if (urb->dev->speed == USB_SPEED_LOW || | |
3781 | urb->dev->speed == USB_SPEED_FULL) | |
3782 | urb->start_frame >>= 3; | |
3783 | ||
28ccd296 | 3784 | xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info)); |
04e51901 AX |
3785 | ep_interval = urb->interval; |
3786 | /* Convert to microframes */ | |
3787 | if (urb->dev->speed == USB_SPEED_LOW || | |
3788 | urb->dev->speed == USB_SPEED_FULL) | |
3789 | ep_interval *= 8; | |
3790 | /* FIXME change this to a warning and a suggestion to use the new API | |
3791 | * to set the polling interval (once the API is added). | |
3792 | */ | |
3793 | if (xhci_interval != ep_interval) { | |
0730d52a DK |
3794 | dev_dbg_ratelimited(&urb->dev->dev, |
3795 | "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n", | |
3796 | ep_interval, ep_interval == 1 ? "" : "s", | |
3797 | xhci_interval, xhci_interval == 1 ? "" : "s"); | |
04e51901 AX |
3798 | urb->interval = xhci_interval; |
3799 | /* Convert back to frames for LS/FS devices */ | |
3800 | if (urb->dev->speed == USB_SPEED_LOW || | |
3801 | urb->dev->speed == USB_SPEED_FULL) | |
3802 | urb->interval /= 8; | |
3803 | } | |
b008df60 AX |
3804 | ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free; |
3805 | ||
3fc8206d | 3806 | return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index); |
04e51901 AX |
3807 | } |
3808 | ||
d0e96f5a SS |
3809 | /**** Command Ring Operations ****/ |
3810 | ||
913a8a34 SS |
3811 | /* Generic function for queueing a command TRB on the command ring. |
3812 | * Check to make sure there's room on the command ring for one command TRB. | |
3813 | * Also check that there's room reserved for commands that must not fail. | |
3814 | * If this is a command that must not fail, meaning command_must_succeed = TRUE, | |
3815 | * then only check for the number of reserved spots. | |
3816 | * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB | |
3817 | * because the command event handler may want to resubmit a failed command. | |
3818 | */ | |
ddba5cd0 MN |
3819 | static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd, |
3820 | u32 field1, u32 field2, | |
3821 | u32 field3, u32 field4, bool command_must_succeed) | |
7f84eef0 | 3822 | { |
913a8a34 | 3823 | int reserved_trbs = xhci->cmd_ring_reserved_trbs; |
d1dc908a | 3824 | int ret; |
ad6b1d91 RQ |
3825 | |
3826 | if (xhci->xhc_state) { | |
3827 | xhci_dbg(xhci, "xHCI dying or halted, can't queue_command\n"); | |
c9aa1a2d | 3828 | return -ESHUTDOWN; |
ad6b1d91 | 3829 | } |
d1dc908a | 3830 | |
913a8a34 SS |
3831 | if (!command_must_succeed) |
3832 | reserved_trbs++; | |
3833 | ||
d1dc908a | 3834 | ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING, |
3b72fca0 | 3835 | reserved_trbs, GFP_ATOMIC); |
d1dc908a SS |
3836 | if (ret < 0) { |
3837 | xhci_err(xhci, "ERR: No room for command on command ring\n"); | |
913a8a34 SS |
3838 | if (command_must_succeed) |
3839 | xhci_err(xhci, "ERR: Reserved TRB counting for " | |
3840 | "unfailable commands failed.\n"); | |
d1dc908a | 3841 | return ret; |
7f84eef0 | 3842 | } |
c9aa1a2d MN |
3843 | |
3844 | cmd->command_trb = xhci->cmd_ring->enqueue; | |
3845 | list_add_tail(&cmd->cmd_list, &xhci->cmd_list); | |
ddba5cd0 | 3846 | |
c311e391 MN |
3847 | /* if there are no other commands queued we start the timeout timer */ |
3848 | if (xhci->cmd_list.next == &cmd->cmd_list && | |
3849 | !timer_pending(&xhci->cmd_timer)) { | |
3850 | xhci->current_cmd = cmd; | |
3851 | mod_timer(&xhci->cmd_timer, jiffies + XHCI_CMD_DEFAULT_TIMEOUT); | |
3852 | } | |
3853 | ||
3b72fca0 AX |
3854 | queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3, |
3855 | field4 | xhci->cmd_ring->cycle_state); | |
7f84eef0 SS |
3856 | return 0; |
3857 | } | |
3858 | ||
3ffbba95 | 3859 | /* Queue a slot enable or disable request on the command ring */ |
ddba5cd0 MN |
3860 | int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd, |
3861 | u32 trb_type, u32 slot_id) | |
3ffbba95 | 3862 | { |
ddba5cd0 | 3863 | return queue_command(xhci, cmd, 0, 0, 0, |
913a8a34 | 3864 | TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false); |
3ffbba95 SS |
3865 | } |
3866 | ||
3867 | /* Queue an address device command TRB */ | |
ddba5cd0 MN |
3868 | int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd, |
3869 | dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev setup) | |
3ffbba95 | 3870 | { |
ddba5cd0 | 3871 | return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr), |
8e595a5d | 3872 | upper_32_bits(in_ctx_ptr), 0, |
48fc7dbd DW |
3873 | TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id) |
3874 | | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false); | |
2a8f82c4 SS |
3875 | } |
3876 | ||
ddba5cd0 | 3877 | int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd, |
0238634d SS |
3878 | u32 field1, u32 field2, u32 field3, u32 field4) |
3879 | { | |
ddba5cd0 | 3880 | return queue_command(xhci, cmd, field1, field2, field3, field4, false); |
0238634d SS |
3881 | } |
3882 | ||
2a8f82c4 | 3883 | /* Queue a reset device command TRB */ |
ddba5cd0 MN |
3884 | int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd, |
3885 | u32 slot_id) | |
2a8f82c4 | 3886 | { |
ddba5cd0 | 3887 | return queue_command(xhci, cmd, 0, 0, 0, |
2a8f82c4 | 3888 | TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id), |
913a8a34 | 3889 | false); |
3ffbba95 | 3890 | } |
f94e0186 SS |
3891 | |
3892 | /* Queue a configure endpoint command TRB */ | |
ddba5cd0 MN |
3893 | int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, |
3894 | struct xhci_command *cmd, dma_addr_t in_ctx_ptr, | |
913a8a34 | 3895 | u32 slot_id, bool command_must_succeed) |
f94e0186 | 3896 | { |
ddba5cd0 | 3897 | return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr), |
8e595a5d | 3898 | upper_32_bits(in_ctx_ptr), 0, |
913a8a34 SS |
3899 | TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id), |
3900 | command_must_succeed); | |
f94e0186 | 3901 | } |
ae636747 | 3902 | |
f2217e8e | 3903 | /* Queue an evaluate context command TRB */ |
ddba5cd0 MN |
3904 | int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd, |
3905 | dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed) | |
f2217e8e | 3906 | { |
ddba5cd0 | 3907 | return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr), |
f2217e8e | 3908 | upper_32_bits(in_ctx_ptr), 0, |
913a8a34 | 3909 | TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id), |
4b266541 | 3910 | command_must_succeed); |
f2217e8e SS |
3911 | } |
3912 | ||
be88fe4f AX |
3913 | /* |
3914 | * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop | |
3915 | * activity on an endpoint that is about to be suspended. | |
3916 | */ | |
ddba5cd0 MN |
3917 | int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd, |
3918 | int slot_id, unsigned int ep_index, int suspend) | |
ae636747 SS |
3919 | { |
3920 | u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); | |
3921 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); | |
3922 | u32 type = TRB_TYPE(TRB_STOP_RING); | |
be88fe4f | 3923 | u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend); |
ae636747 | 3924 | |
ddba5cd0 | 3925 | return queue_command(xhci, cmd, 0, 0, 0, |
be88fe4f | 3926 | trb_slot_id | trb_ep_index | type | trb_suspend, false); |
ae636747 SS |
3927 | } |
3928 | ||
d3a43e66 HG |
3929 | /* Set Transfer Ring Dequeue Pointer command */ |
3930 | void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci, | |
3931 | unsigned int slot_id, unsigned int ep_index, | |
3932 | unsigned int stream_id, | |
3933 | struct xhci_dequeue_state *deq_state) | |
ae636747 SS |
3934 | { |
3935 | dma_addr_t addr; | |
3936 | u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); | |
3937 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); | |
e9df17eb | 3938 | u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id); |
95241dbd | 3939 | u32 trb_sct = 0; |
ae636747 | 3940 | u32 type = TRB_TYPE(TRB_SET_DEQ); |
bf161e85 | 3941 | struct xhci_virt_ep *ep; |
1e3452e3 HG |
3942 | struct xhci_command *cmd; |
3943 | int ret; | |
ae636747 | 3944 | |
d3a43e66 HG |
3945 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
3946 | "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), new deq ptr = %p (0x%llx dma), new cycle = %u", | |
3947 | deq_state->new_deq_seg, | |
3948 | (unsigned long long)deq_state->new_deq_seg->dma, | |
3949 | deq_state->new_deq_ptr, | |
3950 | (unsigned long long)xhci_trb_virt_to_dma( | |
3951 | deq_state->new_deq_seg, deq_state->new_deq_ptr), | |
3952 | deq_state->new_cycle_state); | |
3953 | ||
3954 | addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg, | |
3955 | deq_state->new_deq_ptr); | |
c92bcfa7 | 3956 | if (addr == 0) { |
ae636747 | 3957 | xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n"); |
700e2052 | 3958 | xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n", |
d3a43e66 HG |
3959 | deq_state->new_deq_seg, deq_state->new_deq_ptr); |
3960 | return; | |
c92bcfa7 | 3961 | } |
bf161e85 SS |
3962 | ep = &xhci->devs[slot_id]->eps[ep_index]; |
3963 | if ((ep->ep_state & SET_DEQ_PENDING)) { | |
3964 | xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n"); | |
3965 | xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n"); | |
d3a43e66 | 3966 | return; |
bf161e85 | 3967 | } |
1e3452e3 HG |
3968 | |
3969 | /* This function gets called from contexts where it cannot sleep */ | |
3970 | cmd = xhci_alloc_command(xhci, false, false, GFP_ATOMIC); | |
3971 | if (!cmd) { | |
3972 | xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr: ENOMEM\n"); | |
d3a43e66 | 3973 | return; |
1e3452e3 HG |
3974 | } |
3975 | ||
d3a43e66 HG |
3976 | ep->queued_deq_seg = deq_state->new_deq_seg; |
3977 | ep->queued_deq_ptr = deq_state->new_deq_ptr; | |
95241dbd HG |
3978 | if (stream_id) |
3979 | trb_sct = SCT_FOR_TRB(SCT_PRI_TR); | |
1e3452e3 | 3980 | ret = queue_command(xhci, cmd, |
d3a43e66 HG |
3981 | lower_32_bits(addr) | trb_sct | deq_state->new_cycle_state, |
3982 | upper_32_bits(addr), trb_stream_id, | |
3983 | trb_slot_id | trb_ep_index | type, false); | |
1e3452e3 HG |
3984 | if (ret < 0) { |
3985 | xhci_free_command(xhci, cmd); | |
d3a43e66 | 3986 | return; |
1e3452e3 HG |
3987 | } |
3988 | ||
d3a43e66 HG |
3989 | /* Stop the TD queueing code from ringing the doorbell until |
3990 | * this command completes. The HC won't set the dequeue pointer | |
3991 | * if the ring is running, and ringing the doorbell starts the | |
3992 | * ring running. | |
3993 | */ | |
3994 | ep->ep_state |= SET_DEQ_PENDING; | |
ae636747 | 3995 | } |
a1587d97 | 3996 | |
ddba5cd0 MN |
3997 | int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd, |
3998 | int slot_id, unsigned int ep_index) | |
a1587d97 SS |
3999 | { |
4000 | u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); | |
4001 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); | |
4002 | u32 type = TRB_TYPE(TRB_RESET_EP); | |
4003 | ||
ddba5cd0 MN |
4004 | return queue_command(xhci, cmd, 0, 0, 0, |
4005 | trb_slot_id | trb_ep_index | type, false); | |
a1587d97 | 4006 | } |