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Commit | Line | Data |
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7f84eef0 SS |
1 | /* |
2 | * xHCI host controller driver | |
3 | * | |
4 | * Copyright (C) 2008 Intel Corp. | |
5 | * | |
6 | * Author: Sarah Sharp | |
7 | * Some code borrowed from the Linux EHCI driver. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | * for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software Foundation, | |
20 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
23 | /* | |
24 | * Ring initialization rules: | |
25 | * 1. Each segment is initialized to zero, except for link TRBs. | |
26 | * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or | |
27 | * Consumer Cycle State (CCS), depending on ring function. | |
28 | * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment. | |
29 | * | |
30 | * Ring behavior rules: | |
31 | * 1. A ring is empty if enqueue == dequeue. This means there will always be at | |
32 | * least one free TRB in the ring. This is useful if you want to turn that | |
33 | * into a link TRB and expand the ring. | |
34 | * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a | |
35 | * link TRB, then load the pointer with the address in the link TRB. If the | |
36 | * link TRB had its toggle bit set, you may need to update the ring cycle | |
37 | * state (see cycle bit rules). You may have to do this multiple times | |
38 | * until you reach a non-link TRB. | |
39 | * 3. A ring is full if enqueue++ (for the definition of increment above) | |
40 | * equals the dequeue pointer. | |
41 | * | |
42 | * Cycle bit rules: | |
43 | * 1. When a consumer increments a dequeue pointer and encounters a toggle bit | |
44 | * in a link TRB, it must toggle the ring cycle state. | |
45 | * 2. When a producer increments an enqueue pointer and encounters a toggle bit | |
46 | * in a link TRB, it must toggle the ring cycle state. | |
47 | * | |
48 | * Producer rules: | |
49 | * 1. Check if ring is full before you enqueue. | |
50 | * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing. | |
51 | * Update enqueue pointer between each write (which may update the ring | |
52 | * cycle state). | |
53 | * 3. Notify consumer. If SW is producer, it rings the doorbell for command | |
54 | * and endpoint rings. If HC is the producer for the event ring, | |
55 | * and it generates an interrupt according to interrupt modulation rules. | |
56 | * | |
57 | * Consumer rules: | |
58 | * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state, | |
59 | * the TRB is owned by the consumer. | |
60 | * 2. Update dequeue pointer (which may update the ring cycle state) and | |
61 | * continue processing TRBs until you reach a TRB which is not owned by you. | |
62 | * 3. Notify the producer. SW is the consumer for the event ring, and it | |
63 | * updates event ring dequeue pointer. HC is the consumer for the command and | |
64 | * endpoint rings; it generates events on the event ring for these. | |
65 | */ | |
66 | ||
8a96c052 | 67 | #include <linux/scatterlist.h> |
5a0e3ad6 | 68 | #include <linux/slab.h> |
7f84eef0 | 69 | #include "xhci.h" |
3a7fa5be | 70 | #include "xhci-trace.h" |
7f84eef0 | 71 | |
be88fe4f AX |
72 | static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci, |
73 | struct xhci_virt_device *virt_dev, | |
74 | struct xhci_event_cmd *event); | |
75 | ||
7f84eef0 SS |
76 | /* |
77 | * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA | |
78 | * address of the TRB. | |
79 | */ | |
23e3be11 | 80 | dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, |
7f84eef0 SS |
81 | union xhci_trb *trb) |
82 | { | |
6071d836 | 83 | unsigned long segment_offset; |
7f84eef0 | 84 | |
6071d836 | 85 | if (!seg || !trb || trb < seg->trbs) |
7f84eef0 | 86 | return 0; |
6071d836 SS |
87 | /* offset in TRBs */ |
88 | segment_offset = trb - seg->trbs; | |
89 | if (segment_offset > TRBS_PER_SEGMENT) | |
7f84eef0 | 90 | return 0; |
6071d836 | 91 | return seg->dma + (segment_offset * sizeof(*trb)); |
7f84eef0 SS |
92 | } |
93 | ||
94 | /* Does this link TRB point to the first segment in a ring, | |
95 | * or was the previous TRB the last TRB on the last segment in the ERST? | |
96 | */ | |
575688e1 | 97 | static bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring, |
7f84eef0 SS |
98 | struct xhci_segment *seg, union xhci_trb *trb) |
99 | { | |
100 | if (ring == xhci->event_ring) | |
101 | return (trb == &seg->trbs[TRBS_PER_SEGMENT]) && | |
102 | (seg->next == xhci->event_ring->first_seg); | |
103 | else | |
28ccd296 | 104 | return le32_to_cpu(trb->link.control) & LINK_TOGGLE; |
7f84eef0 SS |
105 | } |
106 | ||
107 | /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring | |
108 | * segment? I.e. would the updated event TRB pointer step off the end of the | |
109 | * event seg? | |
110 | */ | |
575688e1 | 111 | static int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring, |
7f84eef0 SS |
112 | struct xhci_segment *seg, union xhci_trb *trb) |
113 | { | |
114 | if (ring == xhci->event_ring) | |
115 | return trb == &seg->trbs[TRBS_PER_SEGMENT]; | |
116 | else | |
f5960b69 | 117 | return TRB_TYPE_LINK_LE32(trb->link.control); |
7f84eef0 SS |
118 | } |
119 | ||
575688e1 | 120 | static int enqueue_is_link_trb(struct xhci_ring *ring) |
6c12db90 JY |
121 | { |
122 | struct xhci_link_trb *link = &ring->enqueue->link; | |
f5960b69 | 123 | return TRB_TYPE_LINK_LE32(link->control); |
6c12db90 JY |
124 | } |
125 | ||
ec7e43e2 MN |
126 | union xhci_trb *xhci_find_next_enqueue(struct xhci_ring *ring) |
127 | { | |
128 | /* Enqueue pointer can be left pointing to the link TRB, | |
129 | * we must handle that | |
130 | */ | |
131 | if (TRB_TYPE_LINK_LE32(ring->enqueue->link.control)) | |
132 | return ring->enq_seg->next->trbs; | |
133 | return ring->enqueue; | |
134 | } | |
135 | ||
ae636747 SS |
136 | /* Updates trb to point to the next TRB in the ring, and updates seg if the next |
137 | * TRB is in a new segment. This does not skip over link TRBs, and it does not | |
138 | * effect the ring dequeue or enqueue pointers. | |
139 | */ | |
140 | static void next_trb(struct xhci_hcd *xhci, | |
141 | struct xhci_ring *ring, | |
142 | struct xhci_segment **seg, | |
143 | union xhci_trb **trb) | |
144 | { | |
145 | if (last_trb(xhci, ring, *seg, *trb)) { | |
146 | *seg = (*seg)->next; | |
147 | *trb = ((*seg)->trbs); | |
148 | } else { | |
a1669b2c | 149 | (*trb)++; |
ae636747 SS |
150 | } |
151 | } | |
152 | ||
7f84eef0 SS |
153 | /* |
154 | * See Cycle bit rules. SW is the consumer for the event ring only. | |
155 | * Don't make a ring full of link TRBs. That would be dumb and this would loop. | |
156 | */ | |
3b72fca0 | 157 | static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring) |
7f84eef0 | 158 | { |
7f84eef0 | 159 | ring->deq_updates++; |
b008df60 | 160 | |
50d0206f SS |
161 | /* |
162 | * If this is not event ring, and the dequeue pointer | |
163 | * is not on a link TRB, there is one more usable TRB | |
164 | */ | |
b008df60 AX |
165 | if (ring->type != TYPE_EVENT && |
166 | !last_trb(xhci, ring, ring->deq_seg, ring->dequeue)) | |
167 | ring->num_trbs_free++; | |
b008df60 | 168 | |
50d0206f SS |
169 | do { |
170 | /* | |
171 | * Update the dequeue pointer further if that was a link TRB or | |
172 | * we're at the end of an event ring segment (which doesn't have | |
173 | * link TRBS) | |
174 | */ | |
175 | if (last_trb(xhci, ring, ring->deq_seg, ring->dequeue)) { | |
176 | if (ring->type == TYPE_EVENT && | |
177 | last_trb_on_last_seg(xhci, ring, | |
178 | ring->deq_seg, ring->dequeue)) { | |
4e341818 | 179 | ring->cycle_state ^= 1; |
50d0206f SS |
180 | } |
181 | ring->deq_seg = ring->deq_seg->next; | |
182 | ring->dequeue = ring->deq_seg->trbs; | |
183 | } else { | |
184 | ring->dequeue++; | |
7f84eef0 | 185 | } |
50d0206f | 186 | } while (last_trb(xhci, ring, ring->deq_seg, ring->dequeue)); |
7f84eef0 SS |
187 | } |
188 | ||
189 | /* | |
190 | * See Cycle bit rules. SW is the consumer for the event ring only. | |
191 | * Don't make a ring full of link TRBs. That would be dumb and this would loop. | |
192 | * | |
193 | * If we've just enqueued a TRB that is in the middle of a TD (meaning the | |
194 | * chain bit is set), then set the chain bit in all the following link TRBs. | |
195 | * If we've enqueued the last TRB in a TD, make sure the following link TRBs | |
196 | * have their chain bit cleared (so that each Link TRB is a separate TD). | |
197 | * | |
198 | * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit | |
b0567b3f SS |
199 | * set, but other sections talk about dealing with the chain bit set. This was |
200 | * fixed in the 0.96 specification errata, but we have to assume that all 0.95 | |
201 | * xHCI hardware can't handle the chain bit being cleared on a link TRB. | |
6cc30d85 SS |
202 | * |
203 | * @more_trbs_coming: Will you enqueue more TRBs before calling | |
204 | * prepare_transfer()? | |
7f84eef0 | 205 | */ |
6cc30d85 | 206 | static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring, |
3b72fca0 | 207 | bool more_trbs_coming) |
7f84eef0 SS |
208 | { |
209 | u32 chain; | |
210 | union xhci_trb *next; | |
211 | ||
28ccd296 | 212 | chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN; |
b008df60 AX |
213 | /* If this is not event ring, there is one less usable TRB */ |
214 | if (ring->type != TYPE_EVENT && | |
215 | !last_trb(xhci, ring, ring->enq_seg, ring->enqueue)) | |
216 | ring->num_trbs_free--; | |
7f84eef0 SS |
217 | next = ++(ring->enqueue); |
218 | ||
219 | ring->enq_updates++; | |
220 | /* Update the dequeue pointer further if that was a link TRB or we're at | |
221 | * the end of an event ring segment (which doesn't have link TRBS) | |
222 | */ | |
223 | while (last_trb(xhci, ring, ring->enq_seg, next)) { | |
3b72fca0 AX |
224 | if (ring->type != TYPE_EVENT) { |
225 | /* | |
226 | * If the caller doesn't plan on enqueueing more | |
227 | * TDs before ringing the doorbell, then we | |
228 | * don't want to give the link TRB to the | |
229 | * hardware just yet. We'll give the link TRB | |
230 | * back in prepare_ring() just before we enqueue | |
231 | * the TD at the top of the ring. | |
232 | */ | |
233 | if (!chain && !more_trbs_coming) | |
234 | break; | |
6cc30d85 | 235 | |
3b72fca0 AX |
236 | /* If we're not dealing with 0.95 hardware or |
237 | * isoc rings on AMD 0.96 host, | |
238 | * carry over the chain bit of the previous TRB | |
239 | * (which may mean the chain bit is cleared). | |
240 | */ | |
241 | if (!(ring->type == TYPE_ISOC && | |
242 | (xhci->quirks & XHCI_AMD_0x96_HOST)) | |
7e393a83 | 243 | && !xhci_link_trb_quirk(xhci)) { |
3b72fca0 AX |
244 | next->link.control &= |
245 | cpu_to_le32(~TRB_CHAIN); | |
246 | next->link.control |= | |
247 | cpu_to_le32(chain); | |
7f84eef0 | 248 | } |
3b72fca0 AX |
249 | /* Give this link TRB to the hardware */ |
250 | wmb(); | |
251 | next->link.control ^= cpu_to_le32(TRB_CYCLE); | |
252 | ||
7f84eef0 SS |
253 | /* Toggle the cycle bit after the last ring segment. */ |
254 | if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) { | |
255 | ring->cycle_state = (ring->cycle_state ? 0 : 1); | |
7f84eef0 SS |
256 | } |
257 | } | |
258 | ring->enq_seg = ring->enq_seg->next; | |
259 | ring->enqueue = ring->enq_seg->trbs; | |
260 | next = ring->enqueue; | |
261 | } | |
262 | } | |
263 | ||
264 | /* | |
085deb16 AX |
265 | * Check to see if there's room to enqueue num_trbs on the ring and make sure |
266 | * enqueue pointer will not advance into dequeue segment. See rules above. | |
7f84eef0 | 267 | */ |
b008df60 | 268 | static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring, |
7f84eef0 SS |
269 | unsigned int num_trbs) |
270 | { | |
085deb16 | 271 | int num_trbs_in_deq_seg; |
b008df60 | 272 | |
085deb16 AX |
273 | if (ring->num_trbs_free < num_trbs) |
274 | return 0; | |
275 | ||
276 | if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) { | |
277 | num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs; | |
278 | if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg) | |
279 | return 0; | |
280 | } | |
281 | ||
282 | return 1; | |
7f84eef0 SS |
283 | } |
284 | ||
7f84eef0 | 285 | /* Ring the host controller doorbell after placing a command on the ring */ |
23e3be11 | 286 | void xhci_ring_cmd_db(struct xhci_hcd *xhci) |
7f84eef0 | 287 | { |
c181bc5b EF |
288 | if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING)) |
289 | return; | |
290 | ||
7f84eef0 | 291 | xhci_dbg(xhci, "// Ding dong!\n"); |
204b7793 | 292 | writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]); |
7f84eef0 | 293 | /* Flush PCI posted writes */ |
b0ba9720 | 294 | readl(&xhci->dba->doorbell[0]); |
7f84eef0 SS |
295 | } |
296 | ||
b92cc66c EF |
297 | static int xhci_abort_cmd_ring(struct xhci_hcd *xhci) |
298 | { | |
299 | u64 temp_64; | |
300 | int ret; | |
301 | ||
302 | xhci_dbg(xhci, "Abort command ring\n"); | |
303 | ||
304 | if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING)) { | |
305 | xhci_dbg(xhci, "The command ring isn't running, " | |
306 | "Have the command ring been stopped?\n"); | |
307 | return 0; | |
308 | } | |
309 | ||
f7b2e403 | 310 | temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring); |
b92cc66c EF |
311 | if (!(temp_64 & CMD_RING_RUNNING)) { |
312 | xhci_dbg(xhci, "Command ring had been stopped\n"); | |
313 | return 0; | |
314 | } | |
315 | xhci->cmd_ring_state = CMD_RING_STATE_ABORTED; | |
477632df SS |
316 | xhci_write_64(xhci, temp_64 | CMD_RING_ABORT, |
317 | &xhci->op_regs->cmd_ring); | |
b92cc66c EF |
318 | |
319 | /* Section 4.6.1.2 of xHCI 1.0 spec says software should | |
320 | * time the completion od all xHCI commands, including | |
321 | * the Command Abort operation. If software doesn't see | |
322 | * CRR negated in a timely manner (e.g. longer than 5 | |
323 | * seconds), then it should assume that the there are | |
324 | * larger problems with the xHC and assert HCRST. | |
325 | */ | |
2611bd18 | 326 | ret = xhci_handshake(xhci, &xhci->op_regs->cmd_ring, |
b92cc66c EF |
327 | CMD_RING_RUNNING, 0, 5 * 1000 * 1000); |
328 | if (ret < 0) { | |
329 | xhci_err(xhci, "Stopped the command ring failed, " | |
330 | "maybe the host is dead\n"); | |
331 | xhci->xhc_state |= XHCI_STATE_DYING; | |
332 | xhci_quiesce(xhci); | |
333 | xhci_halt(xhci); | |
334 | return -ESHUTDOWN; | |
335 | } | |
336 | ||
337 | return 0; | |
338 | } | |
339 | ||
340 | static int xhci_queue_cd(struct xhci_hcd *xhci, | |
341 | struct xhci_command *command, | |
342 | union xhci_trb *cmd_trb) | |
343 | { | |
344 | struct xhci_cd *cd; | |
345 | cd = kzalloc(sizeof(struct xhci_cd), GFP_ATOMIC); | |
346 | if (!cd) | |
347 | return -ENOMEM; | |
348 | INIT_LIST_HEAD(&cd->cancel_cmd_list); | |
349 | ||
350 | cd->command = command; | |
351 | cd->cmd_trb = cmd_trb; | |
352 | list_add_tail(&cd->cancel_cmd_list, &xhci->cancel_cmd_list); | |
353 | ||
354 | return 0; | |
355 | } | |
356 | ||
357 | /* | |
358 | * Cancel the command which has issue. | |
359 | * | |
360 | * Some commands may hang due to waiting for acknowledgement from | |
361 | * usb device. It is outside of the xHC's ability to control and | |
362 | * will cause the command ring is blocked. When it occurs software | |
363 | * should intervene to recover the command ring. | |
364 | * See Section 4.6.1.1 and 4.6.1.2 | |
365 | */ | |
366 | int xhci_cancel_cmd(struct xhci_hcd *xhci, struct xhci_command *command, | |
367 | union xhci_trb *cmd_trb) | |
368 | { | |
369 | int retval = 0; | |
370 | unsigned long flags; | |
371 | ||
372 | spin_lock_irqsave(&xhci->lock, flags); | |
373 | ||
374 | if (xhci->xhc_state & XHCI_STATE_DYING) { | |
375 | xhci_warn(xhci, "Abort the command ring," | |
376 | " but the xHCI is dead.\n"); | |
377 | retval = -ESHUTDOWN; | |
378 | goto fail; | |
379 | } | |
380 | ||
381 | /* queue the cmd desriptor to cancel_cmd_list */ | |
382 | retval = xhci_queue_cd(xhci, command, cmd_trb); | |
383 | if (retval) { | |
384 | xhci_warn(xhci, "Queuing command descriptor failed.\n"); | |
385 | goto fail; | |
386 | } | |
387 | ||
388 | /* abort command ring */ | |
389 | retval = xhci_abort_cmd_ring(xhci); | |
390 | if (retval) { | |
391 | xhci_err(xhci, "Abort command ring failed\n"); | |
392 | if (unlikely(retval == -ESHUTDOWN)) { | |
393 | spin_unlock_irqrestore(&xhci->lock, flags); | |
394 | usb_hc_died(xhci_to_hcd(xhci)->primary_hcd); | |
395 | xhci_dbg(xhci, "xHCI host controller is dead.\n"); | |
396 | return retval; | |
397 | } | |
398 | } | |
399 | ||
400 | fail: | |
401 | spin_unlock_irqrestore(&xhci->lock, flags); | |
402 | return retval; | |
403 | } | |
404 | ||
be88fe4f | 405 | void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, |
ae636747 | 406 | unsigned int slot_id, |
e9df17eb SS |
407 | unsigned int ep_index, |
408 | unsigned int stream_id) | |
ae636747 | 409 | { |
28ccd296 | 410 | __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id]; |
50d64676 MW |
411 | struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index]; |
412 | unsigned int ep_state = ep->ep_state; | |
ae636747 | 413 | |
ae636747 | 414 | /* Don't ring the doorbell for this endpoint if there are pending |
50d64676 | 415 | * cancellations because we don't want to interrupt processing. |
8df75f42 SS |
416 | * We don't want to restart any stream rings if there's a set dequeue |
417 | * pointer command pending because the device can choose to start any | |
418 | * stream once the endpoint is on the HW schedule. | |
419 | * FIXME - check all the stream rings for pending cancellations. | |
ae636747 | 420 | */ |
50d64676 MW |
421 | if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) || |
422 | (ep_state & EP_HALTED)) | |
423 | return; | |
204b7793 | 424 | writel(DB_VALUE(ep_index, stream_id), db_addr); |
50d64676 MW |
425 | /* The CPU has better things to do at this point than wait for a |
426 | * write-posting flush. It'll get there soon enough. | |
427 | */ | |
ae636747 SS |
428 | } |
429 | ||
e9df17eb SS |
430 | /* Ring the doorbell for any rings with pending URBs */ |
431 | static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci, | |
432 | unsigned int slot_id, | |
433 | unsigned int ep_index) | |
434 | { | |
435 | unsigned int stream_id; | |
436 | struct xhci_virt_ep *ep; | |
437 | ||
438 | ep = &xhci->devs[slot_id]->eps[ep_index]; | |
439 | ||
440 | /* A ring has pending URBs if its TD list is not empty */ | |
441 | if (!(ep->ep_state & EP_HAS_STREAMS)) { | |
d66eaf9f | 442 | if (ep->ring && !(list_empty(&ep->ring->td_list))) |
be88fe4f | 443 | xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0); |
e9df17eb SS |
444 | return; |
445 | } | |
446 | ||
447 | for (stream_id = 1; stream_id < ep->stream_info->num_streams; | |
448 | stream_id++) { | |
449 | struct xhci_stream_info *stream_info = ep->stream_info; | |
450 | if (!list_empty(&stream_info->stream_rings[stream_id]->td_list)) | |
be88fe4f AX |
451 | xhci_ring_ep_doorbell(xhci, slot_id, ep_index, |
452 | stream_id); | |
e9df17eb SS |
453 | } |
454 | } | |
455 | ||
ae636747 SS |
456 | /* |
457 | * Find the segment that trb is in. Start searching in start_seg. | |
458 | * If we must move past a segment that has a link TRB with a toggle cycle state | |
459 | * bit set, then we will toggle the value pointed at by cycle_state. | |
460 | */ | |
461 | static struct xhci_segment *find_trb_seg( | |
462 | struct xhci_segment *start_seg, | |
463 | union xhci_trb *trb, int *cycle_state) | |
464 | { | |
465 | struct xhci_segment *cur_seg = start_seg; | |
466 | struct xhci_generic_trb *generic_trb; | |
467 | ||
468 | while (cur_seg->trbs > trb || | |
469 | &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) { | |
470 | generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic; | |
f5960b69 | 471 | if (generic_trb->field[3] & cpu_to_le32(LINK_TOGGLE)) |
ba0a4d9a | 472 | *cycle_state ^= 0x1; |
ae636747 SS |
473 | cur_seg = cur_seg->next; |
474 | if (cur_seg == start_seg) | |
475 | /* Looped over the entire list. Oops! */ | |
326b4810 | 476 | return NULL; |
ae636747 SS |
477 | } |
478 | return cur_seg; | |
479 | } | |
480 | ||
021bff91 SS |
481 | |
482 | static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci, | |
483 | unsigned int slot_id, unsigned int ep_index, | |
484 | unsigned int stream_id) | |
485 | { | |
486 | struct xhci_virt_ep *ep; | |
487 | ||
488 | ep = &xhci->devs[slot_id]->eps[ep_index]; | |
489 | /* Common case: no streams */ | |
490 | if (!(ep->ep_state & EP_HAS_STREAMS)) | |
491 | return ep->ring; | |
492 | ||
493 | if (stream_id == 0) { | |
494 | xhci_warn(xhci, | |
495 | "WARN: Slot ID %u, ep index %u has streams, " | |
496 | "but URB has no stream ID.\n", | |
497 | slot_id, ep_index); | |
498 | return NULL; | |
499 | } | |
500 | ||
501 | if (stream_id < ep->stream_info->num_streams) | |
502 | return ep->stream_info->stream_rings[stream_id]; | |
503 | ||
504 | xhci_warn(xhci, | |
505 | "WARN: Slot ID %u, ep index %u has " | |
506 | "stream IDs 1 to %u allocated, " | |
507 | "but stream ID %u is requested.\n", | |
508 | slot_id, ep_index, | |
509 | ep->stream_info->num_streams - 1, | |
510 | stream_id); | |
511 | return NULL; | |
512 | } | |
513 | ||
514 | /* Get the right ring for the given URB. | |
515 | * If the endpoint supports streams, boundary check the URB's stream ID. | |
516 | * If the endpoint doesn't support streams, return the singular endpoint ring. | |
517 | */ | |
518 | static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci, | |
519 | struct urb *urb) | |
520 | { | |
521 | return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id, | |
522 | xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id); | |
523 | } | |
524 | ||
ae636747 SS |
525 | /* |
526 | * Move the xHC's endpoint ring dequeue pointer past cur_td. | |
527 | * Record the new state of the xHC's endpoint ring dequeue segment, | |
528 | * dequeue pointer, and new consumer cycle state in state. | |
529 | * Update our internal representation of the ring's dequeue pointer. | |
530 | * | |
531 | * We do this in three jumps: | |
532 | * - First we update our new ring state to be the same as when the xHC stopped. | |
533 | * - Then we traverse the ring to find the segment that contains | |
534 | * the last TRB in the TD. We toggle the xHC's new cycle state when we pass | |
535 | * any link TRBs with the toggle cycle bit set. | |
536 | * - Finally we move the dequeue state one TRB further, toggling the cycle bit | |
537 | * if we've moved it past a link TRB with the toggle cycle bit set. | |
28ccd296 ME |
538 | * |
539 | * Some of the uses of xhci_generic_trb are grotty, but if they're done | |
540 | * with correct __le32 accesses they should work fine. Only users of this are | |
541 | * in here. | |
ae636747 | 542 | */ |
c92bcfa7 | 543 | void xhci_find_new_dequeue_state(struct xhci_hcd *xhci, |
ae636747 | 544 | unsigned int slot_id, unsigned int ep_index, |
e9df17eb SS |
545 | unsigned int stream_id, struct xhci_td *cur_td, |
546 | struct xhci_dequeue_state *state) | |
ae636747 SS |
547 | { |
548 | struct xhci_virt_device *dev = xhci->devs[slot_id]; | |
c4bedb77 | 549 | struct xhci_virt_ep *ep = &dev->eps[ep_index]; |
e9df17eb | 550 | struct xhci_ring *ep_ring; |
ae636747 | 551 | struct xhci_generic_trb *trb; |
c92bcfa7 | 552 | dma_addr_t addr; |
ae636747 | 553 | |
e9df17eb SS |
554 | ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id, |
555 | ep_index, stream_id); | |
556 | if (!ep_ring) { | |
557 | xhci_warn(xhci, "WARN can't find new dequeue state " | |
558 | "for invalid stream ID %u.\n", | |
559 | stream_id); | |
560 | return; | |
561 | } | |
ae636747 | 562 | state->new_cycle_state = 0; |
aa50b290 XR |
563 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
564 | "Finding segment containing stopped TRB."); | |
ae636747 | 565 | state->new_deq_seg = find_trb_seg(cur_td->start_seg, |
63a0d9ab | 566 | dev->eps[ep_index].stopped_trb, |
ae636747 | 567 | &state->new_cycle_state); |
68e41c5d PZ |
568 | if (!state->new_deq_seg) { |
569 | WARN_ON(1); | |
570 | return; | |
571 | } | |
572 | ||
ae636747 | 573 | /* Dig out the cycle state saved by the xHC during the stop ep cmd */ |
aa50b290 XR |
574 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
575 | "Finding endpoint context"); | |
c4bedb77 HG |
576 | /* 4.6.9 the css flag is written to the stream context for streams */ |
577 | if (ep->ep_state & EP_HAS_STREAMS) { | |
578 | struct xhci_stream_ctx *ctx = | |
579 | &ep->stream_info->stream_ctx_array[stream_id]; | |
580 | state->new_cycle_state = 0x1 & le64_to_cpu(ctx->stream_ring); | |
581 | } else { | |
582 | struct xhci_ep_ctx *ep_ctx | |
583 | = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index); | |
584 | state->new_cycle_state = 0x1 & le64_to_cpu(ep_ctx->deq); | |
585 | } | |
ae636747 SS |
586 | |
587 | state->new_deq_ptr = cur_td->last_trb; | |
aa50b290 XR |
588 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
589 | "Finding segment containing last TRB in TD."); | |
ae636747 SS |
590 | state->new_deq_seg = find_trb_seg(state->new_deq_seg, |
591 | state->new_deq_ptr, | |
592 | &state->new_cycle_state); | |
68e41c5d PZ |
593 | if (!state->new_deq_seg) { |
594 | WARN_ON(1); | |
595 | return; | |
596 | } | |
ae636747 SS |
597 | |
598 | trb = &state->new_deq_ptr->generic; | |
f5960b69 ME |
599 | if (TRB_TYPE_LINK_LE32(trb->field[3]) && |
600 | (trb->field[3] & cpu_to_le32(LINK_TOGGLE))) | |
ba0a4d9a | 601 | state->new_cycle_state ^= 0x1; |
ae636747 SS |
602 | next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr); |
603 | ||
01a1fdb9 SS |
604 | /* |
605 | * If there is only one segment in a ring, find_trb_seg()'s while loop | |
606 | * will not run, and it will return before it has a chance to see if it | |
607 | * needs to toggle the cycle bit. It can't tell if the stalled transfer | |
608 | * ended just before the link TRB on a one-segment ring, or if the TD | |
609 | * wrapped around the top of the ring, because it doesn't have the TD in | |
610 | * question. Look for the one-segment case where stalled TRB's address | |
611 | * is greater than the new dequeue pointer address. | |
612 | */ | |
613 | if (ep_ring->first_seg == ep_ring->first_seg->next && | |
614 | state->new_deq_ptr < dev->eps[ep_index].stopped_trb) | |
615 | state->new_cycle_state ^= 0x1; | |
aa50b290 XR |
616 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
617 | "Cycle state = 0x%x", state->new_cycle_state); | |
01a1fdb9 | 618 | |
ae636747 | 619 | /* Don't update the ring cycle state for the producer (us). */ |
aa50b290 XR |
620 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
621 | "New dequeue segment = %p (virtual)", | |
c92bcfa7 SS |
622 | state->new_deq_seg); |
623 | addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr); | |
aa50b290 XR |
624 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
625 | "New dequeue pointer = 0x%llx (DMA)", | |
c92bcfa7 | 626 | (unsigned long long) addr); |
ae636747 SS |
627 | } |
628 | ||
522989a2 SS |
629 | /* flip_cycle means flip the cycle bit of all but the first and last TRB. |
630 | * (The last TRB actually points to the ring enqueue pointer, which is not part | |
631 | * of this TD.) This is used to remove partially enqueued isoc TDs from a ring. | |
632 | */ | |
23e3be11 | 633 | static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring, |
522989a2 | 634 | struct xhci_td *cur_td, bool flip_cycle) |
ae636747 SS |
635 | { |
636 | struct xhci_segment *cur_seg; | |
637 | union xhci_trb *cur_trb; | |
638 | ||
639 | for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb; | |
640 | true; | |
641 | next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) { | |
f5960b69 | 642 | if (TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) { |
ae636747 SS |
643 | /* Unchain any chained Link TRBs, but |
644 | * leave the pointers intact. | |
645 | */ | |
28ccd296 | 646 | cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN); |
522989a2 SS |
647 | /* Flip the cycle bit (link TRBs can't be the first |
648 | * or last TRB). | |
649 | */ | |
650 | if (flip_cycle) | |
651 | cur_trb->generic.field[3] ^= | |
652 | cpu_to_le32(TRB_CYCLE); | |
aa50b290 XR |
653 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
654 | "Cancel (unchain) link TRB"); | |
655 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, | |
656 | "Address = %p (0x%llx dma); " | |
657 | "in seg %p (0x%llx dma)", | |
700e2052 | 658 | cur_trb, |
23e3be11 | 659 | (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb), |
700e2052 GKH |
660 | cur_seg, |
661 | (unsigned long long)cur_seg->dma); | |
ae636747 SS |
662 | } else { |
663 | cur_trb->generic.field[0] = 0; | |
664 | cur_trb->generic.field[1] = 0; | |
665 | cur_trb->generic.field[2] = 0; | |
666 | /* Preserve only the cycle bit of this TRB */ | |
28ccd296 | 667 | cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE); |
522989a2 SS |
668 | /* Flip the cycle bit except on the first or last TRB */ |
669 | if (flip_cycle && cur_trb != cur_td->first_trb && | |
670 | cur_trb != cur_td->last_trb) | |
671 | cur_trb->generic.field[3] ^= | |
672 | cpu_to_le32(TRB_CYCLE); | |
28ccd296 ME |
673 | cur_trb->generic.field[3] |= cpu_to_le32( |
674 | TRB_TYPE(TRB_TR_NOOP)); | |
aa50b290 XR |
675 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
676 | "TRB to noop at offset 0x%llx", | |
79688acf SS |
677 | (unsigned long long) |
678 | xhci_trb_virt_to_dma(cur_seg, cur_trb)); | |
ae636747 SS |
679 | } |
680 | if (cur_trb == cur_td->last_trb) | |
681 | break; | |
682 | } | |
683 | } | |
684 | ||
685 | static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id, | |
e9df17eb SS |
686 | unsigned int ep_index, unsigned int stream_id, |
687 | struct xhci_segment *deq_seg, | |
ae636747 SS |
688 | union xhci_trb *deq_ptr, u32 cycle_state); |
689 | ||
c92bcfa7 | 690 | void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci, |
63a0d9ab | 691 | unsigned int slot_id, unsigned int ep_index, |
e9df17eb | 692 | unsigned int stream_id, |
63a0d9ab | 693 | struct xhci_dequeue_state *deq_state) |
c92bcfa7 | 694 | { |
63a0d9ab SS |
695 | struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index]; |
696 | ||
aa50b290 XR |
697 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
698 | "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), " | |
699 | "new deq ptr = %p (0x%llx dma), new cycle = %u", | |
c92bcfa7 SS |
700 | deq_state->new_deq_seg, |
701 | (unsigned long long)deq_state->new_deq_seg->dma, | |
702 | deq_state->new_deq_ptr, | |
703 | (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr), | |
704 | deq_state->new_cycle_state); | |
e9df17eb | 705 | queue_set_tr_deq(xhci, slot_id, ep_index, stream_id, |
c92bcfa7 SS |
706 | deq_state->new_deq_seg, |
707 | deq_state->new_deq_ptr, | |
708 | (u32) deq_state->new_cycle_state); | |
709 | /* Stop the TD queueing code from ringing the doorbell until | |
710 | * this command completes. The HC won't set the dequeue pointer | |
711 | * if the ring is running, and ringing the doorbell starts the | |
712 | * ring running. | |
713 | */ | |
63a0d9ab | 714 | ep->ep_state |= SET_DEQ_PENDING; |
c92bcfa7 SS |
715 | } |
716 | ||
575688e1 | 717 | static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci, |
6f5165cf SS |
718 | struct xhci_virt_ep *ep) |
719 | { | |
720 | ep->ep_state &= ~EP_HALT_PENDING; | |
721 | /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the | |
722 | * timer is running on another CPU, we don't decrement stop_cmds_pending | |
723 | * (since we didn't successfully stop the watchdog timer). | |
724 | */ | |
725 | if (del_timer(&ep->stop_cmd_timer)) | |
726 | ep->stop_cmds_pending--; | |
727 | } | |
728 | ||
729 | /* Must be called with xhci->lock held in interrupt context */ | |
730 | static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci, | |
07a37e9e | 731 | struct xhci_td *cur_td, int status) |
6f5165cf | 732 | { |
214f76f7 | 733 | struct usb_hcd *hcd; |
8e51adcc AX |
734 | struct urb *urb; |
735 | struct urb_priv *urb_priv; | |
6f5165cf | 736 | |
8e51adcc AX |
737 | urb = cur_td->urb; |
738 | urb_priv = urb->hcpriv; | |
739 | urb_priv->td_cnt++; | |
214f76f7 | 740 | hcd = bus_to_hcd(urb->dev->bus); |
6f5165cf | 741 | |
8e51adcc AX |
742 | /* Only giveback urb when this is the last td in urb */ |
743 | if (urb_priv->td_cnt == urb_priv->length) { | |
c41136b0 AX |
744 | if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { |
745 | xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--; | |
746 | if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) { | |
747 | if (xhci->quirks & XHCI_AMD_PLL_FIX) | |
748 | usb_amd_quirk_pll_enable(); | |
749 | } | |
750 | } | |
8e51adcc | 751 | usb_hcd_unlink_urb_from_ep(hcd, urb); |
8e51adcc AX |
752 | |
753 | spin_unlock(&xhci->lock); | |
754 | usb_hcd_giveback_urb(hcd, urb, status); | |
755 | xhci_urb_free_priv(xhci, urb_priv); | |
756 | spin_lock(&xhci->lock); | |
8e51adcc | 757 | } |
6f5165cf SS |
758 | } |
759 | ||
ae636747 SS |
760 | /* |
761 | * When we get a command completion for a Stop Endpoint Command, we need to | |
762 | * unlink any cancelled TDs from the ring. There are two ways to do that: | |
763 | * | |
764 | * 1. If the HW was in the middle of processing the TD that needs to be | |
765 | * cancelled, then we must move the ring's dequeue pointer past the last TRB | |
766 | * in the TD with a Set Dequeue Pointer Command. | |
767 | * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain | |
768 | * bit cleared) so that the HW will skip over them. | |
769 | */ | |
b8200c94 | 770 | static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id, |
be88fe4f | 771 | union xhci_trb *trb, struct xhci_event_cmd *event) |
ae636747 | 772 | { |
ae636747 | 773 | unsigned int ep_index; |
be88fe4f | 774 | struct xhci_virt_device *virt_dev; |
ae636747 | 775 | struct xhci_ring *ep_ring; |
63a0d9ab | 776 | struct xhci_virt_ep *ep; |
ae636747 | 777 | struct list_head *entry; |
326b4810 | 778 | struct xhci_td *cur_td = NULL; |
ae636747 SS |
779 | struct xhci_td *last_unlinked_td; |
780 | ||
c92bcfa7 | 781 | struct xhci_dequeue_state deq_state; |
ae636747 | 782 | |
bc752bde | 783 | if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) { |
be88fe4f AX |
784 | virt_dev = xhci->devs[slot_id]; |
785 | if (virt_dev) | |
786 | handle_cmd_in_cmd_wait_list(xhci, virt_dev, | |
787 | event); | |
788 | else | |
789 | xhci_warn(xhci, "Stop endpoint command " | |
790 | "completion for disabled slot %u\n", | |
791 | slot_id); | |
792 | return; | |
793 | } | |
794 | ||
ae636747 | 795 | memset(&deq_state, 0, sizeof(deq_state)); |
28ccd296 | 796 | ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); |
63a0d9ab | 797 | ep = &xhci->devs[slot_id]->eps[ep_index]; |
ae636747 | 798 | |
678539cf | 799 | if (list_empty(&ep->cancelled_td_list)) { |
6f5165cf | 800 | xhci_stop_watchdog_timer_in_irq(xhci, ep); |
0714a57c SS |
801 | ep->stopped_td = NULL; |
802 | ep->stopped_trb = NULL; | |
e9df17eb | 803 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); |
ae636747 | 804 | return; |
678539cf | 805 | } |
ae636747 SS |
806 | |
807 | /* Fix up the ep ring first, so HW stops executing cancelled TDs. | |
808 | * We have the xHCI lock, so nothing can modify this list until we drop | |
809 | * it. We're also in the event handler, so we can't get re-interrupted | |
810 | * if another Stop Endpoint command completes | |
811 | */ | |
63a0d9ab | 812 | list_for_each(entry, &ep->cancelled_td_list) { |
ae636747 | 813 | cur_td = list_entry(entry, struct xhci_td, cancelled_td_list); |
aa50b290 XR |
814 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
815 | "Removing canceled TD starting at 0x%llx (dma).", | |
79688acf SS |
816 | (unsigned long long)xhci_trb_virt_to_dma( |
817 | cur_td->start_seg, cur_td->first_trb)); | |
e9df17eb SS |
818 | ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb); |
819 | if (!ep_ring) { | |
820 | /* This shouldn't happen unless a driver is mucking | |
821 | * with the stream ID after submission. This will | |
822 | * leave the TD on the hardware ring, and the hardware | |
823 | * will try to execute it, and may access a buffer | |
824 | * that has already been freed. In the best case, the | |
825 | * hardware will execute it, and the event handler will | |
826 | * ignore the completion event for that TD, since it was | |
827 | * removed from the td_list for that endpoint. In | |
828 | * short, don't muck with the stream ID after | |
829 | * submission. | |
830 | */ | |
831 | xhci_warn(xhci, "WARN Cancelled URB %p " | |
832 | "has invalid stream ID %u.\n", | |
833 | cur_td->urb, | |
834 | cur_td->urb->stream_id); | |
835 | goto remove_finished_td; | |
836 | } | |
ae636747 SS |
837 | /* |
838 | * If we stopped on the TD we need to cancel, then we have to | |
839 | * move the xHC endpoint ring dequeue pointer past this TD. | |
840 | */ | |
63a0d9ab | 841 | if (cur_td == ep->stopped_td) |
e9df17eb SS |
842 | xhci_find_new_dequeue_state(xhci, slot_id, ep_index, |
843 | cur_td->urb->stream_id, | |
844 | cur_td, &deq_state); | |
ae636747 | 845 | else |
522989a2 | 846 | td_to_noop(xhci, ep_ring, cur_td, false); |
e9df17eb | 847 | remove_finished_td: |
ae636747 SS |
848 | /* |
849 | * The event handler won't see a completion for this TD anymore, | |
850 | * so remove it from the endpoint ring's TD list. Keep it in | |
851 | * the cancelled TD list for URB completion later. | |
852 | */ | |
585df1d9 | 853 | list_del_init(&cur_td->td_list); |
ae636747 SS |
854 | } |
855 | last_unlinked_td = cur_td; | |
6f5165cf | 856 | xhci_stop_watchdog_timer_in_irq(xhci, ep); |
ae636747 SS |
857 | |
858 | /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */ | |
859 | if (deq_state.new_deq_ptr && deq_state.new_deq_seg) { | |
63a0d9ab | 860 | xhci_queue_new_dequeue_state(xhci, |
e9df17eb SS |
861 | slot_id, ep_index, |
862 | ep->stopped_td->urb->stream_id, | |
863 | &deq_state); | |
ac9d8fe7 | 864 | xhci_ring_cmd_db(xhci); |
ae636747 | 865 | } else { |
e9df17eb SS |
866 | /* Otherwise ring the doorbell(s) to restart queued transfers */ |
867 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); | |
ae636747 | 868 | } |
526867c3 FW |
869 | |
870 | /* Clear stopped_td and stopped_trb if endpoint is not halted */ | |
871 | if (!(ep->ep_state & EP_HALTED)) { | |
872 | ep->stopped_td = NULL; | |
873 | ep->stopped_trb = NULL; | |
874 | } | |
ae636747 SS |
875 | |
876 | /* | |
877 | * Drop the lock and complete the URBs in the cancelled TD list. | |
878 | * New TDs to be cancelled might be added to the end of the list before | |
879 | * we can complete all the URBs for the TDs we already unlinked. | |
880 | * So stop when we've completed the URB for the last TD we unlinked. | |
881 | */ | |
882 | do { | |
63a0d9ab | 883 | cur_td = list_entry(ep->cancelled_td_list.next, |
ae636747 | 884 | struct xhci_td, cancelled_td_list); |
585df1d9 | 885 | list_del_init(&cur_td->cancelled_td_list); |
ae636747 SS |
886 | |
887 | /* Clean up the cancelled URB */ | |
ae636747 SS |
888 | /* Doesn't matter what we pass for status, since the core will |
889 | * just overwrite it (because the URB has been unlinked). | |
890 | */ | |
07a37e9e | 891 | xhci_giveback_urb_in_irq(xhci, cur_td, 0); |
ae636747 | 892 | |
6f5165cf SS |
893 | /* Stop processing the cancelled list if the watchdog timer is |
894 | * running. | |
895 | */ | |
896 | if (xhci->xhc_state & XHCI_STATE_DYING) | |
897 | return; | |
ae636747 SS |
898 | } while (cur_td != last_unlinked_td); |
899 | ||
900 | /* Return to the event handler with xhci->lock re-acquired */ | |
901 | } | |
902 | ||
50e8725e SS |
903 | static void xhci_kill_ring_urbs(struct xhci_hcd *xhci, struct xhci_ring *ring) |
904 | { | |
905 | struct xhci_td *cur_td; | |
906 | ||
907 | while (!list_empty(&ring->td_list)) { | |
908 | cur_td = list_first_entry(&ring->td_list, | |
909 | struct xhci_td, td_list); | |
910 | list_del_init(&cur_td->td_list); | |
911 | if (!list_empty(&cur_td->cancelled_td_list)) | |
912 | list_del_init(&cur_td->cancelled_td_list); | |
913 | xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN); | |
914 | } | |
915 | } | |
916 | ||
917 | static void xhci_kill_endpoint_urbs(struct xhci_hcd *xhci, | |
918 | int slot_id, int ep_index) | |
919 | { | |
920 | struct xhci_td *cur_td; | |
921 | struct xhci_virt_ep *ep; | |
922 | struct xhci_ring *ring; | |
923 | ||
924 | ep = &xhci->devs[slot_id]->eps[ep_index]; | |
925 | ring = ep->ring; | |
926 | if (!ring) | |
927 | return; | |
928 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, | |
929 | "Killing URBs for slot ID %u, ep index %u", | |
930 | slot_id, ep_index); | |
931 | xhci_kill_ring_urbs(xhci, ring); | |
932 | while (!list_empty(&ep->cancelled_td_list)) { | |
933 | cur_td = list_first_entry(&ep->cancelled_td_list, | |
934 | struct xhci_td, cancelled_td_list); | |
935 | list_del_init(&cur_td->cancelled_td_list); | |
936 | xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN); | |
937 | } | |
938 | } | |
939 | ||
6f5165cf SS |
940 | /* Watchdog timer function for when a stop endpoint command fails to complete. |
941 | * In this case, we assume the host controller is broken or dying or dead. The | |
942 | * host may still be completing some other events, so we have to be careful to | |
943 | * let the event ring handler and the URB dequeueing/enqueueing functions know | |
944 | * through xhci->state. | |
945 | * | |
946 | * The timer may also fire if the host takes a very long time to respond to the | |
947 | * command, and the stop endpoint command completion handler cannot delete the | |
948 | * timer before the timer function is called. Another endpoint cancellation may | |
949 | * sneak in before the timer function can grab the lock, and that may queue | |
950 | * another stop endpoint command and add the timer back. So we cannot use a | |
951 | * simple flag to say whether there is a pending stop endpoint command for a | |
952 | * particular endpoint. | |
953 | * | |
954 | * Instead we use a combination of that flag and a counter for the number of | |
955 | * pending stop endpoint commands. If the timer is the tail end of the last | |
956 | * stop endpoint command, and the endpoint's command is still pending, we assume | |
957 | * the host is dying. | |
958 | */ | |
959 | void xhci_stop_endpoint_command_watchdog(unsigned long arg) | |
960 | { | |
961 | struct xhci_hcd *xhci; | |
962 | struct xhci_virt_ep *ep; | |
6f5165cf | 963 | int ret, i, j; |
f43d6231 | 964 | unsigned long flags; |
6f5165cf SS |
965 | |
966 | ep = (struct xhci_virt_ep *) arg; | |
967 | xhci = ep->xhci; | |
968 | ||
f43d6231 | 969 | spin_lock_irqsave(&xhci->lock, flags); |
6f5165cf SS |
970 | |
971 | ep->stop_cmds_pending--; | |
972 | if (xhci->xhc_state & XHCI_STATE_DYING) { | |
aa50b290 XR |
973 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
974 | "Stop EP timer ran, but another timer marked " | |
975 | "xHCI as DYING, exiting."); | |
f43d6231 | 976 | spin_unlock_irqrestore(&xhci->lock, flags); |
6f5165cf SS |
977 | return; |
978 | } | |
979 | if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) { | |
aa50b290 XR |
980 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
981 | "Stop EP timer ran, but no command pending, " | |
982 | "exiting."); | |
f43d6231 | 983 | spin_unlock_irqrestore(&xhci->lock, flags); |
6f5165cf SS |
984 | return; |
985 | } | |
986 | ||
987 | xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n"); | |
988 | xhci_warn(xhci, "Assuming host is dying, halting host.\n"); | |
989 | /* Oops, HC is dead or dying or at least not responding to the stop | |
990 | * endpoint command. | |
991 | */ | |
992 | xhci->xhc_state |= XHCI_STATE_DYING; | |
993 | /* Disable interrupts from the host controller and start halting it */ | |
994 | xhci_quiesce(xhci); | |
f43d6231 | 995 | spin_unlock_irqrestore(&xhci->lock, flags); |
6f5165cf SS |
996 | |
997 | ret = xhci_halt(xhci); | |
998 | ||
f43d6231 | 999 | spin_lock_irqsave(&xhci->lock, flags); |
6f5165cf SS |
1000 | if (ret < 0) { |
1001 | /* This is bad; the host is not responding to commands and it's | |
1002 | * not allowing itself to be halted. At least interrupts are | |
ac04e6ff | 1003 | * disabled. If we call usb_hc_died(), it will attempt to |
6f5165cf SS |
1004 | * disconnect all device drivers under this host. Those |
1005 | * disconnect() methods will wait for all URBs to be unlinked, | |
1006 | * so we must complete them. | |
1007 | */ | |
1008 | xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n"); | |
1009 | xhci_warn(xhci, "Completing active URBs anyway.\n"); | |
1010 | /* We could turn all TDs on the rings to no-ops. This won't | |
1011 | * help if the host has cached part of the ring, and is slow if | |
1012 | * we want to preserve the cycle bit. Skip it and hope the host | |
1013 | * doesn't touch the memory. | |
1014 | */ | |
1015 | } | |
1016 | for (i = 0; i < MAX_HC_SLOTS; i++) { | |
1017 | if (!xhci->devs[i]) | |
1018 | continue; | |
50e8725e SS |
1019 | for (j = 0; j < 31; j++) |
1020 | xhci_kill_endpoint_urbs(xhci, i, j); | |
6f5165cf | 1021 | } |
f43d6231 | 1022 | spin_unlock_irqrestore(&xhci->lock, flags); |
aa50b290 XR |
1023 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
1024 | "Calling usb_hc_died()"); | |
f6ff0ac8 | 1025 | usb_hc_died(xhci_to_hcd(xhci)->primary_hcd); |
aa50b290 XR |
1026 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
1027 | "xHCI host controller is dead."); | |
6f5165cf SS |
1028 | } |
1029 | ||
b008df60 AX |
1030 | |
1031 | static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci, | |
1032 | struct xhci_virt_device *dev, | |
1033 | struct xhci_ring *ep_ring, | |
1034 | unsigned int ep_index) | |
1035 | { | |
1036 | union xhci_trb *dequeue_temp; | |
1037 | int num_trbs_free_temp; | |
1038 | bool revert = false; | |
1039 | ||
1040 | num_trbs_free_temp = ep_ring->num_trbs_free; | |
1041 | dequeue_temp = ep_ring->dequeue; | |
1042 | ||
0d9f78a9 SS |
1043 | /* If we get two back-to-back stalls, and the first stalled transfer |
1044 | * ends just before a link TRB, the dequeue pointer will be left on | |
1045 | * the link TRB by the code in the while loop. So we have to update | |
1046 | * the dequeue pointer one segment further, or we'll jump off | |
1047 | * the segment into la-la-land. | |
1048 | */ | |
1049 | if (last_trb(xhci, ep_ring, ep_ring->deq_seg, ep_ring->dequeue)) { | |
1050 | ep_ring->deq_seg = ep_ring->deq_seg->next; | |
1051 | ep_ring->dequeue = ep_ring->deq_seg->trbs; | |
1052 | } | |
1053 | ||
b008df60 AX |
1054 | while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) { |
1055 | /* We have more usable TRBs */ | |
1056 | ep_ring->num_trbs_free++; | |
1057 | ep_ring->dequeue++; | |
1058 | if (last_trb(xhci, ep_ring, ep_ring->deq_seg, | |
1059 | ep_ring->dequeue)) { | |
1060 | if (ep_ring->dequeue == | |
1061 | dev->eps[ep_index].queued_deq_ptr) | |
1062 | break; | |
1063 | ep_ring->deq_seg = ep_ring->deq_seg->next; | |
1064 | ep_ring->dequeue = ep_ring->deq_seg->trbs; | |
1065 | } | |
1066 | if (ep_ring->dequeue == dequeue_temp) { | |
1067 | revert = true; | |
1068 | break; | |
1069 | } | |
1070 | } | |
1071 | ||
1072 | if (revert) { | |
1073 | xhci_dbg(xhci, "Unable to find new dequeue pointer\n"); | |
1074 | ep_ring->num_trbs_free = num_trbs_free_temp; | |
1075 | } | |
1076 | } | |
1077 | ||
ae636747 SS |
1078 | /* |
1079 | * When we get a completion for a Set Transfer Ring Dequeue Pointer command, | |
1080 | * we need to clear the set deq pending flag in the endpoint ring state, so that | |
1081 | * the TD queueing code can ring the doorbell again. We also need to ring the | |
1082 | * endpoint doorbell to restart the ring, but only if there aren't more | |
1083 | * cancellations pending. | |
1084 | */ | |
b8200c94 | 1085 | static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id, |
c69a0597 | 1086 | union xhci_trb *trb, u32 cmd_comp_code) |
ae636747 | 1087 | { |
ae636747 | 1088 | unsigned int ep_index; |
e9df17eb | 1089 | unsigned int stream_id; |
ae636747 SS |
1090 | struct xhci_ring *ep_ring; |
1091 | struct xhci_virt_device *dev; | |
9aad95e2 | 1092 | struct xhci_virt_ep *ep; |
d115b048 JY |
1093 | struct xhci_ep_ctx *ep_ctx; |
1094 | struct xhci_slot_ctx *slot_ctx; | |
ae636747 | 1095 | |
28ccd296 ME |
1096 | ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); |
1097 | stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2])); | |
ae636747 | 1098 | dev = xhci->devs[slot_id]; |
9aad95e2 | 1099 | ep = &dev->eps[ep_index]; |
e9df17eb SS |
1100 | |
1101 | ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id); | |
1102 | if (!ep_ring) { | |
e587b8b2 | 1103 | xhci_warn(xhci, "WARN Set TR deq ptr command for freed stream ID %u\n", |
e9df17eb SS |
1104 | stream_id); |
1105 | /* XXX: Harmless??? */ | |
1106 | dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING; | |
1107 | return; | |
1108 | } | |
1109 | ||
d115b048 JY |
1110 | ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index); |
1111 | slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx); | |
ae636747 | 1112 | |
c69a0597 | 1113 | if (cmd_comp_code != COMP_SUCCESS) { |
ae636747 SS |
1114 | unsigned int ep_state; |
1115 | unsigned int slot_state; | |
1116 | ||
c69a0597 | 1117 | switch (cmd_comp_code) { |
ae636747 | 1118 | case COMP_TRB_ERR: |
e587b8b2 | 1119 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n"); |
ae636747 SS |
1120 | break; |
1121 | case COMP_CTX_STATE: | |
e587b8b2 | 1122 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n"); |
28ccd296 | 1123 | ep_state = le32_to_cpu(ep_ctx->ep_info); |
ae636747 | 1124 | ep_state &= EP_STATE_MASK; |
28ccd296 | 1125 | slot_state = le32_to_cpu(slot_ctx->dev_state); |
ae636747 | 1126 | slot_state = GET_SLOT_STATE(slot_state); |
aa50b290 XR |
1127 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
1128 | "Slot state = %u, EP state = %u", | |
ae636747 SS |
1129 | slot_state, ep_state); |
1130 | break; | |
1131 | case COMP_EBADSLT: | |
e587b8b2 ON |
1132 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n", |
1133 | slot_id); | |
ae636747 SS |
1134 | break; |
1135 | default: | |
e587b8b2 ON |
1136 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n", |
1137 | cmd_comp_code); | |
ae636747 SS |
1138 | break; |
1139 | } | |
1140 | /* OK what do we do now? The endpoint state is hosed, and we | |
1141 | * should never get to this point if the synchronization between | |
1142 | * queueing, and endpoint state are correct. This might happen | |
1143 | * if the device gets disconnected after we've finished | |
1144 | * cancelling URBs, which might not be an error... | |
1145 | */ | |
1146 | } else { | |
9aad95e2 HG |
1147 | u64 deq; |
1148 | /* 4.6.10 deq ptr is written to the stream ctx for streams */ | |
1149 | if (ep->ep_state & EP_HAS_STREAMS) { | |
1150 | struct xhci_stream_ctx *ctx = | |
1151 | &ep->stream_info->stream_ctx_array[stream_id]; | |
1152 | deq = le64_to_cpu(ctx->stream_ring) & SCTX_DEQ_MASK; | |
1153 | } else { | |
1154 | deq = le64_to_cpu(ep_ctx->deq) & ~EP_CTX_CYCLE_MASK; | |
1155 | } | |
aa50b290 | 1156 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
9aad95e2 HG |
1157 | "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq); |
1158 | if (xhci_trb_virt_to_dma(ep->queued_deq_seg, | |
1159 | ep->queued_deq_ptr) == deq) { | |
bf161e85 SS |
1160 | /* Update the ring's dequeue segment and dequeue pointer |
1161 | * to reflect the new position. | |
1162 | */ | |
b008df60 AX |
1163 | update_ring_for_set_deq_completion(xhci, dev, |
1164 | ep_ring, ep_index); | |
bf161e85 | 1165 | } else { |
e587b8b2 | 1166 | xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n"); |
bf161e85 | 1167 | xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n", |
9aad95e2 | 1168 | ep->queued_deq_seg, ep->queued_deq_ptr); |
bf161e85 | 1169 | } |
ae636747 SS |
1170 | } |
1171 | ||
63a0d9ab | 1172 | dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING; |
bf161e85 SS |
1173 | dev->eps[ep_index].queued_deq_seg = NULL; |
1174 | dev->eps[ep_index].queued_deq_ptr = NULL; | |
e9df17eb SS |
1175 | /* Restart any rings with pending URBs */ |
1176 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); | |
ae636747 SS |
1177 | } |
1178 | ||
b8200c94 | 1179 | static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id, |
c69a0597 | 1180 | union xhci_trb *trb, u32 cmd_comp_code) |
a1587d97 | 1181 | { |
a1587d97 SS |
1182 | unsigned int ep_index; |
1183 | ||
28ccd296 | 1184 | ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); |
a1587d97 SS |
1185 | /* This command will only fail if the endpoint wasn't halted, |
1186 | * but we don't care. | |
1187 | */ | |
a0254324 | 1188 | xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep, |
c69a0597 | 1189 | "Ignoring reset ep completion code of %u", cmd_comp_code); |
a1587d97 | 1190 | |
ac9d8fe7 SS |
1191 | /* HW with the reset endpoint quirk needs to have a configure endpoint |
1192 | * command complete before the endpoint can be used. Queue that here | |
1193 | * because the HW can't handle two commands being queued in a row. | |
1194 | */ | |
1195 | if (xhci->quirks & XHCI_RESET_EP_QUIRK) { | |
4bdfe4c3 XR |
1196 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
1197 | "Queueing configure endpoint command"); | |
ac9d8fe7 | 1198 | xhci_queue_configure_endpoint(xhci, |
913a8a34 SS |
1199 | xhci->devs[slot_id]->in_ctx->dma, slot_id, |
1200 | false); | |
ac9d8fe7 SS |
1201 | xhci_ring_cmd_db(xhci); |
1202 | } else { | |
e9df17eb | 1203 | /* Clear our internal halted state and restart the ring(s) */ |
63a0d9ab | 1204 | xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED; |
e9df17eb | 1205 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); |
ac9d8fe7 | 1206 | } |
a1587d97 | 1207 | } |
ae636747 | 1208 | |
b63f4053 EF |
1209 | /* Complete the command and detele it from the devcie's command queue. |
1210 | */ | |
1211 | static void xhci_complete_cmd_in_cmd_wait_list(struct xhci_hcd *xhci, | |
1212 | struct xhci_command *command, u32 status) | |
1213 | { | |
1214 | command->status = status; | |
1215 | list_del(&command->cmd_list); | |
1216 | if (command->completion) | |
1217 | complete(command->completion); | |
1218 | else | |
1219 | xhci_free_command(xhci, command); | |
1220 | } | |
1221 | ||
1222 | ||
a50c8aa9 SS |
1223 | /* Check to see if a command in the device's command queue matches this one. |
1224 | * Signal the completion or free the command, and return 1. Return 0 if the | |
1225 | * completed command isn't at the head of the command list. | |
1226 | */ | |
1227 | static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci, | |
1228 | struct xhci_virt_device *virt_dev, | |
1229 | struct xhci_event_cmd *event) | |
1230 | { | |
1231 | struct xhci_command *command; | |
1232 | ||
1233 | if (list_empty(&virt_dev->cmd_list)) | |
1234 | return 0; | |
1235 | ||
1236 | command = list_entry(virt_dev->cmd_list.next, | |
1237 | struct xhci_command, cmd_list); | |
1238 | if (xhci->cmd_ring->dequeue != command->command_trb) | |
1239 | return 0; | |
1240 | ||
b63f4053 EF |
1241 | xhci_complete_cmd_in_cmd_wait_list(xhci, command, |
1242 | GET_COMP_CODE(le32_to_cpu(event->status))); | |
a50c8aa9 SS |
1243 | return 1; |
1244 | } | |
1245 | ||
b63f4053 EF |
1246 | /* |
1247 | * Finding the command trb need to be cancelled and modifying it to | |
1248 | * NO OP command. And if the command is in device's command wait | |
1249 | * list, finishing and freeing it. | |
1250 | * | |
1251 | * If we can't find the command trb, we think it had already been | |
1252 | * executed. | |
1253 | */ | |
1254 | static void xhci_cmd_to_noop(struct xhci_hcd *xhci, struct xhci_cd *cur_cd) | |
1255 | { | |
1256 | struct xhci_segment *cur_seg; | |
1257 | union xhci_trb *cmd_trb; | |
1258 | u32 cycle_state; | |
1259 | ||
1260 | if (xhci->cmd_ring->dequeue == xhci->cmd_ring->enqueue) | |
1261 | return; | |
1262 | ||
1263 | /* find the current segment of command ring */ | |
1264 | cur_seg = find_trb_seg(xhci->cmd_ring->first_seg, | |
1265 | xhci->cmd_ring->dequeue, &cycle_state); | |
1266 | ||
43a09f7f SS |
1267 | if (!cur_seg) { |
1268 | xhci_warn(xhci, "Command ring mismatch, dequeue = %p %llx (dma)\n", | |
1269 | xhci->cmd_ring->dequeue, | |
1270 | (unsigned long long) | |
1271 | xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg, | |
1272 | xhci->cmd_ring->dequeue)); | |
1273 | xhci_debug_ring(xhci, xhci->cmd_ring); | |
1274 | xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring); | |
1275 | return; | |
1276 | } | |
1277 | ||
b63f4053 EF |
1278 | /* find the command trb matched by cd from command ring */ |
1279 | for (cmd_trb = xhci->cmd_ring->dequeue; | |
1280 | cmd_trb != xhci->cmd_ring->enqueue; | |
1281 | next_trb(xhci, xhci->cmd_ring, &cur_seg, &cmd_trb)) { | |
1282 | /* If the trb is link trb, continue */ | |
1283 | if (TRB_TYPE_LINK_LE32(cmd_trb->generic.field[3])) | |
1284 | continue; | |
1285 | ||
1286 | if (cur_cd->cmd_trb == cmd_trb) { | |
1287 | ||
1288 | /* If the command in device's command list, we should | |
1289 | * finish it and free the command structure. | |
1290 | */ | |
1291 | if (cur_cd->command) | |
1292 | xhci_complete_cmd_in_cmd_wait_list(xhci, | |
1293 | cur_cd->command, COMP_CMD_STOP); | |
1294 | ||
1295 | /* get cycle state from the origin command trb */ | |
1296 | cycle_state = le32_to_cpu(cmd_trb->generic.field[3]) | |
1297 | & TRB_CYCLE; | |
1298 | ||
1299 | /* modify the command trb to NO OP command */ | |
1300 | cmd_trb->generic.field[0] = 0; | |
1301 | cmd_trb->generic.field[1] = 0; | |
1302 | cmd_trb->generic.field[2] = 0; | |
1303 | cmd_trb->generic.field[3] = cpu_to_le32( | |
1304 | TRB_TYPE(TRB_CMD_NOOP) | cycle_state); | |
1305 | break; | |
1306 | } | |
1307 | } | |
1308 | } | |
1309 | ||
1310 | static void xhci_cancel_cmd_in_cd_list(struct xhci_hcd *xhci) | |
1311 | { | |
1312 | struct xhci_cd *cur_cd, *next_cd; | |
1313 | ||
1314 | if (list_empty(&xhci->cancel_cmd_list)) | |
1315 | return; | |
1316 | ||
1317 | list_for_each_entry_safe(cur_cd, next_cd, | |
1318 | &xhci->cancel_cmd_list, cancel_cmd_list) { | |
1319 | xhci_cmd_to_noop(xhci, cur_cd); | |
1320 | list_del(&cur_cd->cancel_cmd_list); | |
1321 | kfree(cur_cd); | |
1322 | } | |
1323 | } | |
1324 | ||
1325 | /* | |
1326 | * traversing the cancel_cmd_list. If the command descriptor according | |
1327 | * to cmd_trb is found, the function free it and return 1, otherwise | |
1328 | * return 0. | |
1329 | */ | |
1330 | static int xhci_search_cmd_trb_in_cd_list(struct xhci_hcd *xhci, | |
1331 | union xhci_trb *cmd_trb) | |
1332 | { | |
1333 | struct xhci_cd *cur_cd, *next_cd; | |
1334 | ||
1335 | if (list_empty(&xhci->cancel_cmd_list)) | |
1336 | return 0; | |
1337 | ||
1338 | list_for_each_entry_safe(cur_cd, next_cd, | |
1339 | &xhci->cancel_cmd_list, cancel_cmd_list) { | |
1340 | if (cur_cd->cmd_trb == cmd_trb) { | |
1341 | if (cur_cd->command) | |
1342 | xhci_complete_cmd_in_cmd_wait_list(xhci, | |
1343 | cur_cd->command, COMP_CMD_STOP); | |
1344 | list_del(&cur_cd->cancel_cmd_list); | |
1345 | kfree(cur_cd); | |
1346 | return 1; | |
1347 | } | |
1348 | } | |
1349 | ||
1350 | return 0; | |
1351 | } | |
1352 | ||
1353 | /* | |
1354 | * If the cmd_trb_comp_code is COMP_CMD_ABORT, we just check whether the | |
1355 | * trb pointed by the command ring dequeue pointer is the trb we want to | |
1356 | * cancel or not. And if the cmd_trb_comp_code is COMP_CMD_STOP, we will | |
1357 | * traverse the cancel_cmd_list to trun the all of the commands according | |
1358 | * to command descriptor to NO-OP trb. | |
1359 | */ | |
1360 | static int handle_stopped_cmd_ring(struct xhci_hcd *xhci, | |
1361 | int cmd_trb_comp_code) | |
1362 | { | |
1363 | int cur_trb_is_good = 0; | |
1364 | ||
1365 | /* Searching the cmd trb pointed by the command ring dequeue | |
1366 | * pointer in command descriptor list. If it is found, free it. | |
1367 | */ | |
1368 | cur_trb_is_good = xhci_search_cmd_trb_in_cd_list(xhci, | |
1369 | xhci->cmd_ring->dequeue); | |
1370 | ||
1371 | if (cmd_trb_comp_code == COMP_CMD_ABORT) | |
1372 | xhci->cmd_ring_state = CMD_RING_STATE_STOPPED; | |
1373 | else if (cmd_trb_comp_code == COMP_CMD_STOP) { | |
1374 | /* traversing the cancel_cmd_list and canceling | |
1375 | * the command according to command descriptor | |
1376 | */ | |
1377 | xhci_cancel_cmd_in_cd_list(xhci); | |
1378 | ||
1379 | xhci->cmd_ring_state = CMD_RING_STATE_RUNNING; | |
1380 | /* | |
1381 | * ring command ring doorbell again to restart the | |
1382 | * command ring | |
1383 | */ | |
1384 | if (xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue) | |
1385 | xhci_ring_cmd_db(xhci); | |
1386 | } | |
1387 | return cur_trb_is_good; | |
1388 | } | |
1389 | ||
b244b431 XR |
1390 | static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id, |
1391 | u32 cmd_comp_code) | |
1392 | { | |
1393 | if (cmd_comp_code == COMP_SUCCESS) | |
1394 | xhci->slot_id = slot_id; | |
1395 | else | |
1396 | xhci->slot_id = 0; | |
1397 | complete(&xhci->addr_dev); | |
1398 | } | |
1399 | ||
6c02dd14 XR |
1400 | static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id) |
1401 | { | |
1402 | struct xhci_virt_device *virt_dev; | |
1403 | ||
1404 | virt_dev = xhci->devs[slot_id]; | |
1405 | if (!virt_dev) | |
1406 | return; | |
1407 | if (xhci->quirks & XHCI_EP_LIMIT_QUIRK) | |
1408 | /* Delete default control endpoint resources */ | |
1409 | xhci_free_device_endpoint_resources(xhci, virt_dev, true); | |
1410 | xhci_free_virt_device(xhci, slot_id); | |
1411 | } | |
1412 | ||
6ed46d33 XR |
1413 | static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id, |
1414 | struct xhci_event_cmd *event, u32 cmd_comp_code) | |
1415 | { | |
1416 | struct xhci_virt_device *virt_dev; | |
1417 | struct xhci_input_control_ctx *ctrl_ctx; | |
1418 | unsigned int ep_index; | |
1419 | unsigned int ep_state; | |
1420 | u32 add_flags, drop_flags; | |
1421 | ||
1422 | virt_dev = xhci->devs[slot_id]; | |
1423 | if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event)) | |
1424 | return; | |
1425 | /* | |
1426 | * Configure endpoint commands can come from the USB core | |
1427 | * configuration or alt setting changes, or because the HW | |
1428 | * needed an extra configure endpoint command after a reset | |
1429 | * endpoint command or streams were being configured. | |
1430 | * If the command was for a halted endpoint, the xHCI driver | |
1431 | * is not waiting on the configure endpoint command. | |
1432 | */ | |
1433 | ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx); | |
1434 | if (!ctrl_ctx) { | |
1435 | xhci_warn(xhci, "Could not get input context, bad type.\n"); | |
1436 | return; | |
1437 | } | |
1438 | ||
1439 | add_flags = le32_to_cpu(ctrl_ctx->add_flags); | |
1440 | drop_flags = le32_to_cpu(ctrl_ctx->drop_flags); | |
1441 | /* Input ctx add_flags are the endpoint index plus one */ | |
1442 | ep_index = xhci_last_valid_endpoint(add_flags) - 1; | |
1443 | ||
1444 | /* A usb_set_interface() call directly after clearing a halted | |
1445 | * condition may race on this quirky hardware. Not worth | |
1446 | * worrying about, since this is prototype hardware. Not sure | |
1447 | * if this will work for streams, but streams support was | |
1448 | * untested on this prototype. | |
1449 | */ | |
1450 | if (xhci->quirks & XHCI_RESET_EP_QUIRK && | |
1451 | ep_index != (unsigned int) -1 && | |
1452 | add_flags - SLOT_FLAG == drop_flags) { | |
1453 | ep_state = virt_dev->eps[ep_index].ep_state; | |
1454 | if (!(ep_state & EP_HALTED)) | |
1455 | goto bandwidth_change; | |
1456 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, | |
1457 | "Completed config ep cmd - " | |
1458 | "last ep index = %d, state = %d", | |
1459 | ep_index, ep_state); | |
1460 | /* Clear internal halted state and restart ring(s) */ | |
1461 | virt_dev->eps[ep_index].ep_state &= ~EP_HALTED; | |
1462 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); | |
1463 | return; | |
1464 | } | |
1465 | bandwidth_change: | |
1466 | xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, | |
1467 | "Completed config ep cmd"); | |
1468 | virt_dev->cmd_status = cmd_comp_code; | |
1469 | complete(&virt_dev->cmd_completion); | |
1470 | return; | |
1471 | } | |
1472 | ||
07948a8d XR |
1473 | static void xhci_handle_cmd_eval_ctx(struct xhci_hcd *xhci, int slot_id, |
1474 | struct xhci_event_cmd *event, u32 cmd_comp_code) | |
1475 | { | |
1476 | struct xhci_virt_device *virt_dev; | |
1477 | ||
1478 | virt_dev = xhci->devs[slot_id]; | |
1479 | if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event)) | |
1480 | return; | |
1481 | virt_dev->cmd_status = cmd_comp_code; | |
1482 | complete(&virt_dev->cmd_completion); | |
1483 | } | |
1484 | ||
9b3103ac XR |
1485 | static void xhci_handle_cmd_addr_dev(struct xhci_hcd *xhci, int slot_id, |
1486 | u32 cmd_comp_code) | |
1487 | { | |
1488 | xhci->devs[slot_id]->cmd_status = cmd_comp_code; | |
1489 | complete(&xhci->addr_dev); | |
1490 | } | |
1491 | ||
f681321b XR |
1492 | static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id, |
1493 | struct xhci_event_cmd *event) | |
1494 | { | |
1495 | struct xhci_virt_device *virt_dev; | |
1496 | ||
1497 | xhci_dbg(xhci, "Completed reset device command.\n"); | |
1498 | virt_dev = xhci->devs[slot_id]; | |
1499 | if (virt_dev) | |
1500 | handle_cmd_in_cmd_wait_list(xhci, virt_dev, event); | |
1501 | else | |
1502 | xhci_warn(xhci, "Reset device command completion " | |
1503 | "for disabled slot %u\n", slot_id); | |
1504 | } | |
1505 | ||
2c070821 XR |
1506 | static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci, |
1507 | struct xhci_event_cmd *event) | |
1508 | { | |
1509 | if (!(xhci->quirks & XHCI_NEC_HOST)) { | |
1510 | xhci->error_bitmask |= 1 << 6; | |
1511 | return; | |
1512 | } | |
1513 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, | |
1514 | "NEC firmware version %2x.%02x", | |
1515 | NEC_FW_MAJOR(le32_to_cpu(event->status)), | |
1516 | NEC_FW_MINOR(le32_to_cpu(event->status))); | |
1517 | } | |
1518 | ||
7f84eef0 SS |
1519 | static void handle_cmd_completion(struct xhci_hcd *xhci, |
1520 | struct xhci_event_cmd *event) | |
1521 | { | |
28ccd296 | 1522 | int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
7f84eef0 SS |
1523 | u64 cmd_dma; |
1524 | dma_addr_t cmd_dequeue_dma; | |
e7a79a1d | 1525 | u32 cmd_comp_code; |
9124b121 | 1526 | union xhci_trb *cmd_trb; |
b54fc46d | 1527 | u32 cmd_type; |
7f84eef0 | 1528 | |
28ccd296 | 1529 | cmd_dma = le64_to_cpu(event->cmd_trb); |
9124b121 | 1530 | cmd_trb = xhci->cmd_ring->dequeue; |
23e3be11 | 1531 | cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg, |
9124b121 | 1532 | cmd_trb); |
7f84eef0 SS |
1533 | /* Is the command ring deq ptr out of sync with the deq seg ptr? */ |
1534 | if (cmd_dequeue_dma == 0) { | |
1535 | xhci->error_bitmask |= 1 << 4; | |
1536 | return; | |
1537 | } | |
1538 | /* Does the DMA address match our internal dequeue pointer address? */ | |
1539 | if (cmd_dma != (u64) cmd_dequeue_dma) { | |
1540 | xhci->error_bitmask |= 1 << 5; | |
1541 | return; | |
1542 | } | |
b63f4053 | 1543 | |
9124b121 | 1544 | trace_xhci_cmd_completion(cmd_trb, (struct xhci_generic_trb *) event); |
63a23b9a | 1545 | |
e7a79a1d XR |
1546 | cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status)); |
1547 | if (cmd_comp_code == COMP_CMD_ABORT || cmd_comp_code == COMP_CMD_STOP) { | |
b63f4053 EF |
1548 | /* If the return value is 0, we think the trb pointed by |
1549 | * command ring dequeue pointer is a good trb. The good | |
1550 | * trb means we don't want to cancel the trb, but it have | |
1551 | * been stopped by host. So we should handle it normally. | |
1552 | * Otherwise, driver should invoke inc_deq() and return. | |
1553 | */ | |
e7a79a1d | 1554 | if (handle_stopped_cmd_ring(xhci, cmd_comp_code)) { |
b63f4053 EF |
1555 | inc_deq(xhci, xhci->cmd_ring); |
1556 | return; | |
1557 | } | |
284d2055 MN |
1558 | /* There is no command to handle if we get a stop event when the |
1559 | * command ring is empty, event->cmd_trb points to the next | |
1560 | * unset command | |
1561 | */ | |
1562 | if (xhci->cmd_ring->dequeue == xhci->cmd_ring->enqueue) | |
1563 | return; | |
b63f4053 EF |
1564 | } |
1565 | ||
b54fc46d XR |
1566 | cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3])); |
1567 | switch (cmd_type) { | |
1568 | case TRB_ENABLE_SLOT: | |
e7a79a1d | 1569 | xhci_handle_cmd_enable_slot(xhci, slot_id, cmd_comp_code); |
3ffbba95 | 1570 | break; |
b54fc46d | 1571 | case TRB_DISABLE_SLOT: |
6c02dd14 | 1572 | xhci_handle_cmd_disable_slot(xhci, slot_id); |
3ffbba95 | 1573 | break; |
b54fc46d | 1574 | case TRB_CONFIG_EP: |
e7a79a1d | 1575 | xhci_handle_cmd_config_ep(xhci, slot_id, event, cmd_comp_code); |
f94e0186 | 1576 | break; |
b54fc46d | 1577 | case TRB_EVAL_CONTEXT: |
e7a79a1d | 1578 | xhci_handle_cmd_eval_ctx(xhci, slot_id, event, cmd_comp_code); |
2d3f1fac | 1579 | break; |
b54fc46d | 1580 | case TRB_ADDR_DEV: |
e7a79a1d | 1581 | xhci_handle_cmd_addr_dev(xhci, slot_id, cmd_comp_code); |
3ffbba95 | 1582 | break; |
b54fc46d | 1583 | case TRB_STOP_RING: |
b8200c94 XR |
1584 | WARN_ON(slot_id != TRB_TO_SLOT_ID( |
1585 | le32_to_cpu(cmd_trb->generic.field[3]))); | |
1586 | xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb, event); | |
ae636747 | 1587 | break; |
b54fc46d | 1588 | case TRB_SET_DEQ: |
b8200c94 XR |
1589 | WARN_ON(slot_id != TRB_TO_SLOT_ID( |
1590 | le32_to_cpu(cmd_trb->generic.field[3]))); | |
c69a0597 | 1591 | xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code); |
ae636747 | 1592 | break; |
b54fc46d | 1593 | case TRB_CMD_NOOP: |
7f84eef0 | 1594 | break; |
b54fc46d | 1595 | case TRB_RESET_EP: |
b8200c94 XR |
1596 | WARN_ON(slot_id != TRB_TO_SLOT_ID( |
1597 | le32_to_cpu(cmd_trb->generic.field[3]))); | |
c69a0597 | 1598 | xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code); |
a1587d97 | 1599 | break; |
b54fc46d | 1600 | case TRB_RESET_DEV: |
20e7acb1 | 1601 | WARN_ON(slot_id != TRB_TO_SLOT_ID( |
9124b121 | 1602 | le32_to_cpu(cmd_trb->generic.field[3]))); |
f681321b | 1603 | xhci_handle_cmd_reset_dev(xhci, slot_id, event); |
2a8f82c4 | 1604 | break; |
b54fc46d | 1605 | case TRB_NEC_GET_FW: |
2c070821 | 1606 | xhci_handle_cmd_nec_get_fw(xhci, event); |
0238634d | 1607 | break; |
7f84eef0 SS |
1608 | default: |
1609 | /* Skip over unknown commands on the event ring */ | |
1610 | xhci->error_bitmask |= 1 << 6; | |
1611 | break; | |
1612 | } | |
3b72fca0 | 1613 | inc_deq(xhci, xhci->cmd_ring); |
7f84eef0 SS |
1614 | } |
1615 | ||
0238634d SS |
1616 | static void handle_vendor_event(struct xhci_hcd *xhci, |
1617 | union xhci_trb *event) | |
1618 | { | |
1619 | u32 trb_type; | |
1620 | ||
28ccd296 | 1621 | trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3])); |
0238634d SS |
1622 | xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type); |
1623 | if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST)) | |
1624 | handle_cmd_completion(xhci, &event->event_cmd); | |
1625 | } | |
1626 | ||
f6ff0ac8 SS |
1627 | /* @port_id: the one-based port ID from the hardware (indexed from array of all |
1628 | * port registers -- USB 3.0 and USB 2.0). | |
1629 | * | |
1630 | * Returns a zero-based port number, which is suitable for indexing into each of | |
1631 | * the split roothubs' port arrays and bus state arrays. | |
d0cd5d48 | 1632 | * Add one to it in order to call xhci_find_slot_id_by_port. |
f6ff0ac8 SS |
1633 | */ |
1634 | static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd, | |
1635 | struct xhci_hcd *xhci, u32 port_id) | |
1636 | { | |
1637 | unsigned int i; | |
1638 | unsigned int num_similar_speed_ports = 0; | |
1639 | ||
1640 | /* port_id from the hardware is 1-based, but port_array[], usb3_ports[], | |
1641 | * and usb2_ports are 0-based indexes. Count the number of similar | |
1642 | * speed ports, up to 1 port before this port. | |
1643 | */ | |
1644 | for (i = 0; i < (port_id - 1); i++) { | |
1645 | u8 port_speed = xhci->port_array[i]; | |
1646 | ||
1647 | /* | |
1648 | * Skip ports that don't have known speeds, or have duplicate | |
1649 | * Extended Capabilities port speed entries. | |
1650 | */ | |
22e04870 | 1651 | if (port_speed == 0 || port_speed == DUPLICATE_ENTRY) |
f6ff0ac8 SS |
1652 | continue; |
1653 | ||
1654 | /* | |
1655 | * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and | |
1656 | * 1.1 ports are under the USB 2.0 hub. If the port speed | |
1657 | * matches the device speed, it's a similar speed port. | |
1658 | */ | |
1659 | if ((port_speed == 0x03) == (hcd->speed == HCD_USB3)) | |
1660 | num_similar_speed_ports++; | |
1661 | } | |
1662 | return num_similar_speed_ports; | |
1663 | } | |
1664 | ||
623bef9e SS |
1665 | static void handle_device_notification(struct xhci_hcd *xhci, |
1666 | union xhci_trb *event) | |
1667 | { | |
1668 | u32 slot_id; | |
4ee823b8 | 1669 | struct usb_device *udev; |
623bef9e | 1670 | |
7e76ad43 | 1671 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3])); |
4ee823b8 | 1672 | if (!xhci->devs[slot_id]) { |
623bef9e SS |
1673 | xhci_warn(xhci, "Device Notification event for " |
1674 | "unused slot %u\n", slot_id); | |
4ee823b8 SS |
1675 | return; |
1676 | } | |
1677 | ||
1678 | xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n", | |
1679 | slot_id); | |
1680 | udev = xhci->devs[slot_id]->udev; | |
1681 | if (udev && udev->parent) | |
1682 | usb_wakeup_notification(udev->parent, udev->portnum); | |
623bef9e SS |
1683 | } |
1684 | ||
0f2a7930 SS |
1685 | static void handle_port_status(struct xhci_hcd *xhci, |
1686 | union xhci_trb *event) | |
1687 | { | |
f6ff0ac8 | 1688 | struct usb_hcd *hcd; |
0f2a7930 | 1689 | u32 port_id; |
56192531 | 1690 | u32 temp, temp1; |
518e848e | 1691 | int max_ports; |
56192531 | 1692 | int slot_id; |
5308a91b | 1693 | unsigned int faked_port_index; |
f6ff0ac8 | 1694 | u8 major_revision; |
20b67cf5 | 1695 | struct xhci_bus_state *bus_state; |
28ccd296 | 1696 | __le32 __iomem **port_array; |
386139d7 | 1697 | bool bogus_port_status = false; |
0f2a7930 SS |
1698 | |
1699 | /* Port status change events always have a successful completion code */ | |
28ccd296 | 1700 | if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) { |
0f2a7930 SS |
1701 | xhci_warn(xhci, "WARN: xHC returned failed port status event\n"); |
1702 | xhci->error_bitmask |= 1 << 8; | |
1703 | } | |
28ccd296 | 1704 | port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0])); |
0f2a7930 SS |
1705 | xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id); |
1706 | ||
518e848e SS |
1707 | max_ports = HCS_MAX_PORTS(xhci->hcs_params1); |
1708 | if ((port_id <= 0) || (port_id > max_ports)) { | |
56192531 | 1709 | xhci_warn(xhci, "Invalid port id %d\n", port_id); |
09ce0c0c PC |
1710 | inc_deq(xhci, xhci->event_ring); |
1711 | return; | |
56192531 AX |
1712 | } |
1713 | ||
f6ff0ac8 SS |
1714 | /* Figure out which usb_hcd this port is attached to: |
1715 | * is it a USB 3.0 port or a USB 2.0/1.1 port? | |
1716 | */ | |
1717 | major_revision = xhci->port_array[port_id - 1]; | |
09ce0c0c PC |
1718 | |
1719 | /* Find the right roothub. */ | |
1720 | hcd = xhci_to_hcd(xhci); | |
1721 | if ((major_revision == 0x03) != (hcd->speed == HCD_USB3)) | |
1722 | hcd = xhci->shared_hcd; | |
1723 | ||
f6ff0ac8 SS |
1724 | if (major_revision == 0) { |
1725 | xhci_warn(xhci, "Event for port %u not in " | |
1726 | "Extended Capabilities, ignoring.\n", | |
1727 | port_id); | |
386139d7 | 1728 | bogus_port_status = true; |
f6ff0ac8 | 1729 | goto cleanup; |
5308a91b | 1730 | } |
22e04870 | 1731 | if (major_revision == DUPLICATE_ENTRY) { |
f6ff0ac8 SS |
1732 | xhci_warn(xhci, "Event for port %u duplicated in" |
1733 | "Extended Capabilities, ignoring.\n", | |
1734 | port_id); | |
386139d7 | 1735 | bogus_port_status = true; |
f6ff0ac8 SS |
1736 | goto cleanup; |
1737 | } | |
1738 | ||
1739 | /* | |
1740 | * Hardware port IDs reported by a Port Status Change Event include USB | |
1741 | * 3.0 and USB 2.0 ports. We want to check if the port has reported a | |
1742 | * resume event, but we first need to translate the hardware port ID | |
1743 | * into the index into the ports on the correct split roothub, and the | |
1744 | * correct bus_state structure. | |
1745 | */ | |
f6ff0ac8 SS |
1746 | bus_state = &xhci->bus_state[hcd_index(hcd)]; |
1747 | if (hcd->speed == HCD_USB3) | |
1748 | port_array = xhci->usb3_ports; | |
1749 | else | |
1750 | port_array = xhci->usb2_ports; | |
1751 | /* Find the faked port hub number */ | |
1752 | faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci, | |
1753 | port_id); | |
5308a91b | 1754 | |
b0ba9720 | 1755 | temp = readl(port_array[faked_port_index]); |
7111ebc9 | 1756 | if (hcd->state == HC_STATE_SUSPENDED) { |
56192531 AX |
1757 | xhci_dbg(xhci, "resume root hub\n"); |
1758 | usb_hcd_resume_root_hub(hcd); | |
1759 | } | |
1760 | ||
1761 | if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) { | |
1762 | xhci_dbg(xhci, "port resume event for port %d\n", port_id); | |
1763 | ||
b0ba9720 | 1764 | temp1 = readl(&xhci->op_regs->command); |
56192531 AX |
1765 | if (!(temp1 & CMD_RUN)) { |
1766 | xhci_warn(xhci, "xHC is not running.\n"); | |
1767 | goto cleanup; | |
1768 | } | |
1769 | ||
1770 | if (DEV_SUPERSPEED(temp)) { | |
d93814cf | 1771 | xhci_dbg(xhci, "remote wake SS port %d\n", port_id); |
4ee823b8 SS |
1772 | /* Set a flag to say the port signaled remote wakeup, |
1773 | * so we can tell the difference between the end of | |
1774 | * device and host initiated resume. | |
1775 | */ | |
1776 | bus_state->port_remote_wakeup |= 1 << faked_port_index; | |
d93814cf SS |
1777 | xhci_test_and_clear_bit(xhci, port_array, |
1778 | faked_port_index, PORT_PLC); | |
c9682dff AX |
1779 | xhci_set_link_state(xhci, port_array, faked_port_index, |
1780 | XDEV_U0); | |
d93814cf SS |
1781 | /* Need to wait until the next link state change |
1782 | * indicates the device is actually in U0. | |
1783 | */ | |
1784 | bogus_port_status = true; | |
1785 | goto cleanup; | |
56192531 AX |
1786 | } else { |
1787 | xhci_dbg(xhci, "resume HS port %d\n", port_id); | |
f6ff0ac8 | 1788 | bus_state->resume_done[faked_port_index] = jiffies + |
56192531 | 1789 | msecs_to_jiffies(20); |
f370b996 | 1790 | set_bit(faked_port_index, &bus_state->resuming_ports); |
56192531 | 1791 | mod_timer(&hcd->rh_timer, |
f6ff0ac8 | 1792 | bus_state->resume_done[faked_port_index]); |
56192531 AX |
1793 | /* Do the rest in GetPortStatus */ |
1794 | } | |
1795 | } | |
d93814cf SS |
1796 | |
1797 | if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_U0 && | |
1798 | DEV_SUPERSPEED(temp)) { | |
1799 | xhci_dbg(xhci, "resume SS port %d finished\n", port_id); | |
4ee823b8 SS |
1800 | /* We've just brought the device into U0 through either the |
1801 | * Resume state after a device remote wakeup, or through the | |
1802 | * U3Exit state after a host-initiated resume. If it's a device | |
1803 | * initiated remote wake, don't pass up the link state change, | |
1804 | * so the roothub behavior is consistent with external | |
1805 | * USB 3.0 hub behavior. | |
1806 | */ | |
d93814cf SS |
1807 | slot_id = xhci_find_slot_id_by_port(hcd, xhci, |
1808 | faked_port_index + 1); | |
1809 | if (slot_id && xhci->devs[slot_id]) | |
1810 | xhci_ring_device(xhci, slot_id); | |
ba7b5c22 | 1811 | if (bus_state->port_remote_wakeup & (1 << faked_port_index)) { |
4ee823b8 SS |
1812 | bus_state->port_remote_wakeup &= |
1813 | ~(1 << faked_port_index); | |
1814 | xhci_test_and_clear_bit(xhci, port_array, | |
1815 | faked_port_index, PORT_PLC); | |
1816 | usb_wakeup_notification(hcd->self.root_hub, | |
1817 | faked_port_index + 1); | |
1818 | bogus_port_status = true; | |
1819 | goto cleanup; | |
1820 | } | |
d93814cf | 1821 | } |
56192531 | 1822 | |
8b3d4570 SS |
1823 | /* |
1824 | * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or | |
1825 | * RExit to a disconnect state). If so, let the the driver know it's | |
1826 | * out of the RExit state. | |
1827 | */ | |
1828 | if (!DEV_SUPERSPEED(temp) && | |
1829 | test_and_clear_bit(faked_port_index, | |
1830 | &bus_state->rexit_ports)) { | |
1831 | complete(&bus_state->rexit_done[faked_port_index]); | |
1832 | bogus_port_status = true; | |
1833 | goto cleanup; | |
1834 | } | |
1835 | ||
6fd45621 AX |
1836 | if (hcd->speed != HCD_USB3) |
1837 | xhci_test_and_clear_bit(xhci, port_array, faked_port_index, | |
1838 | PORT_PLC); | |
1839 | ||
56192531 | 1840 | cleanup: |
0f2a7930 | 1841 | /* Update event ring dequeue pointer before dropping the lock */ |
3b72fca0 | 1842 | inc_deq(xhci, xhci->event_ring); |
0f2a7930 | 1843 | |
386139d7 SS |
1844 | /* Don't make the USB core poll the roothub if we got a bad port status |
1845 | * change event. Besides, at that point we can't tell which roothub | |
1846 | * (USB 2.0 or USB 3.0) to kick. | |
1847 | */ | |
1848 | if (bogus_port_status) | |
1849 | return; | |
1850 | ||
c52804a4 SS |
1851 | /* |
1852 | * xHCI port-status-change events occur when the "or" of all the | |
1853 | * status-change bits in the portsc register changes from 0 to 1. | |
1854 | * New status changes won't cause an event if any other change | |
1855 | * bits are still set. When an event occurs, switch over to | |
1856 | * polling to avoid losing status changes. | |
1857 | */ | |
1858 | xhci_dbg(xhci, "%s: starting port polling.\n", __func__); | |
1859 | set_bit(HCD_FLAG_POLL_RH, &hcd->flags); | |
0f2a7930 SS |
1860 | spin_unlock(&xhci->lock); |
1861 | /* Pass this up to the core */ | |
f6ff0ac8 | 1862 | usb_hcd_poll_rh_status(hcd); |
0f2a7930 SS |
1863 | spin_lock(&xhci->lock); |
1864 | } | |
1865 | ||
d0e96f5a SS |
1866 | /* |
1867 | * This TD is defined by the TRBs starting at start_trb in start_seg and ending | |
1868 | * at end_trb, which may be in another segment. If the suspect DMA address is a | |
1869 | * TRB in this TD, this function returns that TRB's segment. Otherwise it | |
1870 | * returns 0. | |
1871 | */ | |
6648f29d | 1872 | struct xhci_segment *trb_in_td(struct xhci_segment *start_seg, |
d0e96f5a SS |
1873 | union xhci_trb *start_trb, |
1874 | union xhci_trb *end_trb, | |
1875 | dma_addr_t suspect_dma) | |
1876 | { | |
1877 | dma_addr_t start_dma; | |
1878 | dma_addr_t end_seg_dma; | |
1879 | dma_addr_t end_trb_dma; | |
1880 | struct xhci_segment *cur_seg; | |
1881 | ||
23e3be11 | 1882 | start_dma = xhci_trb_virt_to_dma(start_seg, start_trb); |
d0e96f5a SS |
1883 | cur_seg = start_seg; |
1884 | ||
1885 | do { | |
2fa88daa | 1886 | if (start_dma == 0) |
326b4810 | 1887 | return NULL; |
ae636747 | 1888 | /* We may get an event for a Link TRB in the middle of a TD */ |
23e3be11 | 1889 | end_seg_dma = xhci_trb_virt_to_dma(cur_seg, |
2fa88daa | 1890 | &cur_seg->trbs[TRBS_PER_SEGMENT - 1]); |
d0e96f5a | 1891 | /* If the end TRB isn't in this segment, this is set to 0 */ |
23e3be11 | 1892 | end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb); |
d0e96f5a SS |
1893 | |
1894 | if (end_trb_dma > 0) { | |
1895 | /* The end TRB is in this segment, so suspect should be here */ | |
1896 | if (start_dma <= end_trb_dma) { | |
1897 | if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma) | |
1898 | return cur_seg; | |
1899 | } else { | |
1900 | /* Case for one segment with | |
1901 | * a TD wrapped around to the top | |
1902 | */ | |
1903 | if ((suspect_dma >= start_dma && | |
1904 | suspect_dma <= end_seg_dma) || | |
1905 | (suspect_dma >= cur_seg->dma && | |
1906 | suspect_dma <= end_trb_dma)) | |
1907 | return cur_seg; | |
1908 | } | |
326b4810 | 1909 | return NULL; |
d0e96f5a SS |
1910 | } else { |
1911 | /* Might still be somewhere in this segment */ | |
1912 | if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma) | |
1913 | return cur_seg; | |
1914 | } | |
1915 | cur_seg = cur_seg->next; | |
23e3be11 | 1916 | start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]); |
2fa88daa | 1917 | } while (cur_seg != start_seg); |
d0e96f5a | 1918 | |
326b4810 | 1919 | return NULL; |
d0e96f5a SS |
1920 | } |
1921 | ||
bcef3fd5 SS |
1922 | static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci, |
1923 | unsigned int slot_id, unsigned int ep_index, | |
e9df17eb | 1924 | unsigned int stream_id, |
bcef3fd5 SS |
1925 | struct xhci_td *td, union xhci_trb *event_trb) |
1926 | { | |
1927 | struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index]; | |
1928 | ep->ep_state |= EP_HALTED; | |
1929 | ep->stopped_td = td; | |
1930 | ep->stopped_trb = event_trb; | |
e9df17eb | 1931 | ep->stopped_stream = stream_id; |
1624ae1c | 1932 | |
bcef3fd5 SS |
1933 | xhci_queue_reset_ep(xhci, slot_id, ep_index); |
1934 | xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index); | |
1624ae1c SS |
1935 | |
1936 | ep->stopped_td = NULL; | |
1937 | ep->stopped_trb = NULL; | |
5e5cf6fc | 1938 | ep->stopped_stream = 0; |
1624ae1c | 1939 | |
bcef3fd5 SS |
1940 | xhci_ring_cmd_db(xhci); |
1941 | } | |
1942 | ||
1943 | /* Check if an error has halted the endpoint ring. The class driver will | |
1944 | * cleanup the halt for a non-default control endpoint if we indicate a stall. | |
1945 | * However, a babble and other errors also halt the endpoint ring, and the class | |
1946 | * driver won't clear the halt in that case, so we need to issue a Set Transfer | |
1947 | * Ring Dequeue Pointer command manually. | |
1948 | */ | |
1949 | static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci, | |
1950 | struct xhci_ep_ctx *ep_ctx, | |
1951 | unsigned int trb_comp_code) | |
1952 | { | |
1953 | /* TRB completion codes that may require a manual halt cleanup */ | |
1954 | if (trb_comp_code == COMP_TX_ERR || | |
1955 | trb_comp_code == COMP_BABBLE || | |
1956 | trb_comp_code == COMP_SPLIT_ERR) | |
1957 | /* The 0.96 spec says a babbling control endpoint | |
1958 | * is not halted. The 0.96 spec says it is. Some HW | |
1959 | * claims to be 0.95 compliant, but it halts the control | |
1960 | * endpoint anyway. Check if a babble halted the | |
1961 | * endpoint. | |
1962 | */ | |
f5960b69 ME |
1963 | if ((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) == |
1964 | cpu_to_le32(EP_STATE_HALTED)) | |
bcef3fd5 SS |
1965 | return 1; |
1966 | ||
1967 | return 0; | |
1968 | } | |
1969 | ||
b45b5069 SS |
1970 | int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code) |
1971 | { | |
1972 | if (trb_comp_code >= 224 && trb_comp_code <= 255) { | |
1973 | /* Vendor defined "informational" completion code, | |
1974 | * treat as not-an-error. | |
1975 | */ | |
1976 | xhci_dbg(xhci, "Vendor defined info completion code %u\n", | |
1977 | trb_comp_code); | |
1978 | xhci_dbg(xhci, "Treating code as success.\n"); | |
1979 | return 1; | |
1980 | } | |
1981 | return 0; | |
1982 | } | |
1983 | ||
4422da61 AX |
1984 | /* |
1985 | * Finish the td processing, remove the td from td list; | |
1986 | * Return 1 if the urb can be given back. | |
1987 | */ | |
1988 | static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td, | |
1989 | union xhci_trb *event_trb, struct xhci_transfer_event *event, | |
1990 | struct xhci_virt_ep *ep, int *status, bool skip) | |
1991 | { | |
1992 | struct xhci_virt_device *xdev; | |
1993 | struct xhci_ring *ep_ring; | |
1994 | unsigned int slot_id; | |
1995 | int ep_index; | |
1996 | struct urb *urb = NULL; | |
1997 | struct xhci_ep_ctx *ep_ctx; | |
1998 | int ret = 0; | |
8e51adcc | 1999 | struct urb_priv *urb_priv; |
4422da61 AX |
2000 | u32 trb_comp_code; |
2001 | ||
28ccd296 | 2002 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
4422da61 | 2003 | xdev = xhci->devs[slot_id]; |
28ccd296 ME |
2004 | ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1; |
2005 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); | |
4422da61 | 2006 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
28ccd296 | 2007 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); |
4422da61 AX |
2008 | |
2009 | if (skip) | |
2010 | goto td_cleanup; | |
2011 | ||
2012 | if (trb_comp_code == COMP_STOP_INVAL || | |
2013 | trb_comp_code == COMP_STOP) { | |
2014 | /* The Endpoint Stop Command completion will take care of any | |
2015 | * stopped TDs. A stopped TD may be restarted, so don't update | |
2016 | * the ring dequeue pointer or take this TD off any lists yet. | |
2017 | */ | |
2018 | ep->stopped_td = td; | |
2019 | ep->stopped_trb = event_trb; | |
2020 | return 0; | |
2021 | } else { | |
2022 | if (trb_comp_code == COMP_STALL) { | |
2023 | /* The transfer is completed from the driver's | |
2024 | * perspective, but we need to issue a set dequeue | |
2025 | * command for this stalled endpoint to move the dequeue | |
2026 | * pointer past the TD. We can't do that here because | |
2027 | * the halt condition must be cleared first. Let the | |
2028 | * USB class driver clear the stall later. | |
2029 | */ | |
2030 | ep->stopped_td = td; | |
2031 | ep->stopped_trb = event_trb; | |
2032 | ep->stopped_stream = ep_ring->stream_id; | |
2033 | } else if (xhci_requires_manual_halt_cleanup(xhci, | |
2034 | ep_ctx, trb_comp_code)) { | |
2035 | /* Other types of errors halt the endpoint, but the | |
2036 | * class driver doesn't call usb_reset_endpoint() unless | |
2037 | * the error is -EPIPE. Clear the halted status in the | |
2038 | * xHCI hardware manually. | |
2039 | */ | |
2040 | xhci_cleanup_halted_endpoint(xhci, | |
2041 | slot_id, ep_index, ep_ring->stream_id, | |
2042 | td, event_trb); | |
2043 | } else { | |
2044 | /* Update ring dequeue pointer */ | |
2045 | while (ep_ring->dequeue != td->last_trb) | |
3b72fca0 AX |
2046 | inc_deq(xhci, ep_ring); |
2047 | inc_deq(xhci, ep_ring); | |
4422da61 AX |
2048 | } |
2049 | ||
2050 | td_cleanup: | |
2051 | /* Clean up the endpoint's TD list */ | |
2052 | urb = td->urb; | |
8e51adcc | 2053 | urb_priv = urb->hcpriv; |
4422da61 AX |
2054 | |
2055 | /* Do one last check of the actual transfer length. | |
2056 | * If the host controller said we transferred more data than | |
2057 | * the buffer length, urb->actual_length will be a very big | |
2058 | * number (since it's unsigned). Play it safe and say we didn't | |
2059 | * transfer anything. | |
2060 | */ | |
2061 | if (urb->actual_length > urb->transfer_buffer_length) { | |
2062 | xhci_warn(xhci, "URB transfer length is wrong, " | |
2063 | "xHC issue? req. len = %u, " | |
2064 | "act. len = %u\n", | |
2065 | urb->transfer_buffer_length, | |
2066 | urb->actual_length); | |
2067 | urb->actual_length = 0; | |
2068 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) | |
2069 | *status = -EREMOTEIO; | |
2070 | else | |
2071 | *status = 0; | |
2072 | } | |
585df1d9 | 2073 | list_del_init(&td->td_list); |
4422da61 AX |
2074 | /* Was this TD slated to be cancelled but completed anyway? */ |
2075 | if (!list_empty(&td->cancelled_td_list)) | |
585df1d9 | 2076 | list_del_init(&td->cancelled_td_list); |
4422da61 | 2077 | |
8e51adcc AX |
2078 | urb_priv->td_cnt++; |
2079 | /* Giveback the urb when all the tds are completed */ | |
c41136b0 | 2080 | if (urb_priv->td_cnt == urb_priv->length) { |
8e51adcc | 2081 | ret = 1; |
c41136b0 AX |
2082 | if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { |
2083 | xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--; | |
2084 | if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs | |
2085 | == 0) { | |
2086 | if (xhci->quirks & XHCI_AMD_PLL_FIX) | |
2087 | usb_amd_quirk_pll_enable(); | |
2088 | } | |
2089 | } | |
2090 | } | |
4422da61 AX |
2091 | } |
2092 | ||
2093 | return ret; | |
2094 | } | |
2095 | ||
8af56be1 AX |
2096 | /* |
2097 | * Process control tds, update urb status and actual_length. | |
2098 | */ | |
2099 | static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td, | |
2100 | union xhci_trb *event_trb, struct xhci_transfer_event *event, | |
2101 | struct xhci_virt_ep *ep, int *status) | |
2102 | { | |
2103 | struct xhci_virt_device *xdev; | |
2104 | struct xhci_ring *ep_ring; | |
2105 | unsigned int slot_id; | |
2106 | int ep_index; | |
2107 | struct xhci_ep_ctx *ep_ctx; | |
2108 | u32 trb_comp_code; | |
2109 | ||
28ccd296 | 2110 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
8af56be1 | 2111 | xdev = xhci->devs[slot_id]; |
28ccd296 ME |
2112 | ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1; |
2113 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); | |
8af56be1 | 2114 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
28ccd296 | 2115 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); |
8af56be1 | 2116 | |
8af56be1 AX |
2117 | switch (trb_comp_code) { |
2118 | case COMP_SUCCESS: | |
2119 | if (event_trb == ep_ring->dequeue) { | |
2120 | xhci_warn(xhci, "WARN: Success on ctrl setup TRB " | |
2121 | "without IOC set??\n"); | |
2122 | *status = -ESHUTDOWN; | |
2123 | } else if (event_trb != td->last_trb) { | |
2124 | xhci_warn(xhci, "WARN: Success on ctrl data TRB " | |
2125 | "without IOC set??\n"); | |
2126 | *status = -ESHUTDOWN; | |
2127 | } else { | |
8af56be1 AX |
2128 | *status = 0; |
2129 | } | |
2130 | break; | |
2131 | case COMP_SHORT_TX: | |
8af56be1 AX |
2132 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) |
2133 | *status = -EREMOTEIO; | |
2134 | else | |
2135 | *status = 0; | |
2136 | break; | |
3abeca99 SS |
2137 | case COMP_STOP_INVAL: |
2138 | case COMP_STOP: | |
2139 | return finish_td(xhci, td, event_trb, event, ep, status, false); | |
8af56be1 AX |
2140 | default: |
2141 | if (!xhci_requires_manual_halt_cleanup(xhci, | |
2142 | ep_ctx, trb_comp_code)) | |
2143 | break; | |
2144 | xhci_dbg(xhci, "TRB error code %u, " | |
2145 | "halted endpoint index = %u\n", | |
2146 | trb_comp_code, ep_index); | |
2147 | /* else fall through */ | |
2148 | case COMP_STALL: | |
2149 | /* Did we transfer part of the data (middle) phase? */ | |
2150 | if (event_trb != ep_ring->dequeue && | |
2151 | event_trb != td->last_trb) | |
2152 | td->urb->actual_length = | |
1c11a172 VG |
2153 | td->urb->transfer_buffer_length - |
2154 | EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); | |
8af56be1 AX |
2155 | else |
2156 | td->urb->actual_length = 0; | |
2157 | ||
2158 | xhci_cleanup_halted_endpoint(xhci, | |
2159 | slot_id, ep_index, 0, td, event_trb); | |
2160 | return finish_td(xhci, td, event_trb, event, ep, status, true); | |
2161 | } | |
2162 | /* | |
2163 | * Did we transfer any data, despite the errors that might have | |
2164 | * happened? I.e. did we get past the setup stage? | |
2165 | */ | |
2166 | if (event_trb != ep_ring->dequeue) { | |
2167 | /* The event was for the status stage */ | |
2168 | if (event_trb == td->last_trb) { | |
2169 | if (td->urb->actual_length != 0) { | |
2170 | /* Don't overwrite a previously set error code | |
2171 | */ | |
2172 | if ((*status == -EINPROGRESS || *status == 0) && | |
2173 | (td->urb->transfer_flags | |
2174 | & URB_SHORT_NOT_OK)) | |
2175 | /* Did we already see a short data | |
2176 | * stage? */ | |
2177 | *status = -EREMOTEIO; | |
2178 | } else { | |
2179 | td->urb->actual_length = | |
2180 | td->urb->transfer_buffer_length; | |
2181 | } | |
2182 | } else { | |
2183 | /* Maybe the event was for the data stage? */ | |
3abeca99 SS |
2184 | td->urb->actual_length = |
2185 | td->urb->transfer_buffer_length - | |
1c11a172 | 2186 | EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); |
3abeca99 SS |
2187 | xhci_dbg(xhci, "Waiting for status " |
2188 | "stage event\n"); | |
2189 | return 0; | |
8af56be1 AX |
2190 | } |
2191 | } | |
2192 | ||
2193 | return finish_td(xhci, td, event_trb, event, ep, status, false); | |
2194 | } | |
2195 | ||
04e51901 AX |
2196 | /* |
2197 | * Process isochronous tds, update urb packet status and actual_length. | |
2198 | */ | |
2199 | static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td, | |
2200 | union xhci_trb *event_trb, struct xhci_transfer_event *event, | |
2201 | struct xhci_virt_ep *ep, int *status) | |
2202 | { | |
2203 | struct xhci_ring *ep_ring; | |
2204 | struct urb_priv *urb_priv; | |
2205 | int idx; | |
2206 | int len = 0; | |
04e51901 AX |
2207 | union xhci_trb *cur_trb; |
2208 | struct xhci_segment *cur_seg; | |
926008c9 | 2209 | struct usb_iso_packet_descriptor *frame; |
04e51901 | 2210 | u32 trb_comp_code; |
926008c9 | 2211 | bool skip_td = false; |
04e51901 | 2212 | |
28ccd296 ME |
2213 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); |
2214 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); | |
04e51901 AX |
2215 | urb_priv = td->urb->hcpriv; |
2216 | idx = urb_priv->td_cnt; | |
926008c9 | 2217 | frame = &td->urb->iso_frame_desc[idx]; |
04e51901 | 2218 | |
926008c9 DT |
2219 | /* handle completion code */ |
2220 | switch (trb_comp_code) { | |
2221 | case COMP_SUCCESS: | |
1c11a172 | 2222 | if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) { |
1530bbc6 SS |
2223 | frame->status = 0; |
2224 | break; | |
2225 | } | |
2226 | if ((xhci->quirks & XHCI_TRUST_TX_LENGTH)) | |
2227 | trb_comp_code = COMP_SHORT_TX; | |
926008c9 DT |
2228 | case COMP_SHORT_TX: |
2229 | frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ? | |
2230 | -EREMOTEIO : 0; | |
2231 | break; | |
2232 | case COMP_BW_OVER: | |
2233 | frame->status = -ECOMM; | |
2234 | skip_td = true; | |
2235 | break; | |
2236 | case COMP_BUFF_OVER: | |
2237 | case COMP_BABBLE: | |
2238 | frame->status = -EOVERFLOW; | |
2239 | skip_td = true; | |
2240 | break; | |
f6ba6fe2 | 2241 | case COMP_DEV_ERR: |
926008c9 | 2242 | case COMP_STALL: |
9c745995 | 2243 | case COMP_TX_ERR: |
926008c9 DT |
2244 | frame->status = -EPROTO; |
2245 | skip_td = true; | |
2246 | break; | |
2247 | case COMP_STOP: | |
2248 | case COMP_STOP_INVAL: | |
2249 | break; | |
2250 | default: | |
2251 | frame->status = -1; | |
2252 | break; | |
04e51901 AX |
2253 | } |
2254 | ||
926008c9 DT |
2255 | if (trb_comp_code == COMP_SUCCESS || skip_td) { |
2256 | frame->actual_length = frame->length; | |
2257 | td->urb->actual_length += frame->length; | |
04e51901 AX |
2258 | } else { |
2259 | for (cur_trb = ep_ring->dequeue, | |
2260 | cur_seg = ep_ring->deq_seg; cur_trb != event_trb; | |
2261 | next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) { | |
f5960b69 ME |
2262 | if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) && |
2263 | !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) | |
28ccd296 | 2264 | len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])); |
04e51901 | 2265 | } |
28ccd296 | 2266 | len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) - |
1c11a172 | 2267 | EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); |
04e51901 AX |
2268 | |
2269 | if (trb_comp_code != COMP_STOP_INVAL) { | |
926008c9 | 2270 | frame->actual_length = len; |
04e51901 AX |
2271 | td->urb->actual_length += len; |
2272 | } | |
2273 | } | |
2274 | ||
04e51901 AX |
2275 | return finish_td(xhci, td, event_trb, event, ep, status, false); |
2276 | } | |
2277 | ||
926008c9 DT |
2278 | static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td, |
2279 | struct xhci_transfer_event *event, | |
2280 | struct xhci_virt_ep *ep, int *status) | |
2281 | { | |
2282 | struct xhci_ring *ep_ring; | |
2283 | struct urb_priv *urb_priv; | |
2284 | struct usb_iso_packet_descriptor *frame; | |
2285 | int idx; | |
2286 | ||
f6975314 | 2287 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); |
926008c9 DT |
2288 | urb_priv = td->urb->hcpriv; |
2289 | idx = urb_priv->td_cnt; | |
2290 | frame = &td->urb->iso_frame_desc[idx]; | |
2291 | ||
b3df3f9c | 2292 | /* The transfer is partly done. */ |
926008c9 DT |
2293 | frame->status = -EXDEV; |
2294 | ||
2295 | /* calc actual length */ | |
2296 | frame->actual_length = 0; | |
2297 | ||
2298 | /* Update ring dequeue pointer */ | |
2299 | while (ep_ring->dequeue != td->last_trb) | |
3b72fca0 AX |
2300 | inc_deq(xhci, ep_ring); |
2301 | inc_deq(xhci, ep_ring); | |
926008c9 DT |
2302 | |
2303 | return finish_td(xhci, td, NULL, event, ep, status, true); | |
2304 | } | |
2305 | ||
22405ed2 AX |
2306 | /* |
2307 | * Process bulk and interrupt tds, update urb status and actual_length. | |
2308 | */ | |
2309 | static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td, | |
2310 | union xhci_trb *event_trb, struct xhci_transfer_event *event, | |
2311 | struct xhci_virt_ep *ep, int *status) | |
2312 | { | |
2313 | struct xhci_ring *ep_ring; | |
2314 | union xhci_trb *cur_trb; | |
2315 | struct xhci_segment *cur_seg; | |
2316 | u32 trb_comp_code; | |
2317 | ||
28ccd296 ME |
2318 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); |
2319 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); | |
22405ed2 AX |
2320 | |
2321 | switch (trb_comp_code) { | |
2322 | case COMP_SUCCESS: | |
2323 | /* Double check that the HW transferred everything. */ | |
1530bbc6 | 2324 | if (event_trb != td->last_trb || |
1c11a172 | 2325 | EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) { |
22405ed2 AX |
2326 | xhci_warn(xhci, "WARN Successful completion " |
2327 | "on short TX\n"); | |
2328 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) | |
2329 | *status = -EREMOTEIO; | |
2330 | else | |
2331 | *status = 0; | |
1530bbc6 SS |
2332 | if ((xhci->quirks & XHCI_TRUST_TX_LENGTH)) |
2333 | trb_comp_code = COMP_SHORT_TX; | |
22405ed2 | 2334 | } else { |
22405ed2 AX |
2335 | *status = 0; |
2336 | } | |
2337 | break; | |
2338 | case COMP_SHORT_TX: | |
2339 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) | |
2340 | *status = -EREMOTEIO; | |
2341 | else | |
2342 | *status = 0; | |
2343 | break; | |
2344 | default: | |
2345 | /* Others already handled above */ | |
2346 | break; | |
2347 | } | |
f444ff27 SS |
2348 | if (trb_comp_code == COMP_SHORT_TX) |
2349 | xhci_dbg(xhci, "ep %#x - asked for %d bytes, " | |
2350 | "%d bytes untransferred\n", | |
2351 | td->urb->ep->desc.bEndpointAddress, | |
2352 | td->urb->transfer_buffer_length, | |
1c11a172 | 2353 | EVENT_TRB_LEN(le32_to_cpu(event->transfer_len))); |
22405ed2 AX |
2354 | /* Fast path - was this the last TRB in the TD for this URB? */ |
2355 | if (event_trb == td->last_trb) { | |
1c11a172 | 2356 | if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) { |
22405ed2 AX |
2357 | td->urb->actual_length = |
2358 | td->urb->transfer_buffer_length - | |
1c11a172 | 2359 | EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); |
22405ed2 AX |
2360 | if (td->urb->transfer_buffer_length < |
2361 | td->urb->actual_length) { | |
2362 | xhci_warn(xhci, "HC gave bad length " | |
2363 | "of %d bytes left\n", | |
1c11a172 | 2364 | EVENT_TRB_LEN(le32_to_cpu(event->transfer_len))); |
22405ed2 AX |
2365 | td->urb->actual_length = 0; |
2366 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) | |
2367 | *status = -EREMOTEIO; | |
2368 | else | |
2369 | *status = 0; | |
2370 | } | |
2371 | /* Don't overwrite a previously set error code */ | |
2372 | if (*status == -EINPROGRESS) { | |
2373 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) | |
2374 | *status = -EREMOTEIO; | |
2375 | else | |
2376 | *status = 0; | |
2377 | } | |
2378 | } else { | |
2379 | td->urb->actual_length = | |
2380 | td->urb->transfer_buffer_length; | |
2381 | /* Ignore a short packet completion if the | |
2382 | * untransferred length was zero. | |
2383 | */ | |
2384 | if (*status == -EREMOTEIO) | |
2385 | *status = 0; | |
2386 | } | |
2387 | } else { | |
2388 | /* Slow path - walk the list, starting from the dequeue | |
2389 | * pointer, to get the actual length transferred. | |
2390 | */ | |
2391 | td->urb->actual_length = 0; | |
2392 | for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg; | |
2393 | cur_trb != event_trb; | |
2394 | next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) { | |
f5960b69 ME |
2395 | if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) && |
2396 | !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) | |
22405ed2 | 2397 | td->urb->actual_length += |
28ccd296 | 2398 | TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])); |
22405ed2 AX |
2399 | } |
2400 | /* If the ring didn't stop on a Link or No-op TRB, add | |
2401 | * in the actual bytes transferred from the Normal TRB | |
2402 | */ | |
2403 | if (trb_comp_code != COMP_STOP_INVAL) | |
2404 | td->urb->actual_length += | |
28ccd296 | 2405 | TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) - |
1c11a172 | 2406 | EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); |
22405ed2 AX |
2407 | } |
2408 | ||
2409 | return finish_td(xhci, td, event_trb, event, ep, status, false); | |
2410 | } | |
2411 | ||
d0e96f5a SS |
2412 | /* |
2413 | * If this function returns an error condition, it means it got a Transfer | |
2414 | * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address. | |
2415 | * At this point, the host controller is probably hosed and should be reset. | |
2416 | */ | |
2417 | static int handle_tx_event(struct xhci_hcd *xhci, | |
2418 | struct xhci_transfer_event *event) | |
ed384bd3 FB |
2419 | __releases(&xhci->lock) |
2420 | __acquires(&xhci->lock) | |
d0e96f5a SS |
2421 | { |
2422 | struct xhci_virt_device *xdev; | |
63a0d9ab | 2423 | struct xhci_virt_ep *ep; |
d0e96f5a | 2424 | struct xhci_ring *ep_ring; |
82d1009f | 2425 | unsigned int slot_id; |
d0e96f5a | 2426 | int ep_index; |
326b4810 | 2427 | struct xhci_td *td = NULL; |
d0e96f5a SS |
2428 | dma_addr_t event_dma; |
2429 | struct xhci_segment *event_seg; | |
2430 | union xhci_trb *event_trb; | |
326b4810 | 2431 | struct urb *urb = NULL; |
d0e96f5a | 2432 | int status = -EINPROGRESS; |
8e51adcc | 2433 | struct urb_priv *urb_priv; |
d115b048 | 2434 | struct xhci_ep_ctx *ep_ctx; |
c2d7b49f | 2435 | struct list_head *tmp; |
66d1eebc | 2436 | u32 trb_comp_code; |
4422da61 | 2437 | int ret = 0; |
c2d7b49f | 2438 | int td_num = 0; |
d0e96f5a | 2439 | |
28ccd296 | 2440 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
82d1009f | 2441 | xdev = xhci->devs[slot_id]; |
d0e96f5a SS |
2442 | if (!xdev) { |
2443 | xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n"); | |
9258c0b2 | 2444 | xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n", |
e910b440 SS |
2445 | (unsigned long long) xhci_trb_virt_to_dma( |
2446 | xhci->event_ring->deq_seg, | |
9258c0b2 SS |
2447 | xhci->event_ring->dequeue), |
2448 | lower_32_bits(le64_to_cpu(event->buffer)), | |
2449 | upper_32_bits(le64_to_cpu(event->buffer)), | |
2450 | le32_to_cpu(event->transfer_len), | |
2451 | le32_to_cpu(event->flags)); | |
2452 | xhci_dbg(xhci, "Event ring:\n"); | |
2453 | xhci_debug_segment(xhci, xhci->event_ring->deq_seg); | |
d0e96f5a SS |
2454 | return -ENODEV; |
2455 | } | |
2456 | ||
2457 | /* Endpoint ID is 1 based, our index is zero based */ | |
28ccd296 | 2458 | ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1; |
63a0d9ab | 2459 | ep = &xdev->eps[ep_index]; |
28ccd296 | 2460 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); |
d115b048 | 2461 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
986a92d4 | 2462 | if (!ep_ring || |
28ccd296 ME |
2463 | (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) == |
2464 | EP_STATE_DISABLED) { | |
e9df17eb SS |
2465 | xhci_err(xhci, "ERROR Transfer event for disabled endpoint " |
2466 | "or incorrect stream ring\n"); | |
9258c0b2 | 2467 | xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n", |
e910b440 SS |
2468 | (unsigned long long) xhci_trb_virt_to_dma( |
2469 | xhci->event_ring->deq_seg, | |
9258c0b2 SS |
2470 | xhci->event_ring->dequeue), |
2471 | lower_32_bits(le64_to_cpu(event->buffer)), | |
2472 | upper_32_bits(le64_to_cpu(event->buffer)), | |
2473 | le32_to_cpu(event->transfer_len), | |
2474 | le32_to_cpu(event->flags)); | |
2475 | xhci_dbg(xhci, "Event ring:\n"); | |
2476 | xhci_debug_segment(xhci, xhci->event_ring->deq_seg); | |
d0e96f5a SS |
2477 | return -ENODEV; |
2478 | } | |
2479 | ||
c2d7b49f AX |
2480 | /* Count current td numbers if ep->skip is set */ |
2481 | if (ep->skip) { | |
2482 | list_for_each(tmp, &ep_ring->td_list) | |
2483 | td_num++; | |
2484 | } | |
2485 | ||
28ccd296 ME |
2486 | event_dma = le64_to_cpu(event->buffer); |
2487 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); | |
986a92d4 | 2488 | /* Look for common error cases */ |
66d1eebc | 2489 | switch (trb_comp_code) { |
b10de142 SS |
2490 | /* Skip codes that require special handling depending on |
2491 | * transfer type | |
2492 | */ | |
2493 | case COMP_SUCCESS: | |
1c11a172 | 2494 | if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) |
1530bbc6 SS |
2495 | break; |
2496 | if (xhci->quirks & XHCI_TRUST_TX_LENGTH) | |
2497 | trb_comp_code = COMP_SHORT_TX; | |
2498 | else | |
8202ce2e SS |
2499 | xhci_warn_ratelimited(xhci, |
2500 | "WARN Successful completion on short TX: needs XHCI_TRUST_TX_LENGTH quirk?\n"); | |
b10de142 SS |
2501 | case COMP_SHORT_TX: |
2502 | break; | |
ae636747 SS |
2503 | case COMP_STOP: |
2504 | xhci_dbg(xhci, "Stopped on Transfer TRB\n"); | |
2505 | break; | |
2506 | case COMP_STOP_INVAL: | |
2507 | xhci_dbg(xhci, "Stopped on No-op or Link TRB\n"); | |
2508 | break; | |
b10de142 | 2509 | case COMP_STALL: |
2a9227a5 | 2510 | xhci_dbg(xhci, "Stalled endpoint\n"); |
63a0d9ab | 2511 | ep->ep_state |= EP_HALTED; |
b10de142 SS |
2512 | status = -EPIPE; |
2513 | break; | |
2514 | case COMP_TRB_ERR: | |
2515 | xhci_warn(xhci, "WARN: TRB error on endpoint\n"); | |
2516 | status = -EILSEQ; | |
2517 | break; | |
ec74e403 | 2518 | case COMP_SPLIT_ERR: |
b10de142 | 2519 | case COMP_TX_ERR: |
2a9227a5 | 2520 | xhci_dbg(xhci, "Transfer error on endpoint\n"); |
b10de142 SS |
2521 | status = -EPROTO; |
2522 | break; | |
4a73143c | 2523 | case COMP_BABBLE: |
2a9227a5 | 2524 | xhci_dbg(xhci, "Babble error on endpoint\n"); |
4a73143c SS |
2525 | status = -EOVERFLOW; |
2526 | break; | |
b10de142 SS |
2527 | case COMP_DB_ERR: |
2528 | xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n"); | |
2529 | status = -ENOSR; | |
2530 | break; | |
986a92d4 AX |
2531 | case COMP_BW_OVER: |
2532 | xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n"); | |
2533 | break; | |
2534 | case COMP_BUFF_OVER: | |
2535 | xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n"); | |
2536 | break; | |
2537 | case COMP_UNDERRUN: | |
2538 | /* | |
2539 | * When the Isoch ring is empty, the xHC will generate | |
2540 | * a Ring Overrun Event for IN Isoch endpoint or Ring | |
2541 | * Underrun Event for OUT Isoch endpoint. | |
2542 | */ | |
2543 | xhci_dbg(xhci, "underrun event on endpoint\n"); | |
2544 | if (!list_empty(&ep_ring->td_list)) | |
2545 | xhci_dbg(xhci, "Underrun Event for slot %d ep %d " | |
2546 | "still with TDs queued?\n", | |
28ccd296 ME |
2547 | TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), |
2548 | ep_index); | |
986a92d4 AX |
2549 | goto cleanup; |
2550 | case COMP_OVERRUN: | |
2551 | xhci_dbg(xhci, "overrun event on endpoint\n"); | |
2552 | if (!list_empty(&ep_ring->td_list)) | |
2553 | xhci_dbg(xhci, "Overrun Event for slot %d ep %d " | |
2554 | "still with TDs queued?\n", | |
28ccd296 ME |
2555 | TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), |
2556 | ep_index); | |
986a92d4 | 2557 | goto cleanup; |
f6ba6fe2 AH |
2558 | case COMP_DEV_ERR: |
2559 | xhci_warn(xhci, "WARN: detect an incompatible device"); | |
2560 | status = -EPROTO; | |
2561 | break; | |
d18240db AX |
2562 | case COMP_MISSED_INT: |
2563 | /* | |
2564 | * When encounter missed service error, one or more isoc tds | |
2565 | * may be missed by xHC. | |
2566 | * Set skip flag of the ep_ring; Complete the missed tds as | |
2567 | * short transfer when process the ep_ring next time. | |
2568 | */ | |
2569 | ep->skip = true; | |
2570 | xhci_dbg(xhci, "Miss service interval error, set skip flag\n"); | |
2571 | goto cleanup; | |
b10de142 | 2572 | default: |
b45b5069 | 2573 | if (xhci_is_vendor_info_code(xhci, trb_comp_code)) { |
5ad6a529 SS |
2574 | status = 0; |
2575 | break; | |
2576 | } | |
986a92d4 AX |
2577 | xhci_warn(xhci, "ERROR Unknown event condition, HC probably " |
2578 | "busted\n"); | |
2579 | goto cleanup; | |
2580 | } | |
2581 | ||
d18240db AX |
2582 | do { |
2583 | /* This TRB should be in the TD at the head of this ring's | |
2584 | * TD list. | |
2585 | */ | |
2586 | if (list_empty(&ep_ring->td_list)) { | |
a83d6755 SS |
2587 | /* |
2588 | * A stopped endpoint may generate an extra completion | |
2589 | * event if the device was suspended. Don't print | |
2590 | * warnings. | |
2591 | */ | |
2592 | if (!(trb_comp_code == COMP_STOP || | |
2593 | trb_comp_code == COMP_STOP_INVAL)) { | |
2594 | xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n", | |
2595 | TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), | |
2596 | ep_index); | |
2597 | xhci_dbg(xhci, "Event TRB with TRB type ID %u\n", | |
2598 | (le32_to_cpu(event->flags) & | |
2599 | TRB_TYPE_BITMASK)>>10); | |
2600 | xhci_print_trb_offsets(xhci, (union xhci_trb *) event); | |
2601 | } | |
d18240db AX |
2602 | if (ep->skip) { |
2603 | ep->skip = false; | |
2604 | xhci_dbg(xhci, "td_list is empty while skip " | |
2605 | "flag set. Clear skip flag.\n"); | |
2606 | } | |
2607 | ret = 0; | |
2608 | goto cleanup; | |
2609 | } | |
986a92d4 | 2610 | |
c2d7b49f AX |
2611 | /* We've skipped all the TDs on the ep ring when ep->skip set */ |
2612 | if (ep->skip && td_num == 0) { | |
2613 | ep->skip = false; | |
2614 | xhci_dbg(xhci, "All tds on the ep_ring skipped. " | |
2615 | "Clear skip flag.\n"); | |
2616 | ret = 0; | |
2617 | goto cleanup; | |
2618 | } | |
2619 | ||
d18240db | 2620 | td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list); |
c2d7b49f AX |
2621 | if (ep->skip) |
2622 | td_num--; | |
926008c9 | 2623 | |
d18240db AX |
2624 | /* Is this a TRB in the currently executing TD? */ |
2625 | event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue, | |
2626 | td->last_trb, event_dma); | |
e1cf486d AH |
2627 | |
2628 | /* | |
2629 | * Skip the Force Stopped Event. The event_trb(event_dma) of FSE | |
2630 | * is not in the current TD pointed by ep_ring->dequeue because | |
2631 | * that the hardware dequeue pointer still at the previous TRB | |
2632 | * of the current TD. The previous TRB maybe a Link TD or the | |
2633 | * last TRB of the previous TD. The command completion handle | |
2634 | * will take care the rest. | |
2635 | */ | |
2636 | if (!event_seg && trb_comp_code == COMP_STOP_INVAL) { | |
2637 | ret = 0; | |
2638 | goto cleanup; | |
2639 | } | |
2640 | ||
926008c9 DT |
2641 | if (!event_seg) { |
2642 | if (!ep->skip || | |
2643 | !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) { | |
ad808333 SS |
2644 | /* Some host controllers give a spurious |
2645 | * successful event after a short transfer. | |
2646 | * Ignore it. | |
2647 | */ | |
2648 | if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) && | |
2649 | ep_ring->last_td_was_short) { | |
2650 | ep_ring->last_td_was_short = false; | |
2651 | ret = 0; | |
2652 | goto cleanup; | |
2653 | } | |
926008c9 DT |
2654 | /* HC is busted, give up! */ |
2655 | xhci_err(xhci, | |
2656 | "ERROR Transfer event TRB DMA ptr not " | |
2657 | "part of current TD\n"); | |
2658 | return -ESHUTDOWN; | |
2659 | } | |
2660 | ||
2661 | ret = skip_isoc_td(xhci, td, event, ep, &status); | |
2662 | goto cleanup; | |
2663 | } | |
ad808333 SS |
2664 | if (trb_comp_code == COMP_SHORT_TX) |
2665 | ep_ring->last_td_was_short = true; | |
2666 | else | |
2667 | ep_ring->last_td_was_short = false; | |
926008c9 DT |
2668 | |
2669 | if (ep->skip) { | |
d18240db AX |
2670 | xhci_dbg(xhci, "Found td. Clear skip flag.\n"); |
2671 | ep->skip = false; | |
2672 | } | |
678539cf | 2673 | |
926008c9 DT |
2674 | event_trb = &event_seg->trbs[(event_dma - event_seg->dma) / |
2675 | sizeof(*event_trb)]; | |
2676 | /* | |
2677 | * No-op TRB should not trigger interrupts. | |
2678 | * If event_trb is a no-op TRB, it means the | |
2679 | * corresponding TD has been cancelled. Just ignore | |
2680 | * the TD. | |
2681 | */ | |
f5960b69 | 2682 | if (TRB_TYPE_NOOP_LE32(event_trb->generic.field[3])) { |
926008c9 DT |
2683 | xhci_dbg(xhci, |
2684 | "event_trb is a no-op TRB. Skip it\n"); | |
2685 | goto cleanup; | |
d18240db | 2686 | } |
4422da61 | 2687 | |
d18240db AX |
2688 | /* Now update the urb's actual_length and give back to |
2689 | * the core | |
82d1009f | 2690 | */ |
d18240db AX |
2691 | if (usb_endpoint_xfer_control(&td->urb->ep->desc)) |
2692 | ret = process_ctrl_td(xhci, td, event_trb, event, ep, | |
2693 | &status); | |
04e51901 AX |
2694 | else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc)) |
2695 | ret = process_isoc_td(xhci, td, event_trb, event, ep, | |
2696 | &status); | |
d18240db AX |
2697 | else |
2698 | ret = process_bulk_intr_td(xhci, td, event_trb, event, | |
2699 | ep, &status); | |
2700 | ||
2701 | cleanup: | |
2702 | /* | |
2703 | * Do not update event ring dequeue pointer if ep->skip is set. | |
2704 | * Will roll back to continue process missed tds. | |
2705 | */ | |
2706 | if (trb_comp_code == COMP_MISSED_INT || !ep->skip) { | |
3b72fca0 | 2707 | inc_deq(xhci, xhci->event_ring); |
d18240db AX |
2708 | } |
2709 | ||
2710 | if (ret) { | |
2711 | urb = td->urb; | |
8e51adcc | 2712 | urb_priv = urb->hcpriv; |
d18240db AX |
2713 | /* Leave the TD around for the reset endpoint function |
2714 | * to use(but only if it's not a control endpoint, | |
2715 | * since we already queued the Set TR dequeue pointer | |
2716 | * command for stalled control endpoints). | |
2717 | */ | |
2718 | if (usb_endpoint_xfer_control(&urb->ep->desc) || | |
2719 | (trb_comp_code != COMP_STALL && | |
2720 | trb_comp_code != COMP_BABBLE)) | |
8e51adcc | 2721 | xhci_urb_free_priv(xhci, urb_priv); |
48c3375c AS |
2722 | else |
2723 | kfree(urb_priv); | |
d18240db | 2724 | |
214f76f7 | 2725 | usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb); |
f444ff27 SS |
2726 | if ((urb->actual_length != urb->transfer_buffer_length && |
2727 | (urb->transfer_flags & | |
2728 | URB_SHORT_NOT_OK)) || | |
fd984d24 SS |
2729 | (status != 0 && |
2730 | !usb_endpoint_xfer_isoc(&urb->ep->desc))) | |
f444ff27 | 2731 | xhci_dbg(xhci, "Giveback URB %p, len = %d, " |
1949f9e2 | 2732 | "expected = %d, status = %d\n", |
f444ff27 SS |
2733 | urb, urb->actual_length, |
2734 | urb->transfer_buffer_length, | |
2735 | status); | |
d18240db | 2736 | spin_unlock(&xhci->lock); |
b3df3f9c SS |
2737 | /* EHCI, UHCI, and OHCI always unconditionally set the |
2738 | * urb->status of an isochronous endpoint to 0. | |
2739 | */ | |
2740 | if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) | |
2741 | status = 0; | |
214f76f7 | 2742 | usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status); |
d18240db AX |
2743 | spin_lock(&xhci->lock); |
2744 | } | |
2745 | ||
2746 | /* | |
2747 | * If ep->skip is set, it means there are missed tds on the | |
2748 | * endpoint ring need to take care of. | |
2749 | * Process them as short transfer until reach the td pointed by | |
2750 | * the event. | |
2751 | */ | |
2752 | } while (ep->skip && trb_comp_code != COMP_MISSED_INT); | |
2753 | ||
d0e96f5a SS |
2754 | return 0; |
2755 | } | |
2756 | ||
0f2a7930 SS |
2757 | /* |
2758 | * This function handles all OS-owned events on the event ring. It may drop | |
2759 | * xhci->lock between event processing (e.g. to pass up port status changes). | |
9dee9a21 ME |
2760 | * Returns >0 for "possibly more events to process" (caller should call again), |
2761 | * otherwise 0 if done. In future, <0 returns should indicate error code. | |
0f2a7930 | 2762 | */ |
9dee9a21 | 2763 | static int xhci_handle_event(struct xhci_hcd *xhci) |
7f84eef0 SS |
2764 | { |
2765 | union xhci_trb *event; | |
0f2a7930 | 2766 | int update_ptrs = 1; |
d0e96f5a | 2767 | int ret; |
7f84eef0 SS |
2768 | |
2769 | if (!xhci->event_ring || !xhci->event_ring->dequeue) { | |
2770 | xhci->error_bitmask |= 1 << 1; | |
9dee9a21 | 2771 | return 0; |
7f84eef0 SS |
2772 | } |
2773 | ||
2774 | event = xhci->event_ring->dequeue; | |
2775 | /* Does the HC or OS own the TRB? */ | |
28ccd296 ME |
2776 | if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) != |
2777 | xhci->event_ring->cycle_state) { | |
7f84eef0 | 2778 | xhci->error_bitmask |= 1 << 2; |
9dee9a21 | 2779 | return 0; |
7f84eef0 SS |
2780 | } |
2781 | ||
92a3da41 ME |
2782 | /* |
2783 | * Barrier between reading the TRB_CYCLE (valid) flag above and any | |
2784 | * speculative reads of the event's flags/data below. | |
2785 | */ | |
2786 | rmb(); | |
0f2a7930 | 2787 | /* FIXME: Handle more event types. */ |
28ccd296 | 2788 | switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) { |
7f84eef0 SS |
2789 | case TRB_TYPE(TRB_COMPLETION): |
2790 | handle_cmd_completion(xhci, &event->event_cmd); | |
2791 | break; | |
0f2a7930 SS |
2792 | case TRB_TYPE(TRB_PORT_STATUS): |
2793 | handle_port_status(xhci, event); | |
2794 | update_ptrs = 0; | |
2795 | break; | |
d0e96f5a SS |
2796 | case TRB_TYPE(TRB_TRANSFER): |
2797 | ret = handle_tx_event(xhci, &event->trans_event); | |
2798 | if (ret < 0) | |
2799 | xhci->error_bitmask |= 1 << 9; | |
2800 | else | |
2801 | update_ptrs = 0; | |
2802 | break; | |
623bef9e SS |
2803 | case TRB_TYPE(TRB_DEV_NOTE): |
2804 | handle_device_notification(xhci, event); | |
2805 | break; | |
7f84eef0 | 2806 | default: |
28ccd296 ME |
2807 | if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >= |
2808 | TRB_TYPE(48)) | |
0238634d SS |
2809 | handle_vendor_event(xhci, event); |
2810 | else | |
2811 | xhci->error_bitmask |= 1 << 3; | |
7f84eef0 | 2812 | } |
6f5165cf SS |
2813 | /* Any of the above functions may drop and re-acquire the lock, so check |
2814 | * to make sure a watchdog timer didn't mark the host as non-responsive. | |
2815 | */ | |
2816 | if (xhci->xhc_state & XHCI_STATE_DYING) { | |
2817 | xhci_dbg(xhci, "xHCI host dying, returning from " | |
2818 | "event handler.\n"); | |
9dee9a21 | 2819 | return 0; |
6f5165cf | 2820 | } |
7f84eef0 | 2821 | |
c06d68b8 SS |
2822 | if (update_ptrs) |
2823 | /* Update SW event ring dequeue pointer */ | |
3b72fca0 | 2824 | inc_deq(xhci, xhci->event_ring); |
c06d68b8 | 2825 | |
9dee9a21 ME |
2826 | /* Are there more items on the event ring? Caller will call us again to |
2827 | * check. | |
2828 | */ | |
2829 | return 1; | |
7f84eef0 | 2830 | } |
9032cd52 SS |
2831 | |
2832 | /* | |
2833 | * xHCI spec says we can get an interrupt, and if the HC has an error condition, | |
2834 | * we might get bad data out of the event ring. Section 4.10.2.7 has a list of | |
2835 | * indicators of an event TRB error, but we check the status *first* to be safe. | |
2836 | */ | |
2837 | irqreturn_t xhci_irq(struct usb_hcd *hcd) | |
2838 | { | |
2839 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
c21599a3 | 2840 | u32 status; |
bda53145 | 2841 | u64 temp_64; |
c06d68b8 SS |
2842 | union xhci_trb *event_ring_deq; |
2843 | dma_addr_t deq; | |
9032cd52 SS |
2844 | |
2845 | spin_lock(&xhci->lock); | |
9032cd52 | 2846 | /* Check if the xHC generated the interrupt, or the irq is shared */ |
b0ba9720 | 2847 | status = readl(&xhci->op_regs->status); |
c21599a3 | 2848 | if (status == 0xffffffff) |
9032cd52 SS |
2849 | goto hw_died; |
2850 | ||
c21599a3 | 2851 | if (!(status & STS_EINT)) { |
9032cd52 | 2852 | spin_unlock(&xhci->lock); |
9032cd52 SS |
2853 | return IRQ_NONE; |
2854 | } | |
27e0dd4d | 2855 | if (status & STS_FATAL) { |
9032cd52 SS |
2856 | xhci_warn(xhci, "WARNING: Host System Error\n"); |
2857 | xhci_halt(xhci); | |
2858 | hw_died: | |
9032cd52 SS |
2859 | spin_unlock(&xhci->lock); |
2860 | return -ESHUTDOWN; | |
2861 | } | |
2862 | ||
bda53145 SS |
2863 | /* |
2864 | * Clear the op reg interrupt status first, | |
2865 | * so we can receive interrupts from other MSI-X interrupters. | |
2866 | * Write 1 to clear the interrupt status. | |
2867 | */ | |
27e0dd4d | 2868 | status |= STS_EINT; |
204b7793 | 2869 | writel(status, &xhci->op_regs->status); |
bda53145 SS |
2870 | /* FIXME when MSI-X is supported and there are multiple vectors */ |
2871 | /* Clear the MSI-X event interrupt status */ | |
2872 | ||
cd70469d | 2873 | if (hcd->irq) { |
c21599a3 SS |
2874 | u32 irq_pending; |
2875 | /* Acknowledge the PCI interrupt */ | |
b0ba9720 | 2876 | irq_pending = readl(&xhci->ir_set->irq_pending); |
4e833c0b | 2877 | irq_pending |= IMAN_IP; |
204b7793 | 2878 | writel(irq_pending, &xhci->ir_set->irq_pending); |
c21599a3 | 2879 | } |
bda53145 | 2880 | |
c06d68b8 | 2881 | if (xhci->xhc_state & XHCI_STATE_DYING) { |
bda53145 SS |
2882 | xhci_dbg(xhci, "xHCI dying, ignoring interrupt. " |
2883 | "Shouldn't IRQs be disabled?\n"); | |
c06d68b8 SS |
2884 | /* Clear the event handler busy flag (RW1C); |
2885 | * the event ring should be empty. | |
bda53145 | 2886 | */ |
f7b2e403 | 2887 | temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); |
477632df SS |
2888 | xhci_write_64(xhci, temp_64 | ERST_EHB, |
2889 | &xhci->ir_set->erst_dequeue); | |
c06d68b8 SS |
2890 | spin_unlock(&xhci->lock); |
2891 | ||
2892 | return IRQ_HANDLED; | |
2893 | } | |
2894 | ||
2895 | event_ring_deq = xhci->event_ring->dequeue; | |
2896 | /* FIXME this should be a delayed service routine | |
2897 | * that clears the EHB. | |
2898 | */ | |
9dee9a21 | 2899 | while (xhci_handle_event(xhci) > 0) {} |
bda53145 | 2900 | |
f7b2e403 | 2901 | temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); |
c06d68b8 SS |
2902 | /* If necessary, update the HW's version of the event ring deq ptr. */ |
2903 | if (event_ring_deq != xhci->event_ring->dequeue) { | |
2904 | deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg, | |
2905 | xhci->event_ring->dequeue); | |
2906 | if (deq == 0) | |
2907 | xhci_warn(xhci, "WARN something wrong with SW event " | |
2908 | "ring dequeue ptr.\n"); | |
2909 | /* Update HC event ring dequeue pointer */ | |
2910 | temp_64 &= ERST_PTR_MASK; | |
2911 | temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK); | |
2912 | } | |
2913 | ||
2914 | /* Clear the event handler busy flag (RW1C); event ring is empty. */ | |
2915 | temp_64 |= ERST_EHB; | |
477632df | 2916 | xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue); |
c06d68b8 | 2917 | |
9032cd52 SS |
2918 | spin_unlock(&xhci->lock); |
2919 | ||
2920 | return IRQ_HANDLED; | |
2921 | } | |
2922 | ||
851ec164 | 2923 | irqreturn_t xhci_msi_irq(int irq, void *hcd) |
9032cd52 | 2924 | { |
968b822c | 2925 | return xhci_irq(hcd); |
9032cd52 | 2926 | } |
7f84eef0 | 2927 | |
d0e96f5a SS |
2928 | /**** Endpoint Ring Operations ****/ |
2929 | ||
7f84eef0 SS |
2930 | /* |
2931 | * Generic function for queueing a TRB on a ring. | |
2932 | * The caller must have checked to make sure there's room on the ring. | |
6cc30d85 SS |
2933 | * |
2934 | * @more_trbs_coming: Will you enqueue more TRBs before calling | |
2935 | * prepare_transfer()? | |
7f84eef0 SS |
2936 | */ |
2937 | static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring, | |
3b72fca0 | 2938 | bool more_trbs_coming, |
7f84eef0 SS |
2939 | u32 field1, u32 field2, u32 field3, u32 field4) |
2940 | { | |
2941 | struct xhci_generic_trb *trb; | |
2942 | ||
2943 | trb = &ring->enqueue->generic; | |
28ccd296 ME |
2944 | trb->field[0] = cpu_to_le32(field1); |
2945 | trb->field[1] = cpu_to_le32(field2); | |
2946 | trb->field[2] = cpu_to_le32(field3); | |
2947 | trb->field[3] = cpu_to_le32(field4); | |
3b72fca0 | 2948 | inc_enq(xhci, ring, more_trbs_coming); |
7f84eef0 SS |
2949 | } |
2950 | ||
d0e96f5a SS |
2951 | /* |
2952 | * Does various checks on the endpoint ring, and makes it ready to queue num_trbs. | |
2953 | * FIXME allocate segments if the ring is full. | |
2954 | */ | |
2955 | static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring, | |
3b72fca0 | 2956 | u32 ep_state, unsigned int num_trbs, gfp_t mem_flags) |
d0e96f5a | 2957 | { |
8dfec614 AX |
2958 | unsigned int num_trbs_needed; |
2959 | ||
d0e96f5a | 2960 | /* Make sure the endpoint has been added to xHC schedule */ |
d0e96f5a SS |
2961 | switch (ep_state) { |
2962 | case EP_STATE_DISABLED: | |
2963 | /* | |
2964 | * USB core changed config/interfaces without notifying us, | |
2965 | * or hardware is reporting the wrong state. | |
2966 | */ | |
2967 | xhci_warn(xhci, "WARN urb submitted to disabled ep\n"); | |
2968 | return -ENOENT; | |
d0e96f5a | 2969 | case EP_STATE_ERROR: |
c92bcfa7 | 2970 | xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n"); |
d0e96f5a SS |
2971 | /* FIXME event handling code for error needs to clear it */ |
2972 | /* XXX not sure if this should be -ENOENT or not */ | |
2973 | return -EINVAL; | |
c92bcfa7 SS |
2974 | case EP_STATE_HALTED: |
2975 | xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n"); | |
d0e96f5a SS |
2976 | case EP_STATE_STOPPED: |
2977 | case EP_STATE_RUNNING: | |
2978 | break; | |
2979 | default: | |
2980 | xhci_err(xhci, "ERROR unknown endpoint state for ep\n"); | |
2981 | /* | |
2982 | * FIXME issue Configure Endpoint command to try to get the HC | |
2983 | * back into a known state. | |
2984 | */ | |
2985 | return -EINVAL; | |
2986 | } | |
8dfec614 AX |
2987 | |
2988 | while (1) { | |
3d4b81ed SS |
2989 | if (room_on_ring(xhci, ep_ring, num_trbs)) |
2990 | break; | |
8dfec614 AX |
2991 | |
2992 | if (ep_ring == xhci->cmd_ring) { | |
2993 | xhci_err(xhci, "Do not support expand command ring\n"); | |
2994 | return -ENOMEM; | |
2995 | } | |
2996 | ||
68ffb011 XR |
2997 | xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion, |
2998 | "ERROR no room on ep ring, try ring expansion"); | |
8dfec614 AX |
2999 | num_trbs_needed = num_trbs - ep_ring->num_trbs_free; |
3000 | if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed, | |
3001 | mem_flags)) { | |
3002 | xhci_err(xhci, "Ring expansion failed\n"); | |
3003 | return -ENOMEM; | |
3004 | } | |
261fa12b | 3005 | } |
6c12db90 JY |
3006 | |
3007 | if (enqueue_is_link_trb(ep_ring)) { | |
3008 | struct xhci_ring *ring = ep_ring; | |
3009 | union xhci_trb *next; | |
6c12db90 | 3010 | |
6c12db90 JY |
3011 | next = ring->enqueue; |
3012 | ||
3013 | while (last_trb(xhci, ring, ring->enq_seg, next)) { | |
7e393a83 AX |
3014 | /* If we're not dealing with 0.95 hardware or isoc rings |
3015 | * on AMD 0.96 host, clear the chain bit. | |
6c12db90 | 3016 | */ |
3b72fca0 AX |
3017 | if (!xhci_link_trb_quirk(xhci) && |
3018 | !(ring->type == TYPE_ISOC && | |
3019 | (xhci->quirks & XHCI_AMD_0x96_HOST))) | |
28ccd296 | 3020 | next->link.control &= cpu_to_le32(~TRB_CHAIN); |
6c12db90 | 3021 | else |
28ccd296 | 3022 | next->link.control |= cpu_to_le32(TRB_CHAIN); |
6c12db90 JY |
3023 | |
3024 | wmb(); | |
f5960b69 | 3025 | next->link.control ^= cpu_to_le32(TRB_CYCLE); |
6c12db90 JY |
3026 | |
3027 | /* Toggle the cycle bit after the last ring segment. */ | |
3028 | if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) { | |
3029 | ring->cycle_state = (ring->cycle_state ? 0 : 1); | |
6c12db90 JY |
3030 | } |
3031 | ring->enq_seg = ring->enq_seg->next; | |
3032 | ring->enqueue = ring->enq_seg->trbs; | |
3033 | next = ring->enqueue; | |
3034 | } | |
3035 | } | |
3036 | ||
d0e96f5a SS |
3037 | return 0; |
3038 | } | |
3039 | ||
23e3be11 | 3040 | static int prepare_transfer(struct xhci_hcd *xhci, |
d0e96f5a SS |
3041 | struct xhci_virt_device *xdev, |
3042 | unsigned int ep_index, | |
e9df17eb | 3043 | unsigned int stream_id, |
d0e96f5a SS |
3044 | unsigned int num_trbs, |
3045 | struct urb *urb, | |
8e51adcc | 3046 | unsigned int td_index, |
d0e96f5a SS |
3047 | gfp_t mem_flags) |
3048 | { | |
3049 | int ret; | |
8e51adcc AX |
3050 | struct urb_priv *urb_priv; |
3051 | struct xhci_td *td; | |
e9df17eb | 3052 | struct xhci_ring *ep_ring; |
d115b048 | 3053 | struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
e9df17eb SS |
3054 | |
3055 | ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id); | |
3056 | if (!ep_ring) { | |
3057 | xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n", | |
3058 | stream_id); | |
3059 | return -EINVAL; | |
3060 | } | |
3061 | ||
3062 | ret = prepare_ring(xhci, ep_ring, | |
28ccd296 | 3063 | le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK, |
3b72fca0 | 3064 | num_trbs, mem_flags); |
d0e96f5a SS |
3065 | if (ret) |
3066 | return ret; | |
d0e96f5a | 3067 | |
8e51adcc AX |
3068 | urb_priv = urb->hcpriv; |
3069 | td = urb_priv->td[td_index]; | |
3070 | ||
3071 | INIT_LIST_HEAD(&td->td_list); | |
3072 | INIT_LIST_HEAD(&td->cancelled_td_list); | |
3073 | ||
3074 | if (td_index == 0) { | |
214f76f7 | 3075 | ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb); |
d13565c1 | 3076 | if (unlikely(ret)) |
8e51adcc | 3077 | return ret; |
d0e96f5a SS |
3078 | } |
3079 | ||
8e51adcc | 3080 | td->urb = urb; |
d0e96f5a | 3081 | /* Add this TD to the tail of the endpoint ring's TD list */ |
8e51adcc AX |
3082 | list_add_tail(&td->td_list, &ep_ring->td_list); |
3083 | td->start_seg = ep_ring->enq_seg; | |
3084 | td->first_trb = ep_ring->enqueue; | |
3085 | ||
3086 | urb_priv->td[td_index] = td; | |
d0e96f5a SS |
3087 | |
3088 | return 0; | |
3089 | } | |
3090 | ||
23e3be11 | 3091 | static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb) |
8a96c052 SS |
3092 | { |
3093 | int num_sgs, num_trbs, running_total, temp, i; | |
3094 | struct scatterlist *sg; | |
3095 | ||
3096 | sg = NULL; | |
bc677d5b | 3097 | num_sgs = urb->num_mapped_sgs; |
8a96c052 SS |
3098 | temp = urb->transfer_buffer_length; |
3099 | ||
8a96c052 | 3100 | num_trbs = 0; |
910f8d0c | 3101 | for_each_sg(urb->sg, sg, num_sgs, i) { |
8a96c052 SS |
3102 | unsigned int len = sg_dma_len(sg); |
3103 | ||
3104 | /* Scatter gather list entries may cross 64KB boundaries */ | |
3105 | running_total = TRB_MAX_BUFF_SIZE - | |
a2490187 | 3106 | (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1)); |
5807795b | 3107 | running_total &= TRB_MAX_BUFF_SIZE - 1; |
8a96c052 SS |
3108 | if (running_total != 0) |
3109 | num_trbs++; | |
3110 | ||
3111 | /* How many more 64KB chunks to transfer, how many more TRBs? */ | |
bcd2fde0 | 3112 | while (running_total < sg_dma_len(sg) && running_total < temp) { |
8a96c052 SS |
3113 | num_trbs++; |
3114 | running_total += TRB_MAX_BUFF_SIZE; | |
3115 | } | |
8a96c052 SS |
3116 | len = min_t(int, len, temp); |
3117 | temp -= len; | |
3118 | if (temp == 0) | |
3119 | break; | |
3120 | } | |
8a96c052 SS |
3121 | return num_trbs; |
3122 | } | |
3123 | ||
23e3be11 | 3124 | static void check_trb_math(struct urb *urb, int num_trbs, int running_total) |
8a96c052 SS |
3125 | { |
3126 | if (num_trbs != 0) | |
a2490187 | 3127 | dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of " |
8a96c052 SS |
3128 | "TRBs, %d left\n", __func__, |
3129 | urb->ep->desc.bEndpointAddress, num_trbs); | |
3130 | if (running_total != urb->transfer_buffer_length) | |
a2490187 | 3131 | dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, " |
8a96c052 SS |
3132 | "queued %#x (%d), asked for %#x (%d)\n", |
3133 | __func__, | |
3134 | urb->ep->desc.bEndpointAddress, | |
3135 | running_total, running_total, | |
3136 | urb->transfer_buffer_length, | |
3137 | urb->transfer_buffer_length); | |
3138 | } | |
3139 | ||
23e3be11 | 3140 | static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id, |
e9df17eb | 3141 | unsigned int ep_index, unsigned int stream_id, int start_cycle, |
e1eab2e0 | 3142 | struct xhci_generic_trb *start_trb) |
8a96c052 | 3143 | { |
8a96c052 SS |
3144 | /* |
3145 | * Pass all the TRBs to the hardware at once and make sure this write | |
3146 | * isn't reordered. | |
3147 | */ | |
3148 | wmb(); | |
50f7b52a | 3149 | if (start_cycle) |
28ccd296 | 3150 | start_trb->field[3] |= cpu_to_le32(start_cycle); |
50f7b52a | 3151 | else |
28ccd296 | 3152 | start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE); |
be88fe4f | 3153 | xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id); |
8a96c052 SS |
3154 | } |
3155 | ||
624defa1 SS |
3156 | /* |
3157 | * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt | |
3158 | * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD | |
3159 | * (comprised of sg list entries) can take several service intervals to | |
3160 | * transmit. | |
3161 | */ | |
3162 | int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |
3163 | struct urb *urb, int slot_id, unsigned int ep_index) | |
3164 | { | |
3165 | struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, | |
3166 | xhci->devs[slot_id]->out_ctx, ep_index); | |
3167 | int xhci_interval; | |
3168 | int ep_interval; | |
3169 | ||
28ccd296 | 3170 | xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info)); |
624defa1 SS |
3171 | ep_interval = urb->interval; |
3172 | /* Convert to microframes */ | |
3173 | if (urb->dev->speed == USB_SPEED_LOW || | |
3174 | urb->dev->speed == USB_SPEED_FULL) | |
3175 | ep_interval *= 8; | |
3176 | /* FIXME change this to a warning and a suggestion to use the new API | |
3177 | * to set the polling interval (once the API is added). | |
3178 | */ | |
3179 | if (xhci_interval != ep_interval) { | |
0730d52a DK |
3180 | dev_dbg_ratelimited(&urb->dev->dev, |
3181 | "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n", | |
3182 | ep_interval, ep_interval == 1 ? "" : "s", | |
3183 | xhci_interval, xhci_interval == 1 ? "" : "s"); | |
624defa1 SS |
3184 | urb->interval = xhci_interval; |
3185 | /* Convert back to frames for LS/FS devices */ | |
3186 | if (urb->dev->speed == USB_SPEED_LOW || | |
3187 | urb->dev->speed == USB_SPEED_FULL) | |
3188 | urb->interval /= 8; | |
3189 | } | |
3fc8206d | 3190 | return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index); |
624defa1 SS |
3191 | } |
3192 | ||
04dd950d SS |
3193 | /* |
3194 | * The TD size is the number of bytes remaining in the TD (including this TRB), | |
3195 | * right shifted by 10. | |
3196 | * It must fit in bits 21:17, so it can't be bigger than 31. | |
3197 | */ | |
3198 | static u32 xhci_td_remainder(unsigned int remainder) | |
3199 | { | |
3200 | u32 max = (1 << (21 - 17 + 1)) - 1; | |
3201 | ||
3202 | if ((remainder >> 10) >= max) | |
3203 | return max << 17; | |
3204 | else | |
3205 | return (remainder >> 10) << 17; | |
3206 | } | |
3207 | ||
4da6e6f2 | 3208 | /* |
4525c0a1 SS |
3209 | * For xHCI 1.0 host controllers, TD size is the number of max packet sized |
3210 | * packets remaining in the TD (*not* including this TRB). | |
4da6e6f2 SS |
3211 | * |
3212 | * Total TD packet count = total_packet_count = | |
4525c0a1 | 3213 | * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize) |
4da6e6f2 SS |
3214 | * |
3215 | * Packets transferred up to and including this TRB = packets_transferred = | |
3216 | * rounddown(total bytes transferred including this TRB / wMaxPacketSize) | |
3217 | * | |
3218 | * TD size = total_packet_count - packets_transferred | |
3219 | * | |
3220 | * It must fit in bits 21:17, so it can't be bigger than 31. | |
4525c0a1 | 3221 | * The last TRB in a TD must have the TD size set to zero. |
4da6e6f2 | 3222 | */ |
4da6e6f2 | 3223 | static u32 xhci_v1_0_td_remainder(int running_total, int trb_buff_len, |
4525c0a1 SS |
3224 | unsigned int total_packet_count, struct urb *urb, |
3225 | unsigned int num_trbs_left) | |
4da6e6f2 SS |
3226 | { |
3227 | int packets_transferred; | |
3228 | ||
48df4a6f | 3229 | /* One TRB with a zero-length data packet. */ |
4525c0a1 | 3230 | if (num_trbs_left == 0 || (running_total == 0 && trb_buff_len == 0)) |
48df4a6f SS |
3231 | return 0; |
3232 | ||
4da6e6f2 SS |
3233 | /* All the TRB queueing functions don't count the current TRB in |
3234 | * running_total. | |
3235 | */ | |
3236 | packets_transferred = (running_total + trb_buff_len) / | |
f18f8ed2 | 3237 | GET_MAX_PACKET(usb_endpoint_maxp(&urb->ep->desc)); |
4da6e6f2 | 3238 | |
4525c0a1 SS |
3239 | if ((total_packet_count - packets_transferred) > 31) |
3240 | return 31 << 17; | |
3241 | return (total_packet_count - packets_transferred) << 17; | |
4da6e6f2 SS |
3242 | } |
3243 | ||
23e3be11 | 3244 | static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags, |
8a96c052 SS |
3245 | struct urb *urb, int slot_id, unsigned int ep_index) |
3246 | { | |
3247 | struct xhci_ring *ep_ring; | |
3248 | unsigned int num_trbs; | |
8e51adcc | 3249 | struct urb_priv *urb_priv; |
8a96c052 SS |
3250 | struct xhci_td *td; |
3251 | struct scatterlist *sg; | |
3252 | int num_sgs; | |
3253 | int trb_buff_len, this_sg_len, running_total; | |
4da6e6f2 | 3254 | unsigned int total_packet_count; |
8a96c052 SS |
3255 | bool first_trb; |
3256 | u64 addr; | |
6cc30d85 | 3257 | bool more_trbs_coming; |
8a96c052 SS |
3258 | |
3259 | struct xhci_generic_trb *start_trb; | |
3260 | int start_cycle; | |
3261 | ||
e9df17eb SS |
3262 | ep_ring = xhci_urb_to_transfer_ring(xhci, urb); |
3263 | if (!ep_ring) | |
3264 | return -EINVAL; | |
3265 | ||
8a96c052 | 3266 | num_trbs = count_sg_trbs_needed(xhci, urb); |
bc677d5b | 3267 | num_sgs = urb->num_mapped_sgs; |
4525c0a1 | 3268 | total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length, |
29cc8897 | 3269 | usb_endpoint_maxp(&urb->ep->desc)); |
8a96c052 | 3270 | |
23e3be11 | 3271 | trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id], |
e9df17eb | 3272 | ep_index, urb->stream_id, |
3b72fca0 | 3273 | num_trbs, urb, 0, mem_flags); |
8a96c052 SS |
3274 | if (trb_buff_len < 0) |
3275 | return trb_buff_len; | |
8e51adcc AX |
3276 | |
3277 | urb_priv = urb->hcpriv; | |
3278 | td = urb_priv->td[0]; | |
3279 | ||
8a96c052 SS |
3280 | /* |
3281 | * Don't give the first TRB to the hardware (by toggling the cycle bit) | |
3282 | * until we've finished creating all the other TRBs. The ring's cycle | |
3283 | * state may change as we enqueue the other TRBs, so save it too. | |
3284 | */ | |
3285 | start_trb = &ep_ring->enqueue->generic; | |
3286 | start_cycle = ep_ring->cycle_state; | |
3287 | ||
3288 | running_total = 0; | |
3289 | /* | |
3290 | * How much data is in the first TRB? | |
3291 | * | |
3292 | * There are three forces at work for TRB buffer pointers and lengths: | |
3293 | * 1. We don't want to walk off the end of this sg-list entry buffer. | |
3294 | * 2. The transfer length that the driver requested may be smaller than | |
3295 | * the amount of memory allocated for this scatter-gather list. | |
3296 | * 3. TRBs buffers can't cross 64KB boundaries. | |
3297 | */ | |
910f8d0c | 3298 | sg = urb->sg; |
8a96c052 SS |
3299 | addr = (u64) sg_dma_address(sg); |
3300 | this_sg_len = sg_dma_len(sg); | |
a2490187 | 3301 | trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1)); |
8a96c052 SS |
3302 | trb_buff_len = min_t(int, trb_buff_len, this_sg_len); |
3303 | if (trb_buff_len > urb->transfer_buffer_length) | |
3304 | trb_buff_len = urb->transfer_buffer_length; | |
8a96c052 SS |
3305 | |
3306 | first_trb = true; | |
3307 | /* Queue the first TRB, even if it's zero-length */ | |
3308 | do { | |
3309 | u32 field = 0; | |
f9dc68fe | 3310 | u32 length_field = 0; |
04dd950d | 3311 | u32 remainder = 0; |
8a96c052 SS |
3312 | |
3313 | /* Don't change the cycle bit of the first TRB until later */ | |
50f7b52a | 3314 | if (first_trb) { |
8a96c052 | 3315 | first_trb = false; |
50f7b52a AX |
3316 | if (start_cycle == 0) |
3317 | field |= 0x1; | |
3318 | } else | |
8a96c052 SS |
3319 | field |= ep_ring->cycle_state; |
3320 | ||
3321 | /* Chain all the TRBs together; clear the chain bit in the last | |
3322 | * TRB to indicate it's the last TRB in the chain. | |
3323 | */ | |
3324 | if (num_trbs > 1) { | |
3325 | field |= TRB_CHAIN; | |
3326 | } else { | |
3327 | /* FIXME - add check for ZERO_PACKET flag before this */ | |
3328 | td->last_trb = ep_ring->enqueue; | |
3329 | field |= TRB_IOC; | |
3330 | } | |
af8b9e63 SS |
3331 | |
3332 | /* Only set interrupt on short packet for IN endpoints */ | |
3333 | if (usb_urb_dir_in(urb)) | |
3334 | field |= TRB_ISP; | |
3335 | ||
8a96c052 | 3336 | if (TRB_MAX_BUFF_SIZE - |
a2490187 | 3337 | (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) { |
8a96c052 SS |
3338 | xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n"); |
3339 | xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n", | |
3340 | (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1), | |
3341 | (unsigned int) addr + trb_buff_len); | |
3342 | } | |
4da6e6f2 SS |
3343 | |
3344 | /* Set the TRB length, TD size, and interrupter fields. */ | |
3345 | if (xhci->hci_version < 0x100) { | |
3346 | remainder = xhci_td_remainder( | |
3347 | urb->transfer_buffer_length - | |
3348 | running_total); | |
3349 | } else { | |
3350 | remainder = xhci_v1_0_td_remainder(running_total, | |
4525c0a1 SS |
3351 | trb_buff_len, total_packet_count, urb, |
3352 | num_trbs - 1); | |
4da6e6f2 | 3353 | } |
f9dc68fe | 3354 | length_field = TRB_LEN(trb_buff_len) | |
04dd950d | 3355 | remainder | |
f9dc68fe | 3356 | TRB_INTR_TARGET(0); |
4da6e6f2 | 3357 | |
6cc30d85 SS |
3358 | if (num_trbs > 1) |
3359 | more_trbs_coming = true; | |
3360 | else | |
3361 | more_trbs_coming = false; | |
3b72fca0 | 3362 | queue_trb(xhci, ep_ring, more_trbs_coming, |
8e595a5d SS |
3363 | lower_32_bits(addr), |
3364 | upper_32_bits(addr), | |
f9dc68fe | 3365 | length_field, |
af8b9e63 | 3366 | field | TRB_TYPE(TRB_NORMAL)); |
8a96c052 SS |
3367 | --num_trbs; |
3368 | running_total += trb_buff_len; | |
3369 | ||
3370 | /* Calculate length for next transfer -- | |
3371 | * Are we done queueing all the TRBs for this sg entry? | |
3372 | */ | |
3373 | this_sg_len -= trb_buff_len; | |
3374 | if (this_sg_len == 0) { | |
3375 | --num_sgs; | |
3376 | if (num_sgs == 0) | |
3377 | break; | |
3378 | sg = sg_next(sg); | |
3379 | addr = (u64) sg_dma_address(sg); | |
3380 | this_sg_len = sg_dma_len(sg); | |
3381 | } else { | |
3382 | addr += trb_buff_len; | |
3383 | } | |
3384 | ||
3385 | trb_buff_len = TRB_MAX_BUFF_SIZE - | |
a2490187 | 3386 | (addr & (TRB_MAX_BUFF_SIZE - 1)); |
8a96c052 SS |
3387 | trb_buff_len = min_t(int, trb_buff_len, this_sg_len); |
3388 | if (running_total + trb_buff_len > urb->transfer_buffer_length) | |
3389 | trb_buff_len = | |
3390 | urb->transfer_buffer_length - running_total; | |
3391 | } while (running_total < urb->transfer_buffer_length); | |
3392 | ||
3393 | check_trb_math(urb, num_trbs, running_total); | |
e9df17eb | 3394 | giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, |
e1eab2e0 | 3395 | start_cycle, start_trb); |
8a96c052 SS |
3396 | return 0; |
3397 | } | |
3398 | ||
b10de142 | 3399 | /* This is very similar to what ehci-q.c qtd_fill() does */ |
23e3be11 | 3400 | int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, |
b10de142 SS |
3401 | struct urb *urb, int slot_id, unsigned int ep_index) |
3402 | { | |
3403 | struct xhci_ring *ep_ring; | |
8e51adcc | 3404 | struct urb_priv *urb_priv; |
b10de142 SS |
3405 | struct xhci_td *td; |
3406 | int num_trbs; | |
3407 | struct xhci_generic_trb *start_trb; | |
3408 | bool first_trb; | |
6cc30d85 | 3409 | bool more_trbs_coming; |
b10de142 | 3410 | int start_cycle; |
f9dc68fe | 3411 | u32 field, length_field; |
b10de142 SS |
3412 | |
3413 | int running_total, trb_buff_len, ret; | |
4da6e6f2 | 3414 | unsigned int total_packet_count; |
b10de142 SS |
3415 | u64 addr; |
3416 | ||
ff9c895f | 3417 | if (urb->num_sgs) |
8a96c052 SS |
3418 | return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index); |
3419 | ||
e9df17eb SS |
3420 | ep_ring = xhci_urb_to_transfer_ring(xhci, urb); |
3421 | if (!ep_ring) | |
3422 | return -EINVAL; | |
b10de142 SS |
3423 | |
3424 | num_trbs = 0; | |
3425 | /* How much data is (potentially) left before the 64KB boundary? */ | |
3426 | running_total = TRB_MAX_BUFF_SIZE - | |
a2490187 | 3427 | (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1)); |
5807795b | 3428 | running_total &= TRB_MAX_BUFF_SIZE - 1; |
b10de142 SS |
3429 | |
3430 | /* If there's some data on this 64KB chunk, or we have to send a | |
3431 | * zero-length transfer, we need at least one TRB | |
3432 | */ | |
3433 | if (running_total != 0 || urb->transfer_buffer_length == 0) | |
3434 | num_trbs++; | |
3435 | /* How many more 64KB chunks to transfer, how many more TRBs? */ | |
3436 | while (running_total < urb->transfer_buffer_length) { | |
3437 | num_trbs++; | |
3438 | running_total += TRB_MAX_BUFF_SIZE; | |
3439 | } | |
3440 | /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */ | |
3441 | ||
e9df17eb SS |
3442 | ret = prepare_transfer(xhci, xhci->devs[slot_id], |
3443 | ep_index, urb->stream_id, | |
3b72fca0 | 3444 | num_trbs, urb, 0, mem_flags); |
b10de142 SS |
3445 | if (ret < 0) |
3446 | return ret; | |
3447 | ||
8e51adcc AX |
3448 | urb_priv = urb->hcpriv; |
3449 | td = urb_priv->td[0]; | |
3450 | ||
b10de142 SS |
3451 | /* |
3452 | * Don't give the first TRB to the hardware (by toggling the cycle bit) | |
3453 | * until we've finished creating all the other TRBs. The ring's cycle | |
3454 | * state may change as we enqueue the other TRBs, so save it too. | |
3455 | */ | |
3456 | start_trb = &ep_ring->enqueue->generic; | |
3457 | start_cycle = ep_ring->cycle_state; | |
3458 | ||
3459 | running_total = 0; | |
4525c0a1 | 3460 | total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length, |
29cc8897 | 3461 | usb_endpoint_maxp(&urb->ep->desc)); |
b10de142 SS |
3462 | /* How much data is in the first TRB? */ |
3463 | addr = (u64) urb->transfer_dma; | |
3464 | trb_buff_len = TRB_MAX_BUFF_SIZE - | |
a2490187 PZ |
3465 | (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1)); |
3466 | if (trb_buff_len > urb->transfer_buffer_length) | |
b10de142 SS |
3467 | trb_buff_len = urb->transfer_buffer_length; |
3468 | ||
3469 | first_trb = true; | |
3470 | ||
3471 | /* Queue the first TRB, even if it's zero-length */ | |
3472 | do { | |
04dd950d | 3473 | u32 remainder = 0; |
b10de142 SS |
3474 | field = 0; |
3475 | ||
3476 | /* Don't change the cycle bit of the first TRB until later */ | |
50f7b52a | 3477 | if (first_trb) { |
b10de142 | 3478 | first_trb = false; |
50f7b52a AX |
3479 | if (start_cycle == 0) |
3480 | field |= 0x1; | |
3481 | } else | |
b10de142 SS |
3482 | field |= ep_ring->cycle_state; |
3483 | ||
3484 | /* Chain all the TRBs together; clear the chain bit in the last | |
3485 | * TRB to indicate it's the last TRB in the chain. | |
3486 | */ | |
3487 | if (num_trbs > 1) { | |
3488 | field |= TRB_CHAIN; | |
3489 | } else { | |
3490 | /* FIXME - add check for ZERO_PACKET flag before this */ | |
3491 | td->last_trb = ep_ring->enqueue; | |
3492 | field |= TRB_IOC; | |
3493 | } | |
af8b9e63 SS |
3494 | |
3495 | /* Only set interrupt on short packet for IN endpoints */ | |
3496 | if (usb_urb_dir_in(urb)) | |
3497 | field |= TRB_ISP; | |
3498 | ||
4da6e6f2 SS |
3499 | /* Set the TRB length, TD size, and interrupter fields. */ |
3500 | if (xhci->hci_version < 0x100) { | |
3501 | remainder = xhci_td_remainder( | |
3502 | urb->transfer_buffer_length - | |
3503 | running_total); | |
3504 | } else { | |
3505 | remainder = xhci_v1_0_td_remainder(running_total, | |
4525c0a1 SS |
3506 | trb_buff_len, total_packet_count, urb, |
3507 | num_trbs - 1); | |
4da6e6f2 | 3508 | } |
f9dc68fe | 3509 | length_field = TRB_LEN(trb_buff_len) | |
04dd950d | 3510 | remainder | |
f9dc68fe | 3511 | TRB_INTR_TARGET(0); |
4da6e6f2 | 3512 | |
6cc30d85 SS |
3513 | if (num_trbs > 1) |
3514 | more_trbs_coming = true; | |
3515 | else | |
3516 | more_trbs_coming = false; | |
3b72fca0 | 3517 | queue_trb(xhci, ep_ring, more_trbs_coming, |
8e595a5d SS |
3518 | lower_32_bits(addr), |
3519 | upper_32_bits(addr), | |
f9dc68fe | 3520 | length_field, |
af8b9e63 | 3521 | field | TRB_TYPE(TRB_NORMAL)); |
b10de142 SS |
3522 | --num_trbs; |
3523 | running_total += trb_buff_len; | |
3524 | ||
3525 | /* Calculate length for next transfer */ | |
3526 | addr += trb_buff_len; | |
3527 | trb_buff_len = urb->transfer_buffer_length - running_total; | |
3528 | if (trb_buff_len > TRB_MAX_BUFF_SIZE) | |
3529 | trb_buff_len = TRB_MAX_BUFF_SIZE; | |
3530 | } while (running_total < urb->transfer_buffer_length); | |
3531 | ||
8a96c052 | 3532 | check_trb_math(urb, num_trbs, running_total); |
e9df17eb | 3533 | giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, |
e1eab2e0 | 3534 | start_cycle, start_trb); |
b10de142 SS |
3535 | return 0; |
3536 | } | |
3537 | ||
d0e96f5a | 3538 | /* Caller must have locked xhci->lock */ |
23e3be11 | 3539 | int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, |
d0e96f5a SS |
3540 | struct urb *urb, int slot_id, unsigned int ep_index) |
3541 | { | |
3542 | struct xhci_ring *ep_ring; | |
3543 | int num_trbs; | |
3544 | int ret; | |
3545 | struct usb_ctrlrequest *setup; | |
3546 | struct xhci_generic_trb *start_trb; | |
3547 | int start_cycle; | |
f9dc68fe | 3548 | u32 field, length_field; |
8e51adcc | 3549 | struct urb_priv *urb_priv; |
d0e96f5a SS |
3550 | struct xhci_td *td; |
3551 | ||
e9df17eb SS |
3552 | ep_ring = xhci_urb_to_transfer_ring(xhci, urb); |
3553 | if (!ep_ring) | |
3554 | return -EINVAL; | |
d0e96f5a SS |
3555 | |
3556 | /* | |
3557 | * Need to copy setup packet into setup TRB, so we can't use the setup | |
3558 | * DMA address. | |
3559 | */ | |
3560 | if (!urb->setup_packet) | |
3561 | return -EINVAL; | |
3562 | ||
d0e96f5a SS |
3563 | /* 1 TRB for setup, 1 for status */ |
3564 | num_trbs = 2; | |
3565 | /* | |
3566 | * Don't need to check if we need additional event data and normal TRBs, | |
3567 | * since data in control transfers will never get bigger than 16MB | |
3568 | * XXX: can we get a buffer that crosses 64KB boundaries? | |
3569 | */ | |
3570 | if (urb->transfer_buffer_length > 0) | |
3571 | num_trbs++; | |
e9df17eb SS |
3572 | ret = prepare_transfer(xhci, xhci->devs[slot_id], |
3573 | ep_index, urb->stream_id, | |
3b72fca0 | 3574 | num_trbs, urb, 0, mem_flags); |
d0e96f5a SS |
3575 | if (ret < 0) |
3576 | return ret; | |
3577 | ||
8e51adcc AX |
3578 | urb_priv = urb->hcpriv; |
3579 | td = urb_priv->td[0]; | |
3580 | ||
d0e96f5a SS |
3581 | /* |
3582 | * Don't give the first TRB to the hardware (by toggling the cycle bit) | |
3583 | * until we've finished creating all the other TRBs. The ring's cycle | |
3584 | * state may change as we enqueue the other TRBs, so save it too. | |
3585 | */ | |
3586 | start_trb = &ep_ring->enqueue->generic; | |
3587 | start_cycle = ep_ring->cycle_state; | |
3588 | ||
3589 | /* Queue setup TRB - see section 6.4.1.2.1 */ | |
3590 | /* FIXME better way to translate setup_packet into two u32 fields? */ | |
3591 | setup = (struct usb_ctrlrequest *) urb->setup_packet; | |
50f7b52a AX |
3592 | field = 0; |
3593 | field |= TRB_IDT | TRB_TYPE(TRB_SETUP); | |
3594 | if (start_cycle == 0) | |
3595 | field |= 0x1; | |
b83cdc8f AX |
3596 | |
3597 | /* xHCI 1.0 6.4.1.2.1: Transfer Type field */ | |
3598 | if (xhci->hci_version == 0x100) { | |
3599 | if (urb->transfer_buffer_length > 0) { | |
3600 | if (setup->bRequestType & USB_DIR_IN) | |
3601 | field |= TRB_TX_TYPE(TRB_DATA_IN); | |
3602 | else | |
3603 | field |= TRB_TX_TYPE(TRB_DATA_OUT); | |
3604 | } | |
3605 | } | |
3606 | ||
3b72fca0 | 3607 | queue_trb(xhci, ep_ring, true, |
28ccd296 ME |
3608 | setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16, |
3609 | le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16, | |
3610 | TRB_LEN(8) | TRB_INTR_TARGET(0), | |
3611 | /* Immediate data in pointer */ | |
3612 | field); | |
d0e96f5a SS |
3613 | |
3614 | /* If there's data, queue data TRBs */ | |
af8b9e63 SS |
3615 | /* Only set interrupt on short packet for IN endpoints */ |
3616 | if (usb_urb_dir_in(urb)) | |
3617 | field = TRB_ISP | TRB_TYPE(TRB_DATA); | |
3618 | else | |
3619 | field = TRB_TYPE(TRB_DATA); | |
3620 | ||
f9dc68fe | 3621 | length_field = TRB_LEN(urb->transfer_buffer_length) | |
04dd950d | 3622 | xhci_td_remainder(urb->transfer_buffer_length) | |
f9dc68fe | 3623 | TRB_INTR_TARGET(0); |
d0e96f5a SS |
3624 | if (urb->transfer_buffer_length > 0) { |
3625 | if (setup->bRequestType & USB_DIR_IN) | |
3626 | field |= TRB_DIR_IN; | |
3b72fca0 | 3627 | queue_trb(xhci, ep_ring, true, |
d0e96f5a SS |
3628 | lower_32_bits(urb->transfer_dma), |
3629 | upper_32_bits(urb->transfer_dma), | |
f9dc68fe | 3630 | length_field, |
af8b9e63 | 3631 | field | ep_ring->cycle_state); |
d0e96f5a SS |
3632 | } |
3633 | ||
3634 | /* Save the DMA address of the last TRB in the TD */ | |
3635 | td->last_trb = ep_ring->enqueue; | |
3636 | ||
3637 | /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */ | |
3638 | /* If the device sent data, the status stage is an OUT transfer */ | |
3639 | if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN) | |
3640 | field = 0; | |
3641 | else | |
3642 | field = TRB_DIR_IN; | |
3b72fca0 | 3643 | queue_trb(xhci, ep_ring, false, |
d0e96f5a SS |
3644 | 0, |
3645 | 0, | |
3646 | TRB_INTR_TARGET(0), | |
3647 | /* Event on completion */ | |
3648 | field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state); | |
3649 | ||
e9df17eb | 3650 | giveback_first_trb(xhci, slot_id, ep_index, 0, |
e1eab2e0 | 3651 | start_cycle, start_trb); |
d0e96f5a SS |
3652 | return 0; |
3653 | } | |
3654 | ||
04e51901 AX |
3655 | static int count_isoc_trbs_needed(struct xhci_hcd *xhci, |
3656 | struct urb *urb, int i) | |
3657 | { | |
3658 | int num_trbs = 0; | |
48df4a6f | 3659 | u64 addr, td_len; |
04e51901 AX |
3660 | |
3661 | addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset); | |
3662 | td_len = urb->iso_frame_desc[i].length; | |
3663 | ||
48df4a6f SS |
3664 | num_trbs = DIV_ROUND_UP(td_len + (addr & (TRB_MAX_BUFF_SIZE - 1)), |
3665 | TRB_MAX_BUFF_SIZE); | |
3666 | if (num_trbs == 0) | |
04e51901 | 3667 | num_trbs++; |
04e51901 AX |
3668 | |
3669 | return num_trbs; | |
3670 | } | |
3671 | ||
5cd43e33 SS |
3672 | /* |
3673 | * The transfer burst count field of the isochronous TRB defines the number of | |
3674 | * bursts that are required to move all packets in this TD. Only SuperSpeed | |
3675 | * devices can burst up to bMaxBurst number of packets per service interval. | |
3676 | * This field is zero based, meaning a value of zero in the field means one | |
3677 | * burst. Basically, for everything but SuperSpeed devices, this field will be | |
3678 | * zero. Only xHCI 1.0 host controllers support this field. | |
3679 | */ | |
3680 | static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci, | |
3681 | struct usb_device *udev, | |
3682 | struct urb *urb, unsigned int total_packet_count) | |
3683 | { | |
3684 | unsigned int max_burst; | |
3685 | ||
3686 | if (xhci->hci_version < 0x100 || udev->speed != USB_SPEED_SUPER) | |
3687 | return 0; | |
3688 | ||
3689 | max_burst = urb->ep->ss_ep_comp.bMaxBurst; | |
3690 | return roundup(total_packet_count, max_burst + 1) - 1; | |
3691 | } | |
3692 | ||
b61d378f SS |
3693 | /* |
3694 | * Returns the number of packets in the last "burst" of packets. This field is | |
3695 | * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so | |
3696 | * the last burst packet count is equal to the total number of packets in the | |
3697 | * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst | |
3698 | * must contain (bMaxBurst + 1) number of packets, but the last burst can | |
3699 | * contain 1 to (bMaxBurst + 1) packets. | |
3700 | */ | |
3701 | static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci, | |
3702 | struct usb_device *udev, | |
3703 | struct urb *urb, unsigned int total_packet_count) | |
3704 | { | |
3705 | unsigned int max_burst; | |
3706 | unsigned int residue; | |
3707 | ||
3708 | if (xhci->hci_version < 0x100) | |
3709 | return 0; | |
3710 | ||
3711 | switch (udev->speed) { | |
3712 | case USB_SPEED_SUPER: | |
3713 | /* bMaxBurst is zero based: 0 means 1 packet per burst */ | |
3714 | max_burst = urb->ep->ss_ep_comp.bMaxBurst; | |
3715 | residue = total_packet_count % (max_burst + 1); | |
3716 | /* If residue is zero, the last burst contains (max_burst + 1) | |
3717 | * number of packets, but the TLBPC field is zero-based. | |
3718 | */ | |
3719 | if (residue == 0) | |
3720 | return max_burst; | |
3721 | return residue - 1; | |
3722 | default: | |
3723 | if (total_packet_count == 0) | |
3724 | return 0; | |
3725 | return total_packet_count - 1; | |
3726 | } | |
3727 | } | |
3728 | ||
04e51901 AX |
3729 | /* This is for isoc transfer */ |
3730 | static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |
3731 | struct urb *urb, int slot_id, unsigned int ep_index) | |
3732 | { | |
3733 | struct xhci_ring *ep_ring; | |
3734 | struct urb_priv *urb_priv; | |
3735 | struct xhci_td *td; | |
3736 | int num_tds, trbs_per_td; | |
3737 | struct xhci_generic_trb *start_trb; | |
3738 | bool first_trb; | |
3739 | int start_cycle; | |
3740 | u32 field, length_field; | |
3741 | int running_total, trb_buff_len, td_len, td_remain_len, ret; | |
3742 | u64 start_addr, addr; | |
3743 | int i, j; | |
47cbf692 | 3744 | bool more_trbs_coming; |
04e51901 AX |
3745 | |
3746 | ep_ring = xhci->devs[slot_id]->eps[ep_index].ring; | |
3747 | ||
3748 | num_tds = urb->number_of_packets; | |
3749 | if (num_tds < 1) { | |
3750 | xhci_dbg(xhci, "Isoc URB with zero packets?\n"); | |
3751 | return -EINVAL; | |
3752 | } | |
3753 | ||
04e51901 AX |
3754 | start_addr = (u64) urb->transfer_dma; |
3755 | start_trb = &ep_ring->enqueue->generic; | |
3756 | start_cycle = ep_ring->cycle_state; | |
3757 | ||
522989a2 | 3758 | urb_priv = urb->hcpriv; |
04e51901 AX |
3759 | /* Queue the first TRB, even if it's zero-length */ |
3760 | for (i = 0; i < num_tds; i++) { | |
4da6e6f2 | 3761 | unsigned int total_packet_count; |
5cd43e33 | 3762 | unsigned int burst_count; |
b61d378f | 3763 | unsigned int residue; |
04e51901 | 3764 | |
4da6e6f2 | 3765 | first_trb = true; |
04e51901 AX |
3766 | running_total = 0; |
3767 | addr = start_addr + urb->iso_frame_desc[i].offset; | |
3768 | td_len = urb->iso_frame_desc[i].length; | |
3769 | td_remain_len = td_len; | |
4525c0a1 | 3770 | total_packet_count = DIV_ROUND_UP(td_len, |
f18f8ed2 SS |
3771 | GET_MAX_PACKET( |
3772 | usb_endpoint_maxp(&urb->ep->desc))); | |
48df4a6f SS |
3773 | /* A zero-length transfer still involves at least one packet. */ |
3774 | if (total_packet_count == 0) | |
3775 | total_packet_count++; | |
5cd43e33 SS |
3776 | burst_count = xhci_get_burst_count(xhci, urb->dev, urb, |
3777 | total_packet_count); | |
b61d378f SS |
3778 | residue = xhci_get_last_burst_packet_count(xhci, |
3779 | urb->dev, urb, total_packet_count); | |
04e51901 AX |
3780 | |
3781 | trbs_per_td = count_isoc_trbs_needed(xhci, urb, i); | |
3782 | ||
3783 | ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index, | |
3b72fca0 | 3784 | urb->stream_id, trbs_per_td, urb, i, mem_flags); |
522989a2 SS |
3785 | if (ret < 0) { |
3786 | if (i == 0) | |
3787 | return ret; | |
3788 | goto cleanup; | |
3789 | } | |
04e51901 | 3790 | |
04e51901 | 3791 | td = urb_priv->td[i]; |
04e51901 AX |
3792 | for (j = 0; j < trbs_per_td; j++) { |
3793 | u32 remainder = 0; | |
760973d2 | 3794 | field = 0; |
04e51901 AX |
3795 | |
3796 | if (first_trb) { | |
760973d2 SS |
3797 | field = TRB_TBC(burst_count) | |
3798 | TRB_TLBPC(residue); | |
04e51901 AX |
3799 | /* Queue the isoc TRB */ |
3800 | field |= TRB_TYPE(TRB_ISOC); | |
3801 | /* Assume URB_ISO_ASAP is set */ | |
3802 | field |= TRB_SIA; | |
50f7b52a AX |
3803 | if (i == 0) { |
3804 | if (start_cycle == 0) | |
3805 | field |= 0x1; | |
3806 | } else | |
04e51901 AX |
3807 | field |= ep_ring->cycle_state; |
3808 | first_trb = false; | |
3809 | } else { | |
3810 | /* Queue other normal TRBs */ | |
3811 | field |= TRB_TYPE(TRB_NORMAL); | |
3812 | field |= ep_ring->cycle_state; | |
3813 | } | |
3814 | ||
af8b9e63 SS |
3815 | /* Only set interrupt on short packet for IN EPs */ |
3816 | if (usb_urb_dir_in(urb)) | |
3817 | field |= TRB_ISP; | |
3818 | ||
04e51901 AX |
3819 | /* Chain all the TRBs together; clear the chain bit in |
3820 | * the last TRB to indicate it's the last TRB in the | |
3821 | * chain. | |
3822 | */ | |
3823 | if (j < trbs_per_td - 1) { | |
3824 | field |= TRB_CHAIN; | |
47cbf692 | 3825 | more_trbs_coming = true; |
04e51901 AX |
3826 | } else { |
3827 | td->last_trb = ep_ring->enqueue; | |
3828 | field |= TRB_IOC; | |
80fab3b2 SS |
3829 | if (xhci->hci_version == 0x100 && |
3830 | !(xhci->quirks & | |
3831 | XHCI_AVOID_BEI)) { | |
ad106f29 AX |
3832 | /* Set BEI bit except for the last td */ |
3833 | if (i < num_tds - 1) | |
3834 | field |= TRB_BEI; | |
3835 | } | |
47cbf692 | 3836 | more_trbs_coming = false; |
04e51901 AX |
3837 | } |
3838 | ||
3839 | /* Calculate TRB length */ | |
3840 | trb_buff_len = TRB_MAX_BUFF_SIZE - | |
3841 | (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1)); | |
3842 | if (trb_buff_len > td_remain_len) | |
3843 | trb_buff_len = td_remain_len; | |
3844 | ||
4da6e6f2 SS |
3845 | /* Set the TRB length, TD size, & interrupter fields. */ |
3846 | if (xhci->hci_version < 0x100) { | |
3847 | remainder = xhci_td_remainder( | |
3848 | td_len - running_total); | |
3849 | } else { | |
3850 | remainder = xhci_v1_0_td_remainder( | |
3851 | running_total, trb_buff_len, | |
4525c0a1 SS |
3852 | total_packet_count, urb, |
3853 | (trbs_per_td - j - 1)); | |
4da6e6f2 | 3854 | } |
04e51901 AX |
3855 | length_field = TRB_LEN(trb_buff_len) | |
3856 | remainder | | |
3857 | TRB_INTR_TARGET(0); | |
4da6e6f2 | 3858 | |
3b72fca0 | 3859 | queue_trb(xhci, ep_ring, more_trbs_coming, |
04e51901 AX |
3860 | lower_32_bits(addr), |
3861 | upper_32_bits(addr), | |
3862 | length_field, | |
af8b9e63 | 3863 | field); |
04e51901 AX |
3864 | running_total += trb_buff_len; |
3865 | ||
3866 | addr += trb_buff_len; | |
3867 | td_remain_len -= trb_buff_len; | |
3868 | } | |
3869 | ||
3870 | /* Check TD length */ | |
3871 | if (running_total != td_len) { | |
3872 | xhci_err(xhci, "ISOC TD length unmatch\n"); | |
cf840551 AX |
3873 | ret = -EINVAL; |
3874 | goto cleanup; | |
04e51901 AX |
3875 | } |
3876 | } | |
3877 | ||
c41136b0 AX |
3878 | if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) { |
3879 | if (xhci->quirks & XHCI_AMD_PLL_FIX) | |
3880 | usb_amd_quirk_pll_disable(); | |
3881 | } | |
3882 | xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++; | |
3883 | ||
e1eab2e0 AX |
3884 | giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, |
3885 | start_cycle, start_trb); | |
04e51901 | 3886 | return 0; |
522989a2 SS |
3887 | cleanup: |
3888 | /* Clean up a partially enqueued isoc transfer. */ | |
3889 | ||
3890 | for (i--; i >= 0; i--) | |
585df1d9 | 3891 | list_del_init(&urb_priv->td[i]->td_list); |
522989a2 SS |
3892 | |
3893 | /* Use the first TD as a temporary variable to turn the TDs we've queued | |
3894 | * into No-ops with a software-owned cycle bit. That way the hardware | |
3895 | * won't accidentally start executing bogus TDs when we partially | |
3896 | * overwrite them. td->first_trb and td->start_seg are already set. | |
3897 | */ | |
3898 | urb_priv->td[0]->last_trb = ep_ring->enqueue; | |
3899 | /* Every TRB except the first & last will have its cycle bit flipped. */ | |
3900 | td_to_noop(xhci, ep_ring, urb_priv->td[0], true); | |
3901 | ||
3902 | /* Reset the ring enqueue back to the first TRB and its cycle bit. */ | |
3903 | ep_ring->enqueue = urb_priv->td[0]->first_trb; | |
3904 | ep_ring->enq_seg = urb_priv->td[0]->start_seg; | |
3905 | ep_ring->cycle_state = start_cycle; | |
b008df60 | 3906 | ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp; |
522989a2 SS |
3907 | usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb); |
3908 | return ret; | |
04e51901 AX |
3909 | } |
3910 | ||
3911 | /* | |
3912 | * Check transfer ring to guarantee there is enough room for the urb. | |
3913 | * Update ISO URB start_frame and interval. | |
3914 | * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to | |
3915 | * update the urb->start_frame by now. | |
3916 | * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input. | |
3917 | */ | |
3918 | int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags, | |
3919 | struct urb *urb, int slot_id, unsigned int ep_index) | |
3920 | { | |
3921 | struct xhci_virt_device *xdev; | |
3922 | struct xhci_ring *ep_ring; | |
3923 | struct xhci_ep_ctx *ep_ctx; | |
3924 | int start_frame; | |
3925 | int xhci_interval; | |
3926 | int ep_interval; | |
3927 | int num_tds, num_trbs, i; | |
3928 | int ret; | |
3929 | ||
3930 | xdev = xhci->devs[slot_id]; | |
3931 | ep_ring = xdev->eps[ep_index].ring; | |
3932 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); | |
3933 | ||
3934 | num_trbs = 0; | |
3935 | num_tds = urb->number_of_packets; | |
3936 | for (i = 0; i < num_tds; i++) | |
3937 | num_trbs += count_isoc_trbs_needed(xhci, urb, i); | |
3938 | ||
3939 | /* Check the ring to guarantee there is enough room for the whole urb. | |
3940 | * Do not insert any td of the urb to the ring if the check failed. | |
3941 | */ | |
28ccd296 | 3942 | ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK, |
3b72fca0 | 3943 | num_trbs, mem_flags); |
04e51901 AX |
3944 | if (ret) |
3945 | return ret; | |
3946 | ||
b0ba9720 | 3947 | start_frame = readl(&xhci->run_regs->microframe_index); |
04e51901 AX |
3948 | start_frame &= 0x3fff; |
3949 | ||
3950 | urb->start_frame = start_frame; | |
3951 | if (urb->dev->speed == USB_SPEED_LOW || | |
3952 | urb->dev->speed == USB_SPEED_FULL) | |
3953 | urb->start_frame >>= 3; | |
3954 | ||
28ccd296 | 3955 | xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info)); |
04e51901 AX |
3956 | ep_interval = urb->interval; |
3957 | /* Convert to microframes */ | |
3958 | if (urb->dev->speed == USB_SPEED_LOW || | |
3959 | urb->dev->speed == USB_SPEED_FULL) | |
3960 | ep_interval *= 8; | |
3961 | /* FIXME change this to a warning and a suggestion to use the new API | |
3962 | * to set the polling interval (once the API is added). | |
3963 | */ | |
3964 | if (xhci_interval != ep_interval) { | |
0730d52a DK |
3965 | dev_dbg_ratelimited(&urb->dev->dev, |
3966 | "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n", | |
3967 | ep_interval, ep_interval == 1 ? "" : "s", | |
3968 | xhci_interval, xhci_interval == 1 ? "" : "s"); | |
04e51901 AX |
3969 | urb->interval = xhci_interval; |
3970 | /* Convert back to frames for LS/FS devices */ | |
3971 | if (urb->dev->speed == USB_SPEED_LOW || | |
3972 | urb->dev->speed == USB_SPEED_FULL) | |
3973 | urb->interval /= 8; | |
3974 | } | |
b008df60 AX |
3975 | ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free; |
3976 | ||
3fc8206d | 3977 | return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index); |
04e51901 AX |
3978 | } |
3979 | ||
d0e96f5a SS |
3980 | /**** Command Ring Operations ****/ |
3981 | ||
913a8a34 SS |
3982 | /* Generic function for queueing a command TRB on the command ring. |
3983 | * Check to make sure there's room on the command ring for one command TRB. | |
3984 | * Also check that there's room reserved for commands that must not fail. | |
3985 | * If this is a command that must not fail, meaning command_must_succeed = TRUE, | |
3986 | * then only check for the number of reserved spots. | |
3987 | * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB | |
3988 | * because the command event handler may want to resubmit a failed command. | |
3989 | */ | |
3990 | static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2, | |
3991 | u32 field3, u32 field4, bool command_must_succeed) | |
7f84eef0 | 3992 | { |
913a8a34 | 3993 | int reserved_trbs = xhci->cmd_ring_reserved_trbs; |
d1dc908a SS |
3994 | int ret; |
3995 | ||
913a8a34 SS |
3996 | if (!command_must_succeed) |
3997 | reserved_trbs++; | |
3998 | ||
d1dc908a | 3999 | ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING, |
3b72fca0 | 4000 | reserved_trbs, GFP_ATOMIC); |
d1dc908a SS |
4001 | if (ret < 0) { |
4002 | xhci_err(xhci, "ERR: No room for command on command ring\n"); | |
913a8a34 SS |
4003 | if (command_must_succeed) |
4004 | xhci_err(xhci, "ERR: Reserved TRB counting for " | |
4005 | "unfailable commands failed.\n"); | |
d1dc908a | 4006 | return ret; |
7f84eef0 | 4007 | } |
3b72fca0 AX |
4008 | queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3, |
4009 | field4 | xhci->cmd_ring->cycle_state); | |
7f84eef0 SS |
4010 | return 0; |
4011 | } | |
4012 | ||
3ffbba95 | 4013 | /* Queue a slot enable or disable request on the command ring */ |
23e3be11 | 4014 | int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id) |
3ffbba95 SS |
4015 | { |
4016 | return queue_command(xhci, 0, 0, 0, | |
913a8a34 | 4017 | TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false); |
3ffbba95 SS |
4018 | } |
4019 | ||
4020 | /* Queue an address device command TRB */ | |
23e3be11 | 4021 | int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, |
48fc7dbd | 4022 | u32 slot_id, enum xhci_setup_dev setup) |
3ffbba95 | 4023 | { |
8e595a5d SS |
4024 | return queue_command(xhci, lower_32_bits(in_ctx_ptr), |
4025 | upper_32_bits(in_ctx_ptr), 0, | |
48fc7dbd DW |
4026 | TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id) |
4027 | | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false); | |
2a8f82c4 SS |
4028 | } |
4029 | ||
0238634d SS |
4030 | int xhci_queue_vendor_command(struct xhci_hcd *xhci, |
4031 | u32 field1, u32 field2, u32 field3, u32 field4) | |
4032 | { | |
4033 | return queue_command(xhci, field1, field2, field3, field4, false); | |
4034 | } | |
4035 | ||
2a8f82c4 SS |
4036 | /* Queue a reset device command TRB */ |
4037 | int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id) | |
4038 | { | |
4039 | return queue_command(xhci, 0, 0, 0, | |
4040 | TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id), | |
913a8a34 | 4041 | false); |
3ffbba95 | 4042 | } |
f94e0186 SS |
4043 | |
4044 | /* Queue a configure endpoint command TRB */ | |
23e3be11 | 4045 | int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, |
913a8a34 | 4046 | u32 slot_id, bool command_must_succeed) |
f94e0186 | 4047 | { |
8e595a5d SS |
4048 | return queue_command(xhci, lower_32_bits(in_ctx_ptr), |
4049 | upper_32_bits(in_ctx_ptr), 0, | |
913a8a34 SS |
4050 | TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id), |
4051 | command_must_succeed); | |
f94e0186 | 4052 | } |
ae636747 | 4053 | |
f2217e8e SS |
4054 | /* Queue an evaluate context command TRB */ |
4055 | int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, | |
4b266541 | 4056 | u32 slot_id, bool command_must_succeed) |
f2217e8e SS |
4057 | { |
4058 | return queue_command(xhci, lower_32_bits(in_ctx_ptr), | |
4059 | upper_32_bits(in_ctx_ptr), 0, | |
913a8a34 | 4060 | TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id), |
4b266541 | 4061 | command_must_succeed); |
f2217e8e SS |
4062 | } |
4063 | ||
be88fe4f AX |
4064 | /* |
4065 | * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop | |
4066 | * activity on an endpoint that is about to be suspended. | |
4067 | */ | |
23e3be11 | 4068 | int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id, |
be88fe4f | 4069 | unsigned int ep_index, int suspend) |
ae636747 SS |
4070 | { |
4071 | u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); | |
4072 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); | |
4073 | u32 type = TRB_TYPE(TRB_STOP_RING); | |
be88fe4f | 4074 | u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend); |
ae636747 SS |
4075 | |
4076 | return queue_command(xhci, 0, 0, 0, | |
be88fe4f | 4077 | trb_slot_id | trb_ep_index | type | trb_suspend, false); |
ae636747 SS |
4078 | } |
4079 | ||
4080 | /* Set Transfer Ring Dequeue Pointer command. | |
4081 | * This should not be used for endpoints that have streams enabled. | |
4082 | */ | |
4083 | static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id, | |
e9df17eb SS |
4084 | unsigned int ep_index, unsigned int stream_id, |
4085 | struct xhci_segment *deq_seg, | |
ae636747 SS |
4086 | union xhci_trb *deq_ptr, u32 cycle_state) |
4087 | { | |
4088 | dma_addr_t addr; | |
4089 | u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); | |
4090 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); | |
e9df17eb | 4091 | u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id); |
95241dbd | 4092 | u32 trb_sct = 0; |
ae636747 | 4093 | u32 type = TRB_TYPE(TRB_SET_DEQ); |
bf161e85 | 4094 | struct xhci_virt_ep *ep; |
ae636747 | 4095 | |
23e3be11 | 4096 | addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr); |
c92bcfa7 | 4097 | if (addr == 0) { |
ae636747 | 4098 | xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n"); |
700e2052 GKH |
4099 | xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n", |
4100 | deq_seg, deq_ptr); | |
c92bcfa7 SS |
4101 | return 0; |
4102 | } | |
bf161e85 SS |
4103 | ep = &xhci->devs[slot_id]->eps[ep_index]; |
4104 | if ((ep->ep_state & SET_DEQ_PENDING)) { | |
4105 | xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n"); | |
4106 | xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n"); | |
4107 | return 0; | |
4108 | } | |
4109 | ep->queued_deq_seg = deq_seg; | |
4110 | ep->queued_deq_ptr = deq_ptr; | |
95241dbd HG |
4111 | if (stream_id) |
4112 | trb_sct = SCT_FOR_TRB(SCT_PRI_TR); | |
4113 | return queue_command(xhci, lower_32_bits(addr) | trb_sct | cycle_state, | |
e9df17eb | 4114 | upper_32_bits(addr), trb_stream_id, |
913a8a34 | 4115 | trb_slot_id | trb_ep_index | type, false); |
ae636747 | 4116 | } |
a1587d97 SS |
4117 | |
4118 | int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id, | |
4119 | unsigned int ep_index) | |
4120 | { | |
4121 | u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); | |
4122 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); | |
4123 | u32 type = TRB_TYPE(TRB_RESET_EP); | |
4124 | ||
913a8a34 SS |
4125 | return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type, |
4126 | false); | |
a1587d97 | 4127 | } |