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5fd54ace | 1 | // SPDX-License-Identifier: GPL-2.0 |
7f84eef0 SS |
2 | /* |
3 | * xHCI host controller driver | |
4 | * | |
5 | * Copyright (C) 2008 Intel Corp. | |
6 | * | |
7 | * Author: Sarah Sharp | |
8 | * Some code borrowed from the Linux EHCI driver. | |
7f84eef0 SS |
9 | */ |
10 | ||
11 | /* | |
12 | * Ring initialization rules: | |
13 | * 1. Each segment is initialized to zero, except for link TRBs. | |
14 | * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or | |
15 | * Consumer Cycle State (CCS), depending on ring function. | |
16 | * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment. | |
17 | * | |
18 | * Ring behavior rules: | |
19 | * 1. A ring is empty if enqueue == dequeue. This means there will always be at | |
20 | * least one free TRB in the ring. This is useful if you want to turn that | |
21 | * into a link TRB and expand the ring. | |
22 | * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a | |
23 | * link TRB, then load the pointer with the address in the link TRB. If the | |
24 | * link TRB had its toggle bit set, you may need to update the ring cycle | |
25 | * state (see cycle bit rules). You may have to do this multiple times | |
26 | * until you reach a non-link TRB. | |
27 | * 3. A ring is full if enqueue++ (for the definition of increment above) | |
28 | * equals the dequeue pointer. | |
29 | * | |
30 | * Cycle bit rules: | |
31 | * 1. When a consumer increments a dequeue pointer and encounters a toggle bit | |
32 | * in a link TRB, it must toggle the ring cycle state. | |
33 | * 2. When a producer increments an enqueue pointer and encounters a toggle bit | |
34 | * in a link TRB, it must toggle the ring cycle state. | |
35 | * | |
36 | * Producer rules: | |
37 | * 1. Check if ring is full before you enqueue. | |
38 | * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing. | |
39 | * Update enqueue pointer between each write (which may update the ring | |
40 | * cycle state). | |
41 | * 3. Notify consumer. If SW is producer, it rings the doorbell for command | |
42 | * and endpoint rings. If HC is the producer for the event ring, | |
43 | * and it generates an interrupt according to interrupt modulation rules. | |
44 | * | |
45 | * Consumer rules: | |
46 | * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state, | |
47 | * the TRB is owned by the consumer. | |
48 | * 2. Update dequeue pointer (which may update the ring cycle state) and | |
49 | * continue processing TRBs until you reach a TRB which is not owned by you. | |
50 | * 3. Notify the producer. SW is the consumer for the event ring, and it | |
51 | * updates event ring dequeue pointer. HC is the consumer for the command and | |
52 | * endpoint rings; it generates events on the event ring for these. | |
53 | */ | |
54 | ||
8a96c052 | 55 | #include <linux/scatterlist.h> |
5a0e3ad6 | 56 | #include <linux/slab.h> |
f9c589e1 | 57 | #include <linux/dma-mapping.h> |
7f84eef0 | 58 | #include "xhci.h" |
3a7fa5be | 59 | #include "xhci-trace.h" |
0cbd4b34 | 60 | #include "xhci-mtk.h" |
7f84eef0 SS |
61 | |
62 | /* | |
63 | * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA | |
64 | * address of the TRB. | |
65 | */ | |
23e3be11 | 66 | dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, |
7f84eef0 SS |
67 | union xhci_trb *trb) |
68 | { | |
6071d836 | 69 | unsigned long segment_offset; |
7f84eef0 | 70 | |
6071d836 | 71 | if (!seg || !trb || trb < seg->trbs) |
7f84eef0 | 72 | return 0; |
6071d836 SS |
73 | /* offset in TRBs */ |
74 | segment_offset = trb - seg->trbs; | |
7895086a | 75 | if (segment_offset >= TRBS_PER_SEGMENT) |
7f84eef0 | 76 | return 0; |
6071d836 | 77 | return seg->dma + (segment_offset * sizeof(*trb)); |
7f84eef0 SS |
78 | } |
79 | ||
0ce57499 MN |
80 | static bool trb_is_noop(union xhci_trb *trb) |
81 | { | |
82 | return TRB_TYPE_NOOP_LE32(trb->generic.field[3]); | |
83 | } | |
84 | ||
2d98ef40 MN |
85 | static bool trb_is_link(union xhci_trb *trb) |
86 | { | |
87 | return TRB_TYPE_LINK_LE32(trb->link.control); | |
88 | } | |
89 | ||
bd5e67f5 MN |
90 | static bool last_trb_on_seg(struct xhci_segment *seg, union xhci_trb *trb) |
91 | { | |
92 | return trb == &seg->trbs[TRBS_PER_SEGMENT - 1]; | |
93 | } | |
94 | ||
95 | static bool last_trb_on_ring(struct xhci_ring *ring, | |
96 | struct xhci_segment *seg, union xhci_trb *trb) | |
97 | { | |
98 | return last_trb_on_seg(seg, trb) && (seg->next == ring->first_seg); | |
99 | } | |
100 | ||
d0c77d84 MN |
101 | static bool link_trb_toggles_cycle(union xhci_trb *trb) |
102 | { | |
103 | return le32_to_cpu(trb->link.control) & LINK_TOGGLE; | |
104 | } | |
105 | ||
2a72126d MN |
106 | static bool last_td_in_urb(struct xhci_td *td) |
107 | { | |
108 | struct urb_priv *urb_priv = td->urb->hcpriv; | |
109 | ||
9ef7fbbb | 110 | return urb_priv->num_tds_done == urb_priv->num_tds; |
2a72126d MN |
111 | } |
112 | ||
113 | static void inc_td_cnt(struct urb *urb) | |
114 | { | |
115 | struct urb_priv *urb_priv = urb->hcpriv; | |
116 | ||
9ef7fbbb | 117 | urb_priv->num_tds_done++; |
2a72126d MN |
118 | } |
119 | ||
ae1e3f07 MN |
120 | static void trb_to_noop(union xhci_trb *trb, u32 noop_type) |
121 | { | |
122 | if (trb_is_link(trb)) { | |
123 | /* unchain chained link TRBs */ | |
124 | trb->link.control &= cpu_to_le32(~TRB_CHAIN); | |
125 | } else { | |
126 | trb->generic.field[0] = 0; | |
127 | trb->generic.field[1] = 0; | |
128 | trb->generic.field[2] = 0; | |
129 | /* Preserve only the cycle bit of this TRB */ | |
130 | trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE); | |
131 | trb->generic.field[3] |= cpu_to_le32(TRB_TYPE(noop_type)); | |
132 | } | |
133 | } | |
134 | ||
ae636747 SS |
135 | /* Updates trb to point to the next TRB in the ring, and updates seg if the next |
136 | * TRB is in a new segment. This does not skip over link TRBs, and it does not | |
137 | * effect the ring dequeue or enqueue pointers. | |
138 | */ | |
139 | static void next_trb(struct xhci_hcd *xhci, | |
140 | struct xhci_ring *ring, | |
141 | struct xhci_segment **seg, | |
142 | union xhci_trb **trb) | |
143 | { | |
2d98ef40 | 144 | if (trb_is_link(*trb)) { |
ae636747 SS |
145 | *seg = (*seg)->next; |
146 | *trb = ((*seg)->trbs); | |
147 | } else { | |
a1669b2c | 148 | (*trb)++; |
ae636747 SS |
149 | } |
150 | } | |
151 | ||
7f84eef0 SS |
152 | /* |
153 | * See Cycle bit rules. SW is the consumer for the event ring only. | |
154 | * Don't make a ring full of link TRBs. That would be dumb and this would loop. | |
155 | */ | |
67d2ea9f | 156 | void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring) |
7f84eef0 | 157 | { |
bd5e67f5 MN |
158 | /* event ring doesn't have link trbs, check for last trb */ |
159 | if (ring->type == TYPE_EVENT) { | |
160 | if (!last_trb_on_seg(ring->deq_seg, ring->dequeue)) { | |
50d0206f | 161 | ring->dequeue++; |
49d5b05e | 162 | goto out; |
7f84eef0 | 163 | } |
bd5e67f5 MN |
164 | if (last_trb_on_ring(ring, ring->deq_seg, ring->dequeue)) |
165 | ring->cycle_state ^= 1; | |
166 | ring->deq_seg = ring->deq_seg->next; | |
167 | ring->dequeue = ring->deq_seg->trbs; | |
49d5b05e | 168 | goto out; |
bd5e67f5 MN |
169 | } |
170 | ||
171 | /* All other rings have link trbs */ | |
172 | if (!trb_is_link(ring->dequeue)) { | |
173 | ring->dequeue++; | |
174 | ring->num_trbs_free++; | |
175 | } | |
176 | while (trb_is_link(ring->dequeue)) { | |
177 | ring->deq_seg = ring->deq_seg->next; | |
178 | ring->dequeue = ring->deq_seg->trbs; | |
179 | } | |
b2d6edbb | 180 | |
49d5b05e | 181 | out: |
b2d6edbb LB |
182 | trace_xhci_inc_deq(ring); |
183 | ||
bd5e67f5 | 184 | return; |
7f84eef0 SS |
185 | } |
186 | ||
187 | /* | |
188 | * See Cycle bit rules. SW is the consumer for the event ring only. | |
189 | * Don't make a ring full of link TRBs. That would be dumb and this would loop. | |
190 | * | |
191 | * If we've just enqueued a TRB that is in the middle of a TD (meaning the | |
192 | * chain bit is set), then set the chain bit in all the following link TRBs. | |
193 | * If we've enqueued the last TRB in a TD, make sure the following link TRBs | |
194 | * have their chain bit cleared (so that each Link TRB is a separate TD). | |
195 | * | |
196 | * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit | |
b0567b3f SS |
197 | * set, but other sections talk about dealing with the chain bit set. This was |
198 | * fixed in the 0.96 specification errata, but we have to assume that all 0.95 | |
199 | * xHCI hardware can't handle the chain bit being cleared on a link TRB. | |
6cc30d85 SS |
200 | * |
201 | * @more_trbs_coming: Will you enqueue more TRBs before calling | |
202 | * prepare_transfer()? | |
7f84eef0 | 203 | */ |
6cc30d85 | 204 | static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring, |
3b72fca0 | 205 | bool more_trbs_coming) |
7f84eef0 SS |
206 | { |
207 | u32 chain; | |
208 | union xhci_trb *next; | |
209 | ||
28ccd296 | 210 | chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN; |
b008df60 | 211 | /* If this is not event ring, there is one less usable TRB */ |
2d98ef40 | 212 | if (!trb_is_link(ring->enqueue)) |
b008df60 | 213 | ring->num_trbs_free--; |
7f84eef0 SS |
214 | next = ++(ring->enqueue); |
215 | ||
2251198b | 216 | /* Update the dequeue pointer further if that was a link TRB */ |
2d98ef40 | 217 | while (trb_is_link(next)) { |
6cc30d85 | 218 | |
2251198b MN |
219 | /* |
220 | * If the caller doesn't plan on enqueueing more TDs before | |
221 | * ringing the doorbell, then we don't want to give the link TRB | |
222 | * to the hardware just yet. We'll give the link TRB back in | |
223 | * prepare_ring() just before we enqueue the TD at the top of | |
224 | * the ring. | |
225 | */ | |
226 | if (!chain && !more_trbs_coming) | |
227 | break; | |
3b72fca0 | 228 | |
2251198b MN |
229 | /* If we're not dealing with 0.95 hardware or isoc rings on |
230 | * AMD 0.96 host, carry over the chain bit of the previous TRB | |
231 | * (which may mean the chain bit is cleared). | |
232 | */ | |
233 | if (!(ring->type == TYPE_ISOC && | |
234 | (xhci->quirks & XHCI_AMD_0x96_HOST)) && | |
235 | !xhci_link_trb_quirk(xhci)) { | |
236 | next->link.control &= cpu_to_le32(~TRB_CHAIN); | |
237 | next->link.control |= cpu_to_le32(chain); | |
7f84eef0 | 238 | } |
2251198b MN |
239 | /* Give this link TRB to the hardware */ |
240 | wmb(); | |
241 | next->link.control ^= cpu_to_le32(TRB_CYCLE); | |
242 | ||
243 | /* Toggle the cycle bit after the last ring segment. */ | |
d0c77d84 | 244 | if (link_trb_toggles_cycle(next)) |
2251198b MN |
245 | ring->cycle_state ^= 1; |
246 | ||
7f84eef0 SS |
247 | ring->enq_seg = ring->enq_seg->next; |
248 | ring->enqueue = ring->enq_seg->trbs; | |
249 | next = ring->enqueue; | |
250 | } | |
b2d6edbb LB |
251 | |
252 | trace_xhci_inc_enq(ring); | |
7f84eef0 SS |
253 | } |
254 | ||
255 | /* | |
085deb16 AX |
256 | * Check to see if there's room to enqueue num_trbs on the ring and make sure |
257 | * enqueue pointer will not advance into dequeue segment. See rules above. | |
7f84eef0 | 258 | */ |
b008df60 | 259 | static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring, |
7f84eef0 SS |
260 | unsigned int num_trbs) |
261 | { | |
085deb16 | 262 | int num_trbs_in_deq_seg; |
b008df60 | 263 | |
085deb16 AX |
264 | if (ring->num_trbs_free < num_trbs) |
265 | return 0; | |
266 | ||
267 | if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) { | |
268 | num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs; | |
269 | if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg) | |
270 | return 0; | |
271 | } | |
272 | ||
273 | return 1; | |
7f84eef0 SS |
274 | } |
275 | ||
7f84eef0 | 276 | /* Ring the host controller doorbell after placing a command on the ring */ |
23e3be11 | 277 | void xhci_ring_cmd_db(struct xhci_hcd *xhci) |
7f84eef0 | 278 | { |
c181bc5b EF |
279 | if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING)) |
280 | return; | |
281 | ||
7f84eef0 | 282 | xhci_dbg(xhci, "// Ding dong!\n"); |
204b7793 | 283 | writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]); |
7f84eef0 | 284 | /* Flush PCI posted writes */ |
b0ba9720 | 285 | readl(&xhci->dba->doorbell[0]); |
7f84eef0 SS |
286 | } |
287 | ||
cb4d5ce5 OH |
288 | static bool xhci_mod_cmd_timer(struct xhci_hcd *xhci, unsigned long delay) |
289 | { | |
290 | return mod_delayed_work(system_wq, &xhci->cmd_timer, delay); | |
291 | } | |
292 | ||
1c111b6c OH |
293 | static struct xhci_command *xhci_next_queued_cmd(struct xhci_hcd *xhci) |
294 | { | |
295 | return list_first_entry_or_null(&xhci->cmd_list, struct xhci_command, | |
296 | cmd_list); | |
297 | } | |
298 | ||
299 | /* | |
300 | * Turn all commands on command ring with status set to "aborted" to no-op trbs. | |
301 | * If there are other commands waiting then restart the ring and kick the timer. | |
302 | * This must be called with command ring stopped and xhci->lock held. | |
303 | */ | |
304 | static void xhci_handle_stopped_cmd_ring(struct xhci_hcd *xhci, | |
305 | struct xhci_command *cur_cmd) | |
306 | { | |
307 | struct xhci_command *i_cmd; | |
1c111b6c OH |
308 | |
309 | /* Turn all aborted commands in list to no-ops, then restart */ | |
310 | list_for_each_entry(i_cmd, &xhci->cmd_list, cmd_list) { | |
311 | ||
0b7c105a | 312 | if (i_cmd->status != COMP_COMMAND_ABORTED) |
1c111b6c OH |
313 | continue; |
314 | ||
604d02a2 | 315 | i_cmd->status = COMP_COMMAND_RING_STOPPED; |
1c111b6c OH |
316 | |
317 | xhci_dbg(xhci, "Turn aborted command %p to no-op\n", | |
318 | i_cmd->command_trb); | |
5278204c MN |
319 | |
320 | trb_to_noop(i_cmd->command_trb, TRB_CMD_NOOP); | |
1c111b6c OH |
321 | |
322 | /* | |
323 | * caller waiting for completion is called when command | |
324 | * completion event is received for these no-op commands | |
325 | */ | |
326 | } | |
327 | ||
328 | xhci->cmd_ring_state = CMD_RING_STATE_RUNNING; | |
329 | ||
330 | /* ring command ring doorbell to restart the command ring */ | |
331 | if ((xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue) && | |
332 | !(xhci->xhc_state & XHCI_STATE_DYING)) { | |
333 | xhci->current_cmd = cur_cmd; | |
334 | xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT); | |
335 | xhci_ring_cmd_db(xhci); | |
336 | } | |
337 | } | |
338 | ||
339 | /* Must be called with xhci->lock held, releases and aquires lock back */ | |
340 | static int xhci_abort_cmd_ring(struct xhci_hcd *xhci, unsigned long flags) | |
b92cc66c EF |
341 | { |
342 | u64 temp_64; | |
343 | int ret; | |
344 | ||
345 | xhci_dbg(xhci, "Abort command ring\n"); | |
346 | ||
1c111b6c | 347 | reinit_completion(&xhci->cmd_ring_stop_completion); |
3425aa03 | 348 | |
1c111b6c | 349 | temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring); |
477632df SS |
350 | xhci_write_64(xhci, temp_64 | CMD_RING_ABORT, |
351 | &xhci->op_regs->cmd_ring); | |
b92cc66c | 352 | |
d9f11ba9 MN |
353 | /* Section 4.6.1.2 of xHCI 1.0 spec says software should also time the |
354 | * completion of the Command Abort operation. If CRR is not negated in 5 | |
355 | * seconds then driver handles it as if host died (-ENODEV). | |
356 | * In the future we should distinguish between -ENODEV and -ETIMEDOUT | |
357 | * and try to recover a -ETIMEDOUT with a host controller reset. | |
b92cc66c | 358 | */ |
dc0b177c | 359 | ret = xhci_handshake(&xhci->op_regs->cmd_ring, |
b92cc66c EF |
360 | CMD_RING_RUNNING, 0, 5 * 1000 * 1000); |
361 | if (ret < 0) { | |
d9f11ba9 | 362 | xhci_err(xhci, "Abort failed to stop command ring: %d\n", ret); |
1cc6d861 | 363 | xhci_halt(xhci); |
d9f11ba9 MN |
364 | xhci_hc_died(xhci); |
365 | return ret; | |
1c111b6c OH |
366 | } |
367 | /* | |
368 | * Writing the CMD_RING_ABORT bit should cause a cmd completion event, | |
369 | * however on some host hw the CMD_RING_RUNNING bit is correctly cleared | |
370 | * but the completion event in never sent. Wait 2 secs (arbitrary | |
371 | * number) to handle those cases after negation of CMD_RING_RUNNING. | |
372 | */ | |
373 | spin_unlock_irqrestore(&xhci->lock, flags); | |
374 | ret = wait_for_completion_timeout(&xhci->cmd_ring_stop_completion, | |
375 | msecs_to_jiffies(2000)); | |
376 | spin_lock_irqsave(&xhci->lock, flags); | |
377 | if (!ret) { | |
378 | xhci_dbg(xhci, "No stop event for abort, ring start fail?\n"); | |
379 | xhci_cleanup_command_queue(xhci); | |
380 | } else { | |
381 | xhci_handle_stopped_cmd_ring(xhci, xhci_next_queued_cmd(xhci)); | |
b92cc66c | 382 | } |
b92cc66c EF |
383 | return 0; |
384 | } | |
385 | ||
be88fe4f | 386 | void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, |
ae636747 | 387 | unsigned int slot_id, |
e9df17eb SS |
388 | unsigned int ep_index, |
389 | unsigned int stream_id) | |
ae636747 | 390 | { |
28ccd296 | 391 | __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id]; |
50d64676 MW |
392 | struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index]; |
393 | unsigned int ep_state = ep->ep_state; | |
ae636747 | 394 | |
ae636747 | 395 | /* Don't ring the doorbell for this endpoint if there are pending |
50d64676 | 396 | * cancellations because we don't want to interrupt processing. |
8df75f42 SS |
397 | * We don't want to restart any stream rings if there's a set dequeue |
398 | * pointer command pending because the device can choose to start any | |
399 | * stream once the endpoint is on the HW schedule. | |
ae636747 | 400 | */ |
9983a5fc | 401 | if ((ep_state & EP_STOP_CMD_PENDING) || (ep_state & SET_DEQ_PENDING) || |
50d64676 MW |
402 | (ep_state & EP_HALTED)) |
403 | return; | |
204b7793 | 404 | writel(DB_VALUE(ep_index, stream_id), db_addr); |
50d64676 MW |
405 | /* The CPU has better things to do at this point than wait for a |
406 | * write-posting flush. It'll get there soon enough. | |
407 | */ | |
ae636747 SS |
408 | } |
409 | ||
e9df17eb SS |
410 | /* Ring the doorbell for any rings with pending URBs */ |
411 | static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci, | |
412 | unsigned int slot_id, | |
413 | unsigned int ep_index) | |
414 | { | |
415 | unsigned int stream_id; | |
416 | struct xhci_virt_ep *ep; | |
417 | ||
418 | ep = &xhci->devs[slot_id]->eps[ep_index]; | |
419 | ||
420 | /* A ring has pending URBs if its TD list is not empty */ | |
421 | if (!(ep->ep_state & EP_HAS_STREAMS)) { | |
d66eaf9f | 422 | if (ep->ring && !(list_empty(&ep->ring->td_list))) |
be88fe4f | 423 | xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0); |
e9df17eb SS |
424 | return; |
425 | } | |
426 | ||
427 | for (stream_id = 1; stream_id < ep->stream_info->num_streams; | |
428 | stream_id++) { | |
429 | struct xhci_stream_info *stream_info = ep->stream_info; | |
430 | if (!list_empty(&stream_info->stream_rings[stream_id]->td_list)) | |
be88fe4f AX |
431 | xhci_ring_ep_doorbell(xhci, slot_id, ep_index, |
432 | stream_id); | |
e9df17eb SS |
433 | } |
434 | } | |
435 | ||
75b040ec AI |
436 | /* Get the right ring for the given slot_id, ep_index and stream_id. |
437 | * If the endpoint supports streams, boundary check the URB's stream ID. | |
438 | * If the endpoint doesn't support streams, return the singular endpoint ring. | |
439 | */ | |
440 | struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci, | |
021bff91 SS |
441 | unsigned int slot_id, unsigned int ep_index, |
442 | unsigned int stream_id) | |
443 | { | |
444 | struct xhci_virt_ep *ep; | |
445 | ||
446 | ep = &xhci->devs[slot_id]->eps[ep_index]; | |
447 | /* Common case: no streams */ | |
448 | if (!(ep->ep_state & EP_HAS_STREAMS)) | |
449 | return ep->ring; | |
450 | ||
451 | if (stream_id == 0) { | |
452 | xhci_warn(xhci, | |
453 | "WARN: Slot ID %u, ep index %u has streams, " | |
454 | "but URB has no stream ID.\n", | |
455 | slot_id, ep_index); | |
456 | return NULL; | |
457 | } | |
458 | ||
459 | if (stream_id < ep->stream_info->num_streams) | |
460 | return ep->stream_info->stream_rings[stream_id]; | |
461 | ||
462 | xhci_warn(xhci, | |
463 | "WARN: Slot ID %u, ep index %u has " | |
464 | "stream IDs 1 to %u allocated, " | |
465 | "but stream ID %u is requested.\n", | |
466 | slot_id, ep_index, | |
467 | ep->stream_info->num_streams - 1, | |
468 | stream_id); | |
469 | return NULL; | |
470 | } | |
471 | ||
e6b20121 MN |
472 | |
473 | /* | |
474 | * Get the hw dequeue pointer xHC stopped on, either directly from the | |
475 | * endpoint context, or if streams are in use from the stream context. | |
476 | * The returned hw_dequeue contains the lowest four bits with cycle state | |
477 | * and possbile stream context type. | |
478 | */ | |
479 | static u64 xhci_get_hw_deq(struct xhci_hcd *xhci, struct xhci_virt_device *vdev, | |
480 | unsigned int ep_index, unsigned int stream_id) | |
481 | { | |
482 | struct xhci_ep_ctx *ep_ctx; | |
483 | struct xhci_stream_ctx *st_ctx; | |
484 | struct xhci_virt_ep *ep; | |
485 | ||
486 | ep = &vdev->eps[ep_index]; | |
487 | ||
488 | if (ep->ep_state & EP_HAS_STREAMS) { | |
489 | st_ctx = &ep->stream_info->stream_ctx_array[stream_id]; | |
490 | return le64_to_cpu(st_ctx->stream_ring); | |
491 | } | |
492 | ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index); | |
493 | return le64_to_cpu(ep_ctx->deq); | |
494 | } | |
495 | ||
ae636747 SS |
496 | /* |
497 | * Move the xHC's endpoint ring dequeue pointer past cur_td. | |
498 | * Record the new state of the xHC's endpoint ring dequeue segment, | |
8790736d | 499 | * dequeue pointer, stream id, and new consumer cycle state in state. |
ae636747 SS |
500 | * Update our internal representation of the ring's dequeue pointer. |
501 | * | |
502 | * We do this in three jumps: | |
503 | * - First we update our new ring state to be the same as when the xHC stopped. | |
504 | * - Then we traverse the ring to find the segment that contains | |
505 | * the last TRB in the TD. We toggle the xHC's new cycle state when we pass | |
506 | * any link TRBs with the toggle cycle bit set. | |
507 | * - Finally we move the dequeue state one TRB further, toggling the cycle bit | |
508 | * if we've moved it past a link TRB with the toggle cycle bit set. | |
28ccd296 ME |
509 | * |
510 | * Some of the uses of xhci_generic_trb are grotty, but if they're done | |
511 | * with correct __le32 accesses they should work fine. Only users of this are | |
512 | * in here. | |
ae636747 | 513 | */ |
c92bcfa7 | 514 | void xhci_find_new_dequeue_state(struct xhci_hcd *xhci, |
ae636747 | 515 | unsigned int slot_id, unsigned int ep_index, |
e9df17eb SS |
516 | unsigned int stream_id, struct xhci_td *cur_td, |
517 | struct xhci_dequeue_state *state) | |
ae636747 SS |
518 | { |
519 | struct xhci_virt_device *dev = xhci->devs[slot_id]; | |
c4bedb77 | 520 | struct xhci_virt_ep *ep = &dev->eps[ep_index]; |
e9df17eb | 521 | struct xhci_ring *ep_ring; |
365038d8 MN |
522 | struct xhci_segment *new_seg; |
523 | union xhci_trb *new_deq; | |
c92bcfa7 | 524 | dma_addr_t addr; |
1f81b6d2 | 525 | u64 hw_dequeue; |
365038d8 MN |
526 | bool cycle_found = false; |
527 | bool td_last_trb_found = false; | |
ae636747 | 528 | |
e9df17eb SS |
529 | ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id, |
530 | ep_index, stream_id); | |
531 | if (!ep_ring) { | |
532 | xhci_warn(xhci, "WARN can't find new dequeue state " | |
533 | "for invalid stream ID %u.\n", | |
534 | stream_id); | |
535 | return; | |
536 | } | |
ae636747 | 537 | /* Dig out the cycle state saved by the xHC during the stop ep cmd */ |
aa50b290 XR |
538 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
539 | "Finding endpoint context"); | |
ae636747 | 540 | |
e6b20121 | 541 | hw_dequeue = xhci_get_hw_deq(xhci, dev, ep_index, stream_id); |
365038d8 MN |
542 | new_seg = ep_ring->deq_seg; |
543 | new_deq = ep_ring->dequeue; | |
544 | state->new_cycle_state = hw_dequeue & 0x1; | |
8790736d | 545 | state->stream_id = stream_id; |
365038d8 | 546 | |
1f81b6d2 | 547 | /* |
365038d8 MN |
548 | * We want to find the pointer, segment and cycle state of the new trb |
549 | * (the one after current TD's last_trb). We know the cycle state at | |
550 | * hw_dequeue, so walk the ring until both hw_dequeue and last_trb are | |
551 | * found. | |
1f81b6d2 | 552 | */ |
365038d8 MN |
553 | do { |
554 | if (!cycle_found && xhci_trb_virt_to_dma(new_seg, new_deq) | |
555 | == (dma_addr_t)(hw_dequeue & ~0xf)) { | |
556 | cycle_found = true; | |
557 | if (td_last_trb_found) | |
558 | break; | |
559 | } | |
560 | if (new_deq == cur_td->last_trb) | |
561 | td_last_trb_found = true; | |
1f81b6d2 | 562 | |
3495e451 MN |
563 | if (cycle_found && trb_is_link(new_deq) && |
564 | link_trb_toggles_cycle(new_deq)) | |
365038d8 MN |
565 | state->new_cycle_state ^= 0x1; |
566 | ||
567 | next_trb(xhci, ep_ring, &new_seg, &new_deq); | |
568 | ||
569 | /* Search wrapped around, bail out */ | |
570 | if (new_deq == ep->ring->dequeue) { | |
571 | xhci_err(xhci, "Error: Failed finding new dequeue state\n"); | |
572 | state->new_deq_seg = NULL; | |
573 | state->new_deq_ptr = NULL; | |
574 | return; | |
575 | } | |
576 | ||
577 | } while (!cycle_found || !td_last_trb_found); | |
ae636747 | 578 | |
365038d8 MN |
579 | state->new_deq_seg = new_seg; |
580 | state->new_deq_ptr = new_deq; | |
ae636747 | 581 | |
1f81b6d2 | 582 | /* Don't update the ring cycle state for the producer (us). */ |
aa50b290 XR |
583 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
584 | "Cycle state = 0x%x", state->new_cycle_state); | |
01a1fdb9 | 585 | |
aa50b290 XR |
586 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
587 | "New dequeue segment = %p (virtual)", | |
c92bcfa7 SS |
588 | state->new_deq_seg); |
589 | addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr); | |
aa50b290 XR |
590 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
591 | "New dequeue pointer = 0x%llx (DMA)", | |
c92bcfa7 | 592 | (unsigned long long) addr); |
ae636747 SS |
593 | } |
594 | ||
522989a2 SS |
595 | /* flip_cycle means flip the cycle bit of all but the first and last TRB. |
596 | * (The last TRB actually points to the ring enqueue pointer, which is not part | |
597 | * of this TD.) This is used to remove partially enqueued isoc TDs from a ring. | |
598 | */ | |
23e3be11 | 599 | static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring, |
0d58a1a0 | 600 | struct xhci_td *td, bool flip_cycle) |
ae636747 | 601 | { |
0d58a1a0 MN |
602 | struct xhci_segment *seg = td->start_seg; |
603 | union xhci_trb *trb = td->first_trb; | |
604 | ||
605 | while (1) { | |
ae1e3f07 MN |
606 | trb_to_noop(trb, TRB_TR_NOOP); |
607 | ||
0d58a1a0 MN |
608 | /* flip cycle if asked to */ |
609 | if (flip_cycle && trb != td->first_trb && trb != td->last_trb) | |
610 | trb->generic.field[3] ^= cpu_to_le32(TRB_CYCLE); | |
611 | ||
612 | if (trb == td->last_trb) | |
ae636747 | 613 | break; |
0d58a1a0 MN |
614 | |
615 | next_trb(xhci, ep_ring, &seg, &trb); | |
ae636747 SS |
616 | } |
617 | } | |
618 | ||
575688e1 | 619 | static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci, |
6f5165cf SS |
620 | struct xhci_virt_ep *ep) |
621 | { | |
9983a5fc | 622 | ep->ep_state &= ~EP_STOP_CMD_PENDING; |
f9926596 MN |
623 | /* Can't del_timer_sync in interrupt */ |
624 | del_timer(&ep->stop_cmd_timer); | |
6f5165cf SS |
625 | } |
626 | ||
2a72126d MN |
627 | /* |
628 | * Must be called with xhci->lock held in interrupt context, | |
629 | * releases and re-acquires xhci->lock | |
630 | */ | |
6f5165cf | 631 | static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci, |
2a72126d | 632 | struct xhci_td *cur_td, int status) |
6f5165cf | 633 | { |
2a72126d MN |
634 | struct urb *urb = cur_td->urb; |
635 | struct urb_priv *urb_priv = urb->hcpriv; | |
636 | struct usb_hcd *hcd = bus_to_hcd(urb->dev->bus); | |
637 | ||
638 | if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { | |
639 | xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--; | |
640 | if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) { | |
641 | if (xhci->quirks & XHCI_AMD_PLL_FIX) | |
642 | usb_amd_quirk_pll_enable(); | |
c41136b0 | 643 | } |
8e51adcc | 644 | } |
446b3141 | 645 | xhci_urb_free_priv(urb_priv); |
2a72126d | 646 | usb_hcd_unlink_urb_from_ep(hcd, urb); |
446b3141 | 647 | spin_unlock(&xhci->lock); |
5abdc2e6 | 648 | trace_xhci_urb_giveback(urb); |
7bc5d5af | 649 | usb_hcd_giveback_urb(hcd, urb, status); |
446b3141 MN |
650 | spin_lock(&xhci->lock); |
651 | } | |
652 | ||
2d6d5769 WY |
653 | static void xhci_unmap_td_bounce_buffer(struct xhci_hcd *xhci, |
654 | struct xhci_ring *ring, struct xhci_td *td) | |
f9c589e1 MN |
655 | { |
656 | struct device *dev = xhci_to_hcd(xhci)->self.controller; | |
657 | struct xhci_segment *seg = td->bounce_seg; | |
658 | struct urb *urb = td->urb; | |
597c56e3 | 659 | size_t len; |
f9c589e1 | 660 | |
f45e2a02 | 661 | if (!ring || !seg || !urb) |
f9c589e1 MN |
662 | return; |
663 | ||
664 | if (usb_urb_dir_out(urb)) { | |
665 | dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len, | |
666 | DMA_TO_DEVICE); | |
667 | return; | |
668 | } | |
669 | ||
f9c589e1 MN |
670 | dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len, |
671 | DMA_FROM_DEVICE); | |
597c56e3 HL |
672 | /* for in tranfers we need to copy the data from bounce to sg */ |
673 | len = sg_pcopy_from_buffer(urb->sg, urb->num_sgs, seg->bounce_buf, | |
674 | seg->bounce_len, seg->bounce_offs); | |
675 | if (len != seg->bounce_len) | |
676 | xhci_warn(xhci, "WARN Wrong bounce buffer read length: %ld != %d\n", | |
677 | len, seg->bounce_len); | |
f9c589e1 MN |
678 | seg->bounce_len = 0; |
679 | seg->bounce_offs = 0; | |
680 | } | |
681 | ||
ae636747 SS |
682 | /* |
683 | * When we get a command completion for a Stop Endpoint Command, we need to | |
684 | * unlink any cancelled TDs from the ring. There are two ways to do that: | |
685 | * | |
686 | * 1. If the HW was in the middle of processing the TD that needs to be | |
687 | * cancelled, then we must move the ring's dequeue pointer past the last TRB | |
688 | * in the TD with a Set Dequeue Pointer Command. | |
689 | * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain | |
690 | * bit cleared) so that the HW will skip over them. | |
691 | */ | |
b8200c94 | 692 | static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id, |
be88fe4f | 693 | union xhci_trb *trb, struct xhci_event_cmd *event) |
ae636747 | 694 | { |
ae636747 SS |
695 | unsigned int ep_index; |
696 | struct xhci_ring *ep_ring; | |
63a0d9ab | 697 | struct xhci_virt_ep *ep; |
326b4810 | 698 | struct xhci_td *cur_td = NULL; |
ae636747 | 699 | struct xhci_td *last_unlinked_td; |
19a7d0d6 FB |
700 | struct xhci_ep_ctx *ep_ctx; |
701 | struct xhci_virt_device *vdev; | |
cdd504e1 | 702 | u64 hw_deq; |
c92bcfa7 | 703 | struct xhci_dequeue_state deq_state; |
ae636747 | 704 | |
bc752bde | 705 | if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) { |
9ea1833e | 706 | if (!xhci->devs[slot_id]) |
be88fe4f AX |
707 | xhci_warn(xhci, "Stop endpoint command " |
708 | "completion for disabled slot %u\n", | |
709 | slot_id); | |
710 | return; | |
711 | } | |
712 | ||
ae636747 | 713 | memset(&deq_state, 0, sizeof(deq_state)); |
28ccd296 | 714 | ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); |
19a7d0d6 FB |
715 | |
716 | vdev = xhci->devs[slot_id]; | |
717 | ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index); | |
718 | trace_xhci_handle_cmd_stop_ep(ep_ctx); | |
719 | ||
63a0d9ab | 720 | ep = &xhci->devs[slot_id]->eps[ep_index]; |
04861f83 FB |
721 | last_unlinked_td = list_last_entry(&ep->cancelled_td_list, |
722 | struct xhci_td, cancelled_td_list); | |
ae636747 | 723 | |
678539cf | 724 | if (list_empty(&ep->cancelled_td_list)) { |
6f5165cf | 725 | xhci_stop_watchdog_timer_in_irq(xhci, ep); |
e9df17eb | 726 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); |
ae636747 | 727 | return; |
678539cf | 728 | } |
ae636747 SS |
729 | |
730 | /* Fix up the ep ring first, so HW stops executing cancelled TDs. | |
731 | * We have the xHCI lock, so nothing can modify this list until we drop | |
732 | * it. We're also in the event handler, so we can't get re-interrupted | |
733 | * if another Stop Endpoint command completes | |
734 | */ | |
04861f83 | 735 | list_for_each_entry(cur_td, &ep->cancelled_td_list, cancelled_td_list) { |
aa50b290 XR |
736 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
737 | "Removing canceled TD starting at 0x%llx (dma).", | |
79688acf SS |
738 | (unsigned long long)xhci_trb_virt_to_dma( |
739 | cur_td->start_seg, cur_td->first_trb)); | |
e9df17eb SS |
740 | ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb); |
741 | if (!ep_ring) { | |
742 | /* This shouldn't happen unless a driver is mucking | |
743 | * with the stream ID after submission. This will | |
744 | * leave the TD on the hardware ring, and the hardware | |
745 | * will try to execute it, and may access a buffer | |
746 | * that has already been freed. In the best case, the | |
747 | * hardware will execute it, and the event handler will | |
748 | * ignore the completion event for that TD, since it was | |
749 | * removed from the td_list for that endpoint. In | |
750 | * short, don't muck with the stream ID after | |
751 | * submission. | |
752 | */ | |
753 | xhci_warn(xhci, "WARN Cancelled URB %p " | |
754 | "has invalid stream ID %u.\n", | |
755 | cur_td->urb, | |
756 | cur_td->urb->stream_id); | |
757 | goto remove_finished_td; | |
758 | } | |
ae636747 SS |
759 | /* |
760 | * If we stopped on the TD we need to cancel, then we have to | |
761 | * move the xHC endpoint ring dequeue pointer past this TD. | |
762 | */ | |
cdd504e1 MN |
763 | hw_deq = xhci_get_hw_deq(xhci, vdev, ep_index, |
764 | cur_td->urb->stream_id); | |
765 | hw_deq &= ~0xf; | |
766 | ||
767 | if (trb_in_td(xhci, cur_td->start_seg, cur_td->first_trb, | |
768 | cur_td->last_trb, hw_deq, false)) { | |
e9df17eb | 769 | xhci_find_new_dequeue_state(xhci, slot_id, ep_index, |
cdd504e1 MN |
770 | cur_td->urb->stream_id, |
771 | cur_td, &deq_state); | |
772 | } else { | |
522989a2 | 773 | td_to_noop(xhci, ep_ring, cur_td, false); |
cdd504e1 MN |
774 | } |
775 | ||
e9df17eb | 776 | remove_finished_td: |
ae636747 SS |
777 | /* |
778 | * The event handler won't see a completion for this TD anymore, | |
779 | * so remove it from the endpoint ring's TD list. Keep it in | |
780 | * the cancelled TD list for URB completion later. | |
781 | */ | |
585df1d9 | 782 | list_del_init(&cur_td->td_list); |
ae636747 | 783 | } |
04861f83 | 784 | |
6f5165cf | 785 | xhci_stop_watchdog_timer_in_irq(xhci, ep); |
ae636747 SS |
786 | |
787 | /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */ | |
788 | if (deq_state.new_deq_ptr && deq_state.new_deq_seg) { | |
1e3452e3 | 789 | xhci_queue_new_dequeue_state(xhci, slot_id, ep_index, |
8790736d | 790 | &deq_state); |
ac9d8fe7 | 791 | xhci_ring_cmd_db(xhci); |
ae636747 | 792 | } else { |
e9df17eb SS |
793 | /* Otherwise ring the doorbell(s) to restart queued transfers */ |
794 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); | |
ae636747 | 795 | } |
526867c3 | 796 | |
ae636747 SS |
797 | /* |
798 | * Drop the lock and complete the URBs in the cancelled TD list. | |
799 | * New TDs to be cancelled might be added to the end of the list before | |
800 | * we can complete all the URBs for the TDs we already unlinked. | |
801 | * So stop when we've completed the URB for the last TD we unlinked. | |
802 | */ | |
803 | do { | |
04861f83 | 804 | cur_td = list_first_entry(&ep->cancelled_td_list, |
ae636747 | 805 | struct xhci_td, cancelled_td_list); |
585df1d9 | 806 | list_del_init(&cur_td->cancelled_td_list); |
ae636747 SS |
807 | |
808 | /* Clean up the cancelled URB */ | |
ae636747 SS |
809 | /* Doesn't matter what we pass for status, since the core will |
810 | * just overwrite it (because the URB has been unlinked). | |
811 | */ | |
f76a28a6 | 812 | ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb); |
a60f2f2f | 813 | xhci_unmap_td_bounce_buffer(xhci, ep_ring, cur_td); |
2a72126d MN |
814 | inc_td_cnt(cur_td->urb); |
815 | if (last_td_in_urb(cur_td)) | |
816 | xhci_giveback_urb_in_irq(xhci, cur_td, 0); | |
ae636747 | 817 | |
6f5165cf SS |
818 | /* Stop processing the cancelled list if the watchdog timer is |
819 | * running. | |
820 | */ | |
821 | if (xhci->xhc_state & XHCI_STATE_DYING) | |
822 | return; | |
ae636747 SS |
823 | } while (cur_td != last_unlinked_td); |
824 | ||
825 | /* Return to the event handler with xhci->lock re-acquired */ | |
826 | } | |
827 | ||
50e8725e SS |
828 | static void xhci_kill_ring_urbs(struct xhci_hcd *xhci, struct xhci_ring *ring) |
829 | { | |
830 | struct xhci_td *cur_td; | |
a54cfae3 | 831 | struct xhci_td *tmp; |
50e8725e | 832 | |
a54cfae3 | 833 | list_for_each_entry_safe(cur_td, tmp, &ring->td_list, td_list) { |
50e8725e | 834 | list_del_init(&cur_td->td_list); |
a54cfae3 | 835 | |
50e8725e SS |
836 | if (!list_empty(&cur_td->cancelled_td_list)) |
837 | list_del_init(&cur_td->cancelled_td_list); | |
f9c589e1 | 838 | |
a60f2f2f | 839 | xhci_unmap_td_bounce_buffer(xhci, ring, cur_td); |
2a72126d MN |
840 | |
841 | inc_td_cnt(cur_td->urb); | |
842 | if (last_td_in_urb(cur_td)) | |
843 | xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN); | |
50e8725e SS |
844 | } |
845 | } | |
846 | ||
847 | static void xhci_kill_endpoint_urbs(struct xhci_hcd *xhci, | |
848 | int slot_id, int ep_index) | |
849 | { | |
850 | struct xhci_td *cur_td; | |
a54cfae3 | 851 | struct xhci_td *tmp; |
50e8725e SS |
852 | struct xhci_virt_ep *ep; |
853 | struct xhci_ring *ring; | |
854 | ||
855 | ep = &xhci->devs[slot_id]->eps[ep_index]; | |
21d0e51b SS |
856 | if ((ep->ep_state & EP_HAS_STREAMS) || |
857 | (ep->ep_state & EP_GETTING_NO_STREAMS)) { | |
858 | int stream_id; | |
859 | ||
4b895868 | 860 | for (stream_id = 1; stream_id < ep->stream_info->num_streams; |
21d0e51b | 861 | stream_id++) { |
4b895868 MN |
862 | ring = ep->stream_info->stream_rings[stream_id]; |
863 | if (!ring) | |
864 | continue; | |
865 | ||
21d0e51b SS |
866 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
867 | "Killing URBs for slot ID %u, ep index %u, stream %u", | |
4b895868 MN |
868 | slot_id, ep_index, stream_id); |
869 | xhci_kill_ring_urbs(xhci, ring); | |
21d0e51b SS |
870 | } |
871 | } else { | |
872 | ring = ep->ring; | |
873 | if (!ring) | |
874 | return; | |
875 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, | |
876 | "Killing URBs for slot ID %u, ep index %u", | |
877 | slot_id, ep_index); | |
878 | xhci_kill_ring_urbs(xhci, ring); | |
879 | } | |
2a72126d | 880 | |
a54cfae3 FB |
881 | list_for_each_entry_safe(cur_td, tmp, &ep->cancelled_td_list, |
882 | cancelled_td_list) { | |
883 | list_del_init(&cur_td->cancelled_td_list); | |
2a72126d | 884 | inc_td_cnt(cur_td->urb); |
a54cfae3 | 885 | |
2a72126d MN |
886 | if (last_td_in_urb(cur_td)) |
887 | xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN); | |
50e8725e SS |
888 | } |
889 | } | |
890 | ||
d9f11ba9 MN |
891 | /* |
892 | * host controller died, register read returns 0xffffffff | |
893 | * Complete pending commands, mark them ABORTED. | |
894 | * URBs need to be given back as usb core might be waiting with device locks | |
895 | * held for the URBs to finish during device disconnect, blocking host remove. | |
896 | * | |
897 | * Call with xhci->lock held. | |
898 | * lock is relased and re-acquired while giving back urb. | |
899 | */ | |
900 | void xhci_hc_died(struct xhci_hcd *xhci) | |
901 | { | |
902 | int i, j; | |
903 | ||
904 | if (xhci->xhc_state & XHCI_STATE_DYING) | |
905 | return; | |
906 | ||
907 | xhci_err(xhci, "xHCI host controller not responding, assume dead\n"); | |
908 | xhci->xhc_state |= XHCI_STATE_DYING; | |
909 | ||
910 | xhci_cleanup_command_queue(xhci); | |
911 | ||
912 | /* return any pending urbs, remove may be waiting for them */ | |
913 | for (i = 0; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) { | |
914 | if (!xhci->devs[i]) | |
915 | continue; | |
916 | for (j = 0; j < 31; j++) | |
917 | xhci_kill_endpoint_urbs(xhci, i, j); | |
918 | } | |
919 | ||
920 | /* inform usb core hc died if PCI remove isn't already handling it */ | |
921 | if (!(xhci->xhc_state & XHCI_STATE_REMOVING)) | |
922 | usb_hc_died(xhci_to_hcd(xhci)); | |
923 | } | |
924 | ||
6f5165cf SS |
925 | /* Watchdog timer function for when a stop endpoint command fails to complete. |
926 | * In this case, we assume the host controller is broken or dying or dead. The | |
927 | * host may still be completing some other events, so we have to be careful to | |
928 | * let the event ring handler and the URB dequeueing/enqueueing functions know | |
929 | * through xhci->state. | |
930 | * | |
931 | * The timer may also fire if the host takes a very long time to respond to the | |
932 | * command, and the stop endpoint command completion handler cannot delete the | |
933 | * timer before the timer function is called. Another endpoint cancellation may | |
934 | * sneak in before the timer function can grab the lock, and that may queue | |
935 | * another stop endpoint command and add the timer back. So we cannot use a | |
936 | * simple flag to say whether there is a pending stop endpoint command for a | |
937 | * particular endpoint. | |
938 | * | |
f9926596 MN |
939 | * Instead we use a combination of that flag and checking if a new timer is |
940 | * pending. | |
6f5165cf | 941 | */ |
66a45503 | 942 | void xhci_stop_endpoint_command_watchdog(struct timer_list *t) |
6f5165cf | 943 | { |
66a45503 KC |
944 | struct xhci_virt_ep *ep = from_timer(ep, t, stop_cmd_timer); |
945 | struct xhci_hcd *xhci = ep->xhci; | |
f43d6231 | 946 | unsigned long flags; |
6f5165cf | 947 | |
f43d6231 | 948 | spin_lock_irqsave(&xhci->lock, flags); |
6f5165cf | 949 | |
f9926596 MN |
950 | /* bail out if cmd completed but raced with stop ep watchdog timer.*/ |
951 | if (!(ep->ep_state & EP_STOP_CMD_PENDING) || | |
952 | timer_pending(&ep->stop_cmd_timer)) { | |
f43d6231 | 953 | spin_unlock_irqrestore(&xhci->lock, flags); |
f9926596 | 954 | xhci_dbg(xhci, "Stop EP timer raced with cmd completion, exit"); |
6f5165cf SS |
955 | return; |
956 | } | |
957 | ||
958 | xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n"); | |
f9926596 MN |
959 | ep->ep_state &= ~EP_STOP_CMD_PENDING; |
960 | ||
d9f11ba9 | 961 | xhci_halt(xhci); |
6f5165cf | 962 | |
d9f11ba9 MN |
963 | /* |
964 | * handle a stop endpoint cmd timeout as if host died (-ENODEV). | |
965 | * In the future we could distinguish between -ENODEV and -ETIMEDOUT | |
966 | * and try to recover a -ETIMEDOUT with a host controller reset | |
967 | */ | |
968 | xhci_hc_died(xhci); | |
6f5165cf | 969 | |
f43d6231 | 970 | spin_unlock_irqrestore(&xhci->lock, flags); |
aa50b290 XR |
971 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
972 | "xHCI host controller is dead."); | |
6f5165cf SS |
973 | } |
974 | ||
b008df60 AX |
975 | static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci, |
976 | struct xhci_virt_device *dev, | |
977 | struct xhci_ring *ep_ring, | |
978 | unsigned int ep_index) | |
979 | { | |
980 | union xhci_trb *dequeue_temp; | |
981 | int num_trbs_free_temp; | |
982 | bool revert = false; | |
983 | ||
984 | num_trbs_free_temp = ep_ring->num_trbs_free; | |
985 | dequeue_temp = ep_ring->dequeue; | |
986 | ||
0d9f78a9 SS |
987 | /* If we get two back-to-back stalls, and the first stalled transfer |
988 | * ends just before a link TRB, the dequeue pointer will be left on | |
989 | * the link TRB by the code in the while loop. So we have to update | |
990 | * the dequeue pointer one segment further, or we'll jump off | |
991 | * the segment into la-la-land. | |
992 | */ | |
2d98ef40 | 993 | if (trb_is_link(ep_ring->dequeue)) { |
0d9f78a9 SS |
994 | ep_ring->deq_seg = ep_ring->deq_seg->next; |
995 | ep_ring->dequeue = ep_ring->deq_seg->trbs; | |
996 | } | |
997 | ||
b008df60 AX |
998 | while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) { |
999 | /* We have more usable TRBs */ | |
1000 | ep_ring->num_trbs_free++; | |
1001 | ep_ring->dequeue++; | |
2d98ef40 | 1002 | if (trb_is_link(ep_ring->dequeue)) { |
b008df60 AX |
1003 | if (ep_ring->dequeue == |
1004 | dev->eps[ep_index].queued_deq_ptr) | |
1005 | break; | |
1006 | ep_ring->deq_seg = ep_ring->deq_seg->next; | |
1007 | ep_ring->dequeue = ep_ring->deq_seg->trbs; | |
1008 | } | |
1009 | if (ep_ring->dequeue == dequeue_temp) { | |
1010 | revert = true; | |
1011 | break; | |
1012 | } | |
1013 | } | |
1014 | ||
1015 | if (revert) { | |
1016 | xhci_dbg(xhci, "Unable to find new dequeue pointer\n"); | |
1017 | ep_ring->num_trbs_free = num_trbs_free_temp; | |
1018 | } | |
1019 | } | |
1020 | ||
ae636747 SS |
1021 | /* |
1022 | * When we get a completion for a Set Transfer Ring Dequeue Pointer command, | |
1023 | * we need to clear the set deq pending flag in the endpoint ring state, so that | |
1024 | * the TD queueing code can ring the doorbell again. We also need to ring the | |
1025 | * endpoint doorbell to restart the ring, but only if there aren't more | |
1026 | * cancellations pending. | |
1027 | */ | |
b8200c94 | 1028 | static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id, |
c69a0597 | 1029 | union xhci_trb *trb, u32 cmd_comp_code) |
ae636747 | 1030 | { |
ae636747 | 1031 | unsigned int ep_index; |
e9df17eb | 1032 | unsigned int stream_id; |
ae636747 SS |
1033 | struct xhci_ring *ep_ring; |
1034 | struct xhci_virt_device *dev; | |
9aad95e2 | 1035 | struct xhci_virt_ep *ep; |
d115b048 JY |
1036 | struct xhci_ep_ctx *ep_ctx; |
1037 | struct xhci_slot_ctx *slot_ctx; | |
ae636747 | 1038 | |
28ccd296 ME |
1039 | ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); |
1040 | stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2])); | |
ae636747 | 1041 | dev = xhci->devs[slot_id]; |
9aad95e2 | 1042 | ep = &dev->eps[ep_index]; |
e9df17eb SS |
1043 | |
1044 | ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id); | |
1045 | if (!ep_ring) { | |
e587b8b2 | 1046 | xhci_warn(xhci, "WARN Set TR deq ptr command for freed stream ID %u\n", |
e9df17eb SS |
1047 | stream_id); |
1048 | /* XXX: Harmless??? */ | |
0d4976ec | 1049 | goto cleanup; |
e9df17eb SS |
1050 | } |
1051 | ||
d115b048 JY |
1052 | ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index); |
1053 | slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx); | |
19a7d0d6 FB |
1054 | trace_xhci_handle_cmd_set_deq(slot_ctx); |
1055 | trace_xhci_handle_cmd_set_deq_ep(ep_ctx); | |
ae636747 | 1056 | |
c69a0597 | 1057 | if (cmd_comp_code != COMP_SUCCESS) { |
ae636747 SS |
1058 | unsigned int ep_state; |
1059 | unsigned int slot_state; | |
1060 | ||
c69a0597 | 1061 | switch (cmd_comp_code) { |
0b7c105a | 1062 | case COMP_TRB_ERROR: |
e587b8b2 | 1063 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n"); |
ae636747 | 1064 | break; |
0b7c105a | 1065 | case COMP_CONTEXT_STATE_ERROR: |
e587b8b2 | 1066 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n"); |
5071e6b2 | 1067 | ep_state = GET_EP_CTX_STATE(ep_ctx); |
28ccd296 | 1068 | slot_state = le32_to_cpu(slot_ctx->dev_state); |
ae636747 | 1069 | slot_state = GET_SLOT_STATE(slot_state); |
aa50b290 XR |
1070 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
1071 | "Slot state = %u, EP state = %u", | |
ae636747 SS |
1072 | slot_state, ep_state); |
1073 | break; | |
0b7c105a | 1074 | case COMP_SLOT_NOT_ENABLED_ERROR: |
e587b8b2 ON |
1075 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n", |
1076 | slot_id); | |
ae636747 SS |
1077 | break; |
1078 | default: | |
e587b8b2 ON |
1079 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n", |
1080 | cmd_comp_code); | |
ae636747 SS |
1081 | break; |
1082 | } | |
1083 | /* OK what do we do now? The endpoint state is hosed, and we | |
1084 | * should never get to this point if the synchronization between | |
1085 | * queueing, and endpoint state are correct. This might happen | |
1086 | * if the device gets disconnected after we've finished | |
1087 | * cancelling URBs, which might not be an error... | |
1088 | */ | |
1089 | } else { | |
9aad95e2 HG |
1090 | u64 deq; |
1091 | /* 4.6.10 deq ptr is written to the stream ctx for streams */ | |
1092 | if (ep->ep_state & EP_HAS_STREAMS) { | |
1093 | struct xhci_stream_ctx *ctx = | |
1094 | &ep->stream_info->stream_ctx_array[stream_id]; | |
1095 | deq = le64_to_cpu(ctx->stream_ring) & SCTX_DEQ_MASK; | |
1096 | } else { | |
1097 | deq = le64_to_cpu(ep_ctx->deq) & ~EP_CTX_CYCLE_MASK; | |
1098 | } | |
aa50b290 | 1099 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
9aad95e2 HG |
1100 | "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq); |
1101 | if (xhci_trb_virt_to_dma(ep->queued_deq_seg, | |
1102 | ep->queued_deq_ptr) == deq) { | |
bf161e85 SS |
1103 | /* Update the ring's dequeue segment and dequeue pointer |
1104 | * to reflect the new position. | |
1105 | */ | |
b008df60 AX |
1106 | update_ring_for_set_deq_completion(xhci, dev, |
1107 | ep_ring, ep_index); | |
bf161e85 | 1108 | } else { |
e587b8b2 | 1109 | xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n"); |
bf161e85 | 1110 | xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n", |
9aad95e2 | 1111 | ep->queued_deq_seg, ep->queued_deq_ptr); |
bf161e85 | 1112 | } |
ae636747 SS |
1113 | } |
1114 | ||
0d4976ec | 1115 | cleanup: |
63a0d9ab | 1116 | dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING; |
bf161e85 SS |
1117 | dev->eps[ep_index].queued_deq_seg = NULL; |
1118 | dev->eps[ep_index].queued_deq_ptr = NULL; | |
e9df17eb SS |
1119 | /* Restart any rings with pending URBs */ |
1120 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); | |
ae636747 SS |
1121 | } |
1122 | ||
b8200c94 | 1123 | static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id, |
c69a0597 | 1124 | union xhci_trb *trb, u32 cmd_comp_code) |
a1587d97 | 1125 | { |
19a7d0d6 FB |
1126 | struct xhci_virt_device *vdev; |
1127 | struct xhci_ep_ctx *ep_ctx; | |
a1587d97 SS |
1128 | unsigned int ep_index; |
1129 | ||
28ccd296 | 1130 | ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); |
19a7d0d6 FB |
1131 | vdev = xhci->devs[slot_id]; |
1132 | ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index); | |
1133 | trace_xhci_handle_cmd_reset_ep(ep_ctx); | |
1134 | ||
a1587d97 SS |
1135 | /* This command will only fail if the endpoint wasn't halted, |
1136 | * but we don't care. | |
1137 | */ | |
a0254324 | 1138 | xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep, |
c69a0597 | 1139 | "Ignoring reset ep completion code of %u", cmd_comp_code); |
a1587d97 | 1140 | |
ac9d8fe7 SS |
1141 | /* HW with the reset endpoint quirk needs to have a configure endpoint |
1142 | * command complete before the endpoint can be used. Queue that here | |
1143 | * because the HW can't handle two commands being queued in a row. | |
1144 | */ | |
1145 | if (xhci->quirks & XHCI_RESET_EP_QUIRK) { | |
ddba5cd0 | 1146 | struct xhci_command *command; |
74e0b564 | 1147 | |
103afda0 | 1148 | command = xhci_alloc_command(xhci, false, GFP_ATOMIC); |
74e0b564 | 1149 | if (!command) |
a0ee619f | 1150 | return; |
74e0b564 | 1151 | |
4bdfe4c3 XR |
1152 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
1153 | "Queueing configure endpoint command"); | |
ddba5cd0 | 1154 | xhci_queue_configure_endpoint(xhci, command, |
913a8a34 SS |
1155 | xhci->devs[slot_id]->in_ctx->dma, slot_id, |
1156 | false); | |
ac9d8fe7 SS |
1157 | xhci_ring_cmd_db(xhci); |
1158 | } else { | |
c3492dbf | 1159 | /* Clear our internal halted state */ |
63a0d9ab | 1160 | xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED; |
ac9d8fe7 | 1161 | } |
f8f80be5 MN |
1162 | |
1163 | /* if this was a soft reset, then restart */ | |
1164 | if ((le32_to_cpu(trb->generic.field[3])) & TRB_TSP) | |
1165 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); | |
a1587d97 | 1166 | } |
ae636747 | 1167 | |
b244b431 | 1168 | static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id, |
c2d3d49b | 1169 | struct xhci_command *command, u32 cmd_comp_code) |
b244b431 XR |
1170 | { |
1171 | if (cmd_comp_code == COMP_SUCCESS) | |
c2d3d49b | 1172 | command->slot_id = slot_id; |
b244b431 | 1173 | else |
c2d3d49b | 1174 | command->slot_id = 0; |
b244b431 XR |
1175 | } |
1176 | ||
6c02dd14 XR |
1177 | static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id) |
1178 | { | |
1179 | struct xhci_virt_device *virt_dev; | |
19a7d0d6 | 1180 | struct xhci_slot_ctx *slot_ctx; |
6c02dd14 XR |
1181 | |
1182 | virt_dev = xhci->devs[slot_id]; | |
1183 | if (!virt_dev) | |
1184 | return; | |
19a7d0d6 FB |
1185 | |
1186 | slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx); | |
1187 | trace_xhci_handle_cmd_disable_slot(slot_ctx); | |
1188 | ||
6c02dd14 XR |
1189 | if (xhci->quirks & XHCI_EP_LIMIT_QUIRK) |
1190 | /* Delete default control endpoint resources */ | |
1191 | xhci_free_device_endpoint_resources(xhci, virt_dev, true); | |
1192 | xhci_free_virt_device(xhci, slot_id); | |
1193 | } | |
1194 | ||
6ed46d33 XR |
1195 | static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id, |
1196 | struct xhci_event_cmd *event, u32 cmd_comp_code) | |
1197 | { | |
1198 | struct xhci_virt_device *virt_dev; | |
1199 | struct xhci_input_control_ctx *ctrl_ctx; | |
19a7d0d6 | 1200 | struct xhci_ep_ctx *ep_ctx; |
6ed46d33 XR |
1201 | unsigned int ep_index; |
1202 | unsigned int ep_state; | |
1203 | u32 add_flags, drop_flags; | |
1204 | ||
6ed46d33 XR |
1205 | /* |
1206 | * Configure endpoint commands can come from the USB core | |
1207 | * configuration or alt setting changes, or because the HW | |
1208 | * needed an extra configure endpoint command after a reset | |
1209 | * endpoint command or streams were being configured. | |
1210 | * If the command was for a halted endpoint, the xHCI driver | |
1211 | * is not waiting on the configure endpoint command. | |
1212 | */ | |
9ea1833e | 1213 | virt_dev = xhci->devs[slot_id]; |
4daf9df5 | 1214 | ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx); |
6ed46d33 XR |
1215 | if (!ctrl_ctx) { |
1216 | xhci_warn(xhci, "Could not get input context, bad type.\n"); | |
1217 | return; | |
1218 | } | |
1219 | ||
1220 | add_flags = le32_to_cpu(ctrl_ctx->add_flags); | |
1221 | drop_flags = le32_to_cpu(ctrl_ctx->drop_flags); | |
1222 | /* Input ctx add_flags are the endpoint index plus one */ | |
1223 | ep_index = xhci_last_valid_endpoint(add_flags) - 1; | |
1224 | ||
19a7d0d6 FB |
1225 | ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, ep_index); |
1226 | trace_xhci_handle_cmd_config_ep(ep_ctx); | |
1227 | ||
6ed46d33 XR |
1228 | /* A usb_set_interface() call directly after clearing a halted |
1229 | * condition may race on this quirky hardware. Not worth | |
1230 | * worrying about, since this is prototype hardware. Not sure | |
1231 | * if this will work for streams, but streams support was | |
1232 | * untested on this prototype. | |
1233 | */ | |
1234 | if (xhci->quirks & XHCI_RESET_EP_QUIRK && | |
1235 | ep_index != (unsigned int) -1 && | |
1236 | add_flags - SLOT_FLAG == drop_flags) { | |
1237 | ep_state = virt_dev->eps[ep_index].ep_state; | |
1238 | if (!(ep_state & EP_HALTED)) | |
ddba5cd0 | 1239 | return; |
6ed46d33 XR |
1240 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
1241 | "Completed config ep cmd - " | |
1242 | "last ep index = %d, state = %d", | |
1243 | ep_index, ep_state); | |
1244 | /* Clear internal halted state and restart ring(s) */ | |
1245 | virt_dev->eps[ep_index].ep_state &= ~EP_HALTED; | |
1246 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); | |
1247 | return; | |
1248 | } | |
6ed46d33 XR |
1249 | return; |
1250 | } | |
1251 | ||
19a7d0d6 FB |
1252 | static void xhci_handle_cmd_addr_dev(struct xhci_hcd *xhci, int slot_id) |
1253 | { | |
1254 | struct xhci_virt_device *vdev; | |
1255 | struct xhci_slot_ctx *slot_ctx; | |
1256 | ||
1257 | vdev = xhci->devs[slot_id]; | |
1258 | slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx); | |
1259 | trace_xhci_handle_cmd_addr_dev(slot_ctx); | |
1260 | } | |
1261 | ||
f681321b XR |
1262 | static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id, |
1263 | struct xhci_event_cmd *event) | |
1264 | { | |
19a7d0d6 FB |
1265 | struct xhci_virt_device *vdev; |
1266 | struct xhci_slot_ctx *slot_ctx; | |
1267 | ||
1268 | vdev = xhci->devs[slot_id]; | |
1269 | slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx); | |
1270 | trace_xhci_handle_cmd_reset_dev(slot_ctx); | |
1271 | ||
f681321b | 1272 | xhci_dbg(xhci, "Completed reset device command.\n"); |
9ea1833e | 1273 | if (!xhci->devs[slot_id]) |
f681321b XR |
1274 | xhci_warn(xhci, "Reset device command completion " |
1275 | "for disabled slot %u\n", slot_id); | |
1276 | } | |
1277 | ||
2c070821 XR |
1278 | static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci, |
1279 | struct xhci_event_cmd *event) | |
1280 | { | |
1281 | if (!(xhci->quirks & XHCI_NEC_HOST)) { | |
f4c8f03c | 1282 | xhci_warn(xhci, "WARN NEC_GET_FW command on non-NEC host\n"); |
2c070821 XR |
1283 | return; |
1284 | } | |
1285 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, | |
1286 | "NEC firmware version %2x.%02x", | |
1287 | NEC_FW_MAJOR(le32_to_cpu(event->status)), | |
1288 | NEC_FW_MINOR(le32_to_cpu(event->status))); | |
1289 | } | |
1290 | ||
9ea1833e | 1291 | static void xhci_complete_del_and_free_cmd(struct xhci_command *cmd, u32 status) |
c9aa1a2d MN |
1292 | { |
1293 | list_del(&cmd->cmd_list); | |
9ea1833e MN |
1294 | |
1295 | if (cmd->completion) { | |
1296 | cmd->status = status; | |
1297 | complete(cmd->completion); | |
1298 | } else { | |
c9aa1a2d | 1299 | kfree(cmd); |
9ea1833e | 1300 | } |
c9aa1a2d MN |
1301 | } |
1302 | ||
1303 | void xhci_cleanup_command_queue(struct xhci_hcd *xhci) | |
1304 | { | |
1305 | struct xhci_command *cur_cmd, *tmp_cmd; | |
d1aad52c | 1306 | xhci->current_cmd = NULL; |
c9aa1a2d | 1307 | list_for_each_entry_safe(cur_cmd, tmp_cmd, &xhci->cmd_list, cmd_list) |
0b7c105a | 1308 | xhci_complete_del_and_free_cmd(cur_cmd, COMP_COMMAND_ABORTED); |
c9aa1a2d MN |
1309 | } |
1310 | ||
cb4d5ce5 | 1311 | void xhci_handle_command_timeout(struct work_struct *work) |
c311e391 MN |
1312 | { |
1313 | struct xhci_hcd *xhci; | |
c311e391 MN |
1314 | unsigned long flags; |
1315 | u64 hw_ring_state; | |
cb4d5ce5 OH |
1316 | |
1317 | xhci = container_of(to_delayed_work(work), struct xhci_hcd, cmd_timer); | |
c311e391 | 1318 | |
c311e391 | 1319 | spin_lock_irqsave(&xhci->lock, flags); |
2b985467 | 1320 | |
a5a1b951 MN |
1321 | /* |
1322 | * If timeout work is pending, or current_cmd is NULL, it means we | |
1323 | * raced with command completion. Command is handled so just return. | |
1324 | */ | |
cb4d5ce5 | 1325 | if (!xhci->current_cmd || delayed_work_pending(&xhci->cmd_timer)) { |
2b985467 LB |
1326 | spin_unlock_irqrestore(&xhci->lock, flags); |
1327 | return; | |
c311e391 | 1328 | } |
2b985467 | 1329 | /* mark this command to be cancelled */ |
0b7c105a | 1330 | xhci->current_cmd->status = COMP_COMMAND_ABORTED; |
2b985467 | 1331 | |
c311e391 MN |
1332 | /* Make sure command ring is running before aborting it */ |
1333 | hw_ring_state = xhci_read_64(xhci, &xhci->op_regs->cmd_ring); | |
d9f11ba9 MN |
1334 | if (hw_ring_state == ~(u64)0) { |
1335 | xhci_hc_died(xhci); | |
1336 | goto time_out_completed; | |
1337 | } | |
1338 | ||
c311e391 MN |
1339 | if ((xhci->cmd_ring_state & CMD_RING_STATE_RUNNING) && |
1340 | (hw_ring_state & CMD_RING_RUNNING)) { | |
1c111b6c OH |
1341 | /* Prevent new doorbell, and start command abort */ |
1342 | xhci->cmd_ring_state = CMD_RING_STATE_ABORTED; | |
c311e391 | 1343 | xhci_dbg(xhci, "Command timeout\n"); |
d9f11ba9 | 1344 | xhci_abort_cmd_ring(xhci, flags); |
4dea7077 | 1345 | goto time_out_completed; |
c311e391 | 1346 | } |
3425aa03 | 1347 | |
1c111b6c OH |
1348 | /* host removed. Bail out */ |
1349 | if (xhci->xhc_state & XHCI_STATE_REMOVING) { | |
1350 | xhci_dbg(xhci, "host removed, ring start fail?\n"); | |
3425aa03 | 1351 | xhci_cleanup_command_queue(xhci); |
4dea7077 LB |
1352 | |
1353 | goto time_out_completed; | |
3425aa03 MN |
1354 | } |
1355 | ||
c311e391 MN |
1356 | /* command timeout on stopped ring, ring can't be aborted */ |
1357 | xhci_dbg(xhci, "Command timeout on stopped ring\n"); | |
1358 | xhci_handle_stopped_cmd_ring(xhci, xhci->current_cmd); | |
4dea7077 LB |
1359 | |
1360 | time_out_completed: | |
c311e391 MN |
1361 | spin_unlock_irqrestore(&xhci->lock, flags); |
1362 | return; | |
1363 | } | |
1364 | ||
7f84eef0 SS |
1365 | static void handle_cmd_completion(struct xhci_hcd *xhci, |
1366 | struct xhci_event_cmd *event) | |
1367 | { | |
28ccd296 | 1368 | int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
7f84eef0 SS |
1369 | u64 cmd_dma; |
1370 | dma_addr_t cmd_dequeue_dma; | |
e7a79a1d | 1371 | u32 cmd_comp_code; |
9124b121 | 1372 | union xhci_trb *cmd_trb; |
c9aa1a2d | 1373 | struct xhci_command *cmd; |
b54fc46d | 1374 | u32 cmd_type; |
7f84eef0 | 1375 | |
28ccd296 | 1376 | cmd_dma = le64_to_cpu(event->cmd_trb); |
9124b121 | 1377 | cmd_trb = xhci->cmd_ring->dequeue; |
a37c3f76 FB |
1378 | |
1379 | trace_xhci_handle_command(xhci->cmd_ring, &cmd_trb->generic); | |
1380 | ||
23e3be11 | 1381 | cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg, |
9124b121 | 1382 | cmd_trb); |
f4c8f03c LB |
1383 | /* |
1384 | * Check whether the completion event is for our internal kept | |
1385 | * command. | |
1386 | */ | |
1387 | if (!cmd_dequeue_dma || cmd_dma != (u64)cmd_dequeue_dma) { | |
1388 | xhci_warn(xhci, | |
1389 | "ERROR mismatched command completion event\n"); | |
7f84eef0 SS |
1390 | return; |
1391 | } | |
b63f4053 | 1392 | |
04861f83 | 1393 | cmd = list_first_entry(&xhci->cmd_list, struct xhci_command, cmd_list); |
c9aa1a2d | 1394 | |
cb4d5ce5 | 1395 | cancel_delayed_work(&xhci->cmd_timer); |
c311e391 | 1396 | |
e7a79a1d | 1397 | cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status)); |
c311e391 MN |
1398 | |
1399 | /* If CMD ring stopped we own the trbs between enqueue and dequeue */ | |
604d02a2 | 1400 | if (cmd_comp_code == COMP_COMMAND_RING_STOPPED) { |
1c111b6c | 1401 | complete_all(&xhci->cmd_ring_stop_completion); |
c311e391 MN |
1402 | return; |
1403 | } | |
33be1265 MN |
1404 | |
1405 | if (cmd->command_trb != xhci->cmd_ring->dequeue) { | |
1406 | xhci_err(xhci, | |
1407 | "Command completion event does not match command\n"); | |
1408 | return; | |
1409 | } | |
1410 | ||
c311e391 MN |
1411 | /* |
1412 | * Host aborted the command ring, check if the current command was | |
1413 | * supposed to be aborted, otherwise continue normally. | |
1414 | * The command ring is stopped now, but the xHC will issue a Command | |
1415 | * Ring Stopped event which will cause us to restart it. | |
1416 | */ | |
0b7c105a | 1417 | if (cmd_comp_code == COMP_COMMAND_ABORTED) { |
c311e391 | 1418 | xhci->cmd_ring_state = CMD_RING_STATE_STOPPED; |
0b7c105a | 1419 | if (cmd->status == COMP_COMMAND_ABORTED) { |
2a7cfdf3 BW |
1420 | if (xhci->current_cmd == cmd) |
1421 | xhci->current_cmd = NULL; | |
c311e391 | 1422 | goto event_handled; |
2a7cfdf3 | 1423 | } |
b63f4053 EF |
1424 | } |
1425 | ||
b54fc46d XR |
1426 | cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3])); |
1427 | switch (cmd_type) { | |
1428 | case TRB_ENABLE_SLOT: | |
c2d3d49b | 1429 | xhci_handle_cmd_enable_slot(xhci, slot_id, cmd, cmd_comp_code); |
3ffbba95 | 1430 | break; |
b54fc46d | 1431 | case TRB_DISABLE_SLOT: |
6c02dd14 | 1432 | xhci_handle_cmd_disable_slot(xhci, slot_id); |
3ffbba95 | 1433 | break; |
b54fc46d | 1434 | case TRB_CONFIG_EP: |
9ea1833e MN |
1435 | if (!cmd->completion) |
1436 | xhci_handle_cmd_config_ep(xhci, slot_id, event, | |
1437 | cmd_comp_code); | |
f94e0186 | 1438 | break; |
b54fc46d | 1439 | case TRB_EVAL_CONTEXT: |
2d3f1fac | 1440 | break; |
b54fc46d | 1441 | case TRB_ADDR_DEV: |
19a7d0d6 | 1442 | xhci_handle_cmd_addr_dev(xhci, slot_id); |
3ffbba95 | 1443 | break; |
b54fc46d | 1444 | case TRB_STOP_RING: |
b8200c94 XR |
1445 | WARN_ON(slot_id != TRB_TO_SLOT_ID( |
1446 | le32_to_cpu(cmd_trb->generic.field[3]))); | |
a38fe338 MN |
1447 | if (!cmd->completion) |
1448 | xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb, event); | |
ae636747 | 1449 | break; |
b54fc46d | 1450 | case TRB_SET_DEQ: |
b8200c94 XR |
1451 | WARN_ON(slot_id != TRB_TO_SLOT_ID( |
1452 | le32_to_cpu(cmd_trb->generic.field[3]))); | |
c69a0597 | 1453 | xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code); |
ae636747 | 1454 | break; |
b54fc46d | 1455 | case TRB_CMD_NOOP: |
c311e391 | 1456 | /* Is this an aborted command turned to NO-OP? */ |
604d02a2 MN |
1457 | if (cmd->status == COMP_COMMAND_RING_STOPPED) |
1458 | cmd_comp_code = COMP_COMMAND_RING_STOPPED; | |
7f84eef0 | 1459 | break; |
b54fc46d | 1460 | case TRB_RESET_EP: |
b8200c94 XR |
1461 | WARN_ON(slot_id != TRB_TO_SLOT_ID( |
1462 | le32_to_cpu(cmd_trb->generic.field[3]))); | |
c69a0597 | 1463 | xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code); |
a1587d97 | 1464 | break; |
b54fc46d | 1465 | case TRB_RESET_DEV: |
6fcfb0d6 MN |
1466 | /* SLOT_ID field in reset device cmd completion event TRB is 0. |
1467 | * Use the SLOT_ID from the command TRB instead (xhci 4.6.11) | |
1468 | */ | |
1469 | slot_id = TRB_TO_SLOT_ID( | |
1470 | le32_to_cpu(cmd_trb->generic.field[3])); | |
f681321b | 1471 | xhci_handle_cmd_reset_dev(xhci, slot_id, event); |
2a8f82c4 | 1472 | break; |
b54fc46d | 1473 | case TRB_NEC_GET_FW: |
2c070821 | 1474 | xhci_handle_cmd_nec_get_fw(xhci, event); |
0238634d | 1475 | break; |
7f84eef0 SS |
1476 | default: |
1477 | /* Skip over unknown commands on the event ring */ | |
f4c8f03c | 1478 | xhci_info(xhci, "INFO unknown command type %d\n", cmd_type); |
7f84eef0 SS |
1479 | break; |
1480 | } | |
c9aa1a2d | 1481 | |
c311e391 | 1482 | /* restart timer if this wasn't the last command */ |
daa47f21 | 1483 | if (!list_is_singular(&xhci->cmd_list)) { |
04861f83 FB |
1484 | xhci->current_cmd = list_first_entry(&cmd->cmd_list, |
1485 | struct xhci_command, cmd_list); | |
cb4d5ce5 | 1486 | xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT); |
2b985467 LB |
1487 | } else if (xhci->current_cmd == cmd) { |
1488 | xhci->current_cmd = NULL; | |
c311e391 MN |
1489 | } |
1490 | ||
1491 | event_handled: | |
9ea1833e | 1492 | xhci_complete_del_and_free_cmd(cmd, cmd_comp_code); |
c9aa1a2d | 1493 | |
3b72fca0 | 1494 | inc_deq(xhci, xhci->cmd_ring); |
7f84eef0 SS |
1495 | } |
1496 | ||
0238634d SS |
1497 | static void handle_vendor_event(struct xhci_hcd *xhci, |
1498 | union xhci_trb *event) | |
1499 | { | |
1500 | u32 trb_type; | |
1501 | ||
28ccd296 | 1502 | trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3])); |
0238634d SS |
1503 | xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type); |
1504 | if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST)) | |
1505 | handle_cmd_completion(xhci, &event->event_cmd); | |
1506 | } | |
1507 | ||
623bef9e SS |
1508 | static void handle_device_notification(struct xhci_hcd *xhci, |
1509 | union xhci_trb *event) | |
1510 | { | |
1511 | u32 slot_id; | |
4ee823b8 | 1512 | struct usb_device *udev; |
623bef9e | 1513 | |
7e76ad43 | 1514 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3])); |
4ee823b8 | 1515 | if (!xhci->devs[slot_id]) { |
623bef9e SS |
1516 | xhci_warn(xhci, "Device Notification event for " |
1517 | "unused slot %u\n", slot_id); | |
4ee823b8 SS |
1518 | return; |
1519 | } | |
1520 | ||
1521 | xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n", | |
1522 | slot_id); | |
1523 | udev = xhci->devs[slot_id]->udev; | |
1524 | if (udev && udev->parent) | |
1525 | usb_wakeup_notification(udev->parent, udev->portnum); | |
623bef9e SS |
1526 | } |
1527 | ||
11644a76 CG |
1528 | /* |
1529 | * Quirk hanlder for errata seen on Cavium ThunderX2 processor XHCI | |
1530 | * Controller. | |
1531 | * As per ThunderX2errata-129 USB 2 device may come up as USB 1 | |
1532 | * If a connection to a USB 1 device is followed by another connection | |
1533 | * to a USB 2 device. | |
1534 | * | |
1535 | * Reset the PHY after the USB device is disconnected if device speed | |
1536 | * is less than HCD_USB3. | |
1537 | * Retry the reset sequence max of 4 times checking the PLL lock status. | |
1538 | * | |
1539 | */ | |
1540 | static void xhci_cavium_reset_phy_quirk(struct xhci_hcd *xhci) | |
1541 | { | |
1542 | struct usb_hcd *hcd = xhci_to_hcd(xhci); | |
1543 | u32 pll_lock_check; | |
1544 | u32 retry_count = 4; | |
1545 | ||
1546 | do { | |
1547 | /* Assert PHY reset */ | |
1548 | writel(0x6F, hcd->regs + 0x1048); | |
1549 | udelay(10); | |
1550 | /* De-assert the PHY reset */ | |
1551 | writel(0x7F, hcd->regs + 0x1048); | |
1552 | udelay(200); | |
1553 | pll_lock_check = readl(hcd->regs + 0x1070); | |
1554 | } while (!(pll_lock_check & 0x1) && --retry_count); | |
1555 | } | |
1556 | ||
0f2a7930 SS |
1557 | static void handle_port_status(struct xhci_hcd *xhci, |
1558 | union xhci_trb *event) | |
1559 | { | |
f6ff0ac8 | 1560 | struct usb_hcd *hcd; |
0f2a7930 | 1561 | u32 port_id; |
76a0f32b | 1562 | u32 portsc, cmd_reg; |
518e848e | 1563 | int max_ports; |
56192531 | 1564 | int slot_id; |
74e6ad58 | 1565 | unsigned int hcd_portnum; |
20b67cf5 | 1566 | struct xhci_bus_state *bus_state; |
386139d7 | 1567 | bool bogus_port_status = false; |
52c7755b | 1568 | struct xhci_port *port; |
0f2a7930 SS |
1569 | |
1570 | /* Port status change events always have a successful completion code */ | |
f4c8f03c LB |
1571 | if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) |
1572 | xhci_warn(xhci, | |
1573 | "WARN: xHC returned failed port status event\n"); | |
1574 | ||
28ccd296 | 1575 | port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0])); |
518e848e | 1576 | max_ports = HCS_MAX_PORTS(xhci->hcs_params1); |
d70d5a84 | 1577 | |
518e848e | 1578 | if ((port_id <= 0) || (port_id > max_ports)) { |
d70d5a84 MN |
1579 | xhci_warn(xhci, "Port change event with invalid port ID %d\n", |
1580 | port_id); | |
09ce0c0c PC |
1581 | inc_deq(xhci, xhci->event_ring); |
1582 | return; | |
56192531 AX |
1583 | } |
1584 | ||
52c7755b MN |
1585 | port = &xhci->hw_ports[port_id - 1]; |
1586 | if (!port || !port->rhub || port->hcd_portnum == DUPLICATE_ENTRY) { | |
d70d5a84 MN |
1587 | xhci_warn(xhci, "Port change event, no port for port ID %u\n", |
1588 | port_id); | |
386139d7 | 1589 | bogus_port_status = true; |
f6ff0ac8 SS |
1590 | goto cleanup; |
1591 | } | |
1592 | ||
1245374e MN |
1593 | /* We might get interrupts after shared_hcd is removed */ |
1594 | if (port->rhub == &xhci->usb3_rhub && xhci->shared_hcd == NULL) { | |
1595 | xhci_dbg(xhci, "ignore port event for removed USB3 hcd\n"); | |
1596 | bogus_port_status = true; | |
1597 | goto cleanup; | |
1598 | } | |
1599 | ||
52c7755b | 1600 | hcd = port->rhub->hcd; |
f6187f42 | 1601 | bus_state = &port->rhub->bus_state; |
74e6ad58 | 1602 | hcd_portnum = port->hcd_portnum; |
52c7755b | 1603 | portsc = readl(port->addr); |
5308a91b | 1604 | |
d70d5a84 MN |
1605 | xhci_dbg(xhci, "Port change event, %d-%d, id %d, portsc: 0x%x\n", |
1606 | hcd->self.busnum, hcd_portnum + 1, port_id, portsc); | |
1607 | ||
74e6ad58 | 1608 | trace_xhci_handle_port_status(hcd_portnum, portsc); |
8ca1358b | 1609 | |
7111ebc9 | 1610 | if (hcd->state == HC_STATE_SUSPENDED) { |
56192531 AX |
1611 | xhci_dbg(xhci, "resume root hub\n"); |
1612 | usb_hcd_resume_root_hub(hcd); | |
1613 | } | |
1614 | ||
76a0f32b | 1615 | if (hcd->speed >= HCD_USB3 && (portsc & PORT_PLS_MASK) == XDEV_INACTIVE) |
74e6ad58 | 1616 | bus_state->port_remote_wakeup &= ~(1 << hcd_portnum); |
fac4271d | 1617 | |
76a0f32b | 1618 | if ((portsc & PORT_PLC) && (portsc & PORT_PLS_MASK) == XDEV_RESUME) { |
56192531 AX |
1619 | xhci_dbg(xhci, "port resume event for port %d\n", port_id); |
1620 | ||
76a0f32b MN |
1621 | cmd_reg = readl(&xhci->op_regs->command); |
1622 | if (!(cmd_reg & CMD_RUN)) { | |
56192531 AX |
1623 | xhci_warn(xhci, "xHC is not running.\n"); |
1624 | goto cleanup; | |
1625 | } | |
1626 | ||
76a0f32b | 1627 | if (DEV_SUPERSPEED_ANY(portsc)) { |
d93814cf | 1628 | xhci_dbg(xhci, "remote wake SS port %d\n", port_id); |
4ee823b8 SS |
1629 | /* Set a flag to say the port signaled remote wakeup, |
1630 | * so we can tell the difference between the end of | |
1631 | * device and host initiated resume. | |
1632 | */ | |
74e6ad58 | 1633 | bus_state->port_remote_wakeup |= 1 << hcd_portnum; |
eaefcf24 | 1634 | xhci_test_and_clear_bit(xhci, port, PORT_PLC); |
6b7f40f7 | 1635 | xhci_set_link_state(xhci, port, XDEV_U0); |
d93814cf SS |
1636 | /* Need to wait until the next link state change |
1637 | * indicates the device is actually in U0. | |
1638 | */ | |
1639 | bogus_port_status = true; | |
1640 | goto cleanup; | |
74e6ad58 | 1641 | } else if (!test_bit(hcd_portnum, &bus_state->resuming_ports)) { |
56192531 | 1642 | xhci_dbg(xhci, "resume HS port %d\n", port_id); |
74e6ad58 | 1643 | bus_state->resume_done[hcd_portnum] = jiffies + |
b9e45188 | 1644 | msecs_to_jiffies(USB_RESUME_TIMEOUT); |
74e6ad58 | 1645 | set_bit(hcd_portnum, &bus_state->resuming_ports); |
0914ea66 AG |
1646 | /* Do the rest in GetPortStatus after resume time delay. |
1647 | * Avoid polling roothub status before that so that a | |
1648 | * usb device auto-resume latency around ~40ms. | |
1649 | */ | |
1650 | set_bit(HCD_FLAG_POLL_RH, &hcd->flags); | |
56192531 | 1651 | mod_timer(&hcd->rh_timer, |
74e6ad58 | 1652 | bus_state->resume_done[hcd_portnum]); |
330e2d61 | 1653 | usb_hcd_start_port_resume(&hcd->self, hcd_portnum); |
0914ea66 | 1654 | bogus_port_status = true; |
56192531 AX |
1655 | } |
1656 | } | |
d93814cf | 1657 | |
6cbcf596 MN |
1658 | if ((portsc & PORT_PLC) && |
1659 | DEV_SUPERSPEED_ANY(portsc) && | |
1660 | ((portsc & PORT_PLS_MASK) == XDEV_U0 || | |
1661 | (portsc & PORT_PLS_MASK) == XDEV_U1 || | |
1662 | (portsc & PORT_PLS_MASK) == XDEV_U2)) { | |
d93814cf | 1663 | xhci_dbg(xhci, "resume SS port %d finished\n", port_id); |
6cbcf596 | 1664 | /* We've just brought the device into U0/1/2 through either the |
4ee823b8 SS |
1665 | * Resume state after a device remote wakeup, or through the |
1666 | * U3Exit state after a host-initiated resume. If it's a device | |
1667 | * initiated remote wake, don't pass up the link state change, | |
1668 | * so the roothub behavior is consistent with external | |
1669 | * USB 3.0 hub behavior. | |
1670 | */ | |
74e6ad58 | 1671 | slot_id = xhci_find_slot_id_by_port(hcd, xhci, hcd_portnum + 1); |
d93814cf SS |
1672 | if (slot_id && xhci->devs[slot_id]) |
1673 | xhci_ring_device(xhci, slot_id); | |
74e6ad58 MN |
1674 | if (bus_state->port_remote_wakeup & (1 << hcd_portnum)) { |
1675 | bus_state->port_remote_wakeup &= ~(1 << hcd_portnum); | |
eaefcf24 | 1676 | xhci_test_and_clear_bit(xhci, port, PORT_PLC); |
4ee823b8 | 1677 | usb_wakeup_notification(hcd->self.root_hub, |
74e6ad58 | 1678 | hcd_portnum + 1); |
4ee823b8 SS |
1679 | bogus_port_status = true; |
1680 | goto cleanup; | |
1681 | } | |
d93814cf | 1682 | } |
56192531 | 1683 | |
8b3d4570 SS |
1684 | /* |
1685 | * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or | |
1686 | * RExit to a disconnect state). If so, let the the driver know it's | |
1687 | * out of the RExit state. | |
1688 | */ | |
958c0bd8 | 1689 | if (!DEV_SUPERSPEED_ANY(portsc) && hcd->speed < HCD_USB3 && |
74e6ad58 | 1690 | test_and_clear_bit(hcd_portnum, |
8b3d4570 | 1691 | &bus_state->rexit_ports)) { |
74e6ad58 | 1692 | complete(&bus_state->rexit_done[hcd_portnum]); |
8b3d4570 SS |
1693 | bogus_port_status = true; |
1694 | goto cleanup; | |
1695 | } | |
1696 | ||
11644a76 | 1697 | if (hcd->speed < HCD_USB3) { |
eaefcf24 | 1698 | xhci_test_and_clear_bit(xhci, port, PORT_PLC); |
11644a76 CG |
1699 | if ((xhci->quirks & XHCI_RESET_PLL_ON_DISCONNECT) && |
1700 | (portsc & PORT_CSC) && !(portsc & PORT_CONNECT)) | |
1701 | xhci_cavium_reset_phy_quirk(xhci); | |
1702 | } | |
6fd45621 | 1703 | |
56192531 | 1704 | cleanup: |
0f2a7930 | 1705 | /* Update event ring dequeue pointer before dropping the lock */ |
3b72fca0 | 1706 | inc_deq(xhci, xhci->event_ring); |
0f2a7930 | 1707 | |
386139d7 SS |
1708 | /* Don't make the USB core poll the roothub if we got a bad port status |
1709 | * change event. Besides, at that point we can't tell which roothub | |
1710 | * (USB 2.0 or USB 3.0) to kick. | |
1711 | */ | |
1712 | if (bogus_port_status) | |
1713 | return; | |
1714 | ||
c52804a4 SS |
1715 | /* |
1716 | * xHCI port-status-change events occur when the "or" of all the | |
1717 | * status-change bits in the portsc register changes from 0 to 1. | |
1718 | * New status changes won't cause an event if any other change | |
1719 | * bits are still set. When an event occurs, switch over to | |
1720 | * polling to avoid losing status changes. | |
1721 | */ | |
1722 | xhci_dbg(xhci, "%s: starting port polling.\n", __func__); | |
1723 | set_bit(HCD_FLAG_POLL_RH, &hcd->flags); | |
0f2a7930 SS |
1724 | spin_unlock(&xhci->lock); |
1725 | /* Pass this up to the core */ | |
f6ff0ac8 | 1726 | usb_hcd_poll_rh_status(hcd); |
0f2a7930 SS |
1727 | spin_lock(&xhci->lock); |
1728 | } | |
1729 | ||
d0e96f5a SS |
1730 | /* |
1731 | * This TD is defined by the TRBs starting at start_trb in start_seg and ending | |
1732 | * at end_trb, which may be in another segment. If the suspect DMA address is a | |
1733 | * TRB in this TD, this function returns that TRB's segment. Otherwise it | |
1734 | * returns 0. | |
1735 | */ | |
cffb9be8 HG |
1736 | struct xhci_segment *trb_in_td(struct xhci_hcd *xhci, |
1737 | struct xhci_segment *start_seg, | |
d0e96f5a SS |
1738 | union xhci_trb *start_trb, |
1739 | union xhci_trb *end_trb, | |
cffb9be8 HG |
1740 | dma_addr_t suspect_dma, |
1741 | bool debug) | |
d0e96f5a SS |
1742 | { |
1743 | dma_addr_t start_dma; | |
1744 | dma_addr_t end_seg_dma; | |
1745 | dma_addr_t end_trb_dma; | |
1746 | struct xhci_segment *cur_seg; | |
1747 | ||
23e3be11 | 1748 | start_dma = xhci_trb_virt_to_dma(start_seg, start_trb); |
d0e96f5a SS |
1749 | cur_seg = start_seg; |
1750 | ||
1751 | do { | |
2fa88daa | 1752 | if (start_dma == 0) |
326b4810 | 1753 | return NULL; |
ae636747 | 1754 | /* We may get an event for a Link TRB in the middle of a TD */ |
23e3be11 | 1755 | end_seg_dma = xhci_trb_virt_to_dma(cur_seg, |
2fa88daa | 1756 | &cur_seg->trbs[TRBS_PER_SEGMENT - 1]); |
d0e96f5a | 1757 | /* If the end TRB isn't in this segment, this is set to 0 */ |
23e3be11 | 1758 | end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb); |
d0e96f5a | 1759 | |
cffb9be8 HG |
1760 | if (debug) |
1761 | xhci_warn(xhci, | |
1762 | "Looking for event-dma %016llx trb-start %016llx trb-end %016llx seg-start %016llx seg-end %016llx\n", | |
1763 | (unsigned long long)suspect_dma, | |
1764 | (unsigned long long)start_dma, | |
1765 | (unsigned long long)end_trb_dma, | |
1766 | (unsigned long long)cur_seg->dma, | |
1767 | (unsigned long long)end_seg_dma); | |
1768 | ||
d0e96f5a SS |
1769 | if (end_trb_dma > 0) { |
1770 | /* The end TRB is in this segment, so suspect should be here */ | |
1771 | if (start_dma <= end_trb_dma) { | |
1772 | if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma) | |
1773 | return cur_seg; | |
1774 | } else { | |
1775 | /* Case for one segment with | |
1776 | * a TD wrapped around to the top | |
1777 | */ | |
1778 | if ((suspect_dma >= start_dma && | |
1779 | suspect_dma <= end_seg_dma) || | |
1780 | (suspect_dma >= cur_seg->dma && | |
1781 | suspect_dma <= end_trb_dma)) | |
1782 | return cur_seg; | |
1783 | } | |
326b4810 | 1784 | return NULL; |
d0e96f5a SS |
1785 | } else { |
1786 | /* Might still be somewhere in this segment */ | |
1787 | if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma) | |
1788 | return cur_seg; | |
1789 | } | |
1790 | cur_seg = cur_seg->next; | |
23e3be11 | 1791 | start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]); |
2fa88daa | 1792 | } while (cur_seg != start_seg); |
d0e96f5a | 1793 | |
326b4810 | 1794 | return NULL; |
d0e96f5a SS |
1795 | } |
1796 | ||
bcef3fd5 SS |
1797 | static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci, |
1798 | unsigned int slot_id, unsigned int ep_index, | |
5fee5a5a | 1799 | unsigned int stream_id, struct xhci_td *td, |
5eee4b6b | 1800 | enum xhci_ep_reset_type reset_type) |
bcef3fd5 SS |
1801 | { |
1802 | struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index]; | |
ddba5cd0 | 1803 | struct xhci_command *command; |
103afda0 | 1804 | command = xhci_alloc_command(xhci, false, GFP_ATOMIC); |
ddba5cd0 MN |
1805 | if (!command) |
1806 | return; | |
1807 | ||
d0167ad2 | 1808 | ep->ep_state |= EP_HALTED; |
1624ae1c | 1809 | |
5eee4b6b | 1810 | xhci_queue_reset_ep(xhci, command, slot_id, ep_index, reset_type); |
1624ae1c | 1811 | |
f5249461 MN |
1812 | if (reset_type == EP_HARD_RESET) { |
1813 | ep->ep_state |= EP_HARD_CLEAR_TOGGLE; | |
d36374fd | 1814 | xhci_cleanup_stalled_ring(xhci, ep_index, stream_id, td); |
f5249461 | 1815 | } |
bcef3fd5 SS |
1816 | xhci_ring_cmd_db(xhci); |
1817 | } | |
1818 | ||
1819 | /* Check if an error has halted the endpoint ring. The class driver will | |
1820 | * cleanup the halt for a non-default control endpoint if we indicate a stall. | |
1821 | * However, a babble and other errors also halt the endpoint ring, and the class | |
1822 | * driver won't clear the halt in that case, so we need to issue a Set Transfer | |
1823 | * Ring Dequeue Pointer command manually. | |
1824 | */ | |
1825 | static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci, | |
1826 | struct xhci_ep_ctx *ep_ctx, | |
1827 | unsigned int trb_comp_code) | |
1828 | { | |
1829 | /* TRB completion codes that may require a manual halt cleanup */ | |
0b7c105a FB |
1830 | if (trb_comp_code == COMP_USB_TRANSACTION_ERROR || |
1831 | trb_comp_code == COMP_BABBLE_DETECTED_ERROR || | |
1832 | trb_comp_code == COMP_SPLIT_TRANSACTION_ERROR) | |
d4fc8bf5 | 1833 | /* The 0.95 spec says a babbling control endpoint |
bcef3fd5 SS |
1834 | * is not halted. The 0.96 spec says it is. Some HW |
1835 | * claims to be 0.95 compliant, but it halts the control | |
1836 | * endpoint anyway. Check if a babble halted the | |
1837 | * endpoint. | |
1838 | */ | |
5071e6b2 | 1839 | if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_HALTED) |
bcef3fd5 SS |
1840 | return 1; |
1841 | ||
1842 | return 0; | |
1843 | } | |
1844 | ||
b45b5069 SS |
1845 | int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code) |
1846 | { | |
1847 | if (trb_comp_code >= 224 && trb_comp_code <= 255) { | |
1848 | /* Vendor defined "informational" completion code, | |
1849 | * treat as not-an-error. | |
1850 | */ | |
1851 | xhci_dbg(xhci, "Vendor defined info completion code %u\n", | |
1852 | trb_comp_code); | |
1853 | xhci_dbg(xhci, "Treating code as success.\n"); | |
1854 | return 1; | |
1855 | } | |
1856 | return 0; | |
1857 | } | |
1858 | ||
55fa4396 FB |
1859 | static int xhci_td_cleanup(struct xhci_hcd *xhci, struct xhci_td *td, |
1860 | struct xhci_ring *ep_ring, int *status) | |
1861 | { | |
55fa4396 FB |
1862 | struct urb *urb = NULL; |
1863 | ||
1864 | /* Clean up the endpoint's TD list */ | |
1865 | urb = td->urb; | |
55fa4396 FB |
1866 | |
1867 | /* if a bounce buffer was used to align this td then unmap it */ | |
a60f2f2f | 1868 | xhci_unmap_td_bounce_buffer(xhci, ep_ring, td); |
55fa4396 FB |
1869 | |
1870 | /* Do one last check of the actual transfer length. | |
1871 | * If the host controller said we transferred more data than the buffer | |
1872 | * length, urb->actual_length will be a very big number (since it's | |
1873 | * unsigned). Play it safe and say we didn't transfer anything. | |
1874 | */ | |
1875 | if (urb->actual_length > urb->transfer_buffer_length) { | |
1876 | xhci_warn(xhci, "URB req %u and actual %u transfer length mismatch\n", | |
1877 | urb->transfer_buffer_length, urb->actual_length); | |
1878 | urb->actual_length = 0; | |
1879 | *status = 0; | |
1880 | } | |
1881 | list_del_init(&td->td_list); | |
1882 | /* Was this TD slated to be cancelled but completed anyway? */ | |
1883 | if (!list_empty(&td->cancelled_td_list)) | |
1884 | list_del_init(&td->cancelled_td_list); | |
1885 | ||
1886 | inc_td_cnt(urb); | |
1887 | /* Giveback the urb when all the tds are completed */ | |
1888 | if (last_td_in_urb(td)) { | |
1889 | if ((urb->actual_length != urb->transfer_buffer_length && | |
1890 | (urb->transfer_flags & URB_SHORT_NOT_OK)) || | |
1891 | (*status != 0 && !usb_endpoint_xfer_isoc(&urb->ep->desc))) | |
1892 | xhci_dbg(xhci, "Giveback URB %p, len = %d, expected = %d, status = %d\n", | |
1893 | urb, urb->actual_length, | |
1894 | urb->transfer_buffer_length, *status); | |
1895 | ||
1896 | /* set isoc urb status to 0 just as EHCI, UHCI, and OHCI */ | |
1897 | if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) | |
1898 | *status = 0; | |
1899 | xhci_giveback_urb_in_irq(xhci, td, *status); | |
1900 | } | |
1901 | ||
1902 | return 0; | |
1903 | } | |
1904 | ||
4422da61 | 1905 | static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td, |
0c341910 | 1906 | struct xhci_transfer_event *event, |
3134bc9c | 1907 | struct xhci_virt_ep *ep, int *status) |
4422da61 AX |
1908 | { |
1909 | struct xhci_virt_device *xdev; | |
4422da61 | 1910 | struct xhci_ep_ctx *ep_ctx; |
be0f50c2 | 1911 | struct xhci_ring *ep_ring; |
be0f50c2 | 1912 | unsigned int slot_id; |
4422da61 | 1913 | u32 trb_comp_code; |
be0f50c2 | 1914 | int ep_index; |
4422da61 | 1915 | |
28ccd296 | 1916 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
4422da61 | 1917 | xdev = xhci->devs[slot_id]; |
28ccd296 ME |
1918 | ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1; |
1919 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); | |
4422da61 | 1920 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
28ccd296 | 1921 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); |
4422da61 | 1922 | |
0b7c105a FB |
1923 | if (trb_comp_code == COMP_STOPPED_LENGTH_INVALID || |
1924 | trb_comp_code == COMP_STOPPED || | |
1925 | trb_comp_code == COMP_STOPPED_SHORT_PACKET) { | |
4422da61 AX |
1926 | /* The Endpoint Stop Command completion will take care of any |
1927 | * stopped TDs. A stopped TD may be restarted, so don't update | |
1928 | * the ring dequeue pointer or take this TD off any lists yet. | |
1929 | */ | |
4422da61 | 1930 | return 0; |
69defe04 | 1931 | } |
0b7c105a | 1932 | if (trb_comp_code == COMP_STALL_ERROR || |
69defe04 MN |
1933 | xhci_requires_manual_halt_cleanup(xhci, ep_ctx, |
1934 | trb_comp_code)) { | |
1935 | /* Issue a reset endpoint command to clear the host side | |
1936 | * halt, followed by a set dequeue command to move the | |
1937 | * dequeue pointer past the TD. | |
1938 | * The class driver clears the device side halt later. | |
1939 | */ | |
1940 | xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index, | |
5fee5a5a | 1941 | ep_ring->stream_id, td, EP_HARD_RESET); |
4422da61 | 1942 | } else { |
69defe04 MN |
1943 | /* Update ring dequeue pointer */ |
1944 | while (ep_ring->dequeue != td->last_trb) | |
3b72fca0 | 1945 | inc_deq(xhci, ep_ring); |
69defe04 MN |
1946 | inc_deq(xhci, ep_ring); |
1947 | } | |
4422da61 | 1948 | |
55fa4396 | 1949 | return xhci_td_cleanup(xhci, td, ep_ring, status); |
4422da61 AX |
1950 | } |
1951 | ||
30a65b45 MN |
1952 | /* sum trb lengths from ring dequeue up to stop_trb, _excluding_ stop_trb */ |
1953 | static int sum_trb_lengths(struct xhci_hcd *xhci, struct xhci_ring *ring, | |
1954 | union xhci_trb *stop_trb) | |
1955 | { | |
1956 | u32 sum; | |
1957 | union xhci_trb *trb = ring->dequeue; | |
1958 | struct xhci_segment *seg = ring->deq_seg; | |
1959 | ||
1960 | for (sum = 0; trb != stop_trb; next_trb(xhci, ring, &seg, &trb)) { | |
1961 | if (!trb_is_noop(trb) && !trb_is_link(trb)) | |
1962 | sum += TRB_LEN(le32_to_cpu(trb->generic.field[2])); | |
1963 | } | |
1964 | return sum; | |
1965 | } | |
1966 | ||
8af56be1 AX |
1967 | /* |
1968 | * Process control tds, update urb status and actual_length. | |
1969 | */ | |
1970 | static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td, | |
f97c08ae | 1971 | union xhci_trb *ep_trb, struct xhci_transfer_event *event, |
8af56be1 AX |
1972 | struct xhci_virt_ep *ep, int *status) |
1973 | { | |
1974 | struct xhci_virt_device *xdev; | |
8af56be1 AX |
1975 | unsigned int slot_id; |
1976 | int ep_index; | |
1977 | struct xhci_ep_ctx *ep_ctx; | |
1978 | u32 trb_comp_code; | |
0b6c324c | 1979 | u32 remaining, requested; |
29fc1aa4 | 1980 | u32 trb_type; |
8af56be1 | 1981 | |
29fc1aa4 | 1982 | trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(ep_trb->generic.field[3])); |
28ccd296 | 1983 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
8af56be1 | 1984 | xdev = xhci->devs[slot_id]; |
28ccd296 | 1985 | ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1; |
8af56be1 | 1986 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
28ccd296 | 1987 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); |
0b6c324c MN |
1988 | requested = td->urb->transfer_buffer_length; |
1989 | remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); | |
1990 | ||
8af56be1 AX |
1991 | switch (trb_comp_code) { |
1992 | case COMP_SUCCESS: | |
29fc1aa4 | 1993 | if (trb_type != TRB_STATUS) { |
0b6c324c | 1994 | xhci_warn(xhci, "WARN: Success on ctrl %s TRB without IOC set?\n", |
29fc1aa4 | 1995 | (trb_type == TRB_DATA) ? "data" : "setup"); |
8af56be1 | 1996 | *status = -ESHUTDOWN; |
0b6c324c | 1997 | break; |
8af56be1 | 1998 | } |
0b6c324c | 1999 | *status = 0; |
8af56be1 | 2000 | break; |
0b7c105a | 2001 | case COMP_SHORT_PACKET: |
0b6c324c | 2002 | *status = 0; |
8af56be1 | 2003 | break; |
0b7c105a | 2004 | case COMP_STOPPED_SHORT_PACKET: |
29fc1aa4 | 2005 | if (trb_type == TRB_DATA || trb_type == TRB_NORMAL) |
0b6c324c | 2006 | td->urb->actual_length = remaining; |
40a3b775 | 2007 | else |
0b6c324c MN |
2008 | xhci_warn(xhci, "WARN: Stopped Short Packet on ctrl setup or status TRB\n"); |
2009 | goto finish_td; | |
0b7c105a | 2010 | case COMP_STOPPED: |
29fc1aa4 FB |
2011 | switch (trb_type) { |
2012 | case TRB_SETUP: | |
2013 | td->urb->actual_length = 0; | |
2014 | goto finish_td; | |
2015 | case TRB_DATA: | |
2016 | case TRB_NORMAL: | |
0b6c324c | 2017 | td->urb->actual_length = requested - remaining; |
29fc1aa4 | 2018 | goto finish_td; |
0ab2881a MN |
2019 | case TRB_STATUS: |
2020 | td->urb->actual_length = requested; | |
2021 | goto finish_td; | |
29fc1aa4 FB |
2022 | default: |
2023 | xhci_warn(xhci, "WARN: unexpected TRB Type %d\n", | |
2024 | trb_type); | |
2025 | goto finish_td; | |
2026 | } | |
0b7c105a | 2027 | case COMP_STOPPED_LENGTH_INVALID: |
0b6c324c | 2028 | goto finish_td; |
8af56be1 AX |
2029 | default: |
2030 | if (!xhci_requires_manual_halt_cleanup(xhci, | |
0b6c324c | 2031 | ep_ctx, trb_comp_code)) |
8af56be1 | 2032 | break; |
0b6c324c MN |
2033 | xhci_dbg(xhci, "TRB error %u, halted endpoint index = %u\n", |
2034 | trb_comp_code, ep_index); | |
8af56be1 | 2035 | /* else fall through */ |
0b7c105a | 2036 | case COMP_STALL_ERROR: |
8af56be1 | 2037 | /* Did we transfer part of the data (middle) phase? */ |
29fc1aa4 | 2038 | if (trb_type == TRB_DATA || trb_type == TRB_NORMAL) |
0b6c324c | 2039 | td->urb->actual_length = requested - remaining; |
22ae47e6 | 2040 | else if (!td->urb_length_set) |
8af56be1 | 2041 | td->urb->actual_length = 0; |
0b6c324c | 2042 | goto finish_td; |
8af56be1 | 2043 | } |
0b6c324c MN |
2044 | |
2045 | /* stopped at setup stage, no data transferred */ | |
29fc1aa4 | 2046 | if (trb_type == TRB_SETUP) |
0b6c324c MN |
2047 | goto finish_td; |
2048 | ||
8af56be1 | 2049 | /* |
0b6c324c MN |
2050 | * if on data stage then update the actual_length of the URB and flag it |
2051 | * as set, so it won't be overwritten in the event for the last TRB. | |
8af56be1 | 2052 | */ |
29fc1aa4 FB |
2053 | if (trb_type == TRB_DATA || |
2054 | trb_type == TRB_NORMAL) { | |
0b6c324c MN |
2055 | td->urb_length_set = true; |
2056 | td->urb->actual_length = requested - remaining; | |
2057 | xhci_dbg(xhci, "Waiting for status stage event\n"); | |
2058 | return 0; | |
8af56be1 AX |
2059 | } |
2060 | ||
0b6c324c MN |
2061 | /* at status stage */ |
2062 | if (!td->urb_length_set) | |
2063 | td->urb->actual_length = requested; | |
2064 | ||
2065 | finish_td: | |
0c341910 | 2066 | return finish_td(xhci, td, event, ep, status); |
8af56be1 AX |
2067 | } |
2068 | ||
04e51901 AX |
2069 | /* |
2070 | * Process isochronous tds, update urb packet status and actual_length. | |
2071 | */ | |
2072 | static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td, | |
f97c08ae | 2073 | union xhci_trb *ep_trb, struct xhci_transfer_event *event, |
04e51901 AX |
2074 | struct xhci_virt_ep *ep, int *status) |
2075 | { | |
2076 | struct xhci_ring *ep_ring; | |
2077 | struct urb_priv *urb_priv; | |
2078 | int idx; | |
926008c9 | 2079 | struct usb_iso_packet_descriptor *frame; |
04e51901 | 2080 | u32 trb_comp_code; |
36da3a1d MN |
2081 | bool sum_trbs_for_length = false; |
2082 | u32 remaining, requested, ep_trb_len; | |
2083 | int short_framestatus; | |
04e51901 | 2084 | |
28ccd296 ME |
2085 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); |
2086 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); | |
04e51901 | 2087 | urb_priv = td->urb->hcpriv; |
9ef7fbbb | 2088 | idx = urb_priv->num_tds_done; |
926008c9 | 2089 | frame = &td->urb->iso_frame_desc[idx]; |
36da3a1d MN |
2090 | requested = frame->length; |
2091 | remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); | |
2092 | ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2])); | |
2093 | short_framestatus = td->urb->transfer_flags & URB_SHORT_NOT_OK ? | |
2094 | -EREMOTEIO : 0; | |
04e51901 | 2095 | |
926008c9 DT |
2096 | /* handle completion code */ |
2097 | switch (trb_comp_code) { | |
2098 | case COMP_SUCCESS: | |
36da3a1d MN |
2099 | if (remaining) { |
2100 | frame->status = short_framestatus; | |
2101 | if (xhci->quirks & XHCI_TRUST_TX_LENGTH) | |
2102 | sum_trbs_for_length = true; | |
1530bbc6 SS |
2103 | break; |
2104 | } | |
36da3a1d MN |
2105 | frame->status = 0; |
2106 | break; | |
0b7c105a | 2107 | case COMP_SHORT_PACKET: |
36da3a1d MN |
2108 | frame->status = short_framestatus; |
2109 | sum_trbs_for_length = true; | |
926008c9 | 2110 | break; |
0b7c105a | 2111 | case COMP_BANDWIDTH_OVERRUN_ERROR: |
926008c9 | 2112 | frame->status = -ECOMM; |
926008c9 | 2113 | break; |
0b7c105a FB |
2114 | case COMP_ISOCH_BUFFER_OVERRUN: |
2115 | case COMP_BABBLE_DETECTED_ERROR: | |
926008c9 | 2116 | frame->status = -EOVERFLOW; |
926008c9 | 2117 | break; |
0b7c105a FB |
2118 | case COMP_INCOMPATIBLE_DEVICE_ERROR: |
2119 | case COMP_STALL_ERROR: | |
d104d015 | 2120 | frame->status = -EPROTO; |
d104d015 | 2121 | break; |
0b7c105a | 2122 | case COMP_USB_TRANSACTION_ERROR: |
926008c9 | 2123 | frame->status = -EPROTO; |
f97c08ae | 2124 | if (ep_trb != td->last_trb) |
d104d015 | 2125 | return 0; |
926008c9 | 2126 | break; |
0b7c105a | 2127 | case COMP_STOPPED: |
36da3a1d MN |
2128 | sum_trbs_for_length = true; |
2129 | break; | |
0b7c105a | 2130 | case COMP_STOPPED_SHORT_PACKET: |
36da3a1d MN |
2131 | /* field normally containing residue now contains tranferred */ |
2132 | frame->status = short_framestatus; | |
2133 | requested = remaining; | |
2134 | break; | |
0b7c105a | 2135 | case COMP_STOPPED_LENGTH_INVALID: |
36da3a1d MN |
2136 | requested = 0; |
2137 | remaining = 0; | |
926008c9 DT |
2138 | break; |
2139 | default: | |
36da3a1d | 2140 | sum_trbs_for_length = true; |
926008c9 DT |
2141 | frame->status = -1; |
2142 | break; | |
04e51901 AX |
2143 | } |
2144 | ||
36da3a1d MN |
2145 | if (sum_trbs_for_length) |
2146 | frame->actual_length = sum_trb_lengths(xhci, ep_ring, ep_trb) + | |
2147 | ep_trb_len - remaining; | |
2148 | else | |
2149 | frame->actual_length = requested; | |
04e51901 | 2150 | |
36da3a1d | 2151 | td->urb->actual_length += frame->actual_length; |
04e51901 | 2152 | |
0c341910 | 2153 | return finish_td(xhci, td, event, ep, status); |
04e51901 AX |
2154 | } |
2155 | ||
926008c9 DT |
2156 | static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td, |
2157 | struct xhci_transfer_event *event, | |
2158 | struct xhci_virt_ep *ep, int *status) | |
2159 | { | |
2160 | struct xhci_ring *ep_ring; | |
2161 | struct urb_priv *urb_priv; | |
2162 | struct usb_iso_packet_descriptor *frame; | |
2163 | int idx; | |
2164 | ||
f6975314 | 2165 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); |
926008c9 | 2166 | urb_priv = td->urb->hcpriv; |
9ef7fbbb | 2167 | idx = urb_priv->num_tds_done; |
926008c9 DT |
2168 | frame = &td->urb->iso_frame_desc[idx]; |
2169 | ||
b3df3f9c | 2170 | /* The transfer is partly done. */ |
926008c9 DT |
2171 | frame->status = -EXDEV; |
2172 | ||
2173 | /* calc actual length */ | |
2174 | frame->actual_length = 0; | |
2175 | ||
2176 | /* Update ring dequeue pointer */ | |
2177 | while (ep_ring->dequeue != td->last_trb) | |
3b72fca0 AX |
2178 | inc_deq(xhci, ep_ring); |
2179 | inc_deq(xhci, ep_ring); | |
926008c9 | 2180 | |
3134bc9c | 2181 | return xhci_td_cleanup(xhci, td, ep_ring, status); |
926008c9 DT |
2182 | } |
2183 | ||
22405ed2 AX |
2184 | /* |
2185 | * Process bulk and interrupt tds, update urb status and actual_length. | |
2186 | */ | |
2187 | static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td, | |
f97c08ae | 2188 | union xhci_trb *ep_trb, struct xhci_transfer_event *event, |
22405ed2 AX |
2189 | struct xhci_virt_ep *ep, int *status) |
2190 | { | |
f8f80be5 | 2191 | struct xhci_slot_ctx *slot_ctx; |
22405ed2 | 2192 | struct xhci_ring *ep_ring; |
22405ed2 | 2193 | u32 trb_comp_code; |
f97c08ae | 2194 | u32 remaining, requested, ep_trb_len; |
f8f80be5 MN |
2195 | unsigned int slot_id; |
2196 | int ep_index; | |
22405ed2 | 2197 | |
f8f80be5 MN |
2198 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
2199 | slot_ctx = xhci_get_slot_ctx(xhci, xhci->devs[slot_id]->out_ctx); | |
2200 | ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1; | |
28ccd296 ME |
2201 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); |
2202 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); | |
30a65b45 | 2203 | remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); |
f97c08ae | 2204 | ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2])); |
30a65b45 | 2205 | requested = td->urb->transfer_buffer_length; |
22405ed2 AX |
2206 | |
2207 | switch (trb_comp_code) { | |
2208 | case COMP_SUCCESS: | |
f8f80be5 | 2209 | ep_ring->err_count = 0; |
30a65b45 | 2210 | /* handle success with untransferred data as short packet */ |
f97c08ae | 2211 | if (ep_trb != td->last_trb || remaining) { |
52ab8685 | 2212 | xhci_warn(xhci, "WARN Successful completion on short TX\n"); |
30a65b45 MN |
2213 | xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n", |
2214 | td->urb->ep->desc.bEndpointAddress, | |
2215 | requested, remaining); | |
22405ed2 | 2216 | } |
52ab8685 | 2217 | *status = 0; |
22405ed2 | 2218 | break; |
0b7c105a | 2219 | case COMP_SHORT_PACKET: |
30a65b45 MN |
2220 | xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n", |
2221 | td->urb->ep->desc.bEndpointAddress, | |
2222 | requested, remaining); | |
52ab8685 | 2223 | *status = 0; |
22405ed2 | 2224 | break; |
0b7c105a | 2225 | case COMP_STOPPED_SHORT_PACKET: |
30a65b45 MN |
2226 | td->urb->actual_length = remaining; |
2227 | goto finish_td; | |
0b7c105a | 2228 | case COMP_STOPPED_LENGTH_INVALID: |
30a65b45 | 2229 | /* stopped on ep trb with invalid length, exclude it */ |
f97c08ae | 2230 | ep_trb_len = 0; |
30a65b45 MN |
2231 | remaining = 0; |
2232 | break; | |
f8f80be5 MN |
2233 | case COMP_USB_TRANSACTION_ERROR: |
2234 | if ((ep_ring->err_count++ > MAX_SOFT_RETRY) || | |
2235 | le32_to_cpu(slot_ctx->tt_info) & TT_SLOT) | |
2236 | break; | |
2237 | *status = 0; | |
2238 | xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index, | |
2239 | ep_ring->stream_id, td, EP_SOFT_RESET); | |
2240 | return 0; | |
22405ed2 | 2241 | default: |
30a65b45 | 2242 | /* do nothing */ |
22405ed2 AX |
2243 | break; |
2244 | } | |
40a3b775 | 2245 | |
f97c08ae | 2246 | if (ep_trb == td->last_trb) |
30a65b45 MN |
2247 | td->urb->actual_length = requested - remaining; |
2248 | else | |
2249 | td->urb->actual_length = | |
f97c08ae MN |
2250 | sum_trb_lengths(xhci, ep_ring, ep_trb) + |
2251 | ep_trb_len - remaining; | |
30a65b45 MN |
2252 | finish_td: |
2253 | if (remaining > requested) { | |
2254 | xhci_warn(xhci, "bad transfer trb length %d in event trb\n", | |
2255 | remaining); | |
22405ed2 | 2256 | td->urb->actual_length = 0; |
22405ed2 | 2257 | } |
0c341910 | 2258 | return finish_td(xhci, td, event, ep, status); |
22405ed2 AX |
2259 | } |
2260 | ||
d0e96f5a SS |
2261 | /* |
2262 | * If this function returns an error condition, it means it got a Transfer | |
2263 | * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address. | |
2264 | * At this point, the host controller is probably hosed and should be reset. | |
2265 | */ | |
2266 | static int handle_tx_event(struct xhci_hcd *xhci, | |
2267 | struct xhci_transfer_event *event) | |
2268 | { | |
2269 | struct xhci_virt_device *xdev; | |
63a0d9ab | 2270 | struct xhci_virt_ep *ep; |
d0e96f5a | 2271 | struct xhci_ring *ep_ring; |
82d1009f | 2272 | unsigned int slot_id; |
d0e96f5a | 2273 | int ep_index; |
326b4810 | 2274 | struct xhci_td *td = NULL; |
f97c08ae MN |
2275 | dma_addr_t ep_trb_dma; |
2276 | struct xhci_segment *ep_seg; | |
2277 | union xhci_trb *ep_trb; | |
d0e96f5a | 2278 | int status = -EINPROGRESS; |
d115b048 | 2279 | struct xhci_ep_ctx *ep_ctx; |
c2d7b49f | 2280 | struct list_head *tmp; |
66d1eebc | 2281 | u32 trb_comp_code; |
c2d7b49f | 2282 | int td_num = 0; |
3b4739b8 | 2283 | bool handling_skipped_tds = false; |
d0e96f5a | 2284 | |
28ccd296 | 2285 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
b3368382 MN |
2286 | ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1; |
2287 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); | |
2288 | ep_trb_dma = le64_to_cpu(event->buffer); | |
2289 | ||
82d1009f | 2290 | xdev = xhci->devs[slot_id]; |
d0e96f5a | 2291 | if (!xdev) { |
b7f769ae ZX |
2292 | xhci_err(xhci, "ERROR Transfer event pointed to bad slot %u\n", |
2293 | slot_id); | |
b3368382 MN |
2294 | goto err_out; |
2295 | } | |
2296 | ||
63a0d9ab | 2297 | ep = &xdev->eps[ep_index]; |
b3368382 | 2298 | ep_ring = xhci_dma_to_transfer_ring(ep, ep_trb_dma); |
d115b048 | 2299 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
b3368382 | 2300 | |
ade2e3a1 | 2301 | if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) { |
b7f769ae | 2302 | xhci_err(xhci, |
ade2e3a1 | 2303 | "ERROR Transfer event for disabled endpoint slot %u ep %u\n", |
b7f769ae | 2304 | slot_id, ep_index); |
b3368382 | 2305 | goto err_out; |
d0e96f5a SS |
2306 | } |
2307 | ||
ade2e3a1 MN |
2308 | /* Some transfer events don't always point to a trb, see xhci 4.17.4 */ |
2309 | if (!ep_ring) { | |
2310 | switch (trb_comp_code) { | |
2311 | case COMP_STALL_ERROR: | |
2312 | case COMP_USB_TRANSACTION_ERROR: | |
2313 | case COMP_INVALID_STREAM_TYPE_ERROR: | |
2314 | case COMP_INVALID_STREAM_ID_ERROR: | |
2315 | xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index, 0, | |
5fee5a5a | 2316 | NULL, EP_SOFT_RESET); |
ade2e3a1 MN |
2317 | goto cleanup; |
2318 | case COMP_RING_UNDERRUN: | |
2319 | case COMP_RING_OVERRUN: | |
d9193efb | 2320 | case COMP_STOPPED_LENGTH_INVALID: |
ade2e3a1 MN |
2321 | goto cleanup; |
2322 | default: | |
2323 | xhci_err(xhci, "ERROR Transfer event for unknown stream ring slot %u ep %u\n", | |
2324 | slot_id, ep_index); | |
2325 | goto err_out; | |
2326 | } | |
2327 | } | |
2328 | ||
c2d7b49f AX |
2329 | /* Count current td numbers if ep->skip is set */ |
2330 | if (ep->skip) { | |
2331 | list_for_each(tmp, &ep_ring->td_list) | |
2332 | td_num++; | |
2333 | } | |
2334 | ||
986a92d4 | 2335 | /* Look for common error cases */ |
66d1eebc | 2336 | switch (trb_comp_code) { |
b10de142 SS |
2337 | /* Skip codes that require special handling depending on |
2338 | * transfer type | |
2339 | */ | |
2340 | case COMP_SUCCESS: | |
1c11a172 | 2341 | if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) |
1530bbc6 SS |
2342 | break; |
2343 | if (xhci->quirks & XHCI_TRUST_TX_LENGTH) | |
0b7c105a | 2344 | trb_comp_code = COMP_SHORT_PACKET; |
1530bbc6 | 2345 | else |
8202ce2e | 2346 | xhci_warn_ratelimited(xhci, |
b7f769ae ZX |
2347 | "WARN Successful completion on short TX for slot %u ep %u: needs XHCI_TRUST_TX_LENGTH quirk?\n", |
2348 | slot_id, ep_index); | |
0b7c105a | 2349 | case COMP_SHORT_PACKET: |
b10de142 | 2350 | break; |
b3368382 | 2351 | /* Completion codes for endpoint stopped state */ |
0b7c105a | 2352 | case COMP_STOPPED: |
b7f769ae ZX |
2353 | xhci_dbg(xhci, "Stopped on Transfer TRB for slot %u ep %u\n", |
2354 | slot_id, ep_index); | |
ae636747 | 2355 | break; |
0b7c105a | 2356 | case COMP_STOPPED_LENGTH_INVALID: |
b7f769ae ZX |
2357 | xhci_dbg(xhci, |
2358 | "Stopped on No-op or Link TRB for slot %u ep %u\n", | |
2359 | slot_id, ep_index); | |
ae636747 | 2360 | break; |
0b7c105a | 2361 | case COMP_STOPPED_SHORT_PACKET: |
b7f769ae ZX |
2362 | xhci_dbg(xhci, |
2363 | "Stopped with short packet transfer detected for slot %u ep %u\n", | |
2364 | slot_id, ep_index); | |
40a3b775 | 2365 | break; |
b3368382 | 2366 | /* Completion codes for endpoint halted state */ |
0b7c105a | 2367 | case COMP_STALL_ERROR: |
b7f769ae ZX |
2368 | xhci_dbg(xhci, "Stalled endpoint for slot %u ep %u\n", slot_id, |
2369 | ep_index); | |
63a0d9ab | 2370 | ep->ep_state |= EP_HALTED; |
b10de142 SS |
2371 | status = -EPIPE; |
2372 | break; | |
0b7c105a FB |
2373 | case COMP_SPLIT_TRANSACTION_ERROR: |
2374 | case COMP_USB_TRANSACTION_ERROR: | |
b7f769ae ZX |
2375 | xhci_dbg(xhci, "Transfer error for slot %u ep %u on endpoint\n", |
2376 | slot_id, ep_index); | |
b10de142 SS |
2377 | status = -EPROTO; |
2378 | break; | |
0b7c105a | 2379 | case COMP_BABBLE_DETECTED_ERROR: |
b7f769ae ZX |
2380 | xhci_dbg(xhci, "Babble error for slot %u ep %u on endpoint\n", |
2381 | slot_id, ep_index); | |
4a73143c SS |
2382 | status = -EOVERFLOW; |
2383 | break; | |
b3368382 MN |
2384 | /* Completion codes for endpoint error state */ |
2385 | case COMP_TRB_ERROR: | |
2386 | xhci_warn(xhci, | |
2387 | "WARN: TRB error for slot %u ep %u on endpoint\n", | |
2388 | slot_id, ep_index); | |
2389 | status = -EILSEQ; | |
2390 | break; | |
2391 | /* completion codes not indicating endpoint state change */ | |
0b7c105a | 2392 | case COMP_DATA_BUFFER_ERROR: |
b7f769ae ZX |
2393 | xhci_warn(xhci, |
2394 | "WARN: HC couldn't access mem fast enough for slot %u ep %u\n", | |
2395 | slot_id, ep_index); | |
b10de142 SS |
2396 | status = -ENOSR; |
2397 | break; | |
0b7c105a | 2398 | case COMP_BANDWIDTH_OVERRUN_ERROR: |
b7f769ae ZX |
2399 | xhci_warn(xhci, |
2400 | "WARN: bandwidth overrun event for slot %u ep %u on endpoint\n", | |
2401 | slot_id, ep_index); | |
986a92d4 | 2402 | break; |
0b7c105a | 2403 | case COMP_ISOCH_BUFFER_OVERRUN: |
b7f769ae ZX |
2404 | xhci_warn(xhci, |
2405 | "WARN: buffer overrun event for slot %u ep %u on endpoint", | |
2406 | slot_id, ep_index); | |
986a92d4 | 2407 | break; |
0b7c105a | 2408 | case COMP_RING_UNDERRUN: |
986a92d4 AX |
2409 | /* |
2410 | * When the Isoch ring is empty, the xHC will generate | |
2411 | * a Ring Overrun Event for IN Isoch endpoint or Ring | |
2412 | * Underrun Event for OUT Isoch endpoint. | |
2413 | */ | |
2414 | xhci_dbg(xhci, "underrun event on endpoint\n"); | |
2415 | if (!list_empty(&ep_ring->td_list)) | |
2416 | xhci_dbg(xhci, "Underrun Event for slot %d ep %d " | |
2417 | "still with TDs queued?\n", | |
28ccd296 ME |
2418 | TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), |
2419 | ep_index); | |
986a92d4 | 2420 | goto cleanup; |
0b7c105a | 2421 | case COMP_RING_OVERRUN: |
986a92d4 AX |
2422 | xhci_dbg(xhci, "overrun event on endpoint\n"); |
2423 | if (!list_empty(&ep_ring->td_list)) | |
2424 | xhci_dbg(xhci, "Overrun Event for slot %d ep %d " | |
2425 | "still with TDs queued?\n", | |
28ccd296 ME |
2426 | TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), |
2427 | ep_index); | |
986a92d4 | 2428 | goto cleanup; |
0b7c105a | 2429 | case COMP_MISSED_SERVICE_ERROR: |
d18240db AX |
2430 | /* |
2431 | * When encounter missed service error, one or more isoc tds | |
2432 | * may be missed by xHC. | |
2433 | * Set skip flag of the ep_ring; Complete the missed tds as | |
2434 | * short transfer when process the ep_ring next time. | |
2435 | */ | |
2436 | ep->skip = true; | |
b7f769ae ZX |
2437 | xhci_dbg(xhci, |
2438 | "Miss service interval error for slot %u ep %u, set skip flag\n", | |
2439 | slot_id, ep_index); | |
d18240db | 2440 | goto cleanup; |
0b7c105a | 2441 | case COMP_NO_PING_RESPONSE_ERROR: |
3b4739b8 | 2442 | ep->skip = true; |
b7f769ae ZX |
2443 | xhci_dbg(xhci, |
2444 | "No Ping response error for slot %u ep %u, Skip one Isoc TD\n", | |
2445 | slot_id, ep_index); | |
3b4739b8 | 2446 | goto cleanup; |
b3368382 MN |
2447 | |
2448 | case COMP_INCOMPATIBLE_DEVICE_ERROR: | |
2449 | /* needs disable slot command to recover */ | |
2450 | xhci_warn(xhci, | |
2451 | "WARN: detect an incompatible device for slot %u ep %u", | |
2452 | slot_id, ep_index); | |
2453 | status = -EPROTO; | |
2454 | break; | |
b10de142 | 2455 | default: |
b45b5069 | 2456 | if (xhci_is_vendor_info_code(xhci, trb_comp_code)) { |
5ad6a529 SS |
2457 | status = 0; |
2458 | break; | |
2459 | } | |
b7f769ae ZX |
2460 | xhci_warn(xhci, |
2461 | "ERROR Unknown event condition %u for slot %u ep %u , HC probably busted\n", | |
2462 | trb_comp_code, slot_id, ep_index); | |
986a92d4 AX |
2463 | goto cleanup; |
2464 | } | |
2465 | ||
d18240db AX |
2466 | do { |
2467 | /* This TRB should be in the TD at the head of this ring's | |
2468 | * TD list. | |
2469 | */ | |
2470 | if (list_empty(&ep_ring->td_list)) { | |
a83d6755 | 2471 | /* |
e4ec40ec MN |
2472 | * Don't print wanings if it's due to a stopped endpoint |
2473 | * generating an extra completion event if the device | |
2474 | * was suspended. Or, a event for the last TRB of a | |
2475 | * short TD we already got a short event for. | |
2476 | * The short TD is already removed from the TD list. | |
a83d6755 | 2477 | */ |
e4ec40ec | 2478 | |
0b7c105a | 2479 | if (!(trb_comp_code == COMP_STOPPED || |
e4ec40ec MN |
2480 | trb_comp_code == COMP_STOPPED_LENGTH_INVALID || |
2481 | ep_ring->last_td_was_short)) { | |
a83d6755 SS |
2482 | xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n", |
2483 | TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), | |
2484 | ep_index); | |
a83d6755 | 2485 | } |
d18240db AX |
2486 | if (ep->skip) { |
2487 | ep->skip = false; | |
b7f769ae ZX |
2488 | xhci_dbg(xhci, "td_list is empty while skip flag set. Clear skip flag for slot %u ep %u.\n", |
2489 | slot_id, ep_index); | |
d18240db | 2490 | } |
d18240db AX |
2491 | goto cleanup; |
2492 | } | |
986a92d4 | 2493 | |
c2d7b49f AX |
2494 | /* We've skipped all the TDs on the ep ring when ep->skip set */ |
2495 | if (ep->skip && td_num == 0) { | |
2496 | ep->skip = false; | |
b7f769ae ZX |
2497 | xhci_dbg(xhci, "All tds on the ep_ring skipped. Clear skip flag for slot %u ep %u.\n", |
2498 | slot_id, ep_index); | |
c2d7b49f AX |
2499 | goto cleanup; |
2500 | } | |
2501 | ||
04861f83 FB |
2502 | td = list_first_entry(&ep_ring->td_list, struct xhci_td, |
2503 | td_list); | |
c2d7b49f AX |
2504 | if (ep->skip) |
2505 | td_num--; | |
926008c9 | 2506 | |
d18240db | 2507 | /* Is this a TRB in the currently executing TD? */ |
f97c08ae MN |
2508 | ep_seg = trb_in_td(xhci, ep_ring->deq_seg, ep_ring->dequeue, |
2509 | td->last_trb, ep_trb_dma, false); | |
e1cf486d AH |
2510 | |
2511 | /* | |
2512 | * Skip the Force Stopped Event. The event_trb(event_dma) of FSE | |
2513 | * is not in the current TD pointed by ep_ring->dequeue because | |
2514 | * that the hardware dequeue pointer still at the previous TRB | |
2515 | * of the current TD. The previous TRB maybe a Link TD or the | |
2516 | * last TRB of the previous TD. The command completion handle | |
2517 | * will take care the rest. | |
2518 | */ | |
0b7c105a FB |
2519 | if (!ep_seg && (trb_comp_code == COMP_STOPPED || |
2520 | trb_comp_code == COMP_STOPPED_LENGTH_INVALID)) { | |
e1cf486d AH |
2521 | goto cleanup; |
2522 | } | |
2523 | ||
f97c08ae | 2524 | if (!ep_seg) { |
926008c9 DT |
2525 | if (!ep->skip || |
2526 | !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) { | |
ad808333 SS |
2527 | /* Some host controllers give a spurious |
2528 | * successful event after a short transfer. | |
2529 | * Ignore it. | |
2530 | */ | |
ddba5cd0 | 2531 | if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) && |
ad808333 SS |
2532 | ep_ring->last_td_was_short) { |
2533 | ep_ring->last_td_was_short = false; | |
ad808333 SS |
2534 | goto cleanup; |
2535 | } | |
926008c9 DT |
2536 | /* HC is busted, give up! */ |
2537 | xhci_err(xhci, | |
2538 | "ERROR Transfer event TRB DMA ptr not " | |
cffb9be8 HG |
2539 | "part of current TD ep_index %d " |
2540 | "comp_code %u\n", ep_index, | |
2541 | trb_comp_code); | |
2542 | trb_in_td(xhci, ep_ring->deq_seg, | |
2543 | ep_ring->dequeue, td->last_trb, | |
f97c08ae | 2544 | ep_trb_dma, true); |
926008c9 DT |
2545 | return -ESHUTDOWN; |
2546 | } | |
2547 | ||
0c03d89d | 2548 | skip_isoc_td(xhci, td, event, ep, &status); |
926008c9 DT |
2549 | goto cleanup; |
2550 | } | |
0b7c105a | 2551 | if (trb_comp_code == COMP_SHORT_PACKET) |
ad808333 SS |
2552 | ep_ring->last_td_was_short = true; |
2553 | else | |
2554 | ep_ring->last_td_was_short = false; | |
926008c9 DT |
2555 | |
2556 | if (ep->skip) { | |
b7f769ae ZX |
2557 | xhci_dbg(xhci, |
2558 | "Found td. Clear skip flag for slot %u ep %u.\n", | |
2559 | slot_id, ep_index); | |
d18240db AX |
2560 | ep->skip = false; |
2561 | } | |
678539cf | 2562 | |
f97c08ae MN |
2563 | ep_trb = &ep_seg->trbs[(ep_trb_dma - ep_seg->dma) / |
2564 | sizeof(*ep_trb)]; | |
a37c3f76 FB |
2565 | |
2566 | trace_xhci_handle_transfer(ep_ring, | |
2567 | (struct xhci_generic_trb *) ep_trb); | |
2568 | ||
926008c9 | 2569 | /* |
810a624b LB |
2570 | * No-op TRB could trigger interrupts in a case where |
2571 | * a URB was killed and a STALL_ERROR happens right | |
2572 | * after the endpoint ring stopped. Reset the halted | |
2573 | * endpoint. Otherwise, the endpoint remains stalled | |
2574 | * indefinitely. | |
926008c9 | 2575 | */ |
f97c08ae | 2576 | if (trb_is_noop(ep_trb)) { |
810a624b LB |
2577 | if (trb_comp_code == COMP_STALL_ERROR || |
2578 | xhci_requires_manual_halt_cleanup(xhci, ep_ctx, | |
2579 | trb_comp_code)) | |
2580 | xhci_cleanup_halted_endpoint(xhci, slot_id, | |
2581 | ep_index, | |
2582 | ep_ring->stream_id, | |
5fee5a5a | 2583 | td, EP_HARD_RESET); |
926008c9 | 2584 | goto cleanup; |
d18240db | 2585 | } |
4422da61 | 2586 | |
0c03d89d | 2587 | /* update the urb's actual_length and give back to the core */ |
d18240db | 2588 | if (usb_endpoint_xfer_control(&td->urb->ep->desc)) |
0c03d89d | 2589 | process_ctrl_td(xhci, td, ep_trb, event, ep, &status); |
04e51901 | 2590 | else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc)) |
0c03d89d | 2591 | process_isoc_td(xhci, td, ep_trb, event, ep, &status); |
d18240db | 2592 | else |
0c03d89d MN |
2593 | process_bulk_intr_td(xhci, td, ep_trb, event, ep, |
2594 | &status); | |
d18240db | 2595 | cleanup: |
3b4739b8 | 2596 | handling_skipped_tds = ep->skip && |
0b7c105a FB |
2597 | trb_comp_code != COMP_MISSED_SERVICE_ERROR && |
2598 | trb_comp_code != COMP_NO_PING_RESPONSE_ERROR; | |
3b4739b8 | 2599 | |
d18240db | 2600 | /* |
3b4739b8 MN |
2601 | * Do not update event ring dequeue pointer if we're in a loop |
2602 | * processing missed tds. | |
d18240db | 2603 | */ |
3b4739b8 | 2604 | if (!handling_skipped_tds) |
3b72fca0 | 2605 | inc_deq(xhci, xhci->event_ring); |
d18240db | 2606 | |
d18240db AX |
2607 | /* |
2608 | * If ep->skip is set, it means there are missed tds on the | |
2609 | * endpoint ring need to take care of. | |
2610 | * Process them as short transfer until reach the td pointed by | |
2611 | * the event. | |
2612 | */ | |
3b4739b8 | 2613 | } while (handling_skipped_tds); |
d18240db | 2614 | |
d0e96f5a | 2615 | return 0; |
b3368382 MN |
2616 | |
2617 | err_out: | |
2618 | xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n", | |
2619 | (unsigned long long) xhci_trb_virt_to_dma( | |
2620 | xhci->event_ring->deq_seg, | |
2621 | xhci->event_ring->dequeue), | |
2622 | lower_32_bits(le64_to_cpu(event->buffer)), | |
2623 | upper_32_bits(le64_to_cpu(event->buffer)), | |
2624 | le32_to_cpu(event->transfer_len), | |
2625 | le32_to_cpu(event->flags)); | |
2626 | return -ENODEV; | |
d0e96f5a SS |
2627 | } |
2628 | ||
0f2a7930 SS |
2629 | /* |
2630 | * This function handles all OS-owned events on the event ring. It may drop | |
2631 | * xhci->lock between event processing (e.g. to pass up port status changes). | |
9dee9a21 ME |
2632 | * Returns >0 for "possibly more events to process" (caller should call again), |
2633 | * otherwise 0 if done. In future, <0 returns should indicate error code. | |
0f2a7930 | 2634 | */ |
9dee9a21 | 2635 | static int xhci_handle_event(struct xhci_hcd *xhci) |
7f84eef0 SS |
2636 | { |
2637 | union xhci_trb *event; | |
0f2a7930 | 2638 | int update_ptrs = 1; |
d0e96f5a | 2639 | int ret; |
7f84eef0 | 2640 | |
f4c8f03c | 2641 | /* Event ring hasn't been allocated yet. */ |
7f84eef0 | 2642 | if (!xhci->event_ring || !xhci->event_ring->dequeue) { |
f4c8f03c LB |
2643 | xhci_err(xhci, "ERROR event ring not ready\n"); |
2644 | return -ENOMEM; | |
7f84eef0 SS |
2645 | } |
2646 | ||
2647 | event = xhci->event_ring->dequeue; | |
2648 | /* Does the HC or OS own the TRB? */ | |
28ccd296 | 2649 | if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) != |
f4c8f03c | 2650 | xhci->event_ring->cycle_state) |
9dee9a21 | 2651 | return 0; |
7f84eef0 | 2652 | |
a37c3f76 FB |
2653 | trace_xhci_handle_event(xhci->event_ring, &event->generic); |
2654 | ||
92a3da41 ME |
2655 | /* |
2656 | * Barrier between reading the TRB_CYCLE (valid) flag above and any | |
2657 | * speculative reads of the event's flags/data below. | |
2658 | */ | |
2659 | rmb(); | |
0f2a7930 | 2660 | /* FIXME: Handle more event types. */ |
f4c8f03c | 2661 | switch (le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) { |
7f84eef0 SS |
2662 | case TRB_TYPE(TRB_COMPLETION): |
2663 | handle_cmd_completion(xhci, &event->event_cmd); | |
2664 | break; | |
0f2a7930 SS |
2665 | case TRB_TYPE(TRB_PORT_STATUS): |
2666 | handle_port_status(xhci, event); | |
2667 | update_ptrs = 0; | |
2668 | break; | |
d0e96f5a SS |
2669 | case TRB_TYPE(TRB_TRANSFER): |
2670 | ret = handle_tx_event(xhci, &event->trans_event); | |
f4c8f03c | 2671 | if (ret >= 0) |
d0e96f5a SS |
2672 | update_ptrs = 0; |
2673 | break; | |
623bef9e SS |
2674 | case TRB_TYPE(TRB_DEV_NOTE): |
2675 | handle_device_notification(xhci, event); | |
2676 | break; | |
7f84eef0 | 2677 | default: |
28ccd296 ME |
2678 | if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >= |
2679 | TRB_TYPE(48)) | |
0238634d SS |
2680 | handle_vendor_event(xhci, event); |
2681 | else | |
f4c8f03c LB |
2682 | xhci_warn(xhci, "ERROR unknown event type %d\n", |
2683 | TRB_FIELD_TO_TYPE( | |
2684 | le32_to_cpu(event->event_cmd.flags))); | |
7f84eef0 | 2685 | } |
6f5165cf SS |
2686 | /* Any of the above functions may drop and re-acquire the lock, so check |
2687 | * to make sure a watchdog timer didn't mark the host as non-responsive. | |
2688 | */ | |
2689 | if (xhci->xhc_state & XHCI_STATE_DYING) { | |
2690 | xhci_dbg(xhci, "xHCI host dying, returning from " | |
2691 | "event handler.\n"); | |
9dee9a21 | 2692 | return 0; |
6f5165cf | 2693 | } |
7f84eef0 | 2694 | |
c06d68b8 SS |
2695 | if (update_ptrs) |
2696 | /* Update SW event ring dequeue pointer */ | |
3b72fca0 | 2697 | inc_deq(xhci, xhci->event_ring); |
c06d68b8 | 2698 | |
9dee9a21 ME |
2699 | /* Are there more items on the event ring? Caller will call us again to |
2700 | * check. | |
2701 | */ | |
2702 | return 1; | |
7f84eef0 | 2703 | } |
9032cd52 SS |
2704 | |
2705 | /* | |
2706 | * xHCI spec says we can get an interrupt, and if the HC has an error condition, | |
2707 | * we might get bad data out of the event ring. Section 4.10.2.7 has a list of | |
2708 | * indicators of an event TRB error, but we check the status *first* to be safe. | |
2709 | */ | |
2710 | irqreturn_t xhci_irq(struct usb_hcd *hcd) | |
2711 | { | |
2712 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
c06d68b8 | 2713 | union xhci_trb *event_ring_deq; |
76a35293 | 2714 | irqreturn_t ret = IRQ_NONE; |
63aea0db | 2715 | unsigned long flags; |
c06d68b8 | 2716 | dma_addr_t deq; |
76a35293 FB |
2717 | u64 temp_64; |
2718 | u32 status; | |
9032cd52 | 2719 | |
63aea0db | 2720 | spin_lock_irqsave(&xhci->lock, flags); |
9032cd52 | 2721 | /* Check if the xHC generated the interrupt, or the irq is shared */ |
b0ba9720 | 2722 | status = readl(&xhci->op_regs->status); |
d9f11ba9 MN |
2723 | if (status == ~(u32)0) { |
2724 | xhci_hc_died(xhci); | |
76a35293 FB |
2725 | ret = IRQ_HANDLED; |
2726 | goto out; | |
9032cd52 | 2727 | } |
76a35293 FB |
2728 | |
2729 | if (!(status & STS_EINT)) | |
2730 | goto out; | |
2731 | ||
27e0dd4d | 2732 | if (status & STS_FATAL) { |
9032cd52 SS |
2733 | xhci_warn(xhci, "WARNING: Host System Error\n"); |
2734 | xhci_halt(xhci); | |
76a35293 FB |
2735 | ret = IRQ_HANDLED; |
2736 | goto out; | |
9032cd52 SS |
2737 | } |
2738 | ||
bda53145 SS |
2739 | /* |
2740 | * Clear the op reg interrupt status first, | |
2741 | * so we can receive interrupts from other MSI-X interrupters. | |
2742 | * Write 1 to clear the interrupt status. | |
2743 | */ | |
27e0dd4d | 2744 | status |= STS_EINT; |
204b7793 | 2745 | writel(status, &xhci->op_regs->status); |
bda53145 | 2746 | |
6a29beef | 2747 | if (!hcd->msi_enabled) { |
c21599a3 | 2748 | u32 irq_pending; |
b0ba9720 | 2749 | irq_pending = readl(&xhci->ir_set->irq_pending); |
4e833c0b | 2750 | irq_pending |= IMAN_IP; |
204b7793 | 2751 | writel(irq_pending, &xhci->ir_set->irq_pending); |
c21599a3 | 2752 | } |
bda53145 | 2753 | |
27a41a83 GKB |
2754 | if (xhci->xhc_state & XHCI_STATE_DYING || |
2755 | xhci->xhc_state & XHCI_STATE_HALTED) { | |
bda53145 SS |
2756 | xhci_dbg(xhci, "xHCI dying, ignoring interrupt. " |
2757 | "Shouldn't IRQs be disabled?\n"); | |
c06d68b8 SS |
2758 | /* Clear the event handler busy flag (RW1C); |
2759 | * the event ring should be empty. | |
bda53145 | 2760 | */ |
f7b2e403 | 2761 | temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); |
477632df SS |
2762 | xhci_write_64(xhci, temp_64 | ERST_EHB, |
2763 | &xhci->ir_set->erst_dequeue); | |
76a35293 FB |
2764 | ret = IRQ_HANDLED; |
2765 | goto out; | |
c06d68b8 SS |
2766 | } |
2767 | ||
2768 | event_ring_deq = xhci->event_ring->dequeue; | |
2769 | /* FIXME this should be a delayed service routine | |
2770 | * that clears the EHB. | |
2771 | */ | |
9dee9a21 | 2772 | while (xhci_handle_event(xhci) > 0) {} |
bda53145 | 2773 | |
f7b2e403 | 2774 | temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); |
c06d68b8 SS |
2775 | /* If necessary, update the HW's version of the event ring deq ptr. */ |
2776 | if (event_ring_deq != xhci->event_ring->dequeue) { | |
2777 | deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg, | |
2778 | xhci->event_ring->dequeue); | |
2779 | if (deq == 0) | |
2780 | xhci_warn(xhci, "WARN something wrong with SW event " | |
2781 | "ring dequeue ptr.\n"); | |
2782 | /* Update HC event ring dequeue pointer */ | |
2783 | temp_64 &= ERST_PTR_MASK; | |
2784 | temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK); | |
2785 | } | |
2786 | ||
2787 | /* Clear the event handler busy flag (RW1C); event ring is empty. */ | |
2788 | temp_64 |= ERST_EHB; | |
477632df | 2789 | xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue); |
76a35293 | 2790 | ret = IRQ_HANDLED; |
c06d68b8 | 2791 | |
76a35293 | 2792 | out: |
63aea0db | 2793 | spin_unlock_irqrestore(&xhci->lock, flags); |
9032cd52 | 2794 | |
76a35293 | 2795 | return ret; |
9032cd52 SS |
2796 | } |
2797 | ||
851ec164 | 2798 | irqreturn_t xhci_msi_irq(int irq, void *hcd) |
9032cd52 | 2799 | { |
968b822c | 2800 | return xhci_irq(hcd); |
9032cd52 | 2801 | } |
7f84eef0 | 2802 | |
d0e96f5a SS |
2803 | /**** Endpoint Ring Operations ****/ |
2804 | ||
7f84eef0 SS |
2805 | /* |
2806 | * Generic function for queueing a TRB on a ring. | |
2807 | * The caller must have checked to make sure there's room on the ring. | |
6cc30d85 SS |
2808 | * |
2809 | * @more_trbs_coming: Will you enqueue more TRBs before calling | |
2810 | * prepare_transfer()? | |
7f84eef0 SS |
2811 | */ |
2812 | static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring, | |
3b72fca0 | 2813 | bool more_trbs_coming, |
7f84eef0 SS |
2814 | u32 field1, u32 field2, u32 field3, u32 field4) |
2815 | { | |
2816 | struct xhci_generic_trb *trb; | |
2817 | ||
2818 | trb = &ring->enqueue->generic; | |
28ccd296 ME |
2819 | trb->field[0] = cpu_to_le32(field1); |
2820 | trb->field[1] = cpu_to_le32(field2); | |
2821 | trb->field[2] = cpu_to_le32(field3); | |
2822 | trb->field[3] = cpu_to_le32(field4); | |
a37c3f76 FB |
2823 | |
2824 | trace_xhci_queue_trb(ring, trb); | |
2825 | ||
3b72fca0 | 2826 | inc_enq(xhci, ring, more_trbs_coming); |
7f84eef0 SS |
2827 | } |
2828 | ||
d0e96f5a SS |
2829 | /* |
2830 | * Does various checks on the endpoint ring, and makes it ready to queue num_trbs. | |
2831 | * FIXME allocate segments if the ring is full. | |
2832 | */ | |
2833 | static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring, | |
3b72fca0 | 2834 | u32 ep_state, unsigned int num_trbs, gfp_t mem_flags) |
d0e96f5a | 2835 | { |
8dfec614 AX |
2836 | unsigned int num_trbs_needed; |
2837 | ||
d0e96f5a | 2838 | /* Make sure the endpoint has been added to xHC schedule */ |
d0e96f5a SS |
2839 | switch (ep_state) { |
2840 | case EP_STATE_DISABLED: | |
2841 | /* | |
2842 | * USB core changed config/interfaces without notifying us, | |
2843 | * or hardware is reporting the wrong state. | |
2844 | */ | |
2845 | xhci_warn(xhci, "WARN urb submitted to disabled ep\n"); | |
2846 | return -ENOENT; | |
d0e96f5a | 2847 | case EP_STATE_ERROR: |
c92bcfa7 | 2848 | xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n"); |
d0e96f5a SS |
2849 | /* FIXME event handling code for error needs to clear it */ |
2850 | /* XXX not sure if this should be -ENOENT or not */ | |
2851 | return -EINVAL; | |
c92bcfa7 SS |
2852 | case EP_STATE_HALTED: |
2853 | xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n"); | |
d0e96f5a SS |
2854 | case EP_STATE_STOPPED: |
2855 | case EP_STATE_RUNNING: | |
2856 | break; | |
2857 | default: | |
2858 | xhci_err(xhci, "ERROR unknown endpoint state for ep\n"); | |
2859 | /* | |
2860 | * FIXME issue Configure Endpoint command to try to get the HC | |
2861 | * back into a known state. | |
2862 | */ | |
2863 | return -EINVAL; | |
2864 | } | |
8dfec614 AX |
2865 | |
2866 | while (1) { | |
3d4b81ed SS |
2867 | if (room_on_ring(xhci, ep_ring, num_trbs)) |
2868 | break; | |
8dfec614 AX |
2869 | |
2870 | if (ep_ring == xhci->cmd_ring) { | |
2871 | xhci_err(xhci, "Do not support expand command ring\n"); | |
2872 | return -ENOMEM; | |
2873 | } | |
2874 | ||
68ffb011 XR |
2875 | xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion, |
2876 | "ERROR no room on ep ring, try ring expansion"); | |
8dfec614 AX |
2877 | num_trbs_needed = num_trbs - ep_ring->num_trbs_free; |
2878 | if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed, | |
2879 | mem_flags)) { | |
2880 | xhci_err(xhci, "Ring expansion failed\n"); | |
2881 | return -ENOMEM; | |
2882 | } | |
261fa12b | 2883 | } |
6c12db90 | 2884 | |
d0c77d84 MN |
2885 | while (trb_is_link(ep_ring->enqueue)) { |
2886 | /* If we're not dealing with 0.95 hardware or isoc rings | |
2887 | * on AMD 0.96 host, clear the chain bit. | |
2888 | */ | |
2889 | if (!xhci_link_trb_quirk(xhci) && | |
2890 | !(ep_ring->type == TYPE_ISOC && | |
2891 | (xhci->quirks & XHCI_AMD_0x96_HOST))) | |
2892 | ep_ring->enqueue->link.control &= | |
2893 | cpu_to_le32(~TRB_CHAIN); | |
2894 | else | |
2895 | ep_ring->enqueue->link.control |= | |
2896 | cpu_to_le32(TRB_CHAIN); | |
6c12db90 | 2897 | |
d0c77d84 MN |
2898 | wmb(); |
2899 | ep_ring->enqueue->link.control ^= cpu_to_le32(TRB_CYCLE); | |
6c12db90 | 2900 | |
d0c77d84 MN |
2901 | /* Toggle the cycle bit after the last ring segment. */ |
2902 | if (link_trb_toggles_cycle(ep_ring->enqueue)) | |
2903 | ep_ring->cycle_state ^= 1; | |
6c12db90 | 2904 | |
d0c77d84 MN |
2905 | ep_ring->enq_seg = ep_ring->enq_seg->next; |
2906 | ep_ring->enqueue = ep_ring->enq_seg->trbs; | |
6c12db90 | 2907 | } |
d0e96f5a SS |
2908 | return 0; |
2909 | } | |
2910 | ||
23e3be11 | 2911 | static int prepare_transfer(struct xhci_hcd *xhci, |
d0e96f5a SS |
2912 | struct xhci_virt_device *xdev, |
2913 | unsigned int ep_index, | |
e9df17eb | 2914 | unsigned int stream_id, |
d0e96f5a SS |
2915 | unsigned int num_trbs, |
2916 | struct urb *urb, | |
8e51adcc | 2917 | unsigned int td_index, |
d0e96f5a SS |
2918 | gfp_t mem_flags) |
2919 | { | |
2920 | int ret; | |
8e51adcc AX |
2921 | struct urb_priv *urb_priv; |
2922 | struct xhci_td *td; | |
e9df17eb | 2923 | struct xhci_ring *ep_ring; |
d115b048 | 2924 | struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
e9df17eb SS |
2925 | |
2926 | ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id); | |
2927 | if (!ep_ring) { | |
2928 | xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n", | |
2929 | stream_id); | |
2930 | return -EINVAL; | |
2931 | } | |
2932 | ||
5071e6b2 | 2933 | ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx), |
3b72fca0 | 2934 | num_trbs, mem_flags); |
d0e96f5a SS |
2935 | if (ret) |
2936 | return ret; | |
d0e96f5a | 2937 | |
8e51adcc | 2938 | urb_priv = urb->hcpriv; |
7e64b037 | 2939 | td = &urb_priv->td[td_index]; |
8e51adcc AX |
2940 | |
2941 | INIT_LIST_HEAD(&td->td_list); | |
2942 | INIT_LIST_HEAD(&td->cancelled_td_list); | |
2943 | ||
2944 | if (td_index == 0) { | |
214f76f7 | 2945 | ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb); |
d13565c1 | 2946 | if (unlikely(ret)) |
8e51adcc | 2947 | return ret; |
d0e96f5a SS |
2948 | } |
2949 | ||
8e51adcc | 2950 | td->urb = urb; |
d0e96f5a | 2951 | /* Add this TD to the tail of the endpoint ring's TD list */ |
8e51adcc AX |
2952 | list_add_tail(&td->td_list, &ep_ring->td_list); |
2953 | td->start_seg = ep_ring->enq_seg; | |
2954 | td->first_trb = ep_ring->enqueue; | |
2955 | ||
d0e96f5a SS |
2956 | return 0; |
2957 | } | |
2958 | ||
67d2ea9f | 2959 | unsigned int count_trbs(u64 addr, u64 len) |
d2510342 AI |
2960 | { |
2961 | unsigned int num_trbs; | |
2962 | ||
2963 | num_trbs = DIV_ROUND_UP(len + (addr & (TRB_MAX_BUFF_SIZE - 1)), | |
2964 | TRB_MAX_BUFF_SIZE); | |
2965 | if (num_trbs == 0) | |
2966 | num_trbs++; | |
2967 | ||
2968 | return num_trbs; | |
2969 | } | |
2970 | ||
2971 | static inline unsigned int count_trbs_needed(struct urb *urb) | |
2972 | { | |
2973 | return count_trbs(urb->transfer_dma, urb->transfer_buffer_length); | |
2974 | } | |
2975 | ||
2976 | static unsigned int count_sg_trbs_needed(struct urb *urb) | |
8a96c052 | 2977 | { |
8a96c052 | 2978 | struct scatterlist *sg; |
d2510342 | 2979 | unsigned int i, len, full_len, num_trbs = 0; |
8a96c052 | 2980 | |
d2510342 | 2981 | full_len = urb->transfer_buffer_length; |
8a96c052 | 2982 | |
d2510342 AI |
2983 | for_each_sg(urb->sg, sg, urb->num_mapped_sgs, i) { |
2984 | len = sg_dma_len(sg); | |
2985 | num_trbs += count_trbs(sg_dma_address(sg), len); | |
2986 | len = min_t(unsigned int, len, full_len); | |
2987 | full_len -= len; | |
2988 | if (full_len == 0) | |
8a96c052 SS |
2989 | break; |
2990 | } | |
d2510342 | 2991 | |
8a96c052 SS |
2992 | return num_trbs; |
2993 | } | |
2994 | ||
d2510342 AI |
2995 | static unsigned int count_isoc_trbs_needed(struct urb *urb, int i) |
2996 | { | |
2997 | u64 addr, len; | |
2998 | ||
2999 | addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset); | |
3000 | len = urb->iso_frame_desc[i].length; | |
3001 | ||
3002 | return count_trbs(addr, len); | |
3003 | } | |
3004 | ||
3005 | static void check_trb_math(struct urb *urb, int running_total) | |
8a96c052 | 3006 | { |
d2510342 | 3007 | if (unlikely(running_total != urb->transfer_buffer_length)) |
a2490187 | 3008 | dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, " |
8a96c052 SS |
3009 | "queued %#x (%d), asked for %#x (%d)\n", |
3010 | __func__, | |
3011 | urb->ep->desc.bEndpointAddress, | |
3012 | running_total, running_total, | |
3013 | urb->transfer_buffer_length, | |
3014 | urb->transfer_buffer_length); | |
3015 | } | |
3016 | ||
23e3be11 | 3017 | static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id, |
e9df17eb | 3018 | unsigned int ep_index, unsigned int stream_id, int start_cycle, |
e1eab2e0 | 3019 | struct xhci_generic_trb *start_trb) |
8a96c052 | 3020 | { |
8a96c052 SS |
3021 | /* |
3022 | * Pass all the TRBs to the hardware at once and make sure this write | |
3023 | * isn't reordered. | |
3024 | */ | |
3025 | wmb(); | |
50f7b52a | 3026 | if (start_cycle) |
28ccd296 | 3027 | start_trb->field[3] |= cpu_to_le32(start_cycle); |
50f7b52a | 3028 | else |
28ccd296 | 3029 | start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE); |
be88fe4f | 3030 | xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id); |
8a96c052 SS |
3031 | } |
3032 | ||
78140156 AI |
3033 | static void check_interval(struct xhci_hcd *xhci, struct urb *urb, |
3034 | struct xhci_ep_ctx *ep_ctx) | |
624defa1 | 3035 | { |
624defa1 SS |
3036 | int xhci_interval; |
3037 | int ep_interval; | |
3038 | ||
28ccd296 | 3039 | xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info)); |
624defa1 | 3040 | ep_interval = urb->interval; |
78140156 | 3041 | |
624defa1 SS |
3042 | /* Convert to microframes */ |
3043 | if (urb->dev->speed == USB_SPEED_LOW || | |
3044 | urb->dev->speed == USB_SPEED_FULL) | |
3045 | ep_interval *= 8; | |
78140156 | 3046 | |
624defa1 SS |
3047 | /* FIXME change this to a warning and a suggestion to use the new API |
3048 | * to set the polling interval (once the API is added). | |
3049 | */ | |
3050 | if (xhci_interval != ep_interval) { | |
0730d52a DK |
3051 | dev_dbg_ratelimited(&urb->dev->dev, |
3052 | "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n", | |
3053 | ep_interval, ep_interval == 1 ? "" : "s", | |
3054 | xhci_interval, xhci_interval == 1 ? "" : "s"); | |
624defa1 SS |
3055 | urb->interval = xhci_interval; |
3056 | /* Convert back to frames for LS/FS devices */ | |
3057 | if (urb->dev->speed == USB_SPEED_LOW || | |
3058 | urb->dev->speed == USB_SPEED_FULL) | |
3059 | urb->interval /= 8; | |
3060 | } | |
78140156 AI |
3061 | } |
3062 | ||
3063 | /* | |
3064 | * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt | |
3065 | * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD | |
3066 | * (comprised of sg list entries) can take several service intervals to | |
3067 | * transmit. | |
3068 | */ | |
3069 | int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |
3070 | struct urb *urb, int slot_id, unsigned int ep_index) | |
3071 | { | |
3072 | struct xhci_ep_ctx *ep_ctx; | |
3073 | ||
3074 | ep_ctx = xhci_get_ep_ctx(xhci, xhci->devs[slot_id]->out_ctx, ep_index); | |
3075 | check_interval(xhci, urb, ep_ctx); | |
3076 | ||
3fc8206d | 3077 | return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index); |
624defa1 SS |
3078 | } |
3079 | ||
4da6e6f2 | 3080 | /* |
4525c0a1 SS |
3081 | * For xHCI 1.0 host controllers, TD size is the number of max packet sized |
3082 | * packets remaining in the TD (*not* including this TRB). | |
4da6e6f2 SS |
3083 | * |
3084 | * Total TD packet count = total_packet_count = | |
4525c0a1 | 3085 | * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize) |
4da6e6f2 SS |
3086 | * |
3087 | * Packets transferred up to and including this TRB = packets_transferred = | |
3088 | * rounddown(total bytes transferred including this TRB / wMaxPacketSize) | |
3089 | * | |
3090 | * TD size = total_packet_count - packets_transferred | |
3091 | * | |
c840d6ce MN |
3092 | * For xHCI 0.96 and older, TD size field should be the remaining bytes |
3093 | * including this TRB, right shifted by 10 | |
3094 | * | |
3095 | * For all hosts it must fit in bits 21:17, so it can't be bigger than 31. | |
3096 | * This is taken care of in the TRB_TD_SIZE() macro | |
3097 | * | |
4525c0a1 | 3098 | * The last TRB in a TD must have the TD size set to zero. |
4da6e6f2 | 3099 | */ |
c840d6ce MN |
3100 | static u32 xhci_td_remainder(struct xhci_hcd *xhci, int transferred, |
3101 | int trb_buff_len, unsigned int td_total_len, | |
124c3937 | 3102 | struct urb *urb, bool more_trbs_coming) |
4da6e6f2 | 3103 | { |
c840d6ce MN |
3104 | u32 maxp, total_packet_count; |
3105 | ||
72b663a9 | 3106 | /* MTK xHCI 0.96 contains some features from 1.0 */ |
0cbd4b34 | 3107 | if (xhci->hci_version < 0x100 && !(xhci->quirks & XHCI_MTK_HOST)) |
c840d6ce MN |
3108 | return ((td_total_len - transferred) >> 10); |
3109 | ||
48df4a6f | 3110 | /* One TRB with a zero-length data packet. */ |
124c3937 | 3111 | if (!more_trbs_coming || (transferred == 0 && trb_buff_len == 0) || |
c840d6ce | 3112 | trb_buff_len == td_total_len) |
48df4a6f SS |
3113 | return 0; |
3114 | ||
72b663a9 CY |
3115 | /* for MTK xHCI 0.96, TD size include this TRB, but not in 1.x */ |
3116 | if ((xhci->quirks & XHCI_MTK_HOST) && (xhci->hci_version < 0x100)) | |
0cbd4b34 CY |
3117 | trb_buff_len = 0; |
3118 | ||
734d3ddd | 3119 | maxp = usb_endpoint_maxp(&urb->ep->desc); |
0cbd4b34 CY |
3120 | total_packet_count = DIV_ROUND_UP(td_total_len, maxp); |
3121 | ||
c840d6ce MN |
3122 | /* Queueing functions don't count the current TRB into transferred */ |
3123 | return (total_packet_count - ((transferred + trb_buff_len) / maxp)); | |
4da6e6f2 SS |
3124 | } |
3125 | ||
f9c589e1 | 3126 | |
474ed23a | 3127 | static int xhci_align_td(struct xhci_hcd *xhci, struct urb *urb, u32 enqd_len, |
f9c589e1 | 3128 | u32 *trb_buff_len, struct xhci_segment *seg) |
474ed23a | 3129 | { |
f9c589e1 | 3130 | struct device *dev = xhci_to_hcd(xhci)->self.controller; |
474ed23a MN |
3131 | unsigned int unalign; |
3132 | unsigned int max_pkt; | |
f9c589e1 | 3133 | u32 new_buff_len; |
597c56e3 | 3134 | size_t len; |
474ed23a | 3135 | |
734d3ddd | 3136 | max_pkt = usb_endpoint_maxp(&urb->ep->desc); |
474ed23a MN |
3137 | unalign = (enqd_len + *trb_buff_len) % max_pkt; |
3138 | ||
3139 | /* we got lucky, last normal TRB data on segment is packet aligned */ | |
3140 | if (unalign == 0) | |
3141 | return 0; | |
3142 | ||
f9c589e1 MN |
3143 | xhci_dbg(xhci, "Unaligned %d bytes, buff len %d\n", |
3144 | unalign, *trb_buff_len); | |
3145 | ||
474ed23a MN |
3146 | /* is the last nornal TRB alignable by splitting it */ |
3147 | if (*trb_buff_len > unalign) { | |
3148 | *trb_buff_len -= unalign; | |
f9c589e1 | 3149 | xhci_dbg(xhci, "split align, new buff len %d\n", *trb_buff_len); |
474ed23a MN |
3150 | return 0; |
3151 | } | |
f9c589e1 MN |
3152 | |
3153 | /* | |
3154 | * We want enqd_len + trb_buff_len to sum up to a number aligned to | |
3155 | * number which is divisible by the endpoint's wMaxPacketSize. IOW: | |
3156 | * (size of currently enqueued TRBs + remainder) % wMaxPacketSize == 0. | |
3157 | */ | |
3158 | new_buff_len = max_pkt - (enqd_len % max_pkt); | |
3159 | ||
3160 | if (new_buff_len > (urb->transfer_buffer_length - enqd_len)) | |
3161 | new_buff_len = (urb->transfer_buffer_length - enqd_len); | |
3162 | ||
3163 | /* create a max max_pkt sized bounce buffer pointed to by last trb */ | |
3164 | if (usb_urb_dir_out(urb)) { | |
597c56e3 | 3165 | len = sg_pcopy_to_buffer(urb->sg, urb->num_sgs, |
f9c589e1 | 3166 | seg->bounce_buf, new_buff_len, enqd_len); |
597c56e3 HL |
3167 | if (len != seg->bounce_len) |
3168 | xhci_warn(xhci, | |
3169 | "WARN Wrong bounce buffer write length: %ld != %d\n", | |
3170 | len, seg->bounce_len); | |
f9c589e1 MN |
3171 | seg->bounce_dma = dma_map_single(dev, seg->bounce_buf, |
3172 | max_pkt, DMA_TO_DEVICE); | |
3173 | } else { | |
3174 | seg->bounce_dma = dma_map_single(dev, seg->bounce_buf, | |
3175 | max_pkt, DMA_FROM_DEVICE); | |
3176 | } | |
3177 | ||
3178 | if (dma_mapping_error(dev, seg->bounce_dma)) { | |
3179 | /* try without aligning. Some host controllers survive */ | |
3180 | xhci_warn(xhci, "Failed mapping bounce buffer, not aligning\n"); | |
3181 | return 0; | |
3182 | } | |
3183 | *trb_buff_len = new_buff_len; | |
3184 | seg->bounce_len = new_buff_len; | |
3185 | seg->bounce_offs = enqd_len; | |
3186 | ||
3187 | xhci_dbg(xhci, "Bounce align, new buff len %d\n", *trb_buff_len); | |
3188 | ||
474ed23a MN |
3189 | return 1; |
3190 | } | |
3191 | ||
d2510342 AI |
3192 | /* This is very similar to what ehci-q.c qtd_fill() does */ |
3193 | int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |
8a96c052 SS |
3194 | struct urb *urb, int slot_id, unsigned int ep_index) |
3195 | { | |
5a5a0b1a | 3196 | struct xhci_ring *ring; |
8e51adcc | 3197 | struct urb_priv *urb_priv; |
8a96c052 | 3198 | struct xhci_td *td; |
d2510342 AI |
3199 | struct xhci_generic_trb *start_trb; |
3200 | struct scatterlist *sg = NULL; | |
5a83f04a MN |
3201 | bool more_trbs_coming = true; |
3202 | bool need_zero_pkt = false; | |
86065c27 MN |
3203 | bool first_trb = true; |
3204 | unsigned int num_trbs; | |
d2510342 | 3205 | unsigned int start_cycle, num_sgs = 0; |
86065c27 | 3206 | unsigned int enqd_len, block_len, trb_buff_len, full_len; |
f9c589e1 | 3207 | int sent_len, ret; |
d2510342 | 3208 | u32 field, length_field, remainder; |
f9c589e1 | 3209 | u64 addr, send_addr; |
8a96c052 | 3210 | |
5a5a0b1a MN |
3211 | ring = xhci_urb_to_transfer_ring(xhci, urb); |
3212 | if (!ring) | |
e9df17eb SS |
3213 | return -EINVAL; |
3214 | ||
86065c27 | 3215 | full_len = urb->transfer_buffer_length; |
d2510342 AI |
3216 | /* If we have scatter/gather list, we use it. */ |
3217 | if (urb->num_sgs) { | |
3218 | num_sgs = urb->num_mapped_sgs; | |
3219 | sg = urb->sg; | |
86065c27 MN |
3220 | addr = (u64) sg_dma_address(sg); |
3221 | block_len = sg_dma_len(sg); | |
d2510342 | 3222 | num_trbs = count_sg_trbs_needed(urb); |
86065c27 | 3223 | } else { |
d2510342 | 3224 | num_trbs = count_trbs_needed(urb); |
86065c27 MN |
3225 | addr = (u64) urb->transfer_dma; |
3226 | block_len = full_len; | |
3227 | } | |
4758dcd1 | 3228 | ret = prepare_transfer(xhci, xhci->devs[slot_id], |
e9df17eb | 3229 | ep_index, urb->stream_id, |
3b72fca0 | 3230 | num_trbs, urb, 0, mem_flags); |
d2510342 | 3231 | if (unlikely(ret < 0)) |
4758dcd1 | 3232 | return ret; |
8e51adcc AX |
3233 | |
3234 | urb_priv = urb->hcpriv; | |
4758dcd1 RA |
3235 | |
3236 | /* Deal with URB_ZERO_PACKET - need one more td/trb */ | |
9ef7fbbb | 3237 | if (urb->transfer_flags & URB_ZERO_PACKET && urb_priv->num_tds > 1) |
5a83f04a | 3238 | need_zero_pkt = true; |
4758dcd1 | 3239 | |
7e64b037 | 3240 | td = &urb_priv->td[0]; |
8e51adcc | 3241 | |
8a96c052 SS |
3242 | /* |
3243 | * Don't give the first TRB to the hardware (by toggling the cycle bit) | |
3244 | * until we've finished creating all the other TRBs. The ring's cycle | |
3245 | * state may change as we enqueue the other TRBs, so save it too. | |
3246 | */ | |
5a5a0b1a MN |
3247 | start_trb = &ring->enqueue->generic; |
3248 | start_cycle = ring->cycle_state; | |
f9c589e1 | 3249 | send_addr = addr; |
8a96c052 | 3250 | |
d2510342 | 3251 | /* Queue the TRBs, even if they are zero-length */ |
0d2daade AB |
3252 | for (enqd_len = 0; first_trb || enqd_len < full_len; |
3253 | enqd_len += trb_buff_len) { | |
d2510342 | 3254 | field = TRB_TYPE(TRB_NORMAL); |
af8b9e63 | 3255 | |
86065c27 MN |
3256 | /* TRB buffer should not cross 64KB boundaries */ |
3257 | trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr); | |
3258 | trb_buff_len = min_t(unsigned int, trb_buff_len, block_len); | |
8a96c052 | 3259 | |
86065c27 MN |
3260 | if (enqd_len + trb_buff_len > full_len) |
3261 | trb_buff_len = full_len - enqd_len; | |
b10de142 SS |
3262 | |
3263 | /* Don't change the cycle bit of the first TRB until later */ | |
86065c27 MN |
3264 | if (first_trb) { |
3265 | first_trb = false; | |
50f7b52a | 3266 | if (start_cycle == 0) |
d2510342 | 3267 | field |= TRB_CYCLE; |
50f7b52a | 3268 | } else |
5a5a0b1a | 3269 | field |= ring->cycle_state; |
b10de142 SS |
3270 | |
3271 | /* Chain all the TRBs together; clear the chain bit in the last | |
3272 | * TRB to indicate it's the last TRB in the chain. | |
3273 | */ | |
86065c27 | 3274 | if (enqd_len + trb_buff_len < full_len) { |
b10de142 | 3275 | field |= TRB_CHAIN; |
2d98ef40 | 3276 | if (trb_is_link(ring->enqueue + 1)) { |
474ed23a | 3277 | if (xhci_align_td(xhci, urb, enqd_len, |
f9c589e1 MN |
3278 | &trb_buff_len, |
3279 | ring->enq_seg)) { | |
3280 | send_addr = ring->enq_seg->bounce_dma; | |
3281 | /* assuming TD won't span 2 segs */ | |
3282 | td->bounce_seg = ring->enq_seg; | |
3283 | } | |
474ed23a | 3284 | } |
f9c589e1 MN |
3285 | } |
3286 | if (enqd_len + trb_buff_len >= full_len) { | |
3287 | field &= ~TRB_CHAIN; | |
4758dcd1 | 3288 | field |= TRB_IOC; |
124c3937 | 3289 | more_trbs_coming = false; |
5a83f04a | 3290 | td->last_trb = ring->enqueue; |
33e39350 NSJ |
3291 | |
3292 | if (xhci_urb_suitable_for_idt(urb)) { | |
3293 | memcpy(&send_addr, urb->transfer_buffer, | |
3294 | trb_buff_len); | |
3295 | field |= TRB_IDT; | |
3296 | } | |
b10de142 | 3297 | } |
af8b9e63 SS |
3298 | |
3299 | /* Only set interrupt on short packet for IN endpoints */ | |
3300 | if (usb_urb_dir_in(urb)) | |
3301 | field |= TRB_ISP; | |
3302 | ||
4da6e6f2 | 3303 | /* Set the TRB length, TD size, and interrupter fields. */ |
86065c27 MN |
3304 | remainder = xhci_td_remainder(xhci, enqd_len, trb_buff_len, |
3305 | full_len, urb, more_trbs_coming); | |
3306 | ||
f9dc68fe | 3307 | length_field = TRB_LEN(trb_buff_len) | |
c840d6ce | 3308 | TRB_TD_SIZE(remainder) | |
f9dc68fe | 3309 | TRB_INTR_TARGET(0); |
4da6e6f2 | 3310 | |
124c3937 | 3311 | queue_trb(xhci, ring, more_trbs_coming | need_zero_pkt, |
f9c589e1 MN |
3312 | lower_32_bits(send_addr), |
3313 | upper_32_bits(send_addr), | |
f9dc68fe | 3314 | length_field, |
d2510342 | 3315 | field); |
b10de142 | 3316 | |
b10de142 | 3317 | addr += trb_buff_len; |
f9c589e1 | 3318 | sent_len = trb_buff_len; |
d2510342 | 3319 | |
f9c589e1 | 3320 | while (sg && sent_len >= block_len) { |
86065c27 MN |
3321 | /* New sg entry */ |
3322 | --num_sgs; | |
f9c589e1 | 3323 | sent_len -= block_len; |
86065c27 | 3324 | if (num_sgs != 0) { |
d2510342 | 3325 | sg = sg_next(sg); |
86065c27 MN |
3326 | block_len = sg_dma_len(sg); |
3327 | addr = (u64) sg_dma_address(sg); | |
f9c589e1 | 3328 | addr += sent_len; |
d2510342 AI |
3329 | } |
3330 | } | |
f9c589e1 MN |
3331 | block_len -= sent_len; |
3332 | send_addr = addr; | |
d2510342 | 3333 | } |
b10de142 | 3334 | |
5a83f04a MN |
3335 | if (need_zero_pkt) { |
3336 | ret = prepare_transfer(xhci, xhci->devs[slot_id], | |
3337 | ep_index, urb->stream_id, | |
3338 | 1, urb, 1, mem_flags); | |
7e64b037 | 3339 | urb_priv->td[1].last_trb = ring->enqueue; |
5a83f04a MN |
3340 | field = TRB_TYPE(TRB_NORMAL) | ring->cycle_state | TRB_IOC; |
3341 | queue_trb(xhci, ring, 0, 0, 0, TRB_INTR_TARGET(0), field); | |
3342 | } | |
3343 | ||
86065c27 | 3344 | check_trb_math(urb, enqd_len); |
e9df17eb | 3345 | giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, |
e1eab2e0 | 3346 | start_cycle, start_trb); |
b10de142 SS |
3347 | return 0; |
3348 | } | |
3349 | ||
d0e96f5a | 3350 | /* Caller must have locked xhci->lock */ |
23e3be11 | 3351 | int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, |
d0e96f5a SS |
3352 | struct urb *urb, int slot_id, unsigned int ep_index) |
3353 | { | |
3354 | struct xhci_ring *ep_ring; | |
3355 | int num_trbs; | |
3356 | int ret; | |
3357 | struct usb_ctrlrequest *setup; | |
3358 | struct xhci_generic_trb *start_trb; | |
3359 | int start_cycle; | |
fb79a6da | 3360 | u32 field; |
8e51adcc | 3361 | struct urb_priv *urb_priv; |
d0e96f5a SS |
3362 | struct xhci_td *td; |
3363 | ||
e9df17eb SS |
3364 | ep_ring = xhci_urb_to_transfer_ring(xhci, urb); |
3365 | if (!ep_ring) | |
3366 | return -EINVAL; | |
d0e96f5a SS |
3367 | |
3368 | /* | |
3369 | * Need to copy setup packet into setup TRB, so we can't use the setup | |
3370 | * DMA address. | |
3371 | */ | |
3372 | if (!urb->setup_packet) | |
3373 | return -EINVAL; | |
3374 | ||
d0e96f5a SS |
3375 | /* 1 TRB for setup, 1 for status */ |
3376 | num_trbs = 2; | |
3377 | /* | |
3378 | * Don't need to check if we need additional event data and normal TRBs, | |
3379 | * since data in control transfers will never get bigger than 16MB | |
3380 | * XXX: can we get a buffer that crosses 64KB boundaries? | |
3381 | */ | |
3382 | if (urb->transfer_buffer_length > 0) | |
3383 | num_trbs++; | |
e9df17eb SS |
3384 | ret = prepare_transfer(xhci, xhci->devs[slot_id], |
3385 | ep_index, urb->stream_id, | |
3b72fca0 | 3386 | num_trbs, urb, 0, mem_flags); |
d0e96f5a SS |
3387 | if (ret < 0) |
3388 | return ret; | |
3389 | ||
8e51adcc | 3390 | urb_priv = urb->hcpriv; |
7e64b037 | 3391 | td = &urb_priv->td[0]; |
8e51adcc | 3392 | |
d0e96f5a SS |
3393 | /* |
3394 | * Don't give the first TRB to the hardware (by toggling the cycle bit) | |
3395 | * until we've finished creating all the other TRBs. The ring's cycle | |
3396 | * state may change as we enqueue the other TRBs, so save it too. | |
3397 | */ | |
3398 | start_trb = &ep_ring->enqueue->generic; | |
3399 | start_cycle = ep_ring->cycle_state; | |
3400 | ||
3401 | /* Queue setup TRB - see section 6.4.1.2.1 */ | |
3402 | /* FIXME better way to translate setup_packet into two u32 fields? */ | |
3403 | setup = (struct usb_ctrlrequest *) urb->setup_packet; | |
50f7b52a AX |
3404 | field = 0; |
3405 | field |= TRB_IDT | TRB_TYPE(TRB_SETUP); | |
3406 | if (start_cycle == 0) | |
3407 | field |= 0x1; | |
b83cdc8f | 3408 | |
dca77945 | 3409 | /* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */ |
0cbd4b34 | 3410 | if ((xhci->hci_version >= 0x100) || (xhci->quirks & XHCI_MTK_HOST)) { |
b83cdc8f AX |
3411 | if (urb->transfer_buffer_length > 0) { |
3412 | if (setup->bRequestType & USB_DIR_IN) | |
3413 | field |= TRB_TX_TYPE(TRB_DATA_IN); | |
3414 | else | |
3415 | field |= TRB_TX_TYPE(TRB_DATA_OUT); | |
3416 | } | |
3417 | } | |
3418 | ||
3b72fca0 | 3419 | queue_trb(xhci, ep_ring, true, |
28ccd296 ME |
3420 | setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16, |
3421 | le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16, | |
3422 | TRB_LEN(8) | TRB_INTR_TARGET(0), | |
3423 | /* Immediate data in pointer */ | |
3424 | field); | |
d0e96f5a SS |
3425 | |
3426 | /* If there's data, queue data TRBs */ | |
af8b9e63 SS |
3427 | /* Only set interrupt on short packet for IN endpoints */ |
3428 | if (usb_urb_dir_in(urb)) | |
3429 | field = TRB_ISP | TRB_TYPE(TRB_DATA); | |
3430 | else | |
3431 | field = TRB_TYPE(TRB_DATA); | |
3432 | ||
d0e96f5a | 3433 | if (urb->transfer_buffer_length > 0) { |
fb79a6da LB |
3434 | u32 length_field, remainder; |
3435 | ||
33e39350 NSJ |
3436 | if (xhci_urb_suitable_for_idt(urb)) { |
3437 | memcpy(&urb->transfer_dma, urb->transfer_buffer, | |
3438 | urb->transfer_buffer_length); | |
3439 | field |= TRB_IDT; | |
3440 | } | |
3441 | ||
fb79a6da LB |
3442 | remainder = xhci_td_remainder(xhci, 0, |
3443 | urb->transfer_buffer_length, | |
3444 | urb->transfer_buffer_length, | |
3445 | urb, 1); | |
3446 | length_field = TRB_LEN(urb->transfer_buffer_length) | | |
3447 | TRB_TD_SIZE(remainder) | | |
3448 | TRB_INTR_TARGET(0); | |
d0e96f5a SS |
3449 | if (setup->bRequestType & USB_DIR_IN) |
3450 | field |= TRB_DIR_IN; | |
3b72fca0 | 3451 | queue_trb(xhci, ep_ring, true, |
d0e96f5a SS |
3452 | lower_32_bits(urb->transfer_dma), |
3453 | upper_32_bits(urb->transfer_dma), | |
f9dc68fe | 3454 | length_field, |
af8b9e63 | 3455 | field | ep_ring->cycle_state); |
d0e96f5a SS |
3456 | } |
3457 | ||
3458 | /* Save the DMA address of the last TRB in the TD */ | |
3459 | td->last_trb = ep_ring->enqueue; | |
3460 | ||
3461 | /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */ | |
3462 | /* If the device sent data, the status stage is an OUT transfer */ | |
3463 | if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN) | |
3464 | field = 0; | |
3465 | else | |
3466 | field = TRB_DIR_IN; | |
3b72fca0 | 3467 | queue_trb(xhci, ep_ring, false, |
d0e96f5a SS |
3468 | 0, |
3469 | 0, | |
3470 | TRB_INTR_TARGET(0), | |
3471 | /* Event on completion */ | |
3472 | field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state); | |
3473 | ||
e9df17eb | 3474 | giveback_first_trb(xhci, slot_id, ep_index, 0, |
e1eab2e0 | 3475 | start_cycle, start_trb); |
d0e96f5a SS |
3476 | return 0; |
3477 | } | |
3478 | ||
5cd43e33 SS |
3479 | /* |
3480 | * The transfer burst count field of the isochronous TRB defines the number of | |
3481 | * bursts that are required to move all packets in this TD. Only SuperSpeed | |
3482 | * devices can burst up to bMaxBurst number of packets per service interval. | |
3483 | * This field is zero based, meaning a value of zero in the field means one | |
3484 | * burst. Basically, for everything but SuperSpeed devices, this field will be | |
3485 | * zero. Only xHCI 1.0 host controllers support this field. | |
3486 | */ | |
3487 | static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci, | |
5cd43e33 SS |
3488 | struct urb *urb, unsigned int total_packet_count) |
3489 | { | |
3490 | unsigned int max_burst; | |
3491 | ||
09c352ed | 3492 | if (xhci->hci_version < 0x100 || urb->dev->speed < USB_SPEED_SUPER) |
5cd43e33 SS |
3493 | return 0; |
3494 | ||
3495 | max_burst = urb->ep->ss_ep_comp.bMaxBurst; | |
3213b151 | 3496 | return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1; |
5cd43e33 SS |
3497 | } |
3498 | ||
b61d378f SS |
3499 | /* |
3500 | * Returns the number of packets in the last "burst" of packets. This field is | |
3501 | * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so | |
3502 | * the last burst packet count is equal to the total number of packets in the | |
3503 | * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst | |
3504 | * must contain (bMaxBurst + 1) number of packets, but the last burst can | |
3505 | * contain 1 to (bMaxBurst + 1) packets. | |
3506 | */ | |
3507 | static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci, | |
b61d378f SS |
3508 | struct urb *urb, unsigned int total_packet_count) |
3509 | { | |
3510 | unsigned int max_burst; | |
3511 | unsigned int residue; | |
3512 | ||
3513 | if (xhci->hci_version < 0x100) | |
3514 | return 0; | |
3515 | ||
09c352ed | 3516 | if (urb->dev->speed >= USB_SPEED_SUPER) { |
b61d378f SS |
3517 | /* bMaxBurst is zero based: 0 means 1 packet per burst */ |
3518 | max_burst = urb->ep->ss_ep_comp.bMaxBurst; | |
3519 | residue = total_packet_count % (max_burst + 1); | |
3520 | /* If residue is zero, the last burst contains (max_burst + 1) | |
3521 | * number of packets, but the TLBPC field is zero-based. | |
3522 | */ | |
3523 | if (residue == 0) | |
3524 | return max_burst; | |
3525 | return residue - 1; | |
b61d378f | 3526 | } |
09c352ed MN |
3527 | if (total_packet_count == 0) |
3528 | return 0; | |
3529 | return total_packet_count - 1; | |
b61d378f SS |
3530 | } |
3531 | ||
79b8094f LB |
3532 | /* |
3533 | * Calculates Frame ID field of the isochronous TRB identifies the | |
3534 | * target frame that the Interval associated with this Isochronous | |
3535 | * Transfer Descriptor will start on. Refer to 4.11.2.5 in 1.1 spec. | |
3536 | * | |
3537 | * Returns actual frame id on success, negative value on error. | |
3538 | */ | |
3539 | static int xhci_get_isoc_frame_id(struct xhci_hcd *xhci, | |
3540 | struct urb *urb, int index) | |
3541 | { | |
3542 | int start_frame, ist, ret = 0; | |
3543 | int start_frame_id, end_frame_id, current_frame_id; | |
3544 | ||
3545 | if (urb->dev->speed == USB_SPEED_LOW || | |
3546 | urb->dev->speed == USB_SPEED_FULL) | |
3547 | start_frame = urb->start_frame + index * urb->interval; | |
3548 | else | |
3549 | start_frame = (urb->start_frame + index * urb->interval) >> 3; | |
3550 | ||
3551 | /* Isochronous Scheduling Threshold (IST, bits 0~3 in HCSPARAMS2): | |
3552 | * | |
3553 | * If bit [3] of IST is cleared to '0', software can add a TRB no | |
3554 | * later than IST[2:0] Microframes before that TRB is scheduled to | |
3555 | * be executed. | |
3556 | * If bit [3] of IST is set to '1', software can add a TRB no later | |
3557 | * than IST[2:0] Frames before that TRB is scheduled to be executed. | |
3558 | */ | |
3559 | ist = HCS_IST(xhci->hcs_params2) & 0x7; | |
3560 | if (HCS_IST(xhci->hcs_params2) & (1 << 3)) | |
3561 | ist <<= 3; | |
3562 | ||
3563 | /* Software shall not schedule an Isoch TD with a Frame ID value that | |
3564 | * is less than the Start Frame ID or greater than the End Frame ID, | |
3565 | * where: | |
3566 | * | |
3567 | * End Frame ID = (Current MFINDEX register value + 895 ms.) MOD 2048 | |
3568 | * Start Frame ID = (Current MFINDEX register value + IST + 1) MOD 2048 | |
3569 | * | |
3570 | * Both the End Frame ID and Start Frame ID values are calculated | |
3571 | * in microframes. When software determines the valid Frame ID value; | |
3572 | * The End Frame ID value should be rounded down to the nearest Frame | |
3573 | * boundary, and the Start Frame ID value should be rounded up to the | |
3574 | * nearest Frame boundary. | |
3575 | */ | |
3576 | current_frame_id = readl(&xhci->run_regs->microframe_index); | |
3577 | start_frame_id = roundup(current_frame_id + ist + 1, 8); | |
3578 | end_frame_id = rounddown(current_frame_id + 895 * 8, 8); | |
3579 | ||
3580 | start_frame &= 0x7ff; | |
3581 | start_frame_id = (start_frame_id >> 3) & 0x7ff; | |
3582 | end_frame_id = (end_frame_id >> 3) & 0x7ff; | |
3583 | ||
3584 | xhci_dbg(xhci, "%s: index %d, reg 0x%x start_frame_id 0x%x, end_frame_id 0x%x, start_frame 0x%x\n", | |
3585 | __func__, index, readl(&xhci->run_regs->microframe_index), | |
3586 | start_frame_id, end_frame_id, start_frame); | |
3587 | ||
3588 | if (start_frame_id < end_frame_id) { | |
3589 | if (start_frame > end_frame_id || | |
3590 | start_frame < start_frame_id) | |
3591 | ret = -EINVAL; | |
3592 | } else if (start_frame_id > end_frame_id) { | |
3593 | if ((start_frame > end_frame_id && | |
3594 | start_frame < start_frame_id)) | |
3595 | ret = -EINVAL; | |
3596 | } else { | |
3597 | ret = -EINVAL; | |
3598 | } | |
3599 | ||
3600 | if (index == 0) { | |
3601 | if (ret == -EINVAL || start_frame == start_frame_id) { | |
3602 | start_frame = start_frame_id + 1; | |
3603 | if (urb->dev->speed == USB_SPEED_LOW || | |
3604 | urb->dev->speed == USB_SPEED_FULL) | |
3605 | urb->start_frame = start_frame; | |
3606 | else | |
3607 | urb->start_frame = start_frame << 3; | |
3608 | ret = 0; | |
3609 | } | |
3610 | } | |
3611 | ||
3612 | if (ret) { | |
3613 | xhci_warn(xhci, "Frame ID %d (reg %d, index %d) beyond range (%d, %d)\n", | |
3614 | start_frame, current_frame_id, index, | |
3615 | start_frame_id, end_frame_id); | |
3616 | xhci_warn(xhci, "Ignore frame ID field, use SIA bit instead\n"); | |
3617 | return ret; | |
3618 | } | |
3619 | ||
3620 | return start_frame; | |
3621 | } | |
3622 | ||
04e51901 AX |
3623 | /* This is for isoc transfer */ |
3624 | static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |
3625 | struct urb *urb, int slot_id, unsigned int ep_index) | |
3626 | { | |
3627 | struct xhci_ring *ep_ring; | |
3628 | struct urb_priv *urb_priv; | |
3629 | struct xhci_td *td; | |
3630 | int num_tds, trbs_per_td; | |
3631 | struct xhci_generic_trb *start_trb; | |
3632 | bool first_trb; | |
3633 | int start_cycle; | |
3634 | u32 field, length_field; | |
3635 | int running_total, trb_buff_len, td_len, td_remain_len, ret; | |
3636 | u64 start_addr, addr; | |
3637 | int i, j; | |
47cbf692 | 3638 | bool more_trbs_coming; |
79b8094f | 3639 | struct xhci_virt_ep *xep; |
09c352ed | 3640 | int frame_id; |
04e51901 | 3641 | |
79b8094f | 3642 | xep = &xhci->devs[slot_id]->eps[ep_index]; |
04e51901 AX |
3643 | ep_ring = xhci->devs[slot_id]->eps[ep_index].ring; |
3644 | ||
3645 | num_tds = urb->number_of_packets; | |
3646 | if (num_tds < 1) { | |
3647 | xhci_dbg(xhci, "Isoc URB with zero packets?\n"); | |
3648 | return -EINVAL; | |
3649 | } | |
04e51901 AX |
3650 | start_addr = (u64) urb->transfer_dma; |
3651 | start_trb = &ep_ring->enqueue->generic; | |
3652 | start_cycle = ep_ring->cycle_state; | |
3653 | ||
522989a2 | 3654 | urb_priv = urb->hcpriv; |
09c352ed | 3655 | /* Queue the TRBs for each TD, even if they are zero-length */ |
04e51901 | 3656 | for (i = 0; i < num_tds; i++) { |
09c352ed MN |
3657 | unsigned int total_pkt_count, max_pkt; |
3658 | unsigned int burst_count, last_burst_pkt_count; | |
3659 | u32 sia_frame_id; | |
04e51901 | 3660 | |
4da6e6f2 | 3661 | first_trb = true; |
04e51901 AX |
3662 | running_total = 0; |
3663 | addr = start_addr + urb->iso_frame_desc[i].offset; | |
3664 | td_len = urb->iso_frame_desc[i].length; | |
3665 | td_remain_len = td_len; | |
734d3ddd | 3666 | max_pkt = usb_endpoint_maxp(&urb->ep->desc); |
09c352ed MN |
3667 | total_pkt_count = DIV_ROUND_UP(td_len, max_pkt); |
3668 | ||
48df4a6f | 3669 | /* A zero-length transfer still involves at least one packet. */ |
09c352ed MN |
3670 | if (total_pkt_count == 0) |
3671 | total_pkt_count++; | |
3672 | burst_count = xhci_get_burst_count(xhci, urb, total_pkt_count); | |
3673 | last_burst_pkt_count = xhci_get_last_burst_packet_count(xhci, | |
3674 | urb, total_pkt_count); | |
04e51901 | 3675 | |
d2510342 | 3676 | trbs_per_td = count_isoc_trbs_needed(urb, i); |
04e51901 AX |
3677 | |
3678 | ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index, | |
3b72fca0 | 3679 | urb->stream_id, trbs_per_td, urb, i, mem_flags); |
522989a2 SS |
3680 | if (ret < 0) { |
3681 | if (i == 0) | |
3682 | return ret; | |
3683 | goto cleanup; | |
3684 | } | |
7e64b037 | 3685 | td = &urb_priv->td[i]; |
09c352ed MN |
3686 | |
3687 | /* use SIA as default, if frame id is used overwrite it */ | |
3688 | sia_frame_id = TRB_SIA; | |
3689 | if (!(urb->transfer_flags & URB_ISO_ASAP) && | |
3690 | HCC_CFC(xhci->hcc_params)) { | |
3691 | frame_id = xhci_get_isoc_frame_id(xhci, urb, i); | |
3692 | if (frame_id >= 0) | |
3693 | sia_frame_id = TRB_FRAME_ID(frame_id); | |
3694 | } | |
3695 | /* | |
3696 | * Set isoc specific data for the first TRB in a TD. | |
3697 | * Prevent HW from getting the TRBs by keeping the cycle state | |
3698 | * inverted in the first TDs isoc TRB. | |
3699 | */ | |
2f6d3b65 | 3700 | field = TRB_TYPE(TRB_ISOC) | |
09c352ed MN |
3701 | TRB_TLBPC(last_burst_pkt_count) | |
3702 | sia_frame_id | | |
3703 | (i ? ep_ring->cycle_state : !start_cycle); | |
3704 | ||
2f6d3b65 MN |
3705 | /* xhci 1.1 with ETE uses TD_Size field for TBC, old is Rsvdz */ |
3706 | if (!xep->use_extended_tbc) | |
3707 | field |= TRB_TBC(burst_count); | |
3708 | ||
09c352ed | 3709 | /* fill the rest of the TRB fields, and remaining normal TRBs */ |
04e51901 AX |
3710 | for (j = 0; j < trbs_per_td; j++) { |
3711 | u32 remainder = 0; | |
09c352ed MN |
3712 | |
3713 | /* only first TRB is isoc, overwrite otherwise */ | |
3714 | if (!first_trb) | |
3715 | field = TRB_TYPE(TRB_NORMAL) | | |
3716 | ep_ring->cycle_state; | |
04e51901 | 3717 | |
af8b9e63 SS |
3718 | /* Only set interrupt on short packet for IN EPs */ |
3719 | if (usb_urb_dir_in(urb)) | |
3720 | field |= TRB_ISP; | |
3721 | ||
09c352ed | 3722 | /* Set the chain bit for all except the last TRB */ |
04e51901 | 3723 | if (j < trbs_per_td - 1) { |
47cbf692 | 3724 | more_trbs_coming = true; |
09c352ed | 3725 | field |= TRB_CHAIN; |
04e51901 | 3726 | } else { |
09c352ed | 3727 | more_trbs_coming = false; |
04e51901 AX |
3728 | td->last_trb = ep_ring->enqueue; |
3729 | field |= TRB_IOC; | |
09c352ed MN |
3730 | /* set BEI, except for the last TD */ |
3731 | if (xhci->hci_version >= 0x100 && | |
3732 | !(xhci->quirks & XHCI_AVOID_BEI) && | |
3733 | i < num_tds - 1) | |
3734 | field |= TRB_BEI; | |
04e51901 | 3735 | } |
04e51901 | 3736 | /* Calculate TRB length */ |
d2510342 | 3737 | trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr); |
04e51901 AX |
3738 | if (trb_buff_len > td_remain_len) |
3739 | trb_buff_len = td_remain_len; | |
3740 | ||
4da6e6f2 | 3741 | /* Set the TRB length, TD size, & interrupter fields. */ |
c840d6ce MN |
3742 | remainder = xhci_td_remainder(xhci, running_total, |
3743 | trb_buff_len, td_len, | |
124c3937 | 3744 | urb, more_trbs_coming); |
c840d6ce | 3745 | |
04e51901 | 3746 | length_field = TRB_LEN(trb_buff_len) | |
04e51901 | 3747 | TRB_INTR_TARGET(0); |
4da6e6f2 | 3748 | |
2f6d3b65 MN |
3749 | /* xhci 1.1 with ETE uses TD Size field for TBC */ |
3750 | if (first_trb && xep->use_extended_tbc) | |
3751 | length_field |= TRB_TD_SIZE_TBC(burst_count); | |
3752 | else | |
3753 | length_field |= TRB_TD_SIZE(remainder); | |
3754 | first_trb = false; | |
3755 | ||
3b72fca0 | 3756 | queue_trb(xhci, ep_ring, more_trbs_coming, |
04e51901 AX |
3757 | lower_32_bits(addr), |
3758 | upper_32_bits(addr), | |
3759 | length_field, | |
af8b9e63 | 3760 | field); |
04e51901 AX |
3761 | running_total += trb_buff_len; |
3762 | ||
3763 | addr += trb_buff_len; | |
3764 | td_remain_len -= trb_buff_len; | |
3765 | } | |
3766 | ||
3767 | /* Check TD length */ | |
3768 | if (running_total != td_len) { | |
3769 | xhci_err(xhci, "ISOC TD length unmatch\n"); | |
cf840551 AX |
3770 | ret = -EINVAL; |
3771 | goto cleanup; | |
04e51901 AX |
3772 | } |
3773 | } | |
3774 | ||
79b8094f LB |
3775 | /* store the next frame id */ |
3776 | if (HCC_CFC(xhci->hcc_params)) | |
3777 | xep->next_frame_id = urb->start_frame + num_tds * urb->interval; | |
3778 | ||
c41136b0 AX |
3779 | if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) { |
3780 | if (xhci->quirks & XHCI_AMD_PLL_FIX) | |
3781 | usb_amd_quirk_pll_disable(); | |
3782 | } | |
3783 | xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++; | |
3784 | ||
e1eab2e0 AX |
3785 | giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, |
3786 | start_cycle, start_trb); | |
04e51901 | 3787 | return 0; |
522989a2 SS |
3788 | cleanup: |
3789 | /* Clean up a partially enqueued isoc transfer. */ | |
3790 | ||
3791 | for (i--; i >= 0; i--) | |
7e64b037 | 3792 | list_del_init(&urb_priv->td[i].td_list); |
522989a2 SS |
3793 | |
3794 | /* Use the first TD as a temporary variable to turn the TDs we've queued | |
3795 | * into No-ops with a software-owned cycle bit. That way the hardware | |
3796 | * won't accidentally start executing bogus TDs when we partially | |
3797 | * overwrite them. td->first_trb and td->start_seg are already set. | |
3798 | */ | |
7e64b037 | 3799 | urb_priv->td[0].last_trb = ep_ring->enqueue; |
522989a2 | 3800 | /* Every TRB except the first & last will have its cycle bit flipped. */ |
7e64b037 | 3801 | td_to_noop(xhci, ep_ring, &urb_priv->td[0], true); |
522989a2 SS |
3802 | |
3803 | /* Reset the ring enqueue back to the first TRB and its cycle bit. */ | |
7e64b037 MN |
3804 | ep_ring->enqueue = urb_priv->td[0].first_trb; |
3805 | ep_ring->enq_seg = urb_priv->td[0].start_seg; | |
522989a2 | 3806 | ep_ring->cycle_state = start_cycle; |
b008df60 | 3807 | ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp; |
522989a2 SS |
3808 | usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb); |
3809 | return ret; | |
04e51901 AX |
3810 | } |
3811 | ||
3812 | /* | |
3813 | * Check transfer ring to guarantee there is enough room for the urb. | |
3814 | * Update ISO URB start_frame and interval. | |
79b8094f LB |
3815 | * Update interval as xhci_queue_intr_tx does. Use xhci frame_index to |
3816 | * update urb->start_frame if URB_ISO_ASAP is set in transfer_flags or | |
3817 | * Contiguous Frame ID is not supported by HC. | |
04e51901 AX |
3818 | */ |
3819 | int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags, | |
3820 | struct urb *urb, int slot_id, unsigned int ep_index) | |
3821 | { | |
3822 | struct xhci_virt_device *xdev; | |
3823 | struct xhci_ring *ep_ring; | |
3824 | struct xhci_ep_ctx *ep_ctx; | |
3825 | int start_frame; | |
04e51901 AX |
3826 | int num_tds, num_trbs, i; |
3827 | int ret; | |
79b8094f LB |
3828 | struct xhci_virt_ep *xep; |
3829 | int ist; | |
04e51901 AX |
3830 | |
3831 | xdev = xhci->devs[slot_id]; | |
79b8094f | 3832 | xep = &xhci->devs[slot_id]->eps[ep_index]; |
04e51901 AX |
3833 | ep_ring = xdev->eps[ep_index].ring; |
3834 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); | |
3835 | ||
3836 | num_trbs = 0; | |
3837 | num_tds = urb->number_of_packets; | |
3838 | for (i = 0; i < num_tds; i++) | |
d2510342 | 3839 | num_trbs += count_isoc_trbs_needed(urb, i); |
04e51901 AX |
3840 | |
3841 | /* Check the ring to guarantee there is enough room for the whole urb. | |
3842 | * Do not insert any td of the urb to the ring if the check failed. | |
3843 | */ | |
5071e6b2 | 3844 | ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx), |
3b72fca0 | 3845 | num_trbs, mem_flags); |
04e51901 AX |
3846 | if (ret) |
3847 | return ret; | |
3848 | ||
79b8094f LB |
3849 | /* |
3850 | * Check interval value. This should be done before we start to | |
3851 | * calculate the start frame value. | |
3852 | */ | |
78140156 | 3853 | check_interval(xhci, urb, ep_ctx); |
79b8094f LB |
3854 | |
3855 | /* Calculate the start frame and put it in urb->start_frame. */ | |
42df7215 | 3856 | if (HCC_CFC(xhci->hcc_params) && !list_empty(&ep_ring->td_list)) { |
5071e6b2 | 3857 | if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_RUNNING) { |
42df7215 LB |
3858 | urb->start_frame = xep->next_frame_id; |
3859 | goto skip_start_over; | |
3860 | } | |
79b8094f LB |
3861 | } |
3862 | ||
3863 | start_frame = readl(&xhci->run_regs->microframe_index); | |
3864 | start_frame &= 0x3fff; | |
3865 | /* | |
3866 | * Round up to the next frame and consider the time before trb really | |
3867 | * gets scheduled by hardare. | |
3868 | */ | |
3869 | ist = HCS_IST(xhci->hcs_params2) & 0x7; | |
3870 | if (HCS_IST(xhci->hcs_params2) & (1 << 3)) | |
3871 | ist <<= 3; | |
3872 | start_frame += ist + XHCI_CFC_DELAY; | |
3873 | start_frame = roundup(start_frame, 8); | |
3874 | ||
3875 | /* | |
3876 | * Round up to the next ESIT (Endpoint Service Interval Time) if ESIT | |
3877 | * is greate than 8 microframes. | |
3878 | */ | |
3879 | if (urb->dev->speed == USB_SPEED_LOW || | |
3880 | urb->dev->speed == USB_SPEED_FULL) { | |
3881 | start_frame = roundup(start_frame, urb->interval << 3); | |
3882 | urb->start_frame = start_frame >> 3; | |
3883 | } else { | |
3884 | start_frame = roundup(start_frame, urb->interval); | |
3885 | urb->start_frame = start_frame; | |
3886 | } | |
3887 | ||
3888 | skip_start_over: | |
b008df60 AX |
3889 | ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free; |
3890 | ||
3fc8206d | 3891 | return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index); |
04e51901 AX |
3892 | } |
3893 | ||
d0e96f5a SS |
3894 | /**** Command Ring Operations ****/ |
3895 | ||
913a8a34 SS |
3896 | /* Generic function for queueing a command TRB on the command ring. |
3897 | * Check to make sure there's room on the command ring for one command TRB. | |
3898 | * Also check that there's room reserved for commands that must not fail. | |
3899 | * If this is a command that must not fail, meaning command_must_succeed = TRUE, | |
3900 | * then only check for the number of reserved spots. | |
3901 | * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB | |
3902 | * because the command event handler may want to resubmit a failed command. | |
3903 | */ | |
ddba5cd0 MN |
3904 | static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd, |
3905 | u32 field1, u32 field2, | |
3906 | u32 field3, u32 field4, bool command_must_succeed) | |
7f84eef0 | 3907 | { |
913a8a34 | 3908 | int reserved_trbs = xhci->cmd_ring_reserved_trbs; |
d1dc908a | 3909 | int ret; |
ad6b1d91 | 3910 | |
98d74f9c MN |
3911 | if ((xhci->xhc_state & XHCI_STATE_DYING) || |
3912 | (xhci->xhc_state & XHCI_STATE_HALTED)) { | |
ad6b1d91 | 3913 | xhci_dbg(xhci, "xHCI dying or halted, can't queue_command\n"); |
c9aa1a2d | 3914 | return -ESHUTDOWN; |
ad6b1d91 | 3915 | } |
d1dc908a | 3916 | |
913a8a34 SS |
3917 | if (!command_must_succeed) |
3918 | reserved_trbs++; | |
3919 | ||
d1dc908a | 3920 | ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING, |
3b72fca0 | 3921 | reserved_trbs, GFP_ATOMIC); |
d1dc908a SS |
3922 | if (ret < 0) { |
3923 | xhci_err(xhci, "ERR: No room for command on command ring\n"); | |
913a8a34 SS |
3924 | if (command_must_succeed) |
3925 | xhci_err(xhci, "ERR: Reserved TRB counting for " | |
3926 | "unfailable commands failed.\n"); | |
d1dc908a | 3927 | return ret; |
7f84eef0 | 3928 | } |
c9aa1a2d MN |
3929 | |
3930 | cmd->command_trb = xhci->cmd_ring->enqueue; | |
ddba5cd0 | 3931 | |
c311e391 | 3932 | /* if there are no other commands queued we start the timeout timer */ |
daa47f21 | 3933 | if (list_empty(&xhci->cmd_list)) { |
c311e391 | 3934 | xhci->current_cmd = cmd; |
cb4d5ce5 | 3935 | xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT); |
c311e391 MN |
3936 | } |
3937 | ||
daa47f21 LB |
3938 | list_add_tail(&cmd->cmd_list, &xhci->cmd_list); |
3939 | ||
3b72fca0 AX |
3940 | queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3, |
3941 | field4 | xhci->cmd_ring->cycle_state); | |
7f84eef0 SS |
3942 | return 0; |
3943 | } | |
3944 | ||
3ffbba95 | 3945 | /* Queue a slot enable or disable request on the command ring */ |
ddba5cd0 MN |
3946 | int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd, |
3947 | u32 trb_type, u32 slot_id) | |
3ffbba95 | 3948 | { |
ddba5cd0 | 3949 | return queue_command(xhci, cmd, 0, 0, 0, |
913a8a34 | 3950 | TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false); |
3ffbba95 SS |
3951 | } |
3952 | ||
3953 | /* Queue an address device command TRB */ | |
ddba5cd0 MN |
3954 | int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd, |
3955 | dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev setup) | |
3ffbba95 | 3956 | { |
ddba5cd0 | 3957 | return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr), |
8e595a5d | 3958 | upper_32_bits(in_ctx_ptr), 0, |
48fc7dbd DW |
3959 | TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id) |
3960 | | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false); | |
2a8f82c4 SS |
3961 | } |
3962 | ||
ddba5cd0 | 3963 | int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd, |
0238634d SS |
3964 | u32 field1, u32 field2, u32 field3, u32 field4) |
3965 | { | |
ddba5cd0 | 3966 | return queue_command(xhci, cmd, field1, field2, field3, field4, false); |
0238634d SS |
3967 | } |
3968 | ||
2a8f82c4 | 3969 | /* Queue a reset device command TRB */ |
ddba5cd0 MN |
3970 | int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd, |
3971 | u32 slot_id) | |
2a8f82c4 | 3972 | { |
ddba5cd0 | 3973 | return queue_command(xhci, cmd, 0, 0, 0, |
2a8f82c4 | 3974 | TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id), |
913a8a34 | 3975 | false); |
3ffbba95 | 3976 | } |
f94e0186 SS |
3977 | |
3978 | /* Queue a configure endpoint command TRB */ | |
ddba5cd0 MN |
3979 | int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, |
3980 | struct xhci_command *cmd, dma_addr_t in_ctx_ptr, | |
913a8a34 | 3981 | u32 slot_id, bool command_must_succeed) |
f94e0186 | 3982 | { |
ddba5cd0 | 3983 | return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr), |
8e595a5d | 3984 | upper_32_bits(in_ctx_ptr), 0, |
913a8a34 SS |
3985 | TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id), |
3986 | command_must_succeed); | |
f94e0186 | 3987 | } |
ae636747 | 3988 | |
f2217e8e | 3989 | /* Queue an evaluate context command TRB */ |
ddba5cd0 MN |
3990 | int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd, |
3991 | dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed) | |
f2217e8e | 3992 | { |
ddba5cd0 | 3993 | return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr), |
f2217e8e | 3994 | upper_32_bits(in_ctx_ptr), 0, |
913a8a34 | 3995 | TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id), |
4b266541 | 3996 | command_must_succeed); |
f2217e8e SS |
3997 | } |
3998 | ||
be88fe4f AX |
3999 | /* |
4000 | * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop | |
4001 | * activity on an endpoint that is about to be suspended. | |
4002 | */ | |
ddba5cd0 MN |
4003 | int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd, |
4004 | int slot_id, unsigned int ep_index, int suspend) | |
ae636747 SS |
4005 | { |
4006 | u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); | |
4007 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); | |
4008 | u32 type = TRB_TYPE(TRB_STOP_RING); | |
be88fe4f | 4009 | u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend); |
ae636747 | 4010 | |
ddba5cd0 | 4011 | return queue_command(xhci, cmd, 0, 0, 0, |
be88fe4f | 4012 | trb_slot_id | trb_ep_index | type | trb_suspend, false); |
ae636747 SS |
4013 | } |
4014 | ||
d3a43e66 HG |
4015 | /* Set Transfer Ring Dequeue Pointer command */ |
4016 | void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci, | |
4017 | unsigned int slot_id, unsigned int ep_index, | |
d3a43e66 | 4018 | struct xhci_dequeue_state *deq_state) |
ae636747 SS |
4019 | { |
4020 | dma_addr_t addr; | |
4021 | u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); | |
4022 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); | |
8790736d | 4023 | u32 trb_stream_id = STREAM_ID_FOR_TRB(deq_state->stream_id); |
95241dbd | 4024 | u32 trb_sct = 0; |
ae636747 | 4025 | u32 type = TRB_TYPE(TRB_SET_DEQ); |
bf161e85 | 4026 | struct xhci_virt_ep *ep; |
1e3452e3 HG |
4027 | struct xhci_command *cmd; |
4028 | int ret; | |
ae636747 | 4029 | |
d3a43e66 HG |
4030 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
4031 | "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), new deq ptr = %p (0x%llx dma), new cycle = %u", | |
4032 | deq_state->new_deq_seg, | |
4033 | (unsigned long long)deq_state->new_deq_seg->dma, | |
4034 | deq_state->new_deq_ptr, | |
4035 | (unsigned long long)xhci_trb_virt_to_dma( | |
4036 | deq_state->new_deq_seg, deq_state->new_deq_ptr), | |
4037 | deq_state->new_cycle_state); | |
4038 | ||
4039 | addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg, | |
4040 | deq_state->new_deq_ptr); | |
c92bcfa7 | 4041 | if (addr == 0) { |
ae636747 | 4042 | xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n"); |
700e2052 | 4043 | xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n", |
d3a43e66 HG |
4044 | deq_state->new_deq_seg, deq_state->new_deq_ptr); |
4045 | return; | |
c92bcfa7 | 4046 | } |
bf161e85 SS |
4047 | ep = &xhci->devs[slot_id]->eps[ep_index]; |
4048 | if ((ep->ep_state & SET_DEQ_PENDING)) { | |
4049 | xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n"); | |
4050 | xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n"); | |
d3a43e66 | 4051 | return; |
bf161e85 | 4052 | } |
1e3452e3 HG |
4053 | |
4054 | /* This function gets called from contexts where it cannot sleep */ | |
103afda0 | 4055 | cmd = xhci_alloc_command(xhci, false, GFP_ATOMIC); |
74e0b564 | 4056 | if (!cmd) |
d3a43e66 | 4057 | return; |
1e3452e3 | 4058 | |
d3a43e66 HG |
4059 | ep->queued_deq_seg = deq_state->new_deq_seg; |
4060 | ep->queued_deq_ptr = deq_state->new_deq_ptr; | |
8790736d | 4061 | if (deq_state->stream_id) |
95241dbd | 4062 | trb_sct = SCT_FOR_TRB(SCT_PRI_TR); |
1e3452e3 | 4063 | ret = queue_command(xhci, cmd, |
d3a43e66 HG |
4064 | lower_32_bits(addr) | trb_sct | deq_state->new_cycle_state, |
4065 | upper_32_bits(addr), trb_stream_id, | |
4066 | trb_slot_id | trb_ep_index | type, false); | |
1e3452e3 HG |
4067 | if (ret < 0) { |
4068 | xhci_free_command(xhci, cmd); | |
d3a43e66 | 4069 | return; |
1e3452e3 HG |
4070 | } |
4071 | ||
d3a43e66 HG |
4072 | /* Stop the TD queueing code from ringing the doorbell until |
4073 | * this command completes. The HC won't set the dequeue pointer | |
4074 | * if the ring is running, and ringing the doorbell starts the | |
4075 | * ring running. | |
4076 | */ | |
4077 | ep->ep_state |= SET_DEQ_PENDING; | |
ae636747 | 4078 | } |
a1587d97 | 4079 | |
ddba5cd0 | 4080 | int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd, |
21749148 MN |
4081 | int slot_id, unsigned int ep_index, |
4082 | enum xhci_ep_reset_type reset_type) | |
a1587d97 SS |
4083 | { |
4084 | u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); | |
4085 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); | |
4086 | u32 type = TRB_TYPE(TRB_RESET_EP); | |
4087 | ||
21749148 MN |
4088 | if (reset_type == EP_SOFT_RESET) |
4089 | type |= TRB_TSP; | |
4090 | ||
ddba5cd0 MN |
4091 | return queue_command(xhci, cmd, 0, 0, 0, |
4092 | trb_slot_id | trb_ep_index | type, false); | |
a1587d97 | 4093 | } |